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Sample records for gate oxide reliability

  1. Impact of boron penetration on gate oxide reliability and device performance in a dual-gate oxide process

    NASA Astrophysics Data System (ADS)

    Zhang, Yunqiang; Gan, Chock H.; Li, Xi; Lee, James; Vigar, David; Sundaresan, Ravi

    2000-10-01

    The effect of boron penetration on device performance and gate oxide reliability of P+ polysilicon gate MOSFET of a dual oxide process with salicide block module was investigated. To get stable non-salicided poly sheet resistance, a capping oxide is required before source/drain RTA anneal. It is found that the transistor performance and gate oxide reliability were degraded with the capping oxide. The optimization scheme by replacing BF2 with Boron for P+ implant is demonstrated.

  2. Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Sahu, P. K.; Singh, D.; Artola, L.; Mohapatra, S. K.

    2015-09-01

    A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon-germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

  3. Fundamental reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition

    SciTech Connect

    Yamada, Hiroshi

    2008-01-15

    The reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition (RIBD) with in situ pyrolytic-gas passivation (PGP) using N{sub 2}O and NF{sub 3} was investigated. RIBD uses low-energy-controlled reactive, ionized species and potentializes low-temperature film growth. Although the oxide films were grown at a low temperature of 150 deg. C, their fundamental indices of reliability, such as the time-dependent dielectric breakdown lifetime and interface state density, were almost equivalent to those of oxide films grown at 850 deg. C using a furnace. This is probably due to localized interfacial N and F atoms. The number density of interfacial N atoms was about seven times larger than that for the furnace-grown oxide films, and this is a key factor for improving the reliability through the compensation of residual inconsistent-state bonding sites.

  4. Improvement in reliability of amorphous indium-gallium-zinc oxide thin-film transistors with Teflon/SiO2 bilayer passivation under gate bias stress

    NASA Astrophysics Data System (ADS)

    Fan, Ching-Lin; Tseng, Fan-Ping; Li, Bo-Jyun; Lin, Yu-Zuo; Wang, Shea-Jue; Lee, Win-Der; Huang, Bohr-Ran

    2016-02-01

    The reliability of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with Teflon/SiO2 bilayer passivation prepared under positive and negative gate bias stresses (PGBS and NGBS, respectively) was investigated. Heavier electrical degradation was observed under PGBS than under NGBS, indicating that the environmental effects under PGBS are more evident than those under NGBS. The device with bilayer passivation under PGBS shows two-step degradation. The positive threshold voltage shifts during the initial stressing period (before 500 s), owing to the charges trapped in the gate insulator or at the gate insulator/a-IGZO active layer interface. The negative threshold voltage shift accompanies the increase in subthreshold swing (SS) for the continuous stressing period (after 500 s) owing to H2O molecules from ambience diffused within the a-IGZO TFTs. It is believed that Teflon/SiO2 bilayer passivation can effectively improve the reliability of the a-IGZO TFTs without passivation even though the devices are stressed under gate bias.

  5. Reliability assessment of germanium gate stacks with promising initial characteristics

    NASA Astrophysics Data System (ADS)

    Lu, Cimang; Lee, Choong Hyun; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2015-02-01

    This work reports on the reliability assessment of germanium (Ge) gate stacks with promising initial electrical properties, with focus on trap generation under a constant electric stress field (Estress). Initial Ge gate stack properties do not necessarily mean highly robust reliability when it is considered that traps are newly generated under high Estress. A small amount of yttrium- or scandium oxide-doped GeO2 (Y-GeO2 or Sc-GeO2, respectively) significantly reduces trap generation in Ge gate stacks without deterioration of the interface. This is explained by the increase in the average coordination number (Nav) of the modified GeO2 network that results from the doping.

  6. Impact strain engineering on gate stack quality and reliability

    NASA Astrophysics Data System (ADS)

    Claeys, C.; Simoen, E.; Put, S.; Giusi, G.; Crupi, F.

    2008-08-01

    Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated.

  7. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  8. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    NASA Astrophysics Data System (ADS)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  9. Physical mechanism of progressive breakdown in gate oxides

    NASA Astrophysics Data System (ADS)

    Palumbo, Felix; Lombardo, Salvatore; Eizenberg, Moshe

    2014-06-01

    The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric.

  10. Breakdown and defect generation in ultrathin gate oxide

    NASA Astrophysics Data System (ADS)

    Depas, M.; Vermeire, B.; Heyns, M. M.

    1996-07-01

    In this work the dielectric reliability of thermally grown ultrathin 3 nm SiO2 layers in poly-Si/SiO2/Si structures is examined. This is compared with a study of the defect generation in the 3 nm gate oxide during tunnel injection of electrons. In these ultrathin SiO2 layers, direct tunneling of electrons becomes very important. An increase of the direct tunnel and Fowler-Nordheim tunnel current during high-field stressing was observed and is explained by the creation of a positive charge in the oxide associated with slow interface traps. It is demonstrated that a higher current instability corresponds with a lower charge to breakdown value (QBD) of the oxide. From these results we conclude that the creation of slow interface traps is an important precursor effect for the 3 nm gate oxide breakdown.

  11. Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

    SciTech Connect

    Park, Hong Bae; Ju, Byongsun; Kang, Chang Yong; Park, Chanro; Park, Chang Seo; Lee, Byoung Hun; Kim, Tea Wan; Kim, Beom Seok; Choi, Rino

    2009-01-26

    The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor I{sub on}-I{sub off} characteristics and reduces negative-bias temperature instability.

  12. Deuterium-incorporated gate oxide of MOS devices fabricated by using deuterium ion implantation

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Sung; Lear, Kevin L.

    2012-04-01

    In the aspect of metal-oxide-semiconductor (MOS) device reliability, deuterium-incorporated gate oxide could be utilized to suppress the wear-out that is combined with oxide trap generation. An alternative deuterium process for the passivation of oxide traps or defects in the gate oxide of MOS devices has been suggested in this study. The deuterium ion is delivered to the location where the gate oxide resides by using an implantation process and subsequent N2 annealing process at the back-end of metallization process. A conventional MOS field-effect transistor (MOSFET) with a 3-nm-thick gate oxide and poly-to-ploy capacitor sandwiched with 20-nm-thick SiO2 were fabricated in order to demonstrate the deuterium effect in our process. An optimum condition of ion implantation was necessary to account for the topography of the overlaying layers in the device structure and to minimize the physical damage due to the energy of the implanted ion. Device parameter variations, the gate leakage current, and the dielectric breakdown phenomenon were investigated in the deuterium-ion-implanted devices. We found the isotope effect between hydrogen- and deuterium-implanted devices and an improved electrical reliability in the deuterated gate oxide. This implies that deuterium bonds are generated effectively at the Si/SiO2 interface and in the SiO2 bulk.

  13. Gate-Tunable Conducting Oxide Metasurfaces.

    PubMed

    Huang, Yao-Wei; Lee, Ho Wai Howard; Sokhoyan, Ruzan; Pala, Ragip A; Thyagarajan, Krishnan; Han, Seunghoon; Tsai, Din Ping; Atwater, Harry A

    2016-09-14

    Metasurfaces composed of planar arrays of subwavelength artificial structures show promise for extraordinary light manipulation. They have yielded novel ultrathin optical components such as flat lenses, wave plates, holographic surfaces, and orbital angular momentum manipulation and detection over a broad range of the electromagnetic spectrum. However, the optical properties of metasurfaces developed to date do not allow for versatile tunability of reflected or transmitted wave amplitude and phase after their fabrication, thus limiting their use in a wide range of applications. Here, we experimentally demonstrate a gate-tunable metasurface that enables dynamic electrical control of the phase and amplitude of the plane wave reflected from the metasurface. Tunability arises from field-effect modulation of the complex refractive index of conducting oxide layers incorporated into metasurface antenna elements which are configured in reflectarray geometry. We measure a phase shift of 180° and ∼30% change in the reflectance by applying 2.5 V gate bias. Additionally, we demonstrate modulation at frequencies exceeding 10 MHz and electrical switching of ±1 order diffracted beams by electrical control over subgroups of metasurface elements, a basic requirement for electrically tunable beam-steering phased array metasurfaces. In principle, electrically gated phase and amplitude control allows for electrical addressability of individual metasurface elements and opens the path to applications in ultrathin optical components for imaging and sensing technologies, such as reconfigurable beam steering devices, dynamic holograms, tunable ultrathin lenses, nanoprojectors, and nanoscale spatial light modulators.

  14. Gate-Tunable Conducting Oxide Metasurfaces.

    PubMed

    Huang, Yao-Wei; Lee, Ho Wai Howard; Sokhoyan, Ruzan; Pala, Ragip A; Thyagarajan, Krishnan; Han, Seunghoon; Tsai, Din Ping; Atwater, Harry A

    2016-09-14

    Metasurfaces composed of planar arrays of subwavelength artificial structures show promise for extraordinary light manipulation. They have yielded novel ultrathin optical components such as flat lenses, wave plates, holographic surfaces, and orbital angular momentum manipulation and detection over a broad range of the electromagnetic spectrum. However, the optical properties of metasurfaces developed to date do not allow for versatile tunability of reflected or transmitted wave amplitude and phase after their fabrication, thus limiting their use in a wide range of applications. Here, we experimentally demonstrate a gate-tunable metasurface that enables dynamic electrical control of the phase and amplitude of the plane wave reflected from the metasurface. Tunability arises from field-effect modulation of the complex refractive index of conducting oxide layers incorporated into metasurface antenna elements which are configured in reflectarray geometry. We measure a phase shift of 180° and ∼30% change in the reflectance by applying 2.5 V gate bias. Additionally, we demonstrate modulation at frequencies exceeding 10 MHz and electrical switching of ±1 order diffracted beams by electrical control over subgroups of metasurface elements, a basic requirement for electrically tunable beam-steering phased array metasurfaces. In principle, electrically gated phase and amplitude control allows for electrical addressability of individual metasurface elements and opens the path to applications in ultrathin optical components for imaging and sensing technologies, such as reconfigurable beam steering devices, dynamic holograms, tunable ultrathin lenses, nanoprojectors, and nanoscale spatial light modulators. PMID:27564012

  15. Gate oxide damage reduction using a protective dielectric layer

    NASA Astrophysics Data System (ADS)

    Gabriel, Calvin T.; Weling, Milind G.

    1994-08-01

    Gate oxide damage from charge entering through the top surface of the gate electrode during plasma ashing, ion implantation, and LDD spacer oxide etching was measured using antenna structures. Significant charge damage to the 9.0 nm-thick gate oxide was detected for each of these processes. The damage was reduced by using a protective dielectric layer, in this case a thermally deposited TEOS oxide, over the polycide gate electrode before gate definition. The dielectric appears to block charge penetration into the antenna. Damage can be reduced further by increasing the thickness of the dielectric layer; for a sufficiently thick layer (about 150 nm), charge entering through the top surface of the antenna was effectively eliminated.

  16. Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

    NASA Astrophysics Data System (ADS)

    Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

    2016-06-01

    This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

  17. Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

    PubMed

    Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

    2016-08-24

    Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing. PMID:27471861

  18. Effect of gate oxide thickness on the radiation hardness of silicon-gate CMOS

    SciTech Connect

    Nordstrom, T.V.; Gibbon, C.F.

    1981-01-01

    Significant improvements have been made in the radiation hardness of silicon-gate CMOS by reducing the gate oxide thickness. The device studied is an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells. Devices with gate oxide thicknesses of 400, 570 (standard), and 700 A were fabricated. Irradiations were done at a dose rate of 2 x 10/sup 6/ rads (Si) per hour. N- and P-channel maximum threshold shifts were reduced by 0.3 and 1.2 volts, respectively, for the thinnest oxide. Approximately, a linear relationship is found for threshold shift versus thickness. The functional radiation hardness of the full integrated circuit was also measured.

  19. NO2 sensitive Au gate metal-oxide-semiconductor capacitors

    NASA Astrophysics Data System (ADS)

    Filippini, D.; Aragón, R.; Weimar, U.

    2001-08-01

    Au gate metal-oxide-semiconductor capacitors are sensitive to NO2 in air up to 200 ppm, depending on operating temperature (100 °C to 200 °C), gate thickness (50 to 900 nm), and morphology. In the absence of catalytic properties or lattice diffusivity, a model invoking molecular surface adsorption and grain boundary diffusion is proposed, which quantitatively describes the transient and steady state response of the devices. Sensitivity is given by the arrival of the diffusing species to the gate-dielectric interface, where capacitive coupling of the adsorbed molecules induces work function changes, which shift the flat band voltage positively, opposite that observed for H2 with Pd gates, consistently with an oxidizing, rather than reducing, character.

  20. Oxidative Modulation of Voltage-Gated Potassium Channels

    PubMed Central

    Sahoo, Nirakar; Hoshi, Toshinori

    2014-01-01

    Abstract Significance: Voltage-gated K+ channels are a large family of K+-selective ion channel protein complexes that open on membrane depolarization. These K+ channels are expressed in diverse tissues and their function is vital for numerous physiological processes, in particular of neurons and muscle cells. Potentially reversible oxidative regulation of voltage-gated K+ channels by reactive species such as reactive oxygen species (ROS) represents a contributing mechanism of normal cellular plasticity and may play important roles in diverse pathologies including neurodegenerative diseases. Recent Advances: Studies using various protocols of oxidative modification, site-directed mutagenesis, and structural and kinetic modeling provide a broader phenomenology and emerging mechanistic insights. Critical Issues: Physicochemical mechanisms of the functional consequences of oxidative modifications of voltage-gated K+ channels are only beginning to be revealed. In vivo documentation of oxidative modifications of specific amino-acid residues of various voltage-gated K+ channel proteins, including the target specificity issue, is largely absent. Future Directions: High-resolution chemical and proteomic analysis of ion channel proteins with respect to oxidative modification combined with ongoing studies on channel structure and function will provide a better understanding of how the function of voltage-gated K+ channels is tuned by ROS and the corresponding reducing enzymes to meet cellular needs. Antioxid. Redox Signal. 21, 933–952. PMID:24040918

  1. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    NASA Astrophysics Data System (ADS)

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-01

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  2. Transparent conducting oxide induced by liquid electrolyte gating

    PubMed Central

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

    2016-01-01

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ∼1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications. PMID:27647884

  3. Improved gate oxide integrity of strained Si n-channel metal oxide silicon field effect transistors using thin virtual substrates

    NASA Astrophysics Data System (ADS)

    Yan, L.; Olsen, S. H.; Escobedo-Cousin, E.; O'Neill, A. G.

    2008-05-01

    This work presents a detailed study of ultrathin gate oxide integrity in strained Si metal oxide silicon field effect transistors (MOSFETs) fabricated on thin virtual substrates aimed at reducing device self-heating. The gate oxide quality and reliability of the devices are compared to those of simultaneously processed Si control devices and conventional thick virtual substrate devices that have the same Ge content (20%), strained Si channel thickness, and channel strain. The thin virtual substrates offer the same mobility enhancement as the thick virtual substrates (˜100% compared to universal mobility data) and are effective at reducing device self-heating. Up to 90% improvement in gate leakage current is demonstrated for the strained Si n-channel MOSFETs compared to that for the bulk Si controls. The lower leakage arises from the increased electron affinity in tensile strained Si and is significant due to the sizeable strain generated by using wafer-level stressors. The strain-induced leakage reductions also lead to major improvements in stress-induced leakage current (SILC) and oxide reliability. The lower leakage current of the thin and thick virtual substrate devices compares well to theoretical estimates based on the Wentzel-Kramers-Brillouin approximation. Breakdown characteristics also differ considerably between the devices, with the strained Si devices exhibiting a one order of magnitude increase in time to hard breakdown (THBD) compared to the Si control devices following high-field stressing at 17 MV cm-1. The strained Si devices are exempted from soft breakdown. Experimental based analytical leakage modeling has been carried out across the field range for the first time in thin oxides and demonstrates that Poole-Frenkel (PF) emissions followed by Fowler-Nordheim tunneling dominate gate leakage current at low fields in all of the devices. This contrasts to the frequently reported assumption that direct tunneling dominates gate leakage in ultrathin

  4. The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement

    NASA Astrophysics Data System (ADS)

    Hsieh, E. R.; Chung, Steve S.

    2015-12-01

    The evolution of gate-current leakage path has been observed and depicted by RTN signals on metal-oxide-silicon field effect transistor with high-k gate dielectric. An experimental method based on gate-current random telegraph noise (Ig-RTN) technique was developed to observe the formation of gate-leakage path for the device under certain electrical stress, such as Bias Temperature Instability. The results show that the evolution of gate-current path consists of three stages. In the beginning, only direct-tunnelling gate current and discrete traps inducing Ig-RTN are observed; in the middle stage, interaction between traps and the percolation paths presents a multi-level gate-current variation, and finally two different patterns of the hard or soft breakdown path can be identified. These observations provide us a better understanding of the gate-leakage and its impact on the device reliability.

  5. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    NASA Astrophysics Data System (ADS)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  6. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric.

    PubMed

    Fujii, Mami N; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices. PMID:26677773

  7. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    PubMed Central

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

  8. Electron Beam Induced Damage of MOS Gate Oxide

    NASA Astrophysics Data System (ADS)

    Konishi, Morikazu; Kubota, Michitaka; Koike, Kaoru

    1998-03-01

    Threshold voltage (Vth) shift of a metal oxide semiconductor (MOS) system due to electron beam (EB) exposure can be expressed quantitatively as a function of the EB dosage which was derived easily as a solution of a differential equation based on the hole capturing model in the gate oxide. The theoretical model assumes two steps for hole capturing. First is the hole capturing by intrinsic hole traps leading to steep Vth shift with EB dosage at early exposure stages. The second is the hole capturing by newborn hole traps due to the EB injection, leading to a rather slow Vth variation at a higher EB dosage. The model shows good agreement with the experimental result over a wide range of electron beam dosages. Moreover, hole injection efficiency in the gate oxide is found to be higher for the third Aluminum interconnection layer exposure than for the first Al layer, corresponding to higher deposition energy around the gate oxide obtained by the Monte Carlo simulation result.

  9. Evaluation of Gate Oxide Damage Caused by Ionization Magnetron Sputtering

    NASA Astrophysics Data System (ADS)

    Matsunaka, Shigeki; Iyanagi, Katsumi; Fukuhara, Jota; Hayase, Shuzi

    2007-11-01

    An unbalanced magnet (UM) is commonly employed in ionization magnetron sputtering (IMS) in order to increase the ionization rates of sputtering species. In this paper, sputtering using an UM is compared with that using a balanced magnet (BM) during the deposition of Ti thin layers. Ti layers were fabricated on the top of polycrystalline silicon (poly-Si) gate electrodes of antenna metal oxide semiconductor (MOS) capacitors with various thicknesses of gate SiO2 layers ranging from 25 to 80 Å, and the durability of the gate SiO2 layers was monitored by current-voltage (I-V) measurements. It was found that the MOS capacitors with thin SiO2 layers fabricated with the UM were much more damaged than those fabricated with the BM. This characteristic became more marked for thinner SiO2 layers. Its origin was investigated by monitoring the current injected from the plasma to the substrate using a specially designed electrical configuration, and was explained as follows. Electrons are carried toward substrates by curvature drift originating from the diverging magnetic field perpendicular to the substrate. This causes the accumulation of electrons on the gate SiO2 thin layers where the diverging magnetic field is developed at the beginning of discharge, i.e., before the uniform Ti deposition starts to occur. Consequently, the accumulated electrons break the gate SiO2 layer. These results suggest that a new design of magnetic fields for the UM is needed so that the magnetic field does not reach the substrate. It is particularly important to keep the diverging magnetic fields away from the substrates at the beginning of discharge.

  10. Graphene-graphene oxide floating gate transistor memory.

    PubMed

    Jang, Sukjae; Hwang, Euyheon; Lee, Jung Heon; Park, Ho Seok; Cho, Jeong Ho

    2015-01-21

    A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles).

  11. Post-growth process-induced degradation in thin gate oxides

    NASA Astrophysics Data System (ADS)

    Mehta, Rajesh; Bhattacharyya, A. B.; Singh, D. N.

    1991-06-01

    The mechanism of degradation in thin gate oxides due to postoxidation processing steps has been investigated using charge to breakdown QBD as a diagnostic tool. The QBD degradation is also correlated with trap generation rate in thin gate oxide. Controlled annealing experiments show that the gate oxide degradation is not related to the diffusion of phosphorous or other mobile ion impurities from the polysilicon film into the gate oxide. The degradation is caused by stress build up in silicon dioxide film with high-temperature annealing, due to viscous shear flow of the gate oxide at polysilicon/silicon dioxide and silicon dioxide/silicon interfaces. In another experiment, where the thickness of polysilicon was taken as a parameter, it is shown that degradation has a direct correlation with the polysilicon thickness which may be related to the mechanical stress.

  12. Mesostructured HfxAlyO2 Thin Films as Reliable and Robust Gate Dielectrics with Tunable Dielectric Constants for High-Performance Graphene-Based Transistors.

    PubMed

    Lee, Yunseong; Jeon, Woojin; Cho, Yeonchoo; Lee, Min-Hyun; Jeong, Seong-Jun; Park, Jongsun; Park, Seongjun

    2016-07-26

    We introduce a reliable and robust gate dielectric material with tunable dielectric constants based on a mesostructured HfxAlyO2 film. The ultrathin mesostructured HfxAlyO2 film is deposited on graphene via a physisorbed-precursor-assisted atomic layer deposition process and consists of an intermediate state with small crystallized parts in an amorphous matrix. Crystal phase engineering using Al dopant is employed to achieve HfO2 phase transitions, which produce the crystallized part of the mesostructured HfxAlyO2 film. The effects of various Al doping concentrations are examined, and an enhanced dielectric constant of ∼25 is obtained. Further, the leakage current is suppressed (∼10(-8) A/cm(2)) and the dielectric breakdown properties are enhanced (breakdown field: ∼7 MV/cm) by the partially remaining amorphous matrix. We believe that this contribution is theoretically and practically relevant because excellent gate dielectric performance is obtained. In addition, an array of top-gated metal-insulator-graphene field-effect transistors is fabricated on a 6 in. wafer, yielding a capacitance equivalent oxide thickness of less than 1 nm (0.78 nm). This low capacitance equivalent oxide thickness has important implications for the incorporation of graphene into high-performance silicon-based nanoelectronics. PMID:27355098

  13. The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

    NASA Astrophysics Data System (ADS)

    Kaczer, B.; Franco, J.; Weckx, P.; Roussel, Ph. J.; Simicic, M.; Putcha, V.; Bury, E.; Cho, M.; Degraeve, R.; Linten, D.; Groeseneken, G.; Debacker, P.; Parvais, B.; Raghavan, P.; Catthoor, F.; Rzepa, G.; Waltl, M.; Goes, W.; Grasser, T.

    2016-11-01

    As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.

  14. Evaluation of 4H-SiC Thermal Oxide Reliability Using Area-Scaling Method

    NASA Astrophysics Data System (ADS)

    Senzaki, Junji; Shimozato, Atsushi; Okamoto, Mitsuo; Kojima, Kazutoshi; Fukuda, Kenji; Okumura, Hajime; Arai, Kazuo

    2009-08-01

    The reliability of thermal oxides grown on an n-type 4H-SiC(0001) was investigated using an area-scaling method, and the influence of dislocation defects on the time-dependent dielectric breakdown characteristics of thermal oxides was examined. A thermal oxide was grown by dry oxidation at 1200 °C followed by nitrogen post-oxidation annealing. Using the area-scaling method, the time-to-breakdown (tBD) distribution curves of metal-oxide-semiconductor (MOS) capacitors with different gate area sizes were converged to a single one. It was clearly shown that origins of dielectric breakdown are edge breakdown and dislocation-related breakdown for steep and gradual slopes of the area-scaling normalized tBD distribution curve, respectively. In addition, a yield analysis of MOS capacitors quantitatively indicated that both threading screw dislocation and basal plane dislocation are predominant killer defects for the dielectric breakdown of thermal oxides on the 4H-SiC(0001) face.

  15. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    DOE PAGESBeta

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a puremore » electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

  16. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    PubMed Central

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  17. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    NASA Astrophysics Data System (ADS)

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-08-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  18. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films.

    PubMed

    Leng, X; Bollinger, A T; Božović, I

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  19. Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Priyanka; Sahu, P. K.

    2016-01-01

    Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

  20. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications. PMID:25741771

  1. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications.

  2. Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Han, Ru; Li, Cong

    2013-02-01

    In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  3. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    NASA Astrophysics Data System (ADS)

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin

    2016-07-01

    We report the abnormal behavior of the threshold voltage (VTH) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (VTG), while bottom gate bias (VBG) is less effect than VTG. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO2/a-IGZO and also the existence of large amount of In+ under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH- at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of VTG both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  4. SEMICONDUCTOR DEVICES Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

    NASA Astrophysics Data System (ADS)

    Yan, Han; Bin, Zhang; Koubao, Ding; Shifeng, Zhang; Chenggong, Han; Jiaxian, Hu; Dazhong, Zhu

    2010-12-01

    The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS (SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift (NDD) region implant on Ron degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced Ron degradation effectively, which is different from uniform gate oxide NLDMOS (UG-NLDMOS) transistors.

  5. Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides

    NASA Astrophysics Data System (ADS)

    Wu, E.; Suñé, J.; Lai, W.; Nowak, E.; McKenna, J.; Vayshenker, A.; Harmon, D.

    2002-11-01

    In this work, we resolved several seemingly conflicting experimental observations regarding temperature dependence of oxide breakdown in the context of change of voltage acceleration factors with reducing voltages. It is found that voltage acceleration factor is temperature dependent at a fixed voltage while voltage acceleration factors are temperature independent at a fixed TBD. We unequivocally demonstrated that strong temperature dependence of time(charge)-to-breakdown, TBD( QBD), observed on ultra-thin gate oxides (<5 nm) is not a thickness effect as previously suggested. It is a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration at a fixed TBD window. For the first time, time-to-breakdown at low temperature of -50 °C is reported. It is found that Weibull slopes are insensitive to temperature variations using accurate area-scaling method. The stress-induced leakage current (SILC) was used as a measure of defect-generation rate and critical defect density to investigate its correlation with the directly measured breakdown data, QBD( TBD). The comprehensive and statistical measurements of SILC at breakdown as a function of temperature are presented in detail for the first time. Based on these results, we conclude that SILC-based measurements cannot adequately explain the temperature dependence of oxide breakdown. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domains constructed from two important empirical relations based on comprehensive experimental database.

  6. Evaluation of Charge Passed through Gate-Oxide Films Using a Charging Damage Measurement Electrode

    NASA Astrophysics Data System (ADS)

    Watanabe, Seiichi; Sumiya, Masahiro; Tamura, Hitoshi; Yoshioka, Ken; Tokunaga, Takafumi; Mizutani, Tatsumi

    2000-02-01

    A charging damage measurement electrode was used to model device structures. The charge passed through gate-oxide films (Qp) was measured in a cavity-resonator-type electron cyclotron resonance (ECR) plasma etcher for 12-inch wafers and the reduction of charging damage was investigated. Parallel circuits composed of resistors and condensers were modeled after the current-voltage (I-V) characteristics of the gate-oxide film. The electron shading effect was introduced by mounting a Si chip with line and space (L&S)-patterned photoresist on the probe, which corresponded to the gate electrode. The reduction of charging damage using the time modulation (TM) bias was determined by evaluating Qp and the damaged test element group (TEG) wafer. This charging damage measurement electrode is effective for investigating the reduction of charging damage in particular, of the etcher used for 12-inch wafers.

  7. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  8. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors. PMID:26381613

  9. Electrical control of Co/Ni magnetism adjacent to gate oxides with low oxygen ion mobility

    SciTech Connect

    Yan, Y. N.; Zhou, X. J.; Li, F.; Cui, B.; Wang, Y. Y.; Wang, G. Y.; Pan, F.; Song, C.

    2015-09-21

    We investigate the electrical manipulation of Co/Ni magnetization through a combination of ionic liquid and oxide gating, where HfO{sub 2} with a low O{sup 2−} ion mobility is employed. A limited oxidation-reduction process at the metal/HfO{sub 2} interface can be induced by large electric field, which can greatly affect the saturated magnetization and Curie temperature of Co/Ni bilayer. Besides the oxidation/reduction process, first-principles calculations show that the variation of d electrons is also responsible for the magnetization variation. Our work discloses the role of gate oxides with a relatively low O{sup 2−} ion mobility in electrical control of magnetism, and might pave the way for the magneto-ionic memory with low power consumption and high endurance performance.

  10. Fundamental studies of quantum codes and gates for building a reliable quantum computer

    NASA Astrophysics Data System (ADS)

    Siddiqui, Shabnam

    In this dissertation we have studied various methods that have been proposed to overcome the problem of decoherence in a quantum computer. These methods are: (1) Quantum-error correcting codes (QECC's); (2) Decoherence-free subsystem/subspace (DFS); (3) Adiabatic gate operation. In the first two methods, information is encoded in the form of a code that provides protection against certain noise and hence protect the qubit from losing information to the environment. In the third method, the gate operation is performed in such a way that the qubit is made to evolve adiabatically because of which it acquires a phase which is insensitive to the certain form of noise. Thus, because of the insensivity of the phase to the noise, the qubit is prevented from losing information to the environment. All these methods have limitations and in this work we studied these limitations. This work is divided into two parts. In the first part, we studied the performance of a 3-qubit QECC in the presence of quantized partially correlated noise, as well as 3 and 4-qubit DFS in the presence of partially correlated noise. We derived the relationship between the fidelity of the code, the initial state, coherence length of the noise and the spatial distance between the qubits. For the case of, 3-qubit QECC we found that the quantum nature of the noise enhances the infidelity of the code. For the case of, 3 and 4-qubit DFS we found that under certain conditions 3-qubit DFS code is a better code over 4-qubit code. Nonetheless, these studies provide us insights of the influence of the environment on the performance of quantum codes. In the second part, we studied the problem of the entanglement of the coherent field (that is used to turn on/off the gate) with the qubit on which gate operation is performed. The gate operation is made adiabatic by making the coherent field to change very slowly in time. The entanglement arises due to the quantum nature of the coherent field and causes faulty gate

  11. Electrostatically Gated Graphene-Zinc Oxide Nanowire Heterojunction.

    PubMed

    You, Xueqiu; Pak, James Jungho

    2015-03-01

    This paper presents an electrostatically gated graphene-ZnO nanowire (NW) heterojunction for the purpose of device applications for the first time. A sub-nanometer-thick energy barrier width was formed between a monatomic graphene layer and electrochemically grown ZnO NWs. Because of the narrow energy barrier, electrons can tunnel through the barrier when a voltage is applied across the junction. A near-ohmic current-voltage (I-V) curve was obtained from the graphene-electrochemically grown ZnO NW heterojunction. This near-ohmic contact changed to asymmetric I-V Schottky contact when the samples were exposed to an oxygen environment. It is believed that the adsorbed oxygen atoms or molecules on the ZnO NW surface capture free electrons of the ZnO NWs, thereby creating a depletion region in the ZnO NWs. Consequentially, the electron concentration in the ZnO NWs is dramatically reduced, and the energy barrier width of the graphene-ZnO NW heterojunction increases greatly. This increased energy barrier width reduces the electron tunneling probability, resulting in a typical Schottky contact. By adjusting the back-gate voltage to control the graphene-ZnO NW Schottky energy barrier height, a large modulation on the junction current (on/off ratio of 10(3)) was achieved.

  12. Gap protection and dynamical decoupling for reliable multi-qubit gates

    NASA Astrophysics Data System (ADS)

    Witzel, Wayne

    2014-03-01

    We propose a scheme for producing multi-qubit gates by adiabatically shuttling an electron between donors in silicon to produce operations that are diagonal in the computational basis. Exploiting the commutation of these diagonal operations, we can use single-qubit refocusing gates to cancel the sensitivity to low-frequency noise and details of the shuttling. This strategy of cancelling unwanted portions of an adiabatic process to build up robust multi-qubit operations could be applied to other systems. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL8.

  13. Mechanically reliable surface oxides for high-temperature corrosion resistance

    SciTech Connect

    Natesan, K.; Veal, B.W.; Grimsditch, M.; Renusch, D.; Paulikas, A.P.

    1995-05-01

    Corrosion is widely recognized as being important, but an understanding of the underlying phenomena involves factors such as the chemistry and physics of early stages of oxidation, chemistry and bonding at the substrate/oxide interface, role of segregants on the strength of that bond, transport processes through scale, mechanisms of residual stress generation and relief, and fracture behavior at the oxide/substrate interface. Because of this complexity a multilaboratory program has been initiated under the auspices of the DOE Center of Excellence for the Synthesis and Processing of Advanced Materials, with strong interactions and cross-leveraging with DOE Fossil Energy and US industry. Objective is to systematically generate the knowledge required to establish a scientific basis for designing and synthesizing improved protective oxide scales/coatings (slow-growing, adherent, sound) on high-temperature materials without compromising the requisite properties of the bulk materials. The objectives of program work at Argonne are to (1) correlate actual corrosion performance with stresses, voids, segregants, interface roughness, initial stages of oxidation, and microstructures; (2) study such behavior in growing or as-grown films; and (3) define prescriptive design and synthesis routes to mechanically reliable surface oxides. Several techniques, such as Auger electron spectroscopy, X-ray diffraction, X-ray grazing incidence reflectance, grazing-angle X-ray fluorescence, optical fluorescence, and Raman spectroscopy, are used in the studies. Tne project has selected Fe-25 wt.% Cr-20 wt.% Ni and Fe-Cr-Al alloys, which are chromia- and alumina-formers respectively, for the studies. This paper presents some of the results on early stages of oxidation and on surface segregation of elements.

  14. Impact of implantation on the properties of N 2O-nitrided oxides of p +- and n +-gate MOS devices

    NASA Astrophysics Data System (ADS)

    Naumova, O. V.; Fomin, B. I.; Sakharova, N. V.; Ilnitsky, M. A.; Popov, V. P.

    2009-05-01

    The impact of the gate implantation on properties of N2O-nitrided thermal oxides MOS dielectric layers were evaluated in this study via current-voltage, j-ramp and current-temperature techniques. The data obtained show that implantation with boron of poly-Si gates can result in generation of border traps in oxides. The energy position of traps generated in the oxides after Fowler-Nordheim voltage stress and after hard breakdown treatments were evaluated.

  15. Dual Gate Thin Film Transistors Based on Indium Oxide Active Layers

    SciTech Connect

    Kekuda, Dhananjaya; Rao, K. Mohan; Tolpadi, Amita; Chu, C. W.

    2011-07-15

    Polycrystalline Indium Oxide (In{sub 2}O{sub 3}) thin films were employed as an active channel layer for the fabrication of bottom and top gate thin film transistors. While conventional SiO{sub 2} served as a bottom gate dielectric, cross-linked poly-4-vinylphenol (PVP) was used a top gate dielectric. These nano-crystalline TFTs exhibited n-channel behavior with their transport behavior highly dependent on the thickness of the channel. The correlation between the thickness of the active layer and TFT parameters such as on/off ratio, field-effect mobility, threshold voltage were carried out. The optical spectra revealed a high transmittance in the entire visible region, thus making them promising candidates for the display technology.

  16. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry

    NASA Astrophysics Data System (ADS)

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  17. Characterization of reliability of printed indium tin oxide thin films.

    PubMed

    Hong, Sung-Jei; Kim, Jong-Woong; Jung, Seung-Boo

    2013-11-01

    Recently, decreasing the amount of indium (In) element in the indium tin oxide (ITO) used for transparent conductive oxide (TCO) thin film has become necessary for cost reduction. One possible approach to this problem is using printed ITO thin film instead of sputtered. Previous studies showed potential for printed ITO thin films as the TCO layer. However, nothing has been reported on the reliability of printed ITO thin films. Therefore, in this study, the reliability of printed ITO thin films was characterized. ITO nanoparticle ink was fabricated and printed onto a glass substrate followed by heating at 400 degrees C. After measurement of the initial values of sheet resistance and optical transmittance of the printed ITO thin films, their reliabilities were characterized with an isothermal-isohumidity test for 500 hours at 85 degrees C and 85% RH, a thermal shock test for 1,000 cycles between 125 degrees C and -40 degrees C, and a high temperature storage test for 500 hours at 125 degrees C. The same properties were investigated after the tests. Printed ITO thin films showed stable properties despite extremely thermal and humid conditions. Sheet resistances of the printed ITO thin films changed slightly from 435 omega/square to 735 omega/square 507 omega/square and 442 omega/square after the tests, respectively. Optical transmittances of the printed ITO thin films were slightly changed from 84.74% to 81.86%, 88.03% and 88.26% after the tests, respectively. These test results suggest the stability of printed ITO thin film despite extreme environments. PMID:24245331

  18. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  19. Extended-Gate Metal Oxide Semiconductor Field Effect Transistor-Based Biosensor for Detection of Deoxynivalenol

    NASA Astrophysics Data System (ADS)

    Kwon, Insu; Lee, Hee-Ho; Choi, Jinhyeon; Shin, Jang-Kyoo; Seo, Sang-Ho; Choi, Sung-Wook; Chun, Hyang Sook

    2011-06-01

    In this work, we present an extended-gate metal oxide semiconductor field effect transistor (MOSFET)-based biosensor for the detection of deoxynivalenol using a null-balancing circuit. An extended-gate MOSFET-based biosensor was fabricated by a standard complementary metal oxide semiconductor (CMOS) process and its characteristics were measured. A null-balancing circuit was used to measure the output voltage of the sensor directly, instead of measuring the drain current of the sensor. Au was used as the gate metal, which has a chemical affinity with thiol, which leads to the immobilization of a self-assembled monolayer (SAM) of mercaptohexadecanoic acid (MHDA). The SAM was used to immobilize the anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti-deoxynivalenol antibody. The anti-deoxynivalenol antibody and deoxynivalenol were bound by their antigen-antibody reaction. The measurements were performed in phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl electrode was employed as a reference electrode. The bindings of a SAM, anti-deoxynivalenol antibody, and deoxynivalenol caused a variation in the output voltage of the extended-gate MOSFET-based biosensor. Surface plasmon resonance (SPR) measurement was performed to verify the interaction among the SAM, deoxynivalenol-antibody, and deoxynivalenol.

  20. Band offsets of a ruthenium gate on ultrathin high-{kappa} oxide films on silicon

    SciTech Connect

    Rangan, Sylvie; Bersch, Eric; Bartynski, Robert Allen; Garfunkel, Eric; Vescovo, Elio

    2009-02-15

    Valence-band and conduction-band edges of ultrathin oxides (SiO{sub 2}, HfO{sub 2}, Hf{sub 0.7}Si{sub 0.3}O{sub 2}, and Al{sub 2}O{sub 3} grown on silicon) and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-{kappa} thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  1. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  2. Impact of carbon and nitrogen on gate dielectrics in metal-oxide-semiconductor devices

    NASA Astrophysics Data System (ADS)

    Choi, Minseok; Lyons, John; Janotti, Anderson; van de Walle, Chris

    2013-03-01

    Al2O3 and HfO2 are used as alternative gate oxides in CMOS technology. Promising results have been achieved with Al2O3/III-V and HfO2/Si MOS structures, which exhibit relatively low densities of interface states. However, the presence of charge traps and fixed-charge centers near the oxide/semiconductor interface still poses serious limitations in device performance. Native point defects are usually proposed as an explanation; unintentional incorporation of impurities in the gate dielectric during the deposition process has so far received less attention. Using first-principles calculations based on hybrid functionals we investigate the effects of carbon and nitrogen impurities in Al2O3 and HfO2. By analyzing the position of the impurity levels with respect to the III-V and Si band edges, we determine if these impurities can act as charge traps or sources of fixed charge. Our results show that carbon can act as a charge trap and lead to leakage current through the gate dielectric. Nitrogen can act as a source of negative fixed charge, but may be effective in alleviating the problem of charge traps and fixed charges associated with Al, Hf, and O vacancies. This work was supported by the ONR DEFINE MURI program.

  3. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors.

    PubMed

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Di Wang; Hahn, Horst; Dasgupta, Subho

    2016-10-14

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm(2) V(-1) s(-1). PMID:27609560

  4. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors

    NASA Astrophysics Data System (ADS)

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Wang, Di; Hahn, Horst; Dasgupta, Subho

    2016-10-01

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm2 V-1 s-1.

  5. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors.

    PubMed

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Di Wang; Hahn, Horst; Dasgupta, Subho

    2016-10-14

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm(2) V(-1) s(-1).

  6. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  7. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    PubMed Central

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-01-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems. PMID:27688042

  8. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    NASA Astrophysics Data System (ADS)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-09-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

  9. High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

    PubMed

    Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

    2015-07-01

    A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications. PMID:26039187

  10. Gate leakage mechanisms in strained Si devices

    NASA Astrophysics Data System (ADS)

    Yan, L.; Olsen, S. H.; Kanoun, M.; Agaiby, R.; O'Neill, A. G.

    2006-11-01

    This work investigates gate leakage mechanisms in advanced strained Si /SiGe metal-oxide-semiconductor field-effect transistor (MOSFET) devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si /SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si /SiGe devices are inadvertently subject to a potential tradeoff between power consumption (gate leakage current) and device reliability (gate oxide interface quality).

  11. Ionizing radiation induced leakage current on ultra-thin gate oxides

    SciTech Connect

    Scarpa, A.; Paccagnella, A.; Montera, F.; Ghibaudo, G.; Pananakakis, G.; Fuochi, P.G.

    1997-12-01

    MOS capacitors with a 4.4 nm thick gate oxide have been exposed to {gamma} radiation from a Co{sup 60} source. As a result, the authors have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. They have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. They have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

  12. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  13. Al and Ge simultaneous oxidation using neutral beam post-oxidation for formation of gate stack structures

    SciTech Connect

    Ohno, Takeo; Nakayama, Daiki; Samukawa, Seiji

    2015-09-28

    To obtain a high-quality Germanium (Ge) metal–oxide–semiconductor structure, a Ge gate stacked structure was fabricated using neutral beam post-oxidation. After deposition of a 1-nm-thick Al metal film on a Ge substrate, simultaneous oxidation of Al and Ge was carried out at 300 °C, and a Ge oxide film with 29% GeO{sub 2} content was obtained by controlling the acceleration bias power of the neutral oxygen beam. In addition, the fabricated AlO{sub x}/GeO{sub x}/Ge structure achieved a low interface state density of less than 1 × 10{sup 11 }cm{sup −2 }eV{sup −1} near the midgap.

  14. Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-06-01

    We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

  15. Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

    PubMed

    Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

    2015-05-27

    The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

  16. Deposition, stabilization and characterization of zirconium oxide and hafnium oxide thin films for high k gate dielectrics

    NASA Astrophysics Data System (ADS)

    Gao, Yong

    As the MOS devices continue to scale down in feature size, the gate oxide thickness is approaching the nanometer node. High leakage current densities caused by tunneling is becoming a serious problem. Replacing silicon oxide with a high kappa material as the gate dielectrics is becoming very critical. In recent years, research has been focused on a few promising candidates, such as ZrO2, HfO2, Al2O3, Ta 2O5, and some silicates. However, unary metal oxides tend to crystallize at relatively low temperatures (less than 700°C). Crystallized films usually have a very small grain size and high leakage current due to the grain boundaries. The alternatives are high kappa oxides which are single crystal or amorphous. Silicates remain amorphous at high temperatures, but have some problems such as phase separation, interface reaction, and lower kappa value. In this work, we addressed the crystallization problems of zirconium oxide and hafnium oxide thin films. Both of these two thin films were deposited by DC reactive magnetron sputtering so that very dense films were deposited with little damage. A specially designed system was set up in order to have good control of the deposition process. The crystallization behavior of as-deposited amorphous ZrO2 and HfO2 films was studied. It was found that the films tended to have higher crystallization temperature when the films were thinner than a critical thickness of approximately 5 nm. However, it was still well below 900°C. The crystallization temperature was significantly increased by sandwiching the high kappa oxide layer between two silica layers. Ultra thin HfO2 films of 5nm thickness remained amorphous up to 900°C. This is the highest crystallization temperature which has been reported. The mechanisms for this effect are proposed. Electrical properties of these high kappa dielectric films were also studied. It was found that ultra thin amorphous HfO2 and ZrO 2 films had superior electrical properties to crystalline films

  17. Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Jur, Jesse Stephen

    The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

  18. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  19. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics.

    PubMed

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 10(7), and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  20. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    NASA Astrophysics Data System (ADS)

    Park, Sungjun; Lee, Seyeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  1. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics.

    PubMed

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-14

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 10(7), and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  2. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  3. Evolution of Insulator-Metal Phase Transitions in Epitaxial Tungsten Oxide Films during Electrolyte-Gating.

    PubMed

    Nishihaya, Shinichi; Uchida, Masaki; Kozuka, Yusuke; Iwasa, Yoshihiro; Kawasaki, Masashi; Nishihaya, S; Uchida, M; Kozuka, Y; Iwasa, Y; Kawasaki, M; Iwasa, Y; Kawasaki, M

    2016-08-31

    An interface between an oxide and an electrolyte gives rise to various processes as exemplified by electrostatic charge accumulation/depletion and electrochemical reactions such as intercalation/decalation under electric field. Here we directly compare typical device operations of those in electric double layer transistor geometry by adopting A-site vacant perovskite WO3 epitaxial thin films as a channel material and two different electrolytes as gating agent. In situ measurements of X-ray diffraction and channel resistance performed during the gating revealed that in both the cases WO3 thin film reaches a new metallic state through multiple phase transitions, accompanied by the change in out-of-plane lattice constant. Electrons are electrostatically accumulated from the interface side with an ionic liquid, while alkaline metal ions are more uniformly intercalated into the film with a polymer electrolyte. We systematically demonstrate this difference in the electrostatic and electrochemical processes, by comparing doped carrier density, lattice deformation behavior, and time constant of the phase transitions. PMID:27502546

  4. Observing two stage recovery of gate oxide damage created under negative bias temperature stress

    NASA Astrophysics Data System (ADS)

    Aichinger, Thomas; Nelhiebel, Michael; Einspieler, Sascha; Grasser, Tibor

    2010-01-01

    We study the hysteresis in threshold voltage shift during alternating gate bias ramps (drain current vs gate voltage (IdVg) sweeps) after negative bias temperature stress and compare the results with carefully recorded charge pumping measurements. This allows us to clearly identify three different types of defects. All defect types have in common that their charge state depends on the position of the Fermi level and that they introduce a broad density of states (DOS) in the vicinity or within of the silicon band gap. Defect I is fully recoverable, defect II is similar to defect I in terms of DOS but does not recover, while defect III can be attributed to the conventional interface states. With a precise microstructural model in mind, and by using specific test chips, which allow us to vary stress bias and temperature quasiarbitrarily, we come to the conclusion that the carrier trapping and detrapping characteristics of stress induced defects can be controlled by temperature and electric field in a similar way, but that irrevocable structural relaxation is mainly influenced by temperature. Based on these ideas, we present a measurement method which can be used to energetically profile the relaxation of stress induced oxide defects.

  5. Trap generation and occupation in stressed gate oxides under spatially variable oxide electric field

    NASA Astrophysics Data System (ADS)

    Avni, E.; Shappir, J.

    1987-11-01

    The spatial variation of the oxide field in metal-oxide-silicon devices due to charge trapping under electron injection stress is included in a self-consistent trapping model. The model predicts the spatial distribution of the stress-generated trapping sites and their occupation level under different conditions of applied voltages and total injected charge. The calculated results agree quite well with the experimental results of prolonged charge injection, as expressed in shifts of the flatband voltage.

  6. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    NASA Astrophysics Data System (ADS)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-01

    We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from -15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e-/2e-), peroxide (O22-) formation or conversion of ionized interstitial (Oi2-) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows -2.7 V shift at VTG = -15 V, which gradually decreases to -0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22-/Oi) and/or hole trapping in the a-IGZO /interfaces.

  7. Electrical properties of metal-oxide-semiconductor structures with low-energy Ge-implanted and annealed thin gate oxides

    NASA Astrophysics Data System (ADS)

    Kapetanakis, E.; Normand, P.; Holliger, P.

    2008-03-01

    The electrical characteristics of low-energy (3keV) Ge-implanted and, subsequently, thermal annealed SiO2 layers are investigated through capacitance-voltage (C-V ) and conductance-voltage (G-V) measurements of metal-oxide-semiconductor capacitors. Particular emphasis is placed on the properties of such gate oxides for memory applications. Capacitance measurements at flatband voltage before and after the application of constant voltage stress in the accumulation regime indicate that the charge trapping behavior of the devices undergoes a major change after annealing at temperatures higher than 910°C. The latter change is identified as a relocation of Ge atoms mainly toward the upper portion of the oxide with a significant fraction of them leaving the oxide; a finding in harmony with secondary ion mass spectroscopy analysis. The interface trap density (Dit) for the thin (9-12nm) implanted oxides decreases with increasing annealing temperature, approaching at 950°C the Dit levels in the mid-1010eV-1cm-2 range of the nonimplanted samples. At elevated annealing temperatures (>1000°C), the device C-V characteristics are substantially disturbed. In this case, the presence of electrically active Ge atoms at an extended depth in the substrate modifies the intrinsic electrical properties of the n-Si substrate, lending a p-type conductivity character to the device high-frequency C-V curves. Substrate electrical modification is interpreted through a model that takes into account the formation of a SiO2/Ge-rich-Si /n-Si system. The SiO2/Ge-rich-Si interface presents very low Dit levels as revealed by conductance loss characteristics. The present study suggests that a combination of Ge implantation into SiO2 films and thermal annealing may be exploited in damage-free SiGe epitaxial growth technology based on Ge implantation.

  8. Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors

    NASA Astrophysics Data System (ADS)

    El Kazzi, M.; Czornomaz, L.; Rossel, C.; Gerl, C.; Caimi, D.; Siegwart, H.; Fompeyrine, J.; Marchiori, C.

    2012-02-01

    Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2 nm HfO2/1 nm Al2O3/1 nm a-Si gate stacks on p-In0.53Ga0.47As/InP (001) substrates. Thanks to the presence of the Al2O3 barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89 nm and mid-gap interface state density of 5 × 1011 eV-1 cm-2 upon post-metallization anneal up to 550 °C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5 nm HfO2/1 nm Al2O3/1 nm a-Si gate stack and raised source and drain (600 °C for 30 min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm2 V-1 s-1 and 740 cm2 V-1 s-1 at carrier density of 6.5 × 1012 cm-2) for a 1.3 nm EOT.

  9. A stable ATP binding to the nucleotide binding domain is important for reliable gating cycle in an ABC transporter CFTR.

    PubMed

    Shimizu, Hiroyasu; Yu, Ying-Chun; Kono, Koichi; Kubota, Takahiro; Yasui, Masato; Li, Min; Hwang, Tzyh-Chang; Sohma, Yoshiro

    2010-09-01

    Cystic fibrosis transmembrane conductance regulator (CFTR) anion channel, a member of ABC transporter superfamily, gates following ATP-dependent conformational changes of the nucleotide binding domains (NBD). Reflecting the hundreds of milliseconds duration of the channel open state corresponding to the dimerization of two NBDs, macroscopic WT-CFTR currents usually showed a fast, single exponential relaxation upon removal of cytoplasmic ATP. Mutations of tyrosine1219, a residue critical for ATP binding in second NBD (NBD2), induced a significant slow phase in the current relaxation, suggesting that weakening ATP binding affinity at NBD2 increases the probability of the stable open state. The slow phase was effectively diminished by a higher affinity ATP analogue. These data suggest that a stable binding of ATP to NBD2 is required for normal CFTR gating cycle, andthat the instability of ATP binding frequently halts the gating cycle in the open state presumably through a failure of ATP hydrolysis at NBD2. PMID:20628841

  10. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

    PubMed Central

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-01-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

  11. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance.

    PubMed

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-01-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm(2)/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 10(5), and a subthreshold slope of 0.10 V/dec. PMID:27641430

  12. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

    NASA Astrophysics Data System (ADS)

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-09-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

  13. Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region

    NASA Astrophysics Data System (ADS)

    Shin, Yong Hyeon; Yun, Ilgu

    2016-06-01

    This paper proposes an analytical model for an asymmetric double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with varying gate-oxide thickness (tox) and flat-band voltage (Vfb) in the subthreshold region. Since such variations cannot be completely avoided, the modeling of their behaviors is essential. The analytical model is developed by solving a 2D Poisson equation with a varying channel doping concentration (NA). To solve the 2D Poisson equation of the asymmetric DG MOSFET, a perturbation method is used to separate the solution of the channel potential into basic and perturbed terms. Since the basic terms can be regarded as the equations derived from a general symmetric doped DG MOSFET, the conventional analytical model is adopted. In addition, a solution related to the perturbed terms for the asymmetric structures is obtained using Fourier series. Based on the obtained channel potential, the electrical characteristics of the drive current (IDS) are expressed in the analytical model. The prediction of the electrical characteristics by the analytical model shows excellent agreement when compared with commercially available 2D numerical device simulation results with respect to not only tox and Vfb variations but also channel length and NA variations.

  14. Electron mobility in ultra-thin InGaAs channels: Impact of surface orientation and different gate oxide materials

    NASA Astrophysics Data System (ADS)

    Krivec, Sabina; Poljak, Mirko; Suligoj, Tomislav

    2016-01-01

    Electron mobility is investigated in sub-20 nm-thick InGaAs channels, sandwiched between different gate oxides (SiO2, Al2O3, HfO2) and InP as substrate, using physics-based numerical modeling. Effects of body thickness downscaling to 2 nm, different gate oxides, and surface orientation [(1 0 0) and (1 1 1)] are examined by including all electron valleys and all relevant scattering mechanisms. We report that ultra-thin (1 1 1) Al2O3-InGaAs-InP devices offer greater electron mobility than (1 0 0) devices even in the extremely-thin channels. Furthermore, ultra-thin (1 0 0) InGaAs devices outperform SOI in terms of electron mobility for body thicknesses above ∼4 nm, while (1 1 1) InGaAs channels are superior to SOI for all body thickness values above ∼3 nm. The study of different gate oxides indicates that HfO2 is the optimum gate dielectric regardless of device orientation, offering a mobility improvement of up to 124% for (1 1 1) and 149% for (1 0 0) surface orientation, when compared to the initial Al2O3-InGaAs-InP structure. The (1 1 1) orientation offers improvement over (1 0 0) device irrespective of the body thickness and gate oxide material, with the highest difference reported for SiO2, followed by Al2O3 and HfO2.

  15. Improvement in performance of solution-processed indium-zinc-tin oxide thin-film transistors by UV/O3 treatment on zirconium oxide gate insulator

    NASA Astrophysics Data System (ADS)

    Naik, Bukke Ravindra; Avis, Christophe; Delwar Hossain Chowdhury, Md; Kim, Taehun; Lin, Tengda; Jang, Jin

    2016-03-01

    We studied solution-processed amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs) with spin-coated zirconium oxide (ZrOx) as the gate insulator. The ZrOx gate insulator was used without and with UV/O3 treatment. The TFTs with an untreated ZrOx gate dielectric showed a saturation mobility (μsat) of 0.91 ± 0.29 cm2 V-1 s-1, a threshold voltage (Vth) of 0.28 ± 0.36 V, a subthreshold swing (SS) of 199 ± 37.17 mV/dec, and a current ratio (ION/IOFF) of ˜107. The TFTs with a UV/O3-treated ZrOx gate insulator exhibited μsat of 2.65 ± 0.43 cm2 V-1 s-1, Vth of 0.44 ± 0.35 V, SS of 133 ± 24.81 mV/dec, and ION/IOFF of ˜108. Hysteresis was 0.32 V in the untreated TFTs and was eliminated by UV/O3 treatment. Also, the leakage current decreased significantly when the IZTO TFT was coated onto a UV/O3-treated ZrOx gate insulator.

  16. Effect of nitrogen incorporation into Al-based gate insulators in AlON/AlGaN/GaN metal-oxide-semiconductor structures

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Nozaki, Mikito; Yamada, Takahiro; Ito, Joyo; Nakazawa, Satoshi; Ishida, Masahiro; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2016-10-01

    The superior physical and electrical properties of aluminum oxynitride (AlON) gate dielectrics on AlGaN/GaN substrates in terms of thermal stability, reliability, and interface quality were demonstrated by direct AlON deposition and subsequent annealing. Nitrogen incorporation into alumina was proven to be beneficial both for suppressing intermixing at the insulator/AlGaN interface and reducing the number of electrical defects in Al2O3 films. Consequently, we achieved high-quality AlON/AlGaN/GaN metal-oxide-semiconductor capacitors with improved stability against charge injection and a reduced interface state density as low as 1.2 × 1011 cm-2 eV-1. The impact of nitrogen incorporation into the insulator will be discussed on the basis of experimental findings.

  17. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    SciTech Connect

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  18. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  19. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    PubMed

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation. PMID:27007748

  20. Self-aligned graphene field-effect transistors on SiC (0001) substrates with self-oxidized gate dielectric

    NASA Astrophysics Data System (ADS)

    Jia, Li; Cui, Yu; Li, Wang; Qingbin, Liu; Zezhao, He; Shujun, Cai; Zhihong, Feng

    2014-07-01

    A scalable self-aligned approach is employed to fabricate monolayer graphene field-effect transistors on semi-insulated 4H-SiC (0001) substrates. The self-aligned process minimized access resistance and parasitic capacitance. Self-oxidized Al2O3, formed by deposition of 2 nm Al followed by exposure in air to be oxidized, is used as gate dielectric and shows excellent insulation. An intrinsic cutoff frequency of 34 GHz and maximum oscillation frequency of 36.4 GHz are realized for the monolayer graphene field-effect transistor with a gate length of 0.2 μm. These studies show a pathway to fabricate graphene transistors for future applications in ultra-high frequency circuits.

  1. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2015-06-01

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlOx) interlayers. A step-by-step in situ procedure by deposition of AlOx and hafnium oxide (HfOx) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO2/AlOx/GeOx/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlOx interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 1011 cm-2eV-1 with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  2. Lateral-coupled oxide electric-double-layer transistors gated by scandia-ceria-stabilized zirconia electrolyte

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Xiao, Hui; Wang, Jian Xin

    2016-01-01

    Scandia-ceria-stabilized zirconia (ScCeSZ) is one of the most important electrolytes used for solid oxide fuel cells. However, it has not been reported for applications in electrolyte gated transistors. Here, a high room-temperature proton conductivity of ~8  ×  10-3 S cm-1 and a large electric-double-layer capacitance of ~1.5 μF cm-2 are observed for a tape-casted water-infiltrated ScCeSZ electrolyte. A laterally coupled indium-tin oxide transistor gated by such an electrolyte exhibits good electric performances at a low voltage of 1.5 V, such as the on/off ratio of above 1  ×  105, mobility of 2.2 cm2 Vs-1 and subthreshold swing of ~160 mV/dec. Furthermore, unique synergic proton modulation behaviors are observed and AND logic operation is demonstrated. The laterally-coupled oxide transistors with synergic proton gating effects may find potential applications in chemical sensors and artificial neuromorphic devices.

  3. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  4. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    NASA Astrophysics Data System (ADS)

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-01

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiOx film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 1011 cm-2 eV-1 by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H2O molecules and facilitate dissociation of the molecules into H and OH-. The OH- ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H2O molecules. The ionization results in the electron stimulated dissociation of H2O molecules and the decreased interface trap density.

  5. Comparison of Measurement Techniques for Gate Shortening in Sub-Micrometer Metal Oxide Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Bhattacharya, Pradeep; Bari, Mohammad; Rao, Krishnaraj

    1993-08-01

    In this paper, various methods of evaluating the electrical channel length change (or gate shortening) as a result of applied gate voltage in sub-micrometer metal oxide semiconductor field effect transistors (MOSFETs) are investigated and the method best suited for such short channel length devices is reported. Studies were performed on n-channel transistors (n-MOSFETs) fabricated using X-ray and optical lithography and having channel lengths in the range of 0.4 to 4 μm and 1.5 to 10 μm respectively. The effective channel lengths were extracted from the current-voltage (I-V) measurements. The measurements were made for different low and high sets of gate voltages. In comparing various methods it was found that the method due to Terada and Muta, and Chern et al. gave accurate results consistently for short channel MOSFETs, whereas the Whitfield method gave accurate results only for larger channel length MOSFETs. The accuracy of the Whitfield method is sensitive to applied gate voltage during I-V measurements. The Peng and Afromowitz method is unsuitable for finding the effective channel length of sub-micrometer MOSFETs especially if the MOSFETs have high values of external resistance.

  6. Comparison of measurement techniques for gate shortening in sub-micrometer metal oxide semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Bhattacharya, Pradeep; Bari, Mohammad; Rao, Krishnaraj

    1993-08-01

    In this paper, various methods of evaluating the electrical channel length change (or gate shortening) as a result of applied gate voltage in sub-micrometer metal oxide semiconductor field effect transistors (MOSFETs) are investigated and the method best suited for such short channel length devices is reported. Studies were performed on n-channel transistors (n-MOSEFTs) fabricated using X-ray and optical lithography and having channel lengths in the range of 0.4 to 4 micron and 1.5 to 10 micron respectively. The effective channel lengths were extracted from the current-voltage (I-V) measurements. The measurements were made for different low and high sets of gate voltages. In comparing various methods it was found that the method due to Terada and Muta, and Chern et al. gave accurate results consistently for short channel MOSEFTs, whereas the Whitfield method gave accurate results only for larger channel length MOSEFTs. The accuracy of the Whitfield method is sensitive to applied gate voltage during I-V measurements. The Peng and Afromowitz method is unsuitable for finding the effective channel length of sub-micrometer MSFETs especially if the MSFETs have high values of external resistance.

  7. Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2014-11-07

    A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

  8. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  9. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  10. Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

    NASA Astrophysics Data System (ADS)

    Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

    2016-04-01

    Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

  11. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    NASA Astrophysics Data System (ADS)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  12. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  13. Extended characterization of the damage by hot charge carriers in gate oxide by short channel MOS field effect transistors

    NASA Astrophysics Data System (ADS)

    Mahnkopf, Reinhard

    Transistors from several technologies are tested by measurements of the capacities and the characteristic curves. A model allows obtaining of the gate and substrate currents. The damages at the phase limit and in the oxide are characterized by macroscopic current and voltage variations and by generated charge densities. For p-MOS (Metal Oxide Semiconductor) transistors, the production of oxide charges is the most important fact, in relation to the injected hot electrons; for n-MOS transistors, the generation of phase limit states is the main phenomenon. It is proved that the damages are located at the chain contact in the lateral direction but appear in the transistor channel with increasing functioning time or voltage.

  14. Extraction of Distance Between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage.

    PubMed

    Seo, Youngsoo; Yoo, Sungwon; Shin, Joonha; Kim, Hyunsoo; Kim, Hyunsuk; Jeon, Sangbin; Shin, Hyungcheol

    2016-05-01

    This paper presents an analysis of the Random Telegraph Noise (RTN) of the Gate-Induced Drain Leakage (GIDL) of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The RTN data that was measured and analytical equations are used to extract the values of the parameters for the vertical distance of the oxide trap from the interface and of the energy level of the interface trap. These values and equations allow for the distance r between the interface trap and the oxide trap to be extracted. For the first time, the accurate field enhancement factor γ(F), which depends on the magnitude of the electric field at the Si/SiO2 interface, was used to calculate the current ratio before and after the electron trapping, and the value extracted for r is completely different depending on the enhancement factor that is used. PMID:27483908

  15. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques

    PubMed Central

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained. PMID:24948884

  16. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques.

    PubMed

    Lee, Hsin-Ying; Huang, Hung-Lin; Tseng, Chun-Yen

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained.

  17. A method for the assessment of oxide charge density and centroid in metal-oxide-semiconductor structures after uniform gate stress

    NASA Astrophysics Data System (ADS)

    Kies, R.; Egilsson, T.; Ghibaudo, G.; Pananakakis, G.

    1996-06-01

    A method for the extraction of the oxide charge density and distribution centroid based on the exploitation of the Fowler plot derivative characteristics is proposed. To this end, the modification of the tunnel transparency due to the presence of charge within the tunneling region is accounted for. Simple analytical formulas which enable the oxide charge density and centroid to be extracted from the maximum Fowler derivative and its electric field position are derived. The comparison with the DiMaria method confirms the overall consistency of the new approach. The impact of negative charge within the oxide on the apparent Fowler barrier height, which can be deduced from the slope of the Fowler plots after uniform gate stress is also analyzed. Finally, it is pointed out that this method permits the oxide trapping properties to be studied even though only one bias polarization can be utilized for the test structure.

  18. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    PubMed

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT. PMID:27129687

  19. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    PubMed

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  20. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

    NASA Astrophysics Data System (ADS)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-04-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  1. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  2. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  3. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    NASA Astrophysics Data System (ADS)

    Chao, Jin Yu; Zhu, Li Qiang; Xiao, Hui; Yuan, Zhi Guo

    2015-12-01

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ˜1.0 V such as on/off ratio of ˜3 × 107, subthreshold swing of ˜65 mV/dec, threshold voltage of ˜0.3 V, and mobility of ˜7 cm2/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  4. ESD robustness concern and optimization for high-voltage p-type LDMOS transistor with thin gate oxide used as the output driver

    NASA Astrophysics Data System (ADS)

    Liu, Siyang; Sun, Weifeng; Wang, Hao; Ye, Ran; Zhang, Chunwei

    2014-11-01

    The p-type lateral double-diffused MOS (pLDMOS) transistor with thin gate oxide has significant advantages when being used as a high side output driver in high-voltage ICs (HVICs), because it usually possesses larger current density compared with a device with thick gate oxide. However, in order to reduce the chip size, many HVICs do not have specialized output electrostatic discharge (ESD) protection cells, so the pLDMOS device is operated both as the output driver and the ESD protection structure. In this work, we have found that the ESD robustness of the pLDMOS with thin gate oxide is poor. As a result, this device is risky for those area-efficient HVICs. To solve the contradiction, the inner mechanism of the poor ESD robustness for the pLDMOS with thin gate oxide has been investigated. Moreover, an improved method, by adjusting the overlap length between the special p-well and the source p+ implantation region, has been presented. The experimental results show that the ESD robustness of the improved pLDMOS with thin gate oxide has been obviously increased, while the large current density can be also maintained.

  5. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

    NASA Astrophysics Data System (ADS)

    Huoxi, Xu; Jingping, Xu

    2016-06-01

    LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV-1 cm-2), gate leakage property (3.6 × 10-3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials. Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

  6. Voltage-gated calcium channel currents in human coronary myocytes. Regulation by cyclic GMP and nitric oxide.

    PubMed Central

    Quignard, J F; Frapier, J M; Harricane, M C; Albat, B; Nargeot, J; Richard, S

    1997-01-01

    Voltage-gated Ca2+ channels contribute to the maintenance of contractile tone in vascular myocytes and are potential targets for vasodilating agents. There is no information available about their nature and regulation in human coronary arteries. We used the whole-cell voltage-clamp technique to characterize Ca2+-channel currents immediately after enzymatic dissociation and after primary culture of coronary myocytes taken from heart transplant patients. We recorded a dihydropyridine-sensitive L-type current in both freshly isolated and primary cultured cells. A T-type current was recorded only in culture. The L- (but not the T-) type current was inhibited by permeable analogues of cGMP in a dose-dependent manner. This effect was mimicked by the nitric oxide-generating agents S-nitroso-N-acetylpenicillamine (SNAP) and 3-morpholinosydnonimine which increased intracellular cGMP. Methylene blue, known to inhibit guanylate cyclase, antagonized the effect of SNAP. Inhibitions by SNAP and cGMP were not additive and seemed to occur through a common pathway. We conclude that (a) L-type Ca2+ channels are the major pathway for voltage-gated Ca2+ entry in human coronary myocytes; (b) their inhibition by agents stimulating nitric oxide and/or intracellular cGMP production is expected to contribute to vasorelaxation and may be involved in the therapeutic effect of nitrovasodilators; and (c) the expression of T-type Ca2+ channels in culture may be triggered by cell proliferation. PMID:9005986

  7. A Back-Gated Ferroelectric Field-Effect Transistor with an Al-Doped Zinc Oxide Channel

    NASA Astrophysics Data System (ADS)

    Jia, Ze; Xu, Jian-Long; Wu, Xiao; Zhang, Ming-Ming; Liou, Juin-J.

    2015-02-01

    We report a back-gated metal-oxide-ferroelectric-metal (MOFM) field-effect transistor (FET) with lead zirconate titanate (PZT) material, in which an Al doped zinc oxide (AZO) channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.

  8. Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

    NASA Astrophysics Data System (ADS)

    Kwon, Dae Woong; Kim, Jang Hyun; Park, Euyhwan; Lee, Junil; Park, Taehyung; Lee, Ryoongbin; Kim, Sihyun; Park, Byung-Gook

    2016-06-01

    A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

  9. Explicit Compact Surface-Potential and Drain-Current Models for Generic Asymmetric Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Zhu, Zhaomin; Zhou, Xing; Chandrasekaran, Karthik; Rustagi, Subhash C.; See, Guan Huei

    2007-04-01

    In this paper, explicit surface potentials for undoped asymmetric-double-gate (a-DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) suitable for compact model development are presented for the first time. The model is physically derived from Poisson’s equation in each region of operation and adopted in a unified regional approach. The proposed model is physically scalable with oxide/channel thicknesses and has been verified with generic implicit solutions for independent gate biases as well as for different gate/oxide materials. The model is extendable to silicon-on-insulator (SOI) and symmetric-DG (s-DG) MOSFETs. Finally, a continuous, explicit drain-current equation has been derived on the basis of the developed explicit surface-potential solutions.

  10. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  11. A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal-Oxide-Semiconductor Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Chiang, Te-Kuang; Chen, Mei-Li

    2007-06-01

    Based on resultant solution of a two-dimensional (2D) Poisson’s equation in the silicon region, a new analytical model for short-channel fully depleted, symmetrical dual-material double-gate (SDMDG) metal-oxide-semiconductor field effect transistors (MOSFETs) has been developed. The SDMDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical double-gate (SDG) MOSFET due to the step potential profile at the interface between different gate materials. It is found that the threshold voltage roll-off can be effectively reduced using both the thin Si film and thin gate oxide. A considerable portion of the large workfunction of metal gate 1 (M1) when laterally merged with the small workfunction of metal gate 2 (M2) can efficiently suppress drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. In this work, not only a precise 2D analytical model of the surface potential and threshold voltage is presented, but also the minimum surface potential in M1 of the shorter channel device that brings about subthreshold swing degradation for the SDMDG MOSFET is discussed. The new model is verified to be in good agreement with numerical simulation results over a wide range of device parameters.

  12. Inorganic oxide core, polymer shell nanocomposite as a high K gate dielectric for flexible electronics applications.

    PubMed

    Maliakal, Ashok; Katz, Howard; Cotts, Pat M; Subramoney, Shekhar; Mirau, Peter

    2005-10-26

    Organic/inorganic core shell nanoparticles have been synthesized using high K TiO(2) as the core nanoparticle, and polystyrene as the shell. This material is easy to process and forms transparent continuous thin films, which exhibit a dielectric constant enhancement of over 3 times that of bulk polystyrene. This new dielectric material has been incorporated into capacitors and thin film transistors (TFTs). Mobilities approaching 0.2 cm(2)/V.s have been measured for pentacene TFTs incorporating the new TiO(2) polystyrene nanostructured gate dielectric, indicating good surface properties for pentacene film growth. This novel strategy for generating high K flexible gate dielectrics will be of value in improving organic and flexible electronic device performance.

  13. Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

    NASA Astrophysics Data System (ADS)

    Oh, Se Woong; Park, Sang Su; Kim, Dong Hun; Kim, Hyun Woo; Kim, Tae Whan

    2009-06-01

    Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices.

  14. Indium-zinc-oxide electric-double-layer thin-film transistors gated by silane coupling agents 3-triethoxysilylpropylamine-graphene oxide solid electrolyte

    NASA Astrophysics Data System (ADS)

    Guo, Liqiang; Huang, Yukai; Shi, Yangyang; Cheng, Guanggui; Ding, Jianning

    2015-07-01

    Silane coupling agents 3-triethoxysilylpropyla-mine-graphene oxide (KH550-GO) solid electrolyte are prepared by spin coating process. A high proton conductivity of ~1.2   ×   10-3 Scm-1 is obtained at room temperature. A strong electric-double-layer (EDL) effect is observed due to the accumulation of protons at KH550-GO/IZO interface. Indium-Zinc-Oxide thin film transistors gated by KH550-GO solid electrolyte are self-assembled on ITO glass substrates. Good electrical performances are obtained, such as a low subthreshold swing of ~140 mV/dec., a high current on/off ratio of ~2.9   ×   107 and a high field-effect mobility of ~13.2 cm2 V-1 S-1, respectively.

  15. Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

    PubMed

    Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

    2013-06-11

    We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

  16. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    SciTech Connect

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-24

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  17. Reliability of thickness of oxide layer of stainless steels with chromium using cellular automaton model

    SciTech Connect

    Lan, K. C.; Chen, Y.; Yu, G. P.; Hung, T. C.

    2012-07-01

    A cellular automaton (CA) model based on the stochastic approach was proposed to simulate the process of oxidation and corrosion of stainless steels with different contents of chromium in-flowing lead bismuth eutectic (LBE). Chromium is a crucial alloying element added in stainless steels and nickel based alloys which have been proposed to be used in advanced nuclear reactors to improve resistance of the oxidation and corrosion. To verify the reliability of the thickness of the oxide layer by CA model, the influence of the stochastic character on the simulating results was investigated as changing parameter of chromium content of structure material in this study. Ten independent simulations were run for each specific environment. A stable and reasonable results were obtained according to the chi-square of goodness-of-fit test, the chi-square of the thickness of oxide layer for each case were significant smaller than critical chi-square value with a confidence level of 95% ({Chi}{sup 2}{alpha}, v = {Chi}{sup 2} 0.05,9 = 16.92). (authors)

  18. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    SciTech Connect

    Zhu, Li Qiang Chao, Jin Yu; Xiao, Hui

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  19. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

    2014-12-01

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ˜8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  20. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  1. Evaluation of nickel and molybdenum silicides for dual gate complementary metal-oxide semiconductor application

    NASA Astrophysics Data System (ADS)

    Biswas, Nivedita; Gurganus, Jason; Misra, Veena; Yang, Yan; Stemmer, Susanne

    2005-01-01

    Characteristics of NiSi and MoSi via full consumption of undoped silicon layers have been studied. Interaction of nickel (Ni) and molybdenum (Mo) silicides with SiO2 was evaluated in terms of work function and thermal stability. For nickel silicide, the work function values were low for samples annealed at 400 °C even after full consumption of silicon. The work function increased with the anneal temperature and stabilized at 600 °C to close to midgap values. Dielectric interaction as a result of silicide formation was studied using current-voltage characteristics. Low leakage currents in these stacks indicated minimum dielectric damage due to silicided gates. Silicidation of Mo was found to be incomplete as the capacitance-voltage curves were marked with larger EOT values and negative shifts in the flatband voltages even at 700 °C. Auger depth profiling, high resolution transmission electron microscopy (HRTEM) and x-ray diffraction (XRD) were used for material analysis of the silicided gate stacks.

  2. Gates and binding pockets for nitric oxide with cytochrome c', according to molecular dynamics.

    PubMed

    Pietra, Francesco

    2013-09-01

    Random-acceleration molecular-dynamics (RAMD) simulations with models of homodimeric 6-ligated distal-NO and 5-ligated proximal-NO cytochrome c' complexes, in TIP3 H2 O, showed two distinct, non-intercommunicating worlds. In the framework of a long cavity formed by four protein helices with heme at one extremity, NO was observed to follow different pathways with the two complexes to reach the solvent. With the 6-ligated complex, NO was observed to progress by exploiting protein internal channels created by thermal fluctuations, and be temporarily trapped into binding pockets before reaching the preferred gate at the heme end of the cavity. In contrast, with the 5-ligated complex, NO was observed to surface the solvent-exposed helix 7, up to a gate at the other extremity of the protein, only occasionally finding an earlier, direct way out toward the solvent. That only bulk NO gets involved in forming the 5-ligated proximal-NO complex is in agreement with previous experimental observations, while the occurrence of binding pockets suggests that also reservoir NO might play a role with the distal-NO complex.

  3. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Esro, M.; Mazzocco, R.; Vourlias, G.; Kolosov, O.; Krier, A.; Milne, W. I.; Adamopoulos, G.

    2015-05-01

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (LaxAl1-xOy) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the LaxAl1-xOy films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlOy dielectrics exhibit a wide band gap (˜6.18 eV), high dielectric constant (k ˜ 16), low roughness (˜1.9 nm), and very low leakage currents (<3 nA/cm2). TFTs employing solution processed LaAlOy gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (˜10 V), high on/off current modulation ratio of >106, subthreshold swing of ˜650 mV dec-1, and electron mobility of ˜12 cm2 V-1 s-1.

  4. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  5. Aqueous combustion synthesis of aluminum oxide thin films and application as gate dielectric in GZTO solution-based TFTs.

    PubMed

    Branquinho, Rita; Salgueiro, Daniela; Santos, Lídia; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2014-11-26

    Solution processing has been recently considered as an option when trying to reduce the costs associated with deposition under vacuum. In this context, most of the research efforts have been centered in the development of the semiconductors processes nevertheless the development of the most suitable dielectrics for oxide based transistors is as relevant as the semiconductor layer itself. In this work we explore the solution combustion synthesis and report on a completely new and green route for the preparation of amorphous aluminum oxide thin films; introducing water as solvent. Optimized dielectric layers were obtained for a water based precursor solution with 0.1 M concentration and demonstrated high capacitance, 625 nF cm(-2) at 10 kHz, and a permittivity of 7.1. These thin films were successfully applied as gate dielectric in solution processed gallium-zinc-tin oxide (GZTO) thin film transistors (TFTs) yielding good electrical performance such as subthreshold slope of about 0.3 V dec(-1) and mobility above 1.3 cm2 V(-1) s(-1). PMID:25354332

  6. Reliability and fatigue failure modes of implant-supported aluminum-oxide fixed dental prostheses

    PubMed Central

    Stappert, Christian F. J.; Baldassarri, Marta; Zhang, Yu; Hänssler, Felix; Rekow, Elizabeth D.; Thompson, Van P.

    2012-01-01

    Objectives To investigate failure modes and reliability of implant-supported aluminum-oxide three-unit fixed-dental-prostheses (FDPs) using two different veneering porcelains. Material and methods Thirty-six aluminum-oxide FDP-frameworks were CAD/CAM fabricated and either hand-veneered(n=18) or over-pressed(n=18). All FDPs were adhesively luted to custom-made zirconium-oxide-abutments attached to dental implant fixtures (RP-4×13mm). Specimens were stored in water prior to mechanical testing. A Step-Stress-Accelerated-Life-Test (SSALT) with three load/cycles varying profiles was developed based on initial single-load-to-failure testing. Failure was defined by veneer chipping or chipping in combination with framework fracture. SSALT was performed on each FDP inclined 30° with respect to the applied load direction. For all specimens, failure modes were analyzed using polarized-reflected-light-microscopy and scanning-electron-microscopy (SEM). Reliability was computed using Weibull analysis software (Reliasoft). Results The dominant failure mode for the over-pressed FDPs was buccal chipping of the porcelain in the loading area of the pontic, while hand-veneered specimens failed mainly by combined failure modes in the veneering porcelain, framework and abutments. Chipping of the porcelain occurred earlier in the over-pressed specimens (350 N/85k, load/cycles) than in the hand-veneered (600 N/110k)(profile I). Given a mission at 300 N load and 100k or 200 K cycles the computed Weibull reliability (2-sided at 90.0 % confidence bounds) was 0.99(1/0.98) and 0.99(1/0.98) for hand-veneered FDPs, and 0.45(0.76/0.10) and 0.05(0.63/0) for over-pressed FDPs, respectively. Conclusions In the range of average clinical loads (300–700 N), hand-veneered aluminum-oxide FDPs showed significantly less failure by chipping of the veneer than the over-pressed. Hand-veneered FDPs under fatigue loading failed at loads ≥ 600N. PMID:22093019

  7. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy

    PubMed Central

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-01-01

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band. PMID:26446400

  8. Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

    SciTech Connect

    Ceschia, M.; Paccagnella, A. |; Cester, A.; Scarpa, A.; Ghidini, G.

    1998-12-01

    Low-field leakage current has been measured in thin oxides after exposure to ionizing radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunneling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely being defects associated to trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

  9. Oxidation of Phe454 in the Gating Segment Inactivates Trametes multicolor Pyranose Oxidase during Substrate Turnover

    PubMed Central

    Volc, Jindrich; Peterbauer, Clemens K.; Leitner, Christian; Haltrich, Dietmar

    2016-01-01

    The flavin-dependent enzyme pyranose oxidase catalyses the oxidation of several pyranose sugars at position C-2. In a second reaction step, oxygen is reduced to hydrogen peroxide. POx is of interest for biocatalytic carbohydrate oxidations, yet it was found that the enzyme is rapidly inactivated under turnover conditions. We studied pyranose oxidase from Trametes multicolor (TmPOx) inactivated either during glucose oxidation or by exogenous hydrogen peroxide using mass spectrometry. MALDI-MS experiments of proteolytic fragments of inactivated TmPOx showed several peptides with a mass increase of 16 or 32 Da indicating oxidation of certain amino acids. Most of these fragments contain at least one methionine residue, which most likely is oxidised by hydrogen peroxide. One peptide fragment that did not contain any amino acid residue that is likely to be oxidised by hydrogen peroxide (DAFSYGAVQQSIDSR) was studied in detail by LC-ESI-MS/MS, which showed a +16 Da mass increase for Phe454. We propose that oxidation of Phe454, which is located at the flexible active-site loop of TmPOx, is the first and main step in the inactivation of TmPOx by hydrogen peroxide. Oxidation of methionine residues might then further contribute to the complete inactivation of the enzyme. PMID:26828796

  10. Phospho-silicate glass gated 4H-SiC metal-oxide-semiconductor devices: Phosphorus concentration dependence

    NASA Astrophysics Data System (ADS)

    Jiao, C.; Ahyi, A. C.; Xu, C.; Morisette, D.; Feldman, L. C.; Dhar, S.

    2016-04-01

    The correlation between phosphorus concentration in phospho-silicate glass (PSG) gate dielectrics and electrical properties of 4H-SiC MOS devices has been investigated. Varying P uptake in PSG is achieved by changing the POCl3 post-oxidation annealing temperature. The density of interface traps (Dit) at the PSG/4H-SiC interface decreases as the amount of interfacial P increases. Most significantly, the MOSFET channel mobility does not correlate with Dit for all samples, which is highly unusual for SiC MOSFETs. Further analysis reveals two types of field-effect mobility (μfe) behavior, depending on the annealing temperature. Annealing at 1000 °C improves the channel mobility most effectively, with a peak value ˜105 cm2 V-1 s-1, and results in a surface phonon scattering limited mobility at high oxide field. On the other hand, PSG annealed at other temperatures results in a surface roughness scattering limited mobility at similar field.

  11. The Impacts of Contact Etch Stop Layer Thickness and Gate Height on Channel Stress in Strained N-Metal Oxide Semiconductor Field Effect Transistors.

    PubMed

    Lin, K C; Twu, M J; Deng, R H; Liu, C H

    2015-04-01

    The stress induced by strain in the channel of metal oxide semiconductor field effect transistors (MOSFET) is an effective method to boost the device performance. The geometric dimensions of spacer, gate height, and the contact etch stop layer (CESL) are important factors among the feasible booster. This study utilized the mismatch of the thermal expansion coefficients of stressors to simulate the process-induced stress in the N-MOSFET. Different temperatures are applied to different region of the device to generate the required strain. The analysis was performed by well-developed finite element package. The composite spacers with variant width of inserted silicon nitride (SiO2/SiN/SiO2, ONO) were proposed and their impacts on channel stress were compared. Two aspects of the impacts of those factors on the channel stress in the longitudinal direction for N-MOSFET with variant channel length were investigated. Firstly, the channel stresses of device without CESL for different gate heights were studied. Secondly, with stress applied to CESL and ONO spacers, the induced stresses in the channel were analyzed for long/short gate length. Two conclusions were drawn from the results of simulation. The N-MOSFET device without CESL shows that the stressed spacer alone generates compressive stress and the magnitude increases along with higher gate height. The channel stress becomes tensile for device with CESL and increases when the thickness of CESL and the height of gate increase, especially for device with shorter gate length. The gate height plays more significant role in inducing channel stress compared with the thickness of CESL. The channel stress can be used to quantify the mobility of electron/hole for strained MOSFET device. Therefore, with the guideline disclosed in this study, better device performance can be expected for N-MOSFET. PMID:26353480

  12. Oxide degradation mechanism in stacked-gate flash memory using the cell array stress test

    NASA Astrophysics Data System (ADS)

    Tsai, Shih-Hung; Hung, Jui-Sheng; Wang, Na-Fu; Horng, Jui-Hong; Houng, Mau-Phon; Wang, Yeong-Her

    2003-09-01

    The generation of oxide charges and interface states during the program/erase operation in flash memory has been known to degrade the tunnel oxide quality. However, there is still no effective method to analyse the endurance and disturbed performance of the flash memory at the test level. So in this paper, a simple and fast method is applied to characterize the endurance and disturbed performance on a 98K bit flash cell array stress test structure. Based on this structure, the behaviour of the weakest part of the memory array after the program/erase operation can be easily observed. Moreover, the effects of the oxide charges and interface states generated are also discussed. Also, excess hole trapping in the oxide leads to fast charge loss during the disturbance test. The fast charge loss caused by holes is the more serious of these two failure mechanisms because the relatively low high-state VT can be corrected by circuit-level, program/erase-verified sequences. However, poor disturbance characteristics cause logical errors during the reading of an array.

  13. Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks.

    PubMed

    Henkel, Christoph; Hellström, Per-Erik; Ostling, Mikael; Stöger-Pollach, Michael; Bethge, Ole; Bertagnolli, Emmerich

    2012-08-01

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La x Ge y O z interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k La x Ge y O z layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found. PMID:23483756

  14. Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks

    PubMed Central

    Henkel, Christoph; Hellström, Per-Erik; Östling, Mikael; Stöger-Pollach, Michael; Bethge, Ole; Bertagnolli, Emmerich

    2012-01-01

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011 eV−1 cm−2 are demonstrated. The formation of the high-k LaxGeyOz layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found. PMID:23483756

  15. Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

    PubMed Central

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-01-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  16. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    NASA Astrophysics Data System (ADS)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-01

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  17. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  18. Electrical Properties and Reliability Analysis of Solution-Processed Indium Tin Zinc Oxide Thin Film Transistors with O2-Plasma Treatment.

    PubMed

    Ko, Sun Wook; Kim, Soon Kon; Kim, Jong Min; Cho, Jae Hee; Park, Hyoung Sun; Choi, Byoung Deog

    2015-10-01

    In this paper, we report the effects of O2-plasma treatment on the reliability and electrical properties of indium tin zinc oxide (ITZO) films. Excellent electrical properties, including a saturation mobility (μsat) of ~20.2 cm2/V · s, a threshold voltage (VTH) of ~-6.8 V, a sub-threshold swing (S.S) of ~0.956 V/decade, and an on/off current ratio (ION/OFF) of ~10(5) can be found with a molarity of 0.4 M and ratio of In:Zn:Sn = 2:1:2. Following O2-plasma treatment, it was confirmed that the electrical properties of the ITZO films are improved when compared to the untreated films. The devices showed a decreased S.S of ~0.51 V/decade, while the VTH and ION/OFF tended to increase. To determine the reliability of a-ITZO TFTs, we analyzed the electrical characteristics according to gate bias stress, VG,stress = 10 V for 4000 s. Improved reliability was confirmed when compared with the variation in threshold voltage prior to O2-plasma treatment, most likely stemming from a smooth surface on the active layer as a result of O2-plasma treatment. We were able to obtain a solution a-ITZO film transmittance of 92% in the visible light region (400~700 nm). These results show that a-ITZO TFTs fabricated via solution process with optimized molar ratio exhibit good electrical properties. a-ITZO films fabricated via spin-coating are a visible alternative to those fabricated via high-cost sputtering methods, and are applicable in flexible and transparent electronics. PMID:26726354

  19. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    NASA Astrophysics Data System (ADS)

    Babadi, A. S.; Lind, E.; Wernersson, L. E.

    2014-12-01

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  20. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    SciTech Connect

    Babadi, A. S. Lind, E.; Wernersson, L. E.

    2014-12-07

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  1. Study of Novel Floating-Gate Oxide Semiconductor Memory Using Indium-Gallium-Zinc Oxide for Low-Power System-on-Panel Applications

    NASA Astrophysics Data System (ADS)

    Yamauchi, Yoshimitsu; Kamakura, Yoshinari; Isagi, Yousuke; Matsuoka, Toshimasa; Malotaux, Satoshi

    2013-09-01

    A novel floating-gate oxide semiconductor (FLOTOS) memory using a wide-band-gap indium-gallium-zinc oxide (IGZO) is presented for low-power system-on-panel applications. An IGZO thin-film-transistor (TFT) is used as a memory transistor for controlling read current as well as a switching transistor for storing charges in a storage capacitor (Cs). The FLOTOS memory is fabricated using a standard IGZO TFT process without any additional process or mask steps. The proposed precharge-assisted threshold voltage compensation technique makes it possible to realize an infinite number of write cycles and a low-power write operation with a bit-line voltage of 5 V. Furthermore, excellent data retention longer than 10 h is obtained at 60 °C even under the worst bias-stress condition of read operation with the ultra low off-state leakage (2.8×10-20 A/µm) of the IGZO TFTs, which is estimated to be smaller by more than 7 orders of magnitude than that of polycrystalline silicon TFTs.

  2. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect

    Kamioka, J.; Oda, S.; Kodera, T.; Takeda, K.; Obata, T.; Tarucha, S.

    2014-05-28

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  3. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  4. Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

    NASA Astrophysics Data System (ADS)

    Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

    2016-04-01

    Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

  5. Quantum Mechanical Effects on the Threshold Voltage of Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Liu, Ran; Qiu, Zhi-Jun; Wang, Ling-Li; Tang, Ting-Ao

    2010-03-01

    A model for a metal-oxide-semiconductor field-effect transistor (MOSFET) with a double gate (DG) is developed. Quantum mechanical effects on the threshold voltage (VTH) are modeled and investigated analytically. The analytic model shows how VTH is increased with quantum mechanical effect. The model is applicable to both symmetric DG (SDG) and asymmetric DG (ADG) nMOSFETs, and is also applicable to both doped and undoped DG nMOSFETs. The analytic results are verified by comparing with the results obtained from simulations using Schred, and good agreement is observed. The VTH of an ADG nMOSFET will shift more than that of an SDG nMOSFET, and the VTH of a DG transistor with (110)-silicon (Si) orientation will shift more than that of a DG transistor with (100)-Si orientation. When the silicon thickness tsi < 3 nm, the VTH shift will be significant, and one should be careful in the use of an extremely thin silicon body. When the body doping density (NA) is not high (<1018 cm-3), the VTH shift is almost the same for different NA. When NA > 1018 cm-3, the higher the NA, the more the VTH shift.

  6. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors.

  7. Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chaitali; Bose, Chayanika

    2016-02-01

    The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal-oxide-semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si-substrate interface than to SiO2/Al-gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance-voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

  8. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors. PMID:27077327

  9. Multi-technique Approach for the Evaluation of the Crystalline Phase of Ultrathin High-k Gate Oxide Films

    NASA Astrophysics Data System (ADS)

    Bersch, E.; LaRose, J. D.; Wells, I.; Consiglio, S.; Clark, R. D.; Leusink, G. J.; Matyi, R. J.; Diebold, A. C.

    2011-11-01

    In order to continue scaling metal oxide semiconductor field effect transistors (MOSFETs) with HfO2 gate oxides, efforts are being made to further improve the deposited high-k film properties. Recently, a process whereby an HfO2 film is deposited through a series of depositions and anneals (so-called DADA process) has been shown to result in films that give rise to MOS capacitors (MOSCAPs) which are electrically scaled compared to MOSCAPs with HfO2 films that only received post deposition anneals (PDA) or no anneals. We have measured as-deposited, DADA and PDA HfO2 films using four measurement techniques, all of which are non-destructive and capable of being used for in-line processing, to evaluate their crystallinity and crystalline phases. Grazing incidence in-plane X-ray diffraction was used to determine the crystalline phases of the HfO2 films. We observed the crystalline phases of these films to be process dependent. Additionally, X-ray and UV photoelectron spectroscopy were used to show the presence of crystallinity in the films. As a fourth technique, spectroscopic ellipsometry was used to determine if the crystalline phases were monoclinic. The combination of techniques was useful in that XPS and UPS were able to confirm the amorphous nature of a 30 cycle DADA film, as measured by GIIXRD, and GIIXRD was able to help us interpret the SE data as being an indication of the monoclinic phase of HfO2.

  10. Reduction of surface roughening due to copper contamination prior to ultra-thin gate oxidation

    NASA Astrophysics Data System (ADS)

    Peterson, Charles A.; Vermeire, Bert; Sarid, Dror; Parks, Harold G.

    2001-09-01

    Roughening of the polished side of a silicon wafer caused by copper contamination present on the unpolished side of the wafer was quantified by tapping-mode atomic force microscopy (AFM). The copper contamination was introduced via a contaminated buffered hydrochloric acid solution on the unpolished side of the silicon wafer while the polished side was protected. The protection was then removed, and the wafer placed in a clean HF solution. As a result, the copper on the unpolished side catalyzed electrochemical dissolution of the polished side of the silicon. Power spectral density analysis of hundreds of AFM images showed a 10-fold increase in surface roughness with features between 30 and 300 nm in diameter. Time-dependant dielectric breakdown measurements showed a significant decrease in oxide quality in these wafers. However, the introduction of HCl to the HF solution significantly reduced the roughening process.

  11. The development of non-uniform deposition of holes in gate oxides

    SciTech Connect

    Freitag, R.K.; Dozier, C.M.; Brown, D.B.; Burke, E.A.

    1988-12-01

    The subthreshold technique was used to study irradiated MOS transistors at 80 K. Stretchout of the subthreshold curve demonstrated production of lateral non-uniformities (LNUs) in the hole distribution. The LNUs were analyzed in terms of (a) a parallel transistor model, and (b) the statistics of the non-uniform distribution of dose deposition in the SiO/sub 2/. The results confirm the hypothesis that at 80 K the principal source of LNUs is the granularity in dose deposition. The relative standard deviation for the deposited dose is larger for thin oxides, for 10 kev x-rays (as opposed to Co-60), and at low doses. These physical phenomena are predicted to have a significant effect at room temperature also.

  12. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    NASA Astrophysics Data System (ADS)

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-05-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2‑xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of ‑2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  13. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  14. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    PubMed Central

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2−xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of −2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  15. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect

    Oshima, Yasuhiro; Sun, Yun; Kuzum, Duygu; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  16. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  17. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  18. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  19. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE PAGESBeta

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  20. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS} = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  1. High Performance Enhancement-Mode AlGaN/GaN MOSHEMT using Bimodal-Gate-Oxide and CF4 Plasma Treatment

    NASA Astrophysics Data System (ADS)

    Pang, Liang; Kim, Kyekyoon

    2013-03-01

    To realize GaN E-mode HEMTs, CF4 plasma treatment is commonly used. However, comparable performance as the D-mode counterpart has yet to be achieved, since the F-ions implanted into 2DEG degrade the electron mobility by impurity scattering. In this study, a bimodal-gate-oxide scheme is developed, where ALD-Al2O3is utilized to prevent deep ion implantation, and sputtered-SiO2 is employed to suppress plasma-induced leakage current. Firstly, with the Al2O3 energy barrier, the CF4-plasma-treated MOSHEMT increased Vth from -3 V to 0 V, while Imax was only reduced from 503 mA/mm to 460 mA/mm. SIMS measurements confirmed that F- ions were accumulated in the top 5 nm of Al2O3, and the 2DEG impurity concentration was 10 times smaller than the conventional structure. However, due to the gate leakage current through plasma-generated defects in Al2O3, the device exhibited small gate swing of 2 V. Therefore, before gate metal deposition, a SiO2 film was sputtered at room temperature in a self-aligned manner. The highly condensed sputtered-SiO2 was effective in blocking the leakage current. Thus-fabricated bimodal-MOSHEMT exhibited Vth of 0 V, gate swing of 5 V, and Imaxof 462 mA/mm. The small 8% current degradation when converting from D-mode to E-mode is better than previous results. The MOCVD AlGaN/GaN templates used in this work were provided by Kyungpook National University, Korea for which we are grateful to Prof. Jung-Hee Lee and Mr. Dong-Seok Kim.

  2. Effect of Pr Valence State on Interfacial Structure and Electrical Properties of Pr Oxide/PrON/Ge Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Sakashita, Mitsuo; Takeuchi, Wakana; Kondo, Hiroki; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-04-01

    In this study, we investigated the valence state and chemical bonding state of Pr in a Pr oxide/PrON/Ge structure. We clarified the relationship between the valence state of Pr and the Pr oxide/Ge interfacial reaction using Pr oxide/Ge and Pr oxide/PrON/Ge samples. We found the formation of three Pr oxide phases in Pr oxide films; hexagonal Pr2O3 (h-Pr2O3) (Pr3+), cubic Pr2O3 (c-Pr2O3) (Pr3+), and c-PrO2 (Pr4+). We also investigated the effect of a nitride interlayer on the interfacial reaction in Pr oxide/Ge gate stacks. In a sample with a nitride interlayer (Pr oxide/PrON/Ge), metallic Pr-Pr bonds are also formed in the c-Pr2O3 film. After annealing in H2 ambient, the diffusion of Ge into Pr oxide is not observed in this sample. Pr-Pr bonds probably prevent the interfacial reaction and Ge oxide formation, considering that the oxygen chemical potential of this film is lower than that of a GeO2/Ge system. On the other hand, the rapid thermal oxidation (RTO) treatment terminates the O vacancies and defects in c-Pr2O3. As a result, c-PrO2 with tetravalent Pr is formed in the Pr oxide/PrON/Ge sample with RTO. In this sample, the leakage current density is effectively decreased in comparison with the sample without RTO. Hydrogen termination works effectively in Pr oxide/PrON/Ge samples with and without RTO, and we can achieve an interface state density of as low as 4 ×1011 eV-1·cm-2.

  3. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  4. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    NASA Astrophysics Data System (ADS)

    Niang, K. M.; Barquinha, P. M. C.; Martins, R. F. P.; Cobb, B.; Powell, M. J.; Flewitt, A. J.

    2016-02-01

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 107 s-1. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.

  5. GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

    NASA Astrophysics Data System (ADS)

    Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

    2015-04-01

    GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

  6. Polarity dependent thermochemical E-model for describing time dependent dielectric breakdown in metal-oxide-semiconductor devices with hyper-thin gate dielectrics

    NASA Astrophysics Data System (ADS)

    McPherson, J. W.

    2016-09-01

    The Lorentz factor L, which is used for describing the local electric fields in hyper-thin (<3.0 nm) gate dielectrics, is found to be polarity dependent for an inversion and accumulation-mode testing of Metal-Oxide-Semiconductor Field Effect Transistors. L is strongly impacted by the dipole layers that are induced in the depletion regions in the poly and silicon-substrate electrodes. While time dependent dielectric breakdown (TDDB) results are much improved with the inversion-mode testing, the reason for this is due to a smaller Lorentz factor (thus smaller Eloc). In fact, when compared at the same local electric field Eloc, there is no difference in TDDB between the inversion and accumulation mode testing. Thus, when properly corrected for the depletion effects in the MOS electrodes, the Thermochemical E-Model becomes polarity dependent and describes well both the inversion and accumulation-mode TDDB testing of the hyper-thin gate dielectrics.

  7. Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Dib, Elias; Bescond, Marc; Cavassilas, Nicolas; Michelini, Fabienne; Raymond, Laurent; Lannoo, Michel

    2013-08-01

    Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

  8. Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

    PubMed Central

    Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

    2011-01-01

    Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

  9. Oxidative stress in the in vivo DMBA rat model of breast cancer: suppression by a voltage-gated sodium channel inhibitor (RS100642).

    PubMed

    Batcioglu, Kadir; Uyumlu, A Burcin; Satilmis, Basri; Yildirim, Battal; Yucel, Neslihan; Demirtas, Hakan; Onkal, Rustem; Guzel, R Mine; Djamgoz, Mustafa B A

    2012-08-01

    Breast cancer (BCa) was induced in vivo in female rats with 7,12-dimethylbenz(a)anthracene (DMBA). Two main questions were addressed. Firstly, would the carcinogenesis be accompanied by oxidative stress as signalled by superoxide dismutase, glutathione peroxidase, malondialdehyde and total nitrate? Secondly, would treating the rats additionally with a blocker of voltage-gated sodium channel (VGSC) activity, shown previously to promote BCa progression, affect the oxidative responses? The DMBA-induced increases in the antioxidant systems were completely blocked by the VGSC inhibitor RS100642, which also significantly prolonged the lifespan. We conclude that VGSC inhibition in vivo can significantly protect against oxidative stress and improve survival from tumour burden. PMID:22429688

  10. Oxidation differentially modulates the recombinant voltage-gated Na(+) channel α-subunits Nav1.7 and Nav1.8.

    PubMed

    Schlüter, Friederike; Leffler, Andreas

    2016-10-01

    Voltage-gated Na(+) channels regulate neuronal excitability by generating the upstroke of action potentials. The α-subunits Nav1.7 and Nav1.8 are required for normal function of sensory neurons and thus for peripheral pain processing, but also for an increased excitability leading to an increased pain sensitivity under several conditions associated with oxidative stress. While little is known about the direct effects of oxidants on Nav1.7 and Nav1.8, a recent study on mouse dorsal root ganglion neurons suggested that oxidant-induced alterations of nociceptor excitability are primarily driven by Nav1.8. Here we performed whole-cell patch clamp recordings to explore how oxidation modulates functional properties of recombinant Nav1.7 and Nav1.8 channels. The strong oxidant chloramine-T (ChT) at 100 and 500µM induced a shift of the voltage-dependency of activation towards more hyperpolarized potentials. While fast inactivation was stabilized by 100µM ChT, it was partially removed by 500µM ChT on both α-subunits (Nav1.7oxidation promotes gating of Nav1.7 and Nav1.8 by reducing the threshold for activation and by abrogating fast inactivation. The resulting persistent currents are regulated by slow inactivation and appear to be more prominent for Nav1.8 as compared to Nav1.7. PMID:27450927

  11. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    NASA Astrophysics Data System (ADS)

    Liu, Hsi-Wen; Chang, Ting-Chang; Tsai, Jyun-Yu; Chen, Ching-En; Liu, Kuan-Ju; Lu, Ying-Hsin; Lin, Chien-Yu; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  12. 1.5-nm-thick silicon oxide gate films grown at 150 deg. C using modified reactive ion beam deposition with pyrolytic-gas passivation

    SciTech Connect

    Yamada, Hiroshi

    2007-03-15

    Low-temperature ultrathin silicon oxide gate film growth using modified reactive ion beam deposition (RIBD) with an in situ pyrolytic-gas passivation (PGP) method is described. RIBD uses low-energy-controlled reactive and ionized species and potentializes low-temperature film growth. By combining RIBD with PGP using N{sub 2}O and NF{sub 3}, 1.5-nm-thick silicon oxide gate films with high-potential barrier height energy, 3.51 eV, and low-leakage current, less than about 10{sup -5} A/cm{sup 2} at 2 MV/cm, can be obtained at a growth temperature of 150 deg. C. From an evaluation of number densities of N, F, and O atoms near the 1.5-5.0-nm-thick RIBD-with-PGP silicon oxide films/Si(100) interfaces, it is believed that interfacial N and F atoms contribute to improve the electrical characteristics and F effectively compensates the residual inconsistent-state bonding sites after the N passivation.

  13. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect

    Roy, Sukhdev Yadav, Chandresh

    2013-12-09

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  14. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  15. Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

    NASA Astrophysics Data System (ADS)

    Lim, Ji-Song; Yang, Xiaodong; Nishida, Toshikazu; Thompson, Scott E.

    2006-08-01

    An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

  16. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  17. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-01

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  18. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics

    SciTech Connect

    Samanta, Piyas; Huang, Heng-Sheng; Chen, Shuang-Yuan; Liu, Chuan-Hsi; Cheng, Li-Wei

    2014-02-21

    We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3} ≡ SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ΔN{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ΔN{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

  19. 20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING WEST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  20. 17. DETAIL VIEW OF TAINTER GATE, SHOWING GATE, GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF TAINTER GATE, SHOWING GATE, GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 6, Trempealeau, Trempealeau County, WI

  1. 17. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS, GATE CHAINS AND SWITCHES, AND BRIDGE GIRDERS, LOOKING SOUTHWEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  2. 18. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS, GATE CHAINS AND SWITCHES, AND BRIDGE GIRDERS, LOOKING NORTHWEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  3. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  4. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  5. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  6. GaN quantum-dots integrated in the gate dielectric of metal-oxide-semiconductor structures for charge-storage applications

    NASA Astrophysics Data System (ADS)

    Dimitrakis, P.; Normand, P.; Bonafos, C.; Papadomanolaki, E.; Iliopoulos, E.

    2013-02-01

    Gallium nitride quantum dots (QDs) were investigated as discrete charge storage nodes embedded in the gate dielectric of metal-oxide-semiconductor (MOS) capacitors. The GaN QDs were formed on top of 3.5 nm-thick SiO2/n-Si(001) substrates by radiofrequency plasma-assisted molecular beam deposition. The MOS structures were studied by transmission electron microscopy. Deposition dose was determined as a critical process parameter to obtain two dimensional arrays of discrete QDs. The memory window width, programming speed, and charge retention time were evaluated for GaN QD devices with different deposition doses. All devices showed enhanced electron trapping leading to significant memory windows. Charge retention measurements, at room temperature, revealed that the sample with the lowest concentration of QDs exhibits a low charge loss with a significant extrapolated programming window after 10 yrs. The present study not only demonstrates GaN QD embedded SiO2 structures fabricated by a fully complementary metal oxide semiconductor compatible method but also points out that these structures are promising for the realization of nanofloating gate non-volatile memory devices.

  7. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  8. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments.

  9. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments. PMID:25656265

  10. Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

    NASA Astrophysics Data System (ADS)

    Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

    2007-12-01

    We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

  11. Resonant gate driver with efficient gate energy recovery and switching loss reduction

    NASA Astrophysics Data System (ADS)

    Kim, I.-G.; Kwak, S.-S.

    2016-04-01

    This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV2 gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.

  12. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Tari, Alireza; Lee, Czang-Ho; Wong, William S.

    2015-07-01

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO2, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiNx, and (3) a PECVD SiOx/SiNx dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the Vo concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiNx (high Vo) and SiO2 (low Vo) had the highest and lowest conductivity, respectively. A PECVD SiOx/SiNx dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  13. Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal-Oxide-Semiconductor Technology

    NASA Astrophysics Data System (ADS)

    Han, Jin-Ping; Shimizu, Takashi; Pan, Li-Hong; Voelker, Moritz; Bernicot, Christophe; Arnaud, Franck; Mocuta, Anda; Stahrenberg, Knut; Azuma, Atsushi; Eller, Manfred; Yang, Guoyong; Jaeger, Daniel; Zhuang, Haoren; Miyashita, Katsura; Stein, Kenneth; Nair, Deleep; Hoo Park, Jae; Kohler, Sabrina; Hamaguchi, Masafumi; Li, Weipeng; Kim, Kisang; Chanemougame, Daniel; Kim, Nam Sung; Uchimura, Sadaharu; Tsutsui, Gen; Wiedholz, Christian; Miyake, Shinich; van Meer, Hans; Liang, Jewel; Ostermayr, Martin; Lian, Jenny; Celik, Muhsin; Donaton, Ricardo; Barla, Kathy; Na, MyungHee; Goto, Yoshiro; Sherony, Melanie; Johnson, Frank S.; Wachnik, Richard; Sudijono, John; Kaste, Ed; Sampson, Ron; Ku, Ja-Hum; Steegen, An; Neumueller, Walter

    2011-04-01

    High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance Gm, conductance Gds, Gm/Id, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., Ion-Ioff, Ioff-Vtsat, DIBL, Cjswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

  14. Characterization of ALD Beryllium Oxide as a Potential High- k Gate Dielectric for Low-Leakage AlGaN/GaN MOSHEMTs

    NASA Astrophysics Data System (ADS)

    Johnson, Derek W.; Yum, Jung Hwan; Hudnall, Todd W.; Mushinski, Ryan M.; Bielawski, Christopher W.; Roberts, John C.; Wang, Wei-E.; Banerjee, Sanjay K.; Harris, H. Rusty

    2014-01-01

    The chemical and electrical characteristics of atomic layer deposited (ALD) beryllium oxide (BeO) on GaN were studied via x-ray photoelectron spectroscopy, current-voltage, and capacitance-voltage measurements and compared with those of ALD Al2O3 and HfO2 on GaN. Radiofrequency (RF) and power electronics based on AlGaN/GaN high-electron-mobility transistors are maturing rapidly, but leakage current reduction and interface defect ( D it) minimization remain heavily researched. BeO has received recent attention as a high- k gate dielectric due to its large band gap (10.6 eV) and thermal stability on InGaAs and Si, but little is known about its performance on GaN. Unintentionally doped GaN was cleaned in dilute aqueous HCl immediately prior to BeO deposition (using diethylberyllium and H2O precursors). Formation of an interfacial layer was observed in as-deposited samples, similar to the layer formed during ALD HfO2 deposition on GaN. Postdeposition anneal (PDA) at 700°C and 900°C had little effect on the observed BeO binding state, confirming the strength of the bond, but led to increased Ga oxide formation, indicating the presence of unincorporated oxygen in the dielectric. Despite the interfacial layer, gate leakage current of 1.1 × 10-7 A/cm2 was realized, confirming the potential of ALD BeO for use in low-leakage AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors.

  15. Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

    NASA Astrophysics Data System (ADS)

    Lai, Kafai; Hao, Ming-Yin; Chen, Wei-Ming; Lee, Jack C.

    1994-09-01

    A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

  16. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  17. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  18. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    PubMed Central

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  19. Properties of c-axis-aligned crystalline indium-gallium-zinc oxide field-effect transistors fabricated through a tapered-trench gate process

    NASA Astrophysics Data System (ADS)

    Asami, Yoshinobu; Kurata, Motomu; Okazaki, Yutaka; Higa, Eiji; Matsubayashi, Daisuke; Okamoto, Satoru; Sasagawa, Shinya; Moriwaka, Tomoaki; Kakehata, Tetsuya; Yakubo, Yuto; Kato, Kiyoshi; Hamada, Takashi; Sakakura, Masayuki; Hayakawa, Masahiko; Yamazaki, Shunpei

    2016-04-01

    To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (\\text{In}:\\text{Ga}:\\text{Zn} = 1:1:1 in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10-16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

  20. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect

    Yang, Xu; Zeng, Zhen-Hua; Wang, Sheng-Kai E-mail: xzhang62@aliyun.com Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang E-mail: xzhang62@aliyun.com; Zhang, Xiong E-mail: xzhang62@aliyun.com

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  1. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    NASA Astrophysics Data System (ADS)

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-09-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement.

  2. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating.

    PubMed

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Tan, Leng Seow

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  3. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  4. Self-correction of field-effect transistor characteristics in the mode of spontaneous space-charge ion polarization of gate oxide

    SciTech Connect

    Zhdan, A. G.; Naryshkina, V. G.; Chucheva, G. V.

    2009-05-15

    Spontaneous space-charge ion polarization of gate oxide in the inversion n-channel silicon field-effect transistor was accomplished in the mode of its Joule heating by the drain current I{sub d}. The transistor characteristics measured at room temperature (T{sub r}) before and after thermal-field treatment show that positive ion (Na{sup +}) localization near the SiO{sub 2}/Si interface is accompanied by an increase in the effective electron mobility (by a factor of {approx} 2.3), steepness, I{sub d}, and by a small decrease in the threshold voltage ({delta}V{sub th} = 0.58 V). At T = T{sub r}, the modified transistor characteristics are retained for months; they can be easily and predictably varied by changing I{sub d} and heating duration.

  5. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    SciTech Connect

    Tari, Alireza Lee, Czang-Ho; Wong, William S.

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  6. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  7. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  8. Towards a reliable and high sensitivity O₂-independent glucose sensor based on Ir oxide nanoparticles.

    PubMed

    Campbell, H B; Elzanowska, H; Birss, V I

    2013-04-15

    The primary goal of this work is the development of a rapidly responding, sensitive, and biocompatible Ir oxide (IrOx)-based glucose sensor that regenerates solely via IrOx-mediation in both O₂-free and aerobic environments. An important discovery is that, for films composed of IrOx nanoparticles, Nafion® and glucose oxidase (GOx), a Michaelis-Menten constant (K'(m)) of 20-30 mM is obtained in the case of dual-regeneration (O₂ and IrOx), while K'(m) values are much smaller (3-5 mM) when re-oxidation of GOx occurs only through IrOx-mediation. These smaller K'(m) values indicate that the regeneration of GOx via direct electron transfer to the IrOx nanoparticles is more rapid than to O₂. Small K'(m) values, which are obtained more commonly when Nafion® is not present in the films, are also important for the accurate measurement of low glucose concentrations under hypoglycemic conditions. In this work, the sensing film was also optimized for miniaturization. Depending on the IrOx and GOx surface loadings and the use of sonication before film deposition, the i(max) values ranged from 5 to 225 μA cm⁻², showing very good sensitivity down to 0.4 mM glucose. PMID:23261690

  9. Designing interlayers to improve the mechanical reliability of transparent conductive oxide coatings on flexible substrates

    NASA Astrophysics Data System (ADS)

    Kim, Eun-Hye; Yang, Chan-Woo; Park, Jin-Woo

    2012-05-01

    In this study, we investigate the effect of interlayers on the mechanical properties of transparent conductive oxide (TCO) on flexible polymer substrates. Indium tin oxide (ITO), which is the most widely used TCO film, and Ti, which is the most widely used adhesive interlayer, are selected as the coating and the interlayer, respectively. These films are deposited on the polymer substrates using dc-magnetron sputtering to achieve varying thicknesses. The changes in the following critical factors for film cracking and delamination are analyzed: the internal stress (σi) induced in the coatings during deposition using a white light interferometer, the crystallinity using a transmission electron microscope, and the surface roughness of ITO caused by the interlayer using an atomic force microscope. The resistances to the cracking and delamination of ITO are evaluated using a fragmentation test. Our tests and analyses reveal the important role of the interlayers, which significantly reduce the compressive σi that is induced in the ITO and increase the resistance to the buckling delamination of the ITO. However, the relaxation of σi is not beneficial to cracking because there is less compensation for the external tension as σi further decreases. Based on these results, the microstructural control is revealed as a more influential factor than σi for improving crack resistance.

  10. Retention and Switching Kinetics of Protonated Gate Field Effect Transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-06-27

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETs containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96% after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  11. Retention and switching kinetics of protonated gate field effect transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-05-23

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETS containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96{percent} after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  12. Automatically closing swing gate closure assembly

    DOEpatents

    Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

    1988-01-01

    A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

  13. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    SciTech Connect

    Flewitt, A. J.; Powell, M. J.

    2014-04-07

    It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65–0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10{sup 6}−10{sup 7} s{sup −1}, which suggests a weak localization of carriers in band tail states over a 20–40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage

  14. Electrical Characteristics of Metal-Oxide-Semiconductor Capacitor with High-κ/Metal Gate Using Oxygen Scavenging Process.

    PubMed

    Lee, Junil; Kim, Jang Hyun; Kwon, Dae Woong; Park, Euyhwan; Park, Taehyung; Kim, Hyun Woo; Park, Byung-gook

    2016-05-01

    It has been widely accepted that the mismatch of lattice constants between HfO2 and Si generates interface traps at the HfO2-Si interface, which causes the degradation of device performances. For better interface quality, very thin SiO2 film (< 2 nm) has been inserted as an interlayer (IL) between HfO2 and Si despite of the increase of EOT. In order to obtain both the better interface quality and the reduction of EOT, we used Ti metal on HfO2/IL SiO2 stack as a scavenging layer to absorb oxygens in the SiO2 and various annealing conditions were applied to optimize the thickness of the SiO2. As a result, we can effectively shrink the EOT from 3.55 nm to 1.15 nm while maintaining the same physical thickness of gate stacks. Furthermore, the diffusion of oxygen was confirmed by high resolution transmission electron microscopy (HRTEM) and time-of-flight secondary ion mass Spectrometry (SIMS). PMID:27483842

  15. Gate dielectric scaling in MOSFETs device

    NASA Astrophysics Data System (ADS)

    Jing, K. Hui; Arshad, M. K. Md.; Huda, A. R. N.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Fathil, M. F. M.; Othman, Noraini; Hashim, U.

    2016-07-01

    Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a basic type of transistor to be used as a switch since 1959. Since then, the successful of MOSFET is due to good properties between silicon and silicon dioxide. The reduction of silicon oxide thickness provide further enhancement in device performance. At 90 and 65 nm technology nodes, the gate oxide could not be scaled anymore due to the direct tunneling effect resulting significant increase of leakage current. At 45 nm the high-k + metal gate has been introduced. Recently, the ferroelectric effect material is introduced which significantly reduce the gate leakage current. This paper review the evolution of gate dielectric scaling from the era of silicon dioxide to high-k + metal gate and ferroelectric effect material.

  16. Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

    SciTech Connect

    Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars

    2013-12-04

    We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

  17. Schottky source/drain germanium-based metal-oxide-semiconductor field-effect transistors with self-aligned NiGe/Ge junction and aggressively scaled high-k gate stack

    NASA Astrophysics Data System (ADS)

    Hosoi, Takuji; Minoura, Yuya; Asahara, Ryohei; Oka, Hiroshi; Shimura, Takayoshi; Watanabe, Heiji

    2015-12-01

    Schottky source/drain (S/D) Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated by combining high permittivity (high-k) gate stacks with ultrathin AlOx interlayers and Fermi level depinning process by means of phosphorous ion implantation into NiGe/Ge contacts. Improved thermal stability of the metal/high-k/Ge stacks enabled self-aligned integration scheme for Schottky S/D complementary MOS applications. Significantly reduced parasitic resistance and aggressively scaled high-k gate stacks with sub-1-nm equivalent oxide thickness were demonstrated for both p- and n-channel Schottky Ge-FETs with the proposed combined technology.

  18. Prediction of Reliable Metal-PH₃ Bond Energies for Ni, Pd, and Pt in the 0 and +2 Oxidation States

    SciTech Connect

    Craciun, Raluca; Vincent, Andrew J.; Shaughnessy, Kevin H.; Dixon, David A.

    2010-06-21

    Phosphine-based catalysts play an important role in many metal-catalyzed carbon-carbon bond formation reactions yet reliable values of their bond energies are not available. We have been studying homogeneous catalysts consisting of a phosphine bonded to a Pt, Pd, or Ni. High level electronic structure calculations at the CCSD(T)/complete basis set level were used to predict the M-PH₃ bond energy (BE) for the 0 and +2 oxidation states for M=Ni, Pd, and Pt. The calculated bond energies can then be used, for example, in the design of new catalyst systems. A wide range of exchange-correlation functionals were also evaluated to assess the performance of density functional theory (DFT) for these important bond energies. None of the DFT functionals were able to predict all of the M-PH3 bond energies to within 5 kcal/mol, and the best functionals were generalized gradient approximation functionals in contrast to the usual hybrid functionals often employed for main group thermochemistry.

  19. Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

    SciTech Connect

    Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng; Lin, Chia-Chun

    2014-11-17

    Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. With a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.

  20. Reconfigurable Ion Gating of 2H-MoTe2 Field-Effect Transistors Using Poly(ethylene oxide)-CsClO4 Solid Polymer Electrolyte.

    PubMed

    Xu, Huilong; Fathipour, Sara; Kinder, Erich W; Seabaugh, Alan C; Fullerton-Shirey, Susan K

    2015-05-26

    Transition metal dichalcogenides are relevant for electronic devices owing to their sizable band gaps and absence of dangling bonds on their surfaces. For device development, a controllable method for doping these materials is essential. In this paper, we demonstrate an electrostatic gating method using a solid polymer electrolyte, poly(ethylene oxide) and CsClO4, on exfoliated, multilayer 2H-MoTe2. The electrolyte enables the device to be efficiently reconfigured between n- and p-channel operation with ON/OFF ratios of approximately 5 decades. Sheet carrier densities as high as 1.6 × 10(13) cm(-2) can be achieved because of a large electric double layer capacitance (measured as 4 μF/cm(2)). Further, we show that an in-plane electric field can be used to establish a cation/anion transition region between source and drain, forming a p-n junction in the 2H-MoTe2 channel. This junction is locked in place by decreasing the temperature of the device below the glass transition temperature of the electrolyte. The ideality factor of the p-n junction is 2.3, suggesting that the junction is recombination dominated. PMID:25877681

  1. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    NASA Astrophysics Data System (ADS)

    Wang, A. L.; Gold, J. M.; Tompkins, N.; Heymann, M.; Harrington, K. I.; Fraden, S.

    2016-02-01

    We investigate the Belousov-Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment.

  2. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    PubMed Central

    Wang, A.L.; Gold, J.M.; Tompkins, N.; Heymann, M.; Harrington, K.I.; Fraden, S.

    2016-01-01

    We investigate the Belousov–Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment. PMID:27168916

  3. On the applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells

    SciTech Connect

    Lara-Curzio, Edgar; Radovic, Miladin; Luttrell, Claire R

    2016-01-01

    The applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells (SOFC) is investigated by measuring the failure rate of Ni-YSZ when subjected to a temperature gradient and comparing it with that predicted using the Ceramics Analysis and Reliability Evaluation of Structures (CARES) code. The use of a temperature gradient to induce stresses was chosen because temperature gradients resulting from gas flow patterns generate stresses during SOFC operation that are the likely to control the structural reliability of cell components The magnitude of the predicted failure rate was found to be comparable to that determined experimentally, which suggests that such probabilistic analyses are appropriate for predicting the structural reliability of materials and components for SOFCs. Considerations for performing more comprehensive studies are discussed.

  4. Materials reliability issues in microelectronics

    SciTech Connect

    Lloyd, J.R. ); Yost, F.G. ); Ho, P.S. )

    1991-01-01

    This book covers the proceedings of a MRS symposium on materials reliability in microelectronics. Topics include: electromigration; stress effects on reliability; stress and packaging; metallization; device, oxide and dielectric reliability; new investigative techniques; and corrosion.

  5. Effect of thin gate dielectrics and gate materials on simulated device characteristics of 3D double gate JNT

    NASA Astrophysics Data System (ADS)

    Baidya, A.; Krishnan, V.; Baishya, S.; Lenka, T. R.

    2015-01-01

    In this paper a novel Silicon based three dimensional (3D) double-gate Junctionless Nanowire Transistor (JNT) of 20 nm gate length is proposed. The device characteristics such as gate characteristics and drain characteristics are studied with the help of Sentaurus TCAD by using different gate materials such as Al, Ti, n+ Polysilicon, Au and using different ultra thin gate dielectrics such as SiO2, Si3N4 and HfO2. The effect of various work functions and dielectrics on the threshold voltage of the JNT is also analysed. From the TCAD simulation results it is observed that high-K material (HfO2) as gate dielectric shows better drain characteristics with respect to others. The JNT with Al as gate material gives better current characteristics with respect to others. It is also analysed that under flat-band condition the driving of drain current does not directly depend on the gate-oxide capacitance but depends upon the channel doping concentrations. Thus by choosing the proper gate material and gate dielectric combinations, the desired device characteristics could be obtained for JNT.

  6. FLOW GATING

    DOEpatents

    Poppelbaum, W.J.

    1962-12-01

    BS>This invention is a fast gating system for eiectronic flipflop circuits. Diodes connect the output of one circuit to the input of another, and the voltage supply for the receiving flip-flop has two alternate levels. When the supply is at its upper level, no current can flow through the diodes, but when the supply is at its lower level, current can flow to set the receiving flip- flop to the same state as that of the circuit to which it is connected. (AEC)

  7. Effect of Oxidation Temperature on Physical and Electrical Properties of Sm2O3 Thin-Film Gate Oxide on Si Substrate

    NASA Astrophysics Data System (ADS)

    Goh, Kian Heng; Haseeb, A. S. M. A.; Wong, Yew Hoong

    2016-06-01

    Thermal oxidation of 150-nm sputtered pure samarium metal film on silicon substrate has been carried out in oxygen ambient at various temperatures (600°C to 900°C) for 15 min and the effect of the oxidation temperature on the structural, chemical, and electrical properties of the resulting Sm2O3 layers investigated. The crystallinity of the Sm2O3 films and the existence of an interfacial layer were evaluated by x-ray diffraction (XRD) analysis, Fourier-transform infrared (FTIR) spectroscopy, and Raman analysis. The crystallite size and microstrain of Sm2O3 were estimated by Williamson-Hall (W-H) plot analysis, with comparison of the former with the crystallite size of Sm2O3 as calculated using the Scherrer equation. High-resolution transmission electron microscopy (HRTEM) with energy-dispersive x-ray (EDX) spectroscopy analysis was carried out to investigate the cross-sectional morphology and chemical distribution of selected regions. The activation energy or growth rate of each stacked layer was calculated from Arrhenius plots. The surface roughness and topography of the Sm2O3 layers were examined by atomic force microscopy (AFM) analysis. A physical model based on semipolycrystalline nature of the interfacial layer is suggested and explained. Results supporting such a model were obtained by FTIR, XRD, Raman, EDX, and HRTEM analyses. Electrical characterization revealed that oxidation temperature at 700°C yielded the highest breakdown voltage, lowest leakage current density, and highest barrier height value.

  8. Effect of Oxidation Temperature on Physical and Electrical Properties of Sm2O3 Thin-Film Gate Oxide on Si Substrate

    NASA Astrophysics Data System (ADS)

    Goh, Kian Heng; Haseeb, A. S. M. A.; Wong, Yew Hoong

    2016-10-01

    Thermal oxidation of 150-nm sputtered pure samarium metal film on silicon substrate has been carried out in oxygen ambient at various temperatures (600°C to 900°C) for 15 min and the effect of the oxidation temperature on the structural, chemical, and electrical properties of the resulting Sm2O3 layers investigated. The crystallinity of the Sm2O3 films and the existence of an interfacial layer were evaluated by x-ray diffraction (XRD) analysis, Fourier-transform infrared (FTIR) spectroscopy, and Raman analysis. The crystallite size and microstrain of Sm2O3 were estimated by Williamson-Hall (W-H) plot analysis, with comparison of the former with the crystallite size of Sm2O3 as calculated using the Scherrer equation. High-resolution transmission electron microscopy (HRTEM) with energy-dispersive x-ray (EDX) spectroscopy analysis was carried out to investigate the cross-sectional morphology and chemical distribution of selected regions. The activation energy or growth rate of each stacked layer was calculated from Arrhenius plots. The surface roughness and topography of the Sm2O3 layers were examined by atomic force microscopy (AFM) analysis. A physical model based on semipolycrystalline nature of the interfacial layer is suggested and explained. Results supporting such a model were obtained by FTIR, XRD, Raman, EDX, and HRTEM analyses. Electrical characterization revealed that oxidation temperature at 700°C yielded the highest breakdown voltage, lowest leakage current density, and highest barrier height value.

  9. Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor.

    PubMed

    Cho, Jun Hee; Lee, Sang-Ick; Kim, Jong Hyun; Yim, Sang Jun; Shin, Hyung Soo; Han, Mi Jeong; Chae, Won Mook; Lee, Sung Duck; Ahn, Chi Young; Kim, Myong-Woon

    2015-01-01

    Zirconium based thin film have been deposited by atomic layer deposition (ALD) process using Zr and Si containing Zr precursor with ozone as oxidant. We have pursued a means to control composition by varying Zr and Si containing precursor by cycle frequency. The molar ratio of Si to Zr in the Zr based films was 0.2, 0.25, 0.33, and 0.5. Addition of Si containing Zr precursor on Zirconium based thin films was effective for the decrease of the roughness, while an increase of density. XPS analysis indicated that the addition of Si containing Zr precursors in the Zr based film formed the silicate structure. The XRD analysis of the all ZrO2-SiO2 mixed films annealed at 600 degrees C for 5 min indicated the presence of amorphous. However, the ZrO2 film showed diffraction peaks at 2θ = 30.6 degrees due to the presence of the Tetragonal ZrO2. The incorporation of Si into ZrO2 films helps stabilize an amorphous structure during deposition and annealing. The Zr based thin film (Si/Zr = 0.25) exhibited that the leakage current density was 6.2 x 10(-7) A/cm2 at a bias of - 1.5 V. PMID:26328365

  10. Electrical characterization of the metal ferroelectric oxide semiconductor and metal ferroelectric nitride semiconductor gate stacks for ferroelectric field effect transistors

    NASA Astrophysics Data System (ADS)

    Verma, Ram Mohan; Rao, Ashwath; Singh, B. R.

    2014-03-01

    This paper presents our work on electrical characterization of metal-ferroelectric-oxide-semiconductor (MFeOS) and metal-ferroelectric-nitride-semiconductor (MFeNS) structures for nonvolatile memory applications. Thin films of lead zirconate titanate (PZT: 35:65) have been used as ferroelectric material on 2.5-5 nm thick thermally grown SiO2 and Si3N4 as buffer layer for MFeOS and MFeNS structures, respectively. Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were used for electrical characterization. Our comparative results reveal that the MFeNS structure with 2.5 nm thick buffer layer has higher memory window of about 3.6 V as compared to 3 V for similar MFeOS structure. Also superior electrical properties such as lower leakage current and higher dielectric strength were observed in MFeNS structures. Higher nitridation time was observed to deteriorate the polarization characteristics resulting in reduced memory window. The highest memory window of 6.5 V was observed for SiO2 buffer layer thickness of 5 nm. We also observed that the annealing temperature influences the leakage current characteristic and memory window of these structures.

  11. Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor.

    PubMed

    Cho, Jun Hee; Lee, Sang-Ick; Kim, Jong Hyun; Yim, Sang Jun; Shin, Hyung Soo; Han, Mi Jeong; Chae, Won Mook; Lee, Sung Duck; Ahn, Chi Young; Kim, Myong-Woon

    2015-01-01

    Zirconium based thin film have been deposited by atomic layer deposition (ALD) process using Zr and Si containing Zr precursor with ozone as oxidant. We have pursued a means to control composition by varying Zr and Si containing precursor by cycle frequency. The molar ratio of Si to Zr in the Zr based films was 0.2, 0.25, 0.33, and 0.5. Addition of Si containing Zr precursor on Zirconium based thin films was effective for the decrease of the roughness, while an increase of density. XPS analysis indicated that the addition of Si containing Zr precursors in the Zr based film formed the silicate structure. The XRD analysis of the all ZrO2-SiO2 mixed films annealed at 600 degrees C for 5 min indicated the presence of amorphous. However, the ZrO2 film showed diffraction peaks at 2θ = 30.6 degrees due to the presence of the Tetragonal ZrO2. The incorporation of Si into ZrO2 films helps stabilize an amorphous structure during deposition and annealing. The Zr based thin film (Si/Zr = 0.25) exhibited that the leakage current density was 6.2 x 10(-7) A/cm2 at a bias of - 1.5 V.

  12. Evolution of the gate current in 32 nm MOSFETs under irradiation

    NASA Astrophysics Data System (ADS)

    Palumbo, F.; Debray, M.; Vega, N.; Quinteros, C.; Kalstein, A.; Guarin, F.

    2016-05-01

    Radiation induced currents on single 32 nm MOSFET transistors have been studied using consecutive runs of 16O at 25 MeV. The main feature is the generation of current peaks - in the gate and channel currents - due to the collection of the electro-hole pairs generated by the incident radiation runs. It has been observed that the incident ions cause damage in the dielectric layer and in the substrate affecting the collection of carriers, and hence the radiation-induced current peaks. It has been find out a decrease of the current peak due to the increase of the series resistance by non-ionizing energy loss in the semiconductor substrate, and an increase of the leakage current due to defects in the gate oxide by ionizing energy loss. For low levels of damage in the gate oxide, the main feature is the shift of the VTH. Hot carriers heated by the incident radiation in the depletion region and injected in the gate oxide cause the change of the VTH due to electron or hole trapping for n- or p-channel respectively. The overall results illustrate that these effects must be taken into consideration for an accurate reliability projection.

  13. [The reliability of reliability].

    PubMed

    Blancas Espejo, A

    1991-01-01

    The author critically analyzes an article by Rodolfo Corona Vazquez that questions the reliability of the preliminary results of the Eleventh Census of Population and Housing, conducted in Mexico in March 1990. The need to define what constitutes "reliability" for preliminary results is stressed. PMID:12317739

  14. Sliding-gate valve for use with abrasive materials

    DOEpatents

    Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

    1985-01-01

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  15. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  16. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    SciTech Connect

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-10-06

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  17. A pH sensor with a double-gate silicon nanowire field-effect transistor

    NASA Astrophysics Data System (ADS)

    Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

    2013-02-01

    A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

  18. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  19. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  20. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section...

  1. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  2. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section...

  3. Electrical properties of GaAs metal-oxide-semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal-organic vapor deposition/atomic layer deposition hybrid system

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2015-08-01

    This paper presents a compressive study on the fabrication and optimization of GaAs metal-oxide-semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal-organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance-voltage (C-V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm-2 eV-1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  4. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    PubMed Central

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

  5. Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system.

    PubMed

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M; Avila-García, Alejandro; Vazquez-Acosta, E N; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe(2)O(3) layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  6. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  7. Oxide Charge Engineering of Atomic Layer Deposited AlOxNy/Al2O3 Gate Dielectrics: A Path to Enhancement Mode GaN Devices.

    PubMed

    Negara, M A; Kitano, M; Long, R D; McIntyre, P C

    2016-08-17

    Nitrogen incorporation to produce negative fixed charge in Al2O3 gate insulator layers is investigated as a path to achieve enhancement mode GaN device operation. A uniform distribution of nitrogen across the resulting AlOxNy films is obtained using N2 plasma enhanced atomic layer deposition (ALD). The flat band voltage (Vfb) increases to a significantly more positive value with increasing nitrogen concentration. Insertion of a 2 nm thick Al2O3 interlayer greatly decreases the trap density of the insulator/GaN interface, and reduces the voltage hysteresis and frequency dispersion of gate capacitance compared to single-layer AlOxNy gate insulators in GaN MOSCAPs.

  8. Oxide Charge Engineering of Atomic Layer Deposited AlOxNy/Al2O3 Gate Dielectrics: A Path to Enhancement Mode GaN Devices.

    PubMed

    Negara, M A; Kitano, M; Long, R D; McIntyre, P C

    2016-08-17

    Nitrogen incorporation to produce negative fixed charge in Al2O3 gate insulator layers is investigated as a path to achieve enhancement mode GaN device operation. A uniform distribution of nitrogen across the resulting AlOxNy films is obtained using N2 plasma enhanced atomic layer deposition (ALD). The flat band voltage (Vfb) increases to a significantly more positive value with increasing nitrogen concentration. Insertion of a 2 nm thick Al2O3 interlayer greatly decreases the trap density of the insulator/GaN interface, and reduces the voltage hysteresis and frequency dispersion of gate capacitance compared to single-layer AlOxNy gate insulators in GaN MOSCAPs. PMID:27459343

  9. Polymer electrolyte gating of carbon nanotube network transistors.

    PubMed

    Ozel, Taner; Gaur, Anshu; Rogers, John A; Shim, Moonsub

    2005-05-01

    Network behavior in single-walled carbon nanotubes (SWNTs) is examined by polymer electrolyte gating. High gate efficiencies, low voltage operation, and the absence of hysteresis in polymer electrolyte gating lead to a convenient and effective method of analyzing transport in SWNT networks. Furthermore, the ability to control carrier type with chemical groups of the host polymer allows us to examine both electron and hole conduction. Comparison to back gate measurements is made on channel length scaling. Frequency measurements are also made giving an upper limit of approximately 300 Hz switching speed for poly(ethylene oxide)/LiClO(4) gated SWNT thin film transistors. PMID:15884892

  10. Influence of uniaxial strain in Si and Ge p-type double-gate metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Moussavou, Manel; Cavassilas, Nicolas; Dib, Elias; Bescond, Marc

    2015-09-01

    We theoretically investigate the impact of uniaxial strain in extremely thin Si and Ge p-type double-gate transistors. Quantum transport modeling is treated using a 6-band k.p Hamiltonian and the non-equilibrium Green's function formalism including phonon scattering. Based on this framework, we analyze the influence of strain on current characteristics considering different transport directions and gate lengths. Our results first confirm the superiority of Ge over Si in long devices (15 nm gate length) for which best electrical performances are obtained considering channels along <110 > with a uni-axial compressive strain. For this configuration, Si devices suffer from inter-subband coupling which generates a strong hole-phonon scattering. Material dominance is reversed for shorter devices (7 nm gate length) where the small effective masses of Ge deteriorate the off-regime of the nano-transistor regardless of strain and crystallographic options. Due to weaker hole-phonon-scattering, <100 > -Si devices with a tensile strain are interestingly found to be more competitive than their <110 > -compressive counterparts. These results show that Si is still the most relevant material to reach the ultimate nanometer scale. More importantly, the same tensile strain can be considered to boost performances of both p- and n-type planar transistors which would lead to a significant simplification of the technological strain manufacturing.

  11. Ferroelectric/Dielectric Double Gate Insulator Spin-Coated Using Barium Titanate Nanocrystals for an Indium Oxide Nanocrystal-Based Thin-Film Transistor.

    PubMed

    Pham, Hien Thu; Yang, Jin Ho; Lee, Don-Sung; Lee, Byoung Hun; Jeong, Hyun-Dam

    2016-03-23

    Barium titanate nanocrystals (BT NCs) were prepared under solvothermal conditions at 200 °C for 24 h. The shape of the BT NCs was tuned from nanodot to nanocube upon changing the polarity of the alcohol solvent, varying the nanosize in the range of 14-22 nm. Oleic acid-passivated NCs showed good solubility in a nonpolar solvent. The effect of size and shape of the BT NCs on the ferroelectric properties was also studied. The maximum polarization value of 7.2 μC/cm(2) was obtained for the BT-5 NC thin film. Dielectric measurements of the films showed comparable dielectric constant values of BT NCs over 1-100 kHz without significant loss. Furthermore, the bottom gate In2O3 NC thin film transistors exhibited outstanding device performance with a field-effect mobility of 11.1 cm(2) V(-1) s(-1) at a low applied gate voltage with BT-5 NC/SiO2 as the gate dielectric. The low-density trapped state was observed at the interface between the In2O3 NC semiconductor and the BT-5 NCs/SiO2 dielectric film. Furthermore, compensation of the applied gate field by an electric dipole-induced dipole field within the BT-5 NC film was also observed.

  12. Graphene gate electrode for MOS structure-based electronic devices.

    PubMed

    Park, Jong Kyung; Song, Seung Min; Mun, Jeong Hun; Cho, Byung Jin

    2011-12-14

    We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.

  13. 6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE WORK, AND GATE STOP FROM SOUTHEAST OF NORTHWEST ELEMENTS. - William Enston Home, Entrance Gate, 900 King Street, Charleston, Charleston County, SC

  14. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, GATE PIER, TRUNNION PIN AND GATE GAUGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  15. Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun; Bang, Tewook; Choi, Yang-Kyu; Park, Sang-Hee Ko; Choi, Kyung Cheol

    2016-05-01

    We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔVth) was 0 V even after a PBS time (tstress) of 3000 s under a gate voltage (VG) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔVth value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔVth values resulting from PBS quantitatively, the average oxide charge trap density (NT) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher NT resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of NT near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.

  16. Gate value with ceramic-coated base operates at high temperatures

    NASA Technical Reports Server (NTRS)

    Brass, A.

    1964-01-01

    A copper base insert coated with a layer of aluminum oxide ceramic prevents frictional binding between the gate and base surfaces of a gate valve which are subject to rapid sliding action and high temperatures.

  17. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  18. Parallelizable adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Nakago, Kosuke; Hajdušek, Michal; Nakayama, Shojun; Murao, Mio

    2015-12-01

    To investigate how a temporally ordered gate sequence can be parallelized in adiabatic implementations of quantum computation, we modify adiabatic gate teleportation, a model of quantum computation proposed by Bacon and Flammia [Phys. Rev. Lett. 103, 120504 (2009), 10.1103/PhysRevLett.103.120504], to a form deterministically simulating parallelized gate teleportation, which is achievable only by postselection. We introduce a twisted Heisenberg-type interaction Hamiltonian, a Heisenberg-type spin interaction where the coordinates of the second qubit are twisted according to a unitary gate. We develop parallelizable adiabatic gate teleportation (PAGT) where a sequence of unitary gates is performed in a single step of the adiabatic process. In PAGT, numeric calculations suggest the necessary time for the adiabatic evolution implementing a sequence of L unitary gates increases at most as O (L5) . However, we show that it has the interesting property that it can map the temporal order of gates to the spatial order of interactions specified by the final Hamiltonian. Using this property, we present a controlled-PAGT scheme to manipulate the order of gates by a control qubit. In the controlled-PAGT scheme, two differently ordered sequential unitary gates F G and G F are coherently performed depending on the state of a control qubit by simultaneously applying the twisted Heisenberg-type interaction Hamiltonians implementing unitary gates F and G . We investigate why the twisted Heisenberg-type interaction Hamiltonian allows PAGT. We show that the twisted Heisenberg-type interaction Hamiltonian has an ability to perform a transposed unitary gate by just modifying the space ordering of the final Hamiltonian implementing a unitary gate in adiabatic gate teleportation. The dynamics generated by the time-reversed Hamiltonian represented by the transposed unitary gate enables deterministic simulation of a postselected event of parallelized gate teleportation in adiabatic

  19. Quantum gate decomposition algorithms.

    SciTech Connect

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  20. A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices

    NASA Astrophysics Data System (ADS)

    Elahipanah, Hossein; Orouji, Ali A.

    2009-11-01

    For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

  1. Investigation of field induced trapping on floating gates

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1975-01-01

    The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

  2. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-01

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  3. Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, M.; Kim, H.; Phan, A.; Seidleck, C.; LaBel, K.; Pellish, J.; Campola, M.

    2015-01-01

    Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

  4. Gated strip proportional detector

    DOEpatents

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  5. Gated strip proportional detector

    DOEpatents

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  6. High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices

    NASA Astrophysics Data System (ADS)

    Chiu, Yu Sheng; Liao, Jen Ting; Lin, Yueh Chin; Chien Liu, Shin; Lin, Tai Ming; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-05-01

    High-κ cerium oxide (CeO2) was applied to AlGaN/GaN high-electron-mobility transistors (HEMTs) as a gate insulator and a passivation layer by molecular beam deposition (MBD) for high-power applications. From capacitance-voltage (C-V) measurement results, the dielectric constant of the CeO2 film was 25.2. The C-V curves showed clear accumulation and depletion behaviors with a small hysteresis (20 mV). Moreover, the interface trap density (D it) was calculated to be 5.5 × 1011 eV-1 cm-2 at 150 °C. A CeO2 MOS-HEMT was fabricated and demonstrated a low subthreshold swing (SS) of 87 mV/decade, a high ON/OFF drain current ratio (I ON/I OFF) of 1.14 × 109, and a low gate leakage current density (J leakage) of 2.85 × 10-9 A cm-2 with an improved dynamic ON-resistance (R ON), which is about one order of magnitude lower than that of a conventional HEMT.

  7. High quality PECVD SiO2 process for recessed MOS-gate of AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Gil; Kim, Hyun-Seop; Seo, Kwang-Seok; Cho, Chun-Hyung; Cha, Ho-Young

    2016-08-01

    A high quality SiO2 deposition process using a plasma enhanced chemical vapor deposition system has been developed for the gate insulator process of normally-off recessed-gate AlGaN/GaN metal-oxide-semiconductor-heterostructure field-effect transistors (MOS-HFETs). SiO2 films were deposited by using SiH4 and N2O mixtures as reactant gases. The breakdown field increased with increasing the N2O flow rate. The optimum SiH4/N2O ratio was 0.05, which resulted in a maximum breakdown field of 11 MV/cm for the SiO2 film deposited on recessed GaN surface. The deposition conditions were optimized as follows; a gas flow rate of SiH4/N2O (=27/540 sccm), a source RF power of 100 W, a pressure of 2 Torr, and a deposition temperature of 350 °C. A fabricated normally-off MOS-HFET exhibited a threshold voltage of 3.2 V, a specific on-resistance of 4.46 mΩ cm2, and a breakdown voltage of 810 V.

  8. Gate-set tomography and beyond

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    Four years ago, there was no reliable way to characterize and debug quantum gates. Process tomography required perfectly pre-calibrated gates, while randomized benchmarking only yielded an overall error rate. Gate-set tomography (GST) emerged around 2012-13 in several variants (most notably at IBM; see PRA 87, 062119) to address this need, providing complete and calibration-free characterization of gates. At Sandia, we have pushed the capabilities of GST well beyond these initial goals. In this talk, I'll demonstrate our open web interface, show how we characterize gates with accuracy at the Heisenberg limit, discuss how we put error bars on the results, and present experimental GST estimates with 1e-5 error bars. I'll also present preliminary results of GST on 2-qubit gates, including a brief survey of the tricks we use to make it possible. I'll conclude with an analysis of GST's limitations (e.g., it scales poorly), and the techniques under development for characterizing and debugging larger (3+ qubit) systems.

  9. Confirming Pseudomonas putida as a reliable bioassay for demonstrating biocompatibility enhancement by solar photo-oxidative processes of a biorecalcitrant effluent.

    PubMed

    García-Ripoll, A; Amat, A M; Arques, A; Vicente, R; Ballesteros Martín, M M; Pérez, J A Sánchez; Oller, I; Malato, S

    2009-03-15

    Experiments based on Vibrio fischeri, activated sludge and Pseudomonas putida have been employed to check variation in the biocompatibility of an aqueous solution of a commercial pesticide, along solar photo-oxidative process (TiO(2) and Fenton reagent). Activated sludge-based experiments have demonstrated a complete detoxification of the solution, although important toxicity is still detected according to the more sensitive V. fischeri assays. In parallel, the biodegradability of organic matter is strongly enhanced, with BOD(5)/COD ratio above 0.8. Bioassays run with P. putida have given similar trends, remarking the convenience of using P. putida culture as a reliable and reproducible method for assessing both toxicity and biodegradability, as a substitute to other more time consuming methods.

  10. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory

    PubMed Central

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  11. 15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND GATE ARMS, PIERS AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  12. 4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE NO. 7 AND NON-SUBMERSIBLE TAINTER GATES, LOOKING WEST (UPSTREAM) - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

  13. 19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTH - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  14. 5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. DETAIL VIEW OF DAM, SHOWING TAINTER GATES, GATE PIERS AND DAN BRIDGE, WITH ROLLER GATE HEADHOUSES AND LOCKS IN BACKGROUND, LOOKING NORTHEAST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 4, Alma, Buffalo County, WI

  15. An enzyme-free and DNA-based Feynman gate for logically reversible operation.

    PubMed

    Zhou, Chunyang; Wang, Kun; Fan, Daoqing; Wu, Changtong; Liu, Dali; Liu, Yaqing; Wang, Erkang

    2015-06-28

    A logically reversible Feynman gate was successfully realized under enzyme-free conditions by integrating graphene oxide and DNA for the first time. The gate has a one-to-one mapping function to identify inputs from the corresponding outputs. This type of reversible logic gate may have great potential applications in information processing and biosensing systems.

  16. An enzyme-free and DNA-based Feynman gate for logically reversible operation.

    PubMed

    Zhou, Chunyang; Wang, Kun; Fan, Daoqing; Wu, Changtong; Liu, Dali; Liu, Yaqing; Wang, Erkang

    2015-06-28

    A logically reversible Feynman gate was successfully realized under enzyme-free conditions by integrating graphene oxide and DNA for the first time. The gate has a one-to-one mapping function to identify inputs from the corresponding outputs. This type of reversible logic gate may have great potential applications in information processing and biosensing systems. PMID:26028329

  17. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  18. Effect of F on B penetration through gate oxide for BF{sub 2} implants used to obtain ultra-shallow junctions by RTA

    SciTech Connect

    Sultan, A.; Craig, M.; Banerjee, S.

    1996-12-31

    We have studied enhancement of B penetration due to the presence of F, when BF{sub 2} implants are used for s/d extension implants in p{sup +} poly gate PMOS devices. A 0.35 {mu}m CMOS full flow is used to characterize the change in linear and saturation threshold voltage due to increased B penetration. The effect of F on other device characteristics is also examined. Contrary to previous concerns, it is found that the threshold voltage shift is quite small (18 mV) for the realistic conditions studied (2{times}10{sup 14} cm{sup -2} or BF{sub 2} dose). The presence of F does not degrade other electrical characteristics such as leakage current, sub-threshold slope or transconductance.

  19. Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects

    NASA Astrophysics Data System (ADS)

    Smaani, Billel; Latreche, Saida; Iñiguez, Benjamín

    2013-12-01

    In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

  20. Sliding-gate valve

    DOEpatents

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  1. Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

    NASA Astrophysics Data System (ADS)

    Sankar Medury, Aditya; Bhat, K. N.; Bhat, Navakanta

    2013-07-01

    In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50 K to 400 K) on the intrinsic carrier concentration (ni), electron concentration (n) and thereby on the threshold voltage (Vth) for thin silicon film (tsi = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (Vth) is defined as the gate voltage (Vg) at which the potential at the center of the channel (Φc) begins to saturate (Φc=Φc(sat)). It is shown that in the strong quantum confinement regime (tsi≤3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (ΔEg(eff)), intrinsic carrier concentration (ni), electron concentration (n), Φc(sat) and the threshold voltage (Vth). On the other hand, for tsi≥4 nm, it is shown that size quantization effects recede with increasing tsi, while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for Vth as a function of device temperature (T).

  2. Fractioned exhaled nitric oxide (FE(NO)) is not a sufficiently reliable test for monitoring asthma in pregnancy.

    PubMed

    Nittner-Marszalska, Marita; Liebhart, Jerzy; Pawłowicz, Robert; Kazimierczak, Anna; Marszalska, Hanna; Kraus-Filarska, Maria; Panaszek, Bernard; Dor-Wojnarowska, Anna

    2013-09-01

    It has been reported that fractioned exhaled nitric oxide (FENO) can be used for monitoring airway inflammation and for asthma management but conclusions drawn by different researchers are controversial. The aim of our study was to evaluate the clinical usefulness of FENO assessment for monitoring asthma during pregnancy. We monitored 72 pregnant asthmatics aged 18-38years (Me=29 years) who underwent monthly investigations including: the level of asthma control according to GINA (Global Initiative for Asthma), the occurrence of exacerbations, ACT (Asthma Control Test), as well as FENO and spirometry measurements. In 50 women, during all visits, asthma was well-controlled. In the remaining 22 women, asthma was periodically uncontrolled. FENO measured at the beginning of the study did not show significant correlation with retrospectively evaluated asthma severity (r=0.07; p=0.97). An analysis of data collected during all 254 visits showed that FENO correlated significantly but weakly with ACT scores (r=0.25; p=0.0004) and FEV1 (r=0.21; p=0.0014). FENO at consecutive visits in women with well-controlled asthma (N=50) showed large variability expressed by median coefficient of variation (CV)=32.0% (Min 2.4%, Max 121.9%). This concerned both: atopic and nonatopic groups (35.5%; and 26.7%, respectively). Large FENO variability (35.5%) was also found in a subgroup of women (N=11) with ACT=25 constantly throughout the study. FENO measured at visits when women temporarily lost control of asthma (N=22; 38 visits), showed an increasing tendency (64.2 ppb; 9.5 ppb-188.3 ppb), but did not differ significantly (p=0.13) from measurements taken at visits during which asthma was well-controlled (27.6 ppb; 6.2 ppb-103.4 ppb). The comparison of FENO in consecutive months of pregnancy in women who had well-controlled asthma did not show significant differences in FENO values during the time of observation. The assessment of asthma during pregnancy by means of monitoring FENO is of

  3. Control of Threshold Voltage for Top-Gated Ambipolar Field-Effect Transistor by Gate Buffer Layer.

    PubMed

    Khim, Dongyoon; Shin, Eul-Yong; Xu, Yong; Park, Won-Tae; Jin, Sung-Ho; Noh, Yong-Young

    2016-07-13

    The threshold voltage and onset voltage for p-channel and n-channel regimes of solution-processed ambipolar organic transistors with top-gate/bottom-contact (TG/BC) geometry were effectively tuned by gate buffer layers in between the gate electrode and the dielectric. The work function of a pristine Al gate electrode (-4.1 eV) was modified by cesium carbonate and vanadium oxide to -2.1 and -5.1 eV, respectively, which could control the flat-band voltage, leading to a remarkable shift of transfer curves in both negative and positive gate voltage directions without any side effects. One important feature is that the mobility of transistors is not very sensitive to the gate buffer layer. This method is simple but useful for electronic devices where the threshold voltage should be precisely controlled, such as ambipolar circuits, memory devices, and light-emitting device applications. PMID:27323003

  4. Improved Reading Gate For Vertical-Bloch-Line Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

  5. Adiabatically implementing quantum gates

    SciTech Connect

    Sun, Jie; Lu, Songfeng Liu, Fang

    2014-06-14

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  6. Gates Speaks to Librarians.

    ERIC Educational Resources Information Center

    St. Lifer, Evan

    1997-01-01

    In an interview, Microsoft CEO Bill Gates answers questions about the Gates Library Foundation; Libraries Online; tax-support for libraries; comparisons to Andrew Carnegie; charges of "buying" the library market; Internet filters, policies, and government censorship; the future of the World Wide Web and the role of librarians in its future.(PEN)

  7. Multi-gate synergic modulation in laterally coupled synaptic transistors

    NASA Astrophysics Data System (ADS)

    Zhu, Li Qiang; Xiao, Hui; Liu, Yang Hui; Wan, Chang Jin; Shi, Yi; Wan, Qing

    2015-10-01

    Laterally coupled oxide-based synaptic transistors with multiple gates are fabricated on phosphorosilicate glass electrolyte films. Electrical performance of the transistor can be evidently improved when the device is operated in a tri-gate synergic modulation mode. Excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked, and PPF index can be effectively tuned by the voltage applied on the modulatory terminal. At last, superlinear to sublinear synaptic integration regulation is also mimicked by applying a modulatory pulse on the third modulatory terminal. The multi-gate oxide-based synaptic transistors may find potential applications in biochemical sensors and neuromorphic systems.

  8. Optical NAND gate

    DOEpatents

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  9. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  10. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

    PubMed

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-17

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  11. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    PubMed Central

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-01-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs. PMID:26674338

  12. Inversion gate capacitance of undoped single-gate and double-gate field-effect transistor geometries in the extreme quantum limit

    SciTech Connect

    Majumdar, Amlan

    2015-05-28

    We present first-principle analytical derivations and numerically modeled data to show that the gate capacitance per unit gate area C{sub G} of extremely thin undoped-channel single-gate and double-gate field-effect transistor geometries in the extreme quantum limit with single-subband occupancy can be written as 1/C{sub G} = 1/C{sub OX} + N{sub G}/C{sub DOS} + N{sub G}/ηC{sub WF}, where N{sub G} is the number of gates, C{sub OX} is the oxide capacitance per unit area, C{sub DOS} is the density-of-states capacitance per unit area, C{sub WF} is the wave function spreading capacitance per unit area, and η is a constant on the order of 1.

  13. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARMS, GATE PIER AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  14. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARM, GATE PIER AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  15. Optical XOR gate

    DOEpatents

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  16. Optical NOR gate

    DOEpatents

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  17. Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

    NASA Astrophysics Data System (ADS)

    Kumar, Manoj; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

    2016-10-01

    The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/- LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

  18. Optimal simulation of Deutsch gates and the Fredkin gate

    NASA Astrophysics Data System (ADS)

    Yu, Nengkun; Ying, Mingsheng

    2015-03-01

    In this paper, we study the optimal simulation of the three-qubit unitary using two-qubit gates. First, we completely characterize the two-qubit gate cost of simulating the Deutsch gate (controlled-controlled gate) by generalizing our result on the two-qubit cost of the Toffoli gate. The function of any Deutsch gate is simply a three-qubit controlled-unitary gate and can be intuitively explained as follows: The gate outputs the states of the two control qubits directly, and applies the given one-qubit unitary u on the target qubit only if both the states of the control qubits are |1 > . Previously, it was only known that five two-qubit gates are sufficient for implementing such a gate [Sleator and Weinfurter, Phys. Rev. Lett. 74, 4087 (1995), 10.1103/PhysRevLett.74.4087]. We show that if the determinant of u is 1, four two-qubit gates are optimal. Otherwise, five two-qubit gates are required. For the Fredkin gate (the controlled-swap gate), we prove that five two-qubit gates are necessary and sufficient, which settles the open problem introduced in Smolin and DiVincenzo [Phys. Rev. A 53, 2855 (1996), 10.1103/PhysRevA.53.2855].

  19. Does respiratory gating improve extracorporeal shockwave lithotripsy results?

    PubMed

    Sade, M; Guler, C; Esen, A A; Kirkali, Z

    1994-10-01

    The reliability and efficacy of extracorporeal shockwave lithotripsy (SWL) has been established in urinary stone disease. Its combination with respiratory gating might be a useful method to increase the effectiveness of treatment and reduce the number of shocks required. For this purpose, the results of SWL combined with respiratory gating were compared with those of SWL without gating. There was no difference in the stone-free rates of the two groups or in the complication rate. It is concluded that this method neither decreases the number of shockwaves needed nor increases the effectiveness of SWL.

  20. Non-Adiabatic Holonomic Quantum Gates in an atomic system

    NASA Astrophysics Data System (ADS)

    Azimi Mousolou, Vahid; Canali, Carlo M.; Sjoqvist, Erik

    2012-02-01

    Quantum computation is essentially the implementation of a universal set of quantum gate operations on a set of qubits, which is reliable in the presence of noise. We propose a scheme to perform robust gates in an atomic four-level system using the idea of non-adiabatic holonomic quantum computation proposed in [1]. The gates are realized by applying sequences of short laser pulses that drive transitions between the four energy levels in such a way that the dynamical phases vanish. [4pt] [1] E. Sjoqvist, D.M. Tong, B. Hessmo, M. Johansson, K. Singh, arXiv:1107.5127v2 [quant-ph

  1. Reliability training

    NASA Technical Reports Server (NTRS)

    Lalli, Vincent R. (Editor); Malec, Henry A. (Editor); Dillard, Richard B.; Wong, Kam L.; Barber, Frank J.; Barina, Frank J.

    1992-01-01

    Discussed here is failure physics, the study of how products, hardware, software, and systems fail and what can be done about it. The intent is to impart useful information, to extend the limits of production capability, and to assist in achieving low cost reliable products. A review of reliability for the years 1940 to 2000 is given. Next, a review of mathematics is given as well as a description of what elements contribute to product failures. Basic reliability theory and the disciplines that allow us to control and eliminate failures are elucidated.

  2. The human respiratory gate

    NASA Technical Reports Server (NTRS)

    Eckberg, Dwain L.

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

  3. Advanced insulated gate bipolar transistor gate drive

    DOEpatents

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  4. SEMICONDUCTOR DEVICES: Double gate lateral IGBT on partial membrane

    NASA Astrophysics Data System (ADS)

    Xiaorong, Luo; Lei, Lei; Wei, Zhang; Bo, Zhang; Zhaoji, Li

    2010-02-01

    A new SOI LIGBT (lateral insulated-gate bipolar transistor) with cathode- and anode-gates on partial membrane is proposed. A low on-state resistance is achieved when a negative voltage is applied to the anode gate. In the blocking state, the cathode gate is shortened to the cathode and the anode gate is shortened to the anode, leading to a fast switching speed. Moreover, the removal of the partial silicon substrate under the drift region avoids collecting charges beneath the buried oxide, which releases potential lines below the membrane, yielding an enhanced breakdown voltage (BV). Furthermore, a high switching speed is obtained due to the absence of the drain-substrate capacitance. Lastly, a combination of uniformity and variation in lateral doping profiles helps to achieve a high BV and low special on-resistance. Compared with a conventional LIGBT, the proposed structure exhibits high current capability, low special on-resistance, and double the BV.

  5. Low interfacial trap density and sub-nm equivalent oxide thickness in In{sub 0.53}Ga{sub 0.47}As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO{sub 2}/Al{sub 2}O{sub 3} as gate dielectrics

    SciTech Connect

    Chu, L. K.; Merckling, C.; Dekoster, J.; Caymax, M.; Alian, A.; Heyns, M.; Kwo, J.; Hong, M.

    2011-07-25

    We investigated the passivation of In{sub 0.53}Ga{sub 0.47}As (001) surface by molecular beam epitaxy techniques. After growth of strained In{sub 0.53}Ga{sub 0.47}As on InP (001) substrate, HfO{sub 2}/Al{sub 2}O{sub 3} high-{kappa} oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (D{sub it}) of the Al{sub 2}O{sub 3}/In{sub 0.53}Ga{sub 0.47}As interface have been revealed by conductance measurement, indicating a downward D{sub it} profile from the energy close to the valence band (medium 10{sup 12} cm{sup -2}eV{sup -1}) towards that close to the conduction band (10{sup 11} cm{sup -2}eV{sup -1}). The low D{sub it}'s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO{sub 2} has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO{sub 2} thickness (dielectric constant of HfO{sub 2}{approx}20) and the remained low D{sub it}'s due to the thin Al{sub 2}O{sub 3} passivation layer. The sample with HfO{sub 2} (3.4 nm)/Al{sub 2}O{sub 3} (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of {approx}0.93 nm.

  6. Ge0.83Sn0.17 p-channel metal-oxide-semiconductor field-effect transistors: Impact of sulfur passivation on gate stack quality

    NASA Astrophysics Data System (ADS)

    Lei, Dian; Wang, Wei; Zhang, Zheng; Pan, Jisheng; Gong, Xiao; Liang, Gengchiau; Tok, Eng-Soon; Yeo, Yee-Chia

    2016-01-01

    The effect of room temperature sulfur passivation of the surface of Ge0.83Sn0.17 prior to high-k dielectric (HfO2) deposition is investigated. X-ray photoelectron spectroscopy (XPS) was used to examine the chemical bonding at the interface of HfO2 and Ge0.83Sn0.17. Sulfur passivation is found to be effective in suppressing the formation of both Ge oxides and Sn oxides. A comparison of XPS results for sulfur-passivated and non-passivated Ge0.83Sn0.17 samples shows that sulfur passivation of the GeSn surface could also suppress the surface segregation of Sn atoms. In addition, sulfur passivation reduces the interface trap density Dit at the high-k dielectric/Ge0.83Sn0.17 interface from the valence band edge to the midgap of Ge0.83Sn0.17, as compared with a non-passivated control. The impact of the improved Dit is demonstrated in Ge0.83Sn0.17 p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs). Ge0.83Sn0.17 p-MOSFETs with sulfur passivation show improved subthreshold swing S, intrinsic transconductance Gm,int, and effective hole mobility μeff as compared with the non-passivated control. At a high inversion carrier density Ninv of 1 × 1013 cm-2, sulfur passivation increases μeff by 25% in Ge0.83Sn0.17 p-MOSFETs.

  7. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

    PubMed Central

    Khan, Z. N.; Ahmed, S.; Ali, M.

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  8. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    PubMed

    Khan, Z N; Ahmed, S; Ali, M

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  9. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    PubMed

    Khan, Z N; Ahmed, S; Ali, M

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  10. Demonstrating 1 nm-oxide-equivalent-thickness HfO{sub 2}/InSb structure with unpinning Fermi level and low gate leakage current density

    SciTech Connect

    Trinh, Hai-Dang; Lin, Yueh-Chin; Nguyen, Hong-Quan; Luc, Quang-Ho; Nguyen, Minh-Thuy; Duong, Quoc-Van; Nguyen, Manh-Nghia; Wang, Shin-Yuan; Yi Chang, Edward

    2013-09-30

    In this work, the band alignment, interface, and electrical characteristics of HfO{sub 2}/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO{sub 2} layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO{sub 2}/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10{sup −4} A/cm{sup −2}. The D{sub it} value of smaller than 10{sup 12} eV{sup −1}cm{sup −2} has been obtained using conduction method.

  11. Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Lee, Min Su; Lee, Hee Chul

    2012-11-01

    To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

  12. Multipulse gate-delayed range gating imaging lidar.

    PubMed

    Wu, Long; Zhao, Yuan; Zhang, Yong; Jin, Chenfei; Wu, Jie

    2011-04-15

    We present a technique to reconstruct a higher resolution of depth map of range gating imaging lidar by applying the delays of the gates to a typical range gating lidar system during the detection of each returned laser pulse with the encoding of the returned signal. With the consequent delays of the gate, the depth of the scene is extended accordingly. A multipulse gate-delayed range gating lidar system is designed to prove the resolution improvement from 6 to 1.5 m. The unchanged peak power of the laser, the widths of the laser pulse and the sampling period result in a simple structure of the lidar system. PMID:21499358

  13. The demonstration of colossal magneto-capacitance effect with the promising gate stack characteristics on Ge (100) by the magnetic gate stack design

    NASA Astrophysics Data System (ADS)

    Liao, M.-H.; Huang, S.-C.

    2014-06-01

    The tetragonal-phase BaTiO3 as the high dielectric (HK) layer and the magnetic FePt film as the metal gate (MG) are proposed to be the gate stack scheme on the Ge (100) substrate. The ˜75% dielectric constant (κ-value) improvement, ˜100X gate leakage (Jg) reduction, and the promising Jg-equivalent-oxide-thickness (EOT) gate stack characteristics are achieved in this work with the colossal magneto-capacitance effect. The perpendicular magnetic field from the magnetic FePt MG film couples and triggers the more dipoles in the BaTiO3 HK layer and then results in the super gate capacitance (Cgate) and κ-value. Super Jg-EOT gate stack characteristics with the magnetic gate stack design on the high mobility (Ge) substrate demonstrated in this work provides the useful solution for the future low power mobile device design.

  14. Reliability automation tool (RAT) for fault tolerance computation

    NASA Astrophysics Data System (ADS)

    Singh, N. S. S.; Hamid, N. H.; Asirvadam, V. S.

    2012-09-01

    As CMOS transistors reduced in size, the circuit built using these nano-scale transistors naturally becomes less reliable. The reliability reduction, which is the measure of circuit performance, has brought up so many challenges in designing modern logic integrated circuit. Therefore, reliability modeling is increasingly important subject to be considered in designing modern logic integrated circuit. This drives a need to compute reliability measures for nano-scale circuits. This paper looks into the development of reliability automation tool (RAT) for circuit's reliability computation. The tool is developed using Matlab programming language based on the reliability evaluation model called Probabilistic Transfer Matrix (PTM). RAT allows users to significantly speed-up the reliability assessments of nano-scale circuits. Users have to provide circuit's netlist as the input to RAT for its reliability computation. The netlist signifies the circuit's description in terms of Gate Profile Matrix (GPM), Adjacency Computation Matrix (ACM) and Grid Layout Matrix (GLM). GPM, ACM and GLM indicate the types of logic gates, the interconnection between these logic gates and the layout matrix of these logic gates respectively in a given circuit design. Here, the reliability assessment by RAT is carried out on Full Adder circuit as the benchmark test circuit.

  15. Single electron transistor with P-type sidewall spacer gates.

    PubMed

    Lee, Jung Han; Li, Dong Hua; Lee, Joung-Eob; Kang, Kwon-Chil; Kim, Kyungwan; Park, Byung-Gook

    2011-07-01

    A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed. PMID:22121580

  16. The human respiratory gate

    PubMed Central

    Eckberg, Dwain L

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this ‘respiratory gating’ is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R–R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R–R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms. PMID:12626671

  17. A nanomechanical Fredkin gate.

    PubMed

    Wenzler, Josef-Stefan; Dunn, Tyler; Toffoli, Tommaso; Mohanty, Pritiraj

    2014-01-01

    Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing. PMID:24328764

  18. Deoxyribozyme-based logic gates.

    PubMed

    Stojanovic, Milan N; Mitchell, Tiffany Elizabeth; Stefanovic, Darko

    2002-04-10

    We report herein a set of deoxyribozyme-based logic gates capable of generating any Boolean function. We construct basic NOT and AND gates, followed by the more complex XOR gate. These gates were constructed through a modular design that combines molecular beacon stem-loops with hammerhead-type deoxyribozymes. Importantly, as the gates have oligonucleotides as both inputs and output, they open the possibility of communication between various computation elements in solution. The operation of these gates is conveniently connected to a fluorescent readout.

  19. Investigation of carbonitrided components of the valve gates of Christmas trees and tubing heads

    SciTech Connect

    Kakhramanov, K.T.; Fataliev, N.S.; Levitan, Y.A.; Safarov, R.S.

    1985-07-01

    The authors evaluate the effectiveness of carbonitride hardening of the valve gates of Christmas trees and tubing heads. Measurements of microhardness, resistance to seizing, corrosion resistance, and durability demonstrate that carbonitriding helps to ensure strength, tightness, and reliable operation of the gate in the pressure range up to 35 MPa. Therefore, gates with carbonitrided components are durable and fully satisfy the requirements of the technique and technology of operation.

  20. On the Asymmetric Splitting of CBED HOLZ Lines under the Gate of Recessed SiGe Source/Drain Transistors

    NASA Astrophysics Data System (ADS)

    Benedetti, A.; Bender, H.

    The behaviour of the CBED HOLZ line splitting under the gate of transistor structures with recessed SiGe in the source/drain regions is investigated. Structures with nitride/oxide dummy gates or with poly gates and nitride spacers are studied. In the gate region as well as below the SiGe, splitting of the HOLZ lines in the CBED patterns is observed with increasing magnitude towards the interface. The splitting under the gate shows an asymmetry for equivalent lines which inverts along horizontal cutlines under the gate. The behaviour is explained by a 3-dimensional relaxation of the stress.

  1. Detail of gate, gate slots, and connection between the two ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Detail of gate, gate slots, and connection between the two segments of the rectangular rearing tank. Pump house (1962) at entrance is in the background. View to the southwest. - Prairie Creek Fish Hatchery, Hwy. 101, Orick, Humboldt County, CA

  2. 7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, HEADHOUSES AND DAM BRIDGE, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  3. Cardiac gated ventilation

    SciTech Connect

    Hanson, C.W. III; Hoffman, E.A.

    1995-12-31

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

  4. Cardiac gated ventilation

    NASA Astrophysics Data System (ADS)

    Hanson, C. William, III; Hoffman, Eric A.

    1995-05-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. We evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50msec scan aperture. Multislice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. We observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a nonfailing model of the heart.

  5. Low Gate Voltage Operated Multi-emitter-dot H+ Ion-Sensitive Gated Lateral Bipolar Junction Transistor

    NASA Astrophysics Data System (ADS)

    Yuan, Heng; Zhang, Ji-Xing; Zhang, Chen; Zhang, Ning; Xu, Li-Xia; Ding, Ming; Patrick, J. Clarke

    2015-02-01

    A low gate voltage operated multi-emitter-dot gated lateral bipolar junction transistor (BJT) ion sensor is proposed. The proposed device is composed of an arrayed gated lateral BJT, which is driven in the metal-oxide-semiconductor field-effect transistor (MOSFET)-BJT hybrid operation mode. Further, it has multiple emitter dots linked to each other in parallel to improve ionic sensitivity. Using hydrogen ionic solutions as reference solutions, we conduct experiments in which we compare the sensitivity and threshold voltage of the multi-emitter-dot gated lateral BJT with that of the single-emitter-dot gated lateral BJT. The multi-emitter-dot gated lateral BJT not only shows increased sensitivity but, more importantly, the proposed device can be operated under very low gate voltage, whereas the conventional ion-sensitive field-effect transistors cannot. This special characteristic is significant for low power devices and for function devices in which the provision of a gate voltage is difficult.

  6. Adiabatic gate teleportation.

    PubMed

    Bacon, Dave; Flammia, Steven T

    2009-09-18

    The difficulty in producing precisely timed and controlled quantum gates is a significant source of error in many physical implementations of quantum computers. Here we introduce a simple universal primitive, adiabatic gate teleportation, which is robust to timing errors and many control errors and maintains a constant energy gap throughout the computation above a degenerate ground state space. This construction allows for geometric robustness based upon the control of two independent qubit interactions. Further, our piecewise adiabatic evolution easily relates to the quantum circuit model, enabling the use of standard methods from fault-tolerance theory for establishing thresholds.

  7. Outlet side of gate, showing the Radial Gate, hoist mechanism ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Outlet side of gate, showing the Radial Gate, hoist mechanism and concrete walkway across the canal. The concrete baffle separating the afterbay and the cipoletti weir is in the foreground - Wellton-Mohawk Irrigation System, Radial Gate Check with Drop, Wellton Canal 9.9, West of Avenue 34 East & north of County Ninth Street, Wellton, Yuma County, AZ

  8. Exterior, looking southeast from within compound towards Main Gate, Gate ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking southeast from within compound towards Main Gate, Gate House center left - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  9. Exterior, looking northwest towards Main Gate, Gate House on left, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking northwest towards Main Gate, Gate House on left, Technical Equipment Building (Building 5760) in background to right - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  10. Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

    NASA Astrophysics Data System (ADS)

    Samanta, Piyas; Mandal, Krishna C.

    2016-08-01

    We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7-25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (tBD) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the tBD values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO2 was observed between 27 and 225 °C.

  11. Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

    NASA Astrophysics Data System (ADS)

    Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

    2015-09-01

    Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

  12. Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Douglas, Erica Ann

    Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated

  13. A Pt-Ti-O gate Si-metal-insulator-semiconductor field-effect transistor hydrogen gas sensor

    NASA Astrophysics Data System (ADS)

    Usagawa, Toshiyuki; Kikuchi, Yota

    2010-10-01

    A hydrogen gas sensor based on platinum-titanium-oxygen (Pt-Ti-O) gate silicon-metal-insulator-semiconductor field-effect transistors (Si-MISFETs) was developed. The sensor has a unique gate structure composed of titanium and oxygen accumulated around platinum grains on top of a novel mixed layer of nanocrystalline TiOx and superheavily oxygen-doped amorphous titanium formed on SiO2/Si substrates. The FET hydrogen sensor shows high reliability and high sensing amplitude (Δ Vg) defined by the magnitude of the threshold voltage shift. Δ Vg is well fitted by a linear function of the logarithm of air-diluted hydrogen concentration C (ppm), i.e., Δ Vg(V) =0.355 log C(ppm ) -0.610 , between 100 ppm and 1%. This high gradient coefficient of Δ Vg for the wide sensing range demonstrates that the sensor is suitable for most hydrogen-safety-monitoring sensor systems. The Pt-Ti-O structures of the sensor are typically realized by annealing Pt (15 nm)/Ti (5 nm)-gate Si-metal-oxide-semiconductor structures in air at 400 °C for 2 h. The Pt-Ti-O gate MIS structures were analyzed by transmission electron microscope (TEM), x-ray diffraction, Auger electron spectroscopy, and TEM energy dispersive x-ray spectroscopy. From the viewpoint of practical sensing applications, hydrogen postannealing of the Pt-Ti-O gate Si-MISFETs is necessary to reduce the residual sensing amplitudes with long tailing profiles.

  14. Modeling and simulation of floating gate nanocrystal FET devices and circuits

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed A. M.

    The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

  15. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  16. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  17. Models of HERG gating.

    PubMed

    Bett, Glenna C L; Zhou, Qinlian; Rasmusson, Randall L

    2011-08-01

    HERG (Kv11.1, KCNH2) is a voltage-gated potassium channel with unique gating characteristics. HERG has fast voltage-dependent inactivation, relatively slow deactivation, and fast recovery from inactivation. This combination of gating kinetics makes study of HERG difficult without using mathematical models. Several HERG models have been developed, with fundamentally different organization. HERG is the molecular basis of I(Kr), which plays a critical role in repolarization. We programmed and compared five distinct HERG models. HERG gating cannot be adequately replicated using Hodgkin-Huxley type formulation. Using Markov models, a five-state model is required with three closed, one open, and one inactivated state, and a voltage-independent step between some of the closed states. A fundamental difference between models is the presence/absence of a transition directly from the proximal closed state to the inactivated state. The only models that effectively reproduce HERG data have no direct closed-inactivated transition, or have a closed-inactivated transition that is effectively zero compared to the closed-open transition, rendering the closed-inactivation transition superfluous. Our single-channel model demonstrates that channels can inactivate without conducting with a flickering or bursting open-state. The various models have qualitative and quantitative differences that are critical to accurate predictions of HERG behavior during repolarization, tachycardia, and premature depolarizations. PMID:21806931

  18. Strategy Retooled at Gates

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2008-01-01

    In rolling out plans last week to revamp its high school strategy and launch a major new effort on the postsecondary front, the Bill & Melinda Gates Foundation is undertaking a more sweeping approach to grantmaking that appears aimed at reshaping some core elements of the U.S. education system. The philanthropy's agenda on secondary schools…

  19. Models of HERG Gating

    PubMed Central

    Bett, Glenna C.L.; Zhou, Qinlian; Rasmusson, Randall L.

    2011-01-01

    HERG (Kv11.1, KCNH2) is a voltage-gated potassium channel with unique gating characteristics. HERG has fast voltage-dependent inactivation, relatively slow deactivation, and fast recovery from inactivation. This combination of gating kinetics makes study of HERG difficult without using mathematical models. Several HERG models have been developed, with fundamentally different organization. HERG is the molecular basis of IKr, which plays a critical role in repolarization. We programmed and compared five distinct HERG models. HERG gating cannot be adequately replicated using Hodgkin-Huxley type formulation. Using Markov models, a five-state model is required with three closed, one open, and one inactivated state, and a voltage-independent step between some of the closed states. A fundamental difference between models is the presence/absence of a transition directly from the proximal closed state to the inactivated state. The only models that effectively reproduce HERG data have no direct closed-inactivated transition, or have a closed-inactivated transition that is effectively zero compared to the closed-open transition, rendering the closed-inactivation transition superfluous. Our single-channel model demonstrates that channels can inactivate without conducting with a flickering or bursting open-state. The various models have qualitative and quantitative differences that are critical to accurate predictions of HERG behavior during repolarization, tachycardia, and premature depolarizations. PMID:21806931

  20. On-current limitation of high-k gate insulator MOSFETs

    NASA Astrophysics Data System (ADS)

    Shih, Chun-Hsing; Wang, Jhong-Sheng; Chien, Nguyen Dang; Shia, Ruei-Kai

    2012-12-01

    This work explores the limitation of high-k gate insulator on improving the driving currents of MOSFET devices. The use of high-k gate dielectric prevents from the gate tunneling current to have an acceptable equivalent oxide thickness (EOT) in scaled MOSFETs. However, the effectiveness of continued EOT reduction in strengthening gate control is limited strongly by the non-scalability of the quantum effect of inversion layer thickness. Both classical and quantum-mechanical approaches of inversion layer thickness are presented to study the effective gate capacitances and associated on-state drain currents. The enhancements of drain current and gate capacitance generated by high-k gate dielectrics are gradually saturated when a higher permittivity dielectric is applied.

  1. Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

    NASA Technical Reports Server (NTRS)

    Lauenstein, Jean-Marie

    2011-01-01

    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

  2. Reliability Prediction

    NASA Technical Reports Server (NTRS)

    1993-01-01

    RELAV, a NASA-developed computer program, enables Systems Control Technology, Inc. (SCT) to predict performance of aircraft subsystems. RELAV provides a system level evaluation of a technology. Systems, the mechanism of a landing gear for example, are first described as a set of components performing a specific function. RELAV analyzes the total system and the individual subsystem probabilities to predict success probability, and reliability. This information is then translated into operational support and maintenance requirements. SCT provides research and development services in support of government contracts.

  3. Improvement of metal gate/high-k dielectric CMOSFETs characteristics by atomic layer etching of high-k gate dielectric

    NASA Astrophysics Data System (ADS)

    Min, K. S.; Park, C.; Kang, C. Y.; Park, C. S.; Park, B. J.; Kim, Y. W.; Lee, B. H.; Lee, Jack C.; Bersuker, G.; Kirsch, P.; Jammy, R.; Yeom, G. Y.

    2013-04-01

    Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal-oxide-semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the improvement of the off-state leakage current (Ioff), which was mainly attributed to the decreased perimeter component of the gate leakage current (IG) particularly, at the low field region. The better electrical characteristics are due to the low trap density at the edge of gate oxides in the S/D region of CMOSFETs.

  4. Electroluminescence from individual air-suspended carbon nanotubes within split-gate structures

    NASA Astrophysics Data System (ADS)

    Higashide, N.; Uda, T.; Yoshida, M.; Ishii, A.; Kato, Y. K.

    Electrically induced light emission from chirality-identified single-walled carbon nanotubes are investigated by utilizing split-gate field-effect devices fabricated on silicon-on-insulator substrates. We begin by etching trenches through the top silicon layer into the buried oxide, and the silicon layer is thermally oxidized for use as local gates. We partially remove the oxide and form gate electrodes, then contacts for nanotubes are deposited on both sides of the trench. Catalyst particles are placed on the contacts, and nanotubes are grown over the trench by chemical vapor deposition. We use photoluminescence microscopy to locate the nanotubes and perform excitation spectroscopy to identify their chirality. Gate-induced photoluminescence quenching is used to confirm carrier doping, and electroluminescence intensity is investigated as a function of the split-gate and bias voltages. Work supported by JSPS (KAKENHI 24340066, 26610080), MEXT (Photon Frontier Network Program, Nanotechnology Platform), Canon Foundation, and Asahi Glass Foundation.

  5. Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications

    SciTech Connect

    Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F.; Lee, Y.; Park, C.

    1999-12-06

    We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.

  6. A deep-submicron single gate CMOS technology using in-situ boron-doped polycrystalline silicon-germanium gates formed by rapid thermal chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Li, Vivian Zhi-Qi

    This thesis presents a comprehensive study of in-situ boron doped polycrystalline-Sisb{1-x}Gesb{x} films deposited in a rapid thermal chemical vapor deposition system and used as the gate electrode in the deep submicron bulk CMOS technology. This work includes an investigation of the nucleation behavior of poly-Sisb{1-x}Gesb{x} films on the oxide surface, development of a deposition process using Sisb2Hsb6,\\ GeHsb4 and Bsb2Hsb6 gases in addition to using common gas mixture of SiHsb4,\\ GeHsb4 and Bsb2Hsb6 in a RTCVD system, characterization of the deposited film structure and its properties, examination of the electrical properties, extraction of the workfunction as a function of the Ge content in the film, development of the NMOS, PMOS and CMOS processes for in-situ boron doped poly-Sisb{1-x}Gesb{x} gate technology, assessment of the impact of poly-Sisb{1-x}Gesb{x} gate on the device performance through computer simulations. The process integration issues such as boron penetration, poly-depletion and gate oxide reliability, and characterization of deep submicron CMOS devices are also studied. One critical concern with the use of poly-Sisb{1-x}Gesb{x} gate materials is its partially selective deposition process on the SiOsb2. In this work, we demonstrated non-selective deposition processes for poly-Sisb{1-x}Gesb{x} without conventional Si pre-deposition onto oxide. One approach is by using in-situ boron doping method and another is by using Sisb2Hsb6 as the Si source gas. Also, it was found that the density of the nucleation sites at the initial stage of deposition increases with the increase of the Bsb2Hsb6 gas flow rate. The resulting continuous poly-Sisb{1-x}Gesb{x} films were attributed to the preferential adsorption of boron atoms onto the oxide surface providing the necessary nucleation sites for the subsequent Sisb{1-x}Gesb{x} film growth. For undoped poly-Sisb{1-x}Gesb{x} films, continuous films can be formed on the oxide using Sisb2Hsb6 and GeHsb4 gases

  7. A quantum Fredkin gate.

    PubMed

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  8. A quantum Fredkin gate

    PubMed Central

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  9. A quantum Fredkin gate.

    PubMed

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  10. Noncollinear Polarization Gating of Attosecond Pulse Trains in the Relativistic Regime.

    PubMed

    Yeung, M; Bierbach, J; Eckner, E; Rykovanov, S; Kuschel, S; Sävert, A; Förster, M; Rödel, C; Paulus, G G; Cousens, S; Coughlan, M; Dromey, B; Zepf, M

    2015-11-01

    High order harmonics generated at relativistic intensities have long been recognized as a route to the most powerful extreme ultraviolet pulses. Reliably generating isolated attosecond pulses requires gating to only a single dominant optical cycle, but techniques developed for lower power lasers have not been readily transferable. We present a novel method to temporally gate attosecond pulse trains by combining noncollinear and polarization gating. This scheme uses a split beam configuration which allows pulse gating to be implemented at the high beam fluence typical of multi-TW to PW class laser systems. Scalings for the gate width demonstrate that isolated attosecond pulses are possible even for modest pulse durations achievable for existing and planned future ultrashort high-power laser systems. Experimental results demonstrating the spectral effects of temporal gating on harmonic spectra generated by a relativistic laser plasma interaction are shown. PMID:26588384

  11. Gated Treatment Delivery Verification With On-Line Megavoltage Fluoroscopy

    SciTech Connect

    Tai An; Christensen, James D.; Gore, Elizabeth; Khamene, Ali; Boettger, Thomas; Li, X. Allen

    2010-04-15

    Purpose: To develop and clinically demonstrate the use of on-line real-time megavoltage (MV) fluoroscopy for gated treatment delivery verification. Methods and Materials: Megavoltage fluoroscopy (MVF) image sequences were acquired using a flat panel equipped for MV cone-beam CT in synchrony with the respiratory signal obtained from the Anzai gating device. The MVF images can be obtained immediately before or during gated treatment delivery. A prototype software tool (named RTReg4D) was developed to register MVF images with phase-sequenced digitally reconstructed radiograph images generated from the treatment planning system based on four-dimensional CT. The image registration can be used to reposition the patient before or during treatment delivery. To demonstrate the reliability and clinical usefulness, the system was first tested using a thoracic phantom and then prospectively in actual patient treatments under an institutional review board-approved protocol. Results: The quality of the MVF images for lung tumors is adequate for image registration with phase-sequenced digitally reconstructed radiographs. The MVF was found to be useful for monitoring inter- and intrafractional variations of tumor positions. With the planning target volume contour displayed on the MVF images, the system can verify whether the moving target stays within the planning target volume margin during gated delivery. Conclusions: The use of MVF images was found to be clinically effective in detecting discrepancies in tumor location before and during respiration-gated treatment delivery. The tools and process developed can be useful for gated treatment delivery verification.

  12. Gating of Permanent Molds for Aluminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-01-01

    This report summarizes a two-year project, DE-FC07-011D13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was to determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings. Equipment and procedure for real time X-Ray radiography of molten aluminum flow into permanent molds have been developed. Other studies have been conducted using water flow and behavior of liquid aluminum in sand mold using real time photography. This investigation utilizes graphite molds transparent to X-Rays making it possible to observe the flow pattern through a number of vertically oriented grating systems. These have included systems that are choked at the base of a rounded vertical sprue and vertical gating systems with a variety of different ingates into the bottom of a mold cavity. These systems have also been changed to include gating systems with vertical and horizontal gate configurations. Several conclusions can be derived from this study. A sprue-well, as designed in these experiments, does not eliminate the vena contracta. Because of the swirling at the sprue-base, the circulating metal begins to push the entering metal stream toward the open runner mitigating the intended effect of the sprue-well. Improved designs of

  13. ZnO-based multiple channel and multiple gate FinMOSFETs

    NASA Astrophysics Data System (ADS)

    Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

    2016-02-01

    In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

  14. Mechanically reliable scales and coatings

    SciTech Connect

    Tortorelli, P.F.; Alexander, K.B.

    1995-07-01

    As the first stage in examining the mechanical reliability of protective surface oxides, the behavior of alumina scales formed on iron-aluminum alloys during high-temperature cyclic oxidation was characterized in terms of damage and spallation tendencies. Scales were thermally grown on specimens of three iron-aluminum composition using a series of exposures to air at 1000{degrees}C. Gravimetric data and microscopy revealed substantially better integrity and adhesion of the scales grown on an alloy containing zirconium. The use of polished (rather than just ground) specimens resulted in scales that were more suitable for subsequent characterization of mechanical reliability.

  15. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  16. Modeling of hole confinement gate voltage range for SiGe channel p-MOSFETs

    NASA Astrophysics Data System (ADS)

    Niu, G. F.; Ruan, G.; Zhang, D. H.

    1996-01-01

    An analytical model of hole confinement gate voltage range is derived for SiGe-channel p-MOSFETs and verified by SEDAN-3 simulation. The hole confinement gate voltage range is shown to be a function of threshold voltage, gate oxide thickness to Si cap thickness ratio, gate material, and Ge mole fraction. Si cap should be thinned with device scaling and power supply decreasing to keep the same hole confinement so as to realise full bias range SiGe-channel operation. It is clarified that various bulk and SIO SiGe p-MOSFETs have the same hole confinement under the same threshold voltage.

  17. Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

    NASA Astrophysics Data System (ADS)

    Gupta, Santosh Kumar

    2015-12-01

    2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate-source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator.

  18. Automation of a gated-pipe irrigation system. Final report

    SciTech Connect

    Manges, H.L.; Blume, H.R.; Matteson, D.K.; Butler, K.G.

    1981-03-01

    An existing gated-pipe system was automated by controlling flow into short segments of gated pipe with flow-control valves. Irrigation controllers and a microcomputer both operated the flow-control valves automatically by radio controls. The irrigation controllers and the microcomputer successfully operated the system. Although both can provide cutback-head irrigation, the microcomputer is capable of more flexible system operation. Radio controls sold for controlling model airplanes did not give reliable service when operated continuously in an irrigated field. Operation of the flo-control valves was satisfactory.

  19. Electrofluidic gating of a chemically reactive surface.

    PubMed

    Jiang, Zhijun; Stein, Derek

    2010-06-01

    We consider the influence of an electric field applied normal to the electric double layer at a chemically reactive surface. Our goal is to elucidate how surface chemistry affects the potential for field-effect control over micro- and nanofluidic systems, which we call electrofluidic gating. The charging of a metal-oxide-electrolyte (MOE) capacitor is first modeled analytically. We apply the Poisson-Boltzmann description of the double layer and impose chemical equilibrium between the ionizable surface groups and the solution at the solid-liquid interface. The chemically reactive surface is predicted to behave as a buffer, regulating the charge in the double layer by either protonating or deprotonating in response to the applied field. We present the dependence of the charge density and the electrochemical potential of the double layer on the applied field, the density, and the dissociation constants of ionizable surface groups and the ionic strength and the pH of the electrolyte. We simulate the responses of SiO(2) and Al(2)O(3), two widely used oxide insulators with different surface chemistries. We also consider the limits to electrofluidic gating imposed by the nonlinear behavior of the double layer and the dielectric strength of oxide materials, which were measured for SiO(2) and Al(2)O(3) films in MOE configurations. Our results clarify the response of chemically reactive surfaces to applied fields, which is crucial to understanding electrofluidic effects in real devices.

  20. Field-effect transistor replaces bulky transformer in analog-gate circuit

    NASA Technical Reports Server (NTRS)

    1965-01-01

    Metal-oxide semiconductor field-effect transistor /MOSFET/ analog-gate circuit adapts well to integrated circuits. It provides better system isolation than a transformer, while size and weight are appreciably reduced.

  1. ONE SHAKE GATE FORMER

    DOEpatents

    Kalibjian, R.; Perez-Mendez, V.

    1957-08-20

    An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

  2. Compact gate valve

    DOEpatents

    Bobo, Gerald E.

    1977-01-01

    This invention relates to a double-disc gate valve which is compact, comparatively simple to construct, and capable of maintaining high closing pressures on the valve discs with low frictional forces. The valve casing includes axially aligned ports. Mounted in the casing is a sealed chamber which is pivotable transversely of the axis of the ports. The chamber contains the levers for moving the valve discs axially, and an actuator for the levers. When an external drive means pivots the chamber to a position where the discs are between the ports and axially aligned therewith, the actuator for the levers is energized to move the discs into sealing engagement with the ports.

  3. Tide gate valve

    SciTech Connect

    Raftis, S. G.

    1985-01-08

    A tide gate check valve in which at least three converging sides are provided at a tapered region of a flexible sleeve, so that on reverse back pressure build-up of fluid, reverse fluid flow is prevented, while the valve sleeve does not invert or collapse. The present configuration features embedded reinforcing elements for resisting inversion or collapsing when the back pressure builds up. This feature is especially important for large-sized conduits of 36'' or 72'' diameter, or even larger, such as are common in storm sewer applications.

  4. 12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE OPERATORS, LOOKING NORTHWEST. - Sacramento River Water Treatment Plant Intake Pier & Access Bridge, Spanning Sacramento River approximately 175 feet west of eastern levee on river; roughly .5 mile downstream from confluence of Sacramento & American Rivers, Sacramento, Sacramento County, CA

  5. 16. Little Hell Gate Bridge with Big Hell Gate Bridge ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. Little Hell Gate Bridge with Big Hell Gate Bridge in background. Wards Island, New York Co., NY. Sec. 4207, MP 8.02. - Northeast Railroad Corridor, Amtrak Route between New Jersey/New York & New York/Connecticut State Lines, New York County, NY

  6. 3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    3. TAINTER GATES (LEFT FOREGROUND) AND ROLLING SECTOR GATE AND SPILLWAY (BACKGROUND) OF THE NORTH CHANNEL DAM, LOOKING SOUTH. - Washington Water Power Company Post Falls Power Plant, North Channel Dam, West of intersection of Spokane & Fourth Streets, Post Falls, Kootenai County, ID

  7. 5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    5. GATE 5, INTAKE CHANNEL LOOKING SOUTH; WATER FROM GATE 5 ENTERED DITCH AND IRRIGATED HONDIUS' FIELDS. - Hondius Water Line, 1.6 miles Northwest of Park headquarters building & 1 mile Northwest of Beaver Meadows entrance station, Estes Park, Larimer County, CO

  8. A graphical language for reliability model generation

    NASA Technical Reports Server (NTRS)

    Howell, Sandra V.; Bavuso, Salvatore J.; Haley, Pamela J.

    1990-01-01

    A graphical interface capability of the hybrid automated reliability predictor (HARP) is described. The graphics-oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault tree gates, including sequence dependency gates, or by a Markov chain. With this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the Graphical Kernel System (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing.

  9. Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

    NASA Astrophysics Data System (ADS)

    Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

    2016-06-01

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  10. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  11. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

    NASA Astrophysics Data System (ADS)

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-09-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10-14 A, leading to ultrahigh on/off ratio over 109, about ~103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

  12. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio.

    PubMed

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-01-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10(-14) A, leading to ultrahigh on/off ratio over 10(9), about ∼10(3) times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics. PMID:27586841

  13. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

    PubMed Central

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-01-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics. PMID:27586841

  14. Image-guided adaptive gating of lung cancer radiotherapy: a computer simulation study

    NASA Astrophysics Data System (ADS)

    Aristophanous, Michalis; Rottmann, Joerg; Park, Sang-June; Nishioka, Seiko; Shirato, Hiroki; Berbeco, Ross I.

    2010-08-01

    regularity of the breathing pattern suggesting that image-guided adaptive gating should be combined with breath coaching. The adaptive gating window technique was able to track the exhale position of the breathing cycle quite successfully. Out of a total of 53 fractions the duty cycle was greater than 20% for 42 fractions for the fixed gating window technique and for 39 fractions for the adaptive gating window technique. The results of this study suggest that real-time updating of the gating window can result in reliably low residual tumor motion and therefore can facilitate safe margin reduction.

  15. Gates Learns to Think Big

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2006-01-01

    This article discusses how the philanthropy of Microsoft Corp software magnate co-chairs, Bill Gates and his wife Melinda, are reshaping the American high school nowadays. Gates and his wife have put the issue on the national agenda like never before, with a commitment of more than 1.3 billion US dollars this decade toward the foundation's agenda…

  16. Penn State DOE GATE Program

    SciTech Connect

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  17. Gate Set Tomography on a trapped ion qubit

    NASA Astrophysics Data System (ADS)

    Nielsen, Erik; Blume-Kohout, Robin; Gamble, John; Rundinger, Kenneth; Mizrahi, Jonathan; Sterk, Johathan; Maunz, Peter

    2015-03-01

    We present enhancements to gate-set tomography (GST), which is a framework in which an entire set of quantum logic gates (including preparation and measurement) can be fully characterized without need for pre-calibrated operations. Our new method, ``extended Linear GST'' (eLGST) uses fast, reliable analysis of structured long gate sequences to deliver tomographic precision at the Heisenberg limit with GST's calibration-free framework. We demonstrate this precision on a trapped-ion qubit, and show significant (orders of magnitude) advantage over both standard process tomography and randomized benchmarking. This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia National Laboratories. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

  18. Theory and experiments of electron-hole recombination at silicon/silicon dioxide interface traps and tunneling in thin oxide MOS transistors

    NASA Astrophysics Data System (ADS)

    Cai, Jin

    2000-10-01

    Surface recombination and channel have dominated the electrical characteristics, performance and reliability of p/n junction diodes and transistors. This dissertation uses a sensitive direct-current current voltage (DCIV) method to measure base terminal currents (IB) modulated by the gate bias (VGB) and forward p/n junction bias (VPN) in a MOS transistor (MOST). Base terminal currents originate from electron-hole recombination at Si/SiO2 interface traps. Fundamental theories which relate DCIV characteristics to device and material parameters are presented. Three theory-based applications are demonstrated on both the unstressed as well as hot-carrier-stressed MOSTs: (1) determination of interface trap density and energy levels, (2) spatial profile of interface traps in the drain/base junction-space-charge region and in the channel region, and (3) determination of gate oxide thickness and impurity doping concentrations. The results show that interface trap energy levels are discrete, which is consistent with those from silicon dangling bonds; in unstressed MOS transistors interface trap density in the channel region rises sharply toward source and drain, and after channel-hot-carrier stress, interface trap density increases mostly in the junction space-charge region. As the gate oxide thins below 3 nm, the gate oxide leakage current via quantum mechanical tunneling becomes significant. A gate oxide tunneling theory which refined the traditional WKB tunneling probability is developed for modeling tunneling currents at low electric fields through a trapezoidal SiO2 barrier. Correlation with experimental data on thin oxide MOSTs reveals two new results: (1) hole tunneling dominates over electron tunneling in p+gate p-channel MOSTs, and (2) the small gate/drain overlap region passes higher tunneling currents than the channel region under depletion to flatband gate voltages. The good theory-experimental correlation enables the extraction of impurity doping concentrations

  19. Low Voltage Silicon Dioxide Reliability

    NASA Astrophysics Data System (ADS)

    Schuegraf, Klaus Florian

    This study investigates the low voltage breakdown and conduction properties of thin thermal silicon dioxides with thickness ranging from 25 A to 130 A using silicon metal-oxide-semiconductor (MOS) capacitors and transistors. Investigation of oxide breakdown shows that anode hole injection is the likely mechanism responsible for silicon dioxide wearout. A quantitative model for oxide breakdown based on anode hole injection is proposed. This model not only agrees with the predictions of an empirical inverse oxide field model ("1 over E model"), it offers a methodology to extrapolate high field oxide breakdown data into the low voltage operating regime. Investigation of low voltage silicon dioxide tunneling current shows that leakage current increases dramatically above that predicted by the Fowler-Nordheim theory for oxide voltages less than 3.15 Volts, possibly setting a scaling limit on thickness at 40 A. The model is also used to compare the breakdown of p^+ and n^+ polysilicon gate, showing no change in damage initiation mechanism. The temperature dependence of breakdown is also investigated, showing that anode hole injection models the breakdown characteristics accurately for temperatures below 150^circC. The temperature acceleration of breakdown is attributed to the oxide's reduced hole immunity at higher temperatures. The anode hole injection model is thereby shown to model the breakdown characteristics of defect-free, "intrinsic" oxide very accurately. A defect model combining the breakdown mechanism of anode hole injection with "effective thinning" is able to characterize defect breakdown distributions by attributing the breakdown to an effective thinning of the oxide at some localized point. Substrate current measurements during electrical breakdown stress establish the basis for the anode hole injection model. Investigations of substrate current in oxides thinner than 55 A show that the anode hole injection current becomes dominated by the tunneling of

  20. Development and Application of Tools to Characterize the Oxidative Degradation of AP/HTPB/Al Propellants in a Propellant Reliability Study

    NASA Technical Reports Server (NTRS)

    Celina, Mathew; Minier, Leanna; Assink, Roger

    2000-01-01

    The oxidative thermal aging of a crosslinked hydroxyl-terminated polybutadiene (HTPB)/isophorone diisocyanate (IPDI) polyurethane rubber was studied at temperatures between 25 C and 125 C. Changes in tensile elongation, mechanical hardening, polymer network properties, density, O2 permeation, and molecular chain dynamics were investigated as a function of age. The techniques used include solvent swelling, detailed modulus profiling, and NMR relaxation measurements. The Arrhenius methodology, which normally assumes a linear extrapolation of high temperature aging data, is critically evaluated by using extensive data superposition and highly sensitive oxygen consumption measurements. Significant curvature in the Arrhenius diagram of these oxidation rates is observed to be similar to previous results found for other rubber materials that have been evaluated by this technique. Preliminary gel/network properties suggest that crosslinking is the dominant process at higher temperatures. The effect on the oxidation rate of the binder when other constituents found in propellants are present, such as ammonium perchlorate, plasticizer and aluminum powder, is presented.

  1. Conical surrounding gate MOSFET: a possibility in gate-all-around family

    NASA Astrophysics Data System (ADS)

    Jena, B.; Ramkrishna, B. S.; Dash, S.; Mishra, G. P.

    2016-03-01

    In this paper a new conical surrounding gate metal-oxide-semiconductor field effect transistor (MOSFET) with triple-material gate has been proposed and verified using TCAD device simulator from Synopsis. The electrostatic performance of conical model with different tapering ratios is extensively investigated and compared with that of cylindrical model (tapering ratio TR = 1). The present model exhibits improved electrostatic behavior for an optimized tapering ratio of 0.98 as compared to the conventional cylindrical model. The results reveal that the triple-material conical model provides better ON current performance, transconductance and reduced threshold voltage. On the contrary the single-material conical model exhibits maximum {{I}}{{O}{{N}}}/{{I}}{{O}{{F}}{{F}}} ratio, minimum OFF current and reduced subthreshold swing (SS) in comparison to other models. Thus, the conical model with optimized tapering ratio can be a possible replacement of cylindrical model for low-power and high speed application.

  2. MOV reliability evaluation and periodic verification scheduling

    SciTech Connect

    Bunte, B.D.

    1996-12-01

    The purpose of this paper is to establish a periodic verification testing schedule based on the expected long term reliability of gate or globe motor operated valves (MOVs). The methodology in this position paper determines the nominal (best estimate) design margin for any MOV based on the best available information pertaining to the MOVs design requirements, design parameters, existing hardware design, and present setup. The uncertainty in this margin is then determined using statistical means. By comparing the nominal margin to the uncertainty, the reliability of the MOV is estimated. The methodology is appropriate for evaluating the reliability of MOVs in the GL 89-10 program. It may be used following periodic testing to evaluate and trend MOV performance and reliability. It may also be used to evaluate the impact of proposed modifications and maintenance activities such as packing adjustments. In addition, it may be used to assess the impact of new information of a generic nature which impacts safety related MOVs.

  3. Measurement of ventricular function by ECG gating during atrial fibrillation

    SciTech Connect

    Bacharach, S.L.; Green, M.V.; Bonow, R.O.; Findley, S.L.; Ostrow, H.G.; Johnston, G.S.

    1981-03-01

    The assumptions necessary to perform ECG-gated cardiac studies are seemingly not valid for patients in atrial fibrillation (AF). To evaluate the effect of AF on equilibrium gated scintigraphy, beat-by-beat measurements of left-ventricular function were made on seven subjects in AF (mean heart rate 64 bpm), using a high-efficiency nonimaging detector. The parameters evaluated were ejection fraction (EF), time to end-systole (TES), peak rates of ejection and filling (PER,PFR), and their times of occurrence (TPER, TPFR). By averaging together single-beat values of EF, PER, etc., it was possible to determine the true mean values of these parameters. The single-beam mean values were compared with the corresponding parameters calculated from one ECG-gated time-activity curve (TAC) obtained by superimposing all the single-beat TACs irrespective of their length. For this population with slow heart rates, we find that the values for EF, etc., produced from ECG-gated time-activity curves, are very similar to those obtained from the single-beat data. Thus use of ECG gating at low heart rates may allow reliable estimation of average cardiac function even in subjects with AF.

  4. Effects of fluorine incorporation into HfO{sub 2} gate dielectrics on InP and In{sub 0.53}Ga{sub 0.47}As metal-oxide-semiconductor field-effect-transistors

    SciTech Connect

    Chen Yenting; Zhao Han; Wang Yanzhen; Xue Fei; Zhou Fei; Lee, Jack C.

    2010-06-21

    In this work, the effects of fluorine (F) incorporation on electrical characteristics of HfO{sub 2}/InP and HfO{sub 2}/In{sub 0.53}Ga{sub 0.47}As gate stack are presented. F had been introduced into HfO{sub 2} gate dielectric by postgate CF{sub 4} plasma treatment, which was confirmed by x-ray photoelectron spectroscopy analysis and a secondary ion mass spectrometry technique. Compared to the control sample, fluorinated samples had great improvements in subthreshold swing, hysteresis, the normalized extrinsic transconductance, and the normalized drain current. These improvements can be attributed to the reduction in fixed charge in the HfO{sub 2} bulk and less interface trap density at the HfO{sub 2}/III-V interface.

  5. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se2 thin-film solar cell absorbers

    NASA Astrophysics Data System (ADS)

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-01

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for "realistic" surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In1-xGax)Se2 thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH3-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is - apart from a slight change in surface composition - identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  6. Design of a recessed-gate GaN-based MOSFET using a dual gate dielectric for high-power applications

    NASA Astrophysics Data System (ADS)

    Yoon, Young Jun; Kang, Hee-Sung; Seo, Jae Hwa; Kim, Young-Jo; Bae, Jin-Hyuk; Lee, Jung-Hee; Kang, In Man; Cho, Seongjae; Cho, Eou-Sik

    2014-11-01

    We have investigated gallium-nitride (GaN)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) having a recessed-gate structure for high-power applications. Recessed-gate GaN-based MOSFETs have been designed with a dual high- k dielectric structure to overcome low current drivability. Compared to recessed-gate GaN-based MOSFETs having a single gate dielectric with the same oxide thickness, recessed-gate GaN-based MOSFETs having a dual high- k dielectric composed of Al2O3 and HfO2 have achieved a high drain current ( I D ) and transconductance ( g m ) due to the high dielectric constant of HfO2. Also, because the dual high- k dielectric forms a high electron density in the channel layer with outstanding gate control capability, low channel resistances ( R ch ) have obtained. In addition, we have studied the effect of the length between the gate and the drain ( L gd ) on the on-resistance ( R on ) to minimize the R on that is associated with power consumption and switching performance. Also, the electric field distribution of a device having a dual high- k dielectric has been examined with a field plate structure for high drive voltage. The proposed device was confirmed to be a remarkable candidate for switching devices in high-power applications.

  7. Impact of Gate and Passivation Structures on Current Collapse of AlGaN/GaN High-Electron-Mobility Transistors under Off-State-Bias Stress

    NASA Astrophysics Data System (ADS)

    Tajima, Masafumi; Hashizume, Tamotsu

    2011-06-01

    Using a dual-gate structure, we have investigated the impact of gate-stress position on the current collapse behavior of AlGaN/GaN high-electron-mobility transistors (HEMTs) without surface passivation. When the gate-bias stress under the off state was applied to the additional gate between the main gate and the drain electrode, we observed a marked increase in on-resistance (RON). On the other hand, the off-state stress on the main gate itself caused a decrease in drain saturation current as well as an increase in RON. The calculation of electric field at the AlGaN surface showed that the field peaks existed at the gate edges on both the drain and source sides, probably causing electron charging at the AlGaN surface near both gate-edge areas. These results indicated that the off-state gate stress induces “virtual gates” in the gate edges expanding in both the drain and source directions. The impacts of device structures on the current collapse have been characterized, using Schottky-gate HEMTs with and without surface passivation and metal-oxide-semiconductor (MOS) gate HEMTs. The surface passivation and MOS-gate structure was effective in mitigating current collapse, which was explained in terms of surface state density, electric field strength, and gate leakage current.

  8. Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

    PubMed

    Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

    2013-01-01

    A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

  9. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se{sub 2} thin-film solar cell absorbers

    SciTech Connect

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-21

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for “realistic” surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In{sub 1-x}Ga{sub x})Se{sub 2} thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH{sub 3}-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is – apart from a slight change in surface composition – identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  10. Monolithic metal oxide transistors.

    PubMed

    Choi, Yongsuk; Park, Won-Yeong; Kang, Moon Sung; Yi, Gi-Ra; Lee, Jun-Young; Kim, Yong-Hoon; Cho, Jeong Ho

    2015-04-28

    We devised a simple transparent metal oxide thin film transistor architecture composed of only two component materials, an amorphous metal oxide and ion gel gate dielectric, which could be entirely assembled using room-temperature processes on a plastic substrate. The geometry cleverly takes advantage of the unique characteristics of the two components. An oxide layer is metallized upon exposure to plasma, leading to the formation of a monolithic source-channel-drain oxide layer, and the ion gel gate dielectric is used to gate the transistor channel effectively at low voltages through a coplanar gate. We confirmed that the method is generally applicable to a variety of sol-gel-processed amorphous metal oxides, including indium oxide, indium zinc oxide, and indium gallium zinc oxide. An inverter NOT logic device was assembled using the resulting devices as a proof of concept demonstration of the applicability of the devices to logic circuits. The favorable characteristics of these devices, including (i) the simplicity of the device structure with only two components, (ii) the benign fabrication processes at room temperature, (iii) the low-voltage operation under 2 V, and (iv) the excellent and stable electrical performances, together support the application of these devices to low-cost portable gadgets, i.e., cheap electronics. PMID:25777338

  11. A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

    NASA Astrophysics Data System (ADS)

    Xu, Gao-Bo; Xu, Qiu-Xia; Yin, Hua-Xiang; Zhou, Hua-Jie; Yang, Tao; Niu, Jie-Bin; Yu, Jia-Han; Li, Jun-Feng; Zhao, Chao

    2013-11-01

    A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device's gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS = VDS = 1.5 V and the off-state current is only 4.4 nA/μm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The device's excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

  12. A novel 3D embedded gate field effect transistor - Screen-grid FET - Device concept and modelling

    NASA Astrophysics Data System (ADS)

    Fobelets, K.; Ding, P. W.; Velazquez-Perez, J. E.

    2007-05-01

    A novel 3D field effect transistor on SOI - screen-grid FET (SGrFET) - is proposed and an analysis of its DC behaviour is presented by means of 2D TCAD analysis. The novel feature of the SGrFET is the design of 3D insulated gate cylinders embedded in the SOI body. This novel gate topology improves efficiency and allows great flexibility in device and gate geometry to optimize DC performance. The floating body effect is avoided and the double gating row configuration controls short channel effects. The traditional intimate relationship between gate length and source-drain distance is removed, resulting in easy control of drain induced barrier lowering, improved output conductance and ideal sub-threshold slope. The separation between the gate fingers in each row is the key factor to optimize the performance, whilst downscaling of the source-drain distance and oxide thickness is not essential from an operational point of view. The device exhibits a huge potential in low power electronics as given by an efficiency of transconductance " gm/ Id" of 39 S/A at VDS = 100 mV over a large gate voltage range and at a source-drain distance of 825 nm. We present the modelling results of the influence of gate cylinder distribution in the channel, channel doping, gate oxide thickness, gate finger distance and source-drain distance on the characteristics of the device.

  13. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  14. Reversible logic gates on Physarum Polycephalum

    SciTech Connect

    Schumann, Andrew

    2015-03-10

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

  15. Ion polarization behavior in alumina under pulsed gate bias stress

    SciTech Connect

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-16

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K{sup +}), sodium (Na{sup +}), and lithium (Li{sup +}), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔV{sub th}) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔV{sub th} over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔV{sub th} from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  16. Ion polarization behavior in alumina under pulsed gate bias stress

    NASA Astrophysics Data System (ADS)

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-01

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K+), sodium (Na+), and lithium (Li+), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔVth) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔVth over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔVth from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  17. Operating principle and integration of in-plane gate logic devices

    NASA Astrophysics Data System (ADS)

    Komatsuzaki, Y.; Saba, K.; Onomitsu, K.; Yamaguchi, H.; Horikoshi, Y.

    2011-12-01

    Logic devices based on in-plane gate (IPG) transistors are realized and their electrical characteristics and integration are investigated. We present logic devices based on lateral gate structures using an additional IPG transistor as a load resistance. These logic devices show clear input-output characteristics and voltage transfer curves as a logic device and the Hi/Low ratio is high enough for reliable logic operations. Furthermore, the IPG logic devices operate at low current levels. Monolithic NOT-gate is demonstrated and the number of terminals and wiring are considerably reduced by using our IPG logic devices compared to logic devices based on CMOS transistors.

  18. A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high- k gate dielectrics

    NASA Astrophysics Data System (ADS)

    Chiang, T. K.; Chen, M. L.

    2007-03-01

    Based on the fully two-dimensional (2D) Poisson's solution in both silicon film and insulator layer, a compact and analytical threshold voltage model, which accounts for the fringing field effect of the short channel symmetrical double-gate (SDG) MOSFETs, has been developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel effects and high- k gate dielectrics assess their overall impact on SDG MOSFET's scaling. It is found that for the same equivalent oxide thickness, the gate insulator with high- k dielectric constant which keeps a great characteristic length allows less design space than SiO 2 to sustain the same FIBL induced threshold voltage degradation.

  19. Persistent optical gating of a topological insulator.

    PubMed

    Yeats, Andrew L; Pan, Yu; Richardella, Anthony; Mintun, Peter J; Samarth, Nitin; Awschalom, David D

    2015-10-01

    The spin-polarized surface states of topological insulators (TIs) are attractive for applications in spintronics and quantum computing. A central challenge with these materials is to reliably tune the chemical potential of their electrons with respect to the Dirac point and the bulk bands. We demonstrate persistent, bidirectional optical control of the chemical potential of (Bi,Sb)2Te3 thin films grown on SrTiO3. By optically modulating a space-charge layer in the SrTiO3 substrates, we induce a persistent field effect in the TI films comparable to electrostatic gating techniques but without additional materials or processing. This enables us to optically pattern arbitrarily shaped p- and n-type regions in a TI, which we subsequently image with scanning photocurrent microscopy. The ability to optically write and erase mesoscopic electronic structures in a TI may aid in the investigation of the unique properties of the topological insulating phase. The gating effect also generalizes to other thin-film materials, suggesting that these phenomena could provide optical control of chemical potential in a wide range of ultrathin electronic systems. PMID:26601300

  20. Persistent optical gating of a topological insulator

    PubMed Central

    Yeats, Andrew L.; Pan, Yu; Richardella, Anthony; Mintun, Peter J.; Samarth, Nitin; Awschalom, David D.

    2015-01-01

    The spin-polarized surface states of topological insulators (TIs) are attractive for applications in spintronics and quantum computing. A central challenge with these materials is to reliably tune the chemical potential of their electrons with respect to the Dirac point and the bulk bands. We demonstrate persistent, bidirectional optical control of the chemical potential of (Bi,Sb)2Te3 thin films grown on SrTiO3. By optically modulating a space-charge layer in the SrTiO3 substrates, we induce a persistent field effect in the TI films comparable to electrostatic gating techniques but without additional materials or processing. This enables us to optically pattern arbitrarily shaped p- and n-type regions in a TI, which we subsequently image with scanning photocurrent microscopy. The ability to optically write and erase mesoscopic electronic structures in a TI may aid in the investigation of the unique properties of the topological insulating phase. The gating effect also generalizes to other thin-film materials, suggesting that these phenomena could provide optical control of chemical potential in a wide range of ultrathin electronic systems. PMID:26601300

  1. Persistent optical gating of a topological insulator.

    PubMed

    Yeats, Andrew L; Pan, Yu; Richardella, Anthony; Mintun, Peter J; Samarth, Nitin; Awschalom, David D

    2015-10-01

    The spin-polarized surface states of topological insulators (TIs) are attractive for applications in spintronics and quantum computing. A central challenge with these materials is to reliably tune the chemical potential of their electrons with respect to the Dirac point and the bulk bands. We demonstrate persistent, bidirectional optical control of the chemical potential of (Bi,Sb)2Te3 thin films grown on SrTiO3. By optically modulating a space-charge layer in the SrTiO3 substrates, we induce a persistent field effect in the TI films comparable to electrostatic gating techniques but without additional materials or processing. This enables us to optically pattern arbitrarily shaped p- and n-type regions in a TI, which we subsequently image with scanning photocurrent microscopy. The ability to optically write and erase mesoscopic electronic structures in a TI may aid in the investigation of the unique properties of the topological insulating phase. The gating effect also generalizes to other thin-film materials, suggesting that these phenomena could provide optical control of chemical potential in a wide range of ultrathin electronic systems.

  2. The thinnest molecular separation sheet by graphene gates of single-walled carbon nanohorns.

    PubMed

    Ohba, Tomonori

    2014-11-25

    Graphene is possibly the thinnest membrane that could be used as a molecular separation gate. Several techniques including absorption, cryogenic distillation, adsorption, and membrane separation have been adopted for constructing separation systems. Molecular separation using graphene as the membrane has been studied because large area synthesis of graphene is possible by chemical vapor deposition. Control of the gate sizes is necessary to achieve high separation performances in graphene membranes. The separation of molecules and ions using graphene and graphene oxide layers could be achieved by the intrinsic defects and defect donation of graphene. However, the controllability of the graphene gates is still under debate because gate size control at the picometer level is inevitable for the fabrication of the thinnest graphene membranes. In this paper, the controlled gate size in the graphene sheets in single-walled carbon nanohorns (NHs) is studied and the molecular separation ability of the graphene sheets is assessed by molecular probing with CO2, O2, N2, CH4, and SF6. Graphene sheets in NHs with different sized gates of 310, 370, and >500 pm were prepared and assessed by molecular probing. The 310 pm-gates in the graphene sheets could separate the molecules tested, whereas weak separation properties were observed for 370 pm-gates. The amount of CO2 that penetrated the 310 pm-gates was more than 35 times larger than that of CH4. These results were supported by molecular dynamics simulations of the penetration of molecules through 300, 400, and 700 pm-gates in graphene sheets. Therefore, a gas separation membrane using a 340-pm-thick graphene sheet has high potential. These findings provide unambiguous evidence of the importance of graphene gates on the picometer level. Control of the gates is the primary challenge for high-performance separation membranes made of graphene. PMID:25347389

  3. Graphical workstation capability for reliability modeling

    NASA Technical Reports Server (NTRS)

    Bavuso, Salvatore J.; Koppen, Sandra V.; Haley, Pamela J.

    1992-01-01

    In addition to computational capabilities, software tools for estimating the reliability of fault-tolerant digital computer systems must also provide a means of interfacing with the user. Described here is the new graphical interface capability of the hybrid automated reliability predictor (HARP), a software package that implements advanced reliability modeling techniques. The graphics oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault-tree gates, including sequence-dependency gates, or by a Markov chain. By using this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain, which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the graphical kernal system (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing stages.

  4. The Gates, 1979-2005

    ERIC Educational Resources Information Center

    School Arts: The Art Education Magazine for Teachers, 2005

    2005-01-01

    One art critic called it pure Despite the mixed reviews of Christo and Jeanne-Claude's temporary art installation in New York's Central Park, the public reaction to The Gates was largely positive.The Gates consisted of 7,500 orange PVC frames straddling the park's walkways that varied in widths from 5 1/2 feet to 18 feet. Eight-foot-long ripstop…

  5. Input states for quantum gates

    SciTech Connect

    Gilchrist, A.; White, A.G.; Munro, W.J.

    2003-04-01

    We examine three possible implementations of nondeterministic linear optical controlled NOT gates with a view to an in-principle demonstration in the near future. To this end we consider demonstrating the gates using currently available sources, such as spontaneous parametric down conversion and coherent states, and current detectors only able to distinguish between zero and many photons. The demonstration is possible in the coincidence basis and the errors introduced by the nonoptimal input states and detectors are analyzed.

  6. Quantum gates with topological phases

    SciTech Connect

    Ionicioiu, Radu

    2003-09-01

    We investigate two models for performing topological quantum gates with the Aharonov-Bohm (AB) and Aharonov-Casher (AC) effects. Topological one- and two-qubit Abelian phases can be enacted with the AB effect using charge qubits, whereas the AC effect can be used to perform all single-qubit gates (Abelian and non-Abelian) for spin qubits. Possible experimental setups suitable for a solid-state implementation are briefly discussed.

  7. Latest design of gate valves

    SciTech Connect

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  8. Redox Regulation of Neuronal Voltage-Gated Calcium Channels

    PubMed Central

    Jevtovic-Todorovic, Vesna

    2014-01-01

    Abstract Significance: Voltage-gated calcium channels are ubiquitously expressed in neurons and are key regulators of cellular excitability and synaptic transmitter release. There is accumulating evidence that multiple subtypes of voltage-gated calcium channels may be regulated by oxidation and reduction. However, the redox mechanisms involved in the regulation of channel function are not well understood. Recent Advances: Several studies have established that both T-type and high-voltage-activated subtypes of voltage-gated calcium channel can be redox-regulated. This article reviews different mechanisms that can be involved in redox regulation of calcium channel function and their implication in neuronal function, particularly in pain pathways and thalamic oscillation. Critical Issues: A current critical issue in the field is to decipher precise mechanisms of calcium channel modulation via redox reactions. In this review we discuss covalent post-translational modification via oxidation of cysteine molecules and chelation of trace metals, and reactions involving nitric oxide-related molecules and free radicals. Improved understanding of the roles of redox-based reactions in regulation of voltage-gated calcium channels may lead to improved understanding of novel redox mechanisms in physiological and pathological processes. Future Directions: Identification of redox mechanisms and sites on voltage-gated calcium channel may allow development of novel and specific ion channel therapies for unmet medical needs. Thus, it may be possible to regulate the redox state of these channels in treatment of pathological process such as epilepsy and neuropathic pain. Antioxid. Redox Signal. 21, 880–891. PMID:24161125

  9. Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

    NASA Astrophysics Data System (ADS)

    Zhao-wen, Yan; Jiao, Wang; Jian-li, Qiao; Wen-jie, Chen; Pan, Yang; Tong, Xiao; Jian-hong, Yang

    2016-06-01

    A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated, in which polysilicon is sandwiched between oxide layers as a floating gate. Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed. The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing (P/E) operations at various P/E voltages are discussed. The simulated results show that present memory exhibits a large memory window of 57.5 V, and a high read current on/off ratio of ≈ 103. Compared with the reported experimental results, these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects, which shows great promise in device designing and practical application.

  10. Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

    PubMed

    Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

    2015-08-01

    In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. PMID:25349117

  11. Reliability model generator

    NASA Technical Reports Server (NTRS)

    McMann, Catherine M. (Inventor); Cohen, Gerald C. (Inventor)

    1991-01-01

    An improved method and system for automatically generating reliability models for use with a reliability evaluation tool is described. The reliability model generator of the present invention includes means for storing a plurality of low level reliability models which represent the reliability characteristics for low level system components. In addition, the present invention includes means for defining the interconnection of the low level reliability models via a system architecture description. In accordance with the principles of the present invention, a reliability model for the entire system is automatically generated by aggregating the low level reliability models based on the system architecture description.

  12. Quantum gate-set tomography

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    2014-03-01

    Quantum information technology is built on (1) physical qubits and (2) precise, accurate quantum logic gates that transform their states. Developing quantum logic gates requires good characterization - both in the development phase, where we need to identify a device's flaws so as to fix them, and in the production phase, where we need to make sure that the device works within specs and predict residual error rates and types. This task falls to quantum state and process tomography. But until recently, protocols for tomography relied on a pre-existing and perfectly calibrated reference frame comprising the measurements (and, for process tomography, input states) used to characterize the device. In practice, these measurements are neither independent nor perfectly known - they are usually implemented via exactly the same gates that we are trying to characterize! In the past year, several partial solutions to this self-consistency problem have been proposed. I will present a framework (gate set tomography, or GST) that addresses and resolves this problem, by self-consistently characterizing an entire set of quantum logic gates on a black-box quantum device. In particular, it contains an explicit closed-form protocol for linear-inversion gate set tomography (LGST), which is immune to both calibration error and technical pathologies like local maxima of the likelihood (which plagued earlier methods). GST also demonstrates significant (multiple orders of magnitude) improvements in efficiency over standard tomography by using data derived from long sequences of gates (much like randomized benchmarking). GST has now been applied to qubit devices in multiple technologies. I will present and discuss results of GST experiments in technologies including a single trapped-ion qubit and a silicon quantum dot qubit. Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U

  13. A detailed coupled-mode-space non-equilibrium Green's function simulation study of source-to-drain tunnelling in gate-all-around Si nanowire metal oxide semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Seoane, N.; Martinez, A.

    2013-09-01

    In this paper we present a 3D quantum transport simulation study of source-to-drain tunnelling in gate-all-around Si nanowire transistors by using the non-equilibrium Green's function approach. The impact of the channel length, device cross-section, and drain and gate applied biases on the source-to-drain tunnelling is examined in detail. The overall effect of tunnelling on the ID-VG characteristics is also investigated. Tunnelling in devices with channel lengths of 10 nm or less substantially enhances the off-current. This enhancement is more important at high drain biases and at larger cross-sections where the sub-threshold slope is substantially degraded. A less common effect is the increase in the on-current due to the tunnelling which contributes as much as 30% of the total on-current. This effect is almost independent of the cross-section, and it depends weakly on the studied channel lengths.

  14. Design of optical reversible logic gates using electro-optic effect of lithium niobate based Mach-Zehnder interferometers.

    PubMed

    Kumar, Santosh; Chanderkanta; Raghuwanshi, Sanjeev Kumar

    2016-07-20

    In recent years reversible logic has come as a promising solution in the optical computing domain. In reversible gates, there is one-to-one mapping between input and output, causing no loss of information. Reversible gates are useful for application in low power complementary metal-oxide semiconductors, with less dissipation, and in quantum computing. These benefits can be utilized by implementing reversible gate structures in the optical domain. In this paper, basic reversible Feynman and Fredkin logic gates using a lithium niobate based Mach-Zehnder interferometer are proposed. The different applications utilizing the proposed structures are also explained in this study.

  15. Design of optical reversible logic gates using electro-optic effect of lithium niobate based Mach-Zehnder interferometers.

    PubMed

    Kumar, Santosh; Chanderkanta; Raghuwanshi, Sanjeev Kumar

    2016-07-20

    In recent years reversible logic has come as a promising solution in the optical computing domain. In reversible gates, there is one-to-one mapping between input and output, causing no loss of information. Reversible gates are useful for application in low power complementary metal-oxide semiconductors, with less dissipation, and in quantum computing. These benefits can be utilized by implementing reversible gate structures in the optical domain. In this paper, basic reversible Feynman and Fredkin logic gates using a lithium niobate based Mach-Zehnder interferometer are proposed. The different applications utilizing the proposed structures are also explained in this study. PMID:27463925

  16. Controlled ambient and temperature treatment of InGaZnO thin film transistors for improved bias-illumination stress reliability

    SciTech Connect

    Vemuri, Rajitha N. P.; Hasin, Muhammad R.; Alford, T. L.

    2014-03-15

    The failure mechanisms arising from the instability in operation of indium gallium zinc oxide based thin film transistors (TFTs) upon prolonged real application stresses (bias and illumination) have been extensively studied and reported. Positive and negative gate bias conditions, along with high photonic energy wavelengths within visible light spectrum are used as stress conditions. The increased carrier concentration due to photonic excitation of defects within bandgap and ionization of deep level vacancies is compensated by the reduction in off currents under illumination due to the trapping of carriers in the intermetal dielectric. Band lowering at the source-channel junction due to accumulation of negative carriers repelled due to negative gate bias stress further causes high carrier flow into the channel and drives the devices into failure. The defect identification during failure and degradation assisted in proposing suitable low temperature post processing in specific ambients. Reliability tests after specific anneals in oxygen, vacuum, and forming gas ambients confirm the correlation of the defect type with anneal ambient. Annealed TFTs demonstrate high stabilities under illumination stresses and do not fail when subjected to combined stresses that cause failure in as-fabricated TFTs. Oxygen and forming gas anneals are impactful on the reliability and opens an area of study on donor and vacancy behavior in amorphous mixed oxide based TFTs. The subthreshold swing, field-effect mobilities, and off currents provide knowledge on best anneal practices by understanding role of hydrogen and oxygen in vacancy annihilation and transistor switching properties.

  17. Nonvolatile Memory Effect in Organic Thin-Film Transistor Based on Aluminum Nanoparticle Floating Gate

    NASA Astrophysics Data System (ADS)

    Wang, Wei; Ma, Dong-Ge

    2010-01-01

    A nonvolatile memory effect was observed in an organic thin-film transistor by introducing a Boating gate structure. The Boating gate was composed of an Al film in a thickness of nanometers, which was thermally deposited on a SiO2 insulator and exposed to air to spontaneously oxidize. It can be seen that the transistors exhibit significant hysteresis behaviors and storage circles in current-voltage characteristics in the dark and under illumination, indicating that the transistors may act as a nonvolatile memory element. The operational mechanism is discussed in the cases of dark and illumination via charge trapping by the Al floating gate.

  18. Advances in the metallurgical design of gate valves

    SciTech Connect

    Hays, C.

    1995-12-31

    Reliability and cost factors represent the two controlling forces for gate valves that contain state-of-the-art metallurgical improvements. Better and less-expensive gate valves are always in demand for the oil and gas or petrochemically-related industries. In this very specialized marketplace, environmental conditions are always the primary design challenge because service requirements typically involve high temperature, elevated pressure, extreme corrosion or erosion. A proper design selection for extended life under such harsh service will always involve the surface integrity for all effluent-wetted gate valve components. This paper gives a brief survey of gate valves in terms of the different design approaches that are used for oilfield and refinery applications. However, the main interest of this paper is devoted to modern surface treatment methods that enhance a cost attractive substrate to achieve a competitive and duplex or composite structure. For example, innovative processes are discussed relative to plating, hardfacing, thermal spray, conversion coatings, spray-fusion, weld-clad and HIC-ing.

  19. Alstom Francis Turbine Ring Gates: from Retrofitting to Commissioning

    NASA Astrophysics Data System (ADS)

    A, Nguyen P.; G, Labrecque; M-O, Thibault; M, Bergeron; A, Steinhilber; D, Havard

    2014-03-01

    The Ring Gate synchronisation system developed by Alstom is new and patented. It uses hydraulic cylinders connected in pairs by a serial connection. The new hydraulic synchronisation system, when compared to the previous mechanical synchronisation system, has several advantages. It is a compact design; it reduces the number of mechanical components as well as maintenance costs. The new system maintains the Ring Gates robustness. The new approach is an evolution from mechanical to hydraulic synchronization assisted by electronic control. The new synchronization system eliminates several mechanical components that used to add wear and friction and which are usually difficult to adjust during maintenance. Tension chains and sprockets and associated controls are eliminated. Through the position sensors, the redundancy of the ring gate synchronization system makes it predictable and reliable. The electronic control compensates for any variation in operation, for example a leak in the hydraulic system. An emergency closing is possible without the electronic control system due to the stiffness of hydraulic serial connection in the hydraulic cylinder pairs. The Ring Gate can work safely against uneven loads and frictions. The development will be reviewed and its application discussed through commissioning results.

  20. Positive-bias gate-controlled metal-insulator transition in ultrathin VO2 channels with TiO2 gate dielectrics

    NASA Astrophysics Data System (ADS)

    Yajima, Takeaki; Nishimura, Tomonori; Toriumi, Akira

    2015-12-01

    The next generation of electronics is likely to incorporate various functional materials, including those exhibiting ferroelectricity, ferromagnetism and metal-insulator transitions. Metal-insulator transitions can be controlled by electron doping, and so incorporating such a material in transistor channels will enable us to significantly modulate transistor current. However, such gate-controlled metal-insulator transitions have been challenging because of the limited number of electrons accumulated by gate dielectrics, or possible electrochemical reaction in ionic liquid gate. Here we achieve a positive-bias gate-controlled metal-insulator transition near the transition temperature. A significant number of electrons were accumulated via a high-permittivity TiO2 gate dielectric with subnanometre equivalent oxide thickness in the inverse-Schottky-gate geometry. An abrupt transition in the VO2 channel is further exploited, leading to a significant current modulation far beyond the capacitive coupling. This solid-state operation enables us to discuss the electrostatic mechanism as well as the collective nature of gate-controlled metal-insulator transitions, paving the pathway for developing functional field effect transistors.

  1. Positive-bias gate-controlled metal–insulator transition in ultrathin VO2 channels with TiO2 gate dielectrics

    PubMed Central

    Yajima, Takeaki; Nishimura, Tomonori; Toriumi, Akira

    2015-01-01

    The next generation of electronics is likely to incorporate various functional materials, including those exhibiting ferroelectricity, ferromagnetism and metal–insulator transitions. Metal–insulator transitions can be controlled by electron doping, and so incorporating such a material in transistor channels will enable us to significantly modulate transistor current. However, such gate-controlled metal–insulator transitions have been challenging because of the limited number of electrons accumulated by gate dielectrics, or possible electrochemical reaction in ionic liquid gate. Here we achieve a positive-bias gate-controlled metal–insulator transition near the transition temperature. A significant number of electrons were accumulated via a high-permittivity TiO2 gate dielectric with subnanometre equivalent oxide thickness in the inverse-Schottky-gate geometry. An abrupt transition in the VO2 channel is further exploited, leading to a significant current modulation far beyond the capacitive coupling. This solid-state operation enables us to discuss the electrostatic mechanism as well as the collective nature of gate-controlled metal–insulator transitions, paving the pathway for developing functional field effect transistors. PMID:26657761

  2. Reliability Generalization: "Lapsus Linguae"

    ERIC Educational Resources Information Center

    Smith, Julie M.

    2011-01-01

    This study examines the proposed Reliability Generalization (RG) method for studying reliability. RG employs the application of meta-analytic techniques similar to those used in validity generalization studies to examine reliability coefficients. This study explains why RG does not provide a proper research method for the study of reliability,…

  3. Quantum gates by periodic driving

    PubMed Central

    Shi, Z. C.; Wang, W.; Yi, X. X.

    2016-01-01

    Topological quantum computation has been extensively studied in the past decades due to its robustness against decoherence. One way to realize the topological quantum computation is by adiabatic evolutions—it requires relatively long time to complete a gate, so the speed of quantum computation slows down. In this work, we present a method to realize single qubit quantum gates by periodic driving. Compared to adiabatic evolution, the single qubit gates can be realized at a fixed time much shorter than that by adiabatic evolution. The driving fields can be sinusoidal or square-well field. With the sinusoidal driving field, we derive an expression for the total operation time in the high-frequency limit, and an exact analytical expression for the evolution operator without any approximations is given for the square well driving. This study suggests that the period driving could provide us with a new direction in regulations of the operation time in topological quantum computation. PMID:26911900

  4. Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

    NASA Technical Reports Server (NTRS)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.; Chen, Yuan

    2016-01-01

    Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

  5. Can There Be Reliability without "Reliability?"

    ERIC Educational Resources Information Center

    Mislevy, Robert J.

    2004-01-01

    An "Educational Researcher" article by Pamela Moss (1994) asks the title question, "Can there be validity without reliability?" Yes, she answers, if by reliability one means "consistency among independent observations intended as interchangeable" (Moss, 1994, p. 7), quantified by internal consistency indices such as KR-20 coefficients and…

  6. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Yu, Ai-Fang; Qi, Qiong; Jiang, Peng; Jiang, Chao

    2009-07-01

    Carrier mobility enhancement from 0.09 to 0.59 cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  7. Time delays in gated radiotherapy.

    PubMed

    Smith, Wendy L; Becker, Nathan

    2009-07-28

    In gated radiotherapy, the accuracy of treatment delivery is determined by the accuracy with which both the imaging and treatment beams are gated. If the time delays (the time between the target entering/leaving the gated region and the first/last image acquired or treatment beam on/off) for the imaging and treatment systems are in the opposite directions, they may increase the required internal target volume (ITV) margin, above that indicated by the tolerance for either system measured individually. We measured a gating system's time delay on 3 fluoroscopy systems, and 3 linear accelerator treatment beams, using a motion phantom of known geometry, varying gating type (amplitude vs. phase), beam energy, dose rate, and period. The average beam on imaging time delays were -0.04 +/- 0.05 s (amplitude, 1 SD), -0.11 +/- 0.04 s (phase); while the average beam off imaging time delays were -0.18 +/- 0.08 s (amplitude) and -0.15 +/- 0.04 s (phase). The average beam on treatment time delays were 0.09 +/- 0.02 s (amplitude, 1 SD), 0.10 +/- 0.03 s (phase); while the average beam off time delays for treatment beams were 0.08 +/- 0.02 s (amplitude) and 0.07 +/- 0.02 s (phase). The negative value indicates the images were acquired early, and the positive values show the treatment beam was triggered late. We present a technique for calculating the margin necessary to account for time delays and found that the difference between the imaging and treatment time delays required a significant increase in the ITV margin in the direction of tumor motion at the gated level.

  8. Localizing a gate in CFTR.

    PubMed

    Gao, Xiaolong; Hwang, Tzyh-Chang

    2015-02-24

    Experimental and computational studies have painted a picture of the chloride permeation pathway in cystic fibrosis transmembrane conductance regulator (CFTR) as a short narrow tunnel flanked by wider inner and outer vestibules. Although these studies also identified a number of transmembrane segments (TMs) as pore-lining, the exact location of CFTR's gate(s) remains unknown. Here, using a channel-permeant probe, [Au(CN)2](-), we provide evidence that CFTR bears a gate that coincides with the predicted narrow section of the pore defined as residues 338-341 in TM6. Specifically, cysteines introduced cytoplasmic to the narrow region (i.e., positions 344 in TM6 and 1148 in TM12) can be modified by intracellular [Au(CN)2](-) in both open and closed states, corroborating the conclusion that the internal vestibule does not harbor a gate. However, cysteines engineered to positions external to the presumed narrow region (e.g., 334, 335, and 337 in TM6) are all nonreactive toward cytoplasmic [Au(CN)2](-) in the absence of ATP, whereas they can be better accessed by extracellular [Au(CN)2](-) when the open probability is markedly reduced by introducing a second mutation, G1349D. As [Au(CN)2](-) and chloride ions share the same permeation pathway, these results imply a gate is situated between amino acid residues 337 and 344 along TM6, encompassing the very segment that may also serve as the selectivity filter for CFTR. The unique position of a gate in the middle of the ion translocation pathway diverges from those seen in ATP-binding cassette (ABC) transporters and thus distinguishes CFTR from other members of the ABC transporter family. PMID:25675504

  9. Trapped ion scaling with pulsed fast gates

    NASA Astrophysics Data System (ADS)

    Bentley, C. D. B.; Carvalho, A. R. R.; Hope, J. J.

    2015-10-01

    Fast entangling gates for trapped ion pairs offer vastly improved gate operation times relative to implemented gates, as well as approaches to trap scaling. Gates on a neighbouring ion pair only involve local ions when performed sufficiently fast, and we find that even a fast gate between a pair of distant ions with few degrees of freedom restores all the motional modes given more stringent gate speed conditions. We compare pulsed fast gate schemes, defined by a timescale faster than the trap period, and find that our proposed scheme has less stringent requirements on laser repetition rate for achieving arbitrary gate time targets and infidelities well below 10-4. By extending gate schemes to ion crystals, we explore the effect of ion number on gate fidelity for coupling two neighbouring ions in large crystals. Inter-ion distance determines the gate time, and a factor of five increase in repetition rate, or correspondingly the laser power, reduces the infidelity by almost two orders of magnitude. We also apply our fast gate scheme to entangle the first and last ions in a crystal. As the number of ions in the crystal increases, significant increases in the laser power are required to provide the short gate times corresponding to fidelity above 0.99.

  10. Novel Dielectrics for GaN Device Passivation and Improved Reliability

    NASA Astrophysics Data System (ADS)

    Ren, F.; Pearton, Stephen J.; Gila, B. P.; Abernathy, C. R.; Fitch, R. C.

    Proper surface cleaning processes and the type of passivation film (SiNX, Sc2O3, MgO) used to reduce the current collapse phenomena in the devices are very critical to reduce the inter-device isolation leakage currents in mesa-isolated AlGaN/GaN high electron mobility transistors and to improve reliability. Three different passivation layers (SiNX, MgO, and Sc2O3) were examined for their effectiveness in mitigating surface state-induced current collapse in AlGaN/GaN high electron mobility transistors (HEMTs). The plasma-enhanced chemical vapor deposited SiNX produced ~80-85% recovery of the drain-source current, independent of whether SiH4/NH3 or SiD4/ND3 plasma chemistries were employed. Both the Sc2O3 and MgO produced essentially complete recovery of the current in GaN-cap HEMT structures and ~80-95% recovery in AlGaN-cap structures. The Sc2O3 had superior long-term stability with no change in HEMT behavior over 5 months aging. The use of MOSFETs could allow the use of complementary devices, thus producing less power consumption and simpler circuit design. The same novel oxides employed for alleviating many of the problems encountered in current Schottky-based devices were successfully used as the gate dielectric for MOS-diode and MOSFETs. Both MgO and Sc2O3 were shown to provide low interface state densities (in the 1011 eV-1 cm-2 range) on n- and p-GaN, making them useful for gate dielectrics for metal-oxide-semiconductor (MOS) devices and also as surface passivation layers to mitigate current collapse in GaN/AlGaN high electron mobility transistors (HEMTs). Clear evidence of inversion was demonstrated in gate-controlled MOS p-GaN diodes using both types of oxide. Charge-pumping measurements on diodes undergoing a high temperature implant activation anneal showed a total surface state density of ~3×1012 cm-2. On HEMT structures, both oxides provided effective passivation of surface states and these devices showed improved output power. The MgO/GaN structures

  11. HELIOS Critical Design Review: Reliability

    NASA Technical Reports Server (NTRS)

    Benoehr, H. C.; Herholz, J.; Prem, H.; Mann, D.; Reichert, L.; Rupp, W.; Campbell, D.; Boettger, H.; Zerwes, G.; Kurvin, C.

    1972-01-01

    This paper presents Helios Critical Design Review Reliability form October 16-20, 1972. The topics include: 1) Reliability Requirement; 2) Reliability Apportionment; 3) Failure Rates; 4) Reliability Assessment; 5) Reliability Block Diagram; and 5) Reliability Information Sheet.

  12. Gated compressor, distortionless signal limiter

    NASA Technical Reports Server (NTRS)

    Woodbury, R. C. (Inventor)

    1974-01-01

    A distortionless gated compressor for limiting the amplitude of a signal so as not to produce undesired signal levels responsive thereto is disclosed. The gated compressor includes a distortionless multiplier which multiplies an AC signal from a factor defined by a DC control signal. The compressor includes a plurality of channels each responsive to a signal produced in response to the multiplier's output. When the signal supplied to any channel exceeds a prescribed level, the level of the DC control signal is reduced to reduce the multiplier's output level and thereby prevent the signal applied to any channel from exceeding its prescribed level.

  13. HELLS GATE ROADLESS AREA, ARIZONA.

    USGS Publications Warehouse

    Conway, Clay M.; McColly, Robert A.

    1984-01-01

    Although no mineral-resource potential was identified in the Hells Gate Roadless Area during mineral surveys, the area is largely underlain by a regionally extensive Proterozoic granite-rhyolite complex which is tin-bearing. The geologic setting precludes the occurrence of fossil fuel resources and no other energy resources were identified. The potential for tin and associated metals in the Hells Gate Roadless Area and the region cannot be fully evaluated at this point. The granophyre and the upper part of the granite pluton along the northwestern margin of the area should be explored.

  14. Dual gated nuclear cardiac images

    SciTech Connect

    Zubal, I.G.; Bennett, G.W.; Bizais, Y.; Brill, A.B.

    1984-02-01

    A data acquisition system has been developed to collect camera events simultaneously with continually digitized electrocardiograph signals and respiratory flow measurements. Software processing of the list mode data creates more precisely gated cardiac frames. Additionally, motion blur due to heart movement during breathing is reduced by selecting events within a specific respiratory phase. Thallium myocardium images of a healthy volunteer show increased definition. This technique of combined cardiac and respiratory gating has the potential of improving the detectability of small lesions, and the characterization of cardiac wall motion.

  15. SiC Power MOSFET with Improved Gate Dielectric

    SciTech Connect

    Sbrockey, Nick M; Tompa, Gary S; Spencer, Michael G; Chandrashekhar, Chandra MVS

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  16. Analysis of nickel-cadmium battery reliability data containing zero failures

    NASA Technical Reports Server (NTRS)

    Denson, William K.; Klein, Glenn C.

    1992-01-01

    An analysis of reliability data on Nickel-Cadmium (NiCd) batteries (for use in spacecraft) is presented. The data were collected by Gates Aerospace and represent a substantial reliability database. The data were taken from the performance of 183 satellites which were in operation from between .1 and 22 years, for a total of 278 million cell-hours of operation.

  17. Gating geometry studies of thin-walled 17-4PH investment castings

    SciTech Connect

    Maguire, M.C.; Zanner, F.J.

    1992-01-01

    The ability to design gating systems that reliably feed and support investment castings is often the result of cut-and-try'' methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channel thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.

  18. Gating geometry studies of thin-walled 17-4PH investment castings

    SciTech Connect

    Maguire, M.C.; Zanner, F.J.

    1992-11-01

    The ability to design gating systems that reliably feed and support investment castings is often the result of ``cut-and-try`` methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channel thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.

  19. Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy

    SciTech Connect

    Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki

    2011-04-15

    Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.

  20. Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

    NASA Astrophysics Data System (ADS)

    Berl, M.; Tiemann, L.; Dietsche, W.; Karl, H.; Wegscheider, W.

    2016-03-01

    We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 106 cm2/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES, thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.

  1. Acute aortic syndromes: new insights from electrocardiographically gated computed tomography.

    PubMed

    Fleischmann, Dominik; Mitchell, R Scott; Miller, D Craig

    2008-01-01

    The development of retrospective electrocardiographic (ECG)-gating has proved to be a diagnostic and therapeutic boon for computed tomography (CT) imaging of patients with acute thoracic aortic diseases, such as aortic dissection/intramural hematoma (AD/IMH), penetrating atherosclerotic ulcer (APU), and ruptured/leaking aneurysm. The notorious pulsation motion artifacts in the ascending aorta confounding regular CT scanning can be eliminated, and involvement of the sinuses of Valsalva, the valve cusps, the aortic annulus, and the coronary arteries in aortic dissection can be clearly depicted or excluded. Motion-free images also allow reliable identification of the site of the primary intimal tear, the location, and extent of the intimomedial flap, and branch artery involvement. ECG-gated CTA also allows the detection of more subtle lesions and variants of aortic dissection, which may ultimately expand our understanding of these complex, life-threatening disorders.

  2. Acute aortic syndromes: new insights from electrocardiographically gated computed tomography.

    PubMed

    Fleischmann, Dominik; Mitchell, R Scott; Miller, D Craig

    2008-01-01

    The development of retrospective electrocardiographic (ECG)-gating has proved to be a diagnostic and therapeutic boon for computed tomography (CT) imaging of patients with acute thoracic aortic diseases, such as aortic dissection/intramural hematoma (AD/IMH), penetrating atherosclerotic ulcer (APU), and ruptured/leaking aneurysm. The notorious pulsation motion artifacts in the ascending aorta confounding regular CT scanning can be eliminated, and involvement of the sinuses of Valsalva, the valve cusps, the aortic annulus, and the coronary arteries in aortic dissection can be clearly depicted or excluded. Motion-free images also allow reliable identification of the site of the primary intimal tear, the location, and extent of the intimomedial flap, and branch artery involvement. ECG-gated CTA also allows the detection of more subtle lesions and variants of aortic dissection, which may ultimately expand our understanding of these complex, life-threatening disorders. PMID:19251175

  3. Demonstration of large field effect in topological insulator films via a high-κ back gate

    NASA Astrophysics Data System (ADS)

    Wang, C. Y.; Lin, H. Y.; Yang, S. R.; Chen, K. H. M.; Lin, Y. H.; Chen, K. H.; Young, L. B.; Cheng, C. K.; Fanchiang, Y. T.; Tseng, S. C.; Hong, M.; Kwo, J.

    2016-05-01

    The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi2Se3 films 6-10 quintuple layer (QL) thick with amorphous high-κ oxides of Al2O3 and Y2O3. Large gating effect of tuning the Fermi level EF to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO2 back gate, and the modulation of film resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN2D/ΔVg varies with TI film thickness as ˜t-0.75. To enhance the gating effect, a Y2O3 layer thickness 4 nm was inserted into Al2O3 gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi2Se3 to form Bi2TexSe1-x. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the EF very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable EF for dissipationless spintronics based on well-established semiconductor technology.

  4. Perchlorate Reductase Is Distinguished by Active Site Aromatic Gate Residues.

    PubMed

    Youngblut, Matthew D; Tsai, Chi-Lin; Clark, Iain C; Carlson, Hans K; Maglaqui, Adrian P; Gau-Pan, Phonchien S; Redford, Steven A; Wong, Alan; Tainer, John A; Coates, John D

    2016-04-22

    Perchlorate is an important ion on both Earth and Mars. Perchlorate reductase (PcrAB), a specialized member of the dimethylsulfoxide reductase superfamily, catalyzes the first step of microbial perchlorate respiration, but little is known about the biochemistry, specificity, structure, and mechanism of PcrAB. Here we characterize the biophysics and phylogeny of this enzyme and report the 1.86-Å resolution PcrAB complex crystal structure. Biochemical analysis revealed a relatively high perchlorate affinity (Km = 6 μm) and a characteristic substrate inhibition compared with the highly similar respiratory nitrate reductase NarGHI, which has a relatively much lower affinity for perchlorate (Km = 1.1 mm) and no substrate inhibition. Structural analysis of oxidized and reduced PcrAB with and without the substrate analog SeO3 (2-) bound to the active site identified key residues in the positively charged and funnel-shaped substrate access tunnel that gated substrate entrance and product release while trapping transiently produced chlorate. The structures suggest gating was associated with shifts of a Phe residue between open and closed conformations plus an Asp residue carboxylate shift between monodentate and bidentate coordination to the active site molybdenum atom. Taken together, structural and mutational analyses of gate residues suggest key roles of these gate residues for substrate entrance and product release. Our combined results provide the first detailed structural insight into the mechanism of biological perchlorate reduction, a critical component of the chlorine redox cycle on Earth.

  5. Loss performance and efficiency comparison of resonant gate drivers

    NASA Astrophysics Data System (ADS)

    Kim, I.-G.; Kwak, S.-S.

    2016-02-01

    In an effort to reduce switching and gate-drive losses in power converters when the energy density is increased by increasing the switching frequency, various resonant gate drivers (RGDs) based on a current source have been proposed to drive metal-oxide-semiconductor field-effect transistors in low-voltage high-current power converters. The resonant gate drivers enable high efficiency owing to energy recovery and the reduction of switching losses. Recently, many studies have been performed on the design of new topologies and loss analyses. Despite numerous proposed studies on RGDs, a comparative study based on a theoretical analysis has not been carried out. In this paper, a theoretical loss analysis in terms of the conduction, switching and gate-drive losses is presented according to the operation stages. In particular, the conduction loss has been expressed in terms of a general loss model that can generally applied to all topologies. Five RGD topologies are evaluated for their efficiency performance with analytical expressions and features based on several operating conditions.

  6. Perchlorate Reductase Is Distinguished by Active Site Aromatic Gate Residues.

    PubMed

    Youngblut, Matthew D; Tsai, Chi-Lin; Clark, Iain C; Carlson, Hans K; Maglaqui, Adrian P; Gau-Pan, Phonchien S; Redford, Steven A; Wong, Alan; Tainer, John A; Coates, John D

    2016-04-22

    Perchlorate is an important ion on both Earth and Mars. Perchlorate reductase (PcrAB), a specialized member of the dimethylsulfoxide reductase superfamily, catalyzes the first step of microbial perchlorate respiration, but little is known about the biochemistry, specificity, structure, and mechanism of PcrAB. Here we characterize the biophysics and phylogeny of this enzyme and report the 1.86-Å resolution PcrAB complex crystal structure. Biochemical analysis revealed a relatively high perchlorate affinity (Km = 6 μm) and a characteristic substrate inhibition compared with the highly similar respiratory nitrate reductase NarGHI, which has a relatively much lower affinity for perchlorate (Km = 1.1 mm) and no substrate inhibition. Structural analysis of oxidized and reduced PcrAB with and without the substrate analog SeO3 (2-) bound to the active site identified key residues in the positively charged and funnel-shaped substrate access tunnel that gated substrate entrance and product release while trapping transiently produced chlorate. The structures suggest gating was associated with shifts of a Phe residue between open and closed conformations plus an Asp residue carboxylate shift between monodentate and bidentate coordination to the active site molybdenum atom. Taken together, structural and mutational analyses of gate residues suggest key roles of these gate residues for substrate entrance and product release. Our combined results provide the first detailed structural insight into the mechanism of biological perchlorate reduction, a critical component of the chlorine redox cycle on Earth. PMID:26940877

  7. Assuring reliability program effectiveness.

    NASA Technical Reports Server (NTRS)

    Ball, L. W.

    1973-01-01

    An attempt is made to provide simple identification and description of techniques that have proved to be most useful either in developing a new product or in improving reliability of an established product. The first reliability task is obtaining and organizing parts failure rate data. Other tasks are parts screening, tabulation of general failure rates, preventive maintenance, prediction of new product reliability, and statistical demonstration of achieved reliability. Five principal tasks for improving reliability involve the physics of failure research, derating of internal stresses, control of external stresses, functional redundancy, and failure effects control. A final task is the training and motivation of reliability specialist engineers.

  8. P-channel silicone gate FET

    NASA Technical Reports Server (NTRS)

    Ostis, S.; Woo, D. S.

    1973-01-01

    Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.

  9. Double-disc gate valve

    DOEpatents

    Wheatley, Seth J.

    1979-01-01

    This invention relates to an improvement in a conventional double-disc gate valve having a vertically movable gate assembly including a wedge, spreaders slidably engaged therewtih, a valve disc carried by the spreaders. When the gate assembly is lowered to a selected point in the valve casing, the valve discs are moved transversely outward to close inlet and outlet ports in the casing. The valve includes hold-down means for guiding the disc-and-spreader assemblies as they are moved transversely outward and inward. If such valves are operated at relatively high differential pressures, they sometimes jam during opening. Such jamming has been a problem for many years in gate valves used in gaseous diffusion plants for the separtion of uranium isotopes. The invention is based on the finding that the above-mentioned jamming results when the outlet disc tilts about its horizontal axis in a certain way during opening of the valve. In accordance with the invention, tilting of the outlet disc is maintained at a tolerable value by providing the disc with a rigid downwardly extending member and by providing the casing with a stop for limiting inward arcuate movement of the member to a preselected value during opening of the valve.

  10. Bill Gates eyes healthcare market.

    PubMed

    Dunbar, C

    1995-02-01

    The entrepreneurial spirit is still top in Bill Gates' mind as he look toward healthcare and other growth industries. Microsoft's CEO has not intention of going the way of other large technology companies that became obsolete before they could compete today.

  11. Developing ICALL Tools Using GATE

    ERIC Educational Resources Information Center

    Wood, Peter

    2008-01-01

    This article discusses the use of the General Architecture for Text Engineering (GATE) as a tool for the development of ICALL and NLP applications. It outlines a paradigm shift in software development, which is mainly influenced by projects such as the Free Software Foundation. It looks at standards that have been proposed to facilitate the…

  12. Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

    NASA Technical Reports Server (NTRS)

    Danchenko, V. (Inventor)

    1974-01-01

    A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

  13. Impact of La{sub 2}O{sub 3} interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks deposited by atomic-layer-deposition

    SciTech Connect

    Chang, C.-Y. Takenaka, M.; Takagi, S.; Ichikawa, O.; Osada, T.; Hata, M.; Yamada, H.

    2015-08-28

    We examine the electrical properties of atomic layer deposition (ALD) La{sub 2}O{sub 3}/InGaAs and Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD La{sub 2}O{sub 3}/InGaAs interface provides low interface state density (D{sub it}) with the minimum value of ∼3 × 10{sup 11} cm{sup −2} eV{sup −1}, which is attributable to the excellent La{sub 2}O{sub 3} passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in La{sub 2}O{sub 3}. In order to simultaneously satisfy low D{sub it} and small hysteresis, the effectiveness of Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks with ultrathin La{sub 2}O{sub 3} interfacial layers is in addition evaluated. The reduction of the La{sub 2}O{sub 3} thickness to 0.4 nm in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, D{sub it} of the Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs interfaces becomes higher than that of the La{sub 2}O{sub 3}/InGaAs ones, attributable to the diffusion of Al{sub 2}O{sub 3} through La{sub 2}O{sub 3} into InGaAs and resulting modification of the La{sub 2}O{sub 3}/InGaAs interface structure. As a result of the effective passivation effect of La{sub 2}O{sub 3} on InGaAs, however, the Al{sub 2}O{sub 3}/10 cycle (0.4 nm) La{sub 2}O{sub 3}/InGaAs gate stacks can realize still lower D{sub it} with maintaining small hysteresis and low leakage current than the conventional Al{sub 2}O{sub 3}/InGaAs MOS interfaces.

  14. Experimental study of time-dependent dielectric breakdown in tri-gate nanowire transistor

    NASA Astrophysics Data System (ADS)

    Ota, Kensuke; Tanaka, Chika; Numata, Toshinori; Matsushita, Daisuke; Saitoh, Masumi

    2016-08-01

    We systematically investigate the size dependence of the time-dependent dielectric breakdown (TDDB) in a tri-gate nanowire transistor (NW Tr.). It is newly found that TDDB reliability is degraded in NW Tr. as compared with that in a planar transistor owing to the locally enhanced electric field at the NW corner. Moreover, in the region with a width (W) less than 40 nm, nanowire width reduction leads to a shorter time to gate dielectric breakdown indicating additional degradation of TDDB reliability in NW Tr. with smaller W. Although TDDB in three-dimensional (3D) MOS structures such as a trench MOS capacitor has already been reported, the size dependence of TDDB in scaled NW Tr. is firstly discussed in this paper since a trench capacitor is different from recent NW Tr. in structure, device size, gate dielectric thickness, and scaling effect on TDDB.

  15. Self-Assembled in-Plane-Gate Thin-Film Transistors Gated by WOx Solid-State Electrolytes

    NASA Astrophysics Data System (ADS)

    Zhu, De-Ming; Men, Chuan-Ling; Wan, Xiang; Deng, Chuang; Li, Zhen-Peng

    2013-08-01

    Low-voltage WOx gated indium-zinc-oxide thin-film transistors (TFTs) with in-plane-gate structures are fabricated by using an extremely simplified one-shadow mask method at room temperature. The proton conductive WOx solid-state electrolyte is demonstrated to form an electric-double-layer (EDL) effect associated with a huge capacitance of 0.51 μF/cm2. The special EDL capacitance of the WOx electrolyte is also extended to novel in-plane-gate structure TFTs as the gate dielectric, reducing the operating voltage to 1.8 V. Such TFTs operate at n-type depletion mode with a threshold voltage of -0.5 V, saturation electron mobility of 13.2 cm2/V·s, ON/OFF ratio of 1.7 × 106, subthreshold swing of 110 mV/dec, and low leakage current less than 7 nA. The hysteresis window of the transfer curves is also explained by an unique reaction within the WOx electrolyte.

  16. Enhancement mode AlGaN/GaN MOS high-electron-mobility transistors with ZrO2 gate dielectric deposited by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Anderson, Travis J.; Wheeler, Virginia D.; Shahin, David I.; Tadjer, Marko J.; Koehler, Andrew D.; Hobart, Karl D.; Christou, Aris; Kub, Francis J.; Eddy, Charles R., Jr.

    2016-07-01

    Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) in high-power RF and power switching are driving the need for insulated gate technology. We present a metal-oxide-semiconductor (MOS) gate structure using atomic-layer-deposited ZrO2 as a high-k, high-breakdown gate dielectric for reduced gate leakage and a recessed barrier structure for enhancement mode operation. Compared to a Schottky metal-gate HEMT, the recessed MOS-HEMT structure demonstrated a reduction in the gate leakage current by 4 orders of magnitude and a threshold voltage shift of +6 V to a record +3.99 V, enabled by a combination of a recessed barrier structure and negative oxide charge.

  17. Human Reliability Program Overview

    SciTech Connect

    Bodin, Michael

    2012-09-25

    This presentation covers the high points of the Human Reliability Program, including certification/decertification, critical positions, due process, organizational structure, program components, personnel security, an overview of the US DOE reliability program, retirees and academia, and security program integration.

  18. Power electronics reliability analysis.

    SciTech Connect

    Smith, Mark A.; Atcitty, Stanley

    2009-12-01

    This report provides the DOE and industry with a general process for analyzing power electronics reliability. The analysis can help with understanding the main causes of failures, downtime, and cost and how to reduce them. One approach is to collect field maintenance data and use it directly to calculate reliability metrics related to each cause. Another approach is to model the functional structure of the equipment using a fault tree to derive system reliability from component reliability. Analysis of a fictitious device demonstrates the latter process. Optimization can use the resulting baseline model to decide how to improve reliability and/or lower costs. It is recommended that both electric utilities and equipment manufacturers make provisions to collect and share data in order to lay the groundwork for improving reliability into the future. Reliability analysis helps guide reliability improvements in hardware and software technology including condition monitoring and prognostics and health management.

  19. Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

    NASA Technical Reports Server (NTRS)

    Straka, Bartholomew

    2013-01-01

    Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

  20. Reliable Design Versus Trust

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth A.

    2016-01-01

    This presentation focuses on reliability and trust for the users portion of the FPGA design flow. It is assumed that the manufacturer prior to hand-off to the user tests FPGA internal components. The objective is to present the challenges of creating reliable and trusted designs. The following will be addressed: What makes a design vulnerable to functional flaws (reliability) or attackers (trust)? What are the challenges for verifying a reliable design versus a trusted design?

  1. The role of ZrN capping layer deposited on ultra-thin high-k Zr-doped yttrium oxide for metal-gate metal-insulator-semiconductor applications

    NASA Astrophysics Data System (ADS)

    Juan, Pi-Chun; Mong, Fan-Chen; Huang, Jen-Hung

    2013-08-01

    Metal-gate MIS structures with and without ZrN capping layer on high-k Y2O3:Zr/Y2O3 stack were fabricated. The binding energies and depth profiles were investigated by x-ray photoelectron spectroscopy (XPS). The x-ray diffraction (XRD) patterns were compared. It is found that Ti out-diffusion into Zr-based high-k dielectric becomes lesser with the insertion of ZrN capping layer. The electrical properties of current-voltage (I-V) and capacitance-voltage (C-V) characteristics were measured in the postannealing temperature range of 550-850 °C. According to the defect reaction model, Zr cation vacancies are associated with the concentration of Ti ion by a transition from +3 to +2 states. The amount of Zr cation vacancies is quantified and equal to a half of Ti substitution amount at Zr site. The reduction in cation vacancies at high temperatures can well explain the decrease in ΔVFB for samples with ZrN layer. In contrast, an excess of Ti outdiffusion will produce the interstitial defects in high-k films without ZrN capping.

  2. Investigation of gate leakage mechanism in Al{sub 2}O{sub 3}/Al{sub 0.55}Ga{sub 0.45}N/GaN metal-oxide-semiconductor high-electron-mobility transistors

    SciTech Connect

    Zhu, Jie-Jie; Ma, Xiao-Hua Hou, Bin; Chen, Wei-Wei; Hao, Yue

    2014-04-14

    The mechanism of both reverse and forward gate leakage currents in Al{sub 2}O{sub 3}/Al{sub 0.55}Ga{sub 0.45}N/GaN structures was studied in this Letter by temperature-dependent current-voltage measurement. Poole–Frenkel (PF) emission, an oxygen vacancy-assisted process, was deduced as the dominant mechanism at high-temperatures (>388 K), and the leakage current at mid-temperatures (<388 K) were found greatly impacted by temperature-independent tunneling current. The reverse PF mission current in low-field, mid-field, and high-field region were related to trap states with activation energy of 0.41 eV, 0.49 eV, and 0.71 eV, respectively, and the activation energy of trap states for forward PF emission current was derived as 0.65 eV.

  3. A multi-radar wireless system for respiratory gating and accurate tumor tracking in lung cancer radiotherapy.

    PubMed

    Gu, Changzhan; Li, Ruijiang; Jiang, Steve B; Li, Changzhi

    2011-01-01

    Respiratory gating and tumor tracking are two promising motion-adaptive lung cancer treatments, minimizing incidence and severity of normal tissues and precisely delivering radiation dose to the tumor. Accurate respiration measurement is important in respiratory-gated radiotherapy. Conventional gating techniques are either invasive to the body or bring insufficient accuracy and discomfort to the patients. In this paper, we present an accurate noncontact means of measuring respiration for the use in gated lung cancer radiotherapy. We also present an accurate tumor tracking technique for dynamical beam tracking radiotherapy. Two 2.4 GHz miniature radars were used to monitor the chest wall and abdominal movements simultaneously to get high resolution and enhanced parameter identification. Ray tracing technique was used to investigate the impact of antenna size in clinical practice. It is shown that our multiple radar system can reliably measure respiration signals for respiratory gating and accurate tumor tracking in motion-adaptive lung cancer radiotherapy.

  4. Environmental noise reduction for holonomic quantum gates

    SciTech Connect

    Parodi, Daniele; Zanghi, Nino; Sassetti, Maura; Solinas, Paolo

    2007-07-15

    We study the performance of holonomic quantum gates, driven by lasers, under the effect of a dissipative environment modeled as a thermal bath of oscillators. We show how to enhance the performance of the gates by a suitable choice of the loop in the manifold of the controllable parameters of the laser. For a simplified, albeit realistic model, we find the surprising result that for a long time evolution the performance of the gate (properly estimated in terms of average fidelity) increases. On the basis of this result, we compare holonomic gates with the so-called stimulated raman adiabatic passage (STIRAP) gates.

  5. Digital avionics design and reliability analyzer

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The description and specifications for a digital avionics design and reliability analyzer are given. Its basic function is to provide for the simulation and emulation of the various fault-tolerant digital avionic computer designs that are developed. It has been established that hardware emulation at the gate-level will be utilized. The primary benefit of emulation to reliability analysis is the fact that it provides the capability to model a system at a very detailed level. Emulation allows the direct insertion of faults into the system, rather than waiting for actual hardware failures to occur. This allows for controlled and accelerated testing of system reaction to hardware failures. There is a trade study which leads to the decision to specify a two-machine system, including an emulation computer connected to a general-purpose computer. There is also an evaluation of potential computers to serve as the emulation computer.

  6. Reliability in aposematic signaling

    PubMed Central

    2010-01-01

    In light of recent work, we will expand on the role and variability of aposematic signals. The focus of this review will be the concepts of reliability and honesty in aposematic signaling. We claim that reliable signaling can solve the problem of aposematic evolution, and that variability in reliability can shed light on the complexity of aposematic systems. PMID:20539774

  7. Viking Lander reliability program

    NASA Technical Reports Server (NTRS)

    Pilny, M. J.

    1978-01-01

    The Viking Lander reliability program is reviewed with attention given to the development of the reliability program requirements, reliability program management, documents evaluation, failure modes evaluation, production variation control, failure reporting and correction, and the parts program. Lander hardware failures which have occurred during the mission are listed.

  8. Reliability as Argument

    ERIC Educational Resources Information Center

    Parkes, Jay

    2007-01-01

    Reliability consists of both important social and scientific values and methods for evidencing those values, though in practice methods are often conflated with the values. With the two distinctly understood, a reliability argument can be made that articulates the particular reliability values most relevant to the particular measurement situation…

  9. Reliability model generator specification

    NASA Technical Reports Server (NTRS)

    Cohen, Gerald C.; Mccann, Catherine

    1990-01-01

    The Reliability Model Generator (RMG), a program which produces reliability models from block diagrams for ASSIST, the interface for the reliability evaluation tool SURE is described. An account is given of motivation for RMG and the implemented algorithms are discussed. The appendices contain the algorithms and two detailed traces of examples.

  10. Product manufacturing, quality, and reliability initiatives to maintain a competitive advantage and meet customer expectations in the semiconductor industry

    NASA Astrophysics Data System (ADS)

    Capps, Gregory

    Semiconductor products are manufactured and consumed across the world. The semiconductor industry is constantly striving to manufacture products with greater performance, improved efficiency, less energy consumption, smaller feature sizes, thinner gate oxides, and faster speeds. Customers have pushed towards zero defects and require a more reliable, higher quality product than ever before. Manufacturers are required to improve yields, reduce operating costs, and increase revenue to maintain a competitive advantage. Opportunities exist for integrated circuit (IC) customers and manufacturers to work together and independently to reduce costs, eliminate waste, reduce defects, reduce warranty returns, and improve quality. This project focuses on electrical over-stress (EOS) and re-test okay (RTOK), two top failure return mechanisms, which both make great defect reduction opportunities in customer-manufacturer relationship. Proactive continuous improvement initiatives and methodologies are addressed with emphasis on product life cycle, manufacturing processes, test, statistical process control (SPC), industry best practices, customer education, and customer-manufacturer interaction.

  11. Plasma-assisted low energy N2 implant for Vfb tuning of Ge gate stacks

    NASA Astrophysics Data System (ADS)

    Kothari, Shraddha; Joishi, Chandan; Nejad, Hasan; Variam, Naushad; Lodha, Saurabh

    2016-08-01

    This work reports Vfb tuning of TiN/HfO2 gate stacks on Ge using low energy plasma-assisted doping with N2 without significant impact on gate capacitance and gate/channel interface trap densities. As required for multi-VT Ge p-FinFETs, controlled change in effective work function up to 180 mV from the near midgap to the near valence band edge of Ge is demonstrated by varying implant dose and energy. Unlike Si gate stacks, increased gate leakage in implanted Ge gate stacks is shown to result from traps created in the HfO2 layer during the implant and exposed to channel carriers due to a low band offset GeO2 interfacial layer (IL). Recovery of gate leakage is demonstrated by substituting GeO2 with an Al2O3 IL. Further, a simple physical model is proposed to extract the work function and oxide charge components of the change in Vfb for varying implant doses and energies.

  12. Radioactive Reliability of Programmable Memories

    NASA Astrophysics Data System (ADS)

    Loncar, Boris; Osmokrovic, Predrag; Stojanovic, Marko; Stankovic, Srboljub

    2001-02-01

    In this study, we examine the reliability of erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) components under the influence of gamma radiation. This problem has significance in military industry and space technology. Total dose results are presented for the JL 27C512D EPROM and 28C64C EEPROM components. There is evidence that EPROM components have better radioactive reliability than EEPROM components. Also, the changes to the EPROM are reversible, and after erasing and reprogramming all EPROM components are functional. On the other hand, changes to the EEPROM are irreversible, and under the influence of gamma radiation, all EEPROM components became permanently nonfunctional. The obtained results are analyzed and explained via the interaction of gamma radiation with oxide layers.

  13. Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

    NASA Astrophysics Data System (ADS)

    Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

    2013-11-01

    We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

  14. The impact of energy barrier height on border traps in the metal insulator semicondoctor gate stacks on III-V semiconductors

    NASA Astrophysics Data System (ADS)

    Yoshida, Shinichi; Taniguchi, Satoshi; Minari, Hideki; Lin, Dennis; Ivanov, Tsvetan; Watanabe, Heiji; Nakazawa, Masashi; Collaert, Nadine; Thean, Aaron

    2016-08-01

    We investigated the effect of a thin interfacial layer (IL) made of silicon or germanium between high-k dielectrics and III-V semiconductors on the frequency dispersion of the capacitance-voltage (C-V) curves in detail. We demonstrated experimentally that the frequency dispersion at accumulation voltage is strongly dependent on the energy barrier height (ΦB) between high-k dielectrics and semiconductors. It was revealed that the improvement of frequency dispersion for n-type III-V semiconductors with IL is attributed to the increase in ΦB realized by inserting Ge IL. Moreover, the border trap density did not necessarily decrease with IL through the assessment of border trap density using a distributed bulk-oxide trap model. Finally, we proved that it is important to increase ΦB to suppress the carrier exchange and improve high-k/III-V gate stack reliability.

  15. The impact of energy barrier height on border traps in the metal insulator semicondoctor gate stacks on III–V semiconductors

    NASA Astrophysics Data System (ADS)

    Yoshida, Shinichi; Taniguchi, Satoshi; Minari, Hideki; Lin, Dennis; Ivanov, Tsvetan; Watanabe, Heiji; Nakazawa, Masashi; Collaert, Nadine; Thean, Aaron

    2016-08-01

    We investigated the effect of a thin interfacial layer (IL) made of silicon or germanium between high-k dielectrics and III–V semiconductors on the frequency dispersion of the capacitance–voltage (C–V) curves in detail. We demonstrated experimentally that the frequency dispersion at accumulation voltage is strongly dependent on the energy barrier height (ΦB) between high-k dielectrics and semiconductors. It was revealed that the improvement of frequency dispersion for n-type III–V semiconductors with IL is attributed to the increase in ΦB realized by inserting Ge IL. Moreover, the border trap density did not necessarily decrease with IL through the assessment of border trap density using a distributed bulk-oxide trap model. Finally, we proved that it is important to increase ΦB to suppress the carrier exchange and improve high-k/III–V gate stack reliability.

  16. A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

    2015-05-01

    A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson's equation is solved in channel region by a method of series expansion similar to Green's function. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this expression, analytical models of threshold voltage, subthreshold swing, and subthreshold drain current for JLDGMTs were derived. Subthreshold behavior was studied in detail by changing different device parameters and bias conditions, including doping concentration, channel thickness, gate length, gate oxide thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the 2-D simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLDGMTs and to optimize their device performance.

  17. Mechanical stress altered electron gate tunneling current and extraction of conduction band deformation potentials for germanium

    NASA Astrophysics Data System (ADS)

    Choi, Youn Sung; Lim, Ji-Song; Numata, Toshinori; Nishida, Toshikazu; Thompson, Scott E.

    2007-11-01

    Strain altered electron gate tunneling current is measured for germanium (Ge) metal-oxide-semiconductor devices with HfO2 gate dielectric. Uniaxial mechanical stress is applied using four-point wafer bending along [100] and [110] directions to extract both dilation and shear deformation potential constants of Ge. Least-squares fit to the experimental data results in Ξd and Ξu of -4.3±0.3 and 16.5±0.5 eV, respectively, which agree with theoretical calculations. The dominant mechanism for the strain altered electron gate tunneling current is a strain-induced change in the conduction band offset between Ge and HfO2. Tensile stress reduces the offset and increases the gate tunneling current for Ge while the opposite occurs for Si.

  18. Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

    NASA Astrophysics Data System (ADS)

    Guodong, Gu; Yong, Cai; Zhihong, Feng; Bo, Liu; Chunhong, Zeng; Guohao, Yu; Zhihua, Dong; Baoshun, Zhang

    2012-06-01

    We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate. The off-state source-drain current density is as low as ~10-7 A/mm at VGS = 0 V and VDS = 5 V. The threshold voltage is measured to be +0.8 V by linear extrapolation from the transfer characteristics. The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V. A low reverse gate leakage current density of 4.9 × 10-7 A/mm is measured at VGS = -15 V.

  19. Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate

    NASA Astrophysics Data System (ADS)

    Dash, Sidhartha; Sahoo, Girija Shankar; Mishra, Guru Prasad

    2016-03-01

    In this work, we have developed a two-dimensional (2-D) analytical drain current model for cylindrical-gate tunnel FET structure with linearly graded binary metal alloy gate. The surface potential of the proposed model is determined using the solution of 2-D Poisson's equation with suitable boundary conditions. Further it paves way for the calculation of other analog parameters such as shortest tunneling distance, drain current, threshold voltage and subthreshold swing (SS). The introduction of linearly modulated work-function of binary alloy optimizes the subthreshold swing by ∼10 mV/decade as compared to conventional cylindrical-gate tunnel FET devices without degrading the drain current and threshold voltage performance. Also the present model shows the reduction in SS with down-scaling of gate oxide thickness and silicon pillar diameter. The analytical results are found to be synonymous with the results of Synopsys TCAD device simulator.

  20. Polydopamine as a biomimetic electron gate for artificial photosynthesis.

    PubMed

    Kim, Jae Hong; Lee, Minah; Park, Chan Beum

    2014-06-16

    We report on the capability of polydopamine (PDA), a mimic of mussel adhesion proteins, as an electron gate as well as a versatile adhesive for mimicking natural photosynthesis. This work demonstrates that PDA accelerates the rate of photoinduced electron transfer from light-harvesting molecules through two-electron and two-proton redox-coupling mechanism. The introduction of PDA as a charge separator significantly increased the efficiency of photochemical water oxidation. Furthermore, simple incorporation of PDA ad-layer on the surface of conducting materials, such as carbon nanotubes, facilitated fast charge separation and oxygen evolution through the synergistic effect of PDA-mediated proton-coupled electron transfer and the high conductivity of the substrate. Our work shows that PDA is an excellent electron acceptor as well as a versatile adhesive; thus, PDA constitutes a new electron gate for harvesting photoinduced electrons and designing artificial photosynthetic systems.