Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

DOE PAGES

Leng, X.; Bozovic, I.; Bollinger, A. T.

2016-08-10

Epitaxial indium tin oxide films have been grown on both LaAlO 3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers amore » pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors.

PubMed

Chen, Hong-Chih; Chang, Ting-Chang; Lai, Wei-Chih; Chen, Guan-Fu; Chen, Bo-Wei; Hung, Yu-Ju; Chang, Kuo-Jui; Cheng, Kai-Chung; Huang, Chen-Shuo; Chen, Kuo-Kuang; Lu, Hsueh-Hsing; Lin, Yu-Hsin

2018-02-26

This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

Transparent conducting oxide induced by liquid electrolyte gating

NASA Astrophysics Data System (ADS)

ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

2016-10-01

Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ˜1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.

2001-06-11

In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSGmore » oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications. {copyright} 2001 American Institute of Physics.« less

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

NASA Astrophysics Data System (ADS)

Cho, Won-Ju; Ahn, Min-Ju

2017-09-01

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

NASA Technical Reports Server (NTRS)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Phosphorus oxide gate dielectric for black phosphorus field effect transistors

NASA Astrophysics Data System (ADS)

Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

2018-04-01

The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

Reliability and commercialization of oxidized VCSEL

NASA Astrophysics Data System (ADS)

Li, Alice; Pan, Jin-Shan; Lai, Horng-Ching; Lee, Bor-Lin; Wu, Jack; Lin, Yung-Sen; Huo, Tai-Chan; Wu, Calvin; Huang, Kai-Feng

2003-06-01

The reliability of oxidized VCSEL has similar result to implanted VCSEL. This paper presents our work on reliability data of oxidized VCSEL device and also the comparison with implanted VCSEL. The MTTF of oxidized VCSEL is 2.73 x 106 hrs at 55°C, 6 mA and failure rate ~ 1 FITs for the first 2 years operation. The reliability data of oxidized VCSEL includes activation energy, MTTF (mean-time-to failure), failure rate prediction, and 85°C / 85% humidity test will be presented below. Commercialization of oxidized VCSEL is demonstrated such as VCSEL structure, manufacturing facility, and packaging. A cost effective approach is key to its success in applications such as Datacomm.

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

NASA Astrophysics Data System (ADS)

Pradhan, K. P.; Priyanka; Sahu, P. K.

2016-01-01

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of Inmore » metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.« less

Chemical gating of epitaxial graphene through ultrathin oxide layers.

PubMed

Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

2015-08-07

We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

NASA Astrophysics Data System (ADS)

Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

2011-03-01

The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

NASA Astrophysics Data System (ADS)

Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

2015-04-01

Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Liu, L.; Lu, H. H.; Lai, P. T.; Tang, W. M.

2015-03-01

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm-2 eV-1 at midgap), smaller gate leakage current (9.5 × 10-5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu Shiyang; Nakajima, Anri; Ohashi, Takuo

2005-12-01

The interface trap generation ({delta}N{sub it}) and fixed oxide charge buildup ({delta}N{sub ot}) under negative bias temperature instability (NBTI) of p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ultrathin (2 nm) plasma-nitrided SiON gate dielectrics were studied using a modified direct-current-current-voltage method and a conventional subthreshold characteristic measurement. Different stress time dependences were shown for {delta}N{sub it} and {delta}N{sub ot}. At the earlier stress times, {delta}N{sub it} dominates the threshold voltage shift ({delta}V{sub th}) and {delta}N{sub ot} is negligible. With increasing stress time, the rate of increase of {delta}N{sub it} decreases continuously, showing a saturating trend for longer stress times, while {delta}N{submore » ot} still has a power-law dependence on stress time so that the relative contribution of {delta}N{sub ot} increases. The thermal activation energy of {delta}N{sub it} and the NBTI lifetime of pMOSFETs, compared at a given stress voltage, are independent of the peak nitrogen concentration of the SiON film. This indicates that plasma nitridation is a more reliable method for incorporating nitrogen in the gate oxide.« less

Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

NASA Astrophysics Data System (ADS)

He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

2017-04-01

In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

NASA Astrophysics Data System (ADS)

Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

2014-08-01

We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down tomore » the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.« less

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

PubMed

Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

2015-07-01

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

DTIC Science & Technology

1993-04-01

CLASSIFICATION 18. SECURITY CLASSIFICATION 19. SECURIlY CLASSIFICATION 20. UMITATION OF ABSTRACT OF REPORT OF THIS PAGE OF ABSTRACT UNCLASSIFIED UNCLASSIFIED...with the silicon underneath, growing a thin nitride layer. This layer of Si 3 N 4 , if not completely removed, will retard oxidation in the area...C. Shatas, K. C. Saraswat and J. D. Meindl, "Interfacial and Breakdown Characteristics of MOS Devices with Rapidly Grown Ultrathin SiO Gate

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

NASA Astrophysics Data System (ADS)

Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

2017-10-01

Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

NASA Astrophysics Data System (ADS)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

PubMed

Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

2013-06-11

We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

ResearchGate is no longer reliable: leniency towards ghost journals may decrease its impact on the scientific community.

PubMed

Memon, Aamir Raoof

2016-12-01

ResearchGate has been regarded as one of the most attractive academic social networking site for scientific community. It has been trying to improve user-centered interfaces to gain more attractiveness to scientists around the world. Display of journal related scietometric measures (such as impact factor, 5-year impact, cited half-life, eigenfactor) is an important feature in ResearchGate. Open access publishing has added more to increased visibility of research work and easy access to information related to research. Moreover, scientific community has been much interested in promoting their work and exhibiting its impact to others through reliable scientometric measures. However, with the growing market of publications and improvements in the field of research, this community has been victimized by the cybercrime in the form of ghost journals, fake publishers and magical impact measures. Particularly, ResearchGate more recently, has been lenient in its policies against this dark side of academic writing. Therefore, this communication aims to discuss concerns associated with leniency in ResearchGate policies and its impact of scientific community.

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

The validity and intra-tester reliability of markerless motion capture to analyse kinematics of the BMX Supercross gate start.

PubMed

Grigg, Josephine; Haakonssen, Eric; Rathbone, Evelyne; Orr, Robin; Keogh, Justin W L

2017-11-13

The aim of this study was to quantify the validity and intra-tester reliability of a novel method of kinematic measurement. The measurement target was the joint angles of an athlete performing a BMX Supercross (SX) gate start action through the first 1.2 s of movement in situ on a BMX SX ramp using a standard gate start procedure. The method employed GoPro® Hero 4 Silver (GoPro Inc., USA) cameras capturing data at 120 fps 720 p on a 'normal' lens setting. Kinovea 0.8.15 (Kinovea.org, France) was used for analysis. Tracking data was exported and angles computed in Matlab (Mathworks®, USA). The gold standard 3D method for joint angle measurement could not safely be employed in this environment, so a rigid angle was used. Validity was measured to be within 2°. Intra-tester reliability was measured by the same tester performing the analysis twice with an average of 55 days between analyses. Intra-tester reliability was high, with an absolute error <6° and <9 frames (0.075 s) across all angles and time points for key positions, respectively. The methodology is valid within 2° and reliable within 6° for the calculation of joint angles in the first ~1.25 s.

Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

PubMed Central

Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

2015-01-01

Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

A novel optical gating method for laser gated imaging

NASA Astrophysics Data System (ADS)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Highly reliable oxide VCSELs for datacom applications

NASA Astrophysics Data System (ADS)

Aeby, Ian; Collins, Doug; Gibson, Brian; Helms, Christopher J.; Hou, Hong Q.; Lou, Wenlin; Bossert, David J.; Wang, Charlie X.

2003-06-01

In this paper we describe the processes and procedures that have been developed to ensure high reliability for Emcore"s 850 nm oxide confined GaAs VCSELs. Evidence from on-going accelerated life testing and other reliability studies that confirm that this process yields reliable products will be discussed. We will present data and analysis techniques used to determine the activation energy and acceleration factors for the dominant wear-out failure mechanisms for our devices as well as our estimated MTTF of greater than 2 million use hours. We conclude with a summary of internal verification and field return rate validation data.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Yin, Ruiyuan; Li, Yue; Sun, Yu; Wen, Cheng P.; Hao, Yilong; Wang, Maojun

2018-06-01

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{supmore » 11} cm{sup −2}).« less

Automatically closing swing gate closure assembly

DOEpatents

Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

1988-01-01

A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

Electron transporting water-gated thin film transistors

NASA Astrophysics Data System (ADS)

Al Naim, Abdullah; Grell, Martin

2012-10-01

We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

PubMed

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

Frequency-dependent reliability of spike propagation is function of axonal voltage-gated sodium channels in cerebellar Purkinje cells.

PubMed

Yang, Zhilai; Wang, Jin-Hui

2013-12-01

The spike propagation on nerve axons, like synaptic transmission, is essential to ensure neuronal communication. The secure propagation of sequential spikes toward axonal terminals has been challenged in the neurons with a high firing rate, such as cerebellar Purkinje cells. The shortfall of spike propagation makes some digital spikes disappearing at axonal terminals, such that the elucidation of the mechanisms underlying spike propagation reliability is crucial to find the strategy of preventing loss of neuronal codes. As the spike propagation failure is influenced by the membrane potentials, this process is likely caused by altering the functional status of voltage-gated sodium channels (VGSC). We examined this hypothesis in Purkinje cells by using pair-recordings at their somata and axonal blebs in cerebellar slices. The reliability of spike propagation was deteriorated by elevating spike frequency. The frequency-dependent reliability of spike propagation was attenuated by inactivating VGSCs and improved by removing their inactivation. Thus, the functional status of axonal VGSCs influences the reliability of spike propagation.

Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

2011-06-01

We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2017-04-01

The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

Charge injection from gate electrode by simultaneous stress of optical and electrical biases in HfInZnO amorphous oxide thin film transistor

NASA Astrophysics Data System (ADS)

Kwon, Dae Woong; Kim, Jang Hyun; Chang, Ji Soo; Kim, Sang Wan; Sun, Min-Chul; Kim, Garam; Kim, Hyun Woo; Park, Jae Chul; Song, Ihun; Kim, Chang Jung; Jung, U. In; Park, Byung-Gook

2010-11-01

A comprehensive study is done regarding stabilities under simultaneous stress of light and dc-bias in amorphous hafnium-indium-zinc-oxide thin film transistors. The positive threshold voltage (Vth) shift is observed after negative gate bias and light stress, and it is completely different from widely accepted phenomenon which explains that negative-bias stress results in Vth shift in the left direction by bias-induced hole-trapping. Gate current measurement is performed to explain the unusual positive Vth shift under simultaneous application of light and negative gate bias. As a result, it is clearly found that the positive Vth shift is derived from electron injection from gate electrode to gate insulator.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Improved Hot Carrier Reliability Characteristics of Metal Oxide Semiconductor Field Effect Transistors with High-k Gate Dielectric by Using High Pressure Deuterium Post Metallization Annealing

NASA Astrophysics Data System (ADS)

Park, Hokyung; Choi, Rino; Lee, Byoung Hun; Hwang, Hyunsang

2007-09-01

High pressure deuterium annealing on the hot carrier reliability characteristics of HfSiO metal oxide semiconductor field effect transistor (MOSFET) was investigated. Comparing with the conventional forming gas (H2/Ar=10%/96%, 480 °C, 30 min) annealed sample, MOSFET annealed in 5 atm pure deuterium ambient at 400 °C showed the improvement of linear drain current, reduction of interface trap density, and improvement of the hot carrier reliability characteristics. These improvements can be attributed to the effective passivation of the interface trap site after high pressure annealing and heavy mass effect of deuterium. These results indicate that high pressure pure deuterium annealing can be a promising process for improving device performance as well as hot carrier reliability, together.

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

NASA Astrophysics Data System (ADS)

Caraveo-Frescas, J. A.; Hedhili, M. N.; Wang, H.; Schwingenschlögl, U.; Alshareef, H. N.

2012-03-01

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ˜350 mV negative shift with the Si overlayer present and a ˜110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasingmore » temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.« less

Ionic liquid gating reveals trap-filled limit mobility in low temperature amorphous zinc oxide

NASA Astrophysics Data System (ADS)

Bubel, S.; Meyer, S.; Kunze, F.; Chabinyc, M. L.

2013-10-01

In low-temperature solution processed amorphous zinc oxide (a-ZnO) thin films, we show the thin film transistor (TFT) characteristics for the trap-filled limit (TFL), when the quasi Fermi energy exceeds the conduction band edge and all tail-states are filled. In order to apply gate fields that are high enough to reach the TFL, we use an ionic liquid tape gate. Performing capacitance voltage measurements to determine the accumulated charge during TFT operation, we find the TFL at biases higher than predicted by the electronic structure of crystalline ZnO. We conclude that the density of states in the conduction band of a-ZnO is higher than in its crystalline state. Furthermore, we find no indication of percolative transport in the conduction band but trap assisted transport in the tail-states of the band.

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

PubMed Central

Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

2016-01-01

The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP. PMID:27924838

Rare-earth gate oxides for GaAs MOSFET application

NASA Astrophysics Data System (ADS)

Kwon, Kwang-Ho; Yang, Jun-Kyu; Park, Hyung-Ho; Kim, Jongdae; Roh, Tae Moon

2006-08-01

Rare-earth oxide films for gate dielectric on n-GaAs have been investigated. The oxide films were e-beam evaporated on S-passivated GaAs, considering interfacial chemical bonding state and energy band structure. Rare-earth oxides such as Gd 2O 3, (Gd xLa 1- x) 2O 3, and Gd-silicate were employed due to high resistivity and no chemical reaction with GaAs. Structural and bonding properties were characterized by X-ray photoemission, absorption, and diffraction. The electrical characteristics of metal-oxide-semiconductor (MOS) diodes were correlated with material properties and energy band structures to guarantee the feasibility for MOS field effect transistor (FET) application. Gd 2O 3 films were grown epitaxially on S-passivated GaAs (0 0 1) at 400 °C. The passivation induced a lowering of crystallization temperature with an epitaxial relationship of Gd 2O 3 (4 4 0) and GaAs (0 0 1). A better lattice matching relation between Gd 2O 3 and GaAs substrate was accomplished by the substitution of Gd with La, which has larger ionic radius. The in-plane relationship of (Gd xLa 1- x) 2O 3 (4 4 0) with GaAs (0 0 1) was found and the epitaxial films showed an improved crystalline quality. Amorphous Gd-silicate film was synthesized by the incorporation of SiO 2 into Gd 2O 3. These amorphous Gd-silicate films excluded defect traps or current flow path due to grain boundaries and showed a relatively larger energy band gap dependent on the contents of SiO 2. Energy band parameters such as Δ EC, Δ EV, and Eg were effectively controlled by the film composition.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chao, Jin Yu; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn

Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor inmore » series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.« less

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Sliding-gate valve for use with abrasive materials

DOEpatents

Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

1985-01-01

The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Thermal Stress Analysis of Floating-Gate Tunneling Oxide Electrically Erasable Programmable Read Only Memory During Manufacturing Process

NASA Astrophysics Data System (ADS)

Zong, Xiang-fu; Wang, Xu; Weng, Yu-min; Yan, Ren-jin; Tang, Guo-an; Zhang, Zhao-qiang

1998-10-01

In this study, finite element modeling was used to evaluate the residual thermal stress in floating-gate tunneling oxide electrically erasable programmable read only memory (FLOTOX E2 PROMs) manufacturing process. Special attention is paid to the tunnel oxide region, in which high field electron injection is the basis to E2 PROMs operation. Calculated results show the presence of large stresses and stress gradients at the fringe. This may contribute to the invalidation of E2 PROMs. A possible failure mechanism of E2 PROM related to residual thermal stress-induced leakage is proposed.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Reliability analysis of visual ranking of coronary artery calcification on low-dose CT of the thorax for lung cancer screening: comparison with ECG-gated calcium scoring CT.

PubMed

Kim, Yoon Kyung; Sung, Yon Mi; Cho, So Hyun; Park, Young Nam; Choi, Hye-Young

2014-12-01

Coronary artery calcification (CAC) is frequently detected on low-dose CT (LDCT) of the thorax. Concurrent assessment of CAC and lung cancer screening using LDCT is beneficial in terms of cost and radiation dose reduction. The aim of our study was to evaluate the reliability of visual ranking of positive CAC on LDCT compared to Agatston score (AS) on electrocardiogram (ECG)-gated calcium scoring CT. We studied 576 patients who were consecutively registered for health screening and undergoing both LDCT and ECG-gated calcium scoring CT. We excluded subjects with an AS of zero. The final study cohort included 117 patients with CAC (97 men; mean age, 53.4 ± 8.5). AS was used as the gold standard (mean score 166.0; range 0.4-3,719.3). Two board-certified radiologists and two radiology residents participated in an observer performance study. Visual ranking of CAC was performed according to four categories (1-10, 11-100, 101-400, and 401 or higher) for coronary artery disease risk stratification. Weighted kappa statistics were used to measure the degree of reliability on visual ranking of CAC on LDCT. The degree of reliability on visual ranking of CAC on LDCT compared to ECG-gated calcium scoring CT was excellent for board-certified radiologists and good for radiology residents. A high degree of association was observed with 71.6% of visual rankings in the same category as the Agatston category and 98.9% varying by no more than one category. Visual ranking of positive CAC on LDCT is reliable for predicting AS rank categorization.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

2010-10-01

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices.

PubMed

Black, Jennifer M; Come, Jeremy; Bi, Sheng; Zhu, Mengyang; Zhao, Wei; Wong, Anthony T; Noh, Joo Hyon; Pudasaini, Pushpa R; Zhang, Pengfei; Okatan, Mahmut Baris; Dai, Sheng; Kalinin, Sergei V; Rack, Philip D; Ward, Thomas Zac; Feng, Guang; Balke, Nina

2017-11-22

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal-insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment and theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

NASA Astrophysics Data System (ADS)

Seema; Chauhan, Sudakar Singh

2018-05-01

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Zhang, Wenfeng

2014-11-07

A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scalingmore » to 0.5 nm is also demonstrated based on these understandings.« less

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

Redox regulation of neuronal voltage-gated calcium channels.

PubMed

Todorovic, Slobodan M; Jevtovic-Todorovic, Vesna

2014-08-20

Voltage-gated calcium channels are ubiquitously expressed in neurons and are key regulators of cellular excitability and synaptic transmitter release. There is accumulating evidence that multiple subtypes of voltage-gated calcium channels may be regulated by oxidation and reduction. However, the redox mechanisms involved in the regulation of channel function are not well understood. Several studies have established that both T-type and high-voltage-activated subtypes of voltage-gated calcium channel can be redox-regulated. This article reviews different mechanisms that can be involved in redox regulation of calcium channel function and their implication in neuronal function, particularly in pain pathways and thalamic oscillation. A current critical issue in the field is to decipher precise mechanisms of calcium channel modulation via redox reactions. In this review we discuss covalent post-translational modification via oxidation of cysteine molecules and chelation of trace metals, and reactions involving nitric oxide-related molecules and free radicals. Improved understanding of the roles of redox-based reactions in regulation of voltage-gated calcium channels may lead to improved understanding of novel redox mechanisms in physiological and pathological processes. Identification of redox mechanisms and sites on voltage-gated calcium channel may allow development of novel and specific ion channel therapies for unmet medical needs. Thus, it may be possible to regulate the redox state of these channels in treatment of pathological process such as epilepsy and neuropathic pain.

Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability

NASA Astrophysics Data System (ADS)

Li, Weiyi; Zhang, Zhili; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Sun, Shichuang; Song, Liang; Hao, Ronghui; Fan, Yaming; Cai, Yong; Zhang, Baoshun

2017-07-01

We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field. Project supported by the Key Technologies Support Program of Jiangsu Province (No. BE2013002-2) and the National Key Scientific Instrument and Equipment Development Projects of China (No. 2013YQ470767).

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Modification of FN tunneling provoking gate-leakage current in ZTO (zinc-tin oxide) TFT by regulating the ZTO/SiO2 area ratio

NASA Astrophysics Data System (ADS)

Li, Jeng-Ting; Tsai, Ho-Lin; Lai, Wei-Yao; Hwang, Weng-Sing; Chen, In-Gann; Chen, Jen-Sue

2018-04-01

This study addresses the variation in gate-leakage current due to the Fowler-Nordheim (FN) tunneling of electrons through a SiO2 dielectric layer in zinc-tin oxide (ZTO) thin film transistors. It is shown that the gate-leakage current is not related to the absolute area of the ZTO active layer, but it is reduced by reducing the ZTO/SiO2 area ratio. The ZTO/SiO2 area ratio modulates the ZTO-SiO2 interface dipole strength as well as the ZTO-SiO2 conduction band offset and subsequently affects the FN tunneling current through the SiO2 layer, which provides a route that modifies the gate-leakage current.

Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation.

PubMed

Vedam, S; Archambault, L; Starkschall, G; Mohan, R; Beddar, S

2007-11-01

and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8 +/- 11% and 14 +/- 21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4 +/- 7% and 8 +/- 15% with and without audiovisual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.

Redox Regulation of Neuronal Voltage-Gated Calcium Channels

PubMed Central

Jevtovic-Todorovic, Vesna

2014-01-01

Abstract Significance: Voltage-gated calcium channels are ubiquitously expressed in neurons and are key regulators of cellular excitability and synaptic transmitter release. There is accumulating evidence that multiple subtypes of voltage-gated calcium channels may be regulated by oxidation and reduction. However, the redox mechanisms involved in the regulation of channel function are not well understood. Recent Advances: Several studies have established that both T-type and high-voltage-activated subtypes of voltage-gated calcium channel can be redox-regulated. This article reviews different mechanisms that can be involved in redox regulation of calcium channel function and their implication in neuronal function, particularly in pain pathways and thalamic oscillation. Critical Issues: A current critical issue in the field is to decipher precise mechanisms of calcium channel modulation via redox reactions. In this review we discuss covalent post-translational modification via oxidation of cysteine molecules and chelation of trace metals, and reactions involving nitric oxide-related molecules and free radicals. Improved understanding of the roles of redox-based reactions in regulation of voltage-gated calcium channels may lead to improved understanding of novel redox mechanisms in physiological and pathological processes. Future Directions: Identification of redox mechanisms and sites on voltage-gated calcium channel may allow development of novel and specific ion channel therapies for unmet medical needs. Thus, it may be possible to regulate the redox state of these channels in treatment of pathological process such as epilepsy and neuropathic pain. Antioxid. Redox Signal. 21, 880–891. PMID:24161125

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

The Relationship of the Silicon Surface Roughness and Gate Oxide Integrity in NH4OH/H2O2 Mixtures

NASA Astrophysics Data System (ADS)

Meuris, M.; Verhaverbeke, S.; Mertens, P. W.; Heyns, M. M.; Hellemans, L.; Bruynseraede, Y.; Philipossian, A.

1992-11-01

In this study some recent findings on the cleaning action of the NH4OH/H2O2 (SC1) step in a pre-gate oxidation cleaning (RCA cleaning) are given. An important parameter in this mixture is the NH4OH/H2O2 ratio. The Fe contamination on the silicon surface after this cleaning step is found to increase upon decreasing the NH4OH/H2O2 ratio. This can be attributed to the incorporation of Fe in the chemical oxide, grown by the hydrogen peroxide. The particle removal efficiency of the cleaning step is found to decrease upon decreasing the NH4OH/H2O2 ratio. On the other hand, using a lower NH4OH concentration results in a less severe silicon surface roughening. It is demonstrated in this study that the NH4OH/H2O2 ratio during the SC1 step of the cleaning is the determining parameter for the breakdown properties of a gate oxide. A (0.25/1/5) NH4OH/H2O2/H2O mixture at 75°C in our experimental conditions is suggested to be the best compromise between particle removal and surface roughness during the SC1 step.

Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vedam, S.; Archambault, L.; Starkschall, G.

2007-11-15

simulation and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8{+-}11% and 14{+-}21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4{+-}7% and 8{+-}15% with and without audio-visual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.« less

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Improved Reading Gate For Vertical-Bloch-Line Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1994-01-01

Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

Ion Sensitive Transparent-Gate Transistor for Visible Cell Sensing.

PubMed

Sakata, Toshiya; Nishimura, Kotaro; Miyazawa, Yuuya; Saito, Akiko; Abe, Hiroyuki; Kajisa, Taira

2017-04-04

In this study, we developed an ion-sensitive transparent-gate transistor (IS-TGT) for visible cell sensing. The gate sensing surface of the IS-TGT is transparent in a solution because a transparent amorphous oxide semiconductor composed of amorphous In-Ga-Zn-oxide (a-IGZO) with a thin SiO 2 film gate that includes an indium tin oxide (ITO) film as the source and drain electrodes is utilized. The pH response of the IS-TGT was found to be about 56 mV/pH, indicating approximately Nernstian response. Moreover, the potential signals of the IS-TGT for sodium and potassium ions, which are usually included in biological environments, were evaluated. The optical and electrical properties of the IS-TGT enable cell functions to be monitored simultaneously with microscopic observation and electrical measurement. A platform based on the IS-TGT can be used as a simple and cost-effective plate-cell-sensing system based on thin-film fabrication technology in the research field of life science.

The operations of quantum logic gates with pure and mixed initial states.

PubMed

Chen, Jun-Liang; Li, Che-Ming; Hwang, Chi-Chuan; Ho, Yi-Hui

2011-04-07

The implementations of quantum logic gates realized by the rovibrational states of a C(12)O(16) molecule in the X((1)Σ(+)) electronic ground state are investigated. Optimal laser fields are obtained by using the modified multitarget optimal theory (MTOCT) which combines the maxima of the cost functional and the fidelity for state and quantum process. The projection operator technique together with modified MTOCT is used to get optimal laser fields. If initial states of the quantum gate are pure states, states at target time approach well to ideal target states. However, if the initial states are mixed states, the target states do not approach well to ideal ones. The process fidelity is introduced to investigate the reliability of the quantum gate operation driven by the optimal laser field. We found that the quantum gates operate reliably whether the initial states are pure or mixed.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

A pH sensor with a double-gate silicon nanowire field-effect transistor

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Kim, Jee-Yeon; Seol, Myeong-Lok; Baek, David J.; Guo, Zheng; Kim, Chang-Hoon; Choi, Sung-Jin; Choi, Yang-Kyu

2013-02-01

A pH sensor composed of a double-gate silicon nanowire field-effect transistor (DG Si-NW FET) is demonstrated. The proposed DG Si-NW FET allows the independent addressing of the gate voltage and hence improves the sensing capability through an application of asymmetric gate voltage between the two gates. One gate is a driving gate which controls the current flow, and the other is a supporting gate which amplifies the shift of the threshold voltage, which is a sensing metric, and which arises from changes in the pH. The pH signal is also amplified through modulation of the gate oxide thickness.

Hafnium oxide films for application as gate dielectrics

NASA Astrophysics Data System (ADS)

Hsu, Shuo-Lin

The deposition and characterization of HfO2 films for potential application as a high-kappa gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high-kappa, films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During post-deposition annealing, the thicker films crystallized at lower temperature (< 600°C), and ultra-thin (5.8 nm) film crystallized at higher temperature (600--720°C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10--20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra-thin annealed HfO2 film. TEM cross-section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2/Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis indicated that the interfacial layer is a silicon-rich silicate layer, which tends to transform to silica-like layer during heat treatment. I-V measurements show the leakage current density of the Al/as deposited-HfO 2/Si MOS diode is of the order of 10-3 A/cm 2, two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

PubMed

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

NASA Astrophysics Data System (ADS)

Kyoung, Sinsu; Hong, Young-sung; Lee, Myung-hwan; Nam, Tae-jin

2018-02-01

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Visual colorimetric detection of tin(II) and nitrite using a molybdenum oxide nanomaterial-based three-input logic gate.

PubMed

Du, Jiayan; Zhao, Mengxin; Huang, Wei; Deng, Yuequan; He, Yi

2018-05-09

We report a molybdenum oxide (MoO 3 ) nanomaterial-based three-input logic gate that uses Sn 2+ , NO 2 - , and H + ions as inputs. Under acidic conditions, Sn 2+ is able to reduce MoO 3 nanosheets, generating oxygen-vacancy-rich MoO 3-x nanomaterials along with strong localized surface plasmon resonance (LSPR) and an intense blue solution as the output signal. When NO 2 - is introduced, the redox reaction between the MoO 3 nanosheets and Sn 2+ is strongly inhibited because the NO 2 - consumes both H + and Sn 2+ . The three-input logic gate was employed for the visual colorimetric detection of Sn 2+ and NO 2 - under different input states. The colorimetric assay's limit of detection for Sn 2+ and the lowest concentration of NO 2 - detectable by the assay were found to be 27.5 nM and 0.1 μM, respectively. The assay permits the visual detection of Sn 2+ and NO 2 - down to concentrations as low as 2 μM and 25 μM, respectively. The applicability of the logic-gate-based colorimetric assay was demonstrated by using it to detect Sn 2+ and NO 2 - in several water sources.

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang

We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{submore » O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.« less

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jo, Kwang-Won; Cho, Won-Ju, E-mail: chowj@kw.ac.kr

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristicmore » trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.« less

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Bragg reflector based gate stack architecture for process integration of excimer laser annealing

NASA Astrophysics Data System (ADS)

Fortunato, G.; Mariucci, L.; Cuscunà, M.; Privitera, V.; La Magna, A.; Spinella, C.; Magrı, A.; Camalleri, M.; Salinas, D.; Simon, F.; Svensson, B.; Monakhov, E.

2006-12-01

An advanced gate stack structure, which incorporates a Bragg reflector, has been developed for the integration of excimer laser annealing into the power metal-oxide semiconductor (MOS) transistor fabrication process. This advanced gate structure effectively protects the gate stack from melting, thus solving the problem related to protrusion formation. By using this gate stack configuration, power MOS transistors were fabricated with improved electrical characteristics. The Bragg reflector based gate stack architecture can be applied to other device structures, such as scaled MOS transistors, thus extending the possibilities of process integration of excimer laser annealing.

Effect of gate voltage polarity on the ionic liquid gating behavior of NdNiO 3/NdGaO 3 heterostructures

DOE PAGES

Dong, Yongqi; Xu, Haoran; Luo, Zhenlin; ...

2017-05-16

The effect of gate voltage polarity on the behavior of NdNiO 3 epitaxial thin films during ionic liquid gating is studied using in situ synchrotron X-ray techniques. We show that while negative biases have no discernible effect on the structure or composition of the films, large positive gate voltages result in the injection of a large concentration of oxygen vacancies (similar to 3%) and pronounced lattice expansion (0.17%) in addition to a 1000-fold increase in sheet resistance at room temperature. Despite the creation of large defect densities, the heterostructures exhibit a largely reversible switching behavior when sufficient time is providedmore » for the vacancies to migrate in and out of the thin film surface. The results confirm that electrostatic gating takes place at negative gate voltages for p-type complex oxides while positive voltages favor the electrochemical reduction of Ni 3+. Switching between positive and negative gate voltages therefore involves a combination of electronic and ionic doping processes that may be utilized in future electrochemical transistors.« less

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

PubMed

Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

2014-12-24

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2016-10-01

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/- LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

Energetic mapping of oxide traps in MoS2 field-effect transistors

NASA Astrophysics Data System (ADS)

Illarionov, Yury Yu; Knobloch, Theresia; Waltl, Michael; Rzepa, Gerhard; Pospischil, Andreas; Polyushkin, Dmitry K.; Furchi, Marco M.; Mueller, Thomas; Grasser, Tibor

2017-06-01

The performance of MoS2 transistors is strongly affected by charge trapping in oxide traps with very broad distributions of time constants. These defects degrade the mobility and additionally lead to the hysteresis of the gate transfer characteristics, which presents a crucial performance and reliability issue for these new technologies. Here we perform a detailed study of the hysteresis in double-gated MoS2 FETs and show that this issue is nothing else than a combination of threshold voltage shifts resulting from positive and negative bias-temperature instabilities. While these instabilities are well known from silicon devices, they are even more important in 2D devices given the considerably larger defect densities. Most importantly, the magnitudes of these threshold voltage shifts depend strongly on the density and energetic alignment of the active oxide traps. Based on this, we introduce the incremental hysteresis sweep method which allows for an accurate mapping of these defects and extract their energy distributions from simulations. By applying our method to analyze the impact of oxide traps situated in the Al2O3 top gate of several devices, we confirm its versatility. Since all 2D devices investigated so far suffer from a similar hysteresis behavior, the incremental hysteresis sweep method provides a unique and powerful way for the detailed characterization of their defect bands.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

pH sensing characteristics and biosensing application of solution-gated reduced graphene oxide field-effect transistors.

PubMed

Sohn, Il-Yung; Kim, Duck-Jin; Jung, Jin-Heak; Yoon, Ok Ja; Thanh, Tien Nguyen; Quang, Trung Tran; Lee, Nae-Eung

2013-07-15

Solution-gated reduced graphene oxide field-effect transistors (R-GO FETs) were investigated for pH sensing and biochemical sensing applications. A channel of a networked R-GO film formed by self-assembly was incorporated as a sensing layer into a solution-gated FET structure for pH sensing and the detection of acetylcholine (Ach), which is a neurotransmitter in the nerve system, through enzymatic reactions. The fabricated R-GO FET was sensitive to protons (H(+)) with a pH sensitivity of 29 mV/pH in terms of the shift of the charge neutrality point (CNP), which is attributed to changes in the surface potential caused by the interaction of protons with OH surface functional groups present on the R-GO surface. The R-GO FET immobilized with acetylcholinesterase (AchE) was used to detect Ach in the concentration range of 0.1-10mM by sensing protons generated during the enzymatic reactions. The results indicate that R-GO FETs provide the capability to detect protons, demonstrating their applicability as a biosensing device for enzymatic reactions. Copyright © 2013 Elsevier B.V. All rights reserved.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-02-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

High-Performance Ink-Synthesized Cu-Gate Thin-Film Transistor with Diffusion Barrier Formation

NASA Astrophysics Data System (ADS)

Woo, Whang Je; Nam, Taewook; Oh, Il-Kwon; Maeng, Wanjoo; Kim, Hyungjun

2018-05-01

The improved electrical properties of Cu-gate thin-film transistors (TFTs) using an ink-synthesizing process were studied; this technology enables a low-cost and large area process for the display industry. We investigated the film properties and the effects of the ink-synthesized Cu layer in detail with respect to device characteristics. The mobility and reliability of the devices were significantly improved by applying a diffusion barrier at the interface between the Cu gate and the gate insulator. By using a TaN diffusion barrier layer, considerably improved and stabilized ink-Cu gated TFTs could be realized, comparable to sputtered-Cu gated TFTs under positive bias temperature stress measurements.

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Electrostatically Gated Graphene-Zinc Oxide Nanowire Heterojunction.

PubMed

You, Xueqiu; Pak, James Jungho

2015-03-01

This paper presents an electrostatically gated graphene-ZnO nanowire (NW) heterojunction for the purpose of device applications for the first time. A sub-nanometer-thick energy barrier width was formed between a monatomic graphene layer and electrochemically grown ZnO NWs. Because of the narrow energy barrier, electrons can tunnel through the barrier when a voltage is applied across the junction. A near-ohmic current-voltage (I-V) curve was obtained from the graphene-electrochemically grown ZnO NW heterojunction. This near-ohmic contact changed to asymmetric I-V Schottky contact when the samples were exposed to an oxygen environment. It is believed that the adsorbed oxygen atoms or molecules on the ZnO NW surface capture free electrons of the ZnO NWs, thereby creating a depletion region in the ZnO NWs. Consequentially, the electron concentration in the ZnO NWs is dramatically reduced, and the energy barrier width of the graphene-ZnO NW heterojunction increases greatly. This increased energy barrier width reduces the electron tunneling probability, resulting in a typical Schottky contact. By adjusting the back-gate voltage to control the graphene-ZnO NW Schottky energy barrier height, a large modulation on the junction current (on/off ratio of 10(3)) was achieved.

Gate protective device for SOS array

NASA Technical Reports Server (NTRS)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Reliability and maintainability assessment factors for reliable fault-tolerant systems

NASA Technical Reports Server (NTRS)

Bavuso, S. J.

1984-01-01

A long term goal of the NASA Langley Research Center is the development of a reliability assessment methodology of sufficient power to enable the credible comparison of the stochastic attributes of one ultrareliable system design against others. This methodology, developed over a 10 year period, is a combined analytic and simulative technique. An analytic component is the Computer Aided Reliability Estimation capability, third generation, or simply CARE III. A simulative component is the Gate Logic Software Simulator capability, or GLOSS. The numerous factors that potentially have a degrading effect on system reliability and the ways in which these factors that are peculiar to highly reliable fault tolerant systems are accounted for in credible reliability assessments. Also presented are the modeling difficulties that result from their inclusion and the ways in which CARE III and GLOSS mitigate the intractability of the heretofore unworkable mathematics.

Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Douglas, Erica Ann

Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated

Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

NASA Technical Reports Server (NTRS)

Lauenstein, Jean-Marie

2011-01-01

Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Characteristics of high-k gate dielectric formed by the oxidation of sputtered Hf/Zr/Hf thin films on the Si substrate

NASA Astrophysics Data System (ADS)

Kim, H. D.; Roh, Y.; Lee, J. E.; Kang, H.-B.; Yang, C.-W.; Lee, N.-E.

2004-07-01

We have investigated the effects of high temperature annealing on the physical and electrical properties of multilayered high-k gate oxide [HfSixOy/HfO2/intermixed-layer(IL)/ZrO2/intermixed-layer(IL)/HfO2] in metal-oxide-semiconductor device. The multilayered high-k films were formed after oxidizing the Hf/Zr/Hf films deposited directly on the Si substrate. The subsequent N2 annealing at high temperature (>= 700 °C) not only results in the polycrystallization of the multilayered high-k films, but also causes the diffusion of Zr. The latter transforms the HfSixOy/HfO2/IL/ZrO2/IL/HfO2 film into the Zr-doped HfO2 film, and improves electrical properties in general. However, the thin SiOx interfacial layer starts to form if annealing temperature increases over 700 °C, deteriorating the equivalent oxide thickness. .

Graphene-graphite oxide field-effect transistors.

PubMed

Standley, Brian; Mendez, Anthony; Schmidgall, Emma; Bockrath, Marc

2012-03-14

Graphene's high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO(2) or HfO(2). In contrast, we have studied the use of an ultrathin layered material, graphene's insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO(2), typically ~1-3 × 10(8) V/m, while its dielectric constant is slightly higher, κ ≈ 4.3. © 2012 American Chemical Society

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

NASA Astrophysics Data System (ADS)

Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

2018-02-01

Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

PubMed Central

Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

2011-01-01

Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Intelligent Gate Drive for Fast Switching and Crosstalk Suppression of SiC Devices

DOE PAGES

Zhang, Zheyu; Dix, Jeffery; Wang, Fei Fred; ...

2017-01-19

This study presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiCmore » MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.« less

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be...

A high-mobility electronic system at an electrolyte-gated oxide surface

DOE PAGES

Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; ...

2015-03-12

Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustratemore » our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 10 14 cm –2. In conclusion, our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized.« less

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Graphical workstation capability for reliability modeling

NASA Technical Reports Server (NTRS)

Bavuso, Salvatore J.; Koppen, Sandra V.; Haley, Pamela J.

1992-01-01

In addition to computational capabilities, software tools for estimating the reliability of fault-tolerant digital computer systems must also provide a means of interfacing with the user. Described here is the new graphical interface capability of the hybrid automated reliability predictor (HARP), a software package that implements advanced reliability modeling techniques. The graphics oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault-tree gates, including sequence-dependency gates, or by a Markov chain. By using this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain, which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the graphical kernal system (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing stages.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Gate Set Tomography on a trapped ion qubit

NASA Astrophysics Data System (ADS)

Nielsen, Erik; Blume-Kohout, Robin; Gamble, John; Rundinger, Kenneth; Mizrahi, Jonathan; Sterk, Johathan; Maunz, Peter

2015-03-01

We present enhancements to gate-set tomography (GST), which is a framework in which an entire set of quantum logic gates (including preparation and measurement) can be fully characterized without need for pre-calibrated operations. Our new method, ``extended Linear GST'' (eLGST) uses fast, reliable analysis of structured long gate sequences to deliver tomographic precision at the Heisenberg limit with GST's calibration-free framework. We demonstrate this precision on a trapped-ion qubit, and show significant (orders of magnitude) advantage over both standard process tomography and randomized benchmarking. This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia National Laboratories. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates

NASA Astrophysics Data System (ADS)

Chappanda, K. N.; Ilyas, S.; Younis, M. I.

2018-05-01

Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5  ×  1012 oscillations.

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-11-01

The ability to design gating systems that reliably feed and support investment castings is often the result of ``cut-and-try`` methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-01-01

The ability to design gating systems that reliably feed and support investment castings is often the result of cut-and-try'' methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ning; Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201; Hui Liu, Yang

2015-02-16

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

PubMed

Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

2016-01-27

We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

Study on effective MOSFET channel length extracted from gate capacitance

NASA Astrophysics Data System (ADS)

Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato

2018-01-01

The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

Understanding the Structure of High-K Gate Oxides - Oral Presentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miranda, Andre

2015-08-25

Hafnium Oxide (HfO 2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO 2 thin films which hasn’t been done with the technique of this study. In this study, two HfO 2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer.more » Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO 2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO 2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO 2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.« less

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Challenges Regarding IP Core Functional Reliability

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.

2017-01-01

For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides

NASA Astrophysics Data System (ADS)

Jiao, C.; Ahyi, A. C.; Dhar, S.; Morisette, D.; Myers-Ward, R.

2017-04-01

We report results on the interface trap density ( D it) of 4H- and 6H-SiC metal-oxide-semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C- ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C- V- or G- ω-based methods, the C- ψ s method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density ( N it) integrated from the C- ψ s method is several times that obtained from the high-low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal-oxide-semiconductor field-effect transistor (MOSFET) channels.

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations

NASA Astrophysics Data System (ADS)

Ibrahim, Walid; Beiu, Valeriu

As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nano-circuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design’s overall reliability, and identifying those (few) gates which impact the design’s reliability most significantly.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Effect of Pr Valence State on Interfacial Structure and Electrical Properties of Pr Oxide/PrON/Ge Gate Stack Structure

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Sakashita, Mitsuo; Takeuchi, Wakana; Kondo, Hiroki; Nakatsuka, Osamu; Zaima, Shigeaki

2011-04-01

In this study, we investigated the valence state and chemical bonding state of Pr in a Pr oxide/PrON/Ge structure. We clarified the relationship between the valence state of Pr and the Pr oxide/Ge interfacial reaction using Pr oxide/Ge and Pr oxide/PrON/Ge samples. We found the formation of three Pr oxide phases in Pr oxide films; hexagonal Pr2O3 (h-Pr2O3) (Pr3+), cubic Pr2O3 (c-Pr2O3) (Pr3+), and c-PrO2 (Pr4+). We also investigated the effect of a nitride interlayer on the interfacial reaction in Pr oxide/Ge gate stacks. In a sample with a nitride interlayer (Pr oxide/PrON/Ge), metallic Pr-Pr bonds are also formed in the c-Pr2O3 film. After annealing in H2 ambient, the diffusion of Ge into Pr oxide is not observed in this sample. Pr-Pr bonds probably prevent the interfacial reaction and Ge oxide formation, considering that the oxygen chemical potential of this film is lower than that of a GeO2/Ge system. On the other hand, the rapid thermal oxidation (RTO) treatment terminates the O vacancies and defects in c-Pr2O3. As a result, c-PrO2 with tetravalent Pr is formed in the Pr oxide/PrON/Ge sample with RTO. In this sample, the leakage current density is effectively decreased in comparison with the sample without RTO. Hydrogen termination works effectively in Pr oxide/PrON/Ge samples with and without RTO, and we can achieve an interface state density of as low as 4 ×1011 eV-1·cm-2.

Reliability and day-to-day variability of peak fat oxidation during treadmill ergometry.

PubMed

De Souza Silveira, Raul; Carlsohn, Anja; Langen, Georg; Mayer, Frank; Scharhag-Rosenberger, Friederike

2016-01-01

Exercising at intensities where fat oxidation rates are high has been shown to induce metabolic benefits in recreational and health-oriented sportsmen. The exercise intensity (Fatpeak) eliciting peak fat oxidation rates is therefore of particular interest when aiming to prescribe exercise for the purpose of fat oxidation and related metabolic effects. Although running and walking are feasible and popular among the target population, no reliable protocols are available to assess Fatpeak as well as its actual velocity (VPFO) during treadmill ergometry. Our purpose was therefore, to assess the reliability and day-to-day variability of VPFO and Fatpeak during treadmill ergometry running. Sixteen recreational athletes (f = 7, m = 9; 25 ± 3 y; 1.76 ± 0.09 m; 68.3 ± 13.7 kg; 23.1 ± 2.9 kg/m(2)) performed 2 different running protocols on 3 different days with standardized nutrition the day before testing. At day 1, peak oxygen uptake (VO2peak) and the velocities at the aerobic threshold (VLT) and respiratory exchange ratio (RER) of 1.00 (VRER) were assessed. At days 2 and 3, subjects ran an identical submaximal incremental test (Fat-peak test) composed of a 10 min warm-up (70 % VLT) followed by 5 stages of 6 min with equal increments (stage 1 = VLT, stage 5 = VRER). Breath-by-breath gas exchange data was measured continuously and used to determine fat oxidation rates. A third order polynomial function was used to identify VPFO and subsequently Fatpeak. The reproducibility and variability of variables was verified with an intraclass correlation coefficient (ICC), Pearson's correlation coefficient, coefficient of variation (CV) and the mean differences (bias) ± 95 % limits of agreement (LoA). ICC, Pearson's correlation and CV for VPFO and Fatpeak were 0.98, 0.97, 5.0 %; and 0.90, 0.81, 7.0 %, respectively. Bias ± 95 % LoA was -0.3 ± 0.9 km/h for VPFO and -2 ± 8 % of VO2peak for Fatpeak. In summary, relative

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.;

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

NASA Astrophysics Data System (ADS)

Poorvasha, S.; Lakshmi, B.

2018-05-01

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (f t), maximum oscillation frequency (f max), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (I ON) of about 0.2 mA and less leakage current (I OFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (g m), higher f t and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher f max of 985 GHz is obtained for drain doping of 5 × 1017 cm‑3 because of the reduced gate-drain capacitance (C gd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of C gd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values. Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

Comparison of LVEF assessed by 2D echocardiography, gated blood pool SPECT, 99mTc tetrofosmin gated SPECT, and 18F-FDG gated PET with ERNV in patients with CAD and severe LV dysfunction.

PubMed

Raja, Senthil; Mittal, Bhagwant R; Santhosh, Sampath; Bhattacharya, Anish; Rohit, Manoj K

2014-11-01

Left ventricular ejection fraction (LVEF) is the single most important predictor of prognosis in patients with coronary artery disease (CAD) and left ventricular (LV) dysfunction. Equilibrium radionuclide ventriculography (ERNV) is considered the most reliable technique for assessing LVEF. Most of these patients undergo two dimensional (2D) echocardiography and myocardial viability study using gated myocardial perfusion imaging (MPI) or gated F-fluorodeoxyglucose (F-FDG) PET. However, the accuracy of LVEF assessed by these methods is not clear. This study has been designed to assess the correlation and agreement between the LVEF measured by 2D echocardiography, gated blood pool single photon emission computed tomography (SPECT), Tc tetrofosmin gated SPECT, and F-FDG gated PET with ERNV in CAD patients with severe LV dysfunction. Patients with CAD and severe LV dysfunction [ejection fraction (EF) <35 assessed by 2D echocardiography] were prospectively included in the study. These patients underwent ERNV along with gated blood pool SPECT, Tc tetrofosmin gated SPECT, and F-FDG gated PET as per the standard protocol for myocardial viability assessment and LVEF calculation. Spearman's coefficient of correlation (r) was calculated for the different sets of values with significance level kept at a P-value less than 0.05. Bland-Altman plots were inspected to visually assess the between-agreement measurements from different methods. Forty-one patients were prospectively included. LVEF calculated by various radionuclide methods showed good correlation with ERNV as follows: gated blood pool SPECT, r=0.92; MPI gated SPECT, r=0.85; and F-FDG gated PET, r=0.76. However, the correlation between 2D echocardiography and ERNV was poor (r=0.520). The Bland-Altman plot for LVEF measured by all radionuclide methods showed good agreement with ERNV. However, agreement between 2D echocardiography and ERNV is poor, as most of the values in this plot gave a negative difference for low EF

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

PubMed

Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

2015-08-01

In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Day to Day Variability and Reliability of Blood Oxidative Stress Markers within a Four-Week Period in Healthy Young Men.

PubMed

Goldfarb, A H; Garten, R S; Waller, J; Labban, J D

2014-01-01

The present study aimed to determine the day to day variability and reliability of several blood oxidative stress markers at rest in a healthy young cohort over a four-week period. Twelve apparently healthy resistance trained males (24.6 ± 3.0 yrs) were tested over 7 visits within 4 weeks with at least 72 hrs between visits at the same time of day. Subjects rested 30 minutes prior to blood being obtained by vacutainer. Results. The highest IntraClass correlations (ICC's) were obtained for protein carbonyls (PC) and oxygen radical absorbance capacity (ORAC) (PC = 0.785 and ORAC = 0.780). Cronbach's α reliability score for PC was 0.967 and for ORAC was 0.961. The ICC's for GSH, GSSG, and the GSSG/TGH ratio ICC were 0.600, 0.573, and 0.570, respectively, with Cronbach's α being 0.913, 0.904, and 0.903, respectively. Xanthine oxidase ICC was 0.163 and Cronbach's α was 0.538. Conclusions. PC and ORAC demonstrated good to excellent reliability while glutathione factors had poor to excellent reliability. Xanthine oxidase showed poor reliability and high variability. These results suggest that the PC and ORAC markers were the most stable and reliable oxidative stress markers in blood and that daily changes across visits should be considered when interpreting resting blood oxidative stress markers.

Light-induced negative differential resistance in gate-controlled graphene-silicon photodiode

NASA Astrophysics Data System (ADS)

Liu, Wei; Guo, Hongwei; Li, Wei; Wan, Xia; Bodepudi, Srikrishna Chanakya; Shehzad, Khurram; Xu, Yang

2018-05-01

In this letter, we investigated light-induced negative differential resistance (L-NDR) effects in a hybrid photodiode formed by a graphene-silicon (GS) junction and a neighboring graphene-oxide-Si (GOS) capacitor. We observed two distinct L-NDR effects originating from the gate-dependent surface recombination and the potential-well-induced confinement of photo-carriers in the GOS region. We verified this by studying the gate-controlled GS diode, which can distinguish the photocurrent from the GS region with that from the GOS region (gate). A large peak-to-valley ratio of up to 12.1 has been obtained for the L-NDR due to gate-dependent surface recombination. Such strong L-NDR effect provides an opportunity to further engineer the optoelectronic properties of GS junctions along with exploring its potential applications in photodetectors, photo-memories, and position sensitive devices.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

Synthesis, integration, and characterization of metal oxide films as alternative gate dielectric materials

NASA Astrophysics Data System (ADS)

Lin, You-Sheng

ZrO2 and HfO2 were investigated in this study to replace SiO2 as the potential gate dielectric materials in metal-oxide-semiconductor field effect transistors. ZrO2 and HfO2 films were deposited on p-type Si (100) wafers by an atomic layer chemical vapor deposition (ALCVD) process using zirconium (IV) t-butoxide and hafnium (IV) t-butoxide as the metal precursors, respectively. Oxygen was used alternatively with these metal alkoxide precursors into the reactor with purging and evacuation in between. The as-deposited ZrO2 and HfO2 films were stoichiometric and uniform based on X-ray photoemission spectroscopy and ellipsometry measurements. X-ray diffraction analysis indicated that the deposited films were amorphous, however, the high-resolution transmission electron microscopy showed an interfacial layer formation on the silicon substrate. Time-of-flight secondary ion mass spectrometry and medium energy ion scattering analysis showed significant intermixing between metal oxides and Si, indicating the formation of metal silicates, which were confirmed by their chemical etching resistance in HF solutions. The thermal stability of ZrO2 and HfO2 thin films on silicon was examined by monitoring their decomposition temperatures in ultra-high vacuum, using in-situ synchrotron radiation ultra-violet photoemission spectroscopy. The as-deposited ZrO2 and HfO2 thin films were thermally stable up to 880°C and 950°C in vacuum, respectively. The highest achieveable dielectric constants of as-deposited ZrO 2 and HfO2 were 21 and 24, respectively, which were slightly lower than the reported dielectric constants of bulk ZrO2 and HfO 2. These slight reductions in dielectric constants were attributed to the formation of the interfacial metal silicate layers. Very small hysteresis and interface state density were observed for both metal oxide films. Their leakage currents were a few orders of magnitude lower than that of SiO 2 at the same equivalent oxide thickness. NMOSFETs were

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk; Barquinha, P. M. C.

Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys.more » 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.« less

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond

NASA Astrophysics Data System (ADS)

Dunn, Derren; Sporre, John R.; Deshpande, Vaibhav; Oulmane, Mohamed; Gull, Ronald; Ventzek, Peter; Ranjan, Alok

2017-03-01

Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.1 When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.2

Alstom Francis Turbine Ring Gates: from Retrofitting to Commissioning

NASA Astrophysics Data System (ADS)

A, Nguyen P.; G, Labrecque; M-O, Thibault; M, Bergeron; A, Steinhilber; D, Havard

2014-03-01

The Ring Gate synchronisation system developed by Alstom is new and patented. It uses hydraulic cylinders connected in pairs by a serial connection. The new hydraulic synchronisation system, when compared to the previous mechanical synchronisation system, has several advantages. It is a compact design; it reduces the number of mechanical components as well as maintenance costs. The new system maintains the Ring Gates robustness. The new approach is an evolution from mechanical to hydraulic synchronization assisted by electronic control. The new synchronization system eliminates several mechanical components that used to add wear and friction and which are usually difficult to adjust during maintenance. Tension chains and sprockets and associated controls are eliminated. Through the position sensors, the redundancy of the ring gate synchronization system makes it predictable and reliable. The electronic control compensates for any variation in operation, for example a leak in the hydraulic system. An emergency closing is possible without the electronic control system due to the stiffness of hydraulic serial connection in the hydraulic cylinder pairs. The Ring Gate can work safely against uneven loads and frictions. The development will be reviewed and its application discussed through commissioning results.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

A graphical language for reliability model generation

NASA Technical Reports Server (NTRS)

Howell, Sandra V.; Bavuso, Salvatore J.; Haley, Pamela J.

1990-01-01

A graphical interface capability of the hybrid automated reliability predictor (HARP) is described. The graphics-oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault tree gates, including sequence dependency gates, or by a Markov chain. With this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the Graphical Kernel System (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing.

Enzymatic AND logic gates operated under conditions characteristic of biomedical applications.

PubMed

Melnikov, Dmitriy; Strack, Guinevere; Zhou, Jian; Windmiller, Joshua Ray; Halámek, Jan; Bocharova, Vera; Chuang, Min-Chieh; Santhosh, Padmanabhan; Privman, Vladimir; Wang, Joseph; Katz, Evgeny

2010-09-23

Experimental and theoretical analyses of the lactate dehydrogenase and glutathione reductase based enzymatic AND logic gates in which the enzymes and their substrates serve as logic inputs are performed. These two systems are examples of the novel, previously unexplored class of biochemical logic gates that illustrate potential biomedical applications of biochemical logic. They are characterized by input concentrations at logic 0 and 1 states corresponding to normal and pathophysiological conditions. Our analysis shows that the logic gates under investigation have similar noise characteristics. Both significantly amplify random noise present in inputs; however, we establish that for realistic widths of the input noise distributions, it is still possible to differentiate between the logic 0 and 1 states of the output. This indicates that reliable detection of pathophysiological conditions is indeed possible with such enzyme logic systems.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Role of F357 as an Oxygen Gate in the Oxidative Half-Reaction of Choline Oxidase.

PubMed

Salvi, Francesca; Rodriguez, Isela; Hamelberg, Donald; Gadda, Giovanni

2016-03-15

Choline oxidase from Arthrobacter globiformis catalyzes the oxidation of choline to glycine betaine by using oxygen as an electron acceptor. A partially rate limiting isomerization of the reduced wild-type enzyme during the reaction with oxygen was previously detected using solvent viscosity effects. In this study, we hypothesized that the side chains of M62 and F357, located at the entrance to the active site of choline oxidase, may be related to the slow isomerization detected. We engineered a double-variant enzyme M62A/F357A. The kinetic characterization of the double-variant enzyme showed a lack of the isomerization detected in wild-type choline oxidase, and a lack of saturation with an oxygen concentration as high as 1 mM, while most other kinetic parameters were similar to those of wild-type choline oxidase. The kinetic characterization of the single-variant enzymes established that only the side chain of F357 plays a role in the isomerization of choline oxidase in the oxidative half-reaction. Molecular dynamics studies suggest that the slow isomerization related to F357 is possibly due to the participation of the phenyl ring in a newly proposed gating mechanism for a narrow tunnel, assumed to regulate the access of oxygen to the reduced cofactor.

Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berl, M., E-mail: mberl@phys.ethz.ch; Tiemann, L.; Dietsche, W.

2016-03-28

We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 10{sup 6} cm{sup 2}/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES,more » thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.« less

Dosimetry applications in GATE Monte Carlo toolkit.

PubMed

Papadimitroulas, Panagiotis

2017-09-01

Monte Carlo (MC) simulations are a well-established method for studying physical processes in medical physics. The purpose of this review is to present GATE dosimetry applications on diagnostic and therapeutic simulated protocols. There is a significant need for accurate quantification of the absorbed dose in several specific applications such as preclinical and pediatric studies. GATE is an open-source MC toolkit for simulating imaging, radiotherapy (RT) and dosimetry applications in a user-friendly environment, which is well validated and widely accepted by the scientific community. In RT applications, during treatment planning, it is essential to accurately assess the deposited energy and the absorbed dose per tissue/organ of interest, as well as the local statistical uncertainty. Several types of realistic dosimetric applications are described including: molecular imaging, radio-immunotherapy, radiotherapy and brachytherapy. GATE has been efficiently used in several applications, such as Dose Point Kernels, S-values, Brachytherapy parameters, and has been compared against various MC codes which are considered as standard tools for decades. Furthermore, the presented studies show reliable modeling of particle beams when comparing experimental with simulated data. Examples of different dosimetric protocols are reported for individualized dosimetry and simulations combining imaging and therapy dose monitoring, with the use of modern computational phantoms. Personalization of medical protocols can be achieved by combining GATE MC simulations with anthropomorphic computational models and clinical anatomical data. This is a review study, covering several dosimetric applications of GATE, and the different tools used for modeling realistic clinical acquisitions with accurate dose assessment. Copyright © 2017 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

Reliability of ^1^H NMR analysis for assessment of lipid oxidation at frying temperatures

USDA-ARS?s Scientific Manuscript database

The reliability of a method using ^1^H NMR analysis for assessment of oil oxidation at a frying temperature was examined. During heating and frying at 180 °C, changes of soybean oil signals in the ^1^H NMR spectrum including olefinic (5.16-5.30 ppm), bisallylic (2.70-2.88 ppm), and allylic (1.94-2.1...

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

DOEpatents

Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

2016-08-02

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

A simple device for respiratory gating for the MRI of laboratory animals.

PubMed

Burdett, N G; Carpenter, T A; Hall, L D

1993-01-01

Respiratory motion must be overcome if MRI of the abdomen, even at the lowest resolution, is to be performed satisfactorily. A simple and reliable respiratory gating device, based on the interruption of an infrared (IR) optical beam is described. This device has the advantage that gating is based on the position of the chest as opposed to its velocity, and that it can be used without degrading the radiofrequency isolation of a Faraday cage. Its use in animal MRI is illustrated by high resolution (200 microns) images of in vivo rat liver and kidney.

Insulator to metal transition in WO 3 induced by electrolyte gating

DOE PAGES

Leng, X.; Pereiro, J.; Strle, J.; ...

2017-07-03

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Evaluation of segmental left ventricular wall motion by equilibrium gated radionuclide ventriculography.

PubMed

Van Nostrand, D; Janowitz, W R; Holmes, D R; Cohen, H A

1979-01-01

The ability of equilibrium gated radionuclide ventriculography to detect segmental left ventricular (LV) wall motion abnormalities was determined in 26 patients undergoing cardiac catheterization. Multiple gated studies obtained in 30 degrees right anterior oblique and 45 degrees left anterior oblique projections, played back in a movie format, were compared to the corresponding LV ventriculograms. The LV wall in the two projections was divided into eight segments. Each segment was graded as normal, hypokinetic, akinetic, dyskinetic, or indeterminate. Thirteen percent of the segments in the gated images were indeterminate; 24 out of 27 of these were proximal or distal inferior wall segments. There was exact agreement in 86% of the remaining segments. The sensitivity of the radionuclide technique for detecting normal versus any abnormal wall motion was 71%, with a specificity of 99%. Equilibrium gated ventriculography is an excellent noninvasive technique for evaluating segmental LV wall motion. It is least reliable in assessing the proximal inferior wall and interventricular septum.

Electrofluidic gating of a chemically reactive surface.

PubMed

Jiang, Zhijun; Stein, Derek

2010-06-01

We consider the influence of an electric field applied normal to the electric double layer at a chemically reactive surface. Our goal is to elucidate how surface chemistry affects the potential for field-effect control over micro- and nanofluidic systems, which we call electrofluidic gating. The charging of a metal-oxide-electrolyte (MOE) capacitor is first modeled analytically. We apply the Poisson-Boltzmann description of the double layer and impose chemical equilibrium between the ionizable surface groups and the solution at the solid-liquid interface. The chemically reactive surface is predicted to behave as a buffer, regulating the charge in the double layer by either protonating or deprotonating in response to the applied field. We present the dependence of the charge density and the electrochemical potential of the double layer on the applied field, the density, and the dissociation constants of ionizable surface groups and the ionic strength and the pH of the electrolyte. We simulate the responses of SiO(2) and Al(2)O(3), two widely used oxide insulators with different surface chemistries. We also consider the limits to electrofluidic gating imposed by the nonlinear behavior of the double layer and the dielectric strength of oxide materials, which were measured for SiO(2) and Al(2)O(3) films in MOE configurations. Our results clarify the response of chemically reactive surfaces to applied fields, which is crucial to understanding electrofluidic effects in real devices.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Fabrication, testing and reliability modeling of copper/titanium-metallized GaAs MESFETs and HEMTs for low-noise applications

NASA Astrophysics Data System (ADS)

Feng, Ting

Today, GaAs based field effect transistors (FETs) have been used in a broad range of high-speed electronic military and commercial applications. However, their reliability still needs to be improved. Particularly the hydrogen induced degradation is a large remaining issue in the reliability of GaAs FETs, because hydrogen can easily be incorporated into devices during the crystal growth and virtually every device processing step. The main objective of this research work is to develop a new gate metallization system in order to reduce the hydrogen induced degradation from the gate region for GaAs based MESFETs and HEMTs. Cu/Ti gate metallization has been introduced into the GaAs MESFETs and HEMTs in our work in order to solve the hydrogen problem. The purpose of the use of copper is to tie up the hydrogen atoms and prevent hydrogen penetration into the device active region as well as to keep a low gate resistance for low noise applications. In this work, the fabrication technology of GaAs MESFETs and AlGaAs/GaAs HEMTs with Cu/Ti metallized gates have been successfully developed and the fabricated Cu/Ti FETs have shown comparable DC performance with similar Au-based GaAs FETs. The Cu/Ti FETs were subjected to temperature accelerated testing at NOT under 5% hydrogen forming gas and the experimental results show the hydrogen induced degradation has been reduced for the Cu/Ti FETs compared to commonly used AuPtTi based GaAs FETs. A long-term reliability testing for Cu/Ti FETs has also been carried out at 200°C and up to 1000hours and testing results show Cu/Ti FETs performed with adequate reliability. The failure modes were found to consist of a decrease in drain saturation current and pinch-off voltage and an increase in source ohmic contact resistance. Material characterization tools including Rutherford backscattering spectroscopy and a back etching technique were used in Cu/Ti GaAs FETs, and pronounced gate metal copper in-diffusion and intermixing compounds at the

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Assessment of regional lung functional impairment with co-registered respiratory-gated ventilation/perfusion SPET-CT images: initial experiences.

PubMed

Suga, Kazuyoshi; Yasuhiko, Kawakami; Zaki, Mohammed; Yamashita, Tomio; Seto, Aska; Matsumoto, Tsuneo; Matsunaga, Naofumi

2004-02-01

In this study, respiratory-gated ventilation and perfusion single-photon emission tomography (SPET) were used to define regional functional impairment and to obtain reliable co-registration with computed tomography (CT) images in various lung diseases. Using a triple-headed SPET unit and a physiological synchroniser, gated perfusion SPET was performed in a total of 78 patients with different pulmonary diseases, including metastatic nodules (n = 15); in 34 of these patients, it was performed in combination with gated technetium-99m Technegas SPET. Projection data were acquired using 60 stops over 120 degrees for each detector. Gated end-inspiration and ungated images were reconstructed from 1/8 data centered at peak inspiration for each regular respiratory cycle and full respiratory cycle data, respectively. Gated images were registered with tidal inspiration CT images using automated three-dimensional (3D) registration software. Registration mismatch was assessed by measuring 3D distance of the centroid of the nine selected round perfusion-defective nodules. Gated SPET images were completed within 29 min, and increased the number of visible ventilation and perfusion defects by 9.7% and 17.2%, respectively, as compared with ungated images; furthermore, lesion-to-normal lung contrast was significantly higher on gated SPET images. In the nine round perfusion-defective nodules, gated images yielded a significantly better SPET-CT match compared with ungated images (4.9 +/- 3.1 mm vs 19.0 +/- 9.1 mm, P<0.001). The co-registered SPET-CT images allowed accurate perception of the location and extent of each ventilation/perfusion defect on the underlying CT anatomy, and characterised the pathophysiology of the various diseases. By reducing respiratory motion effects and enhancing perfusion/ventilation defect clarity, gated SPET can provide reliable co-registered images with CT images to accurately characterise regional functional impairment in various lung diseases.

Assessing self-reported use of new psychoactive substances: The impact of gate questions.

PubMed

Palamar, Joseph J; Acosta, Patricia; Calderón, Fermín Fernández; Sherman, Scott; Cleland, Charles M

2017-09-01

New psychoactive substances (NPS) continue to emerge; however, few surveys of substance use ask about NPS use. Research is needed to determine how to most effectively query use of NPS and other uncommon drugs. To determine whether prevalence of self-reported lifetime and past-year use differs depending on whether or not queries about NPS use are preceded by "gate questions." Gate questions utilize skip-logic, such that only a "yes" response to the use of specific drug class is followed by more extensive queries of drug use in that drug class. We surveyed 1,048 nightclub and dance festival attendees (42.6% female) entering randomly selected venues in New York City in 2016. Participants were randomized to gate vs. no gate question before each drug category. Analyses focus on eight categories classifying 145 compounds: NBOMe, 2C, DOx, "bath salts" (synthetic cathinones), other stimulants, tryptamines, dissociatives, and non-phenethylamine psychedelics. Participants, however, were asked about specific "bath salts" regardless of their response to the gate question to test reliability. We examined whether prevalence of use of each category differed by gate condition and whether gate effects were moderated by participant demographics. Prevalence of use of DOx, other stimulants, and non-phenethylamine psychedelics was higher without a gate question. Gate effects for other stimulants and non-phenethylamine psychedelics were larger among white participants and those attending parties less frequently. Almost one in ten (9.3%) participants reporting no "bath salt" use via the gate question later reported use of a "bath salt" such as mephedrone, methedrone, or methylone. Omitting gate questions may improve accuracy of data collected via self-report.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Gate oxide thickness dependence of the leakage current mechanism in Ru/Ta2O5/SiON/Si structures

NASA Astrophysics Data System (ADS)

Ťapajna, M.; Paskaleva, A.; Atanassova, E.; Dobročka, E.; Hušeková, K.; Fröhlich, K.

2010-07-01

Leakage conduction mechanisms in Ru/Ta2O5/SiON/Si structures with rf-sputtered Ta2O5 with thicknesses ranging from 13.5 to 1.8 nm were systematically studied. Notable reaction at the Ru/Ta2O5 interface was revealed by capacitance-voltage measurements. Temperature-dependent current-voltage characteristics suggest the bulk-limited conduction mechanism in all metal-oxide-semiconductor structures. Under gate injection, Poole-Frenkel emission was identified as a dominant mechanism for 13.5 nm thick Ta2O5. With an oxide thickness decreasing down to 3.5 nm, the conduction mechanism transforms to thermionic trap-assisted tunnelling through the triangular barrier. Under substrate injection, the dominant mechanism gradually changes with decreasing thickness from thermionic trap-assisted tunnelling to trap-assisted tunnelling through the triangular barrier; Poole-Frenkel emission was not observed at all. A 0.7 eV deep defect level distributed over Ta2O5 is assumed to be responsible for bulk-limited conduction mechanisms and is attributed to H-related defects or oxygen vacancies in Ta2O5.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

Demonstration of large field effect in topological insulator films via a high-κ back gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, C. Y.; Lin, H. Y.; Yang, S. R.

2016-05-16

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi{sub 2}Se{sub 3} films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al{sub 2}O{sub 3} and Y{sub 2}O{sub 3}. Large gating effect of tuning the Fermi level E{sub F} to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO{sub 2} back gate, and the modulation of filmmore » resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN{sub 2D}/ΔV{sub g} varies with TI film thickness as ∼t{sup −0.75}. To enhance the gating effect, a Y{sub 2}O{sub 3} layer thickness 4 nm was inserted into Al{sub 2}O{sub 3} gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi{sub 2}Se{sub 3} to form Bi{sub 2}Te{sub x}Se{sub 1−x}. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the E{sub F} very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable E{sub F} for dissipationless spintronics based on well-established semiconductor technology.« less

Gating of the designed trimeric/tetrameric voltage-gated H+ channel

PubMed Central

Fujiwara, Yuichiro; Kurokawa, Tatsuki; Takeshita, Kohei; Nakagawa, Atsushi; Larsson, H Peter; Okamura, Yasushi

2013-01-01

The voltage-gated H+ channel functions as a dimer, a configuration that is different from standard tetrameric voltage-gated channels. Each channel protomer has its own permeation pathway. The C-terminal coiled-coil domain has been shown to be necessary for both dimerization and cooperative gating in the two channel protomers. Here we report the gating cooperativity in trimeric and tetrameric Hv channels engineered by altering the hydrophobic core sequence of the coiled-coil assembly domain. Trimeric and tetrameric channels exhibited more rapid and less sigmoidal kinetics of activation of H+ permeation than dimeric channels, suggesting that some channel protomers in trimers and tetramers failed to produce gating cooperativity observed in wild-type dimers. Multimerization of trimer and tetramer channels were confirmed by the biochemical analysis of proteins, including crystallography. These findings indicate that the voltage-gated H+ channel is optimally designed as a dimeric channel on a solid foundation of the sequence pattern of the coiled-coil core, with efficient cooperative gating that ensures sustained and steep voltage-dependent H+ conductance in blood cells. PMID:23165764

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

PubMed

Dimitrakopoulos; Purushothaman; Kymissis; Callegari; Shaw

1999-02-05

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Field programmable gate arrays: Evaluation report for space-flight application

NASA Technical Reports Server (NTRS)

Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

1992-01-01

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Analytical drain current model for symmetric dual-gate amorphous indium gallium zinc oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Qin, Ting; Liao, Congwei; Huang, Shengxiang; Yu, Tianbao; Deng, Lianwen

2018-01-01

An analytical drain current model based on the surface potential is proposed for amorphous indium gallium zinc oxide (a-InGaZnO) thin-film transistors (TFTs) with a synchronized symmetric dual-gate (DG) structure. Solving the electric field, surface potential (φS), and central potential (φ0) of the InGaZnO film using the Poisson equation with the Gaussian method and Lambert function is demonstrated in detail. The compact analytical model of current-voltage behavior, which consists of drift and diffusion components, is investigated by regional integration, and voltage-dependent effective mobility is taken into account. Comparison results demonstrate that the calculation results obtained using the derived models match well with the simulation results obtained using a technology computer-aided design (TCAD) tool. Furthermore, the proposed model is incorporated into SPICE simulations using Verilog-A to verify the feasibility of using DG InGaZnO TFTs for high-performance circuit designs.

Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

PubMed

Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

2014-01-01

Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Sliding-gate valve

DOEpatents

Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

1979-01-01

This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Wan, Xiang; Shi, Yi; Wan, Qing

2016-01-01

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn; Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201

The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

GaN HEMTs with p-GaN gate: field- and time-dependent degradation

NASA Astrophysics Data System (ADS)

Meneghesso, G.; Meneghini, M.; Rossetto, I.; Canato, E.; Bartholomeus, J.; De Santi, C.; Trivellin, N.; Zanoni, E.

2017-02-01

GaN-HEMTs with p-GaN gate have recently demonstrated to be excellent normally-off devices for application in power conversion systems, thanks to the high and robust threshold voltage (VTH>1 V), the high breakdown voltage, and the low dynamic Ron increase. For this reason, studying the stability and reliability of these devices under high stress conditions is of high importance. This paper reports on our most recent results on the field- and time-dependent degradation of GaN-HEMTs with p-GaN gate submitted to stress with positive gate bias. Based on combined step-stress experiments, constant voltage stress and electroluminescence testing we demonstrated that: (i) when submitted to high/positive gate stress, the transistors may show a negative threshold voltage shift, that is ascribed to the injection of holes from the gate metal towards the p-GaN/AlGaN interface; (ii) in a step-stress experiment, the analyzed commercial devices fail at gate voltages higher than 9-10 V, due to the extremely high electric field over the p-GaN/AlGaN stack; (iii) constant voltage stress tests indicate that the failure is also time-dependent and Weibull distributed. The several processes that can explain the time-dependent failure are discussed in the following.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Graphene-based aptamer logic gates and their application to multiplex detection.

PubMed

Wang, Li; Zhu, Jinbo; Han, Lei; Jin, Lihua; Zhu, Chengzhou; Wang, Erkang; Dong, Shaojun

2012-08-28

In this work, a GO/aptamer system was constructed to create multiplex logic operations and enable sensing of multiplex targets. 6-Carboxyfluorescein (FAM)-labeled adenosine triphosphate binding aptamer (ABA) and FAM-labeled thrombin binding aptamer (TBA) were first adsorbed onto graphene oxide (GO) to form a GO/aptamer complex, leading to the quenching of the fluorescence of FAM. We demonstrated that the unique GO/aptamer interaction and the specific aptamer-target recognition in the target/GO/aptamer system were programmable and could be utilized to regulate the fluorescence of FAM via OR and INHIBIT logic gates. The fluorescence changed according to different input combinations, and the integration of OR and INHIBIT logic gates provided an interesting approach for logic sensing applications where multiple target molecules were present. High-throughput fluorescence imagings that enabled the simultaneous processing of many samples by using the combinatorial logic gates were realized. The developed logic gates may find applications in further development of DNA circuits and advanced sensors for the identification of multiple targets in complex chemical environments.

Advanced reliability modeling of fault-tolerant computer-based systems

NASA Technical Reports Server (NTRS)

Bavuso, S. J.

1982-01-01

Two methodologies for the reliability assessment of fault tolerant digital computer based systems are discussed. The computer-aided reliability estimation 3 (CARE 3) and gate logic software simulation (GLOSS) are assessment technologies that were developed to mitigate a serious weakness in the design and evaluation process of ultrareliable digital systems. The weak link is based on the unavailability of a sufficiently powerful modeling technique for comparing the stochastic attributes of one system against others. Some of the more interesting attributes are reliability, system survival, safety, and mission success.

Optimization of a solid-state electron spin qubit using Gate Set Tomography

DOE PAGES

Dehollain, Juan P.; Muhonen, Juha T.; Blume-Kohout, Robin J.; ...

2016-10-13

Here, state of the art qubit systems are reaching the gate fidelities required for scalable quantum computation architectures. Further improvements in the fidelity of quantum gates demands characterization and benchmarking protocols that are efficient, reliable and extremely accurate. Ideally, a benchmarking protocol should also provide information on how to rectify residual errors. Gate Set Tomography (GST) is one such protocol designed to give detailed characterization of as-built qubits. We implemented GST on a high-fidelity electron-spin qubit confined by a single 31P atom in 28Si. The results reveal systematic errors that a randomized benchmarking analysis could measure but not identify, whereasmore » GST indicated the need for improved calibration of the length of the control pulses. After introducing this modification, we measured a new benchmark average gate fidelity of 99.942(8)%, an improvement on the previous value of 99.90(2)%. Furthermore, GST revealed high levels of non-Markovian noise in the system, which will need to be understood and addressed when the qubit is used within a fault-tolerant quantum computation scheme.« less

Characterisation of Nd2O3 thick gate dielectric for silicon

NASA Astrophysics Data System (ADS)

Dakhel, A. A.

2004-03-01

Thin neodymium films were prepared by the reactive synthesis method on Si (P) substrates to form MOS devices. The oxide films were characterised by UV absorption spectroscopy, X-ray fluorescence (EDXRF) and X-ray diffraction (XRD). The ac conductance and capacitance of the devices were studied as a function of frequency in the range 100 Hz-100 kHz, of temperature in the range 293-473 K and of gate voltage. It was proved that a suitable formalism to explain the frequency dependence of the ac conductivity and capacitance of the insulator is controlled by a universal power law based on the relaxation processes of the hopping or tunnelling of the current carriers between equilibrium sites. The temperature dependence of the ac conductance at the accumulation state shows a small activation energy of about 0.07 eV for a MOS device with amorphous neodymium oxide. The temperature dependence of the accumulation capacitance for a MOS structure with crystalline neodymium oxide shows a maximum at about 390 K; such a maximum was not observed for the structure with amorphous neodymium oxide. The method of capacitance-gate voltage (C-Vg) measurements was used to investigate the effect of annealing in air and in vacuum on the surface density of states (Nss) at the insulator/semiconductor (I/S) interface. It was concluded that the density of surface states in the mid-gap increases by about five times while the density of the trapped charges in the oxide layer decreases by about eight times when the oxide crystallises into a polycrystalline structure.

Dual field effects in electrolyte-gated spinel ferrite: electrostatic carrier doping and redox reactions.

PubMed

Ichimura, Takashi; Fujiwara, Kohei; Tanaka, Hidekazu

2014-07-24

Controlling the electronic properties of functional oxide materials via external electric fields has attracted increasing attention as a key technology for next-generation electronics. For transition-metal oxides with metallic carrier densities, the electric-field effect with ionic liquid electrolytes has been widely used because of the enormous carrier doping capabilities. The gate-induced redox reactions revealed by recent investigations have, however, highlighted the complex nature of the electric-field effect. Here, we use the gate-induced conductance modulation of spinel ZnxFe₃₋xO₄ to demonstrate the dual contributions of volatile and non-volatile field effects arising from electronic carrier doping and redox reactions. These two contributions are found to change in opposite senses depending on the Zn content x; virtual electronic and chemical field effects are observed at appropriate Zn compositions. The tuning of field-effect characteristics via composition engineering should be extremely useful for fabricating high-performance oxide field-effect devices.

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Permanent and Transient Radiation Effects on Thin-Oxide (200-A) MOS Transistors

DTIC Science & Technology

1976-06-01

n-channel technology using a SiO, gate-oxide thickness ol ’ 200 A and a %hallow phiosphorus diffusion of 0.5 pin on a 0.7-ohm)-cmn 8-doped > Si...substrate. The thickness of the sell-aligned it polysilicon gate was kept at 3500 A. The oxide was grown in dry 0, at a temperature ot 1000C, followed...semiconductor work function difference (equal to 0 V for the polysilicon gates’ studied here). The effect of the ionizing radiation is to introduce

ISAC's Gating-ML 2.0 data exchange standard for gating description.

PubMed

Spidlen, Josef; Moore, Wayne; Brinkman, Ryan R

2015-07-01

The lack of software interoperability with respect to gating has traditionally been a bottleneck preventing the use of multiple analytical tools and reproducibility of flow cytometry data analysis by independent parties. To address this issue, ISAC developed Gating-ML, a computer file format to encode and interchange gates. Gating-ML 1.5 was adopted and published as an ISAC Candidate Recommendation in 2008. Feedback during the probationary period from implementors, including major commercial software companies, instrument vendors, and the wider community, has led to a streamlined Gating-ML 2.0. Gating-ML has been significantly simplified and therefore easier to support by software tools. To aid developers, free, open source reference implementations, compliance tests, and detailed examples are provided to stimulate further commercial adoption. ISAC has approved Gating-ML as a standard ready for deployment in the public domain and encourages its support within the community as it is at a mature stage of development having undergone extensive review and testing, under both theoretical and practical conditions. © 2015 International Society for Advancement of Cytometry.

Image-guided adaptive gating of lung cancer radiotherapy: a computer simulation study

NASA Astrophysics Data System (ADS)

Aristophanous, Michalis; Rottmann, Joerg; Park, Sang-June; Nishioka, Seiko; Shirato, Hiroki; Berbeco, Ross I.

2010-08-01

regularity of the breathing pattern suggesting that image-guided adaptive gating should be combined with breath coaching. The adaptive gating window technique was able to track the exhale position of the breathing cycle quite successfully. Out of a total of 53 fractions the duty cycle was greater than 20% for 42 fractions for the fixed gating window technique and for 39 fractions for the adaptive gating window technique. The results of this study suggest that real-time updating of the gating window can result in reliably low residual tumor motion and therefore can facilitate safe margin reduction.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Mechanical reliability and life prediction of coated metallic interconnects within solid oxide fuel cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Zhijie; Xu, Wei; Stephens, Elizabeth

Metallic cell interconnects (IC) made of ferritic stainless steels, i.e., iron-based alloys, have been increasingly favored in the recent development of planar solid oxide fuel cells (SOFCs) because of their advantages in excellent imperviousness, low electrical resistance, ease in fabrication, and cost effectiveness. Typical SOFC operating conditions inevitably lead to the formation of oxide scales on the surface of ferritic stainless steel, which could cause delamination, buckling, and spallation resulting from the mismatch of the coefficient of thermal expansion and eventually reduce the lifetime of the interconnect components. Various protective coating techniques have been applied to alleviate these drawbacks. Inmore » the present work, a fracture-mechanics-based quantitative modeling framework has been established to predict the mechanical reliability and lifetime of the spinel-coated, surface-modified specimens under an isothermal cooling cycle. Analytical solutions have been formulated to evaluate the scale/substrate interfacial strength and determine the critical oxide thickness in terms of a variety of design factors, such as coating thickness, material properties, and uncertainties. In conclusion, the findings then are correlated with the experimentally measured oxide scale growth kinetics to quantify the predicted lifetime of the metallic interconnects.« less

Mechanical reliability and life prediction of coated metallic interconnects within solid oxide fuel cells

DOE PAGES

Xu, Zhijie; Xu, Wei; Stephens, Elizabeth; ...

2017-07-03

Metallic cell interconnects (IC) made of ferritic stainless steels, i.e., iron-based alloys, have been increasingly favored in the recent development of planar solid oxide fuel cells (SOFCs) because of their advantages in excellent imperviousness, low electrical resistance, ease in fabrication, and cost effectiveness. Typical SOFC operating conditions inevitably lead to the formation of oxide scales on the surface of ferritic stainless steel, which could cause delamination, buckling, and spallation resulting from the mismatch of the coefficient of thermal expansion and eventually reduce the lifetime of the interconnect components. Various protective coating techniques have been applied to alleviate these drawbacks. Inmore » the present work, a fracture-mechanics-based quantitative modeling framework has been established to predict the mechanical reliability and lifetime of the spinel-coated, surface-modified specimens under an isothermal cooling cycle. Analytical solutions have been formulated to evaluate the scale/substrate interfacial strength and determine the critical oxide thickness in terms of a variety of design factors, such as coating thickness, material properties, and uncertainties. In conclusion, the findings then are correlated with the experimentally measured oxide scale growth kinetics to quantify the predicted lifetime of the metallic interconnects.« less

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

"Why not stoichiometry" versus "Stoichiometry--why not?" Part II: GATES in context with redox systems.

PubMed

Michałowska-Kaczmarczyk, Anna Maria; Asuero, Agustin G; Toporek, Marcin; Michałowski, Tadeusz

2015-01-01

Redox equilibria and titration play an important role in chemical analysis, and the formulation of an accurate mathematical description is a challenge. This article is devoted to static and (mainly) dynamic redox systems; the dynamic systems are represented by redox titrations. An overview addresses earlier approaches to static redox systems (redox diagram plots, including Pourbaix diagrams) and to titration redox systems, thereby covering a gap in the literature. After this short review, the generalized approach to electrolytic systems (GATES) is introduced, with generalized electron balance (GEB) as its inherent part within GATES/GEB. Computer simulation, performed according to GATES/GEB, enables following the changes in potential and pH of the solution, together with chemical speciation at each step of a titration, thus providing better insight into this procedure. The undeniable advantages of GATES/GEB over earlier approaches are indicated. Formulation of GEB according to two approaches (I and II) is presented on the respective examples. A general criterion distinguishing between non-redox and redox systems is presented. It is indicated that the formulation of GEB according to Approach II does not need the knowledge of oxidation degrees of particular elements; knowledge of the composition, expressed by chemical formula of the species and its charge, is sufficient for this purpose. Approach I to GEB, known also as the "short" version of GEB, is applicable if oxidation degrees for all elements of the system are known beforehand. The roles of oxidants and reductants are not ascribed to particular components forming a system and to the species thus formed. This is the complete opposite of earlier approaches to redox titrations, based on the stoichiometric redox reaction, formulated for this purpose. GEB, perceived as a law of matter conservation, is fully compatible with other (charge and concentration) balances related to the system in question. The applicability

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Design and fabrication of high-performance diamond triple-gate field-effect transistors

PubMed Central

Liu, Jiangwei; Ohsato, Hirotaka; Wang, Xi; Liao, Meiyong; Koide, Yasuo

2016-01-01

The lack of large-area single-crystal diamond wafers has led us to downscale diamond electronic devices. Here, we design and fabricate a hydrogenated diamond (H-diamond) triple-gate metal-oxide-semiconductor field-effect transistor (MOSFET) to extend device downscaling and increase device output current. The device’s electrical properties are compared with those of planar-type MOSFETs, which are fabricated simultaneously on the same substrate. The triple-gate MOSFET’s output current (174.2 mA mm−1) is much higher than that of the planar-type device (45.2 mA mm−1), and the on/off ratio and subthreshold swing are more than 108 and as low as 110 mV dec−1, respectively. The fabrication of these H-diamond triple-gate MOSFETs will drive diamond electronic device development forward towards practical applications. PMID:27708372

Gated strip proportional detector

DOEpatents

Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

1985-02-19

A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

Gated strip proportional detector

DOEpatents

Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

1987-01-01

A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

Optical NAND gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Raring, James [Goleta, CA; Tauke-Pedretti, Anna [Albuquerque, NM

2011-08-09

An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Preparation of gallium nitride surfaces for atomic layer deposition of aluminum oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kerr, A. J.; Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093; Chagarov, E.

2014-09-14

A combined wet and dry cleaning process for GaN(0001) has been investigated with XPS and DFT-MD modeling to determine the molecular-level mechanisms for cleaning and the subsequent nucleation of gate oxide atomic layer deposition (ALD). In situ XPS studies show that for the wet sulfur treatment on GaN(0001), sulfur desorbs at room temperature in vacuum prior to gate oxide deposition. Angle resolved depth profiling XPS post-ALD deposition shows that the a-Al{sub 2}O{sub 3} gate oxide bonds directly to the GaN substrate leaving both the gallium surface atoms and the oxide interfacial atoms with XPS chemical shifts consistent with bulk-like charge.more » These results are in agreement with DFT calculations that predict the oxide/GaN(0001) interface will have bulk-like charges and a low density of band gap states. This passivation is consistent with the oxide restoring the surface gallium atoms to tetrahedral bonding by eliminating the gallium empty dangling bonds on bulk terminated GaN(0001)« less

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

Highly Efficient Gating of Electrically Actuated Nanochannels for Pulsatile Drug Delivery Stemming from a Reversible Wettability Switch.

PubMed

Zhang, Qianqian; Kang, Jianxin; Xie, Zhiqiang; Diao, Xungang; Liu, Zhaoyue; Zhai, Jin

2018-01-01

Many ion channels in the cell membrane are believed to function as gates that control the water and ion flow through the transitions between an inherent hydrophobic state and a stimuli-induced hydration state. The construction of nanofluidic gating systems with high gating efficiency and reversibility is inspired by this hydrophobic gating behavior. A kind of electrically actuated nanochannel is developed by integrating a polypyrrole (PPy) micro/nanoporous film doped with perfluorooctanesulfonate ions onto an anodic aluminum oxide nanoporous membrane. Stemming from the reversible wettability switch of the doped PPy film in response to the applied redox potentials, the nanochannels exhibit highly efficient and reversible gating behaviors. The optimized gating ratio is over 10 5 , which is an ultrahigh value when compared with that of the existing reversibly gated nanochannels with comparable pore diameters. Furthermore, the gating behavior of the electrically actuated nanochannels shows excellent repeatability and stability. Based on this highly efficient and reversible gating function, the electrically actuated nanochannels are further applied for drug delivery, which achieves the pulsatile release of two water-soluble drug models. The electrically actuated nanochannels may find potential applications in accurate and on-demand drug therapy. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance

NASA Astrophysics Data System (ADS)

Dash, S.; Mishra, G. P.

2015-09-01

A 2D analytical tunnel field-effect transistor (FET) potential model with cylindrical gate (CG-TFET) based on the solution of Laplace’s equation is proposed. The band-to-band tunneling (BTBT) current is derived by the help of lateral electric field and the shortest tunneling distance. However, the analysis is extended to obtain the subthreshold swing (SS) and transfer characteristics of the device. The dependency of drain current, SS and transconductance on gate voltage and shortest tunneling distance is discussed. Also, the effect of scaling the gate oxide thickness and the cylindrical body diameter on the electrical parameters of the device is analyzed.

Ratiometric Time-Gated Luminescence Probe for Nitric Oxide Based on an Apoferritin-Assembled Lanthanide Complex-Rhodamine Luminescence Resonance Energy Transfer System.

PubMed

Tian, Lu; Dai, Zhichao; Liu, Xiangli; Song, Bo; Ye, Zhiqiang; Yuan, Jingli

2015-11-03

Using apoferritin (AFt) as a carrier, a novel ratiometric luminescence probe based on luminescence resonance energy transfer (LRET) between a Tb(3+) complex (PTTA-Tb(3+)) and a rhodamine derivative (Rh-NO), PTTA-Tb(3+)@AFt-Rh-NO, has been designed and prepared for the specific recognition and time-gated luminescence detection of nitric oxide (NO) in living samples. In this LRET probe, PTTA-Tb(3+) encapsulated in the core of AFt is the energy donor, and Rh-NO, a NO-responsive rhodamine derivative, bound on the surface of AFt is the energy acceptor. The probe only emits strong Tb(3+) luminescence because the emission of rhodamine is switched off in the absence of NO. Upon reaction with NO, accompanied by the turn-on of rhodamine emission, the LRET from Tb(3+) complex to rhodamine occurs, which results in the remarkable increase and decrease of the long-lived emissions of rhodamine and PTTA-Tb(3+), respectively. After the reaction, the intensity ratio of rhodamine emission to Tb(3+) emission, I565/I539, is ∼24.5-fold increased, and the dose-dependent enhancement of I565/I539 shows a good linearity in a wide concentration range of NO. This unique luminescence response allowed PTTA-Tb(3+)@AFt-Rh-NO to be conveniently used as a ratiometric probe for the time-gated luminescence detection of NO with I565/I539 as a signal. Taking advantages of high specificity and sensitivity of the probe as well as its good water-solubility, biocompatibility, and cell membrane permeability, PTTA-Tb(3+)@AFt-Rh-NO was successfully used for the luminescent imaging of NO in living cells and Daphnia magna. The results demonstrated the efficacy of the probe and highlighted it's advantages for the ratiometric time-gated luminescence bioimaging application.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

NASA Astrophysics Data System (ADS)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xu; Zeng, Zhen-Hua; Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029

2014-09-01

Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to themore » sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.« less

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

PubMed

Liu, Huixuan; Xun, Damao

2018-04-01

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

NASA Astrophysics Data System (ADS)

Condori Quispe, Hugo O.; Encomendero-Risco, Jimy J.; Xing, Huili Grace; Sensale-Rodriguez, Berardi

2016-08-01

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

Highly Conductive and Reliable Copper-Filled Isotropically Conductive Adhesives Using Organic Acids for Oxidation Prevention

NASA Astrophysics Data System (ADS)

Chen, Wenjun; Deng, Dunying; Cheng, Yuanrong; Xiao, Fei

2015-07-01

The easy oxidation of copper is one critical obstacle to high-performance copper-filled isotropically conductive adhesives (ICAs). In this paper, a facile method to prepare highly reliable, highly conductive, and low-cost ICAs is reported. The copper fillers were treated by organic acids for oxidation prevention. Compared with ICA filled with untreated copper flakes, the ICA filled with copper flakes treated by different organic acids exhibited much lower bulk resistivity. The lowest bulk resistivity achieved was 4.5 × 10-5 Ω cm, which is comparable to that of commercially available Ag-filled ICA. After 500 h of 85°C/85% relative humidity (RH) aging, the treated ICAs showed quite stable bulk resistivity and relatively stable contact resistance. Through analyzing the results of x-ray diffraction, x-ray photoelectron spectroscopy, and thermogravimetric analysis, we found that, with the assistance of organic acids, the treated copper flakes exhibited resistance to oxidation, thus guaranteeing good performance.

3. VIEW OF MECHANICAL GATE LIFTING MECHANISM (MULE) AND GATE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

3. VIEW OF MECHANICAL GATE LIFTING MECHANISM (MULE) AND GATE RACKS, LOOKING EAST - Nine Mile Hydroelectric Development, Powerhouse, State Highway 291 along Spokane River, Nine Mile Falls, Spokane County, WA

Cardiac-gated, phase contrast magnetic resonance angiography is a reliable and reproducible technique for quantifying blood flow in canine major cranial abdominal vessels.

PubMed

Del Chicca, Francesca; Schwarz, Andrea; Grest, Paula; Willmitzer, Florian; Dennler, Matthias; Kircher, Patrick R

2018-04-17

Blood flow changes in cranial abdominal vessels are important contributing factors for canine hepatic disease. This prospective, experimental, pilot study aimed to evaluate cardiac-gated, phase contrast magnetic resonance angiography (PCMRA) as a method for characterizing blood flow in canine major cranial abdominal vessels. Eleven, healthy, adult beagle dogs were sampled. Cardiac-gated, phase contrast magnetic resonance angiography of the cranial abdomen was performed in each dog and blood flow was independently measured in each of the major cranial abdominal vessels by three observers, with two observers recording blood flow values once and one observer recording blood flow values three times. Each dog then underwent ultrasonographic examination of the liver with fine needle aspirations and biopsies submitted to cytologic and histologic examination. The mean absolute stroke volume and velocity were respectively 9.6 ± 1.9 ml and -11.1 ± 1.1 cm/s for the cranial abdominal aorta, 2.1 ± 0.6 ml and -6.6 ± 1.9 cm/s for the celiac artery, and 2.3 ± 1.0 ml and -7.9 ± 3.1 cm/s for the cranial mesenteric artery. The mean absolute stroke volume and velocity were respectively 6.7 ± 1.3 ml and 3.9 ± 0.9 cm/s for the caudal vena cava and 2.6 ± 0.9 ml and 3.2 ± 1.2 cm/s for the portal vein. Intraobserver reliability was excellent (intraclass correlation coefficient > 0.9). Interobserver reproducibility was also excellent (intraclass correlation coefficient 0.89-0.99). Results of liver ultrasonography, cytology, and histopathology were unremarkable. Findings indicated that cardiac-gated, phase contrast magnetic resonance angiography is a feasible technique for quantifying blood blow in canine major cranial abdominal vessels. Blood flow values from this sample of healthy beagles can be used as background for future studies on canine hepatic disease. © 2018 American College of Veterinary Radiology.

TH-CD-207A-04: Optimized Respiratory Gating for Abnormal Breathers in Pancreatic SBRT

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, W; Miften, M; Schefter, T

significantly better results than end-inhalation. Conclusion: Amplitude-based gating reliably outperformed phase-based gating, and end-exhalation was more suitable than end-inhalation. These results will be used to guide future dose-escalation trials. Research funding provided by Varian Medical Systems to Miften and Jones.« less

[The anesthetic effects of Gow-Gates technique of inferior alveolar nerve block in impacted mandibular third molar extraction].

PubMed

Yang, Jieping; Liu, Wei; Gao, Qinghong

2013-08-01

To evaluate the anesthetic effects and safety of Gow-Gates technique of inferior alveolar nerve block in impacted mandibular third molar extraction. A split-mouth study was designed. The bilateral impacted mandibular third molar of 32 participants were divided into Gow-Gates technique of inferior alveolar nerve block (Gow-Gates group) and conventional technique of inferior alveolar nerve block (conventional group) randomly with third molar extracted. The anesthetic effects and adverse events were recorded. All the participants completed the research. The anesthetic success rate was 96.9% in Gow-Gates group and 90.6% in conventional group with no statistical difference ( P= 0.317); but when comparing the anesthesia grade, Gow-Gates group had a 96.9% of grade A and B, and conventional group had a rate of 78.1% (P = 0.034). And the Gow-Gates group had a much lower withdrawn bleeding than conventional group (P = 0.025). Two groups had no hematoma. Gow-Gates technique had a reliable anesthesia effects and safety in impacted mandibular third molar extraction and could be chosen as a candidate for the conventional inferior alveolar nerve block.

2. VIEW OF MECHANICAL GATE LIFTING MECHANISM (MULE) AND GATE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

2. VIEW OF MECHANICAL GATE LIFTING MECHANISM (MULE) AND GATE LIFTING RACKS, LOOKING WEST - Nine Mile Hydroelectric Development, Powerhouse, State Highway 291 along Spokane River, Nine Mile Falls, Spokane County, WA

EduGATE - basic examples for educative purpose using the GATE simulation platform.

PubMed

Pietrzyk, Uwe; Zakhnini, Abdelhamid; Axer, Markus; Sauerzapf, Sophie; Benoit, Didier; Gaens, Michaela

2013-02-01

EduGATE is a collection of basic examples to introduce students to the fundamental physical aspects of medical imaging devices. It is based on the GATE platform, which has received a wide acceptance in the field of simulating medical imaging devices including SPECT, PET, CT and also applications in radiation therapy. GATE can be configured by commands, which are, for the sake of simplicity, listed in a collection of one or more macro files to set up phantoms, multiple types of sources, detection device, and acquisition parameters. The aim of the EduGATE is to use all these helpful features of GATE to provide insights into the physics of medical imaging by means of a collection of very basic and simple GATE macros in connection with analysis programs based on ROOT, a framework for data processing. A graphical user interface to define a configuration is also included. Copyright © 2012. Published by Elsevier GmbH.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Condori Quispe, Hugo O.; Sensale-Rodriguez, Berardi; Encomendero-Risco, Jimy J.

2016-08-08

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Silicon carbide: A unique platform for metal-oxide-semiconductor physics

NASA Astrophysics Data System (ADS)

Liu, Gang; Tuttle, Blair R.; Dhar, Sarit

2015-06-01

A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO2/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.

Gate-Induced Interfacial Superconductivity in 1T-SnSe2.

PubMed

Zeng, Junwen; Liu, Erfu; Fu, Yajun; Chen, Zhuoyu; Pan, Chen; Wang, Chenyu; Wang, Miao; Wang, Yaojia; Xu, Kang; Cai, Songhua; Yan, Xingxu; Wang, Yu; Liu, Xiaowei; Wang, Peng; Liang, Shi-Jun; Cui, Yi; Hwang, Harold Y; Yuan, Hongtao; Miao, Feng

2018-02-14

Layered metal chalcogenide materials provide a versatile platform to investigate emergent phenomena and two-dimensional (2D) superconductivity at/near the atomically thin limit. In particular, gate-induced interfacial superconductivity realized by the use of an electric-double-layer transistor (EDLT) has greatly extended the capability to electrically induce superconductivity in oxides, nitrides, and transition metal chalcogenides and enable one to explore new physics, such as the Ising pairing mechanism. Exploiting gate-induced superconductivity in various materials can provide us with additional platforms to understand emergent interfacial superconductivity. Here, we report the discovery of gate-induced 2D superconductivity in layered 1T-SnSe 2 , a typical member of the main-group metal dichalcogenide (MDC) family, using an EDLT gating geometry. A superconducting transition temperature T c ≈ 3.9 K was demonstrated at the EDL interface. The 2D nature of the superconductivity therein was further confirmed based on (1) a 2D Tinkham description of the angle-dependent upper critical field B c2 , (2) the existence of a quantum creep state as well as a large ratio of the coherence length to the thickness of superconductivity. Interestingly, the in-plane B c2 approaching zero temperature was found to be 2-3 times higher than the Pauli limit, which might be related to an electric field-modulated spin-orbit interaction. Such results provide a new perspective to expand the material matrix available for gate-induced 2D superconductivity and the fundamental understanding of interfacial superconductivity.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

NASA Astrophysics Data System (ADS)

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-02-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future.

Highly sensitive glucose sensors based on enzyme-modified whole-graphene solution-gated transistors

PubMed Central

Zhang, Meng; Liao, Caizhi; Mak, Chun Hin; You, Peng; Mak, Chee Leung; Yan, Feng

2015-01-01

Noninvasive glucose detections are convenient techniques for the diagnosis of diabetes mellitus, which require high performance glucose sensors. However, conventional electrochemical glucose sensors are not sensitive enough for these applications. Here, highly sensitive glucose sensors are successfully realized based on whole-graphene solution-gated transistors with the graphene gate electrodes modified with an enzyme glucose oxidase. The sensitivity of the devices is dramatically improved by co-modifying the graphene gates with Pt nanoparticles due to the enhanced electrocatalytic activity of the electrodes. The sensing mechanism is attributed to the reaction of H2O2 generated by the oxidation of glucose near the gate. The optimized glucose sensors show the detection limits down to 0.5 μM and good selectivity, which are sensitive enough for non-invasive glucose detections in body fluids. The devices show the transconductances two orders of magnitude higher than that of a conventional silicon field effect transistor, which is the main reason for their high sensitivity. Moreover, the devices can be conveniently fabricated with low cost. Therefore, the whole-graphene solution-gated transistors are a high-performance sensing platform for not only glucose detections but also many other types of biosensors that may find practical applications in the near future. PMID:25655666

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

NASA Astrophysics Data System (ADS)

Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

2014-01-01

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

Acute aortic syndromes: new insights from electrocardiographically gated computed tomography.

PubMed

Fleischmann, Dominik; Mitchell, R Scott; Miller, D Craig

2008-01-01

The development of retrospective electrocardiographic (ECG)-gating has proved to be a diagnostic and therapeutic boon for computed tomography (CT) imaging of patients with acute thoracic aortic diseases, such as aortic dissection/intramural hematoma (AD/IMH), penetrating atherosclerotic ulcer (APU), and ruptured/leaking aneurysm. The notorious pulsation motion artifacts in the ascending aorta confounding regular CT scanning can be eliminated, and involvement of the sinuses of Valsalva, the valve cusps, the aortic annulus, and the coronary arteries in aortic dissection can be clearly depicted or excluded. Motion-free images also allow reliable identification of the site of the primary intimal tear, the location, and extent of the intimomedial flap, and branch artery involvement. ECG-gated CTA also allows the detection of more subtle lesions and variants of aortic dissection, which may ultimately expand our understanding of these complex, life-threatening disorders.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Properties of the correlated metal phase induced by electrolyte gating of insulating vanadium dioxide nanobeams

NASA Astrophysics Data System (ADS)

Singh, Sujay; Horrocks, Gregory; Marley, Peter; Banerjee, Sarbajit; Sambandamurthy, G.

2014-03-01

Vanadium oxide (VO2) undergoes a first order metal to insulator transition (MIT) and a structural phase transition (monoclinic insulator to rutile metal) near 340 K. Over the past few years, several attempts are made to trigger the MIT in VO2 using ionic liquids (IL). Parkin's group has recently showed that IL gating leads to the creation of oxygen vacancies in VO2 and stabilizes the metallic phase. Our goal is to study the electronic properties, changes in the stoichiometry and structure of this metallic phase created by oxygen vacancies. Electrical transport measurements on single crystal nanobeams show that the metallic phase has a higher resistance while IL gating is applied and results from Raman spectroscopy studies on any structural change during IL gating will be presented. The role of substitutional dopants (such as W, Mo) on the creation of oxygen vacancies and subsequent stabilization of metallic phase in IL gated experiments will also be discussed. The work is supported by NSF DMR 0847324 and 0847169.

Stable indium oxide thin-film transistors with fast threshold voltage recovery

NASA Astrophysics Data System (ADS)

Vygranenko, Yuriy; Wang, Kai; Nathan, Arokia

2007-12-01

Stable thin-film transistors (TFTs) with semiconducting indium oxide channel and silicon dioxide gate dielectric were fabricated by reactive ion beam assisted evaporation and plasma-enhanced chemical vapor deposition. The field-effect mobility is 3.3cm2/Vs, along with an on/off current ratio of 106, and subthreshold slope of 0.5V/decade. When subject to long-term gate bias stress, the TFTs show fast recovery of the threshold voltage (VT) when relaxed without annealing, suggesting that charge trapping at the interface and/or in the bulk gate dielectric to be the dominant mechanism underlying VT instability. Device performance and stability make indium oxide TFTs promising for display applications.

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Deletion of cytosolic gating ring decreases gate and voltage sensor coupling in BK channels.

PubMed

Zhang, Guohui; Geng, Yanyan; Jin, Yakang; Shi, Jingyi; McFarland, Kelli; Magleby, Karl L; Salkoff, Lawrence; Cui, Jianmin

2017-03-06

Large conductance Ca 2+ -activated K + channels (BK channels) gate open in response to both membrane voltage and intracellular Ca 2+ The channel is formed by a central pore-gate domain (PGD), which spans the membrane, plus transmembrane voltage sensors and a cytoplasmic gating ring that acts as a Ca 2+ sensor. How these voltage and Ca 2+ sensors influence the common activation gate, and interact with each other, is unclear. A previous study showed that a BK channel core lacking the entire cytoplasmic gating ring (Core-MT) was devoid of Ca 2+ activation but retained voltage sensitivity (Budelli et al. 2013. Proc. Natl. Acad. Sci. USA http://dx.doi.org/10.1073/pnas.1313433110). In this study, we measure voltage sensor activation and pore opening in this Core-MT channel over a wide range of voltages. We record gating currents and find that voltage sensor activation in this truncated channel is similar to WT but that the coupling between voltage sensor activation and gating of the pore is reduced. These results suggest that the gating ring, in addition to being the Ca 2+ sensor, enhances the effective coupling between voltage sensors and the PGD. We also find that removal of the gating ring alters modulation of the channels by the BK channel's β1 and β2 subunits. © 2017 Zhang et al.

Deletion of cytosolic gating ring decreases gate and voltage sensor coupling in BK channels

PubMed Central

Zhang, Guohui; Shi, Jingyi; McFarland, Kelli; Magleby, Karl L.; Salkoff, Lawrence

2017-01-01

Large conductance Ca2+-activated K+ channels (BK channels) gate open in response to both membrane voltage and intracellular Ca2+. The channel is formed by a central pore-gate domain (PGD), which spans the membrane, plus transmembrane voltage sensors and a cytoplasmic gating ring that acts as a Ca2+ sensor. How these voltage and Ca2+ sensors influence the common activation gate, and interact with each other, is unclear. A previous study showed that a BK channel core lacking the entire cytoplasmic gating ring (Core-MT) was devoid of Ca2+ activation but retained voltage sensitivity (Budelli et al. 2013. Proc. Natl. Acad. Sci. USA. http://dx.doi.org/10.1073/pnas.1313433110). In this study, we measure voltage sensor activation and pore opening in this Core-MT channel over a wide range of voltages. We record gating currents and find that voltage sensor activation in this truncated channel is similar to WT but that the coupling between voltage sensor activation and gating of the pore is reduced. These results suggest that the gating ring, in addition to being the Ca2+ sensor, enhances the effective coupling between voltage sensors and the PGD. We also find that removal of the gating ring alters modulation of the channels by the BK channel’s β1 and β2 subunits. PMID:28196879

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Advanced insulated gate bipolar transistor gate drive

DOEpatents

Short, James Evans [Monongahela, PA; West, Shawn Michael [West Mifflin, PA; Fabean, Robert J [Donora, PA

2009-08-04

A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

Improved scatterer property estimates from ultrasound backscatter for small gate lengths using a gate-edge correction factor

NASA Astrophysics Data System (ADS)

Oelze, Michael L.; O'Brien, William D.

2004-11-01

Backscattered rf signals used to construct conventional ultrasound B-mode images contain frequency-dependent information that can be examined through the backscattered power spectrum. The backscattered power spectrum is found by taking the magnitude squared of the Fourier transform of a gated time segment corresponding to a region in the scattering volume. When a time segment is gated, the edges of the gated regions change the frequency content of the backscattered power spectrum due to truncating of the waveform. Tapered windows, like the Hanning window, and longer gate lengths reduce the relative contribution of the gate-edge effects. A new gate-edge correction factor was developed that partially accounted for the edge effects. The gate-edge correction factor gave more accurate estimates of scatterer properties at small gate lengths compared to conventional windowing functions. The gate-edge correction factor gave estimates of scatterer properties within 5% of actual values at very small gate lengths (less than 5 spatial pulse lengths) in both simulations and from measurements on glass-bead phantoms. While the gate-edge correction factor gave higher accuracy of estimates at smaller gate lengths, the precision of estimates was not improved at small gate lengths over conventional windowing functions. .

Time-Reversal MUSIC Imaging with Time-Domain Gating Technique

NASA Astrophysics Data System (ADS)

Choi, Heedong; Ogawa, Yasutaka; Nishimura, Toshihiko; Ohgane, Takeo

A time-reversal (TR) approach with multiple signal classification (MUSIC) provides super-resolution for detection and localization using multistatic data collected from an array antenna system. The theory of TR-MUSIC assumes that the number of antenna elements is greater than that of scatterers (targets). Furthermore, it requires many sets of frequency-domain data (snapshots) in seriously noisy environments. Unfortunately, these conditions are not practical for real environments due to the restriction of a reasonable antenna structure as well as limited measurement time. We propose an approach that treats both noise reduction and relaxation of the transceiver restriction by using a time-domain gating technique accompanied with the Fourier transform before applying the TR-MUSIC imaging algorithm. Instead of utilizing the conventional multistatic data matrix (MDM), we employ a modified MDM obtained from the gating technique. The resulting imaging functions yield more reliable images with only a few snapshots regardless of the limitation of the antenna arrays.

Decarboxylative alkylation for site-selective bioconjugation of native proteins via oxidation potentials.

PubMed

Bloom, Steven; Liu, Chun; Kölmel, Dominik K; Qiao, Jennifer X; Zhang, Yong; Poss, Michael A; Ewing, William R; MacMillan, David W C

2018-02-01

The advent of antibody-drug conjugates as pharmaceuticals has fuelled a need for reliable methods of site-selective protein modification that furnish homogeneous adducts. Although bioorthogonal methods that use engineered amino acids often provide an elegant solution to the question of selective functionalization, achieving homogeneity using native amino acids remains a challenge. Here, we explore visible-light-mediated single-electron transfer as a mechanism towards enabling site- and chemoselective bioconjugation. Specifically, we demonstrate the use of photoredox catalysis as a platform to selectivity wherein the discrepancy in oxidation potentials between internal versus C-terminal carboxylates can be exploited towards obtaining C-terminal functionalization exclusively. This oxidation potential-gated technology is amenable to endogenous peptides and has been successfully demonstrated on the protein insulin. As a fundamentally new approach to bioconjugation this methodology provides a blueprint toward the development of photoredox catalysis as a generic platform to target other redox-active side chains for native conjugation.

Decarboxylative alkylation for site-selective bioconjugation of native proteins via oxidation potentials

NASA Astrophysics Data System (ADS)

Bloom, Steven; Liu, Chun; Kölmel, Dominik K.; Qiao, Jennifer X.; Zhang, Yong; Poss, Michael A.; Ewing, William R.; MacMillan, David W. C.

2018-02-01

The advent of antibody-drug conjugates as pharmaceuticals has fuelled a need for reliable methods of site-selective protein modification that furnish homogeneous adducts. Although bioorthogonal methods that use engineered amino acids often provide an elegant solution to the question of selective functionalization, achieving homogeneity using native amino acids remains a challenge. Here, we explore visible-light-mediated single-electron transfer as a mechanism towards enabling site- and chemoselective bioconjugation. Specifically, we demonstrate the use of photoredox catalysis as a platform to selectivity wherein the discrepancy in oxidation potentials between internal versus C-terminal carboxylates can be exploited towards obtaining C-terminal functionalization exclusively. This oxidation potential-gated technology is amenable to endogenous peptides and has been successfully demonstrated on the protein insulin. As a fundamentally new approach to bioconjugation this methodology provides a blueprint toward the development of photoredox catalysis as a generic platform to target other redox-active side chains for native conjugation.

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Impact of gate geometry on ionic liquid gated ionotronic systems

DOE PAGES

Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

2017-01-23

Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

Extraction of carrier mobility and interface trap density in InGaAs metal oxide semiconductor structures using gated Hall method

NASA Astrophysics Data System (ADS)

Chidambaram, Thenappan

III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for D it and mobility. Here we employ gated Hall method to quantify the D it spectrum at the high-K oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values.

The four-gate transistor

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

2002-01-01

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

Lithium ion intercalation in thin crystals of hexagonal TaSe2 gated by a polymer electrolyte

NASA Astrophysics Data System (ADS)

Wu, Yueshen; Lian, Hailong; He, Jiaming; Liu, Jinyu; Wang, Shun; Xing, Hui; Mao, Zhiqiang; Liu, Ying

2018-01-01

Ionic liquid gating has been used to modify the properties of layered transition metal dichalcogenides (TMDCs), including two-dimensional (2D) crystals of TMDCs used extensively recently in the device work, which has led to observations of properties not seen in the bulk. The main effect comes from the electrostatic gating due to the strong electric field at the interface. In addition, ionic liquid gating also leads to ion intercalation when the ion size of the gate electrolyte is small compared to the interlayer spacing of TMDCs. However, the microscopic processes of ion intercalation have rarely been explored in layered TMDCs. Here, we employed a technique combining photolithography device fabrication and electrical transport measurements on the thin crystals of hexagonal TaSe2 using multiple channel devices gated by a polymer electrolyte LiClO4/Polyethylene oxide (PEO). The gate voltage and time dependent source-drain resistances of these thin crystals were used to obtain information on the intercalation process, the effect of ion intercalation, and the correlation between the ion occupation of allowed interstitial sites and the device characteristics. We found a gate voltage controlled modulation of the charge density waves and a scattering rate of charge carriers. Our work suggests that ion intercalation can be a useful tool for layered materials engineering and 2D crystal device design.

Stability study of solution-processed zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Zhang, Xue; Ndabakuranye, Jean Pierre; Kim, Dong Wook; Choi, Jong Sun; Park, Jaehoon

2015-11-01

In this study, the environmental dependence of the electrical stability of solution-processed n-channel zinc tin oxide (ZTO) thin-film transistors (TFTs) is reported. Under a prolonged negative gate bias stress, a negative shift in threshold voltage occurs in atmospheric air, whereas a negligible positive shift in threshold voltage occurs under vacuum. In the positive bias-stress experiments, a positive shift in threshold voltage was invariably observed both in atmospheric air and under vacuum. In this study, the negative gate-bias-stress-induced instability in atmospheric air is explained through an internal potential in the ZTO semiconductor, which can be generated owing to the interplay between H2O molecules and majority carrier electrons at the surface of the ZTO film. The positive bias-stress-induced instability is ascribed to electron-trapping phenomenon in and around the TFT channel region, which can be further augmented in the presence of air O2 molecules. These results suggest that the interaction between majority carriers and air molecules will have crucial implications for a reliable operation of solution-processed ZTO TFTs. [Figure not available: see fulltext.

12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

12. INTERIOR VIEW OF GATE OPERATOR ROOM, SHOWING SLIDES GATE OPERATORS, LOOKING NORTHWEST. - Sacramento River Water Treatment Plant Intake Pier & Access Bridge, Spanning Sacramento River approximately 175 feet west of eastern levee on river; roughly .5 mile downstream from confluence of Sacramento & American Rivers, Sacramento, Sacramento County, CA

Effects of plasma-induced charging damage on random telegraph noise in metal-oxide-semiconductor field-effect transistors with SiO2 and high-k gate dielectrics

NASA Astrophysics Data System (ADS)

Kamei, Masayuki; Takao, Yoshinori; Eriguchi, Koji; Ono, Kouichi

2014-01-01

We clarified in this study how plasma-induced charging damage (PCD) affects the so-called “random telegraph noise (RTN)” — a principal concern in designing ultimately scaled large-scale integrated circuits (LSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) with SiO2 and high-k gate dielectric were exposed to an inductively coupled plasma (ICP) with Ar gas. Drain current vs gate voltage (Ids-Vg) characteristics were obtained before and after the ICP plasma exposure for the same device. Then, the time evolution of Ids fluctuation defined as Ids/μIds was measured, where μIds is the mean Ids. This value corresponds to an RTN feature, and RTN was obtained under various gate voltages (Vg) by a customized measurement technique. We focused on the statistical distribution width of (Ids/μIds), δ(Ids/μIds), in order to clarify the effects of PCD on RTN. δ(Ids/μIds) was increased by PCD for both MOSFETs with the SiO2 and high-k gate dielectrics, suggesting that RTN can be used as a measure of PCD, i.e., a distribution width increase directly indicates the presence of PCD. The dependence of δ(Ids/μIds) on the overdrive voltage Vg-Vth, where Vth is the threshold voltage, was investigated by the present technique. It was confirmed that δ(Ids/μIds) increased with a decrease in the overdrive voltage for MOSFETs with the SiO2 and high-k gate dielectrics. The presence of created carrier trap sites with PCD was characterized by the time constants for carrier capture and emission. The threshold voltage shift (ΔVth) induced by PCD was also evaluated and compared with the RTN change, to correlate the RTN increase with ΔVth induced by PCD. Although the estimated time constants exhibited complex behaviors due to the nature of trap sites created by PCD, δ(Ids/μIds) showed a straightforward tendency in accordance with the amount of PCD. These findings provide an in-depth understanding of plasma-induced RTN characteristic changes in future MOSFETs.

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

Reading Gate Positions with a Smartphone

NASA Astrophysics Data System (ADS)

van Overloop, Peter-Jules; Hut, Rolf

2015-04-01

Worldwide many flow gates are built in water networks in order to direct water to appropriate locations. Most of these gates are adjusted manually by field operators of water management organizations and it is often centrally not known what the new position of the gate is. This makes centralized management of the entire water network difficult. One of the reasons why the measurement of the gate position is usually not executed, is that for certain gates it is not easy to do such a reading. Tilting weirs or radial gates are examples where operators need special equipment (measuring rod and long level) to determine the position and it could even be a risky procedure. Another issue is that once the measurement is done, the value is jotted down in a notebook and later, at the office, entered in a computer system. So the entire monitoring procedure is not real-time and prone to human errors. A new way of monitoring gate positions is introduced. It consists of a level that is attached to the gate and an app with which a picture can be taken from the level. Using dedicated pattern recognition algorithms, the gate position can be read by using the angle of the level versus reference points on the gate, the radius of that gate and the absolute level of the joint around which the gate turn. The method uses gps-localization of the smartphone to store the gate position in the right location in the central database.

Effect of active-layer composition and structure on device performance of coplanar top-gate amorphous oxide thin-film transistors

NASA Astrophysics Data System (ADS)

Yue, Lan; Meng, Fanxin; Chen, Jiarong

2018-01-01

The thin-film transistors (TFTs) with amorphous aluminum-indium-zinc-oxide (a-AIZO) active layer were prepared by dip coating method. The dependence of properties of TFTs on the active-layer composition and structure was investigated. The results indicate that Al atoms acted as a carrier suppressor in IZO films. Meanwhile, it was found that the on/off current ratio (I on/off) of TFT was improved by embedding a high-resistivity AIZO layer between the low-resistivity AIZO layer and gate insulator. The improvement in I on/off was attributed to the decrease in off-state current of double-active-layer TFT due to an increase in the active-layer resistance and the contact resistance between active layer and source/drain electrode. Moreover, on-state current and threshold voltage (V th) can be mainly controlled through thickness and Al content of the low-resistivity AIZO layer. In addition, the saturation mobility (μ sat) of TFTs was improved with reducing the size of channel width or/and length, which was attributed to the decrease in trap states in the semiconductor and at the semiconductor/gate-insulator interface with the smaller channel width or/and shorter channel length. Thus, we can demonstrate excellent TFTs via the design of active-layer composition and structure by utilizing a low cost solution-processed method. The resulting TFT, operating in enhancement mode, has a high μ sat of 14.16 cm2 V-1 s-1, a small SS of 0.40 V/decade, a close-to-zero V th of 0.50 V, and I on/off of more than 105.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Gate-Variable Mid-Infrared Optical Transitions in a (Bi1-xSbx)2Te3 Topological Insulator.

PubMed

Whitney, William S; Brar, Victor W; Ou, Yunbo; Shao, Yinming; Davoyan, Artur R; Basov, D N; He, Ke; Xue, Qi-Kun; Atwater, Harry A

2017-01-11

We report mid-infrared spectroscopy measurements of ultrathin, electrostatically gated (Bi 1-x Sb x ) 2 Te 3 topological insulator films in which we observe several percent modulation of transmittance and reflectance as gating shifts the Fermi level. Infrared transmittance measurements of gated films were enabled by use of an epitaxial lift-off method for large-area transfer of topological insulator films from infrared-absorbing SrTiO 3 growth substrates to thermal oxidized silicon substrates. We combine these optical experiments with transport measurements and angle-resolved photoemission spectroscopy to identify the observed spectral modulation as a gate-driven transfer of spectral weight between both bulk and 2D topological surface channels and interband and intraband channels. We develop a model for the complex permittivity of gated (Bi 1-x Sb x ) 2 Te 3 and find a good match to our experimental data. These results open the path for layered topological insulator materials as a new candidate for tunable, ultrathin infrared optics and highlight the possibility of switching topological optoelectronic phenomena between bulk and spin-polarized surface regimes.

Effect of Be Modification on the Oxide Bifilms and Tensile Strength Reliability of Al-Si-Mg Alloys Containing Excess Fe

NASA Astrophysics Data System (ADS)

Asadian Nozari, M.; Taghiabadi, R.; Karimzadeh, M.; Ghoncheh, M. H.

2018-03-01

The effect of oxide bifilms and Be modification (0.2 wt pct) on the tensile strength reliability of the as-cast and T6 heat-treated Al-9Si-0.35Mg-1.5Fe alloy was investigated using Weibull analysis. For this purpose, the density of oxide bifilms in the molten alloy was intentionally increased by surface agitation. According to the results, Be modifies the β-Al5FeSi particles to the less harmful α-Fe compounds and substantially decreases the bifilm density in the castings leading to improved tensile properties and higher reliability. Moreover, the beneficial effect of Be was found to be more in the samples containing higher amounts of bifilms. For instance, in the heat-treated condition, Be increased the Weibull modulus of the non-agitated and surface-agitated samples by 4 and 94 pct, respectively. This improvement can be attributed to the strengthening effect of Be on the young surface oxides so that they resist more against rupture when melt is subjected to the surface turbulence. The reduced pressure test and fractography investigations also confirmed the reduction of bifilm density and bifilm-related defects in Be-modified samples.

Effect of Be Modification on the Oxide Bifilms and Tensile Strength Reliability of Al-Si-Mg Alloys Containing Excess Fe

NASA Astrophysics Data System (ADS)

Asadian Nozari, M.; Taghiabadi, R.; Karimzadeh, M.; Ghoncheh, M. H.

2018-06-01

The effect of oxide bifilms and Be modification (0.2 wt pct) on the tensile strength reliability of the as-cast and T6 heat-treated Al-9Si-0.35Mg-1.5Fe alloy was investigated using Weibull analysis. For this purpose, the density of oxide bifilms in the molten alloy was intentionally increased by surface agitation. According to the results, Be modifies the β-Al5FeSi particles to the less harmful α-Fe compounds and substantially decreases the bifilm density in the castings leading to improved tensile properties and higher reliability. Moreover, the beneficial effect of Be was found to be more in the samples containing higher amounts of bifilms. For instance, in the heat-treated condition, Be increased the Weibull modulus of the non-agitated and surface-agitated samples by 4 and 94 pct, respectively. This improvement can be attributed to the strengthening effect of Be on the young surface oxides so that they resist more against rupture when melt is subjected to the surface turbulence. The reduced pressure test and fractography investigations also confirmed the reduction of bifilm density and bifilm-related defects in Be-modified samples.

Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

NASA Astrophysics Data System (ADS)

Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

2016-04-01

Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

Efficient Z gates for quantum computing

NASA Astrophysics Data System (ADS)

McKay, David C.; Wood, Christopher J.; Sheldon, Sarah; Chow, Jerry M.; Gambetta, Jay M.

2017-08-01

For superconducting qubits, microwave pulses drive rotations around the Bloch sphere. The phase of these drives can be used to generate zero-duration arbitrary virtual Z gates, which, combined with two Xπ /2 gates, can generate any SU(2) gate. Here we show how to best utilize these virtual Z gates to both improve algorithms and correct pulse errors. We perform randomized benchmarking using a Clifford set of Hadamard and Z gates and show that the error per Clifford is reduced versus a set consisting of standard finite-duration X and Y gates. Z gates can correct unitary rotation errors for weakly anharmonic qubits as an alternative to pulse-shaping techniques such as derivative removal by adiabatic gate (DRAG). We investigate leakage and show that a combination of DRAG pulse shaping to minimize leakage and Z gates to correct rotation errors realizes a 13.3 ns Xπ /2 gate characterized by low error [1.95 (3 ) ×10-4] and low leakage [3.1 (6 ) ×10-6] . Ultimately leakage is limited by the finite temperature of the qubit, but this limit is two orders of magnitude smaller than pulse errors due to decoherence.

Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

PubMed

Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

2017-10-10

We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Optical XOR gate

DOEpatents

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Optical NOR gate

DOEpatents

Skogen, Erik J [Albuquerque, NM; Tauke-Pedretti, Anna [Albuquerque, NM

2011-09-06

An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

NASA Astrophysics Data System (ADS)

Liu, H. X.; Li, J.; Tan, R. R.

2018-01-01

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity

NASA Astrophysics Data System (ADS)

Chen, Lei; Kimura, Shinji

In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

HiRel: Hybrid Automated Reliability Predictor (HARP) integrated reliability tool system, (version 7.0). Volume 3: HARP Graphics Oriented (GO) input user's guide

NASA Technical Reports Server (NTRS)

Bavuso, Salvatore J.; Rothmann, Elizabeth; Mittal, Nitin; Koppen, Sandra Howell

1994-01-01

The Hybrid Automated Reliability Predictor (HARP) integrated Reliability (HiRel) tool system for reliability/availability prediction offers a toolbox of integrated reliability/availability programs that can be used to customize the user's application in a workstation or nonworkstation environment. HiRel consists of interactive graphical input/output programs and four reliability/availability modeling engines that provide analytical and simulative solutions to a wide host of highly reliable fault-tolerant system architectures and is also applicable to electronic systems in general. The tool system was designed at the outset to be compatible with most computing platforms and operating systems, and some programs have been beta tested within the aerospace community for over 8 years. This document is a user's guide for the HiRel graphical preprocessor Graphics Oriented (GO) program. GO is a graphical user interface for the HARP engine that enables the drawing of reliability/availability models on a monitor. A mouse is used to select fault tree gates or Markov graphical symbols from a menu for drawing.

Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al 2O 3 gate oxide

DOE PAGES

Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; ...

2016-07-26

The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al 2O 3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×10 13 to 1×10 15cm –2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metalmore » contacts, with increases of specific contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 10 13 cm –2 V –1 for the reference MOSHEMTs to 6.7 × 10 13 cm –2 V –1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm –1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

Quantum computing gates via optimal control

NASA Astrophysics Data System (ADS)

Atia, Yosi; Elias, Yuval; Mor, Tal; Weinstein, Yossi

2014-10-01

We demonstrate the use of optimal control to design two entropy-manipulating quantum gates which are more complex than the corresponding, commonly used, gates, such as CNOT and Toffoli (CCNOT): A two-qubit gate called polarization exchange (PE) and a three-qubit gate called polarization compression (COMP) were designed using GRAPE, an optimal control algorithm. Both gates were designed for a three-spin system. Our design provided efficient and robust nuclear magnetic resonance (NMR) radio frequency (RF) pulses for 13C2-trichloroethylene (TCE), our chosen three-spin system. We then experimentally applied these two quantum gates onto TCE at the NMR lab. Such design of these gates and others could be relevant for near-future applications of quantum computing devices.

Signatures of Mechanosensitive Gating.

PubMed

Morris, Richard G

2017-01-10

The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Aerosol jet printed p- and n-type electrolyte-gated transistors with a variety of electrode materials: exploring practical routes to printed electronics.

PubMed

Hong, Kihyon; Kim, Se Hyun; Mahajan, Ankit; Frisbie, C Daniel

2014-11-12

Printing electrically functional liquid inks is a promising approach for achieving low-cost, large-area, additive manufacturing of flexible electronic circuits. To print thin-film transistors, a basic building block of thin-film electronics, it is important to have several options for printable electrode materials that exhibit high conductivity, high stability, and low-cost. Here we report completely aerosol jet printed (AJP) p- and n-type electrolyte-gated transistors (EGTs) using a variety of different electrode materials including highly conductive metal nanoparticles (Ag), conducting polymers (polystyrenesulfonate doped poly(3,4-ethylendedioxythiophene, PEDOT:PSS), transparent conducting oxides (indium tin oxide), and carbon-based materials (reduced graphene oxide). Using these source-drain electrode materials and a PEDOT:PSS/ion gel gate stack, we demonstrated all-printed p- and n-type EGTs in combination with poly(3-hexythiophene) and ZnO semiconductors. All transistor components (including electrodes, semiconductors, and gate insulators) were printed by AJP. Both kinds of devices showed typical p- and n-type transistor characteristics, and exhibited both low-threshold voltages (<2 V) and high hole and electron mobilities. Our assessment suggests Ag electrodes may be the best option in terms of overall performance for both types of EGTs.

Dynamically correcting two-qubit gates against any systematic logical error

NASA Astrophysics Data System (ADS)

Calderon Vargas, Fernando Antonio

The reliability of quantum information processing depends on the ability to deal with noise and error in an efficient way. A significant source of error in many settings is coherent, systematic gate error. This work introduces a set of composite pulse sequences that generate maximally entangling gates and correct all systematic errors within the logical subspace to arbitrary order. These sequences are applica- ble for any two-qubit interaction Hamiltonian, and make no assumptions about the underlying noise mechanism except that it is constant on the timescale of the opera- tion. The prime use for our results will be in cases where one has limited knowledge of the underlying physical noise and control mechanisms, highly constrained control, or both. In particular, we apply these composite pulse sequences to the quantum system formed by two capacitively coupled singlet-triplet qubits, which is charac- terized by having constrained control and noise sources that are low frequency and of a non-Markovian nature.

Accurate reliability analysis method for quantum-dot cellular automata circuits

NASA Astrophysics Data System (ADS)

Cui, Huanqing; Cai, Li; Wang, Sen; Liu, Xiaoqiang; Yang, Xiaokuo

2015-10-01

Probabilistic transfer matrix (PTM) is a widely used model in the reliability research of circuits. However, PTM model cannot reflect the impact of input signals on reliability, so it does not completely conform to the mechanism of the novel field-coupled nanoelectronic device which is called quantum-dot cellular automata (QCA). It is difficult to get accurate results when PTM model is used to analyze the reliability of QCA circuits. To solve this problem, we present the fault tree models of QCA fundamental devices according to different input signals. After that, the binary decision diagram (BDD) is used to quantitatively investigate the reliability of two QCA XOR gates depending on the presented models. By employing the fault tree models, the impact of input signals on reliability can be identified clearly and the crucial components of a circuit can be found out precisely based on the importance values (IVs) of components. So this method is contributive to the construction of reliable QCA circuits.

Direct activation of the olfactory cyclic nucleotide-gated channel through modification of sulfhydryl groups by NO compounds.

PubMed

Broillet, M C; Firestein, S

1996-02-01

The activation of a cyclic nucleotide-gated channel is the final step in sensory transduction in olfaction. Normally, this channel is opened by the intracellular cyclic nucleotide second messenger cAMP or cGMP. However, in single channel recordings we found that donors of nitric oxide, a putative intercellular messenger, could directly activate the native olfactory neuron channel. Its action was independent of the presence of the normal ligand and did not involve the cyclic nucleotide binding site, suggesting an alternate site on the molecule that is critical in channel gating. The biochemical pathway appears to utilize nitric oxide in one of its alternate redox states, the nitrosonium ion, transnitrosylating a free sulfhydryl group belonging to a cysteine residue tentatively identified as being in the region linking the S6 transmembrane domain to the ligand binding domain.

Verification of Triple Modular Redundancy (TMR) Insertion for Reliable and Trusted Systems

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth A.

2016-01-01

We propose a method for TMR insertion verification that satisfies the process for reliable and trusted systems. If a system is expected to be protected using TMR, improper insertion can jeopardize the reliability and security of the system. Due to the complexity of the verification process, there are currently no available techniques that can provide complete and reliable confirmation of TMR insertion. This manuscript addresses the challenge of confirming that TMR has been inserted without corruption of functionality and with correct application of the expected TMR topology. The proposed verification method combines the usage of existing formal analysis tools with a novel search-detect-and-verify tool. Field programmable gate array (FPGA),Triple Modular Redundancy (TMR),Verification, Trust, Reliability,

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE PAGES

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; ...

2017-06-21

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). In this paper, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increasesmore » proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. Finally, these findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.« less

Experimental Study of the Detection Limit in Dual-Gate Biosensors Using Ultrathin Silicon Transistors.

PubMed

Wu, Ting; Alharbi, Abdullah; You, Kai-Dyi; Kisslinger, Kim; Stach, Eric A; Shahrjerdi, Davood

2017-07-25

Dual-gate field-effect biosensors (bioFETs) with asymmetric gate capacitances were shown to surpass the Nernst limit of 59 mV/pH. However, previous studies have conflicting findings on the effect of the capacitive amplification scheme on the sensor detection limit, which is inversely proportional to the signal-to-noise ratio (SNR). Here, we present a systematic experimental investigation of the SNR using ultrathin silicon transistors. Our sensors operate at low voltage and feature asymmetric front and back oxide capacitances with asymmetry factors of 1.4 and 2.3. We demonstrate that in the dual-gate configuration, the response of our bioFETs to the pH change increases proportional to the asymmetry factor and indeed exceeds the Nernst limit. Further, our results reveal that the noise amplitude also increases in proportion to the asymmetry factor. We establish that the commensurate increase of the noise amplitude originates from the intrinsic low-frequency characteristic of the sensor noise, dominated by number fluctuation. These findings suggest that this capacitive signal amplification scheme does not improve the intrinsic detection limit of the dual-gate biosensors.

49 CFR 234.223 - Gate arm.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm shall...

49 CFR 234.223 - Gate arm.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm shall...

49 CFR 234.223 - Gate arm.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm shall...

Coaxially gated in-wire thin-film transistors made by template assembly.

PubMed

Kovtyukhova, Nina I; Kelley, Brian K; Mallouk, Thomas E

2004-10-13

Nanowire field effect transistors were prepared by a wet chemical template replication method using anodic aluminum oxide membranes. The membrane pores were first lined with a thin SiO2 layer by the surface sol-gel method. Au, CdS (or CdSe), and Au wire segments were then sequentially electrodeposited within the pores, and the resulting nanowires were released by dissolution of the membrane. Electrofluidic alignment of these nanowires between source and drain leads and evaporation of gold over the central CdS (CdSe) stripe affords a "wrap-around gate" structure. At VDS = -2 V, the Au/CdS/Au devices had an ON/OFF current ratio of 103, a threshold voltage of 2.4 V, and a subthreshold slope of 2.2 V/decade. A 3-fold decrease in the subthreshold slope relative to that of planar nanocrystalline CdSe devices can be attributed to coaxial gating. The control of dimensions afforded by template synthesis should make it possible to reduce the gate dielectric thickness, channel length, and diameter of the semiconductor segment to sublithographic dimensions while retaining the simplicity of the wet chemical synthetic method.

Dual-Gated MoTe2/MoS2 van der Waals Heterojunction p-n Diode

NASA Astrophysics Data System (ADS)

Rai, Amritesh; Movva, Hema C. P.; Kang, Sangwoo; Larentis, Stefano; Roy, Anupam; Tutuc, Emanuel; Banerjee, Sanjay K.

2D materials are promising for future electronic and optoelectronic applications. In this regard, it is important to realize p-n diodes, the most fundamental building block of all modern semiconductor devices, based on these 2D materials. While it is challenging to achieve homojunction diodes in 2D semiconductors due to lack of reliable selective doping techniques, it is relatively easier to achieve diode-like behavior in van der Waals (vdW) heterostructures comprising different 2D semiconductors. Here, we demonstrate dual-gated vdW heterojunction p-n diodes based on p-type MoTe2 and n-type MoS2, with hBN as the top and bottom gate dielectric. The heterostructure stack is assembled using a polymer-based `dry-transfer' technique. Pt contact is used for hole injection in MoTe2, whereas Ag is used for electron injection in MoS2. The dual-gates allow for independent electrostatic tuning of the carriers in MoTe2 and MoS2. Room temperature interlayer current-voltage characteristics reveal a strong gate-tunable rectification behavior. At low temperatures, the diode turn-on voltage increases, whereas the reverse saturation current decreases, in accordance with conventional p-n diode behavior. Dual-Gated MoTe2/MoS2 van der Waals Heterojunction p-n Diode.

49 CFR 234.223 - Gate arm.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less than...

49 CFR 234.223 - Gate arm.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less than...

Hybrid automated reliability predictor integrated work station (HiREL)

NASA Technical Reports Server (NTRS)

Bavuso, Salvatore J.

1991-01-01

The Hybrid Automated Reliability Predictor (HARP) integrated reliability (HiREL) workstation tool system marks another step toward the goal of producing a totally integrated computer aided design (CAD) workstation design capability. Since a reliability engineer must generally graphically represent a reliability model before he can solve it, the use of a graphical input description language increases productivity and decreases the incidence of error. The captured image displayed on a cathode ray tube (CRT) screen serves as a documented copy of the model and provides the data for automatic input to the HARP reliability model solver. The introduction of dependency gates to a fault tree notation allows the modeling of very large fault tolerant system models using a concise and visually recognizable and familiar graphical language. In addition to aiding in the validation of the reliability model, the concise graphical representation presents company management, regulatory agencies, and company customers a means of expressing a complex model that is readily understandable. The graphical postprocessor computer program HARPO (HARP Output) makes it possible for reliability engineers to quickly analyze huge amounts of reliability/availability data to observe trends due to exploratory design changes.

Improvement in performance and reliability with CF4 plasma pretreatment on the buffer oxide layer for low-temperature polysilicon thin-film transistor

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Lin, Yi-Yan; Yang, Chun-Chieh

2012-03-01

This study applies CF4 plasma pretreatment to a buffer oxide layer to improve the performance of low-temperature polysilicon thin-film transistors (LTPS TFTs). Results show that the fluorine atoms piled up at the interface between the bulk channel and buffer oxide layer and accumulated in the bulk channel. The reduction of the trap states density by fluorine passivation can improve the electrical characteristics of the LTPS TFTs. It is found that the threshold voltage reduced from 4.32 to 3.03 V and the field-effect mobility increased from 29.71 to 45.65 cm2 V-1 S-1. In addition, the on current degradation and threshold voltage shift after stressing were significantly improved about 31% and 70%, respectively. We believe that the proposed CF4 plasma pretreatment on the buffer oxide layer can passivate the trap states and avoid the plasma induced damage on the polysilicon channel surface, resulting in the improvement in performance and reliability for LTPS-TFT mass production application on AMOLED displays with critical reliability requirement.

Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun

We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{submore » G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.« less

GATE Monte Carlo simulation in a cloud computing environment

NASA Astrophysics Data System (ADS)

Rowedder, Blake Austin

The GEANT4-based GATE is a unique and powerful Monte Carlo (MC) platform, which provides a single code library allowing the simulation of specific medical physics applications, e.g. PET, SPECT, CT, radiotherapy, and hadron therapy. However, this rigorous yet flexible platform is used only sparingly in the clinic due to its lengthy calculation time. By accessing the powerful computational resources of a cloud computing environment, GATE's runtime can be significantly reduced to clinically feasible levels without the sizable investment of a local high performance cluster. This study investigated a reliable and efficient execution of GATE MC simulations using a commercial cloud computing services. Amazon's Elastic Compute Cloud was used to launch several nodes equipped with GATE. Job data was initially broken up on the local computer, then uploaded to the worker nodes on the cloud. The results were automatically downloaded and aggregated on the local computer for display and analysis. Five simulations were repeated for every cluster size between 1 and 20 nodes. Ultimately, increasing cluster size resulted in a decrease in calculation time that could be expressed with an inverse power model. Comparing the benchmark results to the published values and error margins indicated that the simulation results were not affected by the cluster size and thus that integrity of a calculation is preserved in a cloud computing environment. The runtime of a 53 minute long simulation was decreased to 3.11 minutes when run on a 20-node cluster. The ability to improve the speed of simulation suggests that fast MC simulations are viable for imaging and radiotherapy applications. With high power computing continuing to lower in price and accessibility, implementing Monte Carlo techniques with cloud computing for clinical applications will continue to become more attractive.

SU-E-J-126: Respiratory Gating Quality Assurance: A Simple Method to Achieve Millisecond Temporal Resolution

DOE Office of Scientific and Technical Information (OSTI.GOV)

McCabe, B; Wiersma, R

Purpose: Low temporal latency between a gating on/off signal and a linac beam on/off during respiratory gating is critical for patient safety. Although, a measurement of temporal lag is recommended by AAPM Task Group 142 for commissioning and annual quality assurance, there currently exists no published method. Here we describe a simple, inexpensive, and reliable method to precisely measure gating lag at millisecond resolutions. Methods: A Varian Real-time Position Management™ (RPM) gating simulator with rotating disk was modified with a resistive flex sensor (Spectra Symbol) attached to the gating box platform. A photon diode was placed at machine isocenter. Outputmore » signals of the flex sensor and diode were monitored with a multichannel oscilloscope (Tektronix™ DPO3014). Qualitative inspection of the gating window/beam on synchronicity were made by setting the linac to beam on/off at end-expiration, and the oscilloscope's temporal window to 100 ms to visually examine if the on/off timing was within the recommended 100-ms tolerance. Quantitative measurements were made by saving the signal traces and analyzing in MatLab™. The on and off of the beam signal were located and compared to the expected gating window (e.g. 40% to 60%). Four gating cycles were measured and compared. Results: On a Varian TrueBeam™ STx linac with RPM gating software, the average difference in synchronicity at beam on and off for four cycles was 14 ms (3 to 30 ms) and 11 ms (2 to 32 ms), respectively. For a Varian Clinac™ 21EX the average difference at beam on and off was 127 ms (122 to 133 ms) and 46 ms (42 to 49 ms), respectively. The uncertainty in the synchrony difference was estimated at ±6 ms. Conclusion: This new gating QA method is easy to implement and allows for fast qualitative inspection and quantitative measurements for commissioning and TG-142 annual QA measurements.« less

High-performance field-effect transistors based on gadolinium doped indium oxide nanofibers and their application in logic gate

NASA Astrophysics Data System (ADS)

Wang, Chao; Meng, You; Guo, Zidong; Shin, Byoungchul; Liu, Guoxia; Shan, Fukai

2018-05-01

One-dimensional metal oxide nanofibers have been regarded as promising building blocks for large area low cost electronic devices. As one of the representative metal oxide semiconducting materials, In2O3 based materials have attracted much interest due to their excellent electrical and optical properties. However, most of the field-effect transistors (FETs) based on In2O3 nanofibers usually operate in a depletion mode, which lead to large power consumption and a complicated integrated circuit design. In this report, gadolinium (Gd) doped In2O3 (InGdO) nanofibers were fabricated by electrospinning and applied as channels in the FETs. By optimizing the doping concentration and the nanofiber density, the device performance could be precisely manipulated. It was found that the FETs based on InGdO nanofibers, with a Gd doping concentration of 3% and a nanofiber density of 2.9 μm-1, exhibited the best device performance, including a field-effect mobility (μFE) of 2.83 cm2/V s, an on/off current ratio of ˜4 × 108, a threshold voltage (VTH) of 5.8 V, and a subthreshold swing (SS) of 2.4 V/decade. By employing the high-k ZrOx thin films as the gate dielectrics in the FETs, the μFE, VTH and SS can be further improved to be 17.4 cm2/V s, 0.7 V and 160 mV/decade, respectively. Finally, an inverter based on the InGdO nanofibers/ZrOx FETs was constructed and a gain of ˜11 was achieved.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

NASA Astrophysics Data System (ADS)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

NASA Astrophysics Data System (ADS)

Wang, Yan-Rong; Yang, Hong; Xu, Hao; Wang, Xiao-Lei; Luo, Wei-Chun; Qi, Lu-Wei; Zhang, Shu-Xiang; Wang, Wen-Wu; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2015-11-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Pseudo-diode based on protonic/electronic hybrid oxide transistor

NASA Astrophysics Data System (ADS)

Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

2018-01-01

Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Zawawiand, Mohamad Adzhar Md; Missous, Mohamed

2014-03-01

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of -0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = -0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm-1 (from 500 mS mm-1), a high IDSmax of 400 mA mm-1 (from 330 mA mm-1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through VT Shift

NASA Astrophysics Data System (ADS)

Wang, Jih-Jong; Rezzak, Nadia; Dsilva, Durwyn; Xue, Fengliang; Samiee, Salim; Singaraju, Pavan; Jia, James; Nguyen, Victor; Hawley, Frank; Hamdy, Esmat

2016-08-01

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.

Reversible logic gates on Physarum Polycephalum

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schumann, Andrew

2015-03-10

In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.

Travels with Gates - August 2010

Science.gov Websites

combat floods that are affecting 14 million people. Story Biography Speeches Travels Photo Essays Gates Visits Navy Special Warefare Training More Photo Essays Gates Attends Graduation in San Diego Gates Photo Essays News Photos Week In Photos Videos DIMOC DOD/Military Seals DoD Flickr Secretary of Defense

Quantum gates with controlled adiabatic evolutions

NASA Astrophysics Data System (ADS)

Hen, Itay

2015-02-01

We introduce a class of quantum adiabatic evolutions that we claim may be interpreted as the equivalents of the unitary gates of the quantum gate model. We argue that these gates form a universal set and may therefore be used as building blocks in the construction of arbitrary "adiabatic circuits," analogously to the manner in which gates are used in the circuit model. One implication of the above construction is that arbitrary classical boolean circuits as well as gate model circuits may be directly translated to adiabatic algorithms with no additional resources or complexities. We show that while these adiabatic algorithms fail to exhibit certain aspects of the inherent fault tolerance of traditional quantum adiabatic algorithms, they may have certain other experimental advantages acting as quantum gates.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Stanford, Duke, Rice,... and Gates?

ERIC Educational Resources Information Center

Carey, Kevin

2009-01-01

This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

Hysteresis in voltage-gated channels.

PubMed

Villalba-Galea, Carlos A

2017-03-04

Ion channels constitute a superfamily of membrane proteins found in all living creatures. Their activity allows fast translocation of ions across the plasma membrane down the ion's transmembrane electrochemical gradient, resulting in a difference in electrical potential across the plasma membrane, known as the membrane potential. A group within this superfamily, namely voltage-gated channels, displays activity that is sensitive to the membrane potential. The activity of voltage-gated channels is controlled by the membrane potential, while the membrane potential is changed by these channels' activity. This interplay produces variations in the membrane potential that have evolved into electrical signals in many organisms. These signals are essential for numerous biological processes, including neuronal activity, insulin release, muscle contraction, fertilization and many others. In recent years, the activity of the voltage-gated channels has been observed not to follow a simple relationship with the membrane potential. Instead, it has been shown that the activity of voltage-gated channel displays hysteresis. In fact, a growing number of evidence have demonstrated that the voltage dependence of channel activity is dynamically modulated by activity itself. In spite of the great impact that this property can have on electrical signaling, hysteresis in voltage-gated channels is often overlooked. Addressing this issue, this review provides examples of voltage-gated ion channels displaying hysteretic behavior. Further, this review will discuss how Dynamic Voltage Dependence in voltage-gated channels can have a physiological role in electrical signaling. Furthermore, this review will elaborate on the current thoughts on the mechanism underlying hysteresis in voltage-gated channels.

Hysteresis in voltage-gated channels

PubMed Central

2017-01-01

ABSTRACT Ion channels constitute a superfamily of membrane proteins found in all living creatures. Their activity allows fast translocation of ions across the plasma membrane down the ion's transmembrane electrochemical gradient, resulting in a difference in electrical potential across the plasma membrane, known as the membrane potential. A group within this superfamily, namely voltage-gated channels, displays activity that is sensitive to the membrane potential. The activity of voltage-gated channels is controlled by the membrane potential, while the membrane potential is changed by these channels' activity. This interplay produces variations in the membrane potential that have evolved into electrical signals in many organisms. These signals are essential for numerous biological processes, including neuronal activity, insulin release, muscle contraction, fertilization and many others. In recent years, the activity of the voltage-gated channels has been observed not to follow a simple relationship with the membrane potential. Instead, it has been shown that the activity of voltage-gated channel displays hysteresis. In fact, a growing number of evidence have demonstrated that the voltage dependence of channel activity is dynamically modulated by activity itself. In spite of the great impact that this property can have on electrical signaling, hysteresis in voltage-gated channels is often overlooked. Addressing this issue, this review provides examples of voltage-gated ion channels displaying hysteretic behavior. Further, this review will discuss how Dynamic Voltage Dependence in voltage-gated channels can have a physiological role in electrical signaling. Furthermore, this review will elaborate on the current thoughts on the mechanism underlying hysteresis in voltage-gated channels. PMID:27689426

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

Determining oxide trapped charges in Al2O3 insulating films on recessed AlGaN/GaN heterostructures by gate capacitance transients measurements

NASA Astrophysics Data System (ADS)

Fiorenza, Patrick; Greco, Giuseppe; Schilirò, Emanuela; Iucolano, Ferdinando; Lo Nigro, Raffaella; Roccaforte, Fabrizio

2018-05-01

This letter presents time-dependent gate-capacitance transient measurements (C–t) to determine the oxide trapped charges (N ot) in Al2O3 films deposited on recessed AlGaN/GaN heterostructures. The C–t transients acquired at different temperatures under strong accumulation allowed to accurately monitor the gradual electron trapping, while hindering the re-emission by fast traps that may affect conventional C–V hysteresis measurements. Using this method, an increase of N ot from 2 to 6 × 1012 cm‑2 was estimated between 25 and 150 °C. The electron trapping is ruled by an Arrhenius dependence with an activation energy of 0.12 eV which was associated to points defects present in the Al2O3 films.

Benchmarking gate-based quantum computers

NASA Astrophysics Data System (ADS)

Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans

2017-11-01

With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.

Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Arai, Yukiko; Aoki, Hitoshi; Abe, Fumitaka; Todoroki, Shunichiro; Khatami, Ramin; Kazumi, Masaki; Totsuka, Takuya; Wang, Taifeng; Kobayashi, Haruo

2015-04-01

1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.

The human respiratory gate

NASA Technical Reports Server (NTRS)

Eckberg, Dwain L.

2003-01-01

Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

Unifying Gate Synthesis and Magic State Distillation.

PubMed

Campbell, Earl T; Howard, Mark

2017-02-10

The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

Automated Road Closure Gate

DOT National Transportation Integrated Search

2000-05-01

This report presents the procedures involved in the research, design, construction, and testing of an Automated Road Closure Gate. The current road closure gates used in South Dakota are often unsafe and difficult to operate. This report will assist ...

Site-Directed Spin Labeling Reveals Pentameric Ligand-Gated Ion Channel Gating Motions

PubMed Central