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Sample records for gate oxide reliability

  1. Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

    NASA Astrophysics Data System (ADS)

    Sung, Min Gyu; Lim, Kwan-Yong; Cho, Heung-Jae; Lee, Seung Ryong; Jang, Se-Aug; Kim, Yong Soo; Kim, Tae-Yoon; Yang, Hong-Seon; Ku, Ja-Chun; Kim, Jin Woong

    2007-11-01

    Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si-N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

  2. Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Sahu, P. K.; Singh, D.; Artola, L.; Mohapatra, S. K.

    2015-09-01

    A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon-germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

  3. Fundamental reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition

    SciTech Connect

    Yamada, Hiroshi

    2008-01-15

    The reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition (RIBD) with in situ pyrolytic-gas passivation (PGP) using N{sub 2}O and NF{sub 3} was investigated. RIBD uses low-energy-controlled reactive, ionized species and potentializes low-temperature film growth. Although the oxide films were grown at a low temperature of 150 deg. C, their fundamental indices of reliability, such as the time-dependent dielectric breakdown lifetime and interface state density, were almost equivalent to those of oxide films grown at 850 deg. C using a furnace. This is probably due to localized interfacial N and F atoms. The number density of interfacial N atoms was about seven times larger than that for the furnace-grown oxide films, and this is a key factor for improving the reliability through the compensation of residual inconsistent-state bonding sites.

  4. Reliability study of refractory gate gallium arsenide MESFETS

    NASA Technical Reports Server (NTRS)

    Yin, J. C. W.; Portnoy, W. M.

    1981-01-01

    Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

  5. Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Lo, Wen-Cheng; Wu, Shien-Yang; Chang, Sun-Jay; Chiang, Mu-Chi; Lin, Chih-Yung; Chao, Tien-Sheng; Chang, Chun-Yen

    2007-03-01

    In this study, we compared the effects of negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) on the core and input/output (I/O) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) fabricated using the different gate dielectrics of plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO). The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30 and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density.

  6. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  7. Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

    SciTech Connect

    Park, Hong Bae; Ju, Byongsun; Kang, Chang Yong; Park, Chanro; Park, Chang Seo; Lee, Byoung Hun; Kim, Tea Wan; Kim, Beom Seok; Choi, Rino

    2009-01-26

    The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor I{sub on}-I{sub off} characteristics and reduces negative-bias temperature instability.

  8. Gate-Tunable Conducting Oxide Metasurfaces.

    PubMed

    Huang, Yao-Wei; Lee, Ho Wai Howard; Sokhoyan, Ruzan; Pala, Ragip A; Thyagarajan, Krishnan; Han, Seunghoon; Tsai, Din Ping; Atwater, Harry A

    2016-09-14

    Metasurfaces composed of planar arrays of subwavelength artificial structures show promise for extraordinary light manipulation. They have yielded novel ultrathin optical components such as flat lenses, wave plates, holographic surfaces, and orbital angular momentum manipulation and detection over a broad range of the electromagnetic spectrum. However, the optical properties of metasurfaces developed to date do not allow for versatile tunability of reflected or transmitted wave amplitude and phase after their fabrication, thus limiting their use in a wide range of applications. Here, we experimentally demonstrate a gate-tunable metasurface that enables dynamic electrical control of the phase and amplitude of the plane wave reflected from the metasurface. Tunability arises from field-effect modulation of the complex refractive index of conducting oxide layers incorporated into metasurface antenna elements which are configured in reflectarray geometry. We measure a phase shift of 180° and ∼30% change in the reflectance by applying 2.5 V gate bias. Additionally, we demonstrate modulation at frequencies exceeding 10 MHz and electrical switching of ±1 order diffracted beams by electrical control over subgroups of metasurface elements, a basic requirement for electrically tunable beam-steering phased array metasurfaces. In principle, electrically gated phase and amplitude control allows for electrical addressability of individual metasurface elements and opens the path to applications in ultrathin optical components for imaging and sensing technologies, such as reconfigurable beam steering devices, dynamic holograms, tunable ultrathin lenses, nanoprojectors, and nanoscale spatial light modulators.

  9. Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology

    NASA Astrophysics Data System (ADS)

    Mohamad, B.; Leroux, C.; Rideau, D.; Haond, M.; Reimbold, G.; Ghibaudo, G.

    2017-02-01

    Effective work function and equivalent oxide thickness are fundamental parameters for technology optimization. In this work, a comprehensive study is done on a large set of FDSOI devices. The extraction of the gate stack parameters is carried out by fitting experimental CV characteristics to quantum simulation, based on self-consistent solution of one dimensional Poisson and Schrodinger equations. A reliable methodology for gate stack parameters is proposed and validated. This study identifies the process modules that impact directly the effective work function from those that only affect the device threshold voltage, due to the device architecture. Moreover, the relative impacts of various process modules on channel thickness and gate oxide thickness are evidenced.

  10. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    NASA Astrophysics Data System (ADS)

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  11. NO2 sensitive Au gate metal-oxide-semiconductor capacitors

    NASA Astrophysics Data System (ADS)

    Filippini, D.; Aragón, R.; Weimar, U.

    2001-08-01

    Au gate metal-oxide-semiconductor capacitors are sensitive to NO2 in air up to 200 ppm, depending on operating temperature (100 °C to 200 °C), gate thickness (50 to 900 nm), and morphology. In the absence of catalytic properties or lattice diffusivity, a model invoking molecular surface adsorption and grain boundary diffusion is proposed, which quantitatively describes the transient and steady state response of the devices. Sensitivity is given by the arrival of the diffusing species to the gate-dielectric interface, where capacitive coupling of the adsorbed molecules induces work function changes, which shift the flat band voltage positively, opposite that observed for H2 with Pd gates, consistently with an oxidizing, rather than reducing, character.

  12. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    NASA Astrophysics Data System (ADS)

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-01

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  13. Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET Using Defect-Free Gate Recess and Laser Annealing

    DTIC Science & Technology

    2012-07-18

    1 Annual Report for AOARD Grant FA2386-11-1-4077 “Device Performance and Reliability Improvements of AlGaN/GaN/ Si MOSFET Using Defect- Free Gate...transistors (MOS-HEMTs or MOS-HFETs) by incorporating a high-dielectric constant (high-k) oxide layer between the semiconductor and the gate metal.5,6 This...concentrations when compared to various other wet chemical treatments,11 with only HCl seen to produce a marginally more oxide free surface.12 Previous

  14. Effect of Electron Shading on Gate Oxide Degradation

    NASA Astrophysics Data System (ADS)

    Sakamori, Shigenori; Maruyama, Takahiro; Fujiwara, Nobuo; Miyatake, Hiroshi

    1998-04-01

    The oxide degradation due to edge and electron shading effects is investigated in a pulse-modulated plasma using metal-oxide-silicon (MOS) and metal-nitride-oxide-silicon (MNOS) capacitors. Reduction of edge defect, shading defect and electron shading charge build-up is strongly dependent on the on-time in pulse plasma. In particular, when the on-time is shorter than 50 µs, the coefficient of the shading defect becomes almost zero. The investigation of MNOS capacitors, which have the patterns with or without the substrate contact antenna, indicates that the electric stress direction applied to gate oxide changes as the device structure changes.

  15. Reliability study of retention and memory gate integrity in a 1K MNOS RAM

    SciTech Connect

    Nasby, R.D.; Miller, W.M.; White, R.L.

    1986-01-01

    The reliability of a 1K MNOS RAM with regards to retention and nitride gate integrity has been demonstrated. Over 400 devices were screened and life tested to demonstrate 0.999 reliability during device life. The device was a 1K MNOS memory used in a RAM application with an erase/write cycle of 32 microseconds and a life specification of 1E7 cycles.

  16. Transparent conducting oxide induced by liquid electrolyte gating

    PubMed Central

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

    2016-01-01

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ∼1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications. PMID:27647884

  17. Transparent conducting oxide induced by liquid electrolyte gating.

    PubMed

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-Dorin; Altendorf, Simone G; Utsumi, Yuki; Samant, Mahesh G; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S P

    2016-10-04

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3 Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ∼1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

  18. Transparent conducting oxide induced by liquid electrolyte gating

    NASA Astrophysics Data System (ADS)

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

    2016-10-01

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ˜1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

  19. Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

    NASA Astrophysics Data System (ADS)

    Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

    2016-12-01

    This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

  20. Reliability of P50 auditory sensory gating measures in infants during active sleep.

    PubMed

    Hunter, Sharon K; Corral, Nereida; Ponicsan, Heather; Ross, Randal G

    2008-01-08

    This study assessed reliability of auditory sensory gating in young infants from 1-4 months of age using a paired-click paradigm in which auditory 'clicks' were presented at an interstimulus interval of 500 ms. Evoked potential component P1 was measured during periods of active sleep on two different occasions. Amplitudes, latencies, and ratio of the evoked potentials to each of the auditory clicks were compared. Significant reliability was found in the response ratio, response latency to the first stimulus, and response amplitude to the second stimulus, with a trend toward significance for response latency to the second stimulus and response amplitude to the first stimulus. The results suggest that auditory sensory gating can be reliably measured during active sleep in young infants and might be a useful tool in the study of neurodevelopmental disorders.

  1. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    PubMed Central

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

  2. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    NASA Astrophysics Data System (ADS)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  3. Gate Annealing of Cycling Endurance and Interface States for Highly Reliable Flash Memory

    NASA Astrophysics Data System (ADS)

    Kim, Nam-Kyeong; Hong, Se-Hee; Shim, Sa-Yong; Park, Min-Hee; Hwang, Kyung-Pil; Lee, Min-Kyu; Lee, Ju-Yeab; Woo, Won-Sic; Noh, Keum-Hwan; Lee, Hee-Kee; Om, Jae-Chul; Lee, Seok-Kiu; Bae, Gi-Hyun

    2008-01-01

    We report on superior cycling endurance due to a low interface trap density, which accounts for the high gate annealing temperature in flash memory. The interface trap density was characterized using a charge pumping method (CPM). The cycling VTH shift in an erase state value of 1.35 V at 850 °C temperature of an annealing, as measured on a 90-nm-technology 1-Mbit cell array, selected randomly from 1 Gbit cells, drops to less than 0.9 V after annealing at 950 °C. These superior electrical properties resulted from a complete relaxation of silicon interface trap charges due to a plasma-induced attack during gate annealing at temperatures over 950 °C for a long time. Therefore, the key factor for highly reliable endurance with cycling is believed to be the interface trap control of the thermal annealing carried out after gate etching.

  4. Hole Trapping in Thermal Oxides Grown under Various Oxidation Conditions Using Avalanche Injection in Poly-Silicon Gate Structures

    DTIC Science & Technology

    2014-05-01

    Hole Trapping in Thermal Oxides Grown under Vaious Oxidation Conditions Using Avalanche Injection in Poly-Silicon Gate Structures Contractor... Avalanche In ection in Poly-Silicon Gate Structureac 12. PERSONAL AUTHOR(S) K.V. Anand, B.R. Cairns, R.J. Strain 13a. TYPE OF REPORT 13b. TIME...Trapping, Oxidation Conditions, Avalanche Injection, Poly-Silicon Gates, Oxide Traps 19. ABSTRACT (Continue on reverse If necenry W Identify by block

  5. Graphene-graphene oxide floating gate transistor memory.

    PubMed

    Jang, Sukjae; Hwang, Euyheon; Lee, Jung Heon; Park, Ho Seok; Cho, Jeong Ho

    2015-01-21

    A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles).

  6. Realization of reliable and flexible logic gates using noisy nonlinear circuits

    NASA Astrophysics Data System (ADS)

    Murali, K.; Rajamohamed, I.; Sinha, Sudeshna; Ditto, William L.; Bulsara, Adi R.

    2009-11-01

    It was shown recently [Murali et al., Phys. Rev. Lett. 102, 104101 (2009)] that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the interplay between the system noise and the nonlinearity (that characterizes the bistable dynamics). One can switch or "morph" the output into another logic operation (NAND/AND) whose probability displays analogous behavior; the switching is accomplished via a controlled symmetry-breaking dc input. Thus, the interplay of nonlinearity and noise yields flexible and reliable logic behavior, and the natural outcome is, effectively, a logic gate. This "logical stochastic resonance" is demonstrated here via a circuit implementation using a linear resistor, a linear capacitor and four CMOS-transistors with a battery to produce a cubiclike nonlinearity. This circuit is simple, robust, and capable of operating in very high frequency regimes; further, its ease of implementation with integrated circuits and nanoelectronic devices should prove very useful in the context of reliable logic gate implementation in the presence of circuit noise.

  7. Studies on the reliability of ni-gate aluminum gallium nitride / gallium nitride high electron mobility transistors using chemical deprocessing

    NASA Astrophysics Data System (ADS)

    Whiting, Patrick Guzek

    Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors are becoming the technology of choice for applications where hundreds of volts need to be applied in a circuit at frequencies in the hundreds of gigahertz, such as microwave communications. However, because these devices are very new, their reliability in the field is not well understood, partly because of the stochastic nature of the defects which form as a result of their operation. Many analytical techniques are not well suited to the analysis of these defects because they sample regions of the device which are either too small or too large for accurate observation. The use of chemical deprocessing in addition to surface-sensitive analysis techniques such as Scanning Electron Microscopy and Scanning Probe Microscopy can be utilized in the analysis of defect formation in devices formed with nickel gates. Hydrofluoric acid is used to etch the passivation nitride which covers the semiconducting layer of the transistor. A metal etch utilizing FeCN/KI is used to etch the ohmic and gate contacts of the device and a long exposure in various solvent solutions is used to remove organic contaminants, exposing the surface of the semiconducting layer for analysis. Deprocessing was used in conjunction with a variety of metrology techniques to analyze three different defects. One of these defects is a nanoscale crack which emanates from metal inclusions formed during alloying of the ohmic contacts of the device prior to use in the field, could impact the yield of production-level manufacturing of these devices. This defect also appears to grow, in some cases, during electrostatic stressing. Another defect, a native oxide at the surface of the semiconducting layer which appears to react in the presence of an electric field, has not been observed before during post-mortem analysis of degraded devices. It could play a major part in the degredation of the gate contact during high-field, off

  8. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    NASA Astrophysics Data System (ADS)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  9. On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

    NASA Astrophysics Data System (ADS)

    Habaš, Predrag; Selberherr, Siegfried

    1990-12-01

    A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C- V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C- V curves agree with the recently published data of implanted gate devices.

  10. Dual gate indium-gallium-zinc-oxide thin film transistor with an unisolated floating metal gate for threshold voltage modulation and mobility enhancement

    NASA Astrophysics Data System (ADS)

    Zan, Hsiao-Wen; Chen, Wei-Tsung; Yeh, Chung-Cheng; Hsueh, Hsiu-Wen; Tsai, Chuang-Chuang; Meng, Hsin-Fei

    2011-04-01

    In this study, we propose a floating dual gate (FDG) indium-gallium-zinc-oxide (IGZO) thin film transistor (TFT) with a floating metal back gate that is directly contact with IGZO without a dielectric layer. The floating back gate effect is investigated by changing the work function (ϕ) of the back gate. The FDG IGZO TFT exhibits an improved field-effect mobility (μ), unchanged subthreshold swing (SS), high on/off current ratio, and a tunable threshold voltage ranged (Vth) from -5.0 to +7.9 V without an additional back gate power supply.

  11. Oxide Thin-Film Transistors Fabricated Using Biodegradable Gate Dielectric Layer of Chicken Albumen

    NASA Astrophysics Data System (ADS)

    Jeon, Da-Bin; Bak, Jun-Yong; Yoon, Sung-Min

    2013-12-01

    An oxide thin-film transistor (TFT) using chicken albumen as gate dielectric on paper substrate was demonstrated. Chicken albumen, which was directly extracted from chicken egg white, was deposited as gate dielectric layer. An In-Ga-Zn-O was chosen as an active channel. The TFT feasibilities were successfully confirmed, in which channel mobility and subthreshold slope of the TFT were 6.48 cm2 V-1 s-1 and 1.28 V/s, respectively. This is the first report on the device configuration combining the biodegradable gate insulator and oxide semiconducting channel.

  12. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, S.

    2000-01-01

    In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

  13. Edge determination for polycrystalline silicon lines on gate oxide

    NASA Astrophysics Data System (ADS)

    Villarrubia, John S.; Vladar, Andras E.; Lowney, Jeremiah R.; Postek, Michael T., Jr.

    2001-08-01

    In a scanning electron microscope (SEM) top-down secondary electron image, areas within a few tens of nanometers of the line edges are characteristically brighter than the rest of the image. In general, the shape of the secondary electron signal within such edge regions depends upon the energy and spatial distribution of the electron beam and the sample composition, and it is sensitive to small variations in sample geometry. Assigning edge shape and position is done by finding a model sample that is calculated, on the basis of a mathematical model of the instrument-sample interaction, to produce an image equal to the one actually observed. Edge locations, and consequently line widths, are then assigned based upon this model sample. In previous years we have applied this strategy to lines with geometry constrained by preferential etching of single crystal silicon. With this study we test the procedure on polycrystalline silicon lines. Polycrystalline silicon lines fabricated according to usual industrial processes represent a commercially interesting albeit technically more challenging application of this method. With the sample geometry less constrained a priori, a larger set of possible sample geometries must be modeled and tested for a match to the observed line scan, and the possibility of encountering multiple acceptable matches is increased. For this study we have implemented a data analysis procedure that matches measured image line scans to a precomputed library of sample shapes and their corresponding line scans. Linewidth test patterns containing both isolated and dense lines separated form the underlying silicon substrate by a thin gate oxide have been fabricated. Line scans from test pattern images have been fitted to the library of modeled shapes.

  14. High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

    NASA Astrophysics Data System (ADS)

    Pyo, Ju-Young; Cho, Won-Ju

    2017-03-01

    In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH‑1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

  15. Gate oxide shorts in nMOS transistors: Electrical properties and lifetime prediction method

    SciTech Connect

    Dababneh, S.A.; Hawkins, C.F.; Soden, J.M.

    1994-09-01

    Degradation in nMOS transistors from gate oxide shorts is dependent upon oxide trapping and interface state generation. Three distinct damage mechanisms were identified, including generation of: (1) electron traps in the bulk oxide by the injected holes, N{sub ox,h}, (2) electron traps in the bulk oxide by the injected electrons, N{sub ox,e}, and (3) interface states, N{sub ss}. The three damage mechanisms are incorporated into a device lifetime prediction method.

  16. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    DOE PAGES

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a puremore » electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

  17. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films.

    PubMed

    Leng, X; Bollinger, A T; Božović, I

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  18. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    SciTech Connect

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  19. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    PubMed Central

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  20. Theoretical evaluation of zirconia and hafnia as gate oxides for si microelectronics.

    PubMed

    Fiorentini, Vincenzo; Gulleri, Gianluca

    2002-12-23

    Parameters determining the performance of the crystalline oxides zirconia (ZrO2) and hafnia (HfO2) as gate insulators in nanometric Si electronics are estimated via ab initio calculations of the energetics, dielectric properties, and band alignment of bulk and thin-film oxides on Si (001). With their large dielectric constants, stable and low-formation-energy interfaces, large valence offsets, and reasonable (though not optimal) conduction offsets (electron injection barriers), zirconia and hafnia appear to have considerable potential as gate oxides for Si electronics.

  1. Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Priyanka; Sahu, P. K.

    2016-01-01

    Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

  2. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications.

  3. A Novel Gate Electrode Structure for Reduction of Gate Resistance of Sub-0.1 µm RF/Mixed-Signal Metal Oxide Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Nagase, Hirokazu; Tanabe, Akira; Umeda, Kyoko; Watanabe, Takashi; Hayashi, Yoshihiro

    2009-04-01

    To reduce noise and enhance gain for scaled-down metal oxide semiconductor field-effect transistors (MOSFETs), a novel gate electrode structure “direct finger contact (DFC)” is proposed. The DFC structure reduces the gate electrode resistance by 40%. NF50 (noise figure when the input impedance is 50 Ω) is reduced by 4% with the gate length L = 48 nm, the gate width Wfinger =1 µm, and the number of finger N =20. This structure is suitable for low-noise sub-0.1 µm RF/mixed-signal system on chips (SoCs).

  4. Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

    NASA Astrophysics Data System (ADS)

    Miyoshi, Tomoyuki; Oshima, Takayuki; Noguchi, Junji

    2015-05-01

    High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

  5. ResearchGate is no longer reliable: leniency towards ghost journals may decrease its impact on the scientific community.

    PubMed

    Memon, Aamir Raoof

    2016-12-01

    ResearchGate has been regarded as one of the most attractive academic social networking site for scientific community. It has been trying to improve user-centered interfaces to gain more attractiveness to scientists around the world. Display of journal related scietometric measures (such as impact factor, 5-year impact, cited half-life, eigenfactor) is an important feature in ResearchGate. Open access publishing has added more to increased visibility of research work and easy access to information related to research. Moreover, scientific community has been much interested in promoting their work and exhibiting its impact to others through reliable scientometric measures. However, with the growing market of publications and improvements in the field of research, this community has been victimized by the cybercrime in the form of ghost journals, fake publishers and magical impact measures. Particularly, ResearchGate more recently, has been lenient in its policies against this dark side of academic writing. Therefore, this communication aims to discuss concerns associated with leniency in ResearchGate policies and its impact of scientific community.

  6. Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices

    NASA Astrophysics Data System (ADS)

    Vogel, Eric M.; Brown, George A.

    2003-09-01

    Experimental measurements and simulations are used to provide an overview of key issues with the electrical characterization of metal-oxide-semiconductor (MOS) devices with ultra-thin oxide and alternate gate dielectrics. Experimental issues associated with the most common electrical characterization method, capacitance-voltage (C-V), are first described. Issues associated with equivalent oxide thickness extraction and comparison, interface state measurement, extrinsic defects, and defect generation are then overviewed.

  7. SEMICONDUCTOR DEVICES Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

    NASA Astrophysics Data System (ADS)

    Yan, Han; Bin, Zhang; Koubao, Ding; Shifeng, Zhang; Chenggong, Han; Jiaxian, Hu; Dazhong, Zhu

    2010-12-01

    The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS (SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift (NDD) region implant on Ron degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced Ron degradation effectively, which is different from uniform gate oxide NLDMOS (UG-NLDMOS) transistors.

  8. Feasibility study of detection of dielectric breakdown of gate oxide film by using acoustic emission method

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Uesugi, Fumihiko

    2016-12-01

    An in situ detection method for the dielectric breakdown of oxide films for MOS gates has been required in the plasma etching process. In this feasibility study, a conventional MOSFET device is used and an acoustic emission (AE) method is employed for the detection of the dielectric breakdown of a gate oxide film. A thin type AE sensor is attached at the backside of an electrostatic chuck (ESC), and the dielectric breakdown in a MOSFET, which is set on the ESC, is detected. The results demonstrate that the thin type AE sensor can detect the dielectric breakdown with an energy on the order of µJ.

  9. Concurrent validity and test-retest reliability of a global positioning system (GPS) and timing gates to assess sprint performance variables.

    PubMed

    Waldron, Mark; Worsfold, Paul; Twist, Craig; Lamb, Kevin

    2011-12-01

    There has been no previous investigation of the concurrent validity and reliability of the current 5 Hz global positioning system (GPS) to assess sprinting speed or the reliability of integrated GPS-accelerometer technology. In the present study, we wished to determine: (1) the concurrent validity and reliability of a GPS and timing gates to measure sprinting speed or distance, and (2) the reliability of proper accelerations recorded via GPS-accelerometer integration. Nineteen elite youth rugby league players performed two over-ground sprints and were simultaneously assessed using GPS and timing gates. The GPS measurements systematically underestimated both distance and timing gate speed. The GPS measurements were reliable for all variables of distance and speed (coefficient of variation [CV] = 1.62% to 2.3%), particularly peak speed (95% limits of agreement [LOA] = 0.00 ± 0.8 km · h(-1); CV = 0.78%). Timing gates were more reliable (CV = 1% to 1.54%) than equivalent GPS measurements. Accelerometer measurements were least reliable (CV = 4.69% to 5.16%), particularly for the frequency of proper accelerations (95% LOA = 1.00 ± 5.43; CV = 14.12%). Timing gates and GPS were found to reliably assess speed and distance, although the validity of the GPS remains questionable. The error found in accelerometer measurements indicates the limits of this device for detecting changes in performance.

  10. Performance and reliability of HfAlO x-based interpoly dielectrics for floating-gate Flash memory

    NASA Astrophysics Data System (ADS)

    Govoreanu, B.; Wellekens, D.; Haspeslagh, L.; Brunco, D. P.; De Vos, J.; Aguado, D. Ruiz; Blomme, P.; van der Zanden, K.; Van Houdt, J.

    2008-04-01

    This paper discusses the performance and reliability of aggressively scaled HfAlO x-based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45 nm non-volatile memory technologies. It is shown that a less than 5 nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3 V at 150 °C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed.

  11. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  12. Positive Bias Instability of Bottom-Gate Zinc Oxide Thin-Film Transistors with a SiOx/SiNx-Stacked Gate Insulator

    NASA Astrophysics Data System (ADS)

    Furuta, Mamoru; Kamada, Yudai; Hiramatsu, Takahiro; Li, Chaoyang; Kimura, Mutsumi; Fujita, Shizuo; Hirao, Takashi

    2011-03-01

    The positive bias instabilities of the zinc oxide thin-film transistors (ZnO TFTs) with a SiOx/SiNx-stacked gate insulator have been investigated. The film quality of a gate insulator of SiOx, which forms an interface with the ZnO channel, was varied by changing the gas mixture ratio of SiH4/N2O/N2 during plasma-enhanced chemical vapor deposition. The positive bias stress endurance of ZnO TFT strongly depended on the deposition condition of the SiOx gate insulator. From the relaxations of the transfer curve shift after imposition of positive bias stress, transfer curves could not be recovered completely without any thermal annealing. A charge trapping in a gate insulator rather than that in bulk ZnO and its interface with a gate insulator is a dominant instability mechanism of ZnO TFTs under positive bias stress.

  13. Electrical control of Co/Ni magnetism adjacent to gate oxides with low oxygen ion mobility

    SciTech Connect

    Yan, Y. N.; Zhou, X. J.; Li, F.; Cui, B.; Wang, Y. Y.; Wang, G. Y.; Pan, F.; Song, C.

    2015-09-21

    We investigate the electrical manipulation of Co/Ni magnetization through a combination of ionic liquid and oxide gating, where HfO{sub 2} with a low O{sup 2−} ion mobility is employed. A limited oxidation-reduction process at the metal/HfO{sub 2} interface can be induced by large electric field, which can greatly affect the saturated magnetization and Curie temperature of Co/Ni bilayer. Besides the oxidation/reduction process, first-principles calculations show that the variation of d electrons is also responsible for the magnetization variation. Our work discloses the role of gate oxides with a relatively low O{sup 2−} ion mobility in electrical control of magnetism, and might pave the way for the magneto-ionic memory with low power consumption and high endurance performance.

  14. Neural network approach to fault diagnosis in CMOS opamps with gate oxide short faults

    NASA Astrophysics Data System (ADS)

    Yu, S.; Jervis, B. W.; Eckersall, K. R.; Bell, I. M.; Hall, A. G.; Taylor, G. E.

    1994-04-01

    Faults owing to gate oxide shorts in a CMOS opamp have been diagnosed in simulations using artificial neural networks to identify corresponding variations in supply current. Ramp and sinusoidal signals gave fault diagnostic accuracy of 67 and 83 percent, respectively. Using both test signals 100 percent diagnostic accuracy was achieved.

  15. Mechanically reliable surface oxides for high-temperature corrosion resistance

    SciTech Connect

    Natesan, K.; Veal, B.W.; Grimsditch, M.; Renusch, D.; Paulikas, A.P.

    1995-05-01

    Corrosion is widely recognized as being important, but an understanding of the underlying phenomena involves factors such as the chemistry and physics of early stages of oxidation, chemistry and bonding at the substrate/oxide interface, role of segregants on the strength of that bond, transport processes through scale, mechanisms of residual stress generation and relief, and fracture behavior at the oxide/substrate interface. Because of this complexity a multilaboratory program has been initiated under the auspices of the DOE Center of Excellence for the Synthesis and Processing of Advanced Materials, with strong interactions and cross-leveraging with DOE Fossil Energy and US industry. Objective is to systematically generate the knowledge required to establish a scientific basis for designing and synthesizing improved protective oxide scales/coatings (slow-growing, adherent, sound) on high-temperature materials without compromising the requisite properties of the bulk materials. The objectives of program work at Argonne are to (1) correlate actual corrosion performance with stresses, voids, segregants, interface roughness, initial stages of oxidation, and microstructures; (2) study such behavior in growing or as-grown films; and (3) define prescriptive design and synthesis routes to mechanically reliable surface oxides. Several techniques, such as Auger electron spectroscopy, X-ray diffraction, X-ray grazing incidence reflectance, grazing-angle X-ray fluorescence, optical fluorescence, and Raman spectroscopy, are used in the studies. Tne project has selected Fe-25 wt.% Cr-20 wt.% Ni and Fe-Cr-Al alloys, which are chromia- and alumina-formers respectively, for the studies. This paper presents some of the results on early stages of oxidation and on surface segregation of elements.

  16. Frequency-dependent reliability of spike propagation is function of axonal voltage-gated sodium channels in cerebellar Purkinje cells.

    PubMed

    Yang, Zhilai; Wang, Jin-Hui

    2013-12-01

    The spike propagation on nerve axons, like synaptic transmission, is essential to ensure neuronal communication. The secure propagation of sequential spikes toward axonal terminals has been challenged in the neurons with a high firing rate, such as cerebellar Purkinje cells. The shortfall of spike propagation makes some digital spikes disappearing at axonal terminals, such that the elucidation of the mechanisms underlying spike propagation reliability is crucial to find the strategy of preventing loss of neuronal codes. As the spike propagation failure is influenced by the membrane potentials, this process is likely caused by altering the functional status of voltage-gated sodium channels (VGSC). We examined this hypothesis in Purkinje cells by using pair-recordings at their somata and axonal blebs in cerebellar slices. The reliability of spike propagation was deteriorated by elevating spike frequency. The frequency-dependent reliability of spike propagation was attenuated by inactivating VGSCs and improved by removing their inactivation. Thus, the functional status of axonal VGSCs influences the reliability of spike propagation.

  17. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry.

    PubMed

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  18. Study of the relative performance of silicon and germanium nanoparticles embedded gate oxide in metal-oxide-semiconductor memory devices

    NASA Astrophysics Data System (ADS)

    Chakraborty, G.; Sengupta, A.; Requejo, F. G.; Sarkar, C. K.

    2011-03-01

    In the present work, we have investigated a comparative performance of the silicon (Si) and germanium (Ge) nanoparticles embedded SiO2 floating gate MOS memory devices. In such devices for low applied fields, the tunneling current is dominated by the direct tunneling mechanism, whereas for higher electric fields, the Fowler-Nordheim tunneling mechanism dominates. As the device dimensions get smaller, problem arises in the conventional MOS memory devices due to the leakage through the thin tunnel oxide. This leakage can be reduced via charge trapping by embedding nanoparticles in the gate dielectric of such devices. Here one objective is to prevent the leakage due to the direct tunneling mechanism and the other objective is to reduce the write voltage, by lowering the onset voltage of the Fowler-Nordheim tunneling mechanism. Our simulations for the current voltage characteristics covered both the low and the high applied field regions. Simulations showed that both the Si and the Ge nanoparticles embedded gate dielectrics offer reduction of the leakage current and a significant lowering of the writing or programming onset voltage, compared to the pure SiO2 gate dielectric. In terms of the comparative performance, the Germanium nanoparticles embedded gate dielectric showed better results compared to the silicon nanoparticles embedded one. The results of the simulations are discussed in the light of recent experimental results.

  19. Characterization of reliability of printed indium tin oxide thin films.

    PubMed

    Hong, Sung-Jei; Kim, Jong-Woong; Jung, Seung-Boo

    2013-11-01

    Recently, decreasing the amount of indium (In) element in the indium tin oxide (ITO) used for transparent conductive oxide (TCO) thin film has become necessary for cost reduction. One possible approach to this problem is using printed ITO thin film instead of sputtered. Previous studies showed potential for printed ITO thin films as the TCO layer. However, nothing has been reported on the reliability of printed ITO thin films. Therefore, in this study, the reliability of printed ITO thin films was characterized. ITO nanoparticle ink was fabricated and printed onto a glass substrate followed by heating at 400 degrees C. After measurement of the initial values of sheet resistance and optical transmittance of the printed ITO thin films, their reliabilities were characterized with an isothermal-isohumidity test for 500 hours at 85 degrees C and 85% RH, a thermal shock test for 1,000 cycles between 125 degrees C and -40 degrees C, and a high temperature storage test for 500 hours at 125 degrees C. The same properties were investigated after the tests. Printed ITO thin films showed stable properties despite extremely thermal and humid conditions. Sheet resistances of the printed ITO thin films changed slightly from 435 omega/square to 735 omega/square 507 omega/square and 442 omega/square after the tests, respectively. Optical transmittances of the printed ITO thin films were slightly changed from 84.74% to 81.86%, 88.03% and 88.26% after the tests, respectively. These test results suggest the stability of printed ITO thin film despite extreme environments.

  20. Tin oxide nanowire sensor with integrated temperature and gate control for multi-gas recognition

    NASA Astrophysics Data System (ADS)

    Dattoli, Eric N.; Davydov, Albert V.; Benkstein, Kurt D.

    2012-02-01

    The selectivity of a chemiresistive gas sensor comprising an array of single-crystalline tin oxide nanowires (NWs) is shown to be greatly enhanced by combined temperature and gate voltage modulation. This dual modulation was effected by a novel microsensor platform that consisted of a suspended nitride membrane embedded with independently addressable platinum heater and back-gate structures. The sensor was evaluated in a chemical vapor exposure test consisting of three volatile organic compound (VOC) analytes in an air background; VOC concentrations ranged from 20 μmol/mol to 80 μmol/mol. During the exposure test, the temperature and gating conditions of the NW sensor were modulated in order to induce variations in the sensor's analyte response behavior. By treating these temperature- and gate-dependent analyte response variations as an identifying ``fingerprint,'' analyte identification was achieved using a statistical pattern recognition procedure, linear discriminant analysis (LDA). Through optimization of this pattern recognition procedure, a VOC recognition rate of 98% was obtained. An analysis of the recognition results revealed that this high recognition rate could only be achieved through the combined modulation of temperature and gate bias as compared to either parameter alone. Overall, the highly accurate VOC analyte discrimination that was achieved here confirms the selectivity benefits provided by the utilized dual modulation approach and demonstrates the suitability of miniature nanowire sensors in real-world, multi-chemical detection problems.The selectivity of a chemiresistive gas sensor comprising an array of single-crystalline tin oxide nanowires (NWs) is shown to be greatly enhanced by combined temperature and gate voltage modulation. This dual modulation was effected by a novel microsensor platform that consisted of a suspended nitride membrane embedded with independently addressable platinum heater and back-gate structures. The sensor was

  1. Extended-Gate Metal Oxide Semiconductor Field Effect Transistor-Based Biosensor for Detection of Deoxynivalenol

    NASA Astrophysics Data System (ADS)

    Kwon, Insu; Lee, Hee-Ho; Choi, Jinhyeon; Shin, Jang-Kyoo; Seo, Sang-Ho; Choi, Sung-Wook; Chun, Hyang Sook

    2011-06-01

    In this work, we present an extended-gate metal oxide semiconductor field effect transistor (MOSFET)-based biosensor for the detection of deoxynivalenol using a null-balancing circuit. An extended-gate MOSFET-based biosensor was fabricated by a standard complementary metal oxide semiconductor (CMOS) process and its characteristics were measured. A null-balancing circuit was used to measure the output voltage of the sensor directly, instead of measuring the drain current of the sensor. Au was used as the gate metal, which has a chemical affinity with thiol, which leads to the immobilization of a self-assembled monolayer (SAM) of mercaptohexadecanoic acid (MHDA). The SAM was used to immobilize the anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti-deoxynivalenol antibody. The anti-deoxynivalenol antibody and deoxynivalenol were bound by their antigen-antibody reaction. The measurements were performed in phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl electrode was employed as a reference electrode. The bindings of a SAM, anti-deoxynivalenol antibody, and deoxynivalenol caused a variation in the output voltage of the extended-gate MOSFET-based biosensor. Surface plasmon resonance (SPR) measurement was performed to verify the interaction among the SAM, deoxynivalenol-antibody, and deoxynivalenol.

  2. Observation of Reliability of HfZrOX Gate Dielectric Devices with Different Zr/Hf Ratios

    NASA Astrophysics Data System (ADS)

    Liao, Jing-Chyi; Fang, Yean-Kuen; Tian Hou, Yong; Hsiung Tseng, Wei; Yang, Chih I.; Hsu, Peng Fu; Chao, Yuen Shun; Lin, Kang Cheng; Huang, Kuo Tai; Lee, Tzu Liang; Liang, Meng Sung

    2008-04-01

    The impact of the Zr/Hf ratio on the reliability of a HfZrOX gate dielectric has been investigated in detail. By a frequency-varied charge-pumping method, we found that the density of bulk traps is reduced with increasing Zr content. Also, a comparable Dit value observed by the rising/falling time-varied charge-pumping method suggests that Zr incorporation does not degrade the interface quality. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ˜25% mobility enhancement compared with that of HfO2 can be observed. However, the bulk trap density reduction reaches saturation at a higher Zr content. The improvement in positive-bias temperature instability (PBTI) was also demonstrated by both DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. Finally, a reduced gate-induced drain leakage current (GIDL) was also observed with increasing Zr content because of the reduction of trap-assisted tunneling in a high-k film.

  3. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  4. Control of trap density in channel layer for the higher stability of oxide thin film transistors under gate bias stress

    NASA Astrophysics Data System (ADS)

    Moon, Y. K.; Kim, W. S.; Kim, K. T.; Han, D. S.; Shin, S. Y.; Park, J. W.

    2011-12-01

    In this study, we investigated turn-on voltage (VON) stability of oxide-based TFTs under constant voltage stress for the TFTs including intrinsic ZnO, Hf-doped ZnO, and Hf-Zn-Sn-O channel layer. Also, to verify the effects of interfacial trap density on the TFTs stability, we employed SiNX and SiO2/SiNX as gate insulator, respectively. We found that the low trap density of the TFTs, including the interfacial trap density between channel and gate insulator, and oxide semiconductor bulk trap density is intimately related to excellent gate bias and temperature stability.

  5. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors

    NASA Astrophysics Data System (ADS)

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Wang, Di; Hahn, Horst; Dasgupta, Subho

    2016-10-01

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm2 V-1 s-1.

  6. Ionic liquid gating reveals trap-filled limit mobility in low temperature amorphous zinc oxide

    NASA Astrophysics Data System (ADS)

    Bubel, S.; Meyer, S.; Kunze, F.; Chabinyc, M. L.

    2013-10-01

    In low-temperature solution processed amorphous zinc oxide (a-ZnO) thin films, we show the thin film transistor (TFT) characteristics for the trap-filled limit (TFL), when the quasi Fermi energy exceeds the conduction band edge and all tail-states are filled. In order to apply gate fields that are high enough to reach the TFL, we use an ionic liquid tape gate. Performing capacitance voltage measurements to determine the accumulated charge during TFT operation, we find the TFL at biases higher than predicted by the electronic structure of crystalline ZnO. We conclude that the density of states in the conduction band of a-ZnO is higher than in its crystalline state. Furthermore, we find no indication of percolative transport in the conduction band but trap assisted transport in the tail-states of the band.

  7. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    PubMed Central

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-01-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems. PMID:27688042

  8. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    NASA Astrophysics Data System (ADS)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-09-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

  9. High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

    PubMed

    Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

    2015-07-01

    A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

  10. Al and Ge simultaneous oxidation using neutral beam post-oxidation for formation of gate stack structures

    SciTech Connect

    Ohno, Takeo; Nakayama, Daiki; Samukawa, Seiji

    2015-09-28

    To obtain a high-quality Germanium (Ge) metal–oxide–semiconductor structure, a Ge gate stacked structure was fabricated using neutral beam post-oxidation. After deposition of a 1-nm-thick Al metal film on a Ge substrate, simultaneous oxidation of Al and Ge was carried out at 300 °C, and a Ge oxide film with 29% GeO{sub 2} content was obtained by controlling the acceleration bias power of the neutral oxygen beam. In addition, the fabricated AlO{sub x}/GeO{sub x}/Ge structure achieved a low interface state density of less than 1 × 10{sup 11 }cm{sup −2 }eV{sup −1} near the midgap.

  11. Effects of negative gate-bias stress on the performance of solution-processed zinc-oxide transistors

    NASA Astrophysics Data System (ADS)

    Kim, Dongwook; Lee, Woo-Sub; Shin, Hyunji; Choi, Jong Sun; Zhang, Xue; Park, Jaehoon; Hwang, Jaeeun; Kim, Hongdoo; Bae, Jin-Hyuk

    2014-08-01

    We studied the effects of negative gate-bias stress on the electrical characteristics of top-contact zinc-oxide (ZnO) thin-film transistors (TFTs), which were fabricated by spin coating a ZnO solution onto a silicon-nitride gate dielectric layer. The negative gate-bias stress caused characteristic degradations in the on-state currents and the field-effect mobility of the fabricated ZnO TFTs. Additionally, a decrease in the off-state currents and a positive shift in the threshold voltage occurred with increasing stress time. These results indicate that the negative gate-bias stress caused an injection of electrons into the gate dielectric, thereby deteriorating the TFT's performance.

  12. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  13. All-amorphous-oxide transparent, flexible thin-film transistors. Efficacy of bilayer gate dielectrics.

    PubMed

    Liu, Jun; Buchholz, D Bruce; Hennek, Jonathan W; Chang, Robert P H; Facchetti, Antonio; Marks, Tobin J

    2010-09-01

    Optically transparent and mechanically flexible thin-film transistors (TF-TFTs) composed exclusively of amorphous metal oxide films are fabricated on plastic substrates by combining an amorphous Ta(2)O(5)/SiO(x) bilayer transparent oxide insulator (TOI) gate dielectric with an amorphous zinc-indium-tin oxide (a-ZITO) transparent oxide semiconductor (TOS) channel and a-ZITO transparent oxide conductor (TOC) electrodes. The bilayer gate dielectric is fabricated by the post-cross-linking of vapor-deposited hexachlorodisiloxane-derived films to form thin SiO(x) layers (v-SiO(x)) on amorphous Ta(2)O(5) (a-Ta(2)O(5)) films grown by ion-assisted deposition at room temperature. The a-Ta(2)O(5)/v-SiO(x) bilayer TOI dielectric integrates the large capacitance of the high dielectric constant a-Ta(2)O(5) layer with the excellent dielectric/semiconductor interfacial compatibility of the v-SiO(x) layer in a-ZITO TOS-based TF-TFTs. These all-amorphous-oxide TF-TFTs, having a channel length and width of 100 and 2000 microm, respectively, perform far better than a-Ta(2)O(5)-only devices and exhibit saturation-regime field-effect mobilities of approximately 20 cm(2)/V x s, on-currents >10(-4) A, and current on-off ratios >10(5). These TFTs operate at low voltages (approximately 4.0 V) and exhibit good visible-region optical transparency and excellent mechanical flexibility.

  14. Dose dependence of interface traps in gate oxides at high levels of total dose

    SciTech Connect

    Baze, M.P.; Plaag, R.E.; Johnston, A.H. )

    1989-12-01

    Interface traps in gate oxides were found to saturate at high total dose levels. An empirical model was developed to describe the nonlinear dependence and saturation characteristics. Three different processes were studied including CMOS/SOS, hardened bulk CMOS and unhardened bulk CMOS using several combinations of dose rate and bias. An evaluation was made of the model's accuracy in extrapolating the effect of interface traps to very high doses. A possible application of the model in characterizing devices for space environments is discussed along with implications for a physical model of radiation induced interface trap buildup.

  15. Hydrogen annealing of silicon gate-nitride-oxide-silicon nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Topich, James A.; Turi, Raymond A.

    1982-10-01

    A hydrogen annealing study of silicon gate-nitride-oxide-silicon (SNOS) nonvolatile memory devices showed that the important parameter in determining the optimum hydrogen annealing temperature for maximum charge retention is the previous thermal history of the memory devices. If a memory device's charge retention is not degraded by high-temperature processing, then the hydrogen anneal should be at the silicon nitride deposition temperature. If a device is degraded by high-temperature processing, then the hydrogen anneal should be at the degradation temperature.

  16. Study of gate oxide traps in HfO2/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

    NASA Astrophysics Data System (ADS)

    Sun, X.; Saadat, O. I.; Chang-Liao, K. S.; Palacios, T.; Cui, S.; Ma, T. P.

    2013-03-01

    We introduce an ac-transconductance method to profile the gate oxide traps in a HfO2 gated AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors (MOS-HEMTs) that can exchange carriers with metal gates, which in turn causes changes in analog and pulsed channel currents. The method extracts energy and spacial distributions of the oxide and interface traps under the gate from the frequency dependence of ac transconductance. We demonstrate the method using MOS-HEMTs with gate oxides that were annealed at different temperatures.

  17. High-k perovskite gate oxide BaHfO3

    NASA Astrophysics Data System (ADS)

    Kim, Young Mo; Park, Chulkwon; Ha, Taewoo; Kim, Useong; Kim, Namwook; Shin, Juyeon; Kim, Youjung; Yu, Jaejun; Kim, Jae Hoon; Char, Kookrin

    2017-01-01

    We have investigated epitaxial BaHfO3 as a high-k perovskite dielectric. From x-ray diffraction measurement, we confirmed the epitaxial growth of BaHfO3 on BaSnO3 and MgO. We measured optical and dielectric properties of the BaHfO3 gate insulator; the optical bandgap, the dielectric constant, and the breakdown field. Furthermore, we fabricated a perovskite heterostructure field effect transistor using epitaxial BaHfO3 as a gate insulator and La-doped BaSnO3 as a channel layer on SrTiO3 substrate. To reduce the threading dislocations and enhance the electrical properties of the channel, an undoped BaSnO3 buffer layer was grown on SrTiO3 substrates before the channel layer deposition. The device exhibited a field effect mobility value of 52.7 cm2 V-1 s-1, a Ion/Ioff ratio higher than 107, and a subthreshold swing value of 0.80 V dec-1. We compare the device performances with those of other field effect transistors based on BaSnO3 channels and different gate oxides.

  18. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    NASA Astrophysics Data System (ADS)

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-01

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

  19. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  20. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    PubMed Central

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  1. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    NASA Astrophysics Data System (ADS)

    Park, Sungjun; Lee, Seyeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  2. Dual Metal/High-k Gate-Last Complementary Metal-Oxide-Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

    NASA Astrophysics Data System (ADS)

    Kikuchi, Yoshiaki; Wakabayashi, Hitoshi; Tsukamoto, Masanori; Nagashima, Naoki

    2011-08-01

    For the first time, dual metal/high-k gate-last complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal-oxide-semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal-oxide-semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

  3. AlGaN/GaN metal oxide semiconductor heterostructure field-effect transistors with 4 nm thick Al2O3 gate oxide

    NASA Astrophysics Data System (ADS)

    Gregušová, D.; Stoklas, R.; Čičo, K.; Lalinský, T.; Kordoš, P.

    2007-08-01

    AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with 4 nm thick Al2O3 gate oxide were prepared and their performance was compared with that of AlGaN/GaN HFETs. The MOSHFETs yielded ~40% increase of the saturation drain current compared with the HFETs, which is larger than expected due to the gate oxide passivation. Despite a larger gate-channel separation in the MOSHFETs, a higher extrinsic transconductance than that of the HFETs was measured. The drift mobility of the MOSHFETs, evaluated on large-gate FET structures, was significantly higher than that of the HFETs. The zero-bias mobility for MOSHFETs and HFETs was 1950 cm2 V-1 s-1 and 1630 cm2 V-1 s-1, respectively. These features indicate an increase of the drift velocity and/or a decrease of the parasitic series resistance in the MOSHFETs. The current collapse, evaluated from pulsed I-V measurements, was highly suppressed in the MOSHFETs with 4 nm thick Al2O3 gate oxide. This result, together with the suppressed frequency dispersion of the capacitance, indicates that the density of traps in the Al2O3/AlGaN/GaN MOSHFETs was significantly reduced.

  4. Gate Metal-Induced Diffusion and Interface Reactions in Hf Oxide Films on Si

    SciTech Connect

    Goncharova, Lyudmila V.; Dalponte, Mateus; Celik, Ozgur; Garfunkel, Eric; Gustafsson, Torgny; Lysaght, Pat S.; Bersuker, Gennadi I.

    2007-09-26

    When metal electrodes are deposited on a high-{kappa} metal-oxide/SiO{sub 2}/Si stack, chemical interactions may occur both at the metal/high-{kappa} and the high-{kappa}/Si interfaces, causing changes in electrical performance. We report here results from medium energy ion scattering (MEIS) and x-ray photoelectron (XPS) studies of oxygen and silicon transport and interfacial layer reactions in multilayer gate stacks. Our results show that Ti deposition on HfO{sub 2}/SiO{sub 2}/Si stacks causes reduction of the SiO{sub 2} interfacial layer and (to a lesser extent) the HfO{sub 2} layer. Silicon atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for titanium-silicon interdiffusion through the high-{kappa} film in the presence of a titanium gate in crystalline HfO{sub 2} films is also reported.

  5. Multiplexed aptasensors and amplified DNA sensors using functionalized graphene oxide: application for logic gate operations.

    PubMed

    Liu, Xiaoqing; Aizen, Ruth; Freeman, Ronit; Yehezkeli, Omer; Willner, Itamar

    2012-04-24

    Graphene oxide (GO) is implemented as a functional matrix for developing fluorescent sensors for the amplified multiplexed detection of DNA, aptamer-substrate complexes, and for the integration of predesigned DNA constructs that activate logic gate operations. Fluorophore-labeled DNA strands acting as probes for two different DNA targets are adsorbed onto GO, leading to the quenching of the luminescence of the fluorophores. Desorption of the probes from the GO, through hybridization with the target DNAs, leads to the fluorescence of the respective label. By coupling exonuclease III, Exo III, to the system, the recycling of the target DNAs is demonstrated, and this leads to the amplified detection of the DNA targets (detection limit 5 × 10(-12) M). Similarly, adsorption of fluorophore-functionalized aptamers against thrombin or ATP onto the GO leads to the desorption of the aptamer-substrate complexes from GO and to the triggering of the luminescence corresponding to the respective fluorophore, thus, allowing the multiplexed analysis of the aptamer-substrate complexes. By designing functional fluorophore-labeled DNA constructs and their interaction with GO, in the presence (or absence) of nucleic acids, or two different substrates for aptamers, as inputs, the activation of the "OR" and "AND" logic gates is demonstrated.

  6. Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

    NASA Astrophysics Data System (ADS)

    Vasu, K. S.; Chakraborty, Biswanath; Sampath, S.; Sood, A. K.

    2010-08-01

    We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 μm×5 μm shows a single 2D band at 2687 cm -1, characteristic of single-layer graphene. The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 μm using ac dielectrophoresis, show ohmic behavior with a resistance of ˜37 kΩ. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R˜-9.5×10-4/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO+LiClO 4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of ˜6×1012/cm and carrier mobility of ˜50 cm 2/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model.

  7. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  8. Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors

    NASA Astrophysics Data System (ADS)

    Park, Jaechul; Song, Ihun; Kim, Sunil; Kim, Sangwook; Kim, Changjung; Lee, Jaecheol; Lee, Hyungik; Lee, Eunha; Yin, Huaxiang; Kim, Kyoung-Kok; Kwon, Kee-Won; Park, Youngsoo

    2008-08-01

    We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/drain region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/drain region was divided into In-rich and In-deficient regions. The a-GIZO TFT also had a constant sheet resistance of 1 kΩ/◻ for a film thickness of over 40 nm. The interface between the source/drain Mo metal and the Ar plasma-treated a-GIZO indicated a good Ohmic contact and a contact resistivity of 50 μΩ cm2.

  9. Energy-dependent relaxation time in quaternary amorphous oxide semiconductors probed by gated Hall effect measurements

    NASA Astrophysics Data System (ADS)

    Socratous, Josephine; Watanabe, Shun; Banger, Kulbinder K.; Warwick, Christopher N.; Branquinho, Rita; Barquinha, Pedro; Martins, Rodrigo; Fortunato, Elvira; Sirringhaus, Henning

    2017-01-01

    Despite the success of exploiting the properties of amorphous oxide semiconductors for device applications, the charge transport in these materials is still not clearly understood. The observation of a definite Hall voltage suggests that electron transport in the conduction band is free-electron-like. However, the temperature dependence of the Hall and field-effect mobilities cannot be explained using a simple bandlike model. Here, we perform gated Hall effect measurements in field-effect transistors, which allow us to make two independent estimates of the charge carrier concentration and determine the Hall factor providing information on the energy dependence of the relaxation time. We demonstrate that the Hall factor in a range of sputtered and solution-processed quaternary amorphous oxides, such as a-InGaZnO, is close to two, while in ternary oxides, such as InZnO, it is near unity. This suggests that quaternary elements like Ga act as strong ionized impurity scattering centers in these materials.

  10. Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ho, Szu-Han; Chang, Ting-Chang; Wu, Chi-Wei; Lo, Wen-Hung; Chen, Ching-En; Tsai, Jyun-Yu; Liu, Guan-Ru; Chen, Hua-Mao; Lu, Ying-Shin; Wang, Bin-Wei; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Sze, Simon M.

    2013-01-01

    This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ɛhigh-k = Q + Esio2ɛsio2.

  11. Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ho, Szu-Han; Chang, Ting-Chang; Wu, Chi-Wei; Lo, Wen-Hung; Chen, Ching-En; Tsai, Jyun-Yu; Luo, Hung-Ping; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Sze, Simon M.

    2012-07-01

    This letter investigates a hump in gate current after dynamic negative bias stress (NBS) in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. By measuring gate current under initial through body floating and source/drain floating, it shows that hole current flows from source/drain. The fitting of gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after dynamic NBS, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ɛhigh-k = Q + Esio2ɛsio2.

  12. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    NASA Astrophysics Data System (ADS)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-01

    We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from -15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e-/2e-), peroxide (O22-) formation or conversion of ionized interstitial (Oi2-) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows -2.7 V shift at VTG = -15 V, which gradually decreases to -0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22-/Oi) and/or hole trapping in the a-IGZO /interfaces.

  13. Unified model for physics-based modelling of a new device architecture: triple material gate oxide stack epitaxial channel profile (TRIMGAS Epi) MOSFET

    NASA Astrophysics Data System (ADS)

    Goel, Kirti; Saxena, Manoj; Gupta, Mridula; Gupta, R. S.

    2007-04-01

    A new device architecture triple material gate oxide stack (TRIMGAS) epitaxial channel (Epi) MOSFET for reduced short channel effects (SCEs) at short gate lengths is proposed. The structure has a gate electrode consisting of three different materials, an oxide stack having high-K material on top of an SiO2 layer and an epitaxial channel profile. A two-dimensional analytical threshold voltage and drain current model has been presented. An analysis of subthreshold slope and I-V characteristics has been done for the first time including all regions of operation. The model proposed is capable of modelling various other MOSFET structures: (a) dual material gate stack (DUMGAS), (b) single material gate stack (SIMGAS), (c) straddle-gate/EJ/side-gate MOSFET oxide stack, (d) dual/hetero material gate (DMG/HMG), (e) single material gate (SMG) and (f) triple material gate (TMG), all with and without an epitaxial channel profile. A 2D device simulator, ATLAS, is used over a wide range of parameters and bias conditions to validate the analytical results.

  14. Time-delay-and-integration charge-coupled devices using tin oxide gate technology. [for Landsat MSS

    NASA Technical Reports Server (NTRS)

    Thompson, L. L.; Mccann, D. H.; Tracy, R. A.; Kub, F. J.; White, M. H.

    1978-01-01

    Doped tin oxide gates are used in a time-delay-and-integration (TDI) CCD scheme in an effort to develop a stable transparent gate technology. Design characteristics of the system are discussed, including 2 sections of 10 by 9 integration stages, four-phase buried channel construction, and 10 input parallel-in/serial-out output shift register at a video rate of 1.25 MHz. A quantum efficiency of 65% with smooth spectral response is attained by front surface imaging. The suitability of the system for the Landsat program is discussed in terms of TDI-CCD operating parameters.

  15. Electronic States of Hafnium and Vanadium oxide in Silicon Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Tang, Fu; Liu, Xin; Yang, Jialing; Nemanich, Robert

    2010-03-01

    Vanadium oxide (VO2) is a narrow band gap material with a metal-insulator transition (MIT) at less than 100C. Hafnium oxide (HfO2) is currently the preferred high-k material for gate dielectrics. To utilize VO2 in a charge storage device, it is necessary to understand the band relationships between VO2, HfO2, and Si substrate. In this study, a 2nm thick VO2 layer is embedded in a dielectric stack structure between an oxidized n-type Si(100) surface and a 2nm HfO2 layer. The in situ experiments are carried out in an UHV multi-chamber system. After each growth step, the surface is characterized using XPS and UPS. After the initial plasma cleaning and oxidation treatment the Si substrate displayed essentially flat bands at the surface. After deposition of the VO2 layer, the Si 2p peak shifted to lower binding energy, and the Si 2p associated with the SiO2 layer also was shifted, indicating an internal field in the SiO2. The VO2 valence band maximum (VBM) was identified at 0.6 eV below the Fermi level (EF). This ultra thin VO2 exhibits the metal-insulator transition at a temperature higher than thicker films. As a comparison, a 100nm thick film of VO2 on Si showed a MIT at 60C. After the HfO2 deposition, the Si 2p substrate feature returned to the initial value indicating a return to flat band conditions. The UPS indicated the VBM of HfO2 at 4.0 eV below EF. This work is supported by the NSF (DMR-0805353).

  16. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

    NASA Astrophysics Data System (ADS)

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-09-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

  17. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

    PubMed Central

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-01-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

  18. Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

    DTIC Science & Technology

    1993-04-01

    Electrochem. Soc. vol.136, p. 14 7 4 (1989). 98. Ryden K. H., H. Norstrom, C. Nender and S. Berg, "Oxide Breakdown due to Charge Accumulation during Plasma...breakdown due to charge accumulation during plasma etching Author(s): Ryden , K.-H.; Norstrom, H.; Nender, C.; Berg, S. Author Affiliation: Inst. of...of charge accumulation during plasma etching Author(s): Ryden , K.-H.; Norstrom, H.; Nender, C.; Berg, S. Author Affiliation: Inst. of Microwave

  19. Investigation of the gate oxide leakage current of low temperature formed hafnium oxide films

    NASA Astrophysics Data System (ADS)

    Verrelli, E.; Tsoukalas, D.

    2013-03-01

    In this work, low temperature physically deposited hafnium oxide films are investigated in terms of their electrical properties through measurements and analysis of leakage currents in order to understand the defect's behavior in this dielectric material. Two extreme conditions will be presented and discussed: the first one concerns the use of a nearly trap-free hafnium oxide layer, while the second one concerns the use of a hafnium oxide film with a very large amount of electrically active traps. Particular emphasis is given to the detection and comparison of the shallow and deep traps that are responsible for the room temperature leakage of these films. It is shown that by modifying the amount of traps in the hafnium oxide layer, achieved by changing the deposition conditions, the trap's energy location is heavily influenced. The nearly trap-free sample exhibits Ohmic conduction at low fields (with activation energies in the range 16-33 meV for low temperatures and 0.13-0.14 eV for higher than ambient temperatures), Poole-Frenkel conduction at high fields (trap depth in the range 0.23-0.38 eV), while at low temperatures and high fields, the Fowler-Nordheim tunneling is identified (estimated barrier height of 1.9 eV). The charge-trap sample on the other hand exhibits Ohmic conduction at low fields (activation energies in the range 0.26-0.32 eV for higher than ambient temperatures), space charge limited current conduction at intermediate fields (exponent n = 3), while at high fields the Poole-Frenkel conduction appears (trap depth in the range 1.63-1.70 eV).

  20. Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

    NASA Astrophysics Data System (ADS)

    Li, Cong; Zhuang, Yi-Qi; Zhang, Li; Jin, Gang

    2014-01-01

    Based on the quasi-two-dimensional (2D) solution of Poisson's equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate (JLDMCSG) metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG (JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll-off of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional (3D) numerical device simulator ISE.

  1. Solution-Processed Rare-Earth Oxide Thin Films for Alternative Gate Dielectric Application.

    PubMed

    Zhuang, Jiaqing; Sun, Qi-Jun; Zhou, Ye; Han, Su-Ting; Zhou, Li; Yan, Yan; Peng, Haiyan; Venkatesh, Shishir; Wu, Wei; Li, Robert K Y; Roy, V A L

    2016-11-16

    Previous investigations on rare-earth oxides (REOs) reveal their high possibility as dielectric films in electronic devices, while complicated physical methods impede their developments and applications. Herein, we report a facile route to fabricate 16 REOs thin insulating films through a general solution process and their applications in low-voltage thin-film transistors as dielectrics. The formation and properties of REOs thin films are analyzed by atomic force microscopy (AFM), X-ray diffraction (XRD), spectroscopic ellipsometry, water contact angle measurement, X-ray photoemission spectroscopy (XPS), and electrical characterizations, respectively. Ultrasmooth, amorphous, and hydrophilic REO films with thickness around 10 nm have been obtained through a combined spin-coating and postannealing method. The compositional analysis results reveal the formation of RE hydrocarbonates on the surface and silicates at the interface of REOs films annealed on Si substrate. The dielectric properties of REO films are investigated by characterizing capacitors with a Si/Ln2O3/Au (Ln = La, Gd, and Er) structure. The observed low leakage current densities and large areal capacitances indicate these REO films can be employed as alternative gate dielectrics in transistors. Thus, we have successfully fabricated a series of low-voltage organic thin-film transistors based on such sol-gel derived REO films to demonstrate their application in electronics. The optimization of REOs dielectrics in transistors through further surface modification has also been studied. The current study provides a simple solution process approach to fabricate varieties of REOs insulating films, and the results reveal their promising applications as alternative gate dielectrics in thin-film transistors.

  2. Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2017-01-01

    Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low-k). To supplement low-k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high-k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high-k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3.

  3. New Gate Dielectric Oxides for GaAs and Other Semiconductors*

    NASA Astrophysics Data System (ADS)

    Hong, M.

    2000-03-01

    It is well known that electrons move much faster in GaAs than in Si, and this attribute makes the GaAs-based metal oxide semiconductor field effect transistors (MOSFETs) very attractive for high-frequency, high-speed circuits applications. However, identifying a proper insulating oxide for GaAs has been a problem puzzling researchers over 35 years. Recently we discovered that the use of a mixed oxide dielectric Ga_2O_3(Gd_2O_3)^1 formed inversion and accumulation channels on GaAs surfaces, with a low interfacial density of states (D_it) of mid-10^10 cm-2eV-1. Subsequently, we have demonstrated the p- and n- inversion channel MOSFETs^2 and CMOS circuits^3. All oxides in this work were prepared by ultrahigh vacuum deposition from e-beam sources. The initial growth ( 10 Åof Ga_2O_3(Gd_2O_3) film on GaAs takes place from nucleating a thin epitaxial layer of pure Gd_2O_3. In fact, mono-domain, single crystalline Gd_2O3 films (ɛ =12) can be grown on GaAs (100) surface in the (110) Mn_2O3 structure, and that show leakage currents as low as 10-4 A/cm^2 at 10 MV/cm for a film only 25 Åthick^4. We have extended our studies to other rare earth oxides and other semiconductors. For example, low-D_it GaN MOS diodes and GaN MOSFETs operated at 400^circC were obtained. The GaN MOSFET has potential applications in high power switching and high temperature device operation. More remarkably, we have found recently that another rare earth oxide, Y_2O3 (ɛ = 18) showed excellent electrical properties as a gate dielectric for Si, to replace the current SiO_2, where the thickness is now approaching the quantum limit^5. *In collaboration with J. Kwo, A. R. Kortan, J. N. Baillargeon, J. P. Mannaerts, F. Ren, Y. C. Wang, T. S. Lay, H. Ng, R. Opila, K. L. Queeney, Y. J. Chabal, T. Boone, J. J. Krajewski, A. M. Sergent, J. M. Rosamilia, M. Passlack, D. W. Murphy, and A. Y. Cho. 1. M. Hong, et al, J. Vac. Sci. Technol. B14, 2297, (1996). 2. F. Ren et al, IEDM Technical Digest, p.943, (1996

  4. Improvement in performance of solution-processed indium-zinc-tin oxide thin-film transistors by UV/O3 treatment on zirconium oxide gate insulator

    NASA Astrophysics Data System (ADS)

    Naik, Bukke Ravindra; Avis, Christophe; Delwar Hossain Chowdhury, Md; Kim, Taehun; Lin, Tengda; Jang, Jin

    2016-03-01

    We studied solution-processed amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs) with spin-coated zirconium oxide (ZrOx) as the gate insulator. The ZrOx gate insulator was used without and with UV/O3 treatment. The TFTs with an untreated ZrOx gate dielectric showed a saturation mobility (μsat) of 0.91 ± 0.29 cm2 V-1 s-1, a threshold voltage (Vth) of 0.28 ± 0.36 V, a subthreshold swing (SS) of 199 ± 37.17 mV/dec, and a current ratio (ION/IOFF) of ˜107. The TFTs with a UV/O3-treated ZrOx gate insulator exhibited μsat of 2.65 ± 0.43 cm2 V-1 s-1, Vth of 0.44 ± 0.35 V, SS of 133 ± 24.81 mV/dec, and ION/IOFF of ˜108. Hysteresis was 0.32 V in the untreated TFTs and was eliminated by UV/O3 treatment. Also, the leakage current decreased significantly when the IZTO TFT was coated onto a UV/O3-treated ZrOx gate insulator.

  5. Effect of nitrogen incorporation into Al-based gate insulators in AlON/AlGaN/GaN metal-oxide-semiconductor structures

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Nozaki, Mikito; Yamada, Takahiro; Ito, Joyo; Nakazawa, Satoshi; Ishida, Masahiro; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2016-10-01

    The superior physical and electrical properties of aluminum oxynitride (AlON) gate dielectrics on AlGaN/GaN substrates in terms of thermal stability, reliability, and interface quality were demonstrated by direct AlON deposition and subsequent annealing. Nitrogen incorporation into alumina was proven to be beneficial both for suppressing intermixing at the insulator/AlGaN interface and reducing the number of electrical defects in Al2O3 films. Consequently, we achieved high-quality AlON/AlGaN/GaN metal-oxide-semiconductor capacitors with improved stability against charge injection and a reduced interface state density as low as 1.2 × 1011 cm-2 eV-1. The impact of nitrogen incorporation into the insulator will be discussed on the basis of experimental findings.

  6. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    SciTech Connect

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  7. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  8. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    PubMed

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

  9. High-performance GaN metal-insulator-semiconductor ultraviolet photodetectors using gallium oxide as gate layer.

    PubMed

    Lee, Ming-Lun; Mue, T S; Huang, F W; Yang, J H; Sheu, J K

    2011-06-20

    In this study, gallium nitride (GaN)-based metal-insulator-semiconductor (MIS) ultraviolet (UV) photodetectors (PDs) with a gallium oxide (GaO(x)) gate layer formed by alternating current bias-assisted photoelectrochemical oxidation of n-GaN are presented. By introducing the GaO(x) gate layer to the GaN MIS UV PDs, the leakage current is reduced and a much larger UV-to-visible rejection ratio (R(UV/vis)) of spectral responsivity is achieved. In addition, a bias-dependent spectral response results in marked increase of the R(UV/vis) with bias voltage up to ~10(5). The bias-dependent responsivity suggests the possible existence of internal gain in of the GaN MIS PDs.

  10. Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

    NASA Astrophysics Data System (ADS)

    Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

    2011-05-01

    TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

  11. Electrolyte Gating of Correlated Electron Materials and Nanostructures in Complex Oxides

    DTIC Science & Technology

    2015-09-17

    Lee, James R. Williams, David Goldhaber-Gordon, "Gate- tunable superconducting weak link and quantum point contact spectroscopy on a strontium titanate...34Gate-tunable superconducting weak link and quantum point contact spectroscopy on a strontium titanate surface" Nature Physics 10, 748 (2014). • Sam W

  12. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  13. Control of Subthreshold Characteristics of Narrow-Channel Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Transistor with Additional Side Gate Electrodes

    NASA Astrophysics Data System (ADS)

    Okuyama, Kiyoshi; Yoshikawa, Koji; Sunami, Hideo

    2007-04-01

    A silicon-on-insulator (SOI) n-type metal-oxide-semiconductor (MOS) transistor with additional side gate electrodes is fabricated and its subthreshold characteristics are discussed. Since its device structure provides independent biasing to gates, flexible device-characteristic control for the respective device is expected. The key fabrication process is the formation of transistor gates. Additional side gate electrodes are formed by reactive ion etching (RIE) with a SiO2-covered top gate as an etching mask. Subthreshold characteristics are improved by negative side-gate biasing. In addition, the side-gate voltage VSG required to decrease off-leakage current by one decade is around 100 mV. Since the sidewall oxide thickness is chosen to be 5 nm, which is the same as the top-oxide thickness, rather sensitive subthreshold-characteristic control compared with that of biasing through a thick buried-oxide layer is achieved in response to performance requirement. In the viewpoint of stand-by-power suppression, these provide a certain controllability to a circuit operation.

  14. Study of Strain Induction for Metal-Oxide-Semiconductor Field-Effect Transistors using Transparent Dummy Gates and Stress Liners

    NASA Astrophysics Data System (ADS)

    Kosemura, Daisuke; Takei, Munehisa; Nagata, Kohki; Akamatsu, Hiroaki; Kohno, Masayuki; Nishita, Tatsuo; Nakanishi, Toshio; Ogura, Atsushi

    2009-06-01

    Strain induction was studied on a sample that had a dummy gate tetraethyl orthosilicate-silicon dioxide (TEOS-SiO2) and SiN film by UV-Raman spectroscopy with high spatial and high wave-number resolution. The UV laser penetrated through the dummy gate that was transparent to UV light, which enabled us to evaluate strain in the channel of the metal-oxide-semiconductor field-effect transistor (MOSFET) model. Furthermore, we compared stress profiles obtained by finite element (FE) calculations with those obtained by UV-Raman measurements. There was a difference between the stress profiles in the line-and-space pattern sample and in the dummy-gate sample; large compressive (tensile) strains were concentrated at the channel edges in the dummy-gate sample with the compressive (tensile) stress liner, although both tensile and compressive strains existed at the channel edge in the line-and-space pattern sample. The results from UV-Raman spectroscopy were consistent with those obtained by the FE calculation.

  15. Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2014-11-07

    A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

  16. Reliability of ^1^H NMR analysis for assessment of lipid oxidation at frying temperatures

    Technology Transfer Automated Retrieval System (TEKTRAN)

    The reliability of a method using ^1^H NMR analysis for assessment of oil oxidation at a frying temperature was examined. During heating and frying at 180 °C, changes of soybean oil signals in the ^1^H NMR spectrum including olefinic (5.16-5.30 ppm), bisallylic (2.70-2.88 ppm), and allylic (1.94-2.1...

  17. Simple and reliable method for determination of oxygen content in high- Tc copper oxides

    NASA Astrophysics Data System (ADS)

    Maeno, Yoshiteru; Teraoka, Hideki; Matsukuma, Kuniko; Yoshida, Koji; Sugiyama, Kimihiko; Nakamura, Fumihiko; Fujita, Toshizo

    1991-12-01

    We present the details of a simple and reliable iodine-titration method suited for high- Tc copper oxides, in which the use of a solution of ammonium acetate and acetic acid as a buffer agent substantially improves the operation. The results applied to La 2- xM xCuO 4- δ (M = Ba, Sr and Ca) are presented.

  18. MIS and MFIS Devices: DyScO3 as a gate-oxide and buffer-layer

    NASA Astrophysics Data System (ADS)

    Melgarejo, R.; Karan, N. K.; Saavedra-Arias, J.; Pradhan, D. K.; Thomas, R.; Katiyar, R. S.

    2008-03-01

    Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure is of importance in nonvolatile memories, as insulating buffer layer that prevents interdiffusion between the ferroelectric (FE) and the Si substrate. However, insulating layer has some disadvantages viz. generation of depolarization field in FE film and increase of operation voltage. To overcome this, it is important to find a FE with low ɛr (compared to normal FE) and an insulating buffer layer with high ɛr (compared to ɛr = 3.9 of SiO2). High-k materials viz. LaAlO3, SiN, HfO2, HfAlO etc. have been studied as buffer layers in the MFIS structures and as gate-oxide in metal-insulator-silicon (MIS). Recently, a novel gate dielectric material, DyScO3 was considered and studies indicate that crystallization temperature significantly increased and the film on Si remained amorphous even at 1000 C annealing. Considering the requirements on crystallization temperature, ɛr, electrical stability for high-k buffer layers, DyScO3 seems to be very promising for future MFIS device applications. Therefore, the evaluations of MOCVD grown DyScO3 as gate-oxide for MIS and the buffer layers for Bi3.25La0.75Ti3O12 based MFIS structures are presented.

  19. Effects of Rare-Earth Oxides on the Reliability of X7R Dielectrics

    NASA Astrophysics Data System (ADS)

    Sakabe, Yukio; Hamaji, Yukio; Sano, Harunobu; Wada, Nobuyuki

    2002-09-01

    The effects of rare-earth oxides, e.g., La, Nd, Sm, Dy and Yb, on the reliability of multilayer capacitors (MLCs) with X7R dielectrics and Ni electrodes were investigated. Microstructures of the dielectrics were analyzed by transmission electron microscopy (TEM) and electron probe microanalysis (EPMA) in order to characterize the rare-earth ions. Incorporation of rare-earth ions to BaTiO3 ceramics depended on their ionic radius, resulting in different microstructures and electric performances of dielectrics. Dy ions provided BaTiO3 ceramics with ideal X7R characteristics and high reliability. The mechanism governing leakage current was discussed in terms of the voltage dependence of leakage current. Electric properties and related reliability of the capacitors were attributed to solubility, distribution of rare-earth oxides and their occupation site in BaTiO3.

  20. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  1. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  2. Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

    NASA Astrophysics Data System (ADS)

    Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

    2016-12-01

    The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP.

  3. Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

    PubMed Central

    Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

    2016-01-01

    The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP. PMID:27924838

  4. Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

    NASA Astrophysics Data System (ADS)

    Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

    2016-04-01

    Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

  5. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    NASA Astrophysics Data System (ADS)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  6. Sensitive and reliable ascorbic acid sensing by lanthanum oxide/reduced graphene oxide nanocomposite.

    PubMed

    Mogha, Navin Kumar; Sahu, Vikrant; Sharma, Meenakshi; Sharma, Raj Kishore; Masram, Dhanraj T

    2014-10-01

    A simple strategy for the detection and estimation of ascorbic acid (AA), using lanthanum oxide-reduced graphene oxide nanocomposite (LO/RGO) on indium tin oxide (ITO) substrate, is reported. LO/RGO displays high catalytic activity toward the oxidation of AA, and the synergism between lanthanum oxide and reduced graphene oxide was attributed to the successful and efficient detection. Detection mechanism and sensing efficacy of LO/RGO nanocomposite are investigated by electrochemical techniques. Chronoamperometric results under optimal conditions show a linear response range from 14 to 100 μM for AA detection. Commercially available vitamin C tablets were also analyzed using the proposed LO/RGO sensor, and the remarkable recovery percentage (97.64-99.7) shows the potential application in AA detection.

  7. Effects of gate stack structural and process defectivity on high-k dielectric dependence of NBTI reliability in 32 nm technology node PMOSFETs.

    PubMed

    Hussin, H; Soin, N; Bukhori, M F; Hatta, S Wan Muhamad; Wahab, Y Abdul

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E' center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

  8. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  9. Rat Aquaporin-5 Is pH-Gated Induced by Phosphorylation and Is Implicated in Oxidative Stress

    PubMed Central

    Rodrigues, Claudia; Mósca, Andreia Filipa; Martins, Ana Paula; Nobre, Tatiana; Prista, Catarina; Antunes, Fernando; Cipak Gasparovic, Ana; Soveral, Graça

    2016-01-01

    Aquaporin-5 (AQP5) is a membrane water channel widely distributed in human tissues that was found up-regulated in different tumors and considered implicated in carcinogenesis in different organs and systems. Despite its wide distribution pattern and physiological importance, AQP5 short-term regulation was not reported and mechanisms underlying its involvement in cancer are not well defined. In this work, we expressed rat AQP5 in yeast and investigated mechanisms of gating, as well as AQP5’s ability to facilitate H2O2 plasma membrane diffusion. We found that AQP5 can be gated by extracellular pH in a phosphorylation-dependent manner, with higher activity at physiological pH 7.4. Moreover, similar to other mammalian AQPs, AQP5 is able to increase extracellular H2O2 influx and to affect oxidative cell response with dual effects: whereas in acute oxidative stress conditions AQP5 induces an initial higher sensitivity, in chronic stress AQP5 expressing cells show improved cell survival and resistance. Our findings support the involvement of AQP5 in oxidative stress and suggest AQP5 modulation by phosphorylation as a novel tool for therapeutics. PMID:27983600

  10. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  11. An easy and reliable automated method to estimate oxidative stress in the clinical setting.

    PubMed

    Vassalle, Cristina

    2008-01-01

    During the last few years, reliable and simple tests have been proposed to estimate oxidative stress in vivo. Many of them can be easily adapted to automated analyzers, permitting the simultaneous processing of a large number of samples in a greatly reduced time, avoiding manual sample and reagent handling, and reducing variability sources. In this chapter, description of protocols for the estimation of reactive oxygen metabolites and the antioxidant capacity (respectively the d-ROMs and OXY Adsorbent Test, Diacron, Grosseto, Italy) by using the clinical chemistry analyzer SYNCHRON, CX 9 PRO (Beckman Coulter, Brea, CA, USA) is reported as an example of such an automated procedure that can be applied in the clinical setting. Furthermore, a calculation to compute a global oxidative stress index (Oxidative-INDEX), reflecting both oxidative and antioxidant counterparts, and, therefore, a potentially more powerful parameter, is also described.

  12. Improvement of Ron under AC Operation of Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)

    NASA Astrophysics Data System (ADS)

    Takaya, Hidefumi; Miyagi, Kyosuke; Hamada, Kimimori

    A MOSFET structure called a FITMOS (Floating Island and Thick Bottom Oxide Trench Gate MOSFET) that exhibits a record low loss in the 60V breakdown voltage (BVdss) range has been successfully developed. The following improvements achieved progress in the characteristic of FITMOS. (1) At the time of AC operation, the charges in the floating P islands that are a feature of the floating type device become greater, thereby increasing the on-resistance (Ron) due to the JFET effect. This issue was solved by forming passive hole gates in the end walls of the trenches. The Ron under AC operation is equivalent to the Ron under DC operation. This paper clarified the influence of the passive hole gate diffusion layer shape and the impurity concentration to BVdss and AC operation. (2) The trade-off of BVdss and Ron has been improved by making the floating island into an elliptical form. A BVdss of 83V and a specific on-resistance (RonA) of 36mΩmm2 were obtained.

  13. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  14. Leakage current conduction behaviors of 0.65 nm equivalent-oxide-thickness HfZrLaO gate dielectrics

    NASA Astrophysics Data System (ADS)

    Lin, K. C.; Chen, J. Y.; Hsu, H. W.; Chen, H. W.; Liu, C. H.

    2012-11-01

    The high κ gate dielectrics of MOS capacitors with LaO/HfZrO stacked (denoted as HfZrLaO) have been fabricated by atomic-layer-deposited (ALD). In this study, the data show that the gate leakage current density (Jg) is about 1.9 A/cm2, and the equivalent oxide thickness (EOT) is about 0.65 nm with quantum effects taken into account. The analysis of the leakage current conduction characteristics is based on the temperature dependence of the leakage current from 300 to 475 K. The dominant current conduction behaviors are Schottky emission in the region of low electric fields (<1 MV/cm) and high temperatures (450-475 K), Poole-Frankel (P-F) emission in the region of medium electric fields (2.3-3.83 MV/cm) and low temperatures (300-350 K), and Fowler-Nordheim (F-N) tunneling in the region of high electric fields (>4 MV/cm) and low temperatures (<300 K). The electron barrier height (ΦB) at gate interface and the trap energy level (Φt) in the dielectric are extracted to be 1.07 and 1.38 eV, respectively.

  15. A high-mobility electronic system at an electrolyte-gated oxide surface

    PubMed Central

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-01-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm−2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized. PMID:25762485

  16. A high-mobility electronic system at an electrolyte-gated oxide surface

    NASA Astrophysics Data System (ADS)

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-03-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm-2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized.

  17. Enzymatic AND logic gate with sigmoid response induced by photochemically controlled oxidation of the output.

    PubMed

    Privman, Vladimir; Fratto, Brian E; Zavalov, Oleksandr; Halámek, Jan; Katz, Evgeny

    2013-06-27

    We report a study of a system which involves an enzymatic cascade realizing an AND logic gate, with an added photochemical processing of the output, allowing the gate's response to be made sigmoid in both inputs. New functional forms are developed for quantifying the kinetics of such systems, specifically designed to model their response in terms of signal and information processing. These theoretical expressions are tested for the studied system, which also allows us to consider aspects of biochemical information processing such as noise transmission properties and control of timing of the chemical and physical steps.

  18. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

    NASA Astrophysics Data System (ADS)

    Huoxi, Xu; Jingping, Xu

    2016-06-01

    LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV-1 cm-2), gate leakage property (3.6 × 10-3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials. Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

  19. Voltage-gated calcium channel currents in human coronary myocytes. Regulation by cyclic GMP and nitric oxide.

    PubMed Central

    Quignard, J F; Frapier, J M; Harricane, M C; Albat, B; Nargeot, J; Richard, S

    1997-01-01

    Voltage-gated Ca2+ channels contribute to the maintenance of contractile tone in vascular myocytes and are potential targets for vasodilating agents. There is no information available about their nature and regulation in human coronary arteries. We used the whole-cell voltage-clamp technique to characterize Ca2+-channel currents immediately after enzymatic dissociation and after primary culture of coronary myocytes taken from heart transplant patients. We recorded a dihydropyridine-sensitive L-type current in both freshly isolated and primary cultured cells. A T-type current was recorded only in culture. The L- (but not the T-) type current was inhibited by permeable analogues of cGMP in a dose-dependent manner. This effect was mimicked by the nitric oxide-generating agents S-nitroso-N-acetylpenicillamine (SNAP) and 3-morpholinosydnonimine which increased intracellular cGMP. Methylene blue, known to inhibit guanylate cyclase, antagonized the effect of SNAP. Inhibitions by SNAP and cGMP were not additive and seemed to occur through a common pathway. We conclude that (a) L-type Ca2+ channels are the major pathway for voltage-gated Ca2+ entry in human coronary myocytes; (b) their inhibition by agents stimulating nitric oxide and/or intracellular cGMP production is expected to contribute to vasorelaxation and may be involved in the therapeutic effect of nitrovasodilators; and (c) the expression of T-type Ca2+ channels in culture may be triggered by cell proliferation. PMID:9005986

  20. Simulation of quantum dot floating gate MOSFET memory performance using various high-k material as tunnel oxide

    NASA Astrophysics Data System (ADS)

    Aji, Adha Sukma; Darma, Yudi

    2012-06-01

    In this paper, performance of quantum dot floating gate MOSFET memory is simulated by replacing the SiO2 tunnel oxide with high-Κ material. There are three high-k material simulated in this paper, HfO2, ZrO2, and Y2O3. As we know that high-Κ material is used nowadays to reduce leakage current, so this paper demonstrates the application of high-Κ material to reduce leakage current in non-volatile memory quantum dot based floating gate MOSFET. Simulation results of this paper show the leakage current can be suppressed by using high-Κ material as tunnel oxide up to 10 times. Furthermore, this paper also shows that the memory performance can be properly sustained. The writing and erasing time are depend on tunneling current probability which calculated using transfer matrix method. The writing time and erasing time for HfO2 and ZrO2 are 150 nanosecond and 15 nanosecond.

  1. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  2. Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone-Water-Last Treatment

    NASA Astrophysics Data System (ADS)

    Oshiyama, Itaru; Tai, Kaori; Hirano, Tomoyuki; Yamaguchi, Shinpei; Tanaka, Kazuaki; Hagimoto, Yoshiya; Uemura, Takayuki; Ando, Takashi; Watanabe, Koji; Yamamoto, Ryo; Kanda, Saori; Wang, Junli; Tateshita, Yasushi; Wakabayashi, Hitoshi; Tagawa, Yukio; Tsukamoto, Masanori; Iwamoto, Hayato; Saito, Masaki; Oshima, Masaharu; Toyoda, Satoshi; Nagashima, Naoki; Kadomura, Shingo

    2008-04-01

    In this paper, we demonstrate a wet treatment for the HfSix/HfO2 gate stack of n-type metal oxide semiconductor field effect transistor (nMOSFET) fabricated by a gate-last process in order to scale down the electrical thickness at inversion state Tinv value and reduce the gate leakage Jg. As a result, we succeeded in scaling down Tinv to 1.41 nm without mobility or Jg degradation by ozone-water-last treatment. We found that a high-density interfacial layer (IFL) is formed owing to the ozone-water-last treatment, and Hf diffusion to the IFL is suppressed, which was analyzed by high-resolution angle-resolved spectroscopy.

  3. A high-mobility electronic system at an electrolyte-gated oxide surface

    NASA Astrophysics Data System (ADS)

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor; Stanwyck, Sam; Williams, James; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-03-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities in surface two-dimensional electron systems (2DES). Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the surface of interest, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the 2DES. In this talk, we demonstrate that this disorder can be minimized by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride (BN). We illustrate our technique with electrolyte-gated strontium titanate, whose mobility improves more than tenfold when protected with BN. We find this improvement even for our thinnest BN, of measured thickness 6 Angstrom, with which we can accumulate electron densities nearing 1014 cm-2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized.

  4. Ultraviolet-assisted oxidation and nitridation of hafnium and hafnium aluminum alloys as potential gate dielectrics for metal oxide semiconductor applications

    NASA Astrophysics Data System (ADS)

    Essary, Chad Robert

    The continued miniaturization of silicon-based complimentary metal oxide semiconductor (CMOS) devices is pushing the limits of the silicon dioxide (SiO2) gate dielectric. As the channel widths are decreased to increase packing densities and functionality of new chips, proportional vertical scaling of the dielectric must be maintained to keep constant capacitances. Silicon dioxide is approaching its fundamental limit in which it can be used as the gate dielectric due to high leakage currents resulting from direct tunneling through the layer. In order for the continued use of current CMOS gate design, an alternative material with a higher dielectric constant must be found. Several materials have been proposed but are still not providing the electrical characteristics favorable for use in the devices due to problems with excessive leakage and hysteresis resulting from the quality of the film and oxygen defects. The goal of this study is to create higher quality films at lower processing temperatures with low leakage and less hysteresis than has been achieved with hafnium oxide films. This study first examines the formation of the interfacial layer in pulsed laser deposited hafnium oxide films to understand the kinetics behind its formation. The second section focuses on the oxidation of pulsed laser deposited (PLD) hafnium metal thin films using ultraviolet (UV) assisted post-deposition annealing. Another set of samples was deposited in an ammonia atmosphere in order to incorporate nitrogen into the films. Comparisons of microstructure and stoichiometry of oxidized hafnium and oxy-nitride films were made using x-ray photospectroscopy, variable angle spectroscopic ellipsometry, glancing angle x-ray spectroscopy, x-ray reflectivity, and atomic force microscopy. Analysis of the interface between the films and the silicon substrate was carried out using x-ray reflectivity. The electrical characteristics of the films were characterized using capacitance-voltage and current

  5. Influence of source and drain contacts on the properties of the indium-zinc oxide thin-film transistors based on anodic aluminum oxide gate dielectrics

    NASA Astrophysics Data System (ADS)

    Lan, Linfeng; Xu, Miao; Peng, Junbiao; Xu, Hua; Li, Min; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Wang, Lei; Yao, Rihui

    2011-11-01

    Thin-film transistors (TFTs) based on indium-zinc oxide (IZO) active layer and anodic aluminum oxide (Al2O3) gate dielectric layer were fabricated. The influence of source and drain (S/D) contacts on TFT performance was investigated by comparing IZO-TFTs with different S/D electrodes. The TFT with Mo S/D electrodes had higher output current and lower threshold voltage, but had poorer subthreshold swing and lower effective electron mobility compared to that with ITO S/D electrodes. By using x-ray photoelectron spectroscopy (XPS) depth profile analyzing method, it was observed that Mo was diffusing seriously into IZO, resulting in the variation of the effective channel length, thereby causing serious short-channel effect, poor subshreshold swing, and bad uniformity of the TFTs with Mo S/D electrodes.

  6. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    SciTech Connect

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-24

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  7. Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

    PubMed

    Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

    2013-06-11

    We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

  8. High K Oxide Insulated Gate Group III Nitride-Based FETs

    DTIC Science & Technology

    2014-03-21

    AND ADDRESS(ES) Kansas State University 2 Fairchild Hall Manhattan , KS 66506-1103 3. DATES COVERED (From - To) 04/05/2009-03/20/2014 5a. CONTRACT...NUMBER 5b. GRANT NUMBER N00014-09-1-1160 5c. PROGRAM ELEMENT NUMBER 5d. PROJECT NUMBER 09PRE09471-00 5e. TASK NUMBER 5f. WORK UNIT NUMBER 9...results indicate the promising potential of incorporation gate dielectric in future GaN devices. This project supported two students who completed

  9. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    SciTech Connect

    Zhu, Li Qiang Chao, Jin Yu; Xiao, Hui

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  10. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  11. Liquid-Gated High Mobility and Quantum Oscillation of the Two-Dimensional Electron Gas at an Oxide Interface.

    PubMed

    Zeng, Shengwei; Lü, Weiming; Huang, Zhen; Liu, Zhiqi; Han, Kun; Gopinadhan, Kalon; Li, Changjian; Guo, Rui; Zhou, Wenxiong; Ma, Haijiao Harsan; Jian, Linke; Venkatesan, Thirumalai; Ariando

    2016-04-26

    Electric field effect in electronic double layer transistor (EDLT) configuration with ionic liquids as the dielectric materials is a powerful means of exploring various properties in different materials. Here, we demonstrate the modulation of electrical transport properties and extremely high mobility of two-dimensional electron gas at LaAlO3/SrTiO3 (LAO/STO) interface through ionic liquid-assisted electric field effect. With a change of the gate voltages, the depletion of charge carrier and the resultant enhancement of electron mobility up to 19 380 cm(2)/(V s) are realized, leading to quantum oscillations of the conductivity at the LAO/STO interface. The present results suggest that high-mobility oxide interfaces, which exhibit quantum phenomena, could be obtained by ionic liquid-assisted field effect.

  12. Band offsets of high K gate oxides on III-V semiconductors

    NASA Astrophysics Data System (ADS)

    Robertson, J.; Falabretti, B.

    2006-07-01

    III-V semiconductors have high mobility and will be used in field effect transistors with the appropriate gate dielectric. The dielectrics must have band offsets over 1eV to inhibit leakage. The band offsets of various gate dielectrics including HfO2, Al2O3, Gd2O3, Si3N4, and SiO2 on III-V semiconductors such as GaAs, InAs, GaSb, and GaN have been calculated using the method of charge neutrality levels. Generally, the conduction band offsets are found to be over 1eV, so they should inhibit leakage for these dielectrics. On the other hand, SrTiO3 has minimal conduction band offset. The valence band offsets are also reasonably large, except for Si nitride on GaN and Sc2O3 on GaN which are 0.6-0.8eV. There is reasonable agreement with experiment where it exists, although the GaAs :SrTiO3 case is even worse in experiment.

  13. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  14. Aqueous combustion synthesis of aluminum oxide thin films and application as gate dielectric in GZTO solution-based TFTs.

    PubMed

    Branquinho, Rita; Salgueiro, Daniela; Santos, Lídia; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2014-11-26

    Solution processing has been recently considered as an option when trying to reduce the costs associated with deposition under vacuum. In this context, most of the research efforts have been centered in the development of the semiconductors processes nevertheless the development of the most suitable dielectrics for oxide based transistors is as relevant as the semiconductor layer itself. In this work we explore the solution combustion synthesis and report on a completely new and green route for the preparation of amorphous aluminum oxide thin films; introducing water as solvent. Optimized dielectric layers were obtained for a water based precursor solution with 0.1 M concentration and demonstrated high capacitance, 625 nF cm(-2) at 10 kHz, and a permittivity of 7.1. These thin films were successfully applied as gate dielectric in solution processed gallium-zinc-tin oxide (GZTO) thin film transistors (TFTs) yielding good electrical performance such as subthreshold slope of about 0.3 V dec(-1) and mobility above 1.3 cm2 V(-1) s(-1).

  15. Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

    NASA Astrophysics Data System (ADS)

    Kamei, Takahiro; Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

    2012-06-01

    Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage (Vt) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BVg) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO2) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source-drain (SD) breakdown voltage (BVDS) as high as 4.5 V was obtained even when the gate length (Lg) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage (Vg) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.

  16. Light-Induced Carrier Transfer in NiSi-Nanodots/Si-Quantum-Dots Hybrid Floating Gate in Metal-Oxide-Semiconductor Structures

    NASA Astrophysics Data System (ADS)

    Morisawa, Naoya; Ikeda, Mitsuhisa; Nakanishi, Sho; Kawanami, Akira; Makihara, Katsunori; Miyazaki, Seiichi

    2010-04-01

    We have fabricated a metal-oxide-semiconductor (MOS) capacitor with a hybrid floating gate stack consisting of silicon quantum dots (Si-QDs) and NiSi Nanodots (NiSi-NDs) with a 3-nm-thick interlayer SiO2, and studied the effect of 1310 nm light irradiation on charge distribution in a hybrid floating gate. The light irradiation resulted in a reduced flat-band voltage shift due to the charging of the hybrid floating gate under the application of gate biases in comparison to the shift in the dark. This result can be interpreted in terms of the shift of the charge centroid toward the gate side in the hybrid floating gate caused by the photoexcitation of electrons in NiSi-NDs and the subsequent electron tunneling to Si-QDs. When the light irradiation was turned off, the transferred charges moved back from the Si-QDs to the NiSi-NDs without being emitted to the Si substrate.

  17. The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

    PubMed Central

    Yang, Wen; Sun, Qing-Qing; Geng, Yang; Chen, Lin; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

    2015-01-01

    The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics. PMID:26146017

  18. High-performance GaAs metal-oxide-semiconductor capacitor by using NbAlON as high-k gate dielectric

    NASA Astrophysics Data System (ADS)

    Liu, L. N.; Choi, H. W.; Xu, J. P.; Lai, P. T.

    2017-03-01

    A GaAs metal-oxide-semiconductor (MOS) capacitor using NbAlON as a gate dielectric with different Nb contents is fabricated. Experimental results show that the k value and crystallization temperature of the AlON dielectric can be improved by Nb incorporation, together with reduction in negative oxide charges. However, the interface quality and gate leakage become poorer as the Nb content increases, as confirmed by TEM and X-ray photoelectron spectroscopy results. Therefore, through comprehensively considering the advantages and disadvantages, the sample with a Nb/(Al+Nb) atomic ratio of 62.5% exhibits the best characteristics: high k value (23.3), low interface-state density (2.7 × 1012 cm-2/eV), small hysteresis (55 mV), small frequency dispersion, and low gate leakage current (2.66 × 10-5A/cm2 at Vfb + 1 V). By comparing with reported GaAs MOS devices with different high-k gate dielectrics, it can be suggested that NbAlON is a promising gate dielectric material to achieve excellent electrical performance for GaAs MOS devices.

  19. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy

    PubMed Central

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-01-01

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band. PMID:26446400

  20. Effect of Oxide Interface Roughness on the Threshold Voltage Fluctuations in Decanano MOSFETs with Ultrathin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Kaya, S.

    2000-01-01

    In this paper we use the Density Gradient (DG) simulation approach to study, in 3-D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2-D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the Quantum Mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.

  1. Oxidation of Phe454 in the Gating Segment Inactivates Trametes multicolor Pyranose Oxidase during Substrate Turnover

    PubMed Central

    Volc, Jindrich; Peterbauer, Clemens K.; Leitner, Christian; Haltrich, Dietmar

    2016-01-01

    The flavin-dependent enzyme pyranose oxidase catalyses the oxidation of several pyranose sugars at position C-2. In a second reaction step, oxygen is reduced to hydrogen peroxide. POx is of interest for biocatalytic carbohydrate oxidations, yet it was found that the enzyme is rapidly inactivated under turnover conditions. We studied pyranose oxidase from Trametes multicolor (TmPOx) inactivated either during glucose oxidation or by exogenous hydrogen peroxide using mass spectrometry. MALDI-MS experiments of proteolytic fragments of inactivated TmPOx showed several peptides with a mass increase of 16 or 32 Da indicating oxidation of certain amino acids. Most of these fragments contain at least one methionine residue, which most likely is oxidised by hydrogen peroxide. One peptide fragment that did not contain any amino acid residue that is likely to be oxidised by hydrogen peroxide (DAFSYGAVQQSIDSR) was studied in detail by LC-ESI-MS/MS, which showed a +16 Da mass increase for Phe454. We propose that oxidation of Phe454, which is located at the flexible active-site loop of TmPOx, is the first and main step in the inactivation of TmPOx by hydrogen peroxide. Oxidation of methionine residues might then further contribute to the complete inactivation of the enzyme. PMID:26828796

  2. CCD gate definition process

    NASA Astrophysics Data System (ADS)

    Bluzer

    1986-02-01

    The present invention utilizes a double masking step in a CCD gate definition process to eliminate the re-entrant oxide by using a thin film layer other than photoresist to define the polysilicon gates used by defining the thin film layer with a double masking process before any of the polysilicon gate layer is etched. It is one object of the present invention, therefore, to provide an improved process for CCD gate definition. It is another object of the invention to provide an improved CCD gate definition process wherein a profiled oxide layer is produced over a polysilicon layer without re-entrant oxide regions. It is another object of the invention to provide an improved CCD gate definition process wherein a thin film layer is utilized to define the polysilicon gate layers. It is another object of the invention to provide an improved CCD gate definition process wherein the thin film layer is defined by a double masking process before any polysilicon layer is etched.

  3. Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO2 Gate Stack Fabricated by Gate-Last Process

    NASA Astrophysics Data System (ADS)

    Ando, Takashi; Hirano, Tomoyuki; Tai, Kaori; Yamaguchi, Shinpei; Yoshida, Shinichi; Iwamoto, Hayato; Kadomura, Shingo; Watanabe, Heiji

    2010-01-01

    Systematic characterization of Hf-Si/HfO2 gate stacks revealed two mobility degradation modes. One is carrier scattering by fixed charges and/or trapped charges induced by the crystallization in the thick HfO2 case (inversion oxide thickness, Tinv> 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate in the thin HfO2 case (Tinv< 1.6 nm) for the Hf-rich electrode. It was demonstrated that careful optimization of the HfO2 thickness and the Hf-Si composition can suppress both modes. As a result, a high electron mobility equivalent to that of n+polycrystalline silicon (poly-Si)/SiO2 (248 cm2 V-1 s-1 at Eeff=1 MV/cm) was obtained at Tinv of 1.47 nm. Moreover, the effective work function of the optimized Hf-Si/HfO2 gate stack is located within 50 mV from the Si band edge (Ec). An extremely high Ion of 1165 µA/µm (at Ioff = 81 nA/µm) at Vdd=1.0 V was demonstrated for a 45 nm gate n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) without strain enhanced technology.

  4. Flatband voltage control in p-metal gate metal-oxide-semiconductor field effect transistor by insertion of TiO2 layer

    NASA Astrophysics Data System (ADS)

    Maeng, W. J.; Kim, Woo-Hee; Koo, Ja Hoon; Lim, S. J.; Lee, Chang-Soo; Lee, Taeyoon; Kim, Hyungjun

    2010-02-01

    Titanium oxide (TiO2) layer was used to control the flatband voltage (VFB) of p-type metal-oxide-semiconductor field effect transistors. TiO2 was deposited by plasma enhanced atomic layer deposition (PE-ALD) on hafnium oxide (HfO2) gate dielectrics. Comparative studies between TiO2 and Al2O3 as capping layer have shown that improved device properties with lower capacitance equivalent thickness (CET), interface state density (Dit), and flatband voltage (VFB) shift were achieved by PE-ALD TiO2 capping layer.

  5. Floating Gate Memory with Biomineralized Nanodots Embedded in High-k Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Ohara, Kosuke; Yamashita, Ichiro; Yaegashi, Toshitake; Moniwa, Masahiro; Yoshimaru, Masaki; Uraoka, Yukiharu

    2009-09-01

    The memory properties of a nanodot-type floating gate memory with Co bio-nanodots (Co-BNDs) embedded in HfO2 were investigated. High-density and uniform Co-BNDs were adsorbed on the HfO2 tunnel oxide using ferritin. The fabricated metal oxide semiconductor (MOS) capacitor exhibited a capacitance-voltage (C-V) curve with large hysteresis. The memory window size was 30 times higher than that of the MOS capacitor with a SiO2 gate oxide. Not only a large memory window but also excellent charge retention and reliability characteristics were obtained for a MOS field-effect transistor (MOSFET). This research confirmed that the proposed memory is promising for use in next-generation memory devices.

  6. Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

    NASA Astrophysics Data System (ADS)

    Chang, P. K.; Hwu, J. G.

    2017-04-01

    The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

  7. Near-IR squaraine dye-loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device.

    PubMed

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-09-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use.

  8. Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

    PubMed Central

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-01-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  9. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    SciTech Connect

    Babadi, A. S. Lind, E.; Wernersson, L. E.

    2014-12-07

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  10. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  11. Simulation of Leakage Current in Si/Ge/Si Quantum Dot Floating Gate MOSFET Using High-K Material as Tunnel Oxide

    NASA Astrophysics Data System (ADS)

    Aji, Adha Sukma; Nugraha, Mohamad Insan; Yudhistira; Rahayu, Fitria; Darma, Yudi

    2011-12-01

    Leakage current in nano-scale MOSFET has been calculated using variety of tunnel oxides. Firstly, this paper evaluates the leakage current in MOSFET devices when using SiO2 as tunnel oxide. When the thickness of tunnel oxide decreases into 1,4 nm, the leakage current will raise and cause power dissipation about 40 percent. Leakage current can be reduced by using high-K materials as tunnel oxides. Thicker high-K materials as tunnel oxides are easier to fabricate than SiO2 tunnel oxides with the thickness down to 1,4 nm. In term of Equivalent Oxide Thickness (EOT), using high-K materials for tunnel oxides could give the better performance as 1,4nm SiO2 which is also more simple in the fabrication. Here, we also evaluates the leakage current as the function of temperature, channel length, and oxide thickness. Computational result shows that using HfO2 to replace SiO2 as tunnel oxides can make leakage current decrease up to seven times. For practically use, HfO2 were suiTable as tunnel oxide in memory devices, particularly in quantum dot (QD) floating gate memory. In this case we use heterostructure QD consisting Si/Ge/Si as electronic storage node. The results demonstrated that the memory operation using HfO2 as tunnel oxide has a better performance rather than SiO2.

  12. Reliability analysis of visual ranking of coronary artery calcification on low-dose CT of the thorax for lung cancer screening: comparison with ECG-gated calcium scoring CT.

    PubMed

    Kim, Yoon Kyung; Sung, Yon Mi; Cho, So Hyun; Park, Young Nam; Choi, Hye-Young

    2014-12-01

    Coronary artery calcification (CAC) is frequently detected on low-dose CT (LDCT) of the thorax. Concurrent assessment of CAC and lung cancer screening using LDCT is beneficial in terms of cost and radiation dose reduction. The aim of our study was to evaluate the reliability of visual ranking of positive CAC on LDCT compared to Agatston score (AS) on electrocardiogram (ECG)-gated calcium scoring CT. We studied 576 patients who were consecutively registered for health screening and undergoing both LDCT and ECG-gated calcium scoring CT. We excluded subjects with an AS of zero. The final study cohort included 117 patients with CAC (97 men; mean age, 53.4 ± 8.5). AS was used as the gold standard (mean score 166.0; range 0.4-3,719.3). Two board-certified radiologists and two radiology residents participated in an observer performance study. Visual ranking of CAC was performed according to four categories (1-10, 11-100, 101-400, and 401 or higher) for coronary artery disease risk stratification. Weighted kappa statistics were used to measure the degree of reliability on visual ranking of CAC on LDCT. The degree of reliability on visual ranking of CAC on LDCT compared to ECG-gated calcium scoring CT was excellent for board-certified radiologists and good for radiology residents. A high degree of association was observed with 71.6% of visual rankings in the same category as the Agatston category and 98.9% varying by no more than one category. Visual ranking of positive CAC on LDCT is reliable for predicting AS rank categorization.

  13. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect

    Kamioka, J.; Oda, S.; Kodera, T.; Takeda, K.; Obata, T.; Tarucha, S.

    2014-05-28

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  14. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  15. Amorphous indium zinc oxide thin film transistors with poly-4-vinylphenol gate dielectric layers

    NASA Astrophysics Data System (ADS)

    Pu, Haifeng; Li, Guifeng; Feng, Jiahan; Liu, Baoying; Zhang, Qun

    2011-09-01

    Thin film transistors (TFTs) with amorphous indium zinc oxide (a-IZO) as channel layers and poly-4-vinylphenol as dielectric layers were fabricated. Transmission curves show that the double-layer structure of the a-IZO layer and the poly-4-vinylphenol layer exhibits the antireflection effect. It was found that post heat-treatment at relatively low temperature will improve the electrical performance of the transistors. TFT devices with saturation mobility of 25.4 cm2 V-1 s-1, threshold voltage of 4.0 V, subthreshold swing value of 0.88 V/decade and current on/off ratio of 106 were obtained.

  16. Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chaitali; Bose, Chayanika

    2016-02-01

    The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal-oxide-semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si-substrate interface than to SiO2/Al-gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance-voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

  17. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors.

  18. Zinc Oxide Nanorods Grown on Printed Circuit Board for Extended-Gate Field-Effect Transistor pH Sensor

    NASA Astrophysics Data System (ADS)

    Van Thanh, Pham; Nhu, Le Thi Quynh; Mai, Hong Hanh; Tuyen, Nguyen Viet; Doanh, Sai Cong; Viet, Nguyen Canh; Kien, Do Trung

    2017-02-01

    Zinc oxide (ZnO) nanorods (NRs) were grown directly on printed circuit boards with a 35-μm-thick copper layer using a seedless galvanic-cell hydrothermal process. The hexagonal structure of the synthesized ZnO NRs was observed by scanning electron microscopy. The microstructural characteristics of the as-grown ZnO NRs were investigated by x-ray diffraction analysis, revealing preferred (002) growth direction. Raman and photoluminescence spectra confirmed the high crystalline quality of the ZnO NRs. As-grown ZnO NRs were then grown for 7 h using the galvanic effect for use as the pH membrane of an extended-gate field-effect transistor pH sensor (pH-EGFET). The current-voltage characteristics showed sensitivity of 15.4 mV/pH and 0.26 (μA)1/2/pH in the linear and saturated region, respectively. Due to their cost effectiveness, low-temperature processing, and ease of fabrication, such devices are potential candidates for use as flexible, low-cost, disposable biosensors.

  19. Multi-technique Approach for the Evaluation of the Crystalline Phase of Ultrathin High-k Gate Oxide Films

    NASA Astrophysics Data System (ADS)

    Bersch, E.; LaRose, J. D.; Wells, I.; Consiglio, S.; Clark, R. D.; Leusink, G. J.; Matyi, R. J.; Diebold, A. C.

    2011-11-01

    In order to continue scaling metal oxide semiconductor field effect transistors (MOSFETs) with HfO2 gate oxides, efforts are being made to further improve the deposited high-k film properties. Recently, a process whereby an HfO2 film is deposited through a series of depositions and anneals (so-called DADA process) has been shown to result in films that give rise to MOS capacitors (MOSCAPs) which are electrically scaled compared to MOSCAPs with HfO2 films that only received post deposition anneals (PDA) or no anneals. We have measured as-deposited, DADA and PDA HfO2 films using four measurement techniques, all of which are non-destructive and capable of being used for in-line processing, to evaluate their crystallinity and crystalline phases. Grazing incidence in-plane X-ray diffraction was used to determine the crystalline phases of the HfO2 films. We observed the crystalline phases of these films to be process dependent. Additionally, X-ray and UV photoelectron spectroscopy were used to show the presence of crystallinity in the films. As a fourth technique, spectroscopic ellipsometry was used to determine if the crystalline phases were monoclinic. The combination of techniques was useful in that XPS and UPS were able to confirm the amorphous nature of a 30 cycle DADA film, as measured by GIIXRD, and GIIXRD was able to help us interpret the SE data as being an indication of the monoclinic phase of HfO2.

  20. Degradation mechanisms of electron mobility in metal-oxide-semiconductor field-effect transistors with LaAlO{sub 3} gate dielectric

    SciTech Connect

    Chang, Ingram Yin-ku; You Shengwen; Chen Maingwo; Chen Chunheng; Lee, Joseph Yamin; Juan, Pichun

    2009-05-15

    LaAlO{sub 3} is a promising candidate of gate dielectric for future very large scale integration devices. In this work, metal-oxide-semiconductor capacitors and transistors with LaAlO{sub 3} gate dielectric were fabricated and the electron mobility degradation mechanisms were studied. The LaAlO{sub 3} films were deposited by radio frequency magnetron sputtering. The LaAlO{sub 3} films were examined by x-ray diffraction, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy. The temperature dependence of metal-oxide-semiconductor field-effect transistors characteristics was studied from 11 K to 400 K. The rate of threshold voltage change with temperature (DELTAV{sub T}/DELTAT) is -1.51 mV/K. The electron mobility limited by surface roughness is proportional to E{sub eff}{sup -0.66} in the electric field of 0.93 MV/cmgated n-channel metal-oxide-semiconductor field-effect transistors.

  1. Reduction of surface roughening due to copper contamination prior to ultra-thin gate oxidation

    NASA Astrophysics Data System (ADS)

    Peterson, Charles A.; Vermeire, Bert; Sarid, Dror; Parks, Harold G.

    2001-09-01

    Roughening of the polished side of a silicon wafer caused by copper contamination present on the unpolished side of the wafer was quantified by tapping-mode atomic force microscopy (AFM). The copper contamination was introduced via a contaminated buffered hydrochloric acid solution on the unpolished side of the silicon wafer while the polished side was protected. The protection was then removed, and the wafer placed in a clean HF solution. As a result, the copper on the unpolished side catalyzed electrochemical dissolution of the polished side of the silicon. Power spectral density analysis of hundreds of AFM images showed a 10-fold increase in surface roughness with features between 30 and 300 nm in diameter. Time-dependant dielectric breakdown measurements showed a significant decrease in oxide quality in these wafers. However, the introduction of HCl to the HF solution significantly reduced the roughening process.

  2. Low-temperature processed Schottky-gated field-effect transistors based on amorphous gallium-indium-zinc-oxide thin films

    NASA Astrophysics Data System (ADS)

    Lorenz, M.; Lajn, A.; Frenzel, H.; v. Wenckstern, H.; Grundmann, M.; Barquinha, P.; Martins, R.; Fortunato, E.

    2010-12-01

    We have investigated the electrical properties of metal-semiconductor field-effect transistors (MESFET) based on amorphous oxide semiconductor channels. All functional parts of the devices were sputter-deposited at room temperature. The influence on the electrical properties of a 150 °C annealing step of the gallium-indium-zinc-oxide channel is investigated. The MESFET technology offers a simple route for processing of the transistors with excellent electrical properties such as low subthreshold swing of 112 mV/decade, gate sweep voltages of 2.5 V, and channel mobilities up to 15 cm2/V s.

  3. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect

    Oshima, Yasuhiro; Sun, Yun; Kuzum, Duygu; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  4. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-05-25

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  5. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    NASA Astrophysics Data System (ADS)

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-05-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2‑xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of ‑2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  6. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    PubMed Central

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2−xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of −2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  7. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high- k LaTiON gate dielectric

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Chan, C. L.; Lai, P. T.

    2010-06-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La2O3 ratio, a suitable Ti/La2O3 ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×1011 eV-1 cm-2, and relatively low gate-leakage current density of 2.0×10-3 A cm-2 at a gate voltage of 1 V.

  8. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  9. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE PAGES

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; ...

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  10. Determination of trap distributions from current characteristics of pentacene field-effect transistors with surface modified gate oxide

    NASA Astrophysics Data System (ADS)

    Scheinert, Susanne; Pernstich, Kurt P.; Batlogg, Bertram; Paasch, Gernot

    2007-11-01

    It has been demonstrated [K. P. Pernstich, S. Haas, D. Oberhoff, C. Goldmann, D. J. Gundlach, B. Batlogg, A. N. Rashid, and G. Schitter, J. Appl. Phys. 96, 6431 (2004)] that a controllable shift of the threshold voltage in pentacene thin film transistors is caused by the use of organosilanes with different functional groups forming a self-assembled monolayer (SAM) on the gate oxide. The observed broadening of the subthreshold region indicates that the SAM creates additional trap states. Indeed, it is well known that traps strongly influence the behavior of organic field-effect transistors (OFETs). Therefore, the so-called "amorphous silicon (a-Si) model" has been suggested to be an appropriate model to describe OFETs. The main specifics of this model are transport of carriers above a mobility edge obeying Boltzmann statistics and exponentially distributed tail states and deep trap states. Here, approximate trap distributions are determined by adjusting two-dimensional numerical simulations to the experimental data. It follows from a systematic variation of parameters describing the trap distributions that the existence of both donorlike and acceptorlike trap distributions near the valence band, respectively, and a fixed negative interface charge have to be assumed. For two typical devices with different organosilanes the electrical characteristics can be described well with a donorlike bulk trap distribution, an acceptorlike interface distribution, and/or a fixed negative interface charge. As expected, the density of the fixed or trapped interface charge depends strongly on the surface treatment of the dielectric. There are some limitations in determining the trap distributions caused by either slow time-dependent processes resulting in differences between transfer and output characteristics, or in the uncertainty of the effective mobility.

  11. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  12. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS} = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  13. Oxide thickness-dependent effects of source doping profile on the performance of single- and double-gate tunnel field-effect transistors

    NASA Astrophysics Data System (ADS)

    Chien, Nguyen Dang; Shih, Chun-Hsing

    2017-02-01

    Operated by the band-to-band tunneling at the source-channel junction, the source engineering has been considered as an efficient approach to enhance the performance of tunnel field-effect transistors (TFETs). In this paper, we report a new feature that the effects of source doping profile on the performance of single- and double-gate germanium TFETs depend on equivalent oxide thickness (EOT). Based on the numerical simulations, it is shown that the effect of source concentration on the on-current is stronger with decreasing the EOT, particularly in the double-gate configuration due to the higher gate control capability. Importantly, when the EOT is decreased below a certain value, abrupt source-channel junctions are not only unnecessary, but gradual source doping profiles even improve the performance of TFETs because of the increase in vertical tunneling generation. With the continuous trend of scaling EOT, the oxide thickness-dependent effects of source doping profile should be properly considered in designing TFET devices.

  14. CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

    NASA Astrophysics Data System (ADS)

    Hu, Shi-Gang; Hao, Yue; Ma, Xiao-Hua; Cao, Yan-Rong; Chen, Chi; Wu, Xiao-Feng

    2009-12-01

    This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

  15. High Performance Enhancement-Mode AlGaN/GaN MOSHEMT using Bimodal-Gate-Oxide and CF4 Plasma Treatment

    NASA Astrophysics Data System (ADS)

    Pang, Liang; Kim, Kyekyoon

    2013-03-01

    To realize GaN E-mode HEMTs, CF4 plasma treatment is commonly used. However, comparable performance as the D-mode counterpart has yet to be achieved, since the F-ions implanted into 2DEG degrade the electron mobility by impurity scattering. In this study, a bimodal-gate-oxide scheme is developed, where ALD-Al2O3is utilized to prevent deep ion implantation, and sputtered-SiO2 is employed to suppress plasma-induced leakage current. Firstly, with the Al2O3 energy barrier, the CF4-plasma-treated MOSHEMT increased Vth from -3 V to 0 V, while Imax was only reduced from 503 mA/mm to 460 mA/mm. SIMS measurements confirmed that F- ions were accumulated in the top 5 nm of Al2O3, and the 2DEG impurity concentration was 10 times smaller than the conventional structure. However, due to the gate leakage current through plasma-generated defects in Al2O3, the device exhibited small gate swing of 2 V. Therefore, before gate metal deposition, a SiO2 film was sputtered at room temperature in a self-aligned manner. The highly condensed sputtered-SiO2 was effective in blocking the leakage current. Thus-fabricated bimodal-MOSHEMT exhibited Vth of 0 V, gate swing of 5 V, and Imaxof 462 mA/mm. The small 8% current degradation when converting from D-mode to E-mode is better than previous results. The MOCVD AlGaN/GaN templates used in this work were provided by Kyungpook National University, Korea for which we are grateful to Prof. Jung-Hee Lee and Mr. Dong-Seok Kim.

  16. Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

    NASA Astrophysics Data System (ADS)

    Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

    2017-02-01

    This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm‑2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

  17. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  18. Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Dib, Elias; Bescond, Marc; Cavassilas, Nicolas; Michelini, Fabienne; Raymond, Laurent; Lannoo, Michel

    2013-08-01

    Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

  19. Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

    NASA Astrophysics Data System (ADS)

    Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.; Olsen, C.; Miner, G.

    2001-06-01

    In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications.

  20. Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

    PubMed Central

    Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

    2011-01-01

    Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

  1. Oxidation differentially modulates the recombinant voltage-gated Na(+) channel α-subunits Nav1.7 and Nav1.8.

    PubMed

    Schlüter, Friederike; Leffler, Andreas

    2016-10-01

    Voltage-gated Na(+) channels regulate neuronal excitability by generating the upstroke of action potentials. The α-subunits Nav1.7 and Nav1.8 are required for normal function of sensory neurons and thus for peripheral pain processing, but also for an increased excitability leading to an increased pain sensitivity under several conditions associated with oxidative stress. While little is known about the direct effects of oxidants on Nav1.7 and Nav1.8, a recent study on mouse dorsal root ganglion neurons suggested that oxidant-induced alterations of nociceptor excitability are primarily driven by Nav1.8. Here we performed whole-cell patch clamp recordings to explore how oxidation modulates functional properties of recombinant Nav1.7 and Nav1.8 channels. The strong oxidant chloramine-T (ChT) at 100 and 500µM induced a shift of the voltage-dependency of activation towards more hyperpolarized potentials. While fast inactivation was stabilized by 100µM ChT, it was partially removed by 500µM ChT on both α-subunits (Nav1.7oxidation promotes gating of Nav1.7 and Nav1.8 by reducing the threshold for activation and by abrogating fast inactivation. The resulting persistent currents are regulated by slow inactivation and appear to be more prominent for Nav1.8 as compared to Nav1.7.

  2. Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Chen, Jone F.; Chang, Chun-Po; Liu, Yu Ming; Tsai, Yan-Lin; Hsu, Hao-Tang; Chen, Chih-Yuan; Hwang, Hann-Ping

    2016-01-01

    In this study, off-state breakdown voltage (VBD) and hot-carrier-induced degradation in high-voltage n-type metal-oxide-semiconductor transistors with various BF2 implantation doses in the n- drift region are investigated. Results show that a higher BF2 implantation dose results in a higher VBD but leads to a greater hot-carrier-induced device degradation. Experimental data and technology computer-aided design simulations suggest that the higher VBD is due to the suppression of gate-induced drain current. On the other hand, the greater hot-carrier-induced device degradation can be explained by a lower net donor concentration and a different current-flow path, which is closer to the Si-SiO2 interface.

  3. Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

    NASA Astrophysics Data System (ADS)

    Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

    2012-06-01

    The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

  4. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper.

  5. Electric field-induced transport modulation in VO{sub 2} FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    SciTech Connect

    Wei, Tingting; Kanki, Teruo E-mail: h-tanaka@sanken.osaka-u.ac.jp; Chikanari, Masashi; Tanaka, Hidekazu E-mail: h-tanaka@sanken.osaka-u.ac.jp; Fujiwara, Kohei

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta{sub 2}O{sub 5}/organic parylene-C hybrid dielectric-gated VO{sub 2} thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO{sub 2} through the electrostatic field-induced transport modulation.

  6. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  7. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  8. Hypoxic increase in nitric oxide generation of rat sensory neurons requires activation of mitochondrial complex II and voltage-gated calcium channels.

    PubMed

    Henrich, M; Paddenberg, R; Haberberger, R V; Scholz, A; Gruss, M; Hempelmann, G; Kummer, W

    2004-01-01

    Recently, we have demonstrated that sensory neurons of rat lumbar dorsal root ganglia (DRG) respond to hypoxia with an activation of endothelial nitric oxide (NO) synthase (eNOS) resulting in enhanced NO production associated with mitochondria which contributes to resistance against hypoxia. Extracellular calcium is essential to this effect. In the present study on rat DRG slices, we set out to determine what types of calcium channels operate under hypoxia, and which upstream events contribute to their activation, thereby focusing upon mitochondrial complex II. Both the metallic ions Cd2+ and Ni2+, known to inhibit voltage-gated calcium channels and T-type channels, respectively, and verapamil and nifedipine, typical blocker of L-type calcium channels completely prevented the hypoxic neuronal NO generation. Inhibition of complex II by thenoyltrifluoroacetone at the ubiquinon binding site or by 3-nitropropionic acid at the substrate binding site largely diminished hypoxic-induced NO production while having an opposite effect under normoxia. An additional blockade of voltage-gated calcium channels entirely abolished the hypoxic response. The complex II inhibitor malonate inhibited both normoxic and hypoxic NO generation. These data show that complex II activity is required for increased hypoxic NO production. Since succinate dehydrogenase activity of complex II decreased at hypoxia, as measured by histochemistry and densitometry, we propose a hypoxia-induced functional switch of complex II from succinate dehydrogenase to fumarate reductase, which subsequently leads to activation of voltage-gated calcium channels resulting in increased NO production by eNOS.

  9. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-01

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  10. Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks.

    PubMed

    Tang, Kechao; Meng, Andrew C; Droopad, Ravi; McIntyre, Paul C

    2016-11-09

    Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (<2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.

  11. Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides

    NASA Astrophysics Data System (ADS)

    Jiao, C.; Ahyi, A. C.; Dhar, S.; Morisette, D.; Myers-Ward, R.

    2017-04-01

    We report results on the interface trap density ( D it) of 4H- and 6H-SiC metal-oxide-semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C- ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C- V- or G- ω-based methods, the C- ψ s method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density ( N it) integrated from the C- ψ s method is several times that obtained from the high-low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal-oxide-semiconductor field-effect transistor (MOSFET) channels.

  12. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  13. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  14. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  15. Hafnium zirconate gate dielectric for advanced gate stack applications

    NASA Astrophysics Data System (ADS)

    Hegde, R. I.; Triyoso, D. H.; Samavedam, S. B.; White, B. E.

    2007-04-01

    We report on the development of a hafnium zirconate (HfZrO4) alloy gate dielectric for advanced gate stack applications. The HfZrO4 and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. The HfZrO4 material properties were examined and compared with those of HfO2 by a wide variety of analytical methods. The dielectric properties, device performance, and reliability of HfZrO4 were investigated by fabricating HfZrO4/tantalum carbide (TaxCy) metal-oxide-semiconductor field effect transistor. The HfZrO4 dielectric film has smaller band gap, smaller and more uniform grains, less charge traps, and more uniform film quality than HfO2. The HfZrO4 dielectric films exhibited good thermal stability with silicon. Compared to HfO2, the HfZrO4 gate dielectric showed lower capacitance equivalent thickness value, higher transconductance, less charge trapping, higher drive current, lower threshold voltage (Vt), reduced capacitance-voltage (C-V ) hysteresis, lower interface state density, superior wafer level thickness uniformity, and longer positive bias temperature instability lifetime. Incorporation of zirconium dioxide (ZrO2) into HfO2 enhances the dielectric constant (k ) of the resulting HfZrO4 which is associated with structural phase transformation from mainly monoclinic to tetragonal. The tetragonal phase increases the k value of HfZrO4 dielectric to a large value as predicted. The improved device characteristics are attributed to less oxygen vacancy in the fine grained microstructure of HfZrO4 films.

  16. Reliability of proton NMR spectroscopy for the assessment of frying oil oxidation

    Technology Transfer Automated Retrieval System (TEKTRAN)

    Although there are many analytical methods developed to assess oxidation of edible oil, it is still common to see a lack of consistency in results from different methods. This inconsistency is expected since there are numerous oxidation products and any analytical method measuring only one kind of o...

  17. Fabrication of a metal-oxide-semiconductor-type capacitive microtip array using SiO2 or HfO2 gate insulators

    NASA Astrophysics Data System (ADS)

    Kim, Kyung-Min; Choi, Byung Joon; Kim, Seong Keun; Hwang, Cheol Seong

    2004-11-01

    Capacitive tip arrays having a metal-insulator-semiconductor capacitor structure were fabricated using thermally oxidized SiO2 or atomic-layer-deposited HfO2 gate dielectric films for their application to scanning-probe-array-type memory devices. The SiO2 film showed a nonuniform thickness distribution over the flat and tip areas of the arrays owing to the different oxidation speeds of the flat and tip Si surfaces. This resulted in a smaller sensing margin of the device. However, the high-dielectric HfO2 film showed not only a higher capacitance value but also a more uniform growth behavior over the whole area, which would result in a better device performance. The capacitance-voltage characteristics of both devices coincide well with the simulation results based on conventional metal-insulator-semiconductor theories.

  18. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  19. Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

    PubMed

    Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

    2017-03-01

    For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm(2)), insulating property (leakage current densities <10(-7) A/cm(2)), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

  20. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments.

  1. Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal-Oxide-Semiconductor Technology

    NASA Astrophysics Data System (ADS)

    Han, Jin-Ping; Shimizu, Takashi; Pan, Li-Hong; Voelker, Moritz; Bernicot, Christophe; Arnaud, Franck; Mocuta, Anda; Stahrenberg, Knut; Azuma, Atsushi; Eller, Manfred; Yang, Guoyong; Jaeger, Daniel; Zhuang, Haoren; Miyashita, Katsura; Stein, Kenneth; Nair, Deleep; Hoo Park, Jae; Kohler, Sabrina; Hamaguchi, Masafumi; Li, Weipeng; Kim, Kisang; Chanemougame, Daniel; Kim, Nam Sung; Uchimura, Sadaharu; Tsutsui, Gen; Wiedholz, Christian; Miyake, Shinich; van Meer, Hans; Liang, Jewel; Ostermayr, Martin; Lian, Jenny; Celik, Muhsin; Donaton, Ricardo; Barla, Kathy; Na, MyungHee; Goto, Yoshiro; Sherony, Melanie; Johnson, Frank S.; Wachnik, Richard; Sudijono, John; Kaste, Ed; Sampson, Ron; Ku, Ja-Hum; Steegen, An; Neumueller, Walter

    2011-04-01

    High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance Gm, conductance Gds, Gm/Id, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., Ion-Ioff, Ioff-Vtsat, DIBL, Cjswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

  2. Characterization of ALD Beryllium Oxide as a Potential High- k Gate Dielectric for Low-Leakage AlGaN/GaN MOSHEMTs

    NASA Astrophysics Data System (ADS)

    Johnson, Derek W.; Yum, Jung Hwan; Hudnall, Todd W.; Mushinski, Ryan M.; Bielawski, Christopher W.; Roberts, John C.; Wang, Wei-E.; Banerjee, Sanjay K.; Harris, H. Rusty

    2014-01-01

    The chemical and electrical characteristics of atomic layer deposited (ALD) beryllium oxide (BeO) on GaN were studied via x-ray photoelectron spectroscopy, current-voltage, and capacitance-voltage measurements and compared with those of ALD Al2O3 and HfO2 on GaN. Radiofrequency (RF) and power electronics based on AlGaN/GaN high-electron-mobility transistors are maturing rapidly, but leakage current reduction and interface defect ( D it) minimization remain heavily researched. BeO has received recent attention as a high- k gate dielectric due to its large band gap (10.6 eV) and thermal stability on InGaAs and Si, but little is known about its performance on GaN. Unintentionally doped GaN was cleaned in dilute aqueous HCl immediately prior to BeO deposition (using diethylberyllium and H2O precursors). Formation of an interfacial layer was observed in as-deposited samples, similar to the layer formed during ALD HfO2 deposition on GaN. Postdeposition anneal (PDA) at 700°C and 900°C had little effect on the observed BeO binding state, confirming the strength of the bond, but led to increased Ga oxide formation, indicating the presence of unincorporated oxygen in the dielectric. Despite the interfacial layer, gate leakage current of 1.1 × 10-7 A/cm2 was realized, confirming the potential of ALD BeO for use in low-leakage AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors.

  3. Ratiometric Time-Gated Luminescence Probe for Nitric Oxide Based on an Apoferritin-Assembled Lanthanide Complex-Rhodamine Luminescence Resonance Energy Transfer System.

    PubMed

    Tian, Lu; Dai, Zhichao; Liu, Xiangli; Song, Bo; Ye, Zhiqiang; Yuan, Jingli

    2015-11-03

    Using apoferritin (AFt) as a carrier, a novel ratiometric luminescence probe based on luminescence resonance energy transfer (LRET) between a Tb(3+) complex (PTTA-Tb(3+)) and a rhodamine derivative (Rh-NO), PTTA-Tb(3+)@AFt-Rh-NO, has been designed and prepared for the specific recognition and time-gated luminescence detection of nitric oxide (NO) in living samples. In this LRET probe, PTTA-Tb(3+) encapsulated in the core of AFt is the energy donor, and Rh-NO, a NO-responsive rhodamine derivative, bound on the surface of AFt is the energy acceptor. The probe only emits strong Tb(3+) luminescence because the emission of rhodamine is switched off in the absence of NO. Upon reaction with NO, accompanied by the turn-on of rhodamine emission, the LRET from Tb(3+) complex to rhodamine occurs, which results in the remarkable increase and decrease of the long-lived emissions of rhodamine and PTTA-Tb(3+), respectively. After the reaction, the intensity ratio of rhodamine emission to Tb(3+) emission, I565/I539, is ∼24.5-fold increased, and the dose-dependent enhancement of I565/I539 shows a good linearity in a wide concentration range of NO. This unique luminescence response allowed PTTA-Tb(3+)@AFt-Rh-NO to be conveniently used as a ratiometric probe for the time-gated luminescence detection of NO with I565/I539 as a signal. Taking advantages of high specificity and sensitivity of the probe as well as its good water-solubility, biocompatibility, and cell membrane permeability, PTTA-Tb(3+)@AFt-Rh-NO was successfully used for the luminescent imaging of NO in living cells and Daphnia magna. The results demonstrated the efficacy of the probe and highlighted it's advantages for the ratiometric time-gated luminescence bioimaging application.

  4. Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

    NASA Astrophysics Data System (ADS)

    Lai, Kafai; Hao, Ming-Yin; Chen, Wei-Ming; Lee, Jack C.

    1994-09-01

    A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

  5. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    PubMed Central

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  6. Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

    PubMed

    Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

    2016-01-27

    We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

  7. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect

    Yang, Xu; Zeng, Zhen-Hua; Wang, Sheng-Kai E-mail: xzhang62@aliyun.com Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang E-mail: xzhang62@aliyun.com; Zhang, Xiong E-mail: xzhang62@aliyun.com

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  8. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  9. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  10. Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers.

    PubMed

    Wang, Lin; Chen, Xiaolong; Wang, Yang; Wu, Zefei; Li, Wei; Han, Yu; Zhang, Mingwei; He, Yuheng; Zhu, Chao; Fung, Kwok Kwong; Wang, Ning

    2013-02-07

    We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers.

  11. Dual-Gate Modulation of Carrier Density and Disorder in an Oxide Two-Dimensional Electron System

    SciTech Connect

    Chen, Zhuoyu; Yuan, Hongtao; Xie, Yanwu; Lu, Di; Inoue, Hisashi; Hikita, Yasuyuki; Bell, Christopher; Hwang, Harold Y.

    2016-09-08

    Carrier density and disorder are two crucial parameters that control the properties of correlated two-dimensional electron systems. Furthermore, in order to disentangle their individual contributions to quantum phenomena, independent tuning of these two parameters is required. By utilizing a hybrid liquid/solid electric dual-gate geometry acting on the conducting LaAlO3/SrTiO3 heterointerface, we obtain an additional degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independent from the carrier density. A dual-gate controlled nonlinear Hall effect is a direct manifestation of this profile, which can be quantitatively understood by a Poisson–Schrödinger sub-band model. In particular, the large nonlinear dielectric response of SrTiO3 enables a very wide range of tunable density and disorder, far beyond that for conventional semiconductors. This study provides a broad framework for understanding various reported phenomena at the LaAlO3/SrTiO3 interface.

  12. Dual-Gate Modulation of Carrier Density and Disorder in an Oxide Two-Dimensional Electron System

    DOE PAGES

    Chen, Zhuoyu; Yuan, Hongtao; Xie, Yanwu; ...

    2016-09-08

    Carrier density and disorder are two crucial parameters that control the properties of correlated two-dimensional electron systems. Furthermore, in order to disentangle their individual contributions to quantum phenomena, independent tuning of these two parameters is required. By utilizing a hybrid liquid/solid electric dual-gate geometry acting on the conducting LaAlO3/SrTiO3 heterointerface, we obtain an additional degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independent from the carrier density. A dual-gate controlled nonlinear Hall effect is a direct manifestation of this profile, which can be quantitatively understood by a Poisson–Schrödinger sub-band model. Inmore » particular, the large nonlinear dielectric response of SrTiO3 enables a very wide range of tunable density and disorder, far beyond that for conventional semiconductors. This study provides a broad framework for understanding various reported phenomena at the LaAlO3/SrTiO3 interface.« less

  13. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    SciTech Connect

    Tari, Alireza Lee, Czang-Ho; Wong, William S.

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  14. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  15. GATED PORES IN THE FERRITIN PROTEIN NANOCAGE

    PubMed Central

    Theil, Elizabeth C.; Liu, Xiaofeng S.; Tosha, Takehiko

    2008-01-01

    Synopsis and pictogram: Gated pores in the ferritin family of protein nanocages, illustrated in the pictogram, control transfer of ferrous iron into and out of the cages by regulating contact between hydrated ferric oxide mineral inside the protein cage, and reductants such as FMNH2 on the outside. The structural and functional homology between the gated ion channel proteins in inaccessible membranes and gated ferritin pores in the stable, water soluble nanoprotein, make studies of ferritin pores models for gated pores in many ion channel proteins. Properties of ferritin gated pores, which control rates of FMNH2 reduction of ferric iron in hydrated oxide minerals inside the protein nanocage, are discussed in terms of the conserved pore gate residues (arginine 72-apspartate 122 and leucine 110-leucine 134), of pore sensitivity to heat at temperatures 30 °C below that of the nanocage itself, and of pore sensitivity to physiological changes in urea (1–10 mM). Conditions which alter ferritin pore structure/function in solution, coupled with the high evolutionary conservation of the pore gates, suggest the presence of molecular regulators in vivo that recognize the pore gates and hold them either closed or open, depending on biological iron need. The apparent homology between ferrous ion transport through gated pores in the ferritin nanocage and ion transport through gated pores in ion channel proteins embedded in cell membranes, make studies of water soluble ferritin and the pore gating folding/unfolding a useful model for other gated pores. PMID:19262678

  16. Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Gu, J. J.; Wu, Y. Q.; Ye, P. D.

    2011-03-01

    Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III-V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III-V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGaAs MOSFET without sulfur passivation, featuring optimized threshold voltage and negligible off-state degradation.

  17. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  18. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  19. Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Kwon, Jang Yeon; Kyeong Jeong, Jae

    2015-02-01

    This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

  20. Designing interlayers to improve the mechanical reliability of transparent conductive oxide coatings on flexible substrates

    SciTech Connect

    Kim, Eun-Hye; Yang, Chan-Woo; Park, Jin-Woo

    2012-05-01

    In this study, we investigate the effect of interlayers on the mechanical properties of transparent conductive oxide (TCO) on flexible polymer substrates. Indium tin oxide (ITO), which is the most widely used TCO film, and Ti, which is the most widely used adhesive interlayer, are selected as the coating and the interlayer, respectively. These films are deposited on the polymer substrates using dc-magnetron sputtering to achieve varying thicknesses. The changes in the following critical factors for film cracking and delamination are analyzed: the internal stress ({sigma}{sup i}) induced in the coatings during deposition using a white light interferometer, the crystallinity using a transmission electron microscope, and the surface roughness of ITO caused by the interlayer using an atomic force microscope. The resistances to the cracking and delamination of ITO are evaluated using a fragmentation test. Our tests and analyses reveal the important role of the interlayers, which significantly reduce the compressive {sigma}{sup i} that is induced in the ITO and increase the resistance to the buckling delamination of the ITO. However, the relaxation of {sigma}{sup i} is not beneficial to cracking because there is less compensation for the external tension as {sigma}{sup i} further decreases. Based on these results, the microstructural control is revealed as a more influential factor than {sigma}{sup i} for improving crack resistance.

  1. Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

    NASA Astrophysics Data System (ADS)

    Han, In-Shik; Kwon, Hyuk-Min; Bok, Jung-Deuk; Kwon, Sung-Kyu; Jung, Yi-Jung; Choi, Woon-il; Choi, Deuk-Sung; Lim, Min-Gyu; Chung, Yi-Sun; Lee, Jung-Hwan; Lee, Ga-Won; Lee, Hi-Deok

    2011-10-01

    In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID-RTS) noise shows similar values (70-78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

  2. The reliability and predictive ability of a biomarker of oxidative DNA damage on functional outcomes after stroke rehabilitation.

    PubMed

    Hsieh, Yu-Wei; Lin, Keh-Chung; Korivi, Mallikarjuna; Lee, Tsong-Hai; Wu, Ching-Yi; Wu, Kuen-Yuh

    2014-04-16

    We evaluated the reliability of 8-hydroxy-2'-deoxyguanosine (8-OHdG), and determined its ability to predict functional outcomes in stroke survivors. The rehabilitation effect on 8-OHdG and functional outcomes were also assessed. Sixty-one stroke patients received a 4-week rehabilitation. Urinary 8-OHdG levels were determined by liquid chromatography-tandem mass spectrometry. The test-retest reliability of 8-OHdG was good (interclass correlation coefficient=0.76). Upper-limb motor function and muscle power determined by the Fugl-Meyer Assessment (FMA) and Medical Research Council (MRC) scales before rehabilitation showed significant negative correlation with 8-OHdG (r=-0.38, r=-0.30; p<0.05). After rehabilitation, we found a fair and significant correlation between 8-OHdG and FMA (r=-0.34) and 8-OHdG and pain (r=0.26, p<0.05). Baseline 8-OHdG was significantly correlated with post-treatment FMA, MRC, and pain scores (r=-0.34, -0.31, and 0.25; p<0.05), indicating its ability to predict functional outcomes. 8-OHdG levels were significantly decreased, and functional outcomes were improved after rehabilitation. The exploratory study findings conclude that 8-OHdG is a reliable and promising biomarker of oxidative stress and could be a valid predictor of functional outcomes in patients. Monitoring of behavioral indicators along with biomarkers may have crucial benefits in translational stroke research.

  3. Short-Term Ketamine Treatment Decreases Oxidative Stress Without Influencing TRPM2 and TRPV1 Channel Gating in the Hippocampus and Dorsal Root Ganglion of Rats.

    PubMed

    Demirdaş, Arif; Nazıroğlu, Mustafa; Övey, Ishak Suat

    2017-01-01

    Calcium ions (Ca(2+)) are important second messengers in neurons. Ketamine (KETAM) is an anesthetic and analgesic, with psychotomimetic effects and abuse potential. KETAM modulates the entry of Ca(2+) in neurons through glutamate receptors, but its effect on transient receptor potential melastatin 2 (TRPM2) and transient receptor potential vanilloid 1 (TRPV1) channels has not been clarified. This study investigated the short-term effects of KETAM on oxidative stress and TRPM2 and TRPV1 channel gating in hippocampal and dorsal root ganglion (DRG) neurons of rats. Freshly isolated hippocampal and DRG neurons were incubated for 24 h with KETAM (0.3 mM). The TRPM2 channel antagonist, N-(p-amylcinnamoyl)anthranilic acid (ACA), inhibited cumene hydroperoxide and ADP-ribose-induced TRPM2 currents in the neurons, and capsazepine (CPZ) inhibited capsaicin-induced TRPV1 currents. The TRPM2 and TRPV1 channel current densities and intracellular free calcium ion concentration of the neurons were lower in the neurons exposed to ACA and CPZ compared to the control neurons, respectively. However, the values were not further decreased by the KETAM + CPZ and KETAM + ACA treatments. KETAM decreased lipid peroxidation levels in the neurons but increased glutathione peroxidase activity. In conclusion, short-term KETAM treatment decreased oxidative stress levels but did not seem to influence TRPM2- and TRPV1-mediated Ca(2+) entry.

  4. Automatically closing swing gate closure assembly

    DOEpatents

    Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

    1988-01-01

    A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

  5. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    NASA Astrophysics Data System (ADS)

    Flewitt, A. J.; Powell, M. J.

    2014-04-01

    It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 106-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions

  6. Electron transporting water-gated thin film transistors

    NASA Astrophysics Data System (ADS)

    Al Naim, Abdullah; Grell, Martin

    2012-10-01

    We demonstrate an electron-transporting water-gated thin film transistor, using thermally converted precursor-route zinc-oxide (ZnO) intrinsic semiconductors with hexamethyldisilazene (HMDS) hydrophobic surface modification. Water gated HMDS-ZnO thin film transistors (TFT) display low threshold and high electron mobility. ZnO films constitute an attractive alternative to organic semiconductors for TFT transducers in sensor applications for waterborne analytes. Despite the use of an electrolyte as gate medium, the gate geometry (shape of gate electrode and distance between gate electrode and TFT channel) is relevant for optimum performance of water-gated TFTs.

  7. Electrostatic Gating of Ultrathin Films

    NASA Astrophysics Data System (ADS)

    Goldman, A. M.

    2014-07-01

    Electrostatic gating of ultrathin films can be used to modify electronic and magnetic properties of materials by effecting controlled alterations of carrier concentration while, in principle, not changing the level of disorder. As such, electrostatic gating can facilitate the development of novel devices and can serve as a means of exploring the fundamental properties of materials in a manner far simpler than is possible with the conventional approach of chemical doping. The entire phase diagram of a compound can be traversed by changing the gate voltage. In this review, we survey results involving conventional field effect devices as well as more recent progress, which has involved structures that rely on electrochemical configurations such as electric double-layer transistors. We emphasize progress involving thin films of oxide materials such as high-temperature superconductors, magnetic oxides, and oxides that undergo metal-insulator transitions.

  8. Day to Day Variability and Reliability of Blood Oxidative Stress Markers within a Four-Week Period in Healthy Young Men

    PubMed Central

    Goldfarb, A. H.; Garten, R. S.; Waller, J.; Labban, J. D.

    2014-01-01

    The present study aimed to determine the day to day variability and reliability of several blood oxidative stress markers at rest in a healthy young cohort over a four-week period. Twelve apparently healthy resistance trained males (24.6 ± 3.0 yrs) were tested over 7 visits within 4 weeks with at least 72 hrs between visits at the same time of day. Subjects rested 30 minutes prior to blood being obtained by vacutainer. Results. The highest IntraClass correlations (ICC's) were obtained for protein carbonyls (PC) and oxygen radical absorbance capacity (ORAC) (PC = 0.785 and ORAC = 0.780). Cronbach's α reliability score for PC was 0.967 and for ORAC was 0.961. The ICC's for GSH, GSSG, and the GSSG/TGH ratio ICC were 0.600, 0.573, and 0.570, respectively, with Cronbach's α being 0.913, 0.904, and 0.903, respectively. Xanthine oxidase ICC was 0.163 and Cronbach's α was 0.538. Conclusions. PC and ORAC demonstrated good to excellent reliability while glutathione factors had poor to excellent reliability. Xanthine oxidase showed poor reliability and high variability. These results suggest that the PC and ORAC markers were the most stable and reliable oxidative stress markers in blood and that daily changes across visits should be considered when interpreting resting blood oxidative stress markers. PMID:26317028

  9. A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1‑ x O2 Gate dielectric and improved electrical and hysteresis performance

    NASA Astrophysics Data System (ADS)

    Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

    2017-04-01

    The use of co-sputtered zirconium silicon oxide (Zr x Si1‑ x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0–150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1‑ x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V‑1 s‑1).

  10. Properties of high k gate dielectric gadolinium oxide deposited on Si (1 0 0) by dual ion beam deposition (DIBD)

    NASA Astrophysics Data System (ADS)

    Zhou, Jian-Ping; Chai, Chun-Lin; Yang, Shao-Yan; Liu, Zhi-Kai; Song, Shu-Lin; Li, Yan-Li; Chen, Nuo-Fu

    2004-09-01

    Gadolinium oxide thin films have been prepared on silicon (1 0 0) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation (4 bar 0 2) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (2 0 2), and finally, the cubic structure appeared at the substrate temperature of 700 °C, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented.

  11. Consecutive Gated Injection-Based Microchip Electrophoresis for Simultaneous Quantitation of Superoxide Anion and Nitric Oxide in Single PC-12 Cells.

    PubMed

    Li, Lu; Li, Qingling; Chen, Peilin; Li, Zhongyi; Chen, Zhenzhen; Tang, Bo

    2016-01-05

    As important reactive oxygen species (ROS) and reactive nitrogen species (RNS), cellular superoxide anion (O2(•-)) and nitric oxide (NO) play significant roles in numerous physiological and pathological processes. Cellular O2(•-) and NO also have a close relationship and always interact with each other. Thus, the simultaneous detection of intracellular O2(•-) and NO, especially at the single-cell level, is important. In this paper, we present a novel method to simultaneously detect and quantify O2(•-) and NO in single cells using microchip electrophoresis based on a new consecutive gated injection method. This novel injection method achieved consecutive manipulation of single cells, guaranteeing an almost constant volumetric flow rate and thus good quantitative reproducibility. After cellular content separation by microchip electrophoresis and detection by laser-induced fluorescence (MCE-LIF), O2(•-) and NO in single PC-12 cells were simultaneously quantified in an automated fashion. This is the first report of consecutive absolute quantitation at the single-cell level. The quantitative results obtained from single cells is beneficial for deep understanding of the biological roles of cellular O2(•-) and NO. This new method constitutes a consecutive, accurate way to study the synergistic function of O2(•-) and NO and other biomolecules in various biological events at the single-cell level.

  12. Circadian phase-dependent effect of nitric oxide on L-type voltage-gated calcium channels in avian cone photoreceptors

    PubMed Central

    Ko, Michael L.; Shi, Liheng; Huang, Cathy Chia-Yu; Grushin, Kirill; Park, So-Young; Ko, Gladys Y.-P.

    2014-01-01

    Nitric oxide (NO) plays an important role in phase-shifting of circadian neuronal activities in the suprachiasmatic nucleus and circadian behavior activity rhythms. In the retina, NO production is increased in a light-dependent manner. While endogenous circadian oscillators in retinal photoreceptors regulate their physiological states, it is not clear whether NO also participates in the circadian regulation of photoreceptors. In the present study, we demonstrate that NO is involved in the circadian phase-dependent regulation of L-type voltage-gated calcium channels (L-VGCCs). In chick cone photoreceptors, the L-VGCCα1 subunit expression and the maximal L-VGCC currents are higher at night, and both Ras-MAPK (mitogen-activated protein kinase)-Erk (extracellular-signal-regulated kinase) and Ras-phosphatidylinositol 3 kinase (PI3K)-protein kinase B (Akt) are part of the circadian output pathways regulating L-VGCCs. The NO-cGMP-protein kinase G (PKG) pathway decreases L-VGCCα1 subunit expression and L-VGCC currents at night, but not during the day, and exogenous NO donor or cGMP decreases the phosphorylation of Erk and Akt at night. The protein expression of neural NO synthase (nNOS) is also under circadian control, with both nNOS and NO production being higher during the day. Taken together, NO/cGMP/PKG signaling is involved as part of the circadian output pathway to regulate L-VGCCs in cone photoreceptors. PMID:23895452

  13. Multiple-stimuli responsive bioelectrocatalysis based on reduced graphene oxide/poly(N-isopropylacrylamide) composite films and its application in the fabrication of logic gates.

    PubMed

    Wang, Lei; Lian, Wenjing; Yao, Huiqin; Liu, Hongyun

    2015-03-11

    In the present work, reduced graphene oxide (rGO)/poly(N-isopropylacrylamide) (PNIPAA) composite films were electrodeposited onto the surface of Au electrodes in a fast and one-step manner from an aqueous mixture of a graphene oxide (GO) dispersion and N-isopropylacrylamide (NIPAA) monomer solutions. Reflection-absorption infrared (IR) and Raman spectroscopies were employed to characterize the successful construction of the rGO/PNIPAA composite films. The rGO/PNIPAA composite films exhibited reversible potential-, pH-, temperature-, and sulfate-sensitive cyclic voltammetric (CV) on-off behavior to the electroactive probe ferrocenedicarboxylic acid (Fc(COOH)2). For instance, after the composite films were treated at -0.7 V for 7 min, the CV responses of Fc(COOH)2 at the rGO/PNIPAA electrodes were quite large at pH 8.0, exhibiting the on state. However, after the films were treated at 0 V for 30 min, the CV peak currents became much smaller, demonstrating the off state. The mechanism of the multiple-stimuli switchable behaviors for the system was investigated not only by electrochemical methods but also by scanning electron microscopy and X-ray photoelectron spectroscopy. The potential-responsive behavior for this system was mainly attributed to the transformation between rGO and GO in the films at different potentials. The film system was further used to realize multiple-stimuli responsive bioelectrocatalysis of glucose catalyzed by the enzyme of glucose oxidase and mediated by the electroactive probe of Fc(COOH)2 in solution. On the basis of this, a four-input enabled OR (EnOR) logic gate network was established.

  14. Prediction of Reliable Metal-PH₃ Bond Energies for Ni, Pd, and Pt in the 0 and +2 Oxidation States

    SciTech Connect

    Craciun, Raluca; Vincent, Andrew J.; Shaughnessy, Kevin H.; Dixon, David A.

    2010-06-21

    Phosphine-based catalysts play an important role in many metal-catalyzed carbon-carbon bond formation reactions yet reliable values of their bond energies are not available. We have been studying homogeneous catalysts consisting of a phosphine bonded to a Pt, Pd, or Ni. High level electronic structure calculations at the CCSD(T)/complete basis set level were used to predict the M-PH₃ bond energy (BE) for the 0 and +2 oxidation states for M=Ni, Pd, and Pt. The calculated bond energies can then be used, for example, in the design of new catalyst systems. A wide range of exchange-correlation functionals were also evaluated to assess the performance of density functional theory (DFT) for these important bond energies. None of the DFT functionals were able to predict all of the M-PH3 bond energies to within 5 kcal/mol, and the best functionals were generalized gradient approximation functionals in contrast to the usual hybrid functionals often employed for main group thermochemistry.

  15. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    PubMed Central

    Wang, A.L.; Gold, J.M.; Tompkins, N.; Heymann, M.; Harrington, K.I.; Fraden, S.

    2016-01-01

    We investigate the Belousov–Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment. PMID:27168916

  16. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    NASA Astrophysics Data System (ADS)

    Wang, A. L.; Gold, J. M.; Tompkins, N.; Heymann, M.; Harrington, K. I.; Fraden, S.

    2016-02-01

    We investigate the Belousov-Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment.

  17. Buffer layer engineering on graphene via various oxidation methods for atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Takahashi, Nobuaki; Nagashio, Kosuke

    2016-12-01

    The integration of a high-k oxide on graphene using atomic layer deposition requires an electrically reliable buffer layer. In this study, Y was selected as the buffer layer due to its highest oxidation ability among the rare-earth elements, and various oxidation methods (atmospheric, and high-pressure O2 and ozone annealing) were applied to the Y metal buffer layer. By optimizing the oxidation conditions of the top-gate insulator, we successfully improved the capacitance of the top gate Y2O3 insulator and demonstrated a large I on/I off ratio for bilayer graphene under an external electric field.

  18. On the applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells

    SciTech Connect

    Lara-Curzio, Edgar; Radovic, Miladin; Luttrell, Claire R

    2016-01-01

    The applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells (SOFC) is investigated by measuring the failure rate of Ni-YSZ when subjected to a temperature gradient and comparing it with that predicted using the Ceramics Analysis and Reliability Evaluation of Structures (CARES) code. The use of a temperature gradient to induce stresses was chosen because temperature gradients resulting from gas flow patterns generate stresses during SOFC operation that are the likely to control the structural reliability of cell components The magnitude of the predicted failure rate was found to be comparable to that determined experimentally, which suggests that such probabilistic analyses are appropriate for predicting the structural reliability of materials and components for SOFCs. Considerations for performing more comprehensive studies are discussed.

  19. Side Gate Tunable Josephson Junctions at the LaAlO3/SrTiO3 Interface

    PubMed Central

    2017-01-01

    Novel physical phenomena arising at the interface of complex oxide heterostructures offer exciting opportunities for the development of future electronic devices. Using the prototypical LaAlO3/SrTiO3 interface as a model system, we employ a single-step lithographic process to realize gate-tunable Josephson junctions through a combination of lateral confinement and local side gating. The action of the side gates is found to be comparable to that of a local back gate, constituting a robust and efficient way to control the properties of the interface at the nanoscale. We demonstrate that the side gates enable reliable tuning of both the normal-state resistance and the critical (Josephson) current of the constrictions. The conductance and Josephson current show mesoscopic fluctuations as a function of the applied side gate voltage, and the analysis of their amplitude enables the extraction of the phase coherence and thermal lengths. Finally, we realize a superconducting quantum interference device in which the critical currents of each of the constriction-type Josephson junctions can be controlled independently via the side gates. PMID:28071920

  20. Effect of Oxidation Temperature on Physical and Electrical Properties of Sm2O3 Thin-Film Gate Oxide on Si Substrate

    NASA Astrophysics Data System (ADS)

    Goh, Kian Heng; Haseeb, A. S. M. A.; Wong, Yew Hoong

    2016-10-01

    Thermal oxidation of 150-nm sputtered pure samarium metal film on silicon substrate has been carried out in oxygen ambient at various temperatures (600°C to 900°C) for 15 min and the effect of the oxidation temperature on the structural, chemical, and electrical properties of the resulting Sm2O3 layers investigated. The crystallinity of the Sm2O3 films and the existence of an interfacial layer were evaluated by x-ray diffraction (XRD) analysis, Fourier-transform infrared (FTIR) spectroscopy, and Raman analysis. The crystallite size and microstrain of Sm2O3 were estimated by Williamson-Hall (W-H) plot analysis, with comparison of the former with the crystallite size of Sm2O3 as calculated using the Scherrer equation. High-resolution transmission electron microscopy (HRTEM) with energy-dispersive x-ray (EDX) spectroscopy analysis was carried out to investigate the cross-sectional morphology and chemical distribution of selected regions. The activation energy or growth rate of each stacked layer was calculated from Arrhenius plots. The surface roughness and topography of the Sm2O3 layers were examined by atomic force microscopy (AFM) analysis. A physical model based on semipolycrystalline nature of the interfacial layer is suggested and explained. Results supporting such a model were obtained by FTIR, XRD, Raman, EDX, and HRTEM analyses. Electrical characterization revealed that oxidation temperature at 700°C yielded the highest breakdown voltage, lowest leakage current density, and highest barrier height value.

  1. Evolution of the gate current in 32 nm MOSFETs under irradiation

    NASA Astrophysics Data System (ADS)

    Palumbo, F.; Debray, M.; Vega, N.; Quinteros, C.; Kalstein, A.; Guarin, F.

    2016-05-01

    Radiation induced currents on single 32 nm MOSFET transistors have been studied using consecutive runs of 16O at 25 MeV. The main feature is the generation of current peaks - in the gate and channel currents - due to the collection of the electro-hole pairs generated by the incident radiation runs. It has been observed that the incident ions cause damage in the dielectric layer and in the substrate affecting the collection of carriers, and hence the radiation-induced current peaks. It has been find out a decrease of the current peak due to the increase of the series resistance by non-ionizing energy loss in the semiconductor substrate, and an increase of the leakage current due to defects in the gate oxide by ionizing energy loss. For low levels of damage in the gate oxide, the main feature is the shift of the VTH. Hot carriers heated by the incident radiation in the depletion region and injected in the gate oxide cause the change of the VTH due to electron or hole trapping for n- or p-channel respectively. The overall results illustrate that these effects must be taken into consideration for an accurate reliability projection.

  2. Nonvolatile floating gate memory containing AgInSbTe-SiO2 nanocomposite layer and capping the HfO2/SiO2 composite blocking oxide layer.

    PubMed

    Chiang, Kuo-Chang; Hsieh, Tsung-Eong

    2012-06-08

    An extremely large memory window shift of about 30.7 V and high charge storage density =2.3 × 10(13) cm(-2) at ± 23 V gate voltage sweep were achieved in the nonvolatile floating gate memory (NFGM) device containing the AgInSbTe (AIST)-SiO(2) nanocomposite as the charge trap layer and HfO(2)/SiO(2) as the blocking oxide layer. Due to the deep trap sites formed by high-density AIST nanocrystals (NCs) in the nanocomposite matrix and the high-barrier-height feature of the composite blocking oxide layer, a good retention property of the device with a charge loss of about 16.1% at ± 15 V gate voltage stress for 10(4) s at the test temperature of 85 °C was observed. In addition to inhibiting the Hf diffusion into the programming layer, incorporation of the SiO(2) layer prepared by plasma-enhanced chemical vapor deposition in the sample provided a good Coulomb blockade effect and allowed significant charge storage in AIST NCs. Analytical results demonstrated the feasibility of an AIST-SiO(2) nanocomposite layer in memory device fabrication with a simplified processing method and post-annealing at a comparatively low temperature of 400 °C in comparison with previous NC-based NFGM studies.

  3. Sliding-gate valve for use with abrasive materials

    DOEpatents

    Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

    1985-01-01

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  4. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  5. Improved electrical properties of Ge metal-oxide-semiconductor capacitors with high-k HfO2 gate dielectric by using La2O3 interlayer sputtered with/without N2 ambient

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Lai, P. T.

    2010-07-01

    The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.

  6. Agomelatine and duloxetine synergistically modulates apoptotic pathway by inhibiting oxidative stress triggered intracellular calcium entry in neuronal PC12 cells: role of TRPM2 and voltage-gated calcium channels.

    PubMed

    Akpinar, Abdullah; Uğuz, Abdülhadi Cihangir; Nazıroğlu, Mustafa

    2014-05-01

    Calcium ion (Ca(2+)) is one of the universal second messengers, which acts in a wide range of cellular processes. Results of recent studies indicated that ROS generated by depression leads to loss of endoplasmic reticulum-Ca(2+) homeostasis, oxidative stress, and apoptosis. Agomelatine and duloxetine are novel antidepressant and antioxidant drugs and may reduce oxidative stress, apoptosis, and Ca(2+) entry through TRPM2 and voltage-gated calcium channels. We tested the effects of agomelatine, duloxetine, and their combination on oxidative stress, Ca(2+) influx, mitochondrial depolarization, apoptosis, and caspase values in the PC-12 neuronal cells. PC-12 neuronal cells were exposed in cell culture and exposed to appropriate non-toxic concentrations and incubation times for agomelatine were determined in the neurons by assessing cell viability. Then PC-12 cells were incubated with agomelatine and duloxetine for 24 h. Treatment of cultured PC-12 cells with agomelatine, duloxetine, and their combination results in a protection on apoptosis, caspase-3, caspase-9, mitochondrial membrane depolarization, cytosolic ROS production, glutathione peroxidase, reduced glutathione, and lipid peroxidation, values. Ca(2+) entry through non-specific TRPM2 channel blocker (2-APB) and voltage-gated Ca(2+) channel blockers (verapamil and diltiazem) was modulated by agomelatine and duloxetine. However, effects of duloxetine on the Ca(2+) entry through TRPM2 channels were higher than in agomelatine. Results of current study suggest that the agomelatine and duloxetine are useful against apoptotic cell death and oxidative stress in PC-12 cells, which seem to be dependent on mitochondrial damage and increased levels of intracellular Ca(2+) through activation of TRPM2 and voltage-gated Ca(2+) channels.

  7. Corticostriatal output gating during selection from working memory.

    PubMed

    Chatham, Christopher H; Frank, Michael J; Badre, David

    2014-02-19

    Convergent evidence suggests that corticostriatal interactions act as a gate to select the input to working memory (WM). However, not all information in WM is relevant for behavior simultaneously. For this reason, a second "output gate" might advantageously govern which contents of WM influence behavior. Here, we test whether frontostriatal circuits previously implicated in input gating also support output gating during selection from WM. fMRI of a hierarchical rule task with dissociable input and output gating demands demonstrated greater lateral prefrontal cortex (PFC) recruitment and frontostriatal connectivity during output gating. Moreover, PFC and striatum correlated with distinct behavioral profiles. Whereas PFC recruitment correlated with mean efficiency of selection from WM, striatal recruitment and frontostriatal interactions correlated with its reliability, as though such dynamics stochastically gate WM's output. These results support the output gating hypothesis, suggesting that contextual representations in PFC influence striatum to select which information in WM drives responding.

  8. Gate stack engineering for GaN lateral power transistors

    NASA Astrophysics Data System (ADS)

    Yang, Shu; Liu, Shenghou; Liu, Cheng; Hua, Mengyuan; Chen, Kevin J.

    2016-02-01

    Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables optimal trade-off between performance and stability; (3) bulk quality and reliability enhancement of the gate dielectric. These gate-stack techniques in terms of new process development and device structure design are valuable to realize highly reliable and competitive GaN power devices.

  9. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    SciTech Connect

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specific contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.

  10. Electrical properties of GaAs metal-oxide-semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal-organic vapor deposition/atomic layer deposition hybrid system

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2015-08-01

    This paper presents a compressive study on the fabrication and optimization of GaAs metal-oxide-semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal-organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance-voltage (C-V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm-2 eV-1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  11. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  12. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  13. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  14. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  15. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  16. Nitric oxide inhibits neuroendocrine CaV1 L-channel gating via cGMP-dependent protein kinase in cell-attached patches of bovine chromaffin cells

    PubMed Central

    Carabelli, Valentina; D'Ascenzo, Marcello; Carbone, Emilio; Grassi, Claudio

    2002-01-01

    Nitric oxide (NO) regulates the release of catecholamines from the adrenal medulla but the molecular targets of its action are not yet well identified. Here we show that the NO donor sodium nitroprusside (SNP, 200 μM) causes a marked depression of the single CaV1 L-channel activity in cell-attached patches of bovine chromaffin cells. SNP action was complete within 3-5 min of cell superfusion. In multichannel patches the open probability (NPo) decreased by ∼60 % between 0 and +20 mV. Averaged currents over a number of traces were proportionally reduced and showed no drastic changes to their time course. In single-channel patches the open probability (Po) at +10 mV decreased by the same amount as that of multichannel patches (∼61 %). Such a reduction was mainly associated with an increased probability of null sweeps and a prolongation of mean shut times, while first latency, mean open time and single-channel conductance were not significantly affected. Addition of the NO scavenger carboxy-PTIO or cell treatment with the guanylate cyclase inhibitor ODQ prevented the SNP-induced inhibition. 8-Bromo-cyclicGMP (8-Br-cGMP; 400 μM) mimicked the action of the NO donor and the protein kinase G blocker KT-5823 prevented this effect. The depressive action of SNP was preserved after blocking the cAMP-dependent up-regulatory pathway with the protein kinase A inhibitor H89. Similarly, the inhibitory action of 8-Br-cGMP proceeded regardless of the elevation of cAMP levels, suggesting that cGMP/PKG and cAMP/PKA act independently on L-channel gating. The inhibitory action of 8-Br-cGMP was also independent of the G protein-induced inhibition of L-channels mediated by purinergic and opiodergic autoreceptors. Since Ca2+ channels contribute critically to both the local production of NO and catecholamine release, the NO/PKG-mediated inhibition of neuroendocrine L-channels described here may represent an important autocrine signalling mechanism for controlling the rate of

  17. Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system.

    PubMed

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M; Avila-García, Alejandro; Vazquez-Acosta, E N; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe(2)O(3) layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  18. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    PubMed Central

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

  19. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  20. DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1977-01-01

    Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

  1. Improvement in performance and reliability with CF4 plasma pretreatment on the buffer oxide layer for low-temperature polysilicon thin-film transistor

    NASA Astrophysics Data System (ADS)

    Fan, Ching-Lin; Lin, Yi-Yan; Yang, Chun-Chieh

    2012-03-01

    This study applies CF4 plasma pretreatment to a buffer oxide layer to improve the performance of low-temperature polysilicon thin-film transistors (LTPS TFTs). Results show that the fluorine atoms piled up at the interface between the bulk channel and buffer oxide layer and accumulated in the bulk channel. The reduction of the trap states density by fluorine passivation can improve the electrical characteristics of the LTPS TFTs. It is found that the threshold voltage reduced from 4.32 to 3.03 V and the field-effect mobility increased from 29.71 to 45.65 cm2 V-1 S-1. In addition, the on current degradation and threshold voltage shift after stressing were significantly improved about 31% and 70%, respectively. We believe that the proposed CF4 plasma pretreatment on the buffer oxide layer can passivate the trap states and avoid the plasma induced damage on the polysilicon channel surface, resulting in the improvement in performance and reliability for LTPS-TFT mass production application on AMOLED displays with critical reliability requirement.

  2. Ferroelectric/Dielectric Double Gate Insulator Spin-Coated Using Barium Titanate Nanocrystals for an Indium Oxide Nanocrystal-Based Thin-Film Transistor.

    PubMed

    Pham, Hien Thu; Yang, Jin Ho; Lee, Don-Sung; Lee, Byoung Hun; Jeong, Hyun-Dam

    2016-03-23

    Barium titanate nanocrystals (BT NCs) were prepared under solvothermal conditions at 200 °C for 24 h. The shape of the BT NCs was tuned from nanodot to nanocube upon changing the polarity of the alcohol solvent, varying the nanosize in the range of 14-22 nm. Oleic acid-passivated NCs showed good solubility in a nonpolar solvent. The effect of size and shape of the BT NCs on the ferroelectric properties was also studied. The maximum polarization value of 7.2 μC/cm(2) was obtained for the BT-5 NC thin film. Dielectric measurements of the films showed comparable dielectric constant values of BT NCs over 1-100 kHz without significant loss. Furthermore, the bottom gate In2O3 NC thin film transistors exhibited outstanding device performance with a field-effect mobility of 11.1 cm(2) V(-1) s(-1) at a low applied gate voltage with BT-5 NC/SiO2 as the gate dielectric. The low-density trapped state was observed at the interface between the In2O3 NC semiconductor and the BT-5 NCs/SiO2 dielectric film. Furthermore, compensation of the applied gate field by an electric dipole-induced dipole field within the BT-5 NC film was also observed.

  3. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Azzah Bte Suleiman, Sumarlina; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal-oxide-semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel-Poole emission at high electric field. This Frenkel-Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel-Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley-Read-Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id∝T-0.37 observed for passivated device, in comparison to Id∝T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  4. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal--Oxide--Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Suleiman, Sumarlina Azzah Bte; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal--oxide--semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel--Poole emission at high electric field. This Frenkel--Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3× 1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel--Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley--Read--Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id\\propto T-0.37 observed for passivated device, in comparison to Id\\propto T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  5. 6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE WORK, AND GATE STOP FROM SOUTHEAST OF NORTHWEST ELEMENTS. - William Enston Home, Entrance Gate, 900 King Street, Charleston, Charleston County, SC

  6. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, GATE PIER, TRUNNION PIN AND GATE GAUGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  7. Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxide-semiconductor field-effect transistors with nitrogen and silicon incorporated HfO2 gate dielectrics

    NASA Astrophysics Data System (ADS)

    Choi, Changhwan; Lee, Jack C.

    2011-02-01

    Negative bias temperature instabilities (NBTIs) of p-channel metal-oxide-semiconductor field-effect-transistor with HfO2, HfOxNy, and HfSiON were investigated. Higher bulk trap generation (ΔNot) is mainly attributed to threshold voltage shift rather than interface trap generation (ΔNit). ΔNit, ΔNot, activation energy (Ea), and lifetime were exacerbated with incorporated nitrogen while improved with adding Si into gate dielectrics. Compared to HfO2, HfOxNy showed worse NBTI due to nitrogen pile-up at Si interface. However, adding Si into HfOxNy placed nitrogen peak profile away from Si/oxide interface and NBTI was reduced. This improvement is ascribed to reduced ΔNot and ΔNit, resulting from less nitrogen at Si interface.

  8. Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun; Bang, Tewook; Choi, Yang-Kyu; Park, Sang-Hee Ko; Choi, Kyung Cheol

    2016-05-01

    We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔVth) was 0 V even after a PBS time (tstress) of 3000 s under a gate voltage (VG) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔVth value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔVth values resulting from PBS quantitatively, the average oxide charge trap density (NT) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher NT resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of NT near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.

  9. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  10. Parallelizable adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Nakago, Kosuke; Hajdušek, Michal; Nakayama, Shojun; Murao, Mio

    2015-12-01

    To investigate how a temporally ordered gate sequence can be parallelized in adiabatic implementations of quantum computation, we modify adiabatic gate teleportation, a model of quantum computation proposed by Bacon and Flammia [Phys. Rev. Lett. 103, 120504 (2009), 10.1103/PhysRevLett.103.120504], to a form deterministically simulating parallelized gate teleportation, which is achievable only by postselection. We introduce a twisted Heisenberg-type interaction Hamiltonian, a Heisenberg-type spin interaction where the coordinates of the second qubit are twisted according to a unitary gate. We develop parallelizable adiabatic gate teleportation (PAGT) where a sequence of unitary gates is performed in a single step of the adiabatic process. In PAGT, numeric calculations suggest the necessary time for the adiabatic evolution implementing a sequence of L unitary gates increases at most as O (L5) . However, we show that it has the interesting property that it can map the temporal order of gates to the spatial order of interactions specified by the final Hamiltonian. Using this property, we present a controlled-PAGT scheme to manipulate the order of gates by a control qubit. In the controlled-PAGT scheme, two differently ordered sequential unitary gates F G and G F are coherently performed depending on the state of a control qubit by simultaneously applying the twisted Heisenberg-type interaction Hamiltonians implementing unitary gates F and G . We investigate why the twisted Heisenberg-type interaction Hamiltonian allows PAGT. We show that the twisted Heisenberg-type interaction Hamiltonian has an ability to perform a transposed unitary gate by just modifying the space ordering of the final Hamiltonian implementing a unitary gate in adiabatic gate teleportation. The dynamics generated by the time-reversed Hamiltonian represented by the transposed unitary gate enables deterministic simulation of a postselected event of parallelized gate teleportation in adiabatic

  11. Adaptive quantum gate-set tomography

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    2013-03-01

    Quantum information hardware needs to be characterized and calibrated. This is the job of quantum state and process tomography, but standard tomographic methods have an Achilles heel: to characterize an unknown process, they rely on a set of absolutely calibrated measurements. But many technologies (e.g., solid-state qubits) admit only a single native measurement basis, and other bases are measured using unitary control. So tomography becomes circular - tomographic protocols are using gates to calibrate themselves! Gate-set tomography confronts this problem head-on and resolves it by treating gates relationally. We abandon all assumptions about what a given gate operation does, and characterize entire universal gate sets from the ground up using only the observed statistics of an [unknown] 2-outcome measurement after various strings of [unknown] gate operations. The accuracy and reliability of the resulting estimate depends critically on which gate strings are used, and benefits greatly from adaptivity. Sandia National Labs is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Dept. of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000

  12. Quantum gate decomposition algorithms.

    SciTech Connect

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  13. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-04

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  14. Investigation of field induced trapping on floating gates

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1975-01-01

    The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

  15. Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, M.; Kim, H.; Phan, A.; Seidleck, C.; LaBel, K.; Pellish, J.; Campola, M.

    2015-01-01

    Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

  16. Protocol Optimisation For Work-Function Measurements Of Metal Gates Using Kelvin Force Microscopy

    SciTech Connect

    Mariolle, D.; Kaja, K.; Bertin, F.; Martinez, E.; Martin, F.; Gassilloud, R.

    2007-09-26

    Currently, the work-functions of metal gates are determined using capacitance-versus-gate-voltage measurements of a dedicated MOS capacitor structure. Alternatively, Kelvin Force Microscopy (KFM) is a promising technique which allows the work-function to be measured with high spatial resolution (<100 nm) coupled with a high sensitivity (10 meV). Nevertheless, before becoming a standard technique, there are still challenges facing a reliable operating protocol such as careful specimen preparation and environmental control to avoid surface artifacts. In the paper we show that the presence of an oxide, confirmed by Auger Electron Spectroscopy (AES), on a WSi{sub x} metallic layer surface have a detrimental effect on the work-function measurement using KFM.

  17. Gated strip proportional detector

    DOEpatents

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  18. Gated strip proportional detector

    DOEpatents

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  19. Range gated imaging experiments using gated intensifiers

    SciTech Connect

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  20. High quality PECVD SiO2 process for recessed MOS-gate of AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Gil; Kim, Hyun-Seop; Seo, Kwang-Seok; Cho, Chun-Hyung; Cha, Ho-Young

    2016-08-01

    A high quality SiO2 deposition process using a plasma enhanced chemical vapor deposition system has been developed for the gate insulator process of normally-off recessed-gate AlGaN/GaN metal-oxide-semiconductor-heterostructure field-effect transistors (MOS-HFETs). SiO2 films were deposited by using SiH4 and N2O mixtures as reactant gases. The breakdown field increased with increasing the N2O flow rate. The optimum SiH4/N2O ratio was 0.05, which resulted in a maximum breakdown field of 11 MV/cm for the SiO2 film deposited on recessed GaN surface. The deposition conditions were optimized as follows; a gas flow rate of SiH4/N2O (=27/540 sccm), a source RF power of 100 W, a pressure of 2 Torr, and a deposition temperature of 350 °C. A fabricated normally-off MOS-HFET exhibited a threshold voltage of 3.2 V, a specific on-resistance of 4.46 mΩ cm2, and a breakdown voltage of 810 V.

  1. Reliability properties of metal-oxide-semiconductor capacitors using LaAlO3 high-k dielectric

    NASA Astrophysics Data System (ADS)

    Yeh, Lingyen; Chang, Ingram Yin-Ku; Chen, Chun-Heng; Lee, Joseph Ya-Min

    2009-10-01

    In this study, metal-oxide-semiconductor (MOS) capacitors with high dielectric constant LaAlO3 film were fabricated. Furthermore, the characteristic time-to-breakdown, TBD, of the MOS capacitors was investigated. The TBD was measured and the corresponding Weibull slopes, β, of the MOS capacitors with various LaAlO3 thicknesses were calculated. In addition, a modified percolation model was proposed to consider the extrinsic factors of breakdown. These extrinsic factors were described by an equivalent reduction of the path-to-breakdown, tex, in the model. Using this model, the calculated tex of the MOS capacitor was 5.8 nm.

  2. Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide Semiconductor Devices

    DTIC Science & Technology

    1980-05-01

    shorting problem with poly-Si can be understood from the oxidation results. Therefore, the present study deals firstly with descnb- ing the morphologial ...Poly-Si islands with curved surfaces facing the thermal SiO 2 layer will give field distortion and current enhance- ment. V. CONCLUSIONS Clearly, this...equivalent to that In ftg 19 which was stremd with V3 -8 V frm an intal umchargs virgi Mtat. Vo~ ag *ft indicate "peulte due to umistentional writ of W

  3. Molecular doping for control of gate bias stress in organic thin film transistors

    NASA Astrophysics Data System (ADS)

    Hein, Moritz P.; Zakhidov, Alexander A.; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K.; Leo, Karl

    2014-01-01

    The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

  4. Gate-set tomography and beyond

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    Four years ago, there was no reliable way to characterize and debug quantum gates. Process tomography required perfectly pre-calibrated gates, while randomized benchmarking only yielded an overall error rate. Gate-set tomography (GST) emerged around 2012-13 in several variants (most notably at IBM; see PRA 87, 062119) to address this need, providing complete and calibration-free characterization of gates. At Sandia, we have pushed the capabilities of GST well beyond these initial goals. In this talk, I'll demonstrate our open web interface, show how we characterize gates with accuracy at the Heisenberg limit, discuss how we put error bars on the results, and present experimental GST estimates with 1e-5 error bars. I'll also present preliminary results of GST on 2-qubit gates, including a brief survey of the tricks we use to make it possible. I'll conclude with an analysis of GST's limitations (e.g., it scales poorly), and the techniques under development for characterizing and debugging larger (3+ qubit) systems.

  5. Amorphous Indium Gallium Zinc Oxide Semiconductor Thin Film Transistors Using O2 Plasma Treatment on the SiNx Gate Insulator

    NASA Astrophysics Data System (ADS)

    Kim, Woong-Sun; Moon, Yeon-Keon; Lee, Sih; Kang, Byung-Woo; Kim, Kyung-Taek; Lee, Je-Hun; Kim, Joo-Han; Ahn, Byung-Du; Park, Jong-Wan

    2010-08-01

    In this study, we investigated the role of processing parameters on the electrical characteristics of amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) fabricated using DC magnetron sputtering at room temperature. Processing parameters including the oxygen partial pressure, annealing temperature, and channel thickness have a great influence on TFT performance and better devices are obtained at a low oxygen partial pressure, annealing at 200 °C, and a low channel thickness. We attempted to improve the a-IGZO TFT performance and stability under a gate bias stress using O2 plasma treatment. With an O2 plasma treated gate insulator, remarkable properties including excellent bias stability as well as a field effect mobility (µFE) of 11.5 cm2 V-1 s-1, a subthreshold swing (S) of 0.59 V/decade, a turn-on voltage (VON) of -1.3 V, and an on/off current ratio (ION/IOFF) of 105 were achieved.

  6. Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

    SciTech Connect

    Vedam, S.; Archambault, L.; Starkschall, G.; Mohan, R.; Beddar, S.

    2007-11-15

    and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8{+-}11% and 14{+-}21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4{+-}7% and 8{+-}15% with and without audio-visual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.

  7. Steep sub-threshold current slope (∼2 mV/dec) Pt/Cu2S/Pt gated memristor with lon/Ioff > 100

    NASA Astrophysics Data System (ADS)

    Mou, N. I.; Zhang, Y.; Pai, P.; Tabib-Azar, M.

    2017-01-01

    Memristors with steep off-on transitions and high "on" currents are excellent candidates for very low power and efficient electronics. Owing to their switching mechanism based on ion motion and oxidation/reduction process, memristors bridge the gap between MEMS and MOSFETs. They have better reliability similar to MOSFETS and at the same time have the more desirable off-to-on current ratios of MEMS. Here we show that by adding a gate electrode to memristors, the SET/RESET voltages in electrochemical memristors can be controlled enabling their applications in circuits with high input/output isolations. We discuss devices with 2 mV/dec sub-threshold slope and show that the gate field effect can be used to modify the SET/RESET voltages considerably. In addition to enabling very low power switches using memristors, the gate can also be used as a global RESET.

  8. Confirming Pseudomonas putida as a reliable bioassay for demonstrating biocompatibility enhancement by solar photo-oxidative processes of a biorecalcitrant effluent.

    PubMed

    García-Ripoll, A; Amat, A M; Arques, A; Vicente, R; Ballesteros Martín, M M; Pérez, J A Sánchez; Oller, I; Malato, S

    2009-03-15

    Experiments based on Vibrio fischeri, activated sludge and Pseudomonas putida have been employed to check variation in the biocompatibility of an aqueous solution of a commercial pesticide, along solar photo-oxidative process (TiO(2) and Fenton reagent). Activated sludge-based experiments have demonstrated a complete detoxification of the solution, although important toxicity is still detected according to the more sensitive V. fischeri assays. In parallel, the biodegradability of organic matter is strongly enhanced, with BOD(5)/COD ratio above 0.8. Bioassays run with P. putida have given similar trends, remarking the convenience of using P. putida culture as a reliable and reproducible method for assessing both toxicity and biodegradability, as a substitute to other more time consuming methods.

  9. Optical Logic Gates

    NASA Technical Reports Server (NTRS)

    Du Fresne, E. R.; Dowler, W. L.

    1985-01-01

    Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.

  10. 19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTH - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  11. 4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE NO. 7 AND NON-SUBMERSIBLE TAINTER GATES, LOOKING WEST (UPSTREAM) - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

  12. 15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND GATE ARMS, PIERS AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  13. An enzyme-free and DNA-based Feynman gate for logically reversible operation.

    PubMed

    Zhou, Chunyang; Wang, Kun; Fan, Daoqing; Wu, Changtong; Liu, Dali; Liu, Yaqing; Wang, Erkang

    2015-06-28

    A logically reversible Feynman gate was successfully realized under enzyme-free conditions by integrating graphene oxide and DNA for the first time. The gate has a one-to-one mapping function to identify inputs from the corresponding outputs. This type of reversible logic gate may have great potential applications in information processing and biosensing systems.

  14. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  15. Sliding-gate valve

    DOEpatents

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  16. Gates for electron confinement in Si/SiGe 2DEGs at cryogenic temperatures

    NASA Astrophysics Data System (ADS)

    Slinker, K. A.; Klein, L. J.; Goswami, S.; Truitt, J. L.; Savage, D. E.; Lagally, M. G.; van der Weide, D. W.; Coppersmith, S. N.; Eriksson, M. A.; Chu, J. O.; Ott, J. A.; Mooney, P. M.

    2004-03-01

    A major challenge is the fabrication of ultra-low leakage gates for 2DEG confinement in Si/SiGe at cryogenic temperatures. Here we report results on the fabrication of gates by four different methods: metallic Schottky gates, metal-oxide-silicon, metal-dielectric-silicon using spin-on glass, and lateral etch-defined gates. Lateral etch-defined gates are shown to produce quantum dots displaying Coulomb blockade. We discuss the prospects for producing similar structures using truly metallic gates in combination with etch-defined trenches.

  17. Improved Reading Gate For Vertical-Bloch-Line Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

  18. Fractioned exhaled nitric oxide (FE(NO)) is not a sufficiently reliable test for monitoring asthma in pregnancy.

    PubMed

    Nittner-Marszalska, Marita; Liebhart, Jerzy; Pawłowicz, Robert; Kazimierczak, Anna; Marszalska, Hanna; Kraus-Filarska, Maria; Panaszek, Bernard; Dor-Wojnarowska, Anna

    2013-09-01

    It has been reported that fractioned exhaled nitric oxide (FENO) can be used for monitoring airway inflammation and for asthma management but conclusions drawn by different researchers are controversial. The aim of our study was to evaluate the clinical usefulness of FENO assessment for monitoring asthma during pregnancy. We monitored 72 pregnant asthmatics aged 18-38years (Me=29 years) who underwent monthly investigations including: the level of asthma control according to GINA (Global Initiative for Asthma), the occurrence of exacerbations, ACT (Asthma Control Test), as well as FENO and spirometry measurements. In 50 women, during all visits, asthma was well-controlled. In the remaining 22 women, asthma was periodically uncontrolled. FENO measured at the beginning of the study did not show significant correlation with retrospectively evaluated asthma severity (r=0.07; p=0.97). An analysis of data collected during all 254 visits showed that FENO correlated significantly but weakly with ACT scores (r=0.25; p=0.0004) and FEV1 (r=0.21; p=0.0014). FENO at consecutive visits in women with well-controlled asthma (N=50) showed large variability expressed by median coefficient of variation (CV)=32.0% (Min 2.4%, Max 121.9%). This concerned both: atopic and nonatopic groups (35.5%; and 26.7%, respectively). Large FENO variability (35.5%) was also found in a subgroup of women (N=11) with ACT=25 constantly throughout the study. FENO measured at visits when women temporarily lost control of asthma (N=22; 38 visits), showed an increasing tendency (64.2 ppb; 9.5 ppb-188.3 ppb), but did not differ significantly (p=0.13) from measurements taken at visits during which asthma was well-controlled (27.6 ppb; 6.2 ppb-103.4 ppb). The comparison of FENO in consecutive months of pregnancy in women who had well-controlled asthma did not show significant differences in FENO values during the time of observation. The assessment of asthma during pregnancy by means of monitoring FENO is of

  19. Adiabatically implementing quantum gates

    SciTech Connect

    Sun, Jie; Lu, Songfeng Liu, Fang

    2014-06-14

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  20. Optical NAND gate

    DOEpatents

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  1. Hafnium dioxide gate dielectrics, metal gate electrodes, and phenomena occurring at their interfaces

    NASA Astrophysics Data System (ADS)

    Schaeffer, James Kenyon, III

    As metal-oxide-semiconductor field-effect transistor (MOSFET) gate lengths scale down below 45 nm, the gate oxide thickness approaches 1 nm equivalent oxide thickness. At this thickness, conventional silicon dioxide (SiO 2) gate dielectrics suffer from excessive gate leakage. Higher permittivity dielectrics are required to counter the increase in gate leakage. Hafnium dioxide (HfO2) has emerged as a promising dielectric candidate. HfO2 films deposited using metal organic chemical vapor deposition are being studied to determine the impact of process and annealing conditions on the physical and electrical properties of the gate dielectric. This study indicates that deposition and annealing temperatures influence the microstructure, density, impurity concentration, chemical environment of the impurities, and band-gap of the HfO2 dielectric. Correlations of the electrical and physical properties of the films indicate that impurities in the form of segregated carbon clusters, and low HfO2 density are detrimental to the leakage properties of the gate dielectric. Additionally, as the HfO2 thickness scales, the additional series capacitance due to poly-silicon depletion plays a larger roll in reducing the total gate capacitance. To solve this problem, high performance bulk MOSFETs will require dual metal gate electrodes possessing work functions near the silicon band edges for optimized drive current. This investigation evaluates TiN, Ta-Si-N, Ti-Al-N, WN, TaN, TaSi, Ir and IrO2 electrodes as candidate electrodes on HfO2 dielectrics. The metal-dielectric compatibility was studied by annealing the gate stacks at different temperatures. The physical stability and effective work functions of metal electrodes on HfO2 are discussed. Finally, Fermi level pinning of the metal is a barrier to identifying materials with appropriate threshold voltages. The contributions to the Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the

  2. Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

    2016-11-01

    Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

  3. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  4. Gallium arsenide processing for gate array logic

    NASA Astrophysics Data System (ADS)

    Cole, Eric D.

    1989-09-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  5. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    PubMed Central

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-01-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs. PMID:26674338

  6. Inversion gate capacitance of undoped single-gate and double-gate field-effect transistor geometries in the extreme quantum limit

    SciTech Connect

    Majumdar, Amlan

    2015-05-28

    We present first-principle analytical derivations and numerically modeled data to show that the gate capacitance per unit gate area C{sub G} of extremely thin undoped-channel single-gate and double-gate field-effect transistor geometries in the extreme quantum limit with single-subband occupancy can be written as 1/C{sub G} = 1/C{sub OX} + N{sub G}/C{sub DOS} + N{sub G}/ηC{sub WF}, where N{sub G} is the number of gates, C{sub OX} is the oxide capacitance per unit area, C{sub DOS} is the density-of-states capacitance per unit area, C{sub WF} is the wave function spreading capacitance per unit area, and η is a constant on the order of 1.

  7. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARM, GATE PIER AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  8. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARMS, GATE PIER AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  9. Optical XOR gate

    SciTech Connect

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  10. Optical NOR gate

    DOEpatents

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  11. Reliability Design Handbook

    DTIC Science & Technology

    1976-03-01

    prediction, failure modes and effects analysis ( FMEA ) and reliability growth techniques represent those prediction and design evaluation methods that...Assessment Production Operation Ö Maintenance MIL-HDBK- 217 Bayesian Techniques Probabilistic Design FMEA I R Growth " I...devices suffer thermal aging; oxidation and other chemical reactions are enhanced; viscosity reduction and evaporation of lubricants are problems

  12. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

    NASA Astrophysics Data System (ADS)

    Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

    2015-09-01

    In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

  13. Quantification of F2-isoprostanes as a reliable index of oxidative stress in vivo using gas chromatography-mass spectrometry (GC-MS) method.

    PubMed

    Liu, Wei; Morrow, Jason D; Yin, Huiyong

    2009-10-15

    Free radical-induced lipid peroxidation has been implicated in a number of human diseases including atherosclerosis, cancer, and neurodegenerative diseases. F(2)-Isoprostanes (IsoPs) are isomers of prostaglandin PGF(2alpha) that are generated in vivo from the free radical-initiated peroxidation of arachidonic acid independent of cyclooxygenase enzymes. Since the discovery of the IsoPs in the early 1990s, a large body of evidence has been accumulated to indicate that quantification of these F(2)-IsoPs represents the most reliable biomarker to assess oxidative stress in vivo. A variety of analytical approaches have been developed for the quantification of these novel compounds; these methods include mass spectrometry (MS) detection coupled to gas chromatography (GC) or liquid chromatography (LC) separation, and detection using immunological approaches. This article summarizes our current methodology to quantify F(2)-IsoPs in biological fluids and tissues using GC-MS. This method includes solid-phase extraction (SPE), thin-layer chromatography (TLC) purification, chemical derivatization, and MS detection using negative ion chemical ionization (NICI) coupled with GC. The protocol described herein has been optimized and validated to provide the best sensitivity and selectivity for quantification of F(2)-IsoPs from a variety of biological sources.

  14. Round-robin evaluation of a solid-phase microextraction-gas chromatographic method for reliable determination of trace level ethylene oxide in sterilized medical devices.

    PubMed

    Harper, Thomas; Cushinotto, Lisa; Blaszko, Nancy; Arinaga, Julie; Davis, Frank; Cummins, Calvin; DiCicco, Michael

    2008-02-01

    Medical devices that are sterilized with ethylene oxide (EtO) retain small quantities of EtO residuals, which may cause negative systemic and local irritating effects, and must be accurately quantified to ensure non-toxicity. The goal of this round-robin study is to investigate the capability of a novel solid-phase microextraction-gas chromatographic (SPME-GC) method for trace-level EtO residuals analysis: three independent laboratories conducted a guided experiment using this SPME-GC method, in assessing method performance, ruggedness and the feasibility of SPME fibers. These were satisfactory across the independent laboratories, at the 0.05-5.00 ppm EtO range. This method was then successfully applied to analyze EtO residuals in several sterilized/aerated medical devices of various polymeric composition, reliably detecting and quantifying the trace levels of EtO residuals present ( approximately 0.05 ppm EtO). SPME is a feasible alternative for quantifying trace-level EtO residuals in sterilized medical devices, thereby lowering the limit of quantification (LOQ) by as much as two to three orders of magnitude over the current GC methodology of direct liquid injection.

  15. Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal-oxide-silicon fin field-effect transistors

    NASA Astrophysics Data System (ADS)

    Mizubayashi, Wataru; Onoda, Hiroshi; Nakashima, Yoshiki; Ishikawa, Yuki; Matsukawa, Takashi; Endo, Kazuhiko; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Migita, Shinji; Morita, Yukinori; Ota, Hiroyuki; Masahara, Meishoku

    2015-04-01

    We have investigated the impact of heated ion implantation (I/I) on the performance and reliability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) fin field-effect transistors (FinFETs). An implantation temperature equal to and higher than 400 °C is needed to maintain the crystallinity of the Si substrate during I/I within the experimental conditions of ion species, implantation energy, and ion dose in this study. By heated I/I at 500 °C, the 11-nm-thick SOI layer perfectly maintains the crystallinity even after I/I, and a defect-free crystal is obtained by activation annealing. It was clarified that the cap layer is essential for the suppression of the out-diffusion during heated I/I. Heated I/I on the source and drain improves the on-current-off-current (Ion-Ioff), threshold voltage (Vth) variability, and bias temperature instability (BTI) characteristics of nMOS and pMOS FinFETs as compared with those after room-temperature I/I.

  16. Demonstrating 1 nm-oxide-equivalent-thickness HfO2/InSb structure with unpinning Fermi level and low gate leakage current density

    NASA Astrophysics Data System (ADS)

    Trinh, Hai-Dang; Lin, Yueh-Chin; Nguyen, Minh-Thuy; Nguyen, Hong-Quan; Duong, Quoc-Van; Luc, Quang-Ho; Wang, Shin-Yuan; Nguyen, Manh-Nghia; Yi Chang, Edward

    2013-09-01

    In this work, the band alignment, interface, and electrical characteristics of HfO2/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO2 layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO2/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10-4 A/cm-2. The Dit value of smaller than 1012 eV-1cm-2 has been obtained using conduction method.

  17. Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

    NASA Astrophysics Data System (ADS)

    Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

    2016-12-01

    The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

  18. Non-Adiabatic Holonomic Quantum Gates in an atomic system

    NASA Astrophysics Data System (ADS)

    Azimi Mousolou, Vahid; Canali, Carlo M.; Sjoqvist, Erik

    2012-02-01

    Quantum computation is essentially the implementation of a universal set of quantum gate operations on a set of qubits, which is reliable in the presence of noise. We propose a scheme to perform robust gates in an atomic four-level system using the idea of non-adiabatic holonomic quantum computation proposed in [1]. The gates are realized by applying sequences of short laser pulses that drive transitions between the four energy levels in such a way that the dynamical phases vanish. [4pt] [1] E. Sjoqvist, D.M. Tong, B. Hessmo, M. Johansson, K. Singh, arXiv:1107.5127v2 [quant-ph

  19. Gate contact resistive random access memory in nano scaled FinFET logic technologies

    NASA Astrophysics Data System (ADS)

    Hsu, Meng-Yin; Shih, Yi-Hong; Chih, Yue-Der; Lin, Chrong Jung; King, Ya-Chin

    2017-04-01

    A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gate contact plug and interlayer dielectric (ILD) in the middle, and a gate contact and an n-type epitaxial drain terminal as the top and bottom electrodes, respectively. It features low-voltage operation and reset current, compact cell size, and a stable read window. As a promising embedded NVM solution, the compact one transistor and one resistor (1T1R) cell is highly scalable as the technology node progresses. Excellent data retention and cycling capability have also been demonstrated by the reliability testing results. These superior characteristics make GC-RRAM one of a few viable candidates for logic NVM for future FinFET circuits.

  20. The human respiratory gate

    NASA Technical Reports Server (NTRS)

    Eckberg, Dwain L.

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

  1. Advanced insulated gate bipolar transistor gate drive

    DOEpatents

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  2. AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors with high on/off current ratio of over 5 × 1010 achieved by ozone pretreatment and using ozone oxidant for Al2O3 gate insulator

    NASA Astrophysics Data System (ADS)

    Tokuda, Hirokuni; Asubar, Joel T.; Kuzuhara, Masaaki

    2016-12-01

    This letter describes DC characteristics of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with Al2O3 deposited by atomic layer deposition (ALD) as gate dielectric. Comparison was made for the samples deposited using ozone (O3) or water as oxidant. The effect of pretreatment, where O3 was solely supplied prior to depositing Al2O3, was also investigated. The MIS-HEMT with O3 pretreatment and Al2O3 gate dielectric deposited using O3 as the oxidant exhibited the most desirable characteristics with an excellent high on/off current ratio of 7.1 × 1010, and a low sub-threshold swing (SS) of 73 mV/dec.

  3. Reliability training

    NASA Technical Reports Server (NTRS)

    Lalli, Vincent R. (Editor); Malec, Henry A. (Editor); Dillard, Richard B.; Wong, Kam L.; Barber, Frank J.; Barina, Frank J.

    1992-01-01

    Discussed here is failure physics, the study of how products, hardware, software, and systems fail and what can be done about it. The intent is to impart useful information, to extend the limits of production capability, and to assist in achieving low cost reliable products. A review of reliability for the years 1940 to 2000 is given. Next, a review of mathematics is given as well as a description of what elements contribute to product failures. Basic reliability theory and the disciplines that allow us to control and eliminate failures are elucidated.

  4. Exceptional capability of nanosized CeO(2) materials to "dissolve" lanthanide oxides established by time-gated excitation and emission spectroscopy.

    PubMed

    Tiseanu, Carmen; Parvulescu, Vasile; Avram, Daniel; Cojocaru, Bogdan; Sanchez-Dominguez, Margarita

    2014-05-28

    The atomic scale homogeneity of Ce and Zr oxygen bonds represents the main reason for enhanced total oxygen storage capability of CeO2-ZrO2 (Ce/Zr = 1) as compared to that of CeO2. Here, we demonstrate that the addition of 10% Eu(3+) by wet impregnation on preformed nanosized CeO2-ZrO2 (Ce/Zr = 1) followed by calcination induces a remarkable homogeneity of 10% Eu(3+)-CeO2-ZrO2 solid solution. By use of time-resolved emission and excitation spectroscopies, the improvement of the nanoscale chemical and structural homogeneity of 10% Eu(3+)-CeO2-ZrO2 calcined at 1000 as compared to sample calcined at 750 °C is demonstrated. Based on the comparison of luminescence properties of 10% Eu(3+) impregnated on preformed nanosized CeO2-ZrO2 and CeO2, we also show that the presence of zirconium does not only preserve the ability of cerium oxide to "dissolve" lanthanide oxide, but also determines an important stabilization of defects (oxygen vacancies) generated upon Eu(3+) doping.

  5. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    PubMed

    Khan, Z N; Ahmed, S; Ali, M

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  6. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

    PubMed Central

    Khan, Z. N.; Ahmed, S.; Ali, M.

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  7. Person Reliability

    ERIC Educational Resources Information Center

    Lumsden, James

    1977-01-01

    Person changes can be of three kinds: developmental trends, swells, and tremors. Person unreliability in the tremor sense (momentary fluctuations) can be estimated from person characteristic curves. Average person reliability for groups can be compared from item characteristic curves. (Author)

  8. CFTR Gating I

    PubMed Central

    Bompadre, Silvia G.; Ai, Tomohiko; Cho, Jeong Han; Wang, Xiaohui; Sohma, Yoshiro; Li, Min; Hwang, Tzyh-Chang

    2005-01-01

    The CFTR chloride channel is activated by phosphorylation of serine residues in the regulatory (R) domain and then gated by ATP binding and hydrolysis at the nucleotide binding domains (NBDs). Studies of the ATP-dependent gating process in excised inside-out patches are very often hampered by channel rundown partly caused by membrane-associated phosphatases. Since the severed ΔR-CFTR, whose R domain is completely removed, can bypass the phosphorylation-dependent regulation, this mutant channel might be a useful tool to explore the gating mechanisms of CFTR. To this end, we investigated the regulation and gating of the ΔR-CFTR expressed in Chinese hamster ovary cells. In the cell-attached mode, basal ΔR-CFTR currents were always obtained in the absence of cAMP agonists. Application of cAMP agonists or PMA, a PKC activator, failed to affect the activity, indicating that the activity of ΔR-CFTR channels is indeed phosphorylation independent. Consistent with this conclusion, in excised inside-out patches, application of the catalytic subunit of PKA did not affect ATP-induced currents. Similarities of ATP-dependent gating between wild type and ΔR-CFTR make this phosphorylation-independent mutant a useful system to explore more extensively the gating mechanisms of CFTR. Using the ΔR-CFTR construct, we studied the inhibitory effect of ADP on CFTR gating. The Ki for ADP increases as the [ATP] is increased, suggesting a competitive mechanism of inhibition. Single channel kinetic analysis reveals a new closed state in the presence of ADP, consistent with a kinetic mechanism by which ADP binds at the same site as ATP for channel opening. Moreover, we found that the open time of the channel is shortened by as much as 54% in the presence of ADP. This unexpected result suggests another ADP binding site that modulates channel closing. PMID:15767295

  9. DNA logic gates.

    PubMed

    Okamoto, Akimitsu; Tanaka, Kazuo; Saito, Isao

    2004-08-04

    A conceptually new logic gate based on DNA has been devised. Methoxybenzodeazaadenine ((MD)A), an artificial nucleobase which we recently developed for efficient hole transport through DNA, formed stable base pairs with T and C. However, a reasonable hole-transport efficiency was observed in the reaction for the duplex containing an (MD)A/T base pair, whereas the hole transport was strongly suppressed in the reaction using a duplex where the base opposite (MD)A was replaced by C. The influence of complementary pyrimidines on the efficiency of hole transport through (MD)A was quite contrary to the selectivity observed for hole transport through G. The orthogonality of the modulation of these hole-transport properties by complementary pyrimidine bases is promising for the design of a new molecular logic gate. The logic gate system was executed by hole transport through short DNA duplexes, which consisted of the "logic gate strand", containing hole-transporting nucleobases, and the "input strand", containing pyrimidines which modulate the hole-transport efficiency of logic bases. A logic gate strand containing multiple (MD)A bases in series provided the basis for a sharp AND logic action. On the other hand, for OR logic and combinational logic, conversion of Boolean expressions to standard sum-of-product (SOP) expressions was indispensable. Three logic gate strands were designed for OR logic according to each product term in the standard SOP expression of OR logic. The hole-transport efficiency observed for the mixed sample of logic gate strands exhibited an OR logic behavior. This approach is generally applicable to the design of other complicated combinational logic circuits such as the full-adder.

  10. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  11. Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Lina, Shi; Yiqi, Zhuang; Cong, Li; Dechang, Li

    2014-03-01

    An analytical direct tunneling gate current model for cylindrical surrounding gate (CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current. Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  12. Electrolytic gate for quantum efficiency enhancement in thinned CCDs

    NASA Astrophysics Data System (ADS)

    Damento, Michael A.; Watson, Mary; Sims, Gary R.

    1993-07-01

    A transparent, semi-solid, electrolytic gate has been applied to the backside of thinned CCDs for quantum efficiency enhancement. The gate is applied by spreading a water solution of phosphoric acid and polyvinyl alcohol onto the silicon and drying it to form a thin plastic film. When a negative voltage of less than one volt with respect to substrate ground is applied to the gate, a QE pinned condition (100% internal quantum efficiency) is produced. An insulating layer is not needed with this gate (as it is with electronic conductors) since a threshold voltage of about 1.2 V is required before conduction into the silicon can occur. The mechanism of charging is believed to involve a pile-up of negative ions at the silicon-electrolyte interface which compensates for the positive oxide charge. Conduction into the silicon at low voltages is restricted by the oxidation potential of the negative ions in the electrolyte.

  13. Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

    DTIC Science & Technology

    2010-03-31

    floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...organic semiconductors. The field effect transistors showed floating gate effects, but the potential for organic memories was not realized. Recently...

  14. Reliability automation tool (RAT) for fault tolerance computation

    NASA Astrophysics Data System (ADS)

    Singh, N. S. S.; Hamid, N. H.; Asirvadam, V. S.

    2012-09-01

    As CMOS transistors reduced in size, the circuit built using these nano-scale transistors naturally becomes less reliable. The reliability reduction, which is the measure of circuit performance, has brought up so many challenges in designing modern logic integrated circuit. Therefore, reliability modeling is increasingly important subject to be considered in designing modern logic integrated circuit. This drives a need to compute reliability measures for nano-scale circuits. This paper looks into the development of reliability automation tool (RAT) for circuit's reliability computation. The tool is developed using Matlab programming language based on the reliability evaluation model called Probabilistic Transfer Matrix (PTM). RAT allows users to significantly speed-up the reliability assessments of nano-scale circuits. Users have to provide circuit's netlist as the input to RAT for its reliability computation. The netlist signifies the circuit's description in terms of Gate Profile Matrix (GPM), Adjacency Computation Matrix (ACM) and Grid Layout Matrix (GLM). GPM, ACM and GLM indicate the types of logic gates, the interconnection between these logic gates and the layout matrix of these logic gates respectively in a given circuit design. Here, the reliability assessment by RAT is carried out on Full Adder circuit as the benchmark test circuit.

  15. Review paper: Transparent amorphous oxide semiconductor thin film transistor

    NASA Astrophysics Data System (ADS)

    Kwon, Jang-Yeon; Lee, Do-Joong; Kim, Ki-Bum

    2011-03-01

    Thin film transistors (TFTs) with oxide semiconductors have drawn great attention in the last few years, especially for large area electronic applications, such as high resolution active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs), because of their high electron mobility and spatial uniform property. This paper reviews and summarizes recent emerging reports that include potential applications, oxide semiconductor materials, and the impact of the fabrication process on electrical performance. We also address the stability behavior of such devices under bias/illumination stress and critical factors related to reliability, such as the gate insulator, the ambient and the device structure.

  16. Investigation of carbonitrided components of the valve gates of Christmas trees and tubing heads

    SciTech Connect

    Kakhramanov, K.T.; Fataliev, N.S.; Levitan, Y.A.; Safarov, R.S.

    1985-07-01

    The authors evaluate the effectiveness of carbonitride hardening of the valve gates of Christmas trees and tubing heads. Measurements of microhardness, resistance to seizing, corrosion resistance, and durability demonstrate that carbonitriding helps to ensure strength, tightness, and reliable operation of the gate in the pressure range up to 35 MPa. Therefore, gates with carbonitrided components are durable and fully satisfy the requirements of the technique and technology of operation.

  17. 7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, HEADHOUSES AND DAM BRIDGE, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  18. 2. CANNON GATES. DETAIL OF NORTHWEST GATE STONE WALL TO ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    2. CANNON GATES. DETAIL OF NORTHWEST GATE STONE WALL TO LEFT IS A REMNANT OF THE ORIGINAL FACILITY BOUNDARY FENCE. IT IS CONSTRUCTED IN BLUE PUDDING STONE. - Picatinny Arsenal, State Route 15 near I-80, Dover, Morris County, NJ

  19. On the Asymmetric Splitting of CBED HOLZ Lines under the Gate of Recessed SiGe Source/Drain Transistors

    NASA Astrophysics Data System (ADS)

    Benedetti, A.; Bender, H.

    The behaviour of the CBED HOLZ line splitting under the gate of transistor structures with recessed SiGe in the source/drain regions is investigated. Structures with nitride/oxide dummy gates or with poly gates and nitride spacers are studied. In the gate region as well as below the SiGe, splitting of the HOLZ lines in the CBED patterns is observed with increasing magnitude towards the interface. The splitting under the gate shows an asymmetry for equivalent lines which inverts along horizontal cutlines under the gate. The behaviour is explained by a 3-dimensional relaxation of the stress.

  20. Adiabatic gate teleportation.

    PubMed

    Bacon, Dave; Flammia, Steven T

    2009-09-18

    The difficulty in producing precisely timed and controlled quantum gates is a significant source of error in many physical implementations of quantum computers. Here we introduce a simple universal primitive, adiabatic gate teleportation, which is robust to timing errors and many control errors and maintains a constant energy gap throughout the computation above a degenerate ground state space. This construction allows for geometric robustness based upon the control of two independent qubit interactions. Further, our piecewise adiabatic evolution easily relates to the quantum circuit model, enabling the use of standard methods from fault-tolerance theory for establishing thresholds.

  1. Exterior, looking northwest towards Main Gate, Gate House on left, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking northwest towards Main Gate, Gate House on left, Technical Equipment Building (Building 5760) in background to right - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  2. Exterior, looking southeast from within compound towards Main Gate, Gate ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking southeast from within compound towards Main Gate, Gate House center left - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  3. Reliability physics

    NASA Technical Reports Server (NTRS)

    Cuddihy, E. F.; Ross, R. G., Jr.

    1984-01-01

    Speakers whose topics relate to the reliability physics of solar arrays are listed and their topics briefly reviewed. Nine reports are reviewed ranging in subjects from studies of photothermal degradation in encapsulants and polymerizable ultraviolet stabilizers to interface bonding stability to electrochemical degradation of photovoltaic modules.

  4. Leaf Senescence Signaling: The Ca2+-Conducting Arabidopsis Cyclic Nucleotide Gated Channel2 Acts through Nitric Oxide to Repress Senescence Programming1[W][OA

    PubMed Central

    Ma, Wei; Smigel, Andries; Walker, Robin K.; Moeder, Wolfgang; Yoshioka, Keiko; Berkowitz, Gerald A.

    2010-01-01

    Ca2+ and nitric oxide (NO) are essential components involved in plant senescence signaling cascades. In other signaling pathways, NO generation can be dependent on cytosolic Ca2+. The Arabidopsis (Arabidopsis thaliana) mutant dnd1 lacks a plasma membrane-localized cation channel (CNGC2). We recently demonstrated that this channel affects plant response to pathogens through a signaling cascade involving Ca2+ modulation of NO generation; the pathogen response phenotype of dnd1 can be complemented by application of a NO donor. At present, the interrelationship between Ca2+ and NO generation in plant cells during leaf senescence remains unclear. Here, we use dnd1 plants to present genetic evidence consistent with the hypothesis that Ca2+ uptake and NO production play pivotal roles in plant leaf senescence. Leaf Ca2+ accumulation is reduced in dnd1 leaves compared to the wild type. Early senescence-associated phenotypes (such as loss of chlorophyll, expression level of senescence-associated genes, H2O2 generation, lipid peroxidation, tissue necrosis, and increased salicylic acid levels) were more prominent in dnd1 leaves compared to the wild type. Application of a Ca2+ channel blocker hastened senescence of detached wild-type leaves maintained in the dark, increasing the rate of chlorophyll loss, expression of a senescence-associated gene, and lipid peroxidation. Pharmacological manipulation of Ca2+ signaling provides evidence consistent with genetic studies of the relationship between Ca2+ signaling and senescence with the dnd1 mutant. Basal levels of NO in dnd1 leaf tissue were lower than that in leaves of wild-type plants. Application of a NO donor effectively rescues many dnd1 senescence-related phenotypes. Our work demonstrates that the CNGC2 channel is involved in Ca2+ uptake during plant development beyond its role in pathogen defense response signaling. Work presented here suggests that this function of CNGC2 may impact downstream basal NO production in addition

  5. Leaf senescence signaling: the Ca2+-conducting Arabidopsis cyclic nucleotide gated channel2 acts through nitric oxide to repress senescence programming.

    PubMed

    Ma, Wei; Smigel, Andries; Walker, Robin K; Moeder, Wolfgang; Yoshioka, Keiko; Berkowitz, Gerald A

    2010-10-01

    Ca(2+) and nitric oxide (NO) are essential components involved in plant senescence signaling cascades. In other signaling pathways, NO generation can be dependent on cytosolic Ca(2+). The Arabidopsis (Arabidopsis thaliana) mutant dnd1 lacks a plasma membrane-localized cation channel (CNGC2). We recently demonstrated that this channel affects plant response to pathogens through a signaling cascade involving Ca(2+) modulation of NO generation; the pathogen response phenotype of dnd1 can be complemented by application of a NO donor. At present, the interrelationship between Ca(2+) and NO generation in plant cells during leaf senescence remains unclear. Here, we use dnd1 plants to present genetic evidence consistent with the hypothesis that Ca(2+) uptake and NO production play pivotal roles in plant leaf senescence. Leaf Ca(2+) accumulation is reduced in dnd1 leaves compared to the wild type. Early senescence-associated phenotypes (such as loss of chlorophyll, expression level of senescence-associated genes, H(2)O(2) generation, lipid peroxidation, tissue necrosis, and increased salicylic acid levels) were more prominent in dnd1 leaves compared to the wild type. Application of a Ca(2+) channel blocker hastened senescence of detached wild-type leaves maintained in the dark, increasing the rate of chlorophyll loss, expression of a senescence-associated gene, and lipid peroxidation. Pharmacological manipulation of Ca(2+) signaling provides evidence consistent with genetic studies of the relationship between Ca(2+) signaling and senescence with the dnd1 mutant. Basal levels of NO in dnd1 leaf tissue were lower than that in leaves of wild-type plants. Application of a NO donor effectively rescues many dnd1 senescence-related phenotypes. Our work demonstrates that the CNGC2 channel is involved in Ca(2+) uptake during plant development beyond its role in pathogen defense response signaling. Work presented here suggests that this function of CNGC2 may impact downstream basal

  6. Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

    PubMed

    Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

    2017-04-12

    The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10(6), effective mobility up to 30 cm(2) V(-1) s(-1), small hysteresis, and small subthreshold swing (90-140 mV dec(-1)), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 Vdd = 1 V) and a voltage gain as high as 30 (at Vdd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at Vdd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

  7. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  8. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  9. Characterization and reliability of aluminum gallium nitride/gallium nitride high electron mobility transistors

    NASA Astrophysics Data System (ADS)

    Douglas, Erica Ann

    Compound semiconductor devices, particularly those based on GaN, have found significant use in military and civilian systems for both microwave and optoelectronic applications. Future uses in ultra-high power radar systems will require the use of GaN transistors operated at very high voltages, currents and temperatures. GaN-based high electron mobility transistors (HEMTs) have proven power handling capability that overshadows all other wide band gap semiconductor devices for high frequency and high-power applications. Little conclusive research has been reported in order to determine the dominating degradation mechanisms of the devices that result in failure under standard operating conditions in the field. Therefore, it is imperative that further reliability testing be carried out to determine the failure mechanisms present in GaN HEMTs in order to improve device performance, and thus further the ability for future technologies to be developed. In order to obtain a better understanding of the true reliability of AlGaN/GaN HEMTs and determine the MTTF under standard operating conditions, it is crucial to investigate the interaction effects between thermal and electrical degradation. This research spans device characterization, device reliability, and device simulation in order to obtain an all-encompassing picture of the device physics. Initially, finite element thermal simulations were performed to investigate the effect of device design on self-heating under high power operation. This was then followed by a study of reliability of HEMTs and other tests structures during high power dc operation. Test structures without Schottky contacts showed high stability as compared to HEMTs, indicating that degradation of the gate is the reason for permanent device degradation. High reverse bias of the gate has been shown to induce the inverse piezoelectric effect, resulting in a sharp increase in gate leakage current due to crack formation. The introduction of elevated

  10. Reliability study of Zr and Al incorporated Hf based high-k dielectric deposited by advanced processing

    NASA Astrophysics Data System (ADS)

    Bhuyian, Md Nasir Uddin

    Hafnium-based high-kappa dielectric materials have been successfully used in the industry as a key replacement for SiO2 based gate dielectrics in order to continue CMOS device scaling to the 22-nm technology node. Further scaling according to the device roadmap requires the development of oxides with higher kappa values in order to scale the equivalent oxide thickness (EOT) to 0.7 nm or below while achieving low defect densities. In addition, next generation devices need to meet challenges like improved channel mobility, reduced gate leakage current, good control on threshold voltage, lower interface state density, and good reliability. In order to overcome these challenges, improvements of the high-kappa film properties and deposition methods are highly desirable. In this dissertation, a detail study of Zr and Al incorporated HfO 2 based high-kappa dielectrics is conducted to investigate improvement in electrical characteristics and reliability. To meet scaling requirements of the gate dielectric to sub 0.7 nm, Zr is added to HfO2 to form Hf1-xZrxO2 with x=0, 0.31 and 0.8 where the dielectric film is deposited by using various intermediate processing conditions, like (i) DADA: intermediate thermal annealing in a cyclical deposition process; (ii) DSDS: similar cyclical process with exposure to SPA Ar plasma; and (iii) As-Dep: the dielectric deposited without any intermediate step. MOSCAPs are formed with TiN metal gate and the reliability of these devices is investigated by subjecting them to a constant voltage stress in the gate injection mode. Stress induced flat-band voltage shift (DeltaVFB), stress induced leakage current (SILC) and stress induced interface state degradation are observed. DSDS samples demonstrate the superior characteristics whereas the worst degradation is observed for DADA samples. Time dependent dielectric breakdown (TDDB) shows that DSDS Hf1-xZrxO2 (x=0.8) has the superior characteristics with reduced oxygen vacancy, which is affiliated to

  11. Self-aligned inversion n-channel In 0.2Ga 0.8As/GaAs metal-oxide-semiconductor field-effect-transistors with TiN gate and Ga 2O 3(Gd 2O 3) dielectric

    NASA Astrophysics Data System (ADS)

    Chen, C. P.; Lin, T. D.; Lee, Y. J.; Chang, Y. C.; Hong, M.; Kwo, J.

    2008-10-01

    A self-aligned process for fabricating inversion n-channel metal-oxide-semiconductor field-effect-transistors (MOSFET's) of strained In 0.2Ga 0.8As on GaAs using TiN as gate metal and Ga 2O 3(Gd 2O 3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of <10 -7 A/cm 2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ˜10 5 in drain current. For comparison, a TiN/Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10 -8-10 -9 A/cm 2, well-behaved capacitance-voltage ( C- V) characteristics giving a high dielectric constant of ˜16 and a low interfacial density of state of ˜(2˜6) × 10 11 cm -2 eV -1, and an atomically sharp smooth Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As interface.

  12. Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

    NASA Technical Reports Server (NTRS)

    Lauenstein, Jean-Marie

    2011-01-01

    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

  13. Parametric Reliability of Space-Based Field Programmable Gate Arrays

    DTIC Science & Technology

    2007-03-01

    feature-sized commercial-off-the-shelf (COTS) FPGAs in four common satellite orbits around the earth . The results are then compared to an...system. In theory, these particles are generated by supernovas of far off stars, or maybe even during the “big bang”. These particles can have...Low Earth (LEO) Medium Earth (MEO) Geosynchronous (GEO) 200 km to 2000 km 2000 km to 35,786 km 35,786 km Lower energy (< 100 MeV) GCR particle

  14. Interdigitated Extended Gate Field Effect Transistor Without Reference Electrode

    NASA Astrophysics Data System (ADS)

    Ali, Ghusoon M.

    2017-02-01

    An interdigitated extended gate field effect transistor (IEGFET) has been proposed as a modified pH sensor structure of an extended gate field effect transistor (EGFET). The reference electrode and the extended gate in the conventional device have been replaced by a single interdigitated extended gate. A metal-semiconductor-metal interdigitated extended gate containing two multi-finger Ni electrodes based on zinc oxide (ZnO) thin film as a pH-sensitive membrane. ZnO thin film was grown on a p-type Si (100) substrate by the sol-gel technique. The fabricated extended gate is connected to a commercial metal-oxide-semiconductor field-effect transistor device in CD4007UB. The experimental data show that this structure has real time and linear pH voltage and current sensitivities in a concentration range between pH 4 and 11. The voltage and current sensitivities are found to be about 22.4 mV/pH and 45 μA/pH, respectively. Reference electrode elimination makes the IEGFET device simple to fabricate, easy to carry out the measurements, needing a small volume of solution to test and suitable for disposable biosensor applications. Furthermore, this uncomplicated structure could be extended to fabricate multiple ions microsensors and lab-on-chip devices.

  15. Challenges Regarding IP Core Functional Reliability

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth A.

    2017-01-01

    For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.

  16. Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

    NASA Astrophysics Data System (ADS)

    Kim, Seunghyun; Lee, Sang-Ho; Kim, Young-Goan; Cho, Seongjae; Park, Byung-Gook

    2017-01-01

    In this paper, a highly reliable circuit model of gate-all-around (GAA) charge-trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon-oxide-nitride-oxide-silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.

  17. Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications

    SciTech Connect

    Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F.; Lee, Y.; Park, C.

    1999-12-06

    We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.

  18. Electroluminescence from individual air-suspended carbon nanotubes within split-gate structures

    NASA Astrophysics Data System (ADS)

    Higashide, N.; Uda, T.; Yoshida, M.; Ishii, A.; Kato, Y. K.

    Electrically induced light emission from chirality-identified single-walled carbon nanotubes are investigated by utilizing split-gate field-effect devices fabricated on silicon-on-insulator substrates. We begin by etching trenches through the top silicon layer into the buried oxide, and the silicon layer is thermally oxidized for use as local gates. We partially remove the oxide and form gate electrodes, then contacts for nanotubes are deposited on both sides of the trench. Catalyst particles are placed on the contacts, and nanotubes are grown over the trench by chemical vapor deposition. We use photoluminescence microscopy to locate the nanotubes and perform excitation spectroscopy to identify their chirality. Gate-induced photoluminescence quenching is used to confirm carrier doping, and electroluminescence intensity is investigated as a function of the split-gate and bias voltages. Work supported by JSPS (KAKENHI 24340066, 26610080), MEXT (Photon Frontier Network Program, Nanotechnology Platform), Canon Foundation, and Asahi Glass Foundation.

  19. Network reliability

    NASA Technical Reports Server (NTRS)

    Johnson, Marjory J.

    1985-01-01

    Network control (or network management) functions are essential for efficient and reliable operation of a network. Some control functions are currently included as part of the Open System Interconnection model. For local area networks, it is widely recognized that there is a need for additional control functions, including fault isolation functions, monitoring functions, and configuration functions. These functions can be implemented in either a central or distributed manner. The Fiber Distributed Data Interface Medium Access Control and Station Management protocols provide an example of distributed implementation. Relative information is presented here in outline form.

  20. A quantum Fredkin gate.

    PubMed

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  1. A quantum Fredkin gate

    PubMed Central

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  2. Synchronous pulsing plasma utilization in dummy poly gate removal process

    NASA Astrophysics Data System (ADS)

    Huang, Ruixuan; Meng, Xiao-Ying; Han, Qiu-Hua; Zhang, Hai-Yang

    2015-03-01

    When CMOS technology reaches 28/20nm node and beyond, several new schemes are implemented such as High K metal gate (HKMG) which can enhance the device performance and has better control of device current leakage. Dummy poly gate removal (DPGR) process is introduced for HKMG, and works as a key process to control the work function of metal gate and threshold voltage (Vt) shift. In dry etch technology, conventional continuous wave (CW) plasma process has been widely used, however, it may not be capable for some challenging process in 28nm node and beyond. In DPGR process for HKMG scheme, CW scheme may result in plasma damage of gate oxide/capping layer for its inherent high electron temperature (Te) and ion energy while synchronous pulsing scheme is capable to simultaneously pulse both source and bias power, which could achieve lower Te, independent control of ion and radical flux, well control the loading of polymer deposition on dense/ isolate features. It's the first attempt to utilize synchronous pulsing plasma in DPGR process. Experiment results indicate that synchronous pulsing could provide less silicon recess under thin gate oxide which is induced by the plasma oxidation. Furthermore, the loading of HK capping layer loss between long channel and short channel can be well controlled which plays a key role on transistor performance, such as leakage and threshold voltage shift. Additionally, it has been found that synchronous pulsing could distinctly improve ILD loss when compared with CW, which is helpful to broaden the whole process window.

  3. Surface and Interface Chemistry for Gate Stacks on Silicon

    NASA Astrophysics Data System (ADS)

    Frank, M. M.; Chabal, Y. J.

    This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

  4. Impact of gate geometry on ionic liquid gated ionotronic systems

    NASA Astrophysics Data System (ADS)

    Wong, A. T.; Noh, J. H.; Pudasaini, P. R.; Wolf, B.; Balke, N.; Herklotz, A.; Sharma, Y.; Haglund, A. V.; Dai, S.; Mandrus, D.; Rack, P. D.; Ward, T. Z.

    2017-04-01

    Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard "side gate" 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. These findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

  5. Gating of Permanent Molds for Aluminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-01-01

    This report summarizes a two-year project, DE-FC07-011D13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was to determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings. Equipment and procedure for real time X-Ray radiography of molten aluminum flow into permanent molds have been developed. Other studies have been conducted using water flow and behavior of liquid aluminum in sand mold using real time photography. This investigation utilizes graphite molds transparent to X-Rays making it possible to observe the flow pattern through a number of vertically oriented grating systems. These have included systems that are choked at the base of a rounded vertical sprue and vertical gating systems with a variety of different ingates into the bottom of a mold cavity. These systems have also been changed to include gating systems with vertical and horizontal gate configurations. Several conclusions can be derived from this study. A sprue-well, as designed in these experiments, does not eliminate the vena contracta. Because of the swirling at the sprue-base, the circulating metal begins to push the entering metal stream toward the open runner mitigating the intended effect of the sprue-well. Improved designs of

  6. Technical and dosimetric aspects of respiratory gating using a pressure-sensor motion monitoring system

    SciTech Connect

    Li, X. Allen; Stepaniak, Christopher; Gore, Elizabeth

    2006-01-15

    This work introduces a gating technique that uses 4DCT to determine gating parameters and to plan gated treatment, and employs a Siemens linear accelerator to deliver the gated treatment. Because of technology incompatibility, the 4DCT scanner (LightSpeed, GE) and the Siemens accelerator require two different motion-monitoring systems. The motion monitoring system (AZ-773V, Anzai Med.) used for the gated delivery utilizes a pressure sensor to detect the external respiratory motion (pressure change) in real time. Another system (RPM, Varian) used for the 4DCT scanner (LightSpeed, GE) is based on an infrared camera to detect motion of external markers. These two motion monitoring systems (RPM and Anzai systems) were found to correlate well with each other. The depth doses and profile measured for gated delivery (with a duty cycle of 25% or 50%) were found to agree within 1.0% with those measured for ungated delivery, indicating that gating did not significantly alter beam characteristics. The measurement verified also that the MU linearity and beam output remained unchanged (within 0.3%). A practical method of using 4DCT to plan a gated treatment was developed. The duty cycle for either phase or amplitude gating can be determined based on 4DCT with consideration of set-up error and delivery efficiency. The close-loop measurement involving the entire gating process (imaging, planning, and delivery) showed that the measured isodose distributions agreed with those intended, validating the accuracy and reliability of the gating technique. Based these observations, we conclude that the gating technique introduced in this work, integrating Siemens linear accelerator and Anzai pressure sensor device with GE/Varian RPM 4DCT, is reliable and effective, and it can be used clinically to account for respiratory motion during radiation therapy.

  7. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    NASA Astrophysics Data System (ADS)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  8. Mechanically reliable scales and coatings

    SciTech Connect

    Tortorelli, P.F.; Alexander, K.B.

    1995-07-01

    As the first stage in examining the mechanical reliability of protective surface oxides, the behavior of alumina scales formed on iron-aluminum alloys during high-temperature cyclic oxidation was characterized in terms of damage and spallation tendencies. Scales were thermally grown on specimens of three iron-aluminum composition using a series of exposures to air at 1000{degrees}C. Gravimetric data and microscopy revealed substantially better integrity and adhesion of the scales grown on an alloy containing zirconium. The use of polished (rather than just ground) specimens resulted in scales that were more suitable for subsequent characterization of mechanical reliability.

  9. Multibit gates for quantum computing.

    PubMed

    Wang, X; Sørensen, A; Mølmer, K

    2001-04-23

    We present a general technique to implement products of many qubit operators communicating via a joint harmonic oscillator degree of freedom in a quantum computer. By conditional displacements and rotations we can implement Hamiltonians which are trigonometric functions of qubit operators. With such operators we can effectively implement higher order gates such as Toffoli gates and C(n)-NOT gates, and we show that the entire Grover search algorithm can be implemented in a direct way.

  10. Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

    NASA Astrophysics Data System (ADS)

    Gupta, Santosh Kumar

    2015-12-01

    2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate-source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator.

  11. Compact gate valve

    DOEpatents

    Bobo, Gerald E.

    1977-01-01

    This invention relates to a double-disc gate valve which is compact, comparatively simple to construct, and capable of maintaining high closing pressures on the valve discs with low frictional forces. The valve casing includes axially aligned ports. Mounted in the casing is a sealed chamber which is pivotable transversely of the axis of the ports. The chamber contains the levers for moving the valve discs axially, and an actuator for the levers. When an external drive means pivots the chamber to a position where the discs are between the ports and axially aligned therewith, the actuator for the levers is energized to move the discs into sealing engagement with the ports.

  12. ONE SHAKE GATE FORMER

    DOEpatents

    Kalibjian, R.; Perez-Mendez, V.

    1957-08-20

    An improved circuit for forming square pulses having substantially short and precise durations is described. The gate forming circuit incorporates a secondary emission R. F. pentode adapted to receive input trigger pulses amd having a positive feedback loop comnected from the dynode to the control grid to maintain conduction in response to trigger pulses. A short circuited pulse delay line is employed to precisely control the conducting time of the tube and a circuit for squelching spurious oscillations is provided in the feedback loop.

  13. Field-effect transistor replaces bulky transformer in analog-gate circuit

    NASA Technical Reports Server (NTRS)

    1965-01-01

    Metal-oxide semiconductor field-effect transistor /MOSFET/ analog-gate circuit adapts well to integrated circuits. It provides better system isolation than a transformer, while size and weight are appreciably reduced.

  14. Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Sreelal, S.; Lau, C. K.; Samudra, G. S.

    2002-03-01

    Grooved gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

  15. Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

    NASA Astrophysics Data System (ADS)

    Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

    2016-06-01

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  16. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  17. A graphical language for reliability model generation

    NASA Technical Reports Server (NTRS)

    Howell, Sandra V.; Bavuso, Salvatore J.; Haley, Pamela J.

    1990-01-01

    A graphical interface capability of the hybrid automated reliability predictor (HARP) is described. The graphics-oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault tree gates, including sequence dependency gates, or by a Markov chain. With this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the Graphical Kernel System (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing.

  18. CMOS reliability issues for emerging cryogenic Lunar electronics applications

    NASA Astrophysics Data System (ADS)

    Chen, Tianbing; Zhu, Chendong; Najafizadeh, Laleh; Jun, Bongim; Ahmed, Adnan; Diestelhorst, Ryan; Espinel, Gustavo; Cressler, John D.

    2006-06-01

    We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

  19. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

    PubMed Central

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-01-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10−14 A, leading to ultrahigh on/off ratio over 109, about ∼103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics. PMID:27586841

  20. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio.

    PubMed

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-09-02

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10(-14) A, leading to ultrahigh on/off ratio over 10(9), about ∼10(3) times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

  1. Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio

    NASA Astrophysics Data System (ADS)

    Vu, Quoc An; Shin, Yong Seon; Kim, Young Rae; Nguyen, Van Luan; Kang, Won Tae; Kim, Hyun; Luong, Dinh Hoa; Lee, Il Min; Lee, Kiyoung; Ko, Dong-Su; Heo, Jinseong; Park, Seongjun; Lee, Young Hee; Yu, Woo Jong

    2016-09-01

    Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10-14 A, leading to ultrahigh on/off ratio over 109, about ~103 times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.

  2. Gates Learns to Think Big

    ERIC Educational Resources Information Center

    Robelen, Erik W.

    2006-01-01

    This article discusses how the philanthropy of Microsoft Corp software magnate co-chairs, Bill Gates and his wife Melinda, are reshaping the American high school nowadays. Gates and his wife have put the issue on the national agenda like never before, with a commitment of more than 1.3 billion US dollars this decade toward the foundation's agenda…

  3. Penn State DOE GATE Program

    SciTech Connect

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  4. Cooperative gating between ion channels.

    PubMed

    Choi, Kee-Hyun

    2014-01-01

    Cooperative gating between ion channels, i.e. the gating of one channel directly coupled to the gating of neighboring channels, has been observed in diverse channel types at the single-channel level. Positively coupled gating could enhance channel-mediated signaling while negative coupling may effectively reduce channel gating noise. Indeed, the physiological significance of cooperative channel gating in signal transduction has been recognized in several in vivo studies. Moreover, coupled gating of ion channels was reported to be associated with some human disease states. In this review, physiological roles for channel cooperativity and channel clustering observed in vitro and in vivo are introduced, and stimulation-induced channel clustering and direct channel cross linking are suggested as the physical mechanisms of channel assembly. Along with physical clustering, several molecular mechanisms proposed as the molecular basis for functional coupling of neighboring channels are covered: permeant ions as a channel coupling mediator, concerted channel activation through the membrane, and allosteric mechanisms. Also, single-channel analysis methods for cooperative gating such as the binomial analysis, the variance analysis, the conditional dwell time density analysis, and the maximum likelihood fitting analysis are reviewed and discussed.

  5. Mechanically reliable thermoelectric (TE) nanocomposites by dispersing and embedding TE-nanostructures inside a tetragonal ZrO2 matrix: the concept and experimental demonstration in graphene oxide-3YSZ system.

    PubMed

    Estili, Mehdi; Wu, Wen-Wen; Khazaei, Mohammad; Sakka, Yoshio

    2014-02-01

    Novel low-dimensional thermoelectric (TE) materials suffer from poor mechanical reliability, which limits their applications, especially in mechanically harsh environments. Here, we propose a new concept, in which the novel, abundant, thermally stable TE-nanostructures are dispersed and then intimately embedded inside a protective, mechanically reliable tetragonal ZrO2 (TZP) ceramic matrix with a low thermal conductivity. We also demonstrate an experimental proof-of-principle verification of our concept in reduced-graphene oxide (GO)-3 mol% Y2O3-ZrO2 (3YSZ or 3Y-TZP) nanocomposite system. TE characterizations suggest that our protective TZP matrix does not degrade the intrinsic TE property of the reduced GO network. These preliminary results are promising and encouraging to start research on similar TZP-matrix TE-nanocomposites, which contain more effective TE-nanostructures with larger intrinsic power factors. In this regard, we propose a scalable approach for fabrication of similar dense TE-nanocomposites composed of other one-dimensional and/or two-dimensional TE-nanostructures, which involves an aqueous colloidal approach and a subsequent spark plasma sintering. These new TZP-matrix TE-nanocomposites could be used for sustainable clean power generation, especially in mechanically harsh environments with thermal/mechanical shocks and vibrations, where energy availability, reliability and durability are more important than the energy efficiency. Considering the excellent biocompatibility of TZP matrix, they could even be used inside the body to power implanted medical devices.

  6. Pinhole array capacitor for oxide integrity analysis

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Pina, C. A.; Griswold, T. W.

    1983-01-01

    The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

  7. Pinhole array capacitor for oxide integrity analysis

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Pina, C. A.; Griswold, T. W.

    1985-01-01

    The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

  8. Image-guided adaptive gating of lung cancer radiotherapy: a computer simulation study

    NASA Astrophysics Data System (ADS)

    Aristophanous, Michalis; Rottmann, Joerg; Park, Sang-June; Nishioka, Seiko; Shirato, Hiroki; Berbeco, Ross I.

    2010-08-01

    regularity of the breathing pattern suggesting that image-guided adaptive gating should be combined with breath coaching. The adaptive gating window technique was able to track the exhale position of the breathing cycle quite successfully. Out of a total of 53 fractions the duty cycle was greater than 20% for 42 fractions for the fixed gating window technique and for 39 fractions for the adaptive gating window technique. The results of this study suggest that real-time updating of the gating window can result in reliably low residual tumor motion and therefore can facilitate safe margin reduction.

  9. Theory and experiments of electron-hole recombination at silicon/silicon dioxide interface traps and tunneling in thin oxide MOS transistors

    NASA Astrophysics Data System (ADS)

    Cai, Jin

    2000-10-01

    Surface recombination and channel have dominated the electrical characteristics, performance and reliability of p/n junction diodes and transistors. This dissertation uses a sensitive direct-current current voltage (DCIV) method to measure base terminal currents (IB) modulated by the gate bias (VGB) and forward p/n junction bias (VPN) in a MOS transistor (MOST). Base terminal currents originate from electron-hole recombination at Si/SiO2 interface traps. Fundamental theories which relate DCIV characteristics to device and material parameters are presented. Three theory-based applications are demonstrated on both the unstressed as well as hot-carrier-stressed MOSTs: (1) determination of interface trap density and energy levels, (2) spatial profile of interface traps in the drain/base junction-space-charge region and in the channel region, and (3) determination of gate oxide thickness and impurity doping concentrations. The results show that interface trap energy levels are discrete, which is consistent with those from silicon dangling bonds; in unstressed MOS transistors interface trap density in the channel region rises sharply toward source and drain, and after channel-hot-carrier stress, interface trap density increases mostly in the junction space-charge region. As the gate oxide thins below 3 nm, the gate oxide leakage current via quantum mechanical tunneling becomes significant. A gate oxide tunneling theory which refined the traditional WKB tunneling probability is developed for modeling tunneling currents at low electric fields through a trapezoidal SiO2 barrier. Correlation with experimental data on thin oxide MOSTs reveals two new results: (1) hole tunneling dominates over electron tunneling in p+gate p-channel MOSTs, and (2) the small gate/drain overlap region passes higher tunneling currents than the channel region under depletion to flatband gate voltages. The good theory-experimental correlation enables the extraction of impurity doping concentrations

  10. Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

    NASA Astrophysics Data System (ADS)

    Ramezani, Zeinab; Orouji, Ali A.

    2017-04-01

    To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

  11. Development and Application of Tools to Characterize the Oxidative Degradation of AP/HTPB/Al Propellants in a Propellant Reliability Study

    NASA Technical Reports Server (NTRS)

    Celina, Mathew; Minier, Leanna; Assink, Roger

    2000-01-01

    The oxidative thermal aging of a crosslinked hydroxyl-terminated polybutadiene (HTPB)/isophorone diisocyanate (IPDI) polyurethane rubber was studied at temperatures between 25 C and 125 C. Changes in tensile elongation, mechanical hardening, polymer network properties, density, O2 permeation, and molecular chain dynamics were investigated as a function of age. The techniques used include solvent swelling, detailed modulus profiling, and NMR relaxation measurements. The Arrhenius methodology, which normally assumes a linear extrapolation of high temperature aging data, is critically evaluated by using extensive data superposition and highly sensitive oxygen consumption measurements. Significant curvature in the Arrhenius diagram of these oxidation rates is observed to be similar to previous results found for other rubber materials that have been evaluated by this technique. Preliminary gel/network properties suggest that crosslinking is the dominant process at higher temperatures. The effect on the oxidation rate of the binder when other constituents found in propellants are present, such as ammonium perchlorate, plasticizer and aluminum powder, is presented.

  12. Leakage Current and Floating Gate Capacitor Matching Test

    NASA Astrophysics Data System (ADS)

    Tian, Weidong; Trogolo, Joe R.; Todd, Bob

    Capacitor mismatch is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. In this paper we describe the impact of leakage current on the technique. The leakage can come from, for example, thin gate oxide MOSFETs or high dielectric constant capacitors in advanced technologies. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. Criteria for accurate capacitor systematic and random mismatch characterization are developed, and practical methods of increasing measurement accuracy are discussed.

  13. Interfacial reaction and electrical properties of HfO2 film gate dielectric prepared by pulsed laser deposition in nitrogen: role of rapid thermal annealing and gate electrode.

    PubMed

    Wang, Yi; Wang, Hao; Ye, Cong; Zhang, Jun; Wang, Hanbin; Jiang, Yong

    2011-10-01

    The high-k dielectric HfO(2) thin films were deposited by pulsed laser deposition in nitrogen atmosphere. Rapid thermal annealing effect on film surface roughness, structure and electrical properties of HfO(2) film was investigated. The mechanism of interfacial reaction and the annealing atmosphere effect on the interfacial layer thickness were discussed. The sample annealed in nitrogen shows an amorphous dominated structure and the lowest leakage current density. Capacitors with high-k HfO(2) film as gate dielectric were fabricated, using Pt, Au, and Ti as the top gate electrode whereas Pt constitutes the bottom side electrode. At the gate injection case, the Pt- and Au-gated metal oxide semiconductor devices present a lower leakage current than that of the Ti-gated device, as well as similar leakage current conduction mechanism and interfacial properties at the metal/HfO(2) interface, because of their close work function and chemical properties.

  14. Impact of gate geometry on ionic liquid gated ionotronic systems

    DOE PAGES

    Wong, Anthony T.; Noh, Joo Hyon; Pudasaini, Pushpa Raj; ...

    2017-01-23

    Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard “side gate” 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. Finally, these findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

  15. Measurement of ventricular function by ECG gating during atrial fibrillation

    SciTech Connect

    Bacharach, S.L.; Green, M.V.; Bonow, R.O.; Findley, S.L.; Ostrow, H.G.; Johnston, G.S.

    1981-03-01

    The assumptions necessary to perform ECG-gated cardiac studies are seemingly not valid for patients in atrial fibrillation (AF). To evaluate the effect of AF on equilibrium gated scintigraphy, beat-by-beat measurements of left-ventricular function were made on seven subjects in AF (mean heart rate 64 bpm), using a high-efficiency nonimaging detector. The parameters evaluated were ejection fraction (EF), time to end-systole (TES), peak rates of ejection and filling (PER,PFR), and their times of occurrence (TPER, TPFR). By averaging together single-beat values of EF, PER, etc., it was possible to determine the true mean values of these parameters. The single-beam mean values were compared with the corresponding parameters calculated from one ECG-gated time-activity curve (TAC) obtained by superimposing all the single-beat TACs irrespective of their length. For this population with slow heart rates, we find that the values for EF, etc., produced from ECG-gated time-activity curves, are very similar to those obtained from the single-beat data. Thus use of ECG gating at low heart rates may allow reliable estimation of average cardiac function even in subjects with AF.

  16. Tomographic characterization of a linear optical quantum Toffoli gate

    NASA Astrophysics Data System (ADS)

    Mičuda, M.; Miková, M.; Straka, I.; Sedlák, M.; Dušek, M.; Ježek, M.; Fiurášek, J.

    2015-09-01

    We report on a detailed characterization of a three-qubit linear optical quantum Toffoli gate. Our experiment utilizes correlated photon pairs generated in the process of spontaneous parametric down-conversion. Two qubits are encoded into polarization and spatial degrees of freedom of a signal photon, and the third qubit is represented by polarization of an idler photon. The linear optical Toffoli gate is implemented by interference of photons on a partially polarizing beam splitter inserted inside a Mach Zehnder interferometer formed by two calcite beam displacers. We have measured 4032 different two-photon coincidences, which allows us to estimate the fidelity of the gate to be 90%. Although these data are not tomographically complete, we show that they are sufficient for a reliable reconstruction of the quantum process matrix of the gate via the recently proposed maximum likelihood-maximum entropy estimation procedure. To probe the entangling capability of the gate, we have investigated generation of three-qubit GHZ states from fully and partially separable input states and we have performed a full tomography of the output states. We compare the reconstructed states with theoretical predictions obtained with the use of the estimated quantum process matrix and obtain a very good agreement.

  17. MOV reliability evaluation and periodic verification scheduling

    SciTech Connect

    Bunte, B.D.

    1996-12-01

    The purpose of this paper is to establish a periodic verification testing schedule based on the expected long term reliability of gate or globe motor operated valves (MOVs). The methodology in this position paper determines the nominal (best estimate) design margin for any MOV based on the best available information pertaining to the MOVs design requirements, design parameters, existing hardware design, and present setup. The uncertainty in this margin is then determined using statistical means. By comparing the nominal margin to the uncertainty, the reliability of the MOV is estimated. The methodology is appropriate for evaluating the reliability of MOVs in the GL 89-10 program. It may be used following periodic testing to evaluate and trend MOV performance and reliability. It may also be used to evaluate the impact of proposed modifications and maintenance activities such as packing adjustments. In addition, it may be used to assess the impact of new information of a generic nature which impacts safety related MOVs.

  18. MNOS/SOS radiation hardness performance and reliability study

    NASA Astrophysics Data System (ADS)

    Hampton, F. L.; Cricchi, J. R.

    1982-05-01

    In this investigation the endurance-retention characteristics of fast-write MNOS memory structure, and radiation tolerance of metal-gate dual-dielectric and polysilicon-gate all-oxide devices have been evaluated. Writing and clearing speed have been studied with respect to the NH3:SiH4 ratio (APCVD), and NH3:SiC12H2 ratio (LPCVD). The films deposited with a low NH3:SiC12 ratios could be written and cleared with shorter pulse widths; however, a degradation in retention was observed. An improvement in the endurance retention product of a drain source protected transistor structure has been realized by oxidizing the memory nitride followed by an H2 anneal immediately after deposition. The film was deposited with a LPCVD reactor at 750 deg with a NH3:SiC12H2 ratio of 9:1. Oxidation was performed in steam at 900 C, as was the subsequent H2 anneal. The effect of total dose radiation was found to be more severe for a positive bias. The all oxide polysilicon gate transistor structures were observed to be relatively soft, however results from capacitor structures shows promise in developing a radiation tolerant polysilicon-gate all-oxide gate structure.

  19. Robust Soldier Crab Ball Gate

    NASA Astrophysics Data System (ADS)

    Gunji, Yukio-Pegio; Nishiyama, Yuta; Adamatzky, Andrew

    2011-09-01

    Based on the field observation of soldier crabs, we previously proposed a model for a swarm of soldier crabs. Here, we describe the interaction of coherent swarms in the simulation model, which is implemented in a logical gate. Because a swarm is generated by inherent perturbation, a swarm can be generated and maintained under highly perturbed conditions. Thus, the model reveals a robust logical gate rather than stable one. In addition, we show that the logical gate of swarms is also implemented by real soldier crabs (Mictyris guinotae).

  20. Superconducting gates with fluxon logics

    NASA Astrophysics Data System (ADS)

    Nacak, H.; Kusmartsev, F. V.

    2010-10-01

    We have developed several logic gates (OR, XOR, AND and NAND) made of superconducting Josephson junctions. The gates based of the flux cloning phenomenon and high speed of fluxons moving in Josephson junctions of different shapes. In a contrast with previous design the gates operates extremely fast since fluxons are moving with the speed close to the speed of light. We have demonstrated their operations and indicated several ways to made a more complicated logic elements which have at the same time a compact form.

  1. Commentary on WHO GATE Initiative.

    PubMed

    Cooper, Rory A

    2017-01-01

    Assistive technology is essential to people with spinal cord injuries (SCI) for living and participating in their communities. However, many people with SCI do not have access to adequate assistive technology and qualified services. The World Health Organization (WHO) is addressing this need through the Global Cooperation on Assistive Technology (GATE). The GATE initiative is focused on improving access to high-quality affordable AT world-wide. GATE working to meet the AT sector needs in response to the call by WHO to increase access to essential, high-quality, safe, effective and affordable medical devices, which is one of the six WHO leadership priorities.

  2. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se2 thin-film solar cell absorbers

    NASA Astrophysics Data System (ADS)

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-01

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for "realistic" surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In1-xGax)Se2 thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH3-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is - apart from a slight change in surface composition - identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  3. Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

    PubMed Central

    Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

    2013-01-01

    A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

  4. Characteristics of LaAlO3 gate dielectrics on Si grown by metalorganic chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Li, Ai-Dong; Shao, Qi-Yue; Ling, Hui-Qin; Cheng, Jin-Bo; Wu, Di; Liu, Zhi-Guo; Ming, Nai-Ben; Wang, Cathy; Zhou, Hong-Wei; Nguyen, Bich-Yen

    2003-10-01

    Amorphous LaAlO3 (LAO) gate dielectric thin films have been deposited on Si substrates using La(dpm)3 and Al(acac)3 sources by low-pressure metalorganic chemical vapor deposition. The growth mechanism, interfacial structure, and electrical properties have been investigated by various techniques. The ultrathin films show smaller roughness of ˜0.3 nm, larger band gap of 6.47 eV, and good thermal stability. The growth follows a chemical dynamic control mechanism. High-resolution transmission electron microscopy confirms there exists no interfacial layer, or only thinner ones, between LAO and Si. X-ray photoelectron spectroscopy analyses reveal that the thinner interfacial layer is compositionally graded La-Al-Si-O silicate and Al element is deficient in the interfacial layer. The reliable value of equivalent oxide thickness around 1.2 nm of LAO/Si has been achieved.

  5. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  6. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  7. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  8. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm. 234.223 Section 234.223 Transportation... Maintenance Standards § 234.223 Gate arm. Each gate arm, when in the downward position, shall extend across... clearly viewed by approaching highway users. Each gate arm shall start its downward motion not less...

  9. 49 CFR 234.223 - Gate arm.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm. 234.223 Section 234.223 Transportation... SYSTEMS Maintenance, Inspection, and Testing Maintenance Standards § 234.223 Gate arm. Each gate arm, when... maintained in a condition sufficient to be clearly viewed by approaching highway users. Each gate arm...

  10. Ion polarization behavior in alumina under pulsed gate bias stress

    NASA Astrophysics Data System (ADS)

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-01

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K+), sodium (Na+), and lithium (Li+), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔVth) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔVth over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔVth from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  11. Ion polarization behavior in alumina under pulsed gate bias stress

    SciTech Connect

    Liu, Yu; Diallo, Abdou Karim; Katz, Howard E.

    2015-03-16

    Alkali metal ion incorporation in alumina significantly increases alumina capacitance by ion polarization. With high capacitance, ion-incorporated aluminas become promising high dielectric constant (high-k) gate dielectric materials in field-effect transistors (FETs) to enable reduced operating voltage, using oxide or organic semiconductors. Alumina capacitance can be manipulated by incorporation of alkali metal ions, including potassium (K{sup +}), sodium (Na{sup +}), and lithium (Li{sup +}), having different bond strengths with oxygen. To investigate the electrical stability of zinc tin oxide-based transistors using ion incorporated alumina as gate dielectrics, pulsed biases at different duty cycles (20%, 10%, and 2% representing 5 ms, 10 ms, and 50 ms periods, respectively) were applied to the gate electrode, sweeping the gate voltage over series of these cycles. We observed a particular bias stress-induced decrease of saturation field-effect mobility accompanied by threshold voltage shifts (ΔV{sub th}) in potassium and sodium-incorporated alumina (abbreviated as PA and SA)-based FETs at high duty cycle that persisted over multiple gate voltage sweeps, suggesting a possible creation of new defects in the semiconductor. This conclusion is also supported by the greater change in the mobility-capacitance (μC) product than in capacitance itself. Moreover, a more pronounced ΔV{sub th} over shorter times was observed in lithium-incorporated alumina (abbreviated as LA)-based transistors, suggesting trapping of electrons in existing interfacial states. ΔV{sub th} from multiple gate voltage sweeps over time were fit to stretched exponential forms. All three dielectrics show good stability using 50-ms intervals (20-Hz frequencies), corresponding to 2% duty cycles.

  12. A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

    NASA Astrophysics Data System (ADS)

    Xu, Gao-Bo; Xu, Qiu-Xia; Yin, Hua-Xiang; Zhou, Hua-Jie; Yang, Tao; Niu, Jie-Bin; Yu, Jia-Han; Li, Jun-Feng; Zhao, Chao

    2013-11-01

    A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device's gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS = VDS = 1.5 V and the off-state current is only 4.4 nA/μm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (~ 0.24 V) for high performance NMOSFETs. The device's excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

  13. Persistent optical gating of a topological insulator

    PubMed Central

    Yeats, Andrew L.; Pan, Yu; Richardella, Anthony; Mintun, Peter J.; Samarth, Nitin; Awschalom, David D.

    2015-01-01

    The spin-polarized surface states of topological insulators (TIs) are attractive for applications in spintronics and quantum computing. A central challenge with these materials is to reliably tune the chemical potential of their electrons with respect to the Dirac point and the bulk bands. We demonstrate persistent, bidirectional optical control of the chemical potential of (Bi,Sb)2Te3 thin films grown on SrTiO3. By optically modulating a space-charge layer in the SrTiO3 substrates, we induce a persistent field effect in the TI films comparable to electrostatic gating techniques but without additional materials or processing. This enables us to optically pattern arbitrarily shaped p- and n-type regions in a TI, which we subsequently image with scanning photocurrent microscopy. The ability to optically write and erase mesoscopic electronic structures in a TI may aid in the investigation of the unique properties of the topological insulating phase. The gating effect also generalizes to other thin-film materials, suggesting that these phenomena could provide optical control of chemical potential in a wide range of ultrathin electronic systems. PMID:26601300

  14. Reliable wet-chemical cleaning of natively oxidized high-efficiency Cu(In,Ga)Se{sub 2} thin-film solar cell absorbers

    SciTech Connect

    Lehmann, Jascha; Lehmann, Sebastian; Lauermann, Iver; Rissom, Thorsten; Kaufmann, Christian A.; Lux-Steiner, Martha Ch.; Bär, Marcus; Sadewasser, Sascha

    2014-12-21

    Currently, Cu-containing chalcopyrite-based solar cells provide the highest conversion efficiencies among all thin-film photovoltaic (PV) technologies. They have reached efficiency values above 20%, the same performance level as multi-crystalline silicon-wafer technology that dominates the commercial PV market. Chalcopyrite thin-film heterostructures consist of a layer stack with a variety of interfaces between different materials. It is the chalcopyrite/buffer region (forming the p-n junction), which is of crucial importance and therefore frequently investigated using surface and interface science tools, such as photoelectron spectroscopy and scanning probe microscopy. To ensure comparability and validity of the results, a general preparation guide for “realistic” surfaces of polycrystalline chalcopyrite thin films is highly desirable. We present results on wet-chemical cleaning procedures of polycrystalline Cu(In{sub 1-x}Ga{sub x})Se{sub 2} thin films with an average x = [Ga]/([In] + [Ga]) = 0.29, which were exposed to ambient conditions for different times. The hence natively oxidized sample surfaces were etched in KCN- or NH{sub 3}-based aqueous solutions. By x-ray photoelectron spectroscopy, we find that the KCN treatment results in a chemical surface structure which is – apart from a slight change in surface composition – identical to a pristine as-received sample surface. Additionally, we discover a different oxidation behavior of In and Ga, in agreement with thermodynamic reference data, and we find indications for the segregation and removal of copper selenide surface phases from the polycrystalline material.

  15. The Gates, 1979-2005

    ERIC Educational Resources Information Center

    School Arts: The Art Education Magazine for Teachers, 2005

    2005-01-01

    One art critic called it pure Despite the mixed reviews of Christo and Jeanne-Claude's temporary art installation in New York's Central Park, the public reaction to The Gates was largely positive.The Gates consisted of 7,500 orange PVC frames straddling the park's walkways that varied in widths from 5 1/2 feet to 18 feet. Eight-foot-long ripstop…

  16. Quantum gates with topological phases

    SciTech Connect

    Ionicioiu, Radu

    2003-09-01

    We investigate two models for performing topological quantum gates with the Aharonov-Bohm (AB) and Aharonov-Casher (AC) effects. Topological one- and two-qubit Abelian phases can be enacted with the AB effect using charge qubits, whereas the AC effect can be used to perform all single-qubit gates (Abelian and non-Abelian) for spin qubits. Possible experimental setups suitable for a solid-state implementation are briefly discussed.

  17. MNOS stack for reliable, low optical loss, Cu based CMOS plasmonic devices.

    PubMed

    Emboras, Alexandros; Najar, Adel; Nambiar, Siddharth; Grosse, Philippe; Augendre, Emmanuel; Leroux, Charles; de Salvo, Barbara; de Lamaestre, Roch Espiau

    2012-06-18

    We study the electro optical properties of a Metal-Nitride-Oxide-Silicon (MNOS) stack for a use in CMOS compatible plasmonic active devices. We show that the insertion of an ultrathin stoichiometric Si(3)N(4) layer in a MOS stack lead to an increase in the electrical reliability of a copper gate MNOS capacitance from 50 to 95% thanks to a diffusion barrier effect, while preserving the low optical losses brought by the use of copper as the plasmon supporting metal. An experimental investigation is undertaken at a wafer scale using some CMOS standard processes of the LETI foundry. Optical transmission measurments conducted in a MNOS channel waveguide configuration coupled to standard silicon photonics circuitry confirms the very low optical losses (0.39 dB.μm(-1)), in good agreement with predictions using ellipsometric optical constants of Cu.

  18. Latest design of gate valves

    SciTech Connect

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  19. Graphical workstation capability for reliability modeling

    NASA Technical Reports Server (NTRS)

    Bavuso, Salvatore J.; Koppen, Sandra V.; Haley, Pamela J.

    1992-01-01

    In addition to computational capabilities, software tools for estimating the reliability of fault-tolerant digital computer systems must also provide a means of interfacing with the user. Described here is the new graphical interface capability of the hybrid automated reliability predictor (HARP), a software package that implements advanced reliability modeling techniques. The graphics oriented (GO) module provides the user with a graphical language for modeling system failure modes through the selection of various fault-tree gates, including sequence-dependency gates, or by a Markov chain. By using this graphical input language, a fault tree becomes a convenient notation for describing a system. In accounting for any sequence dependencies, HARP converts the fault-tree notation to a complex stochastic process that is reduced to a Markov chain, which it can then solve for system reliability. The graphics capability is available for use on an IBM-compatible PC, a Sun, and a VAX workstation. The GO module is written in the C programming language and uses the graphical kernal system (GKS) standard for graphics implementation. The PC, VAX, and Sun versions of the HARP GO module are currently in beta-testing stages.

  20. Gate Last Indium-Gallium-Arsenide MOSFETs with Regrown Source-Drain Regions and ALD Dielectrics

    NASA Astrophysics Data System (ADS)

    Carter, Andrew Daniel

    III-V-based MOSFETs have the potential to exceed the performance of silicon-based MOSFETs due to the semiconductor's small electron effective mass. Modern silicon-based MOSFETs with 22 nm gate lengths utilize high-k gate insulators and non-planar device geometries to optimize device performance. III-V HEMT technology has achieved similar gate lengths, but large source-drain access resistances and the lack of high-quality gate insulators prevent further device performance scaling. Sub-22 nm gate length III-V MOSFETs require metal-semiconductor contact resistivity to be less than 1 ohm-micron squared, gate insulators with less than 1 nm effective oxide thickness, and semiconductor-insulator interface trap densities less than 2E12 per square centimeter per electron volt. This dissertation presents InGaAs-based III-V MOSFET process flows and device results to assess their use in VLSI circuits. Previous III-V MOSFET results focused on long (>100 nm) gate lengths and ion implantation for source-drain region formation. Scaling III-V MOSFETs to shorter gate lengths requires source-drain regions that have low sheet resistance, high mobile charge densities, and low metal-semiconductor contact resistance. MBE- and MOCVD-based raised epitaxial source-drain regrowth meet these requirements. MBE InAs source-drain regrowth samples have shown 0.5 to 2 ohm-micron squared metal semiconductor contact resistivities. MOCVD InGaAs source-drain regrowth samples have shown < 100 ohm-micron single-sided access resistance to InGaAs MOSFETs. Gate insulators on III-V materials require large conduction band offsets to the channel, high dielectric permittivities, and low semiconductor-insulator interface trap densities. An in-situ hydrogen plasma / trimethylaluminum treatment has been developed to lower the gate semiconductor-insulator interface trap density. This treatment, done immediately before gate insulator deposition, has been shown to lower MOS capacitor interface trap densities by more

  1. Redox Regulation of Neuronal Voltage-Gated Calcium Channels

    PubMed Central

    Jevtovic-Todorovic, Vesna

    2014-01-01

    Abstract Significance: Voltage-gated calcium channels are ubiquitously expressed in neurons and are key regulators of cellular excitability and synaptic transmitter release. There is accumulating evidence that multiple subtypes of voltage-gated calcium channels may be regulated by oxidation and reduction. However, the redox mechanisms involved in the regulation of channel function are not well understood. Recent Advances: Several studies have established that both T-type and high-voltage-activated subtypes of voltage-gated calcium channel can be redox-regulated. This article reviews different mechanisms that can be involved in redox regulation of calcium channel function and their implication in neuronal function, particularly in pain pathways and thalamic oscillation. Critical Issues: A current critical issue in the field is to decipher precise mechanisms of calcium channel modulation via redox reactions. In this review we discuss covalent post-translational modification via oxidation of cysteine molecules and chelation of trace metals, and reactions involving nitric oxide-related molecules and free radicals. Improved understanding of the roles of redox-based reactions in regulation of voltage-gated calcium channels may lead to improved understanding of novel redox mechanisms in physiological and pathological processes. Future Directions: Identification of redox mechanisms and sites on voltage-gated calcium channel may allow development of novel and specific ion channel therapies for unmet medical needs. Thus, it may be possible to regulate the redox state of these channels in treatment of pathological process such as epilepsy and neuropathic pain. Antioxid. Redox Signal. 21, 880–891. PMID:24161125

  2. Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

    PubMed

    Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

    2015-08-01

    In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis.

  3. Brain anatomy and sensorimotor gating in Asperger's syndrome.

    PubMed

    McAlonan, Grainne M; Daly, Eileen; Kumari, Veena; Critchley, Hugo D; van Amelsvoort, Therese; Suckling, John; Simmons, Andrew; Sigmundsson, Thordur; Greenwood, Kathyrn; Russell, Ailsa; Schmitz, Nicole; Happe, Francesca; Howlin, Patricia; Murphy, Declan G M

    2002-07-01

    Asperger's syndrome (an autistic disorder) is characterized by stereotyped and obsessional behaviours, and pervasive abnormalities in socio-emotional and communicative behaviour. These symptoms lead to social exclusion and a significant healthcare burden; however, their neurobiological basis is poorly understood. There are few studies on brain anatomy of Asperger's syndrome, and no focal anatomical abnormality has been reliably reported from brain imaging studies of autism, although there is increasing evidence for differences in limbic circuits. These brain regions are important in sensorimotor gating, and impaired 'gating' may partly explain the failure of people with autistic disorders to inhibit repetitive thoughts and actions. Thus, we compared brain anatomy and sensorimotor gating in healthy people with Asperger's syndrome and controls. We included 21 adults with Asperger's syndrome and 24 controls. All had normal IQ and were aged 18-49 years. We studied brain anatomy using quantitative MRI, and sensorimotor gating using prepulse inhibition of startle in a subset of 12 individuals with Asperger's syndrome and 14 controls. We found significant age-related differences in volume of cerebral hemispheres and caudate nuclei (controls, but not people with Asperger's syndrome, had age-related reductions in volume). Also, people with Asperger's syndrome had significantly less grey matter in fronto-striatal and cerebellar regions than controls, and widespread differences in white matter. Moreover, sensorimotor gating was significantly impaired in Asperger's syndrome. People with Asperger's syndrome most likely have generalized alterations in brain development, but this is associated with significant differences from controls in the anatomy and function of specific brain regions implicated in behaviours characterizing the disorder. We hypothesize that Asperger's syndrome is associated with abnormalities in fronto-striatal pathways resulting in defective sensorimotor

  4. The impact of cardiac gating on the detection of coronary calcifications in dual-energy chest radiography: a phantom study

    NASA Astrophysics Data System (ADS)

    Sabol, John M.; Liu, Ray; Saunders, Rowland; Markley, Jonathan; Moreno, Nery; Seamans, John; Wiese, Scott; Jabri, Kadri; Gilkeson, Robert C.

    2006-03-01

    The detection of coronary calcifications with CT is generally accepted as a useful method for predicting early onset of coronary artery disease. Film-screen X-ray and fluoroscopy have also been shown to have high predictive value for coronary disease diagnosis, but have minimal sensitivity. Recently, flat-panel detectors capable of dual-energy techniques have enabled the separation of soft-tissue and bone from images. Clinical studies report substantially improved sensitivity for the detection of coronary calcifications using these techniques. However, heart motion causes minor artefacts from misregistration of both calcified and soft-tissue structures, resulting in inconsistent detection of calcifications. This research examines whether cardiac gating improves the reliability of calcification detection. Single-energy, gated, and non-gated dual-energy imaging techniques are examined in a dynamic phantom model. A gating system was developed to synchronize two dual-energy exposures to a specified phase of the cardiac cycle. The performance and repeatability of the gating system was validated with the use of a cyclical phantom. An anthropomorphic phantom was developed to simulate both cardiac and soft-tissue motion, and generate ECG-like output signals. The anthropomorphic phantom and motion artefact accuracy was verified by comparison with clinical images of patients with calcifications. The ability of observers to detect calcifications in non-gated, and gated techniques was compared through the use of an ROC experiment. Gating visibly reduces the effect of motion artifacts in the dual-energy images. Without gating, motion artefacts cause greater variability in calcification detection. Comparison of the average area-under-the-curve of the ROC curves show that gating significantly increases the accuracy of calcification detection. The effects of motion and gating on DE cardiac calcification detection have been demonstrated and characterized in a phantom model that

  5. Quantum gate-set tomography

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    2014-03-01

    Quantum information technology is built on (1) physical qubits and (2) precise, accurate quantum logic gates that transform their states. Developing quantum logic gates requires good characterization - both in the development phase, where we need to identify a device's flaws so as to fix them, and in the production phase, where we need to make sure that the device works within specs and predict residual error rates and types. This task falls to quantum state and process tomography. But until recently, protocols for tomography relied on a pre-existing and perfectly calibrated reference frame comprising the measurements (and, for process tomography, input states) used to characterize the device. In practice, these measurements are neither independent nor perfectly known - they are usually implemented via exactly the same gates that we are trying to characterize! In the past year, several partial solutions to this self-consistency problem have been proposed. I will present a framework (gate set tomography, or GST) that addresses and resolves this problem, by self-consistently characterizing an entire set of quantum logic gates on a black-box quantum device. In particular, it contains an explicit closed-form protocol for linear-inversion gate set tomography (LGST), which is immune to both calibration error and technical pathologies like local maxima of the likelihood (which plagued earlier methods). GST also demonstrates significant (multiple orders of magnitude) improvements in efficiency over standard tomography by using data derived from long sequences of gates (much like randomized benchmarking). GST has now been applied to qubit devices in multiple technologies. I will present and discuss results of GST experiments in technologies including a single trapped-ion qubit and a silicon quantum dot qubit. Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U

  6. An investigation into the reliability of the silicon dioxide/silicon carbide material system

    NASA Astrophysics Data System (ADS)

    Maranowski, Michelle Mathur

    1998-12-01

    The goal of this thesis is to determine the reliability of thermally grown oxide films on SiC. The necessity of performing reliability measurements is to be able to design and fabricate power MOSFETS. Reliability testing occurs under accelerated temperature and field conditions. This allows extrapolation of the data to at-use conditions. This is the first time that a set of comprehensive reliability measurements is taken on the SiC semiconductor. Using the constant voltage stress test technique, time dependent dielectric breakdown (TDDB) measurements are made on both n-type and p-type 6H SiC capacitors. Preliminary measurements are also made on 4H SiC capacitors. The purpose of taking TDDB scans on both n-type and p-type substrates is to understand how the polarity of charge injection affects the reliability of the oxide. TDDB measurements are made at three temperatures(145 C, 240 C, and 305 C) and three or four field values. All measurements are made in accumulation mode so that the applied voltage drops across the oxide only. The results show failure for thermally grown oxides on SiC is multi-modal, consisting of a two part extrinsic failure mode and an intrinsic failure mode. Extrapolation of the intrinsic n-type data taken at 145 C shows that the tsb{50%} at 3 MV/cm is approximately 2,000,000 years. The extrapolation of the extrinsic data shows that tsb{50%} is 10 years. At higher temperatures tsb{50%} decreases for both extrinsic and intrinsic failures. As expected, the activation energy for the extrinsic failures is less than that of the intrinsic failures. This confirms that the mechanism of failure between the two modes differs. In the p-type configuration, charge is injected from the gate into the oxide. This proves to be less damaging than injecting from the semiconductor. The p-type data also varies from the n-type data in the fact that the p-type devices fail slower. As a result, the extrapolation to at-use conditions for p-type data is longer than the

  7. Reliability model generator

    NASA Technical Reports Server (NTRS)

    McMann, Catherine M. (Inventor); Cohen, Gerald C. (Inventor)

    1991-01-01

    An improved method and system for automatically generating reliability models for use with a reliability evaluation tool is described. The reliability model generator of the present invention includes means for storing a plurality of low level reliability models which represent the reliability characteristics for low level system components. In addition, the present invention includes means for defining the interconnection of the low level reliability models via a system architecture description. In accordance with the principles of the present invention, a reliability model for the entire system is automatically generated by aggregating the low level reliability models based on the system architecture description.

  8. Prospectively gated cardiac computed tomography.

    PubMed

    Moore, S C; Judy, P F; Garnic, J D; Kambic, G X; Bonk, F; Cochran, G; Margosian, P; McCroskey, W; Foote, F

    1983-01-01

    A fourth-generation scanner has been modified to perform prospectively gated cardiac computed tomography (CT). A computer program monitors the electrocardiogram (ECG) and predicts when to initiate the next scan in a gated series in order to acquire all projection data for a desired phase of the heart cycle. The system has been tested with dogs and has produced cross-sectional images of all phases of the cardiac cycle. Eight to ten scans per series were sufficient to obtain reproducible images of each transverse section in the end-diastolic and end-systolic phases. The radiation dose to the skin was approximately 1.4 cGy per scan. The prospectively gated system is more than twice as efficient as a retrospectively gated system in obtaining complete angular projection data for a 10% heart cycle window. A temporal smoothing technique to suppress reconstruction artifacts due to sorting inconsistent projection data was developed and evaluated. Image noise was reduced by averaging together any overlapping projection data. Prospectively gated cardiac CT has also been used to demonstrate that the error in attenuation measured with a single nongated CT scan through the heart can be as large as 50-60 CT numbers outside the heart in the lung field.

  9. Gate-controlled conductance switching in DNA

    PubMed Central

    Xiang, Limin; Palma, Julio L.; Li, Yueqi; Mujica, Vladimiro; Ratner, Mark A.; Tao, Nongjian

    2017-01-01

    Extensive evidence has shown that long-range charge transport can occur along double helical DNA, but active control (switching) of single-DNA conductance with an external field has not yet been demonstrated. Here we demonstrate conductance switching in DNA by replacing a DNA base with a redox group. By applying an electrochemical (EC) gate voltage to the molecule, we switch the redox group between the oxidized and reduced states, leading to reversible switching of the DNA conductance between two discrete levels. We further show that monitoring the individual conductance switching allows the study of redox reaction kinetics and thermodynamics at single molecular level using DNA as a probe. Our theoretical calculations suggest that the switch is due to the change in the energy level alignment of the redox states relative to the Fermi level of the electrodes. PMID:28218275

  10. Gate-controlled conductance switching in DNA

    NASA Astrophysics Data System (ADS)

    Xiang, Limin; Palma, Julio L.; Li, Yueqi; Mujica, Vladimiro; Ratner, Mark A.; Tao, Nongjian

    2017-02-01

    Extensive evidence has shown that long-range charge transport can occur along double helical DNA, but active control (switching) of single-DNA conductance with an external field has not yet been demonstrated. Here we demonstrate conductance switching in DNA by replacing a DNA base with a redox group. By applying an electrochemical (EC) gate voltage to the molecule, we switch the redox group between the oxidized and reduced states, leading to reversible switching of the DNA conductance between two discrete levels. We further show that monitoring the individual conductance switching allows the study of redox reaction kinetics and thermodynamics at single molecular level using DNA as a probe. Our theoretical calculations suggest that the switch is due to the change in the energy level alignment of the redox states relative to the Fermi level of the electrodes.

  11. Advances in the metallurgical design of gate valves

    SciTech Connect

    Hays, C.

    1995-12-31

    Reliability and cost factors represent the two controlling forces for gate valves that contain state-of-the-art metallurgical improvements. Better and less-expensive gate valves are always in demand for the oil and gas or petrochemically-related industries. In this very specialized marketplace, environmental conditions are always the primary design challenge because service requirements typically involve high temperature, elevated pressure, extreme corrosion or erosion. A proper design selection for extended life under such harsh service will always involve the surface integrity for all effluent-wetted gate valve components. This paper gives a brief survey of gate valves in terms of the different design approaches that are used for oilfield and refinery applications. However, the main interest of this paper is devoted to modern surface treatment methods that enhance a cost attractive substrate to achieve a competitive and duplex or composite structure. For example, innovative processes are discussed relative to plating, hardfacing, thermal spray, conversion coatings, spray-fusion, weld-clad and HIC-ing.

  12. Body factor conscious modeling of single gate fully depleted SOI MOSFETs for low power applications

    NASA Astrophysics Data System (ADS)

    Kumar, Anil; Nagumo, Toshiharu; Tsutsui, Gen; Ohtou, Tetsu; Hiramoto, Toshiro

    2005-06-01

    Degradation of body factor (γ) and subthreshold factor (S) of single gate fully depleted SOI MOSFETs due to short channel effects has been studied analytically. The effect of source/drain fringing fields in buried oxide is found to play a more significant role in the reduction of body factor at smaller gate lengths. Present work provides the analytical expressions of effective back gate voltage, body factor and subthreshold factor of short channel fully depleted SOI MOSFETs. The results obtained are found in good approximation with 2D simulation.

  13. Self-Aligned ALD AlOx T-gate Insulator for Gate Leakage Current Suppression in SiNx-Passivated AlGaN/GaN HEMTs

    DTIC Science & Technology

    2010-01-01

    blanket-deposited between the source and drain, as has been demonstrated by Ye et al. [21]. Similiarly, Saadat and co-workers have used ALD-deposited HfOx...been reported previously by Saadat et al. [22] and noted to be indicative of slow trapping centers in the oxide and at the oxide/semiconductor...gate dielectric. Appl Phys Lett 2005;86:063501–3. [22] Saadat OI, Chung JW, Piner EL, Palacios T. Gate-first AlGaN/GaN HEMT technology for high-frequency

  14. Controlled ambient and temperature treatment of InGaZnO thin film transistors for improved bias-illumination stress reliability

    SciTech Connect

    Vemuri, Rajitha N. P.; Hasin, Muhammad R.; Alford, T. L.

    2014-03-15

    The failure mechanisms arising from the instability in operation of indium gallium zinc oxide based thin film transistors (TFTs) upon prolonged real application stresses (bias and illumination) have been extensively studied and reported. Positive and negative gate bias conditions, along with high photonic energy wavelengths within visible light spectrum are used as stress conditions. The increased carrier concentration due to photonic excitation of defects within bandgap and ionization of deep level vacancies is compensated by the reduction in off currents under illumination due to the trapping of carriers in the intermetal dielectric. Band lowering at the source-channel junction due to accumulation of negative carriers repelled due to negative gate bias stress further causes high carrier flow into the channel and drives the devices into failure. The defect identification during failure and degradation assisted in proposing suitable low temperature post processing in specific ambients. Reliability tests after specific anneals in oxygen, vacuum, and forming gas ambients confirm the correlation of the defect type with anneal ambient. Annealed TFTs demonstrate high stabilities under illumination stresses and do not fail when subjected to combined stresses that cause failure in as-fabricated TFTs. Oxygen and forming gas anneals are impactful on the reliability and opens an area of study on donor and vacancy behavior in amorphous mixed oxide based TFTs. The subthreshold swing, field-effect mobilities, and off currents provide knowledge on best anneal practices by understanding role of hydrogen and oxygen in vacancy annihilation and transistor switching properties.

  15. Positive-bias gate-controlled metal–insulator transition in ultrathin VO2 channels with TiO2 gate dielectrics

    PubMed Central

    Yajima, Takeaki; Nishimura, Tomonori; Toriumi, Akira

    2015-01-01

    The next generation of electronics is likely to incorporate various functional materials, including those exhibiting ferroelectricity, ferromagnetism and metal–insulator transitions. Metal–insulator transitions can be controlled by electron doping, and so incorporating such a material in transistor channels will enable us to significantly modulate transistor current. However, such gate-controlled metal–insulator transitions have been challenging because of the limited number of electrons accumulated by gate dielectrics, or possible electrochemical reaction in ionic liquid gate. Here we achieve a positive-bias gate-controlled metal–insulator transition near the transition temperature. A significant number of electrons were accumulated via a high-permittivity TiO2 gate dielectric with subnanometre equivalent oxide thickness in the inverse-Schottky-gate geometry. An abrupt transition in the VO2 channel is further exploited, leading to a significant current modulation far beyond the capacitive coupling. This solid-state operation enables us to discuss the electrostatic mechanism as well as the collective nature of gate-controlled metal–insulator transitions, paving the pathway for developing functional field effect transistors. PMID:26657761

  16. Ionic thermoelectric gating organic transistors

    PubMed Central

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (∼100 μV K−1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (∼10,000 μV K−1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins. PMID:28139738

  17. Ionic thermoelectric gating organic transistors

    NASA Astrophysics Data System (ADS)

    Zhao, Dan; Fabiano, Simone; Berggren, Magnus; Crispin, Xavier

    2017-01-01

    Temperature is one of the most important environmental stimuli to record and amplify. While traditional thermoelectric materials are attractive for temperature/heat flow sensing applications, their sensitivity is limited by their low Seebeck coefficient (~100 μV K-1). Here we take advantage of the large ionic thermoelectric Seebeck coefficient found in polymer electrolytes (~10,000 μV K-1) to introduce the concept of ionic thermoelectric gating a low-voltage organic transistor. The temperature sensing amplification of such ionic thermoelectric-gated devices is thousands of times superior to that of a single thermoelectric leg in traditional thermopiles. This suggests that ionic thermoelectric sensors offer a way to go beyond the limitations of traditional thermopiles and pyroelectric detectors. These findings pave the way for new infrared-gated electronic circuits with potential applications in photonics, thermography and electronic-skins.

  18. Quantum gates by periodic driving

    PubMed Central

    Shi, Z. C.; Wang, W.; Yi, X. X.

    2016-01-01

    Topological quantum computation has been extensively studied in the past decades due to its robustness against decoherence. One way to realize the topological quantum computation is by adiabatic evolutions—it requires relatively long time to complete a gate, so the speed of quantum computation slows down. In this work, we present a method to realize single qubit quantum gates by periodic driving. Compared to adiabatic evolution, the single qubit gates can be realized at a fixed time much shorter than that by adiabatic evolution. The driving fields can be sinusoidal or square-well field. With the sinusoidal driving field, we derive an expression for the total operation time in the high-frequency limit, and an exact analytical expression for the evolution operator without any approximations is given for the square well driving. This study suggests that the period driving could provide us with a new direction in regulations of the operation time in topological quantum computation. PMID:26911900

  19. Analysis of optical parity gates of generating Bell state for quantum information and secure quantum communication via weak cross-Kerr nonlinearity under decoherence effect

    NASA Astrophysics Data System (ADS)

    Heo, Jino; Hong, Chang-Ho; Yang, Hyung-Jin; Hong, Jong-Phil; Choi, Seong-Gon

    2017-04-01

    We demonstrate the advantages of an optical parity gate using weak cross-Kerr nonlinearities (XKNLs), quantum bus (qubus) beams, and photon number resolving (PNR) measurement through our analysis, utilizing a master equation under the decoherence effect (occurred the dephasing and photon loss). To generate Bell states, parity gates based on quantum non-demolition measurement using XKNL are extensively employed in quantum information processing. When designing a parity gate via XKNL, the parity gate can be diversely constructed according to the measurement strategies. In practice, the interactions of XKNLs in optical fiber are inevitable under the decoherence effect. Thus, by our analysis of the decoherence effect, we show that the designed parity gate employing homodyne measurement would not be expected to provide reliable quantum operation. Furthermore, compared with a parity gate using a displacement operator and PNR measurement, we conclude there is experimental benefit from implementation of a parity gate via qubus beams and PNR measurement under the decoherence effect.

  20. Abnormal degradation of high-voltage p-type MOSFET with n+ polycrystalline silicon gate during AC stress

    NASA Astrophysics Data System (ADS)

    Lee, Dongjun; Joo, Ikhyung; Lee, Changsub; Song, Duheon; Choi, Byoungdeog

    2016-11-01

    We investigated the abnormal degradation of high-voltage p-type MOSFET (HV pMOSFET) under negative AC gate bias stress. In HV pMOSFET with n+ polycrystalline silicon (poly-Si) gate, the abnormal degradation occurs after the gradual degradation during negative AC stress. The abnormal degradation is suppressed by changing the gate material from n+ poly-Si to p+ poly-Si, and it is caused by hot holes produced by the impact ionization near the surface when electrons move from the gate toward the gate oxide. We suggest a possible mechanism to explain the improvement of degradation by using p+ poly-Si as a gate material.

  1. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Yu, Ai-Fang; Qi, Qiong; Jiang, Peng; Jiang, Chao

    2009-07-01

    Carrier mobility enhancement from 0.09 to 0.59 cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  2. Localizing a gate in CFTR

    PubMed Central

    Gao, Xiaolong; Hwang, Tzyh-Chang

    2015-01-01

    Experimental and computational studies have painted a picture of the chloride permeation pathway in cystic fibrosis transmembrane conductance regulator (CFTR) as a short narrow tunnel flanked by wider inner and outer vestibules. Although these studies also identified a number of transmembrane segments (TMs) as pore-lining, the exact location of CFTR’s gate(s) remains unknown. Here, using a channel-permeant probe, [Au(CN)2]−, we provide evidence that CFTR bears a gate that coincides with the predicted narrow section of the pore defined as residues 338–341 in TM6. Specifically, cysteines introduced cytoplasmic to the narrow region (i.e., positions 344 in TM6 and 1148 in TM12) can be modified by intracellular [Au(CN)2]− in both open and closed states, corroborating the conclusion that the internal vestibule does not harbor a gate. However, cysteines engineered to positions external to the presumed narrow region (e.g., 334, 335, and 337 in TM6) are all nonreactive toward cytoplasmic [Au(CN)2]− in the absence of ATP, whereas they can be better accessed by extracellular [Au(CN)2]− when the open probability is markedly reduced by introducing a second mutation, G1349D. As [Au(CN)2]− and chloride ions share the same permeation pathway, these results imply a gate is situated between amino acid residues 337 and 344 along TM6, encompassing the very segment that may also serve as the selectivity filter for CFTR. The unique position of a gate in the middle of the ion translocation pathway diverges from those seen in ATP-binding cassette (ABC) transporters and thus distinguishes CFTR from other members of the ABC transporter family. PMID:25675504

  3. Localizing a gate in CFTR.

    PubMed

    Gao, Xiaolong; Hwang, Tzyh-Chang

    2015-02-24

    Experimental and computational studies have painted a picture of the chloride permeation pathway in cystic fibrosis transmembrane conductance regulator (CFTR) as a short narrow tunnel flanked by wider inner and outer vestibules. Although these studies also identified a number of transmembrane segments (TMs) as pore-lining, the exact location of CFTR's gate(s) remains unknown. Here, using a channel-permeant probe, [Au(CN)2](-), we provide evidence that CFTR bears a gate that coincides with the predicted narrow section of the pore defined as residues 338-341 in TM6. Specifically, cysteines introduced cytoplasmic to the narrow region (i.e., positions 344 in TM6 and 1148 in TM12) can be modified by intracellular [Au(CN)2](-) in both open and closed states, corroborating the conclusion that the internal vestibule does not harbor a gate. However, cysteines engineered to positions external to the presumed narrow region (e.g., 334, 335, and 337 in TM6) are all nonreactive toward cytoplasmic [Au(CN)2](-) in the absence of ATP, whereas they can be better accessed by extracellular [Au(CN)2](-) when the open probability is markedly reduced by introducing a second mutation, G1349D. As [Au(CN)2](-) and chloride ions share the same permeation pathway, these results imply a gate is situated between amino acid residues 337 and 344 along TM6, encompassing the very segment that may also serve as the selectivity filter for CFTR. The unique position of a gate in the middle of the ion translocation pathway diverges from those seen in ATP-binding cassette (ABC) transporters and thus distinguishes CFTR from other members of the ABC transporter family.

  4. Reliability Generalization: "Lapsus Linguae"

    ERIC Educational Resources Information Center

    Smith, Julie M.

    2011-01-01

    This study examines the proposed Reliability Generalization (RG) method for studying reliability. RG employs the application of meta-analytic techniques similar to those used in validity generalization studies to examine reliability coefficients. This study explains why RG does not provide a proper research method for the study of reliability,…

  5. Reading Gate Positions with a Smartphone

    NASA Astrophysics Data System (ADS)

    van Overloop, Peter-Jules; Hut, Rolf

    2015-04-01

    Worldwide many flow gates are built in water networks in order to direct water to appropriate locations. Most of these gates are adjusted manually by field operators of water management organizations and it is often centrally not known what the new position of the gate is. This makes centralized management of the entire water network difficult. One of the reasons why the measurement of the gate position is usually not executed, is that for certain gates it is not easy to do such a reading. Tilting weirs or radial gates are examples where operators need special equipment (measuring rod and long level) to determine the position and it could even be a risky procedure. Another issue is that once the measurement is done, the value is jotted down in a notebook and later, at the office, entered in a computer system. So the entire monitoring procedure is not real-time and prone to human errors. A new way of monitoring gate positions is introduced. It consists of a level that is attached to the gate and an app with which a picture can be taken from the level. Using dedicated pattern recognition algorithms, the gate position can be read by using the angle of the level versus reference points on the gate, the radius of that gate and the absolute level of the joint around which the gate turn. The method uses gps-localization of the smartphone to store the gate position in the right location in the central database.

  6. Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

    NASA Astrophysics Data System (ADS)

    Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

    2014-01-01

    In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

  7. Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

    NASA Technical Reports Server (NTRS)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.; Chen, Yuan

    2016-01-01

    Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

  8. Novel Dielectrics for GaN Device Passivation and Improved Reliability

    NASA Astrophysics Data System (ADS)

    Ren, F.; Pearton, Stephen J.; Gila, B. P.; Abernathy, C. R.; Fitch, R. C.

    Proper surface cleaning processes and the type of passivation film (SiNX, Sc2O3, MgO) used to reduce the current collapse phenomena in the devices are very critical to reduce the inter-device isolation leakage currents in mesa-isolated AlGaN/GaN high electron mobility transistors and to improve reliability. Three different passivation layers (SiNX, MgO, and Sc2O3) were examined for their effectiveness in mitigating surface state-induced current collapse in AlGaN/GaN high electron mobility transistors (HEMTs). The plasma-enhanced chemical vapor deposited SiNX produced ~80-85% recovery of the drain-source current, independent of whether SiH4/NH3 or SiD4/ND3 plasma chemistries were employed. Both the Sc2O3 and MgO produced essentially complete recovery of the current in GaN-cap HEMT structures and ~80-95% recovery in AlGaN-cap structures. The Sc2O3 had superior long-term stability with no change in HEMT behavior over 5 months aging. The use of MOSFETs could allow the use of complementary devices, thus producing less power consumption and simpler circuit design. The same novel oxides employed for alleviating many of the problems encountered in current Schottky-based devices were successfully used as the gate dielectric for MOS-diode and MOSFETs. Both MgO and Sc2O3 were shown to provide low interface state densities (in the 1011 eV-1 cm-2 range) on n- and p-GaN, making them useful for gate dielectrics for metal-oxide-semiconductor (MOS) devices and also as surface passivation layers to mitigate current collapse in GaN/AlGaN high electron mobility transistors (HEMTs). Clear evidence of inversion was demonstrated in gate-controlled MOS p-GaN diodes using both types of oxide. Charge-pumping measurements on diodes undergoing a high temperature implant activation anneal showed a total surface state density of ~3×1012 cm-2. On HEMT structures, both oxides provided effective passivation of surface states and these devices showed improved output power. The MgO/GaN structures

  9. SiC Power MOSFET with Improved Gate Dielectric

    SciTech Connect

    Sbrockey, Nick M; Tompa, Gary S; Spencer, Michael G; Chandrashekhar, Chandra MVS

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  10. Can There Be Reliability without "Reliability?"

    ERIC Educational Resources Information Center

    Mislevy, Robert J.

    2004-01-01

    An "Educational Researcher" article by Pamela Moss (1994) asks the title question, "Can there be validity without reliability?" Yes, she answers, if by reliability one means "consistency among independent observations intended as interchangeable" (Moss, 1994, p. 7), quantified by internal consistency indices such as…

  11. Radial gate evaluation: Olympus Dam, Colorado

    SciTech Connect

    1997-06-01

    The report presents a structural analysis of the radial gates of Olympus Dam in eastern Colorado. Five 20-foot wide by 17-foot high radial gates are used to control flow through the spillway at Olympus Dam. The spillway gates were designed in 1947. The gate arm assemblies consist of two separate wide flange beams, with a single brace between the arms. The arms pivot about a 4.0-inch diameter pin and bronze graphite-insert bushing. The pin is cantilevered from the pier anchor girder. The radial gates are supported by a pin bearing on a pier anchor birder bolted to the end of the concrete pier. The gates are operated by two-part wire rope 15,000-pound capacity hoise. Stoplog slots upstream of the radial gates are provided in the concrete piers. Selected drawings of the gates and hoists are located in appendix A.

  12. The Gow-Gates Technique for Mandibular Block Anesthesia

    PubMed Central

    Kafalias, Michael C.; Gow-Gates, George A.E.; Saliba, Gary J.

    1987-01-01

    Reliable profound mandibular block anesthesia is questionable when depositing the anesthetic solution at the lingula. Complications can occur and the needle may impact a number of important anatomical structures by deep penetration. The Gow-Gates technique for mandibular anesthesia obviates these problems. In this paper the Gow-Gates technique is reinterpreted using a geometrical approach based on lines and planes and is proved mathematically. In so doing a simple yet concise method of reaching the injection site is presented with a definite relationship between the anatomical pathway of the needle and a formal geometrical and mathematical pattern. ImagesFigure 1Figure 2Figure 3Figure 4Figure 5Figure 6Figure 7 PMID:3481514

  13. Nonvolatile Transistor Memory with Self-Assembled Semiconducting Polymer Nanodomain Floating Gates.

    PubMed

    Wang, Wei; Kim, Kang Lib; Cho, Suk Man; Lee, Ju Han; Park, Cheolmin

    2016-12-14

    Organic field effect transistor based nonvolatile memory (OFET-NVM) with semiconducting nanofloating gates offers additional benefits over OFET-NVMs with conventional metallic floating gates due to the facile controllability of charge storage based on the energetic structure of the floating gate. In particular, an all-in-one tunneling and floating-gate layer in which the semiconducting polymer nanodomains are self-assembled in the dielectric tunneling layer is promising. In this study, we utilize crystals of a p-type semiconducting polymer in which the crystalline lamellae of the polymer are spontaneously developed and embedded in the tunneling matrix as the nanofloating gate. The widths and lengths of the polymer nanodomains are approximately 20 nm and a few hundred nanometers, respectively. An OFET-NVM containing the crystalline nanofloating gates exhibits memory performance with a large memory window of 10 V, programming/erasing switching endurance for over 500 cycles, and a long retention time of 5000 s. Moreover, the device performance is improved by comixing with an n-type semiconductor; thus, the solution-processed p- and n-type double floating gates capable of storing both holes and electrons allow for the multilevel operation of our OFET-NVM. Four highly reliable levels (two bits per cell) of charge trapping and detrapping are achieved using this OFET-NVM by accurately choosing the programming/erasing voltages.

  14. Target detection in turbid medium using polarization-based range-gated technology.

    PubMed

    Guan, Jinge; Zhu, Jingping

    2013-06-17

    Range-gated technology is well known for its good reliability, large field of view (FOV) and low cost in target detection through scattering or turbid medium. However, the tail-gating technology suffers from low signal-to-noise ratio in high turbidity levels due to superposition of photons multiply scattered from the medium and that reflected from the target. In this paper, polarization properties of multiply scattered photons emerging from the turbid medium are studied. Results demonstrate that diffusive photons are almost completely depolarized with no diattenuation and retardance. We combined the tail-gated technology with polarization detection method to effectively image in high level of turbidity. This approach showed about two times enhancement in image contrast as compared with the conventional range-gated technology.

  15. Analysis of nickel-cadmium battery reliability data containing zero failures

    NASA Technical Reports Server (NTRS)

    Denson, William K.; Klein, Glenn C.

    1992-01-01

    An analysis of reliability data on Nickel-Cadmium (NiCd) batteries (for use in spacecraft) is presented. The data were collected by Gates Aerospace and represent a substantial reliability database. The data were taken from the performance of 183 satellites which were in operation from between .1 and 22 years, for a total of 278 million cell-hours of operation.

  16. Double-disc gate valve

    DOEpatents

    Wheatley, Seth J.

    1979-01-01

    This invention relates to an improvement in a conventional double-disc gate valve having a vertically movable gate assembly including a wedge, spreaders slidably engaged therewtih, a valve disc carried by the spreaders. When the gate assembly is lowered to a selected point in the valve casing, the valve discs are moved transversely outward to close inlet and outlet ports in the casing. The valve includes hold-down means for guiding the disc-and-spreader assemblies as they are moved transversely outward and inward. If such valves are operated at relatively high differential pressures, they sometimes jam during opening. Such jamming has been a problem for many years in gate valves used in gaseous diffusion plants for the separtion of uranium isotopes. The invention is based on the finding that the above-mentioned jamming results when the outlet disc tilts about its horizontal axis in a certain way during opening of the valve. In accordance with the invention, tilting of the outlet disc is maintained at a tolerable value by providing the disc with a rigid downwardly extending member and by providing the casing with a stop for limiting inward arcuate movement of the member to a preselected value during opening of the valve.

  17. Developing ICALL Tools Using GATE

    ERIC Educational Resources Information Center

    Wood, Peter

    2008-01-01

    This article discusses the use of the General Architecture for Text Engineering (GATE) as a tool for the development of ICALL and NLP applications. It outlines a paradigm shift in software development, which is mainly influenced by projects such as the Free Software Foundation. It looks at standards that have been proposed to facilitate the…

  18. Talking with Microsoft's Bill Gates.

    ERIC Educational Resources Information Center

    EDUCOM Review, 1994

    1994-01-01

    Presents the transcript of an interview with William Gates, chairman of Microsoft Corporation. Topics discussed include continued support from the information technology industry for higher education; experiences with recent college graduates in the industry; new technologies developing in the near future; alliances in the computer industry; and…

  19. Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

    NASA Technical Reports Server (NTRS)

    Danchenko, V. (Inventor)

    1974-01-01

    A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

  20. Impact of La{sub 2}O{sub 3} interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks deposited by atomic-layer-deposition

    SciTech Connect

    Chang, C.-Y. Takenaka, M.; Takagi, S.; Ichikawa, O.; Osada, T.; Hata, M.; Yamada, H.

    2015-08-28

    We examine the electrical properties of atomic layer deposition (ALD) La{sub 2}O{sub 3}/InGaAs and Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD La{sub 2}O{sub 3}/InGaAs interface provides low interface state density (D{sub it}) with the minimum value of ∼3 × 10{sup 11} cm{sup −2} eV{sup −1}, which is attributable to the excellent La{sub 2}O{sub 3} passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in La{sub 2}O{sub 3}. In order to simultaneously satisfy low D{sub it} and small hysteresis, the effectiveness of Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks with ultrathin La{sub 2}O{sub 3} interfacial layers is in addition evaluated. The reduction of the La{sub 2}O{sub 3} thickness to 0.4 nm in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, D{sub it} of the Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs interfaces becomes higher than that of the La{sub 2}O{sub 3}/InGaAs ones, attributable to the diffusion of Al{sub 2}O{sub 3} through La{sub 2}O{sub 3} into InGaAs and resulting modification of the La{sub 2}O{sub 3}/InGaAs interface structure. As a result of the effective passivation effect of La{sub 2}O{sub 3} on InGaAs, however, the Al{sub 2}O{sub 3}/10 cycle (0.4 nm) La{sub 2}O{sub 3}/InGaAs gate stacks can realize still lower D{sub it} with maintaining small hysteresis and low leakage current than the conventional Al{sub 2}O{sub 3}/InGaAs MOS interfaces.

  1. Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates

    NASA Astrophysics Data System (ADS)

    Li, Zhiqiang; Chen, Sai; Song, Xiaoyu; Perkowski, Marek; Chen, Hanwu; Zhu, Wei

    2017-04-01

    Since Controlled-Square-Root-of-NOT (CV, CV‡) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.

  2. Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates

    NASA Astrophysics Data System (ADS)

    Li, Zhiqiang; Chen, Sai; Song, Xiaoyu; Perkowski, Marek; Chen, Hanwu; Zhu, Wei

    2016-12-01

    Since Controlled-Square-Root-of-NOT (CV, CV‡) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.

  3. Assuring reliability program effectiveness.

    NASA Technical Reports Server (NTRS)

    Ball, L. W.

    1973-01-01

    An attempt is made to provide simple identification and description of techniques that have proved to be most useful either in developing a new product or in improving reliability of an established product. The first reliability task is obtaining and organizing parts failure rate data. Other tasks are parts screening, tabulation of general failure rates, preventive maintenance, prediction of new product reliability, and statistical demonstration of achieved reliability. Five principal tasks for improving reliability involve the physics of failure research, derating of internal stresses, control of external stresses, functional redundancy, and failure effects control. A final task is the training and motivation of reliability specialist engineers.

  4. Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET

    NASA Astrophysics Data System (ADS)

    Kim, Jae-hong; Kim, Geun-ho; Ko, Suk-woong; Jung, Hak-kee

    2002-11-01

    In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (MG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 2V in the main gate 50nm. Also, we know that optimum side gate length for each main gate length is 70nm above. DG MOSFET shows a small threshold voltage (Vth) roll-off. From the I-V characteristics, we obtained IDsat=510μA/μm at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86mV/decade, transconductance is 111μA/V and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Also, we have presented that TCAD simulator is suitable for device simulation.

  5. Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

    NASA Technical Reports Server (NTRS)

    Straka, Bartholomew

    2013-01-01

    Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

  6. Enhancement mode AlGaN/GaN MOS high-electron-mobility transistors with ZrO2 gate dielectric deposited by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Anderson, Travis J.; Wheeler, Virginia D.; Shahin, David I.; Tadjer, Marko J.; Koehler, Andrew D.; Hobart, Karl D.; Christou, Aris; Kub, Francis J.; Eddy, Charles R., Jr.

    2016-07-01

    Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) in high-power RF and power switching are driving the need for insulated gate technology. We present a metal-oxide-semiconductor (MOS) gate structure using atomic-layer-deposited ZrO2 as a high-k, high-breakdown gate dielectric for reduced gate leakage and a recessed barrier structure for enhancement mode operation. Compared to a Schottky metal-gate HEMT, the recessed MOS-HEMT structure demonstrated a reduction in the gate leakage current by 4 orders of magnitude and a threshold voltage shift of +6 V to a record +3.99 V, enabled by a combination of a recessed barrier structure and negative oxide charge.

  7. The role of ZrN capping layer deposited on ultra-thin high-k Zr-doped yttrium oxide for metal-gate metal–insulator–semiconductor applications

    SciTech Connect

    Juan, Pi-Chun; Mong, Fan-Chen; Huang, Jen-Hung

    2013-08-28

    Metal-gate MIS structures with and without ZrN capping layer on high-k Y{sub 2}O{sub 3}:Zr/Y{sub 2}O{sub 3} stack were fabricated. The binding energies and depth profiles were investigated by x-ray photoelectron spectroscopy (XPS). The x-ray diffraction (XRD) patterns were compared. It is found that Ti out-diffusion into Zr-based high-k dielectric becomes lesser with the insertion of ZrN capping layer. The electrical properties of current-voltage (I-V) and capacitance-voltage (C-V) characteristics were measured in the postannealing temperature range of 550–850 °C. According to the defect reaction model, Zr cation vacancies are associated with the concentration of Ti ion by a transition from +3 to +2 states. The amount of Zr cation vacancies is quantified and equal to a half of Ti substitution amount at Zr site. The reduction in cation vacancies at high temperatures can well explain the decrease in ΔV{sub FB} for samples with ZrN layer. In contrast, an excess of Ti outdiffusion will produce the interstitial defects in high-k films without ZrN capping.

  8. Environmental noise reduction for holonomic quantum gates

    SciTech Connect

    Parodi, Daniele; Zanghi, Nino; Sassetti, Maura; Solinas, Paolo

    2007-07-15

    We study the performance of holonomic quantum gates, driven by lasers, under the effect of a dissipative environment modeled as a thermal bath of oscillators. We show how to enhance the performance of the gates by a suitable choice of the loop in the manifold of the controllable parameters of the laser. For a simplified, albeit realistic model, we find the surprising result that for a long time evolution the performance of the gate (properly estimated in terms of average fidelity) increases. On the basis of this result, we compare holonomic gates with the so-called stimulated raman adiabatic passage (STIRAP) gates.

  9. RGB-NIR active gated imaging

    NASA Astrophysics Data System (ADS)

    Spooren, Nick; Geelen, Bert; Tack, Klaas; Lambrechts, Andy; Jayapala, Murali; Ginat, Ran; David, Yaara; Levi, Eyal; Grauer, Yoav

    2016-10-01

    This paper presents multispectral active gated imaging in relation to the transportation and security fields. Active gated imaging is based on a fast gated camera and pulsed illuminator, synchronized in the time domain to provide range based images. We have developed a multispectral pattern deposited on a gated CMOS Image Sensor (CIS) with a pulsed Near Infrared VCSEL module. This paper will cover the component-level description of the multispectral gated CIS including the camera and illuminator units. Furthermore, the design considerations and characterization results of the spectral filters are presented together with a newly developed image processing method.

  10. Power electronics reliability analysis.

    SciTech Connect

    Smith, Mark A.; Atcitty, Stanley

    2009-12-01

    This report provides the DOE and industry with a general process for analyzing power electronics reliability. The analysis can help with understanding the main causes of failures, downtime, and cost and how to reduce them. One approach is to collect field maintenance data and use it directly to calculate reliability metrics related to each cause. Another approach is to model the functional structure of the equipment using a fault tree to derive system reliability from component reliability. Analysis of a fictitious device demonstrates the latter process. Optimization can use the resulting baseline model to decide how to improve reliability and/or lower costs. It is recommended that both electric utilities and equipment manufacturers make provisions to collect and share data in order to lay the groundwork for improving reliability into the future. Reliability analysis helps guide reliability improvements in hardware and software technology including condition monitoring and prognostics and health management.

  11. Human Reliability Program Overview

    SciTech Connect

    Bodin, Michael

    2012-09-25

    This presentation covers the high points of the Human Reliability Program, including certification/decertification, critical positions, due process, organizational structure, program components, personnel security, an overview of the US DOE reliability program, retirees and academia, and security program integration.

  12. Integrated avionics reliability

    NASA Technical Reports Server (NTRS)

    Alikiotis, Dimitri

    1988-01-01

    The integrated avionics reliability task is an effort to build credible reliability and/or performability models for multisensor integrated navigation and flight control. The research was initiated by the reliability analysis of a multisensor navigation system consisting of the Global Positioning System (GPS), the Long Range Navigation system (Loran C), and an inertial measurement unit (IMU). Markov reliability models were developed based on system failure rates and mission time.

  13. Reliable Design Versus Trust

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth A.

    2016-01-01

    This presentation focuses on reliability and trust for the users portion of the FPGA design flow. It is assumed that the manufacturer prior to hand-off to the user tests FPGA internal components. The objective is to present the challenges of creating reliable and trusted designs. The following will be addressed: What makes a design vulnerable to functional flaws (reliability) or attackers (trust)? What are the challenges for verifying a reliable design versus a trusted design?

  14. Quantum computing gates via optimal control

    NASA Astrophysics Data System (ADS)

    Atia, Yosi; Elias, Yuval; Mor, Tal; Weinstein, Yossi

    2014-10-01

    We demonstrate the use of optimal control to design two entropy-manipulating quantum gates which are more complex than the corresponding, commonly used, gates, such as CNOT and Toffoli (CCNOT): A two-qubit gate called polarization exchange (PE) and a three-qubit gate called polarization compression (COMP) were designed using GRAPE, an optimal control algorithm. Both gates were designed for a three-spin system. Our design provided efficient and robust nuclear magnetic resonance (NMR) radio frequency (RF) pulses for 13C2-trichloroethylene (TCE), our chosen three-spin system. We then experimentally applied these two quantum gates onto TCE at the NMR lab. Such design of these gates and others could be relevant for near-future applications of quantum computing devices.

  15. Unifying Gate Synthesis and Magic State Distillation

    NASA Astrophysics Data System (ADS)

    Campbell, Earl T.; Howard, Mark

    2017-02-01

    The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

  16. Digital avionics design and reliability analyzer

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The description and specifications for a digital avionics design and reliability analyzer are given. Its basic function is to provide for the simulation and emulation of the various fault-tolerant digital avionic computer designs that are developed. It has been established that hardware emulation at the gate-level will be utilized. The primary benefit of emulation to reliability analysis is the fact that it provides the capability to model a system at a very detailed level. Emulation allows the direct insertion of faults into the system, rather than waiting for actual hardware failures to occur. This allows for controlled and accelerated testing of system reaction to hardware failures. There is a trade study which leads to the decision to specify a two-machine system, including an emulation computer connected to a general-purpose computer. There is also an evaluation of potential computers to serve as the emulation computer.

  17. Reliability and structural integrity

    NASA Technical Reports Server (NTRS)

    Davidson, J. R.

    1976-01-01

    An analytic model is developed to calculate the reliability of a structure after it is inspected for cracks. The model accounts for the growth of undiscovered cracks between inspections and their effect upon the reliability after subsequent inspections. The model is based upon a differential form of Bayes' Theorem for reliability, and upon fracture mechanics for crack growth.

  18. Reliability model generator specification

    NASA Technical Reports Server (NTRS)

    Cohen, Gerald C.; Mccann, Catherine

    1990-01-01

    The Reliability Model Generator (RMG), a program which produces reliability models from block diagrams for ASSIST, the interface for the reliability evaluation tool SURE is described. An account is given of motivation for RMG and the implemented algorithms are discussed. The appendices contain the algorithms and two detailed traces of examples.

  19. Viking Lander reliability program

    NASA Technical Reports Server (NTRS)

    Pilny, M. J.

    1978-01-01

    The Viking Lander reliability program is reviewed with attention given to the development of the reliability program requirements, reliability program management, documents evaluation, failure modes evaluation, production variation control, failure reporting and correction, and the parts program. Lander hardware failures which have occurred during the mission are listed.

  20. Theory of reliable systems

    NASA Technical Reports Server (NTRS)

    Meyer, J. F.

    1975-01-01

    An attempt was made to refine the current notion of system reliability by identifying and investigating attributes of a system which are important to reliability considerations. Techniques which facilitate analysis of system reliability are included. Special attention was given to fault tolerance, diagnosability, and reconfigurability characteristics of systems.