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Sample records for gate oxide reliability

  1. Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

    NASA Astrophysics Data System (ADS)

    Sung, Min Gyu; Lim, Kwan-Yong; Cho, Heung-Jae; Lee, Seung Ryong; Jang, Se-Aug; Kim, Yong Soo; Kim, Tae-Yoon; Yang, Hong-Seon; Ku, Ja-Chun; Kim, Jin Woong

    2007-11-01

    Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si-N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

  2. Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Sahu, P. K.; Singh, D.; Artola, L.; Mohapatra, S. K.

    2015-09-01

    A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon-germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

  3. Fundamental reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition

    SciTech Connect

    Yamada, Hiroshi

    2008-01-15

    The reliability of 1.5-nm-thick silicon oxide gate films grown at 150 deg. C by modified reactive ion beam deposition (RIBD) with in situ pyrolytic-gas passivation (PGP) using N{sub 2}O and NF{sub 3} was investigated. RIBD uses low-energy-controlled reactive, ionized species and potentializes low-temperature film growth. Although the oxide films were grown at a low temperature of 150 deg. C, their fundamental indices of reliability, such as the time-dependent dielectric breakdown lifetime and interface state density, were almost equivalent to those of oxide films grown at 850 deg. C using a furnace. This is probably due to localized interfacial N and F atoms. The number density of interfacial N atoms was about seven times larger than that for the furnace-grown oxide films, and this is a key factor for improving the reliability through the compensation of residual inconsistent-state bonding sites.

  4. Impact strain engineering on gate stack quality and reliability

    NASA Astrophysics Data System (ADS)

    Claeys, C.; Simoen, E.; Put, S.; Giusi, G.; Crupi, F.

    2008-08-01

    Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated.

  5. Reliability study of refractory gate gallium arsenide MESFETS

    NASA Technical Reports Server (NTRS)

    Yin, J. C. W.; Portnoy, W. M.

    1981-01-01

    Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

  6. Systematical Study of Reliability Issues in Plasma-Nitrided and Thermally Nitrided Oxides for Advanced Dual-Gate Oxide p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Lo, Wen-Cheng; Wu, Shien-Yang; Chang, Sun-Jay; Chiang, Mu-Chi; Lin, Chih-Yung; Chao, Tien-Sheng; Chang, Chun-Yen

    2007-03-01

    In this study, we compared the effects of negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) on the core and input/output (I/O) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) fabricated using the different gate dielectrics of plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO). The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30 and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density.

  7. Single event gate rupture in thin gate oxides

    SciTech Connect

    Sexton, F.W.; Fleetwood, D.M.; Shaneyfelt, M.R.; Dodd, P.E.; Hash, G.L.

    1997-06-01

    As integrated circuit densities increase with each new technology generation, both the lateral and vertical dimensions shrink. Operating voltages, however, have not scaled as aggressively as feature size, with a resultant increase in the electric fields within advanced geometry devices. Oxide electric fields are in fact increasing to greater than 5 MV/cm as feature size approaches 0.1 {micro}m. This trend raises the concern that single event gate rupture (SEGR) may limit the scaling of advanced integrated circuits (ICs) for space applications. The dependence of single event gate rupture (SEGR) critical field on oxide thickness is examined for thin gate oxides. Critical field for SEGR increases with decreasing oxide thickness, consistent with an increasing intrinsic breakdown field.

  8. Ultrathin gate oxide with a reduced transition layer grown by plasma-assisted oxidation

    SciTech Connect

    Hyun, S.; Buh, G.H.; Hong, S.H.; Koo, B.Y.; Shin, Y.G.; Jung, U.I.; Moon, J.T.; Cho, M.-H.; Chang, H.S.; Moon, D.W.

    2004-08-09

    Ultrathin SiO{sub 2} grown by plasma-assisted oxidation (plasma oxide) has been investigated by high-resolution x-ray photoemission spectroscopy and medium energy ion scattering spectroscopy. We found that the plasma oxide grown at the low temperature of 400 deg. C has a thinner transition layer than conventional thermal oxide. This thinner transition layer in the plasma oxide not only decreased the gate leakage current effectively, but also enhanced the reliability of the gate oxide. We attribute these electrical properties of the plasma oxide to the reduction of the transition layer.

  9. Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

    SciTech Connect

    Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei; Wu, Yung-Hsien

    2015-02-02

    ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribed to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.

  10. Physical mechanism of progressive breakdown in gate oxides

    NASA Astrophysics Data System (ADS)

    Palumbo, Felix; Lombardo, Salvatore; Eizenberg, Moshe

    2014-06-01

    The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric.

  11. Reliability characterization of advanced oxynitride gate dielectrics for ULSI MOSFET application

    NASA Astrophysics Data System (ADS)

    Min, Byoung Woon

    1998-12-01

    The evolution of ULSI MOSFET technology has occurred primarily as a result of the increased number of devices on a chip. This has been accomplished by the aggressive scaling of feature size and gate oxide thickness of MOSFET. As a result, the reliability of the gate dielectrics becomes a more important issue. Moreover, use of aggressive plasma-based processes has become commonplace in modern integrated circuit manufacturing, requiring more reliable gate dielectrics against the plasma-induced damage. This research work is initially divided into four parts; (1) plasma-induced charging damage in MOSFETs with NO-based oxynitride, (2) gate-induced drain leakage in MOSFETs with NO-based oxynitride, (3) soft breakdown characteristics in ultra-thin gate dielectrics, and (4) characterization of MOSFETs with oxynitride gate dielectrics fabricated at high pressure and low temperature. Prior research has focused on the fabrication and development of NO-annealed oxynitridation. This research concentrates on reliability characterization of MOSFET with the oxynitride gate dielectrics formed by two advanced oxynitridation techniques with anneal of thermal oxide in NO-ambient and/or growth of oxynitride in high pressure Nsb2O ambient, resulting in the formation of reliable gate dielectrics with low thermal budget against hot carrier reliability, plasma-induced charging damage, dielectric breakdown and boron penetration. However, it is found that nitrogen peak distribution around SiOsb2/Si-substrate interface degraded gate-induced drain leakage in N-MOSFETs and gate dielectric hardness in P-MOSFETs. In N-MOSFETs, nitrogen distribution underneath SiOsb2 enhances the gate-induced drain leakage after hot carrier stress due to the enhanced band-to-defect tunneling through mid-gap traps at the buried nitrogen rich layer. In P-MOSFETs, boron accumulation within the dielectrics due to the nitrogen peak at SiOsb2/Si-substrate results in dielectric degradation. Nitrogen peak at top surface

  12. A reversible fluorescent DNA logic gate based on graphene oxide and its application for iodide sensing.

    PubMed

    Zhang, Min; Ye, Bang-Ce

    2012-04-14

    A simple and reliable fluorescent DNA logic gate is developed by utilizing graphene oxide as a signal transducer and mercury ions and iodide as mechanical activators. This journal is © The Royal Society of Chemistry 2012

  13. An advanced tunnel oxide layer process for 65 nm NOR floating-gate flash memories

    NASA Astrophysics Data System (ADS)

    Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Liao, Yiming; Wu, Fuwei; Yan, Feng

    2015-10-01

    An advanced tunnel oxide layer process for 65 nm NOR-type floating-gate flash memory is proposed to improve tunnel oxide quality by an additive sacrificial oxide layer growth. The sacrificial oxide layer process effectively controls the thickness variation of tunnel oxide and improves the flatness of the SiO2/Si interface across the active area. The interface traps’ generation during program/erase cycling of flash cells is found to be reduced, and the reliability property is significantly improved as compared to flash cells without the sacrificial oxide layer process. The technology is applicable to further scaled floating-gate flash memories.

  14. Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

    SciTech Connect

    Park, Hong Bae; Ju, Byongsun; Kang, Chang Yong; Park, Chanro; Park, Chang Seo; Lee, Byoung Hun; Kim, Tea Wan; Kim, Beom Seok; Choi, Rino

    2009-01-26

    The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor I{sub on}-I{sub off} characteristics and reduces negative-bias temperature instability.

  15. Gate-Tunable Conducting Oxide Metasurfaces.

    PubMed

    Huang, Yao-Wei; Lee, Ho Wai Howard; Sokhoyan, Ruzan; Pala, Ragip A; Thyagarajan, Krishnan; Han, Seunghoon; Tsai, Din Ping; Atwater, Harry A

    2016-09-14

    Metasurfaces composed of planar arrays of subwavelength artificial structures show promise for extraordinary light manipulation. They have yielded novel ultrathin optical components such as flat lenses, wave plates, holographic surfaces, and orbital angular momentum manipulation and detection over a broad range of the electromagnetic spectrum. However, the optical properties of metasurfaces developed to date do not allow for versatile tunability of reflected or transmitted wave amplitude and phase after their fabrication, thus limiting their use in a wide range of applications. Here, we experimentally demonstrate a gate-tunable metasurface that enables dynamic electrical control of the phase and amplitude of the plane wave reflected from the metasurface. Tunability arises from field-effect modulation of the complex refractive index of conducting oxide layers incorporated into metasurface antenna elements which are configured in reflectarray geometry. We measure a phase shift of 180° and ∼30% change in the reflectance by applying 2.5 V gate bias. Additionally, we demonstrate modulation at frequencies exceeding 10 MHz and electrical switching of ±1 order diffracted beams by electrical control over subgroups of metasurface elements, a basic requirement for electrically tunable beam-steering phased array metasurfaces. In principle, electrically gated phase and amplitude control allows for electrical addressability of individual metasurface elements and opens the path to applications in ultrathin optical components for imaging and sensing technologies, such as reconfigurable beam steering devices, dynamic holograms, tunable ultrathin lenses, nanoprojectors, and nanoscale spatial light modulators.

  16. Gate Rupture in Ultra-Thin Gate Oxides Irradiated With Heavy Ions

    NASA Astrophysics Data System (ADS)

    Silvestri, Marco; Gerardin, Simone; Paccagnella, Alessandro; Ghidini, Gabriella

    2009-08-01

    We investigated the combined effect of heavy-ion irradiation and large applied bias on the dielectric breakdown of ultra-thin gate oxides, analyzing the impact of border regions through dedicated test structures. We found that the irradiation bias polarity plays a fundamental role, with inversion being more detrimental than accumulation for the onset of gate rupture. Moreover, the average voltage to breakdown was, under certain conditions, lower in structures more closely resembling real MOSFETs, as compared to those commonly used for the evaluation of Single Event Gate Rupture. These findings raise some important hardness assurance issues concerning the integrity of gate oxides in radiation environments.

  17. Reliability analysis for determining performance of barrage based on gates operation

    NASA Astrophysics Data System (ADS)

    Adiningrum, C.; Hadihardaja, I. K.

    2017-06-01

    Some rivers located on a flat slope topography such as Cilemahabang river and Ciherang river in Cilemahabang watershed, Bekasi regency, West Java are susceptible to flooding. The inundation mostly happens near a barrage in the middle and downstream of the Cilemahabang watershed, namely the Cilemahabang and Caringin barrages. Barrages or gated weirs are difficult to exploit since the gate must be kept and operated properly under any circumstances. Therefore, a reliability analysis of the gates operation is necessary to determine the performance of the barrage with respect to the number of gates opened and the gates opening heights. The First Order Second Moment (FOSM) method was used to determine the performance by the reliability index (β) and the probability of failure (risk). It was found that for Cilemahabang Barrage, the number of gates opened with load (L) represents the peak discharge derived from various rainfall (P) respectively one gate with opening height (h=1m) for Preal, two gates (h=1m and h=1,5m) for P50, and three gates (each gate with h=2,5m) for P100. For Caringin Barrage, the results are minimum three gates opened (each gate with h=2,5 m) for Preal, five gates opened (each gate with h=2,5m) for P50, and six gates opened (each gate with h=2,5m) for P100. It can be concluded that a greater load (L) needs greater resistance (R) to counterbalance. Resistance can be added by increasing the number of gates opened and the gate opening height. A higher number of gates opened will lead to the decrease of water level in the upstream of barrage and less risk of overflow.

  18. Arsenic ion implant energy effects on CMOS gate oxide hardness.

    SciTech Connect

    Dondero, Richard; Headley, Thomas Jeffrey; Young, Ralph Watson; Draper, Bruce Leroy; Shaneyfelt, Marty Ray

    2005-07-01

    Under conditions that were predicted as 'safe' by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.

  19. Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology

    NASA Astrophysics Data System (ADS)

    Mohamad, B.; Leroux, C.; Rideau, D.; Haond, M.; Reimbold, G.; Ghibaudo, G.

    2017-02-01

    Effective work function and equivalent oxide thickness are fundamental parameters for technology optimization. In this work, a comprehensive study is done on a large set of FDSOI devices. The extraction of the gate stack parameters is carried out by fitting experimental CV characteristics to quantum simulation, based on self-consistent solution of one dimensional Poisson and Schrodinger equations. A reliable methodology for gate stack parameters is proposed and validated. This study identifies the process modules that impact directly the effective work function from those that only affect the device threshold voltage, due to the device architecture. Moreover, the relative impacts of various process modules on channel thickness and gate oxide thickness are evidenced.

  20. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    NASA Astrophysics Data System (ADS)

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  1. NO2 sensitive Au gate metal-oxide-semiconductor capacitors

    NASA Astrophysics Data System (ADS)

    Filippini, D.; Aragón, R.; Weimar, U.

    2001-08-01

    Au gate metal-oxide-semiconductor capacitors are sensitive to NO2 in air up to 200 ppm, depending on operating temperature (100 °C to 200 °C), gate thickness (50 to 900 nm), and morphology. In the absence of catalytic properties or lattice diffusivity, a model invoking molecular surface adsorption and grain boundary diffusion is proposed, which quantitatively describes the transient and steady state response of the devices. Sensitivity is given by the arrival of the diffusing species to the gate-dielectric interface, where capacitive coupling of the adsorbed molecules induces work function changes, which shift the flat band voltage positively, opposite that observed for H2 with Pd gates, consistently with an oxidizing, rather than reducing, character.

  2. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    NASA Astrophysics Data System (ADS)

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-01

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al2O3 as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al2O3, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al2O3 is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  3. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    SciTech Connect

    Guo, Y.; Li, H.; Robertson, J.

    2016-05-28

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  4. Effect of Electron Shading on Gate Oxide Degradation

    NASA Astrophysics Data System (ADS)

    Sakamori, Shigenori; Maruyama, Takahiro; Fujiwara, Nobuo; Miyatake, Hiroshi

    1998-04-01

    The oxide degradation due to edge and electron shading effects is investigated in a pulse-modulated plasma using metal-oxide-silicon (MOS) and metal-nitride-oxide-silicon (MNOS) capacitors. Reduction of edge defect, shading defect and electron shading charge build-up is strongly dependent on the on-time in pulse plasma. In particular, when the on-time is shorter than 50 µs, the coefficient of the shading defect becomes almost zero. The investigation of MNOS capacitors, which have the patterns with or without the substrate contact antenna, indicates that the electric stress direction applied to gate oxide changes as the device structure changes.

  5. Transparent conducting oxide induced by liquid electrolyte gating

    PubMed Central

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

    2016-01-01

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ∼1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications. PMID:27647884

  6. Transparent conducting oxide induced by liquid electrolyte gating.

    PubMed

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-Dorin; Altendorf, Simone G; Utsumi, Yuki; Samant, Mahesh G; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S P

    2016-10-04

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3 Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ∼1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

  7. Transparent conducting oxide induced by liquid electrolyte gating

    NASA Astrophysics Data System (ADS)

    ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

    2016-10-01

    Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ˜1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

  8. Reliability study of retention and memory gate integrity in a 1K MNOS RAM

    SciTech Connect

    Nasby, R.D.; Miller, W.M.; White, R.L.

    1986-01-01

    The reliability of a 1K MNOS RAM with regards to retention and nitride gate integrity has been demonstrated. Over 400 devices were screened and life tested to demonstrate 0.999 reliability during device life. The device was a 1K MNOS memory used in a RAM application with an erase/write cycle of 32 microseconds and a life specification of 1E7 cycles.

  9. Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

    NASA Astrophysics Data System (ADS)

    Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

    2016-12-01

    This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

  10. Oxide VCSEL reliability qualification at Agilent Technologies

    NASA Astrophysics Data System (ADS)

    Herrick, Robert W.

    2002-06-01

    In the past two years, Agilent Technologies has had a unique opportunity to study the reliability of VCSELs from most major manufacturers. We report on our methodology for qualifying prospective VCSEL suppliers, and briefly discuss our findings. The expected use environment for VCSELs is covered, along with VCSEL reliability limitations with existing technology. Differences between maverick and wearout failures are discussed, and examples of each are shown; VCSEL failure analysis is also briefly touched on. Finally, recent challenges in using oxide VCSELs in non-hermetic packaging, and 10 Gb/s operation, are briefly covered.

  11. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    NASA Astrophysics Data System (ADS)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  12. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    PubMed Central

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-01-01

    The use of indium–gallium–zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic–inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic–inorganic hybrid devices. PMID:26677773

  13. Reliability of P50 auditory sensory gating measures in infants during active sleep.

    PubMed

    Hunter, Sharon K; Corral, Nereida; Ponicsan, Heather; Ross, Randal G

    2008-01-08

    This study assessed reliability of auditory sensory gating in young infants from 1-4 months of age using a paired-click paradigm in which auditory 'clicks' were presented at an interstimulus interval of 500 ms. Evoked potential component P1 was measured during periods of active sleep on two different occasions. Amplitudes, latencies, and ratio of the evoked potentials to each of the auditory clicks were compared. Significant reliability was found in the response ratio, response latency to the first stimulus, and response amplitude to the second stimulus, with a trend toward significance for response latency to the second stimulus and response amplitude to the first stimulus. The results suggest that auditory sensory gating can be reliably measured during active sleep in young infants and might be a useful tool in the study of neurodevelopmental disorders.

  14. High-κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

    PubMed Central

    Liao, Lei; Bai, Jingwei; Qu, Yongquan; Lin, Yung-chen; Li, Yujing; Huang, Yu; Duan, Xiangfeng

    2010-01-01

    Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al2O3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm2/V·s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics. PMID:20308584

  15. Gate Annealing of Cycling Endurance and Interface States for Highly Reliable Flash Memory

    NASA Astrophysics Data System (ADS)

    Kim, Nam-Kyeong; Hong, Se-Hee; Shim, Sa-Yong; Park, Min-Hee; Hwang, Kyung-Pil; Lee, Min-Kyu; Lee, Ju-Yeab; Woo, Won-Sic; Noh, Keum-Hwan; Lee, Hee-Kee; Om, Jae-Chul; Lee, Seok-Kiu; Bae, Gi-Hyun

    2008-01-01

    We report on superior cycling endurance due to a low interface trap density, which accounts for the high gate annealing temperature in flash memory. The interface trap density was characterized using a charge pumping method (CPM). The cycling VTH shift in an erase state value of 1.35 V at 850 °C temperature of an annealing, as measured on a 90-nm-technology 1-Mbit cell array, selected randomly from 1 Gbit cells, drops to less than 0.9 V after annealing at 950 °C. These superior electrical properties resulted from a complete relaxation of silicon interface trap charges due to a plasma-induced attack during gate annealing at temperatures over 950 °C for a long time. Therefore, the key factor for highly reliable endurance with cycling is believed to be the interface trap control of the thermal annealing carried out after gate etching.

  16. Hole Trapping in Thermal Oxides Grown under Various Oxidation Conditions Using Avalanche Injection in Poly-Silicon Gate Structures

    DTIC Science & Technology

    2014-05-01

    Hole Trapping in Thermal Oxides Grown under Vaious Oxidation Conditions Using Avalanche Injection in Poly-Silicon Gate Structures Contractor... Avalanche In ection in Poly-Silicon Gate Structureac 12. PERSONAL AUTHOR(S) K.V. Anand, B.R. Cairns, R.J. Strain 13a. TYPE OF REPORT 13b. TIME...Trapping, Oxidation Conditions, Avalanche Injection, Poly-Silicon Gates, Oxide Traps 19. ABSTRACT (Continue on reverse If necenry W Identify by block

  17. Metal-gate-induced reduction of the interfacial layer in Hf oxide gate stacks

    SciTech Connect

    Goncharova, L. V.; Dalponte, M.; Gustafsson, T.; Celik, O.; Garfunkel, E.; Lysaght, P. S.; Bersuker, G.

    2007-03-15

    The properties of high-{kappa} metal oxide gate stacks are often determined in the final processing steps following dielectric deposition. We report here results from medium energy ion scattering and x-ray photoelectron spectroscopy studies of oxygen and silicon diffusion and interfacial layer reactions in multilayer gate stacks. Our results show that Ti metallization of HfO{sub 2}/SiO{sub 2}/Si stacks reduces the SiO{sub 2} interlayer and (to a more limited extent) the HfO{sub 2} layer. We find that Si atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for Ti-Si interdiffusion through the high-{kappa} film in the presence of a Ti gate in the crystalline HfO{sub 2} films is also reported. This diffusion is likely to be related to defects in crystalline HfO{sub 2} films, such as grain boundaries. High-resolution transmission electron microscopy and corresponding electron energy loss spectroscopy scans show aggressive Ti-Si intermixing and oxygen diffusion to the outermost Ti layer, given high enough annealing temperature. Thermodynamic calculations show that the driving forces exist for some of the observed diffusion processes.

  18. Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, Subhash

    2000-01-01

    In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

  19. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    NASA Astrophysics Data System (ADS)

    Alshareef, H. N.; Caraveo-Frescas, J. A.; Cha, D. K.

    2010-11-01

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  20. Graphene-graphene oxide floating gate transistor memory.

    PubMed

    Jang, Sukjae; Hwang, Euyheon; Lee, Jung Heon; Park, Ho Seok; Cho, Jeong Ho

    2015-01-21

    A novel transparent, flexible, graphene channel floating-gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH3+), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al2 O3 blocking dielectric layers. Important design rules are proposed for a high-performance graphene memory device: (i) precise doping of the graphene channel, and (ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor-type memory device. Additionally, the positively charged GO (GO-NH3+) interacts electrostatically with hydroxyl groups of both UV-treated Al2 O3 and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene-graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10(5) s), and good mechanical stability (1000 cycles).

  1. HRTEM image simulations for the study of ultra-thin gate oxides

    SciTech Connect

    Taylor, Seth T.; Mardinly, John; O'Keefe, Michael A.

    2001-07-17

    We have performed high resolution transmission electron microscope (HRTEM) image simulations to qualitatively assess the visibility of various structural defects in ultra-thin gate oxides of MOSFET devices, and to quantitatively examine the accuracy of HRTEM in performing gate oxide metrology. Structural models contained crystalline defects embedded in an amorphous 16 {angstrom}-thick gate oxide. Simulated images were calculated for structures viewed in cross-section. Defect visibility was assessed as a function of specimen thickness and defect morphology, composition, size and orientation. Defect morphologies included asperities lying on the substrate surface, as well as ''bridging'' defects connecting the substrate to the gate electrode. Measurements of gate oxide thickness extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy for metrology. The effects of specimen tilt, specimen thickness, objective lens defocus and coefficient of spherical aberration (C{sub s}) on measurement accuracy were explored for nominal 10{angstrom} gate oxide thickness. Results from this work suggest that accurate metrology of ultra-thin gate oxides (i.e. limited to several per cent error) is feasible on a consistent basis only by using a C{sub s}-corrected microscope. However, fundamental limitations remain for characterizing defects in gate oxides using HRTEM, even with the new generation of C{sub s}-corrected microscopes.

  2. Realization of reliable and flexible logic gates using noisy nonlinear circuits

    NASA Astrophysics Data System (ADS)

    Murali, K.; Rajamohamed, I.; Sinha, Sudeshna; Ditto, William L.; Bulsara, Adi R.

    2009-11-01

    It was shown recently [Murali et al., Phys. Rev. Lett. 102, 104101 (2009)] that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the interplay between the system noise and the nonlinearity (that characterizes the bistable dynamics). One can switch or "morph" the output into another logic operation (NAND/AND) whose probability displays analogous behavior; the switching is accomplished via a controlled symmetry-breaking dc input. Thus, the interplay of nonlinearity and noise yields flexible and reliable logic behavior, and the natural outcome is, effectively, a logic gate. This "logical stochastic resonance" is demonstrated here via a circuit implementation using a linear resistor, a linear capacitor and four CMOS-transistors with a battery to produce a cubiclike nonlinearity. This circuit is simple, robust, and capable of operating in very high frequency regimes; further, its ease of implementation with integrated circuits and nanoelectronic devices should prove very useful in the context of reliable logic gate implementation in the presence of circuit noise.

  3. Studies on the reliability of ni-gate aluminum gallium nitride / gallium nitride high electron mobility transistors using chemical deprocessing

    NASA Astrophysics Data System (ADS)

    Whiting, Patrick Guzek

    Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors are becoming the technology of choice for applications where hundreds of volts need to be applied in a circuit at frequencies in the hundreds of gigahertz, such as microwave communications. However, because these devices are very new, their reliability in the field is not well understood, partly because of the stochastic nature of the defects which form as a result of their operation. Many analytical techniques are not well suited to the analysis of these defects because they sample regions of the device which are either too small or too large for accurate observation. The use of chemical deprocessing in addition to surface-sensitive analysis techniques such as Scanning Electron Microscopy and Scanning Probe Microscopy can be utilized in the analysis of defect formation in devices formed with nickel gates. Hydrofluoric acid is used to etch the passivation nitride which covers the semiconducting layer of the transistor. A metal etch utilizing FeCN/KI is used to etch the ohmic and gate contacts of the device and a long exposure in various solvent solutions is used to remove organic contaminants, exposing the surface of the semiconducting layer for analysis. Deprocessing was used in conjunction with a variety of metrology techniques to analyze three different defects. One of these defects is a nanoscale crack which emanates from metal inclusions formed during alloying of the ohmic contacts of the device prior to use in the field, could impact the yield of production-level manufacturing of these devices. This defect also appears to grow, in some cases, during electrostatic stressing. Another defect, a native oxide at the surface of the semiconducting layer which appears to react in the presence of an electric field, has not been observed before during post-mortem analysis of degraded devices. It could play a major part in the degredation of the gate contact during high-field, off

  4. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    PubMed Central

    Long, Rathnait D.; McIntyre, Paul C.

    2012-01-01

    The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  5. On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

    NASA Astrophysics Data System (ADS)

    Habaš, Predrag; Selberherr, Siegfried

    1990-12-01

    A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C- V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C- V curves agree with the recently published data of implanted gate devices.

  6. Oxide Thin-Film Transistors Fabricated Using Biodegradable Gate Dielectric Layer of Chicken Albumen

    NASA Astrophysics Data System (ADS)

    Jeon, Da-Bin; Bak, Jun-Yong; Yoon, Sung-Min

    2013-12-01

    An oxide thin-film transistor (TFT) using chicken albumen as gate dielectric on paper substrate was demonstrated. Chicken albumen, which was directly extracted from chicken egg white, was deposited as gate dielectric layer. An In-Ga-Zn-O was chosen as an active channel. The TFT feasibilities were successfully confirmed, in which channel mobility and subthreshold slope of the TFT were 6.48 cm2 V-1 s-1 and 1.28 V/s, respectively. This is the first report on the device configuration combining the biodegradable gate insulator and oxide semiconducting channel.

  7. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Saini, S.

    2000-01-01

    In this paper for the first time we study the influence of the polysilicon gate on the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with tunnelling gate oxides. This is done by using an efficient 3D 'atomistic' simulation technique described elsewhere. Devices with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveale that the polysilicon gate is responsible for a substantial fraction of the threshold voltage fluctuations in both devices when the gate oxide is scaled to tunnelling thickness in the range of 1 - 2 nm.

  8. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    NASA Astrophysics Data System (ADS)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  9. Edge determination for polycrystalline silicon lines on gate oxide

    NASA Astrophysics Data System (ADS)

    Villarrubia, John S.; Vladar, Andras E.; Lowney, Jeremiah R.; Postek, Michael T., Jr.

    2001-08-01

    In a scanning electron microscope (SEM) top-down secondary electron image, areas within a few tens of nanometers of the line edges are characteristically brighter than the rest of the image. In general, the shape of the secondary electron signal within such edge regions depends upon the energy and spatial distribution of the electron beam and the sample composition, and it is sensitive to small variations in sample geometry. Assigning edge shape and position is done by finding a model sample that is calculated, on the basis of a mathematical model of the instrument-sample interaction, to produce an image equal to the one actually observed. Edge locations, and consequently line widths, are then assigned based upon this model sample. In previous years we have applied this strategy to lines with geometry constrained by preferential etching of single crystal silicon. With this study we test the procedure on polycrystalline silicon lines. Polycrystalline silicon lines fabricated according to usual industrial processes represent a commercially interesting albeit technically more challenging application of this method. With the sample geometry less constrained a priori, a larger set of possible sample geometries must be modeled and tested for a match to the observed line scan, and the possibility of encountering multiple acceptable matches is increased. For this study we have implemented a data analysis procedure that matches measured image line scans to a precomputed library of sample shapes and their corresponding line scans. Linewidth test patterns containing both isolated and dense lines separated form the underlying silicon substrate by a thin gate oxide have been fabricated. Line scans from test pattern images have been fitted to the library of modeled shapes.

  10. High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

    NASA Astrophysics Data System (ADS)

    Pyo, Ju-Young; Cho, Won-Ju

    2017-03-01

    In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH‑1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

  11. Gate oxide shorts in nMOS transistors: Electrical properties and lifetime prediction method

    SciTech Connect

    Dababneh, S.A.; Hawkins, C.F.; Soden, J.M.

    1994-09-01

    Degradation in nMOS transistors from gate oxide shorts is dependent upon oxide trapping and interface state generation. Three distinct damage mechanisms were identified, including generation of: (1) electron traps in the bulk oxide by the injected holes, N{sub ox,h}, (2) electron traps in the bulk oxide by the injected electrons, N{sub ox,e}, and (3) interface states, N{sub ss}. The three damage mechanisms are incorporated into a device lifetime prediction method.

  12. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films.

    PubMed

    Leng, X; Bollinger, A T; Božović, I

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  13. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    SciTech Connect

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.

  14. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    DOE PAGES

    Leng, X.; Bozovic, I.; Bollinger, A. T.

    2016-08-10

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a puremore » electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices.« less

  15. Purely electronic mechanism of electrolyte gating of indium tin oxide thin films

    PubMed Central

    Leng, X.; Bollinger, A. T.; Božović, I.

    2016-01-01

    Epitaxial indium tin oxide films have been grown on both LaAlO3 and yttria-stabilized zirconia substrates using RF magnetron sputtering. Electrolyte gating causes a large change in the film resistance that occurs immediately after the gate voltage is applied, and shows no hysteresis during the charging/discharging processes. When two devices are patterned next to one another and the first one gated through an electrolyte, the second one shows no changes in conductance, in contrast to what happens in materials (like tungsten oxide) susceptible to ionic electromigration and intercalation. These findings indicate that electrolyte gating in indium tin oxide triggers a pure electronic process (electron depletion or accumulation, depending on the polarity of the gate voltage), with no electrochemical reactions involved. Electron accumulation occurs in a very thin layer near the film surface, which becomes highly conductive. These results contribute to our understanding of the electrolyte gating mechanism in complex oxides and may be relevant for applications of electric double layer transistor devices. PMID:27506371

  16. Theoretical evaluation of zirconia and hafnia as gate oxides for si microelectronics.

    PubMed

    Fiorentini, Vincenzo; Gulleri, Gianluca

    2002-12-23

    Parameters determining the performance of the crystalline oxides zirconia (ZrO2) and hafnia (HfO2) as gate insulators in nanometric Si electronics are estimated via ab initio calculations of the energetics, dielectric properties, and band alignment of bulk and thin-film oxides on Si (001). With their large dielectric constants, stable and low-formation-energy interfaces, large valence offsets, and reasonable (though not optimal) conduction offsets (electron injection barriers), zirconia and hafnia appear to have considerable potential as gate oxides for Si electronics.

  17. Transient characteristics for proton gating in laterally coupled indium-zinc-oxide transistors.

    PubMed

    Liu, Ning; Zhu, Li Qiang; Xiao, Hui; Wan, Chang Jin; Liu, Yang Hui; Chao, Jin Yu

    2015-03-25

    The control and detection over processing, transport and delivery of chemical species is of great importance in sensors and biological systems. The transient characteristics of the migration of chemical species reflect the basic properties in the processings of chemical species. Here, we observed the field-configurable proton effects in a laterally coupled transistor gated by phosphorosilicate glass (PSG). The bias on the lateral gate would modulate the interplay between protons and electrons at the PSG/indium-zinc-oxide (IZO) channel interface. Due to the modulation of protons flux within the PSG films, the IZO channel current would be modified correspondingly. The characteristic time for the proton gating is estimated to be on the order of 20 ms. Such laterally coupled oxide based transistors with proton gating are promising for low-cost portable biosensors and neuromorphic system applications.

  18. Room-temperature phosphorescence logic gates developed from nucleic acid functionalized carbon dots and graphene oxide

    NASA Astrophysics Data System (ADS)

    Gui, Rijun; Jin, Hui; Wang, Zonghua; Zhang, Feifei; Xia, Jianfei; Yang, Min; Bi, Sai; Xia, Yanzhi

    2015-04-01

    Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs.Room-temperature phosphorescence (RTP) logic gates were developed using capture ssDNA (cDNA) modified carbon dots and graphene oxide (GO). The experimental results suggested the feasibility of these developed RTP-based ``OR'', ``INHIBIT'' and ``OR-INHIBIT'' logic gate operations, using Hg2+, target ssDNA (tDNA) and doxorubicin (DOX) as inputs. Electronic supplementary information (ESI) available: All experimental details, Part S1-3, Fig. S1-6 and Table S1. See DOI: 10.1039/c4nr07620f

  19. Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

    NASA Astrophysics Data System (ADS)

    Pradhan, K. P.; Priyanka; Sahu, P. K.

    2016-01-01

    Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

  20. A Novel Gate Electrode Structure for Reduction of Gate Resistance of Sub-0.1 µm RF/Mixed-Signal Metal Oxide Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Nagase, Hirokazu; Tanabe, Akira; Umeda, Kyoko; Watanabe, Takashi; Hayashi, Yoshihiro

    2009-04-01

    To reduce noise and enhance gain for scaled-down metal oxide semiconductor field-effect transistors (MOSFETs), a novel gate electrode structure “direct finger contact (DFC)” is proposed. The DFC structure reduces the gate electrode resistance by 40%. NF50 (noise figure when the input impedance is 50 Ω) is reduced by 4% with the gate length L = 48 nm, the gate width Wfinger =1 µm, and the number of finger N =20. This structure is suitable for low-noise sub-0.1 µm RF/mixed-signal system on chips (SoCs).

  1. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    SciTech Connect

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin

    2016-07-15

    We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  2. Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

    NASA Astrophysics Data System (ADS)

    Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin

    2016-07-01

    We report the abnormal behavior of the threshold voltage (VTH) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (VTG), while bottom gate bias (VBG) is less effect than VTG. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO2/a-IGZO and also the existence of large amount of In+ under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH- at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of VTG both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

  3. Technologies for suppressing charge-traps in novel p-channel Field-MOSFET with thick gate oxide

    NASA Astrophysics Data System (ADS)

    Miyoshi, Tomoyuki; Oshima, Takayuki; Noguchi, Junji

    2015-05-01

    High voltage laterally diffused MOS (LDMOS) FETs are widely used in analog applications. A Field-MOSFET with a thick gate oxide is one of the best ways of achieving a simpler design and smaller circuit footprint for high-voltage analog circuits. This paper focuses on an approach to improving the reliability of p-channel Field-MOSFETs. By introducing a fluorine implantation process and terminating fluorine at the LOCOS bird’s beak, the gate oxide breakdown voltage could be raised to 350 V at a high-slew rate and the negative bias temperature instability (NBTI) shift could be kept to within 15% over a product’s lifetime. By controlling the amount of charge in the insulating layer through improving the interlayer dielectric (ILD) deposition processes, a higher BVDSS of 370 V and 10-year tolerability of 300 V were obtained with an assisted reduced surface electric field (RESURF) effect. These techniques can supply an efficient solution for ensuring reliable high-performance applications.

  4. Challenges of Electrical Measurements of Advanced Gate Dielectrics in Metal-Oxide-Semiconductor Devices

    NASA Astrophysics Data System (ADS)

    Vogel, Eric M.; Brown, George A.

    2003-09-01

    Experimental measurements and simulations are used to provide an overview of key issues with the electrical characterization of metal-oxide-semiconductor (MOS) devices with ultra-thin oxide and alternate gate dielectrics. Experimental issues associated with the most common electrical characterization method, capacitance-voltage (C-V), are first described. Issues associated with equivalent oxide thickness extraction and comparison, interface state measurement, extrinsic defects, and defect generation are then overviewed.

  5. Feasibility study of detection of dielectric breakdown of gate oxide film by using acoustic emission method

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Uesugi, Fumihiko

    2016-12-01

    An in situ detection method for the dielectric breakdown of oxide films for MOS gates has been required in the plasma etching process. In this feasibility study, a conventional MOSFET device is used and an acoustic emission (AE) method is employed for the detection of the dielectric breakdown of a gate oxide film. A thin type AE sensor is attached at the backside of an electrostatic chuck (ESC), and the dielectric breakdown in a MOSFET, which is set on the ESC, is detected. The results demonstrate that the thin type AE sensor can detect the dielectric breakdown with an energy on the order of µJ.

  6. SEMICONDUCTOR DEVICES Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

    NASA Astrophysics Data System (ADS)

    Yan, Han; Bin, Zhang; Koubao, Ding; Shifeng, Zhang; Chenggong, Han; Jiaxian, Hu; Dazhong, Zhu

    2010-12-01

    The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS (SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift (NDD) region implant on Ron degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced Ron degradation effectively, which is different from uniform gate oxide NLDMOS (UG-NLDMOS) transistors.

  7. A Dual-Gate Memory Cell with Two Inter-Poly Oxides

    NASA Astrophysics Data System (ADS)

    Raguet, Jean-René; Calenzo, Patrick; Laffont, Romain; Deleruyelle, Damien; Bouchakour, Rachid; Bidal, Virginie; Regnier, Arnaud; Niel, Stephan; Fornara, Pascal; Mirabel, Jean-Michel

    2009-04-01

    A new dual-gate memory cell with two different inter-poly oxides is presented in this paper. This cell allows high density memory application and a cell programming only with the dual-gate without high bias on drain or source compared to standard electrical erasable and programmable read-only memory (EEPROM). Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 48%. The specificity is to use a dual-gate to program the cell with two different ways of charge injection and perform the memory operations without high bias on drain and also without select transistor. Thus this cell can be shrunk more easily and its lifetime can be improved because the band to band tunneling stress due to high drain potential is eliminated. Moreover, this dual-gate cell can become an adjustable threshold voltage transistor.

  8. ResearchGate is no longer reliable: leniency towards ghost journals may decrease its impact on the scientific community.

    PubMed

    Memon, Aamir Raoof

    2016-12-01

    ResearchGate has been regarded as one of the most attractive academic social networking site for scientific community. It has been trying to improve user-centered interfaces to gain more attractiveness to scientists around the world. Display of journal related scietometric measures (such as impact factor, 5-year impact, cited half-life, eigenfactor) is an important feature in ResearchGate. Open access publishing has added more to increased visibility of research work and easy access to information related to research. Moreover, scientific community has been much interested in promoting their work and exhibiting its impact to others through reliable scientometric measures. However, with the growing market of publications and improvements in the field of research, this community has been victimized by the cybercrime in the form of ghost journals, fake publishers and magical impact measures. Particularly, ResearchGate more recently, has been lenient in its policies against this dark side of academic writing. Therefore, this communication aims to discuss concerns associated with leniency in ResearchGate policies and its impact of scientific community.

  9. Concurrent validity and test-retest reliability of a global positioning system (GPS) and timing gates to assess sprint performance variables.

    PubMed

    Waldron, Mark; Worsfold, Paul; Twist, Craig; Lamb, Kevin

    2011-12-01

    There has been no previous investigation of the concurrent validity and reliability of the current 5 Hz global positioning system (GPS) to assess sprinting speed or the reliability of integrated GPS-accelerometer technology. In the present study, we wished to determine: (1) the concurrent validity and reliability of a GPS and timing gates to measure sprinting speed or distance, and (2) the reliability of proper accelerations recorded via GPS-accelerometer integration. Nineteen elite youth rugby league players performed two over-ground sprints and were simultaneously assessed using GPS and timing gates. The GPS measurements systematically underestimated both distance and timing gate speed. The GPS measurements were reliable for all variables of distance and speed (coefficient of variation [CV] = 1.62% to 2.3%), particularly peak speed (95% limits of agreement [LOA] = 0.00 ± 0.8 km · h(-1); CV = 0.78%). Timing gates were more reliable (CV = 1% to 1.54%) than equivalent GPS measurements. Accelerometer measurements were least reliable (CV = 4.69% to 5.16%), particularly for the frequency of proper accelerations (95% LOA = 1.00 ± 5.43; CV = 14.12%). Timing gates and GPS were found to reliably assess speed and distance, although the validity of the GPS remains questionable. The error found in accelerometer measurements indicates the limits of this device for detecting changes in performance.

  10. Performance and reliability of HfAlO x-based interpoly dielectrics for floating-gate Flash memory

    NASA Astrophysics Data System (ADS)

    Govoreanu, B.; Wellekens, D.; Haspeslagh, L.; Brunco, D. P.; De Vos, J.; Aguado, D. Ruiz; Blomme, P.; van der Zanden, K.; Van Houdt, J.

    2008-04-01

    This paper discusses the performance and reliability of aggressively scaled HfAlO x-based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45 nm non-volatile memory technologies. It is shown that a less than 5 nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3 V at 150 °C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed.

  11. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    PubMed

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  12. Electrical control of Co/Ni magnetism adjacent to gate oxides with low oxygen ion mobility

    SciTech Connect

    Yan, Y. N.; Zhou, X. J.; Li, F.; Cui, B.; Wang, Y. Y.; Wang, G. Y.; Pan, F.; Song, C.

    2015-09-21

    We investigate the electrical manipulation of Co/Ni magnetization through a combination of ionic liquid and oxide gating, where HfO{sub 2} with a low O{sup 2−} ion mobility is employed. A limited oxidation-reduction process at the metal/HfO{sub 2} interface can be induced by large electric field, which can greatly affect the saturated magnetization and Curie temperature of Co/Ni bilayer. Besides the oxidation/reduction process, first-principles calculations show that the variation of d electrons is also responsible for the magnetization variation. Our work discloses the role of gate oxides with a relatively low O{sup 2−} ion mobility in electrical control of magnetism, and might pave the way for the magneto-ionic memory with low power consumption and high endurance performance.

  13. Threshold voltage control of electrolyte solution gate field-effect transistor by electrochemical oxidation

    NASA Astrophysics Data System (ADS)

    Naramura, Takuro; Inaba, Masafumi; Mizuno, Sho; Igarashi, Keisuke; Kida, Eriko; Mohd Sukri, Shaili Falina; Shintani, Yukihiro; Kawarada, Hiroshi

    2017-07-01

    Diamond electrolyte solution-gate-field effect transistors (SGFETs) are suitable for applications as chemical ion sensors because of their wide potential window and good physical and chemical stabilities. In this study, we fabricated an anodically oxidized diamond SGFET from a full hydrogen-terminated diamond SGFET and demonstrated control of the device threshold voltage by irreversible anodic oxidation. The applied anodic bias voltage (VAO) was varied gradually from low to high (1.1-1.7 V). As the anodic oxidation proceeded, the threshold voltage shifted to more negative values with no degradation of hole mobility. Thus, anodic oxidation is a useful method for controlling the threshold voltage of diamond SGFETs.

  14. Advanced high-k gate dielectric amorphous LaGdO3 gated metal-oxide-semiconductor devices with sub-nanometer equivalent oxide thickness

    NASA Astrophysics Data System (ADS)

    Pavunny, S. P.; Misra, P.; Thomas, R.; Kumar, A.; Schubert, J.; Scott, J. F.; Katiyar, R. S.

    2013-05-01

    Careful selection of pulsed laser deposition conditions was executed to achieve sub-nanometer EOT (equivalent oxide thickness) in amorphous LaGdO3 based high-k/metal gate stacks. The lowest EOTs attained were ˜5.4 Å and 8.4 Å with and without quantum mechanical correction, respectively. The electrical measurements yielded a high permittivity of 20.5 ± 2.4, a thin bottom interfacial layer of thickness 4.5 ± 1 Å, and interface (cm-2 eV-1) and fixed (cm-2) charge densities of ˜1012. Analysis of temperature dependent leakage currents revealed that gate injection current was dominated by Schottky emission below 1.2 MV/cm and quantum mechanical tunneling above this field. The physical origin of substrate injection was found to be a combination of Schottky emission and trap assisted tunneling.

  15. Oxide-based synaptic transistors gated by solution-processed gelatin electrolytes

    NASA Astrophysics Data System (ADS)

    He, Yinke; Sun, Jia; Qian, Chuan; Kong, Ling-An; Gou, Guangyang; Li, Hongjian

    2017-04-01

    In human brain, a large number of neurons are connected via synapses. Simulation of the synaptic behaviors using electronic devices is the most important step for neuromorphic systems. In this paper, proton conducting gelatin electrolyte-gated oxide field-effect transistors (FETs) were used for emulating synaptic functions, in which the gate electrode is regarded as pre-synaptic neuron and the channel layer as the post-synaptic neuron. In analogy to the biological synapse, a potential spike can be applied at the gate electrode and trigger ionic motion in the gelatin electrolyte, which in turn generates excitatory post-synaptic current (EPSC) in the channel layer. Basic synaptic behaviors including spike time-dependent EPSC, paired-pulse facilitation (PPF), self-adaptation, and frequency-dependent synaptic transmission were successfully mimicked. Such ionic/electronic hybrid devices are beneficial for synaptic electronics and brain-inspired neuromorphic systems.

  16. Gap protection and dynamical decoupling for reliable multi-qubit gates

    NASA Astrophysics Data System (ADS)

    Witzel, Wayne

    2014-03-01

    We propose a scheme for producing multi-qubit gates by adiabatically shuttling an electron between donors in silicon to produce operations that are diagonal in the computational basis. Exploiting the commutation of these diagonal operations, we can use single-qubit refocusing gates to cancel the sensitivity to low-frequency noise and details of the shuttling. This strategy of cancelling unwanted portions of an adiabatic process to build up robust multi-qubit operations could be applied to other systems. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL8.

  17. Tin oxide nanowire sensor with integrated temperature and gate control for multi-gas recognition.

    PubMed

    Dattoli, Eric N; Davydov, Albert V; Benkstein, Kurt D

    2012-03-07

    The selectivity of a chemiresistive gas sensor comprising an array of single-crystalline tin oxide nanowires (NWs) is shown to be greatly enhanced by combined temperature and gate voltage modulation. This dual modulation was effected by a novel microsensor platform that consisted of a suspended nitride membrane embedded with independently addressable platinum heater and back-gate structures. The sensor was evaluated in a chemical vapor exposure test consisting of three volatile organic compound (VOC) analytes in an air background; VOC concentrations ranged from 20 μmol/mol to 80 μmol/mol. During the exposure test, the temperature and gating conditions of the NW sensor were modulated in order to induce variations in the sensor's analyte response behavior. By treating these temperature- and gate-dependent analyte response variations as an identifying "fingerprint," analyte identification was achieved using a statistical pattern recognition procedure, linear discriminant analysis (LDA). Through optimization of this pattern recognition procedure, a VOC recognition rate of 98% was obtained. An analysis of the recognition results revealed that this high recognition rate could only be achieved through the combined modulation of temperature and gate bias as compared to either parameter alone. Overall, the highly accurate VOC analyte discrimination that was achieved here confirms the selectivity benefits provided by the utilized dual modulation approach and demonstrates the suitability of miniature nanowire sensors in real-world, multi-chemical detection problems.

  18. Study of the relative performance of silicon and germanium nanoparticles embedded gate oxide in metal-oxide-semiconductor memory devices

    NASA Astrophysics Data System (ADS)

    Chakraborty, G.; Sengupta, A.; Requejo, F. G.; Sarkar, C. K.

    2011-03-01

    In the present work, we have investigated a comparative performance of the silicon (Si) and germanium (Ge) nanoparticles embedded SiO2 floating gate MOS memory devices. In such devices for low applied fields, the tunneling current is dominated by the direct tunneling mechanism, whereas for higher electric fields, the Fowler-Nordheim tunneling mechanism dominates. As the device dimensions get smaller, problem arises in the conventional MOS memory devices due to the leakage through the thin tunnel oxide. This leakage can be reduced via charge trapping by embedding nanoparticles in the gate dielectric of such devices. Here one objective is to prevent the leakage due to the direct tunneling mechanism and the other objective is to reduce the write voltage, by lowering the onset voltage of the Fowler-Nordheim tunneling mechanism. Our simulations for the current voltage characteristics covered both the low and the high applied field regions. Simulations showed that both the Si and the Ge nanoparticles embedded gate dielectrics offer reduction of the leakage current and a significant lowering of the writing or programming onset voltage, compared to the pure SiO2 gate dielectric. In terms of the comparative performance, the Germanium nanoparticles embedded gate dielectric showed better results compared to the silicon nanoparticles embedded one. The results of the simulations are discussed in the light of recent experimental results.

  19. Mechanically reliable surface oxides for high-temperature corrosion resistance

    SciTech Connect

    Natesan, K.; Veal, B.W.; Grimsditch, M.; Renusch, D.; Paulikas, A.P.

    1995-05-01

    Corrosion is widely recognized as being important, but an understanding of the underlying phenomena involves factors such as the chemistry and physics of early stages of oxidation, chemistry and bonding at the substrate/oxide interface, role of segregants on the strength of that bond, transport processes through scale, mechanisms of residual stress generation and relief, and fracture behavior at the oxide/substrate interface. Because of this complexity a multilaboratory program has been initiated under the auspices of the DOE Center of Excellence for the Synthesis and Processing of Advanced Materials, with strong interactions and cross-leveraging with DOE Fossil Energy and US industry. Objective is to systematically generate the knowledge required to establish a scientific basis for designing and synthesizing improved protective oxide scales/coatings (slow-growing, adherent, sound) on high-temperature materials without compromising the requisite properties of the bulk materials. The objectives of program work at Argonne are to (1) correlate actual corrosion performance with stresses, voids, segregants, interface roughness, initial stages of oxidation, and microstructures; (2) study such behavior in growing or as-grown films; and (3) define prescriptive design and synthesis routes to mechanically reliable surface oxides. Several techniques, such as Auger electron spectroscopy, X-ray diffraction, X-ray grazing incidence reflectance, grazing-angle X-ray fluorescence, optical fluorescence, and Raman spectroscopy, are used in the studies. Tne project has selected Fe-25 wt.% Cr-20 wt.% Ni and Fe-Cr-Al alloys, which are chromia- and alumina-formers respectively, for the studies. This paper presents some of the results on early stages of oxidation and on surface segregation of elements.

  20. Extended-Gate Metal Oxide Semiconductor Field Effect Transistor-Based Biosensor for Detection of Deoxynivalenol

    NASA Astrophysics Data System (ADS)

    Kwon, Insu; Lee, Hee-Ho; Choi, Jinhyeon; Shin, Jang-Kyoo; Seo, Sang-Ho; Choi, Sung-Wook; Chun, Hyang Sook

    2011-06-01

    In this work, we present an extended-gate metal oxide semiconductor field effect transistor (MOSFET)-based biosensor for the detection of deoxynivalenol using a null-balancing circuit. An extended-gate MOSFET-based biosensor was fabricated by a standard complementary metal oxide semiconductor (CMOS) process and its characteristics were measured. A null-balancing circuit was used to measure the output voltage of the sensor directly, instead of measuring the drain current of the sensor. Au was used as the gate metal, which has a chemical affinity with thiol, which leads to the immobilization of a self-assembled monolayer (SAM) of mercaptohexadecanoic acid (MHDA). The SAM was used to immobilize the anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti-deoxynivalenol antibody. The anti-deoxynivalenol antibody and deoxynivalenol were bound by their antigen-antibody reaction. The measurements were performed in phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl electrode was employed as a reference electrode. The bindings of a SAM, anti-deoxynivalenol antibody, and deoxynivalenol caused a variation in the output voltage of the extended-gate MOSFET-based biosensor. Surface plasmon resonance (SPR) measurement was performed to verify the interaction among the SAM, deoxynivalenol-antibody, and deoxynivalenol.

  1. Tin oxide nanowire sensor with integrated temperature and gate control for multi-gas recognition

    NASA Astrophysics Data System (ADS)

    Dattoli, Eric N.; Davydov, Albert V.; Benkstein, Kurt D.

    2012-02-01

    The selectivity of a chemiresistive gas sensor comprising an array of single-crystalline tin oxide nanowires (NWs) is shown to be greatly enhanced by combined temperature and gate voltage modulation. This dual modulation was effected by a novel microsensor platform that consisted of a suspended nitride membrane embedded with independently addressable platinum heater and back-gate structures. The sensor was evaluated in a chemical vapor exposure test consisting of three volatile organic compound (VOC) analytes in an air background; VOC concentrations ranged from 20 μmol/mol to 80 μmol/mol. During the exposure test, the temperature and gating conditions of the NW sensor were modulated in order to induce variations in the sensor's analyte response behavior. By treating these temperature- and gate-dependent analyte response variations as an identifying ``fingerprint,'' analyte identification was achieved using a statistical pattern recognition procedure, linear discriminant analysis (LDA). Through optimization of this pattern recognition procedure, a VOC recognition rate of 98% was obtained. An analysis of the recognition results revealed that this high recognition rate could only be achieved through the combined modulation of temperature and gate bias as compared to either parameter alone. Overall, the highly accurate VOC analyte discrimination that was achieved here confirms the selectivity benefits provided by the utilized dual modulation approach and demonstrates the suitability of miniature nanowire sensors in real-world, multi-chemical detection problems.The selectivity of a chemiresistive gas sensor comprising an array of single-crystalline tin oxide nanowires (NWs) is shown to be greatly enhanced by combined temperature and gate voltage modulation. This dual modulation was effected by a novel microsensor platform that consisted of a suspended nitride membrane embedded with independently addressable platinum heater and back-gate structures. The sensor was

  2. Frequency-dependent reliability of spike propagation is function of axonal voltage-gated sodium channels in cerebellar Purkinje cells.

    PubMed

    Yang, Zhilai; Wang, Jin-Hui

    2013-12-01

    The spike propagation on nerve axons, like synaptic transmission, is essential to ensure neuronal communication. The secure propagation of sequential spikes toward axonal terminals has been challenged in the neurons with a high firing rate, such as cerebellar Purkinje cells. The shortfall of spike propagation makes some digital spikes disappearing at axonal terminals, such that the elucidation of the mechanisms underlying spike propagation reliability is crucial to find the strategy of preventing loss of neuronal codes. As the spike propagation failure is influenced by the membrane potentials, this process is likely caused by altering the functional status of voltage-gated sodium channels (VGSC). We examined this hypothesis in Purkinje cells by using pair-recordings at their somata and axonal blebs in cerebellar slices. The reliability of spike propagation was deteriorated by elevating spike frequency. The frequency-dependent reliability of spike propagation was attenuated by inactivating VGSCs and improved by removing their inactivation. Thus, the functional status of axonal VGSCs influences the reliability of spike propagation.

  3. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry

    NASA Astrophysics Data System (ADS)

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  4. Note: Design and construction of a simple and reliable printed circuit board-substrate Bradbury-Nielsen gate for ion mobility spectrometry.

    PubMed

    Du, Yongzhai; Cang, Huaiwen; Wang, Weiguo; Han, Fenglei; Chen, Chuang; Li, Lin; Hou, Keyong; Li, Haiyang

    2011-08-01

    A less laborious, structure-simple, and performance-reliable printed circuit board (PCB) based Bradbury-Nielsen gate for high-resolution ion mobility spectrometry was introduced and investigated. The gate substrate was manufactured using a PCB etching process with small holes (Φ 0.1 mm) drilled along the gold-plated copper lines. Two interdigitated sets of rigid stainless steel spring wire (Φ 0.1 mm) that stands high temperature and guarantees performance stability were threaded through the holes. Our homebuilt ion mobility spectrometer mounted with the gate gave results of about 40 for resolution while keeping a signal intensity of over 0.5 nano-amperes.

  5. Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

    NASA Astrophysics Data System (ADS)

    Xu, Hui Fang; Gui Guan, Bang

    2017-05-01

    A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

  6. Band Offsets of a Ruthenium Gate on Ultrathin High-k Oxide Films on Silicon

    SciTech Connect

    Rangan, S.; Bersch, W; Bartynski, R; Garfunkel, E; Vescovo, E

    2009-01-01

    Valence-band and conduction-band edges of ultrathin oxides and their shifts upon sequential metallization with ruthenium have been measured using synchrotron-radiation-excited x-ray, ultraviolet, and inverse photoemissions. From these techniques, the offsets between the valence-band and conduction-band edges of the oxides, and the ruthenium metal gate Fermi edge have been directly measured. In addition the core levels of the oxides and the ruthenium have been characterized. Upon deposition, Ru remains metallic and no chemical alteration of the underlying oxide gates, or interfacial SiO{sub 2} in the case of the high-? thin films, can be detected. However a clear shift of the band edges is measured for all samples due to the creation of an interface dipole at the ruthenium-oxide interface. Using the energy gap, the electron affinity of the oxides, and the ruthenium work function that have been directly measured on these samples, the experimental band offsets are compared to those predicted by the induced gap states model.

  7. Characterization of reliability of printed indium tin oxide thin films.

    PubMed

    Hong, Sung-Jei; Kim, Jong-Woong; Jung, Seung-Boo

    2013-11-01

    Recently, decreasing the amount of indium (In) element in the indium tin oxide (ITO) used for transparent conductive oxide (TCO) thin film has become necessary for cost reduction. One possible approach to this problem is using printed ITO thin film instead of sputtered. Previous studies showed potential for printed ITO thin films as the TCO layer. However, nothing has been reported on the reliability of printed ITO thin films. Therefore, in this study, the reliability of printed ITO thin films was characterized. ITO nanoparticle ink was fabricated and printed onto a glass substrate followed by heating at 400 degrees C. After measurement of the initial values of sheet resistance and optical transmittance of the printed ITO thin films, their reliabilities were characterized with an isothermal-isohumidity test for 500 hours at 85 degrees C and 85% RH, a thermal shock test for 1,000 cycles between 125 degrees C and -40 degrees C, and a high temperature storage test for 500 hours at 125 degrees C. The same properties were investigated after the tests. Printed ITO thin films showed stable properties despite extremely thermal and humid conditions. Sheet resistances of the printed ITO thin films changed slightly from 435 omega/square to 735 omega/square 507 omega/square and 442 omega/square after the tests, respectively. Optical transmittances of the printed ITO thin films were slightly changed from 84.74% to 81.86%, 88.03% and 88.26% after the tests, respectively. These test results suggest the stability of printed ITO thin film despite extreme environments.

  8. Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

    NASA Astrophysics Data System (ADS)

    Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

    2017-10-01

    Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

  9. Effect of low and high temperature anneal on process-induced damage of gate oxide

    SciTech Connect

    King, J.C.; Hu, C. . Dept. of Electrical Engineering and Computer Sciences)

    1994-11-01

    The authors have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800 C anneal cannot restore the stability in interface trap generation. Even 900 C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows them to monitor the damages even at the end of the fabrication process.

  10. Impact of hot-carrier stress on gate-induced floating body effects and drain current transients of thin gate oxide partially depleted SOI nMOSFETs

    NASA Astrophysics Data System (ADS)

    Rafí, J. M.; Simoen, E.; Mercha, A.; Campabadal, F.; Claeys, C.

    2005-09-01

    The impact of hot-carrier (HC) stress on thin gate oxide PD SOI nMOSFETs is investigated by analyzing the front and back channel current-voltage characteristics and the switch-off drain current transients. A particular hot-carrier degradation mode, characterized by a turn-around behavior for front gate threshold voltage degradation, is analyzed for devices with different geometries, bias conditions and source/drain architecture. A significant positive back gate threshold voltage shift is also observed after long HC stress. The maximum hot-carrier degradation (HCD) is obtained for the highest front gate biases, corresponding to the conditions of maximum electron valence band injection of majority carriers into the floating body. The presence of the HCD is found to reduce both the generation and the recombination switch-off drain current transient times. Unbiased thermal annealing in the range of 200-250 °C significantly reduces the hot-carrier-induced damage affecting the back channel characteristics. Whereas front gate direct tunnel stress is not causing any significant degradation for stress biases up to about two times the power supply for this technology node and reasonably short stress times, for the highest stress conditions the drain current transients are found to be progressively faster till front gate dielectric breakdown occurs.

  11. Observation of Reliability of HfZrOX Gate Dielectric Devices with Different Zr/Hf Ratios

    NASA Astrophysics Data System (ADS)

    Liao, Jing-Chyi; Fang, Yean-Kuen; Tian Hou, Yong; Hsiung Tseng, Wei; Yang, Chih I.; Hsu, Peng Fu; Chao, Yuen Shun; Lin, Kang Cheng; Huang, Kuo Tai; Lee, Tzu Liang; Liang, Meng Sung

    2008-04-01

    The impact of the Zr/Hf ratio on the reliability of a HfZrOX gate dielectric has been investigated in detail. By a frequency-varied charge-pumping method, we found that the density of bulk traps is reduced with increasing Zr content. Also, a comparable Dit value observed by the rising/falling time-varied charge-pumping method suggests that Zr incorporation does not degrade the interface quality. Consequently, mobility increases with increasing Zr content in the HfZrOX dielectric and ˜25% mobility enhancement compared with that of HfO2 can be observed. However, the bulk trap density reduction reaches saturation at a higher Zr content. The improvement in positive-bias temperature instability (PBTI) was also demonstrated by both DC and pulse techniques. The smaller Vth shift in PBTI is attributed to the reduction of fast trapping and the generation of slow traps. Finally, a reduced gate-induced drain leakage current (GIDL) was also observed with increasing Zr content because of the reduction of trap-assisted tunneling in a high-k film.

  12. Control of trap density in channel layer for the higher stability of oxide thin film transistors under gate bias stress

    NASA Astrophysics Data System (ADS)

    Moon, Y. K.; Kim, W. S.; Kim, K. T.; Han, D. S.; Shin, S. Y.; Park, J. W.

    2011-12-01

    In this study, we investigated turn-on voltage (VON) stability of oxide-based TFTs under constant voltage stress for the TFTs including intrinsic ZnO, Hf-doped ZnO, and Hf-Zn-Sn-O channel layer. Also, to verify the effects of interfacial trap density on the TFTs stability, we employed SiNX and SiO2/SiNX as gate insulator, respectively. We found that the low trap density of the TFTs, including the interfacial trap density between channel and gate insulator, and oxide semiconductor bulk trap density is intimately related to excellent gate bias and temperature stability.

  13. Atomic-Scale Characterization of Oxide Thin Films Gated by Ionic Liquid

    SciTech Connect

    Lang, Andrew C.; Sloppy, Jennifer; Ghassemi, H.; Devlin, Robert C.; Sichel-Tissot, Rebecca J.; Idrobo Tapia, Juan Carlos; May, Steven J.; Taheri, Mitra L.

    2014-09-04

    Ionic liquids (ILs) have been considered for use in electrostatic gating in complex oxide systems. Understanding the ionic liquid/oxide interface, and any bias-induced electrochemical degradation, is critical for the interpretation of transport phenomena. The integrity of the interface between ionic liquid 1-ethyl-3-methylimidazolium hexafluorophosphate and La1/3Sr2/3FeO3 under various biasing conditions was examined by analytical transmission electron microscopy, and we report film degradation in the form of an irreversible chemical reaction regardless of the applied bias. This results in an intermixing region of 4–6 nm at the IL/oxide interface. Electron energy loss spectroscopy shows La and Fe migration into the ionic liquid, resulting in secondary phase formation under negative bias. Our approach can be extended to other ionic liquid/oxide systems in order to better understand the electrochemical stability window of these device structures.

  14. Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors

    NASA Astrophysics Data System (ADS)

    Stoesser, Anna; von Seggern, Falk; Purohit, Suneeti; Nasr, Babak; Kruk, Robert; Dehm, Simone; Wang, Di; Hahn, Horst; Dasgupta, Subho

    2016-10-01

    Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm2 V-1 s-1.

  15. High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

    PubMed

    Jaehnike, Felix; Pham, Duy Vu; Anselmann, Ralf; Bock, Claudia; Kunze, Ulrich

    2015-07-01

    A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

  16. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    PubMed Central

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-01-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems. PMID:27688042

  17. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    NASA Astrophysics Data System (ADS)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-09-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

  18. New Compact and Time-Efficient Reliability Physics Model for p-Type Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Sheu, Chorng-Jye

    2010-11-01

    In this paper, we present a new compact and time-efficient reliability physics model of drain, substrate, and gate currents for p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs). The pre-stress drain current and channel electric field are first calculated, and the spatial distribution of electron temperature along the channel is then derived using a simplified energy balance equation. Having calculated the nonlocal impact ionization coefficient and electron temperature, and modified the lucky-electron concept, the nonlocal electron substrate and gate currents can be derived. We use an oxide-trapping mechanism for calculating the spatial distribution of oxide-trapping charges, which are substituted into the damaged pMOSFETs drain current model; then we can model the hot-carrier-damaged drain current. This model is a time-saving computer-aided-design (CAD) model and is physics transparent for pMOSFETs.

  19. Ionizing radiation induced leakage current on ultra-thin gate oxides

    SciTech Connect

    Scarpa, A.; Paccagnella, A.; Montera, F.; Ghibaudo, G.; Pananakakis, G.; Fuochi, P.G.

    1997-12-01

    MOS capacitors with a 4.4 nm thick gate oxide have been exposed to {gamma} radiation from a Co{sup 60} source. As a result, the authors have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. They have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. They have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

  20. Al and Ge simultaneous oxidation using neutral beam post-oxidation for formation of gate stack structures

    SciTech Connect

    Ohno, Takeo; Nakayama, Daiki; Samukawa, Seiji

    2015-09-28

    To obtain a high-quality Germanium (Ge) metal–oxide–semiconductor structure, a Ge gate stacked structure was fabricated using neutral beam post-oxidation. After deposition of a 1-nm-thick Al metal film on a Ge substrate, simultaneous oxidation of Al and Ge was carried out at 300 °C, and a Ge oxide film with 29% GeO{sub 2} content was obtained by controlling the acceleration bias power of the neutral oxygen beam. In addition, the fabricated AlO{sub x}/GeO{sub x}/Ge structure achieved a low interface state density of less than 1 × 10{sup 11 }cm{sup −2 }eV{sup −1} near the midgap.

  1. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    SciTech Connect

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-23

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  2. Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Kondo, Hiroki; Sakashita, Mitsuo; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-06-01

    We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C- V characteristics of Al/Pr-oxide/Ge 3N 4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr 2O 3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge 3N 4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed.

  3. All-amorphous-oxide transparent, flexible thin-film transistors. Efficacy of bilayer gate dielectrics.

    PubMed

    Liu, Jun; Buchholz, D Bruce; Hennek, Jonathan W; Chang, Robert P H; Facchetti, Antonio; Marks, Tobin J

    2010-09-01

    Optically transparent and mechanically flexible thin-film transistors (TF-TFTs) composed exclusively of amorphous metal oxide films are fabricated on plastic substrates by combining an amorphous Ta(2)O(5)/SiO(x) bilayer transparent oxide insulator (TOI) gate dielectric with an amorphous zinc-indium-tin oxide (a-ZITO) transparent oxide semiconductor (TOS) channel and a-ZITO transparent oxide conductor (TOC) electrodes. The bilayer gate dielectric is fabricated by the post-cross-linking of vapor-deposited hexachlorodisiloxane-derived films to form thin SiO(x) layers (v-SiO(x)) on amorphous Ta(2)O(5) (a-Ta(2)O(5)) films grown by ion-assisted deposition at room temperature. The a-Ta(2)O(5)/v-SiO(x) bilayer TOI dielectric integrates the large capacitance of the high dielectric constant a-Ta(2)O(5) layer with the excellent dielectric/semiconductor interfacial compatibility of the v-SiO(x) layer in a-ZITO TOS-based TF-TFTs. These all-amorphous-oxide TF-TFTs, having a channel length and width of 100 and 2000 microm, respectively, perform far better than a-Ta(2)O(5)-only devices and exhibit saturation-regime field-effect mobilities of approximately 20 cm(2)/V x s, on-currents >10(-4) A, and current on-off ratios >10(5). These TFTs operate at low voltages (approximately 4.0 V) and exhibit good visible-region optical transparency and excellent mechanical flexibility.

  4. Study of gate oxide traps in HfO2/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

    NASA Astrophysics Data System (ADS)

    Sun, X.; Saadat, O. I.; Chang-Liao, K. S.; Palacios, T.; Cui, S.; Ma, T. P.

    2013-03-01

    We introduce an ac-transconductance method to profile the gate oxide traps in a HfO2 gated AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors (MOS-HEMTs) that can exchange carriers with metal gates, which in turn causes changes in analog and pulsed channel currents. The method extracts energy and spacial distributions of the oxide and interface traps under the gate from the frequency dependence of ac transconductance. We demonstrate the method using MOS-HEMTs with gate oxides that were annealed at different temperatures.

  5. Progressive breakdown dynamics and entropy production in ultrathin SiO2 gate oxides

    NASA Astrophysics Data System (ADS)

    Miranda, E.; Jiménez, D.; Suñé, J.

    2011-06-01

    The progressive breakdown of ultrathin (≈2nm) SiO2 gate oxides subjected to constant electrical stress is investigated using a simple equivalent circuit model. It is shown how the interplay among series, parallel, and filamentary conductances that represent the breakdown path and its surroundings leads under certain hypothesis to a sigmoidal current-time characteristic compatible with the experimental observations. The dynamical properties of the breakdown trajectories are analyzed in terms of the logistic potential function, the Lyapunov exponent, and the system's attractor. It is also shown that the current evolution is compatible with Prigogine's minimum entropy production principle.

  6. Dose dependence of interface traps in gate oxides at high levels of total dose

    SciTech Connect

    Baze, M.P.; Plaag, R.E.; Johnston, A.H. )

    1989-12-01

    Interface traps in gate oxides were found to saturate at high total dose levels. An empirical model was developed to describe the nonlinear dependence and saturation characteristics. Three different processes were studied including CMOS/SOS, hardened bulk CMOS and unhardened bulk CMOS using several combinations of dose rate and bias. An evaluation was made of the model's accuracy in extrapolating the effect of interface traps to very high doses. A possible application of the model in characterizing devices for space environments is discussed along with implications for a physical model of radiation induced interface trap buildup.

  7. Hydrogen annealing of silicon gate-nitride-oxide-silicon nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Topich, James A.; Turi, Raymond A.

    1982-10-01

    A hydrogen annealing study of silicon gate-nitride-oxide-silicon (SNOS) nonvolatile memory devices showed that the important parameter in determining the optimum hydrogen annealing temperature for maximum charge retention is the previous thermal history of the memory devices. If a memory device's charge retention is not degraded by high-temperature processing, then the hydrogen anneal should be at the silicon nitride deposition temperature. If a device is degraded by high-temperature processing, then the hydrogen anneal should be at the degradation temperature.

  8. High-k perovskite gate oxide BaHfO3

    NASA Astrophysics Data System (ADS)

    Kim, Young Mo; Park, Chulkwon; Ha, Taewoo; Kim, Useong; Kim, Namwook; Shin, Juyeon; Kim, Youjung; Yu, Jaejun; Kim, Jae Hoon; Char, Kookrin

    2017-01-01

    We have investigated epitaxial BaHfO3 as a high-k perovskite dielectric. From x-ray diffraction measurement, we confirmed the epitaxial growth of BaHfO3 on BaSnO3 and MgO. We measured optical and dielectric properties of the BaHfO3 gate insulator; the optical bandgap, the dielectric constant, and the breakdown field. Furthermore, we fabricated a perovskite heterostructure field effect transistor using epitaxial BaHfO3 as a gate insulator and La-doped BaSnO3 as a channel layer on SrTiO3 substrate. To reduce the threading dislocations and enhance the electrical properties of the channel, an undoped BaSnO3 buffer layer was grown on SrTiO3 substrates before the channel layer deposition. The device exhibited a field effect mobility value of 52.7 cm2 V-1 s-1, a Ion/Ioff ratio higher than 107, and a subthreshold swing value of 0.80 V dec-1. We compare the device performances with those of other field effect transistors based on BaSnO3 channels and different gate oxides.

  9. Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

    NASA Astrophysics Data System (ADS)

    Jur, Jesse Stephen

    The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

  10. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    PubMed Central

    Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-01-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

  11. Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

    NASA Astrophysics Data System (ADS)

    Park, Sungjun; Lee, Seyeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

    2015-08-01

    Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo.

  12. Dual Metal/High-k Gate-Last Complementary Metal-Oxide-Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

    NASA Astrophysics Data System (ADS)

    Kikuchi, Yoshiaki; Wakabayashi, Hitoshi; Tsukamoto, Masanori; Nagashima, Naoki

    2011-08-01

    For the first time, dual metal/high-k gate-last complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal-oxide-semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal-oxide-semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

  13. AlGaN/GaN metal oxide semiconductor heterostructure field-effect transistors with 4 nm thick Al2O3 gate oxide

    NASA Astrophysics Data System (ADS)

    Gregušová, D.; Stoklas, R.; Čičo, K.; Lalinský, T.; Kordoš, P.

    2007-08-01

    AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with 4 nm thick Al2O3 gate oxide were prepared and their performance was compared with that of AlGaN/GaN HFETs. The MOSHFETs yielded ~40% increase of the saturation drain current compared with the HFETs, which is larger than expected due to the gate oxide passivation. Despite a larger gate-channel separation in the MOSHFETs, a higher extrinsic transconductance than that of the HFETs was measured. The drift mobility of the MOSHFETs, evaluated on large-gate FET structures, was significantly higher than that of the HFETs. The zero-bias mobility for MOSHFETs and HFETs was 1950 cm2 V-1 s-1 and 1630 cm2 V-1 s-1, respectively. These features indicate an increase of the drift velocity and/or a decrease of the parasitic series resistance in the MOSHFETs. The current collapse, evaluated from pulsed I-V measurements, was highly suppressed in the MOSHFETs with 4 nm thick Al2O3 gate oxide. This result, together with the suppressed frequency dispersion of the capacitance, indicates that the density of traps in the Al2O3/AlGaN/GaN MOSHFETs was significantly reduced.

  14. Multiplexed aptasensors and amplified DNA sensors using functionalized graphene oxide: application for logic gate operations.

    PubMed

    Liu, Xiaoqing; Aizen, Ruth; Freeman, Ronit; Yehezkeli, Omer; Willner, Itamar

    2012-04-24

    Graphene oxide (GO) is implemented as a functional matrix for developing fluorescent sensors for the amplified multiplexed detection of DNA, aptamer-substrate complexes, and for the integration of predesigned DNA constructs that activate logic gate operations. Fluorophore-labeled DNA strands acting as probes for two different DNA targets are adsorbed onto GO, leading to the quenching of the luminescence of the fluorophores. Desorption of the probes from the GO, through hybridization with the target DNAs, leads to the fluorescence of the respective label. By coupling exonuclease III, Exo III, to the system, the recycling of the target DNAs is demonstrated, and this leads to the amplified detection of the DNA targets (detection limit 5 × 10(-12) M). Similarly, adsorption of fluorophore-functionalized aptamers against thrombin or ATP onto the GO leads to the desorption of the aptamer-substrate complexes from GO and to the triggering of the luminescence corresponding to the respective fluorophore, thus, allowing the multiplexed analysis of the aptamer-substrate complexes. By designing functional fluorophore-labeled DNA constructs and their interaction with GO, in the presence (or absence) of nucleic acids, or two different substrates for aptamers, as inputs, the activation of the "OR" and "AND" logic gates is demonstrated.

  15. Gate Metal-Induced Diffusion and Interface Reactions in Hf Oxide Films on Si

    SciTech Connect

    Goncharova, Lyudmila V.; Dalponte, Mateus; Celik, Ozgur; Garfunkel, Eric; Gustafsson, Torgny; Lysaght, Pat S.; Bersuker, Gennadi I.

    2007-09-26

    When metal electrodes are deposited on a high-{kappa} metal-oxide/SiO{sub 2}/Si stack, chemical interactions may occur both at the metal/high-{kappa} and the high-{kappa}/Si interfaces, causing changes in electrical performance. We report here results from medium energy ion scattering (MEIS) and x-ray photoelectron (XPS) studies of oxygen and silicon transport and interfacial layer reactions in multilayer gate stacks. Our results show that Ti deposition on HfO{sub 2}/SiO{sub 2}/Si stacks causes reduction of the SiO{sub 2} interfacial layer and (to a lesser extent) the HfO{sub 2} layer. Silicon atoms initially present in the interfacial SiO{sub 2} layer incorporate into the bottom of the high-{kappa} layer. Some evidence for titanium-silicon interdiffusion through the high-{kappa} film in the presence of a titanium gate in crystalline HfO{sub 2} films is also reported.

  16. Probing top-gated field effect transistor of reduced graphene oxide monolayer made by dielectrophoresis

    NASA Astrophysics Data System (ADS)

    Vasu, K. S.; Chakraborty, Biswanath; Sampath, S.; Sood, A. K.

    2010-08-01

    We demonstrate a top-gated field effect transistor made of a reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. The Raman spectrum of RGO flakes of typical size of 5 μm×5 μm shows a single 2D band at 2687 cm -1, characteristic of single-layer graphene. The two-probe current-voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 μm using ac dielectrophoresis, show ohmic behavior with a resistance of ˜37 kΩ. The temperature dependence of the resistance (R) of RGO measured between 305 K and 393 K yields a temperature coefficient of resistance [dR/dT]/R˜-9.5×10-4/K, the same as that of mechanically exfoliated single-layer graphene. The field-effect transistor action was obtained by electrochemical top-gating using a solid polymer electrolyte (PEO+LiClO 4) and Pt wire. The ambipolar nature of graphene flakes is observed up to a doping level of ˜6×1012/cm and carrier mobility of ˜50 cm 2/V s. The source-drain current characteristics show a tendency of current saturation at high source-drain voltage which is analyzed quantitatively by a diffusive transport model.

  17. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    NASA Astrophysics Data System (ADS)

    Inaba, Masafumi; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-01

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al2O3. Using Al2O3 as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  18. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    SciTech Connect

    Inaba, Masafumi Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi; Kawarada, Hiroshi

    2016-07-18

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  19. Current-driven phase-change optical gate switch using indium-tin-oxide heater

    NASA Astrophysics Data System (ADS)

    Kato, Kentaro; Kuwahara, Masashi; Kawashima, Hitoshi; Tsuruoka, Tohru; Tsuda, Hiroyuki

    2017-07-01

    We proposed and fabricated a current-driven phase-change optical gate switch using a Ge2Sb2Te5 (GST225) thin film, an indium-tin-oxide (ITO) heater, and a Si waveguide. Microfabrication technology compatible with CMOS fabrication was used for the fabrication of the Si waveguide. The repetitive phase changing of GST225 was obtained by injecting a current pulse into the ITO heater beneath the GST225 thin film. The switching operation was observed by injecting a 100-ns current pulse of 20 mA into the ITO heater. The average extinction ratio over the wavelength range of 1,525 to 1,625 nm was 1.2 dB.

  20. Hydrogen Electrochemistry in SiO2 Related to Breakdown of Gate Oxides

    NASA Astrophysics Data System (ADS)

    Bloechl, Peter

    2000-03-01

    Further scaling of semiconductor devices faces major difficulties due to the limited lifetime of the gate oxide, which will be scaled below 2 ~ nm within 5 years. Breakdown has been correlated with stress-induced leakage currents (SILC) induced by hydrogen. State-of-the-art electronic structure calculations of defects related to hydrogen and oxygen vacancies in SiO2 have been performed. The origin of the SILC is attributed to the hydrogen bridge, as the only stable defect allowing two-step tunneling below 3 ~eV. The result is confirmed by EDMR measurements. I argue that SILC is not the direct cause of SILC, but some related electrochemical process. Hydrogen reactions with SiO2 indicate the creation of charged coordination defects, which results in a pathway for hydrogen induced electromigration that potentially may be the cause of breakdown.

  1. Energy-dependent relaxation time in quaternary amorphous oxide semiconductors probed by gated Hall effect measurements

    NASA Astrophysics Data System (ADS)

    Socratous, Josephine; Watanabe, Shun; Banger, Kulbinder K.; Warwick, Christopher N.; Branquinho, Rita; Barquinha, Pedro; Martins, Rodrigo; Fortunato, Elvira; Sirringhaus, Henning

    2017-01-01

    Despite the success of exploiting the properties of amorphous oxide semiconductors for device applications, the charge transport in these materials is still not clearly understood. The observation of a definite Hall voltage suggests that electron transport in the conduction band is free-electron-like. However, the temperature dependence of the Hall and field-effect mobilities cannot be explained using a simple bandlike model. Here, we perform gated Hall effect measurements in field-effect transistors, which allow us to make two independent estimates of the charge carrier concentration and determine the Hall factor providing information on the energy dependence of the relaxation time. We demonstrate that the Hall factor in a range of sputtered and solution-processed quaternary amorphous oxides, such as a-InGaZnO, is close to two, while in ternary oxides, such as InZnO, it is near unity. This suggests that quaternary elements like Ga act as strong ionized impurity scattering centers in these materials.

  2. Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ho, Szu-Han; Chang, Ting-Chang; Wu, Chi-Wei; Lo, Wen-Hung; Chen, Ching-En; Tsai, Jyun-Yu; Liu, Guan-Ru; Chen, Hua-Mao; Lu, Ying-Shin; Wang, Bin-Wei; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Sze, Simon M.

    2013-01-01

    This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ɛhigh-k = Q + Esio2ɛsio2.

  3. Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Ho, Szu-Han; Chang, Ting-Chang; Wu, Chi-Wei; Lo, Wen-Hung; Chen, Ching-En; Tsai, Jyun-Yu; Luo, Hung-Ping; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Sze, Simon M.

    2012-07-01

    This letter investigates a hump in gate current after dynamic negative bias stress (NBS) in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. By measuring gate current under initial through body floating and source/drain floating, it shows that hole current flows from source/drain. The fitting of gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after dynamic NBS, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ɛhigh-k = Q + Esio2ɛsio2.

  4. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    NASA Astrophysics Data System (ADS)

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-01

    We have studied the effect of top gate bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from -15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e-/2e-), peroxide (O22-) formation or conversion of ionized interstitial (Oi2-) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows -2.7 V shift at VTG = -15 V, which gradually decreases to -0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22-/Oi) and/or hole trapping in the a-IGZO /interfaces.

  5. Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

    NASA Astrophysics Data System (ADS)

    Choi, Youn Sung; Numata, Toshinori; Nishida, Toshikazu; Harris, Rusty; Thompson, Scott E.

    2008-03-01

    Uniaxial four-point wafer bending stress-altered gate tunneling currents are measured for germanium (Ge)/silicon (Si) channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with HfO2/SiO2 gate dielectrics and TiN/P+ poly Si electrodes. Carrier separation is used to measure electron and hole currents. The strain-altered hole tunneling current from the p-type inversion layer of Ge is measured to be ˜4 times larger than that for the Si channel MOSFET, since the larger strain-induced valence band-edge splitting in Ge results in more hole repopulation into a subband with a smaller out-of-plane effective mass and a lower tunneling barrier height. The strain-altered electron tunneling current from the metal gate is measured and shown to change due to strain altering the metal work function as quantified by flatband voltage shift measurements of Si MOS capacitors with TaN electrodes.

  6. Unified model for physics-based modelling of a new device architecture: triple material gate oxide stack epitaxial channel profile (TRIMGAS Epi) MOSFET

    NASA Astrophysics Data System (ADS)

    Goel, Kirti; Saxena, Manoj; Gupta, Mridula; Gupta, R. S.

    2007-04-01

    A new device architecture triple material gate oxide stack (TRIMGAS) epitaxial channel (Epi) MOSFET for reduced short channel effects (SCEs) at short gate lengths is proposed. The structure has a gate electrode consisting of three different materials, an oxide stack having high-K material on top of an SiO2 layer and an epitaxial channel profile. A two-dimensional analytical threshold voltage and drain current model has been presented. An analysis of subthreshold slope and I-V characteristics has been done for the first time including all regions of operation. The model proposed is capable of modelling various other MOSFET structures: (a) dual material gate stack (DUMGAS), (b) single material gate stack (SIMGAS), (c) straddle-gate/EJ/side-gate MOSFET oxide stack, (d) dual/hetero material gate (DMG/HMG), (e) single material gate (SMG) and (f) triple material gate (TMG), all with and without an epitaxial channel profile. A 2D device simulator, ATLAS, is used over a wide range of parameters and bias conditions to validate the analytical results.

  7. Time-delay-and-integration charge-coupled devices using tin oxide gate technology. [for Landsat MSS

    NASA Technical Reports Server (NTRS)

    Thompson, L. L.; Mccann, D. H.; Tracy, R. A.; Kub, F. J.; White, M. H.

    1978-01-01

    Doped tin oxide gates are used in a time-delay-and-integration (TDI) CCD scheme in an effort to develop a stable transparent gate technology. Design characteristics of the system are discussed, including 2 sections of 10 by 9 integration stages, four-phase buried channel construction, and 10 input parallel-in/serial-out output shift register at a video rate of 1.25 MHz. A quantum efficiency of 65% with smooth spectral response is attained by front surface imaging. The suitability of the system for the Landsat program is discussed in terms of TDI-CCD operating parameters.

  8. Electronic States of Hafnium and Vanadium oxide in Silicon Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Zhu, Chiyu; Tang, Fu; Liu, Xin; Yang, Jialing; Nemanich, Robert

    2010-03-01

    Vanadium oxide (VO2) is a narrow band gap material with a metal-insulator transition (MIT) at less than 100C. Hafnium oxide (HfO2) is currently the preferred high-k material for gate dielectrics. To utilize VO2 in a charge storage device, it is necessary to understand the band relationships between VO2, HfO2, and Si substrate. In this study, a 2nm thick VO2 layer is embedded in a dielectric stack structure between an oxidized n-type Si(100) surface and a 2nm HfO2 layer. The in situ experiments are carried out in an UHV multi-chamber system. After each growth step, the surface is characterized using XPS and UPS. After the initial plasma cleaning and oxidation treatment the Si substrate displayed essentially flat bands at the surface. After deposition of the VO2 layer, the Si 2p peak shifted to lower binding energy, and the Si 2p associated with the SiO2 layer also was shifted, indicating an internal field in the SiO2. The VO2 valence band maximum (VBM) was identified at 0.6 eV below the Fermi level (EF). This ultra thin VO2 exhibits the metal-insulator transition at a temperature higher than thicker films. As a comparison, a 100nm thick film of VO2 on Si showed a MIT at 60C. After the HfO2 deposition, the Si 2p substrate feature returned to the initial value indicating a return to flat band conditions. The UPS indicated the VBM of HfO2 at 4.0 eV below EF. This work is supported by the NSF (DMR-0805353).

  9. Impact of boron diffusion on oxynitrided gate oxides in 4H-SiC metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Cabello, M.; Soler, V.; Montserrat, J.; Rebollo, J.; Rafí, J. M.; Godignon, P.

    2017-07-01

    An alternative gate oxide configuration is proposed to enhance the SiO2/SiC interface quality, enabling high mobility 4H-SiC lateral metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxide is prepared by the combination of rapid thermal oxidation in N2O ambient, boron diffusion into SiO2, and plasma enhanced chemical vapor deposition of tetraethyl orthosilicate oxide. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurements on fabricated capacitors reveal a reduction of both interface trap and near interface oxide trap densities. The fabrication of MOSFETs with very high field-effect mobility (μfe) values, up to 160 cm2/V s, is enabled. Several channel orientations, with respect to the wafer flat {11 2 ¯ 0}, have been studied to check μfe values and isotropy. Higher μfe values are obtained for a channel orientation of 90°. Boron distribution is studied by secondary ion mass spectrometry (SIMS) and time of flight SIMS. We propose that the combination of boron and nitrogen induces changes in the structure of the gate oxide which are positive in terms of the SiO2/SiC interface quality.

  10. A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

    PubMed Central

    Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

    2016-01-01

    Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

  11. Investigation of the gate oxide leakage current of low temperature formed hafnium oxide films

    NASA Astrophysics Data System (ADS)

    Verrelli, E.; Tsoukalas, D.

    2013-03-01

    In this work, low temperature physically deposited hafnium oxide films are investigated in terms of their electrical properties through measurements and analysis of leakage currents in order to understand the defect's behavior in this dielectric material. Two extreme conditions will be presented and discussed: the first one concerns the use of a nearly trap-free hafnium oxide layer, while the second one concerns the use of a hafnium oxide film with a very large amount of electrically active traps. Particular emphasis is given to the detection and comparison of the shallow and deep traps that are responsible for the room temperature leakage of these films. It is shown that by modifying the amount of traps in the hafnium oxide layer, achieved by changing the deposition conditions, the trap's energy location is heavily influenced. The nearly trap-free sample exhibits Ohmic conduction at low fields (with activation energies in the range 16-33 meV for low temperatures and 0.13-0.14 eV for higher than ambient temperatures), Poole-Frenkel conduction at high fields (trap depth in the range 0.23-0.38 eV), while at low temperatures and high fields, the Fowler-Nordheim tunneling is identified (estimated barrier height of 1.9 eV). The charge-trap sample on the other hand exhibits Ohmic conduction at low fields (activation energies in the range 0.26-0.32 eV for higher than ambient temperatures), space charge limited current conduction at intermediate fields (exponent n = 3), while at high fields the Poole-Frenkel conduction appears (trap depth in the range 1.63-1.70 eV).

  12. Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

    NASA Astrophysics Data System (ADS)

    Li, Cong; Zhuang, Yi-Qi; Zhang, Li; Jin, Gang

    2014-01-01

    Based on the quasi-two-dimensional (2D) solution of Poisson's equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate (JLDMCSG) metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG (JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll-off of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional (3D) numerical device simulator ISE.

  13. Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying

    2008-12-01

    Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

  14. Solution-Processed Rare-Earth Oxide Thin Films for Alternative Gate Dielectric Application.

    PubMed

    Zhuang, Jiaqing; Sun, Qi-Jun; Zhou, Ye; Han, Su-Ting; Zhou, Li; Yan, Yan; Peng, Haiyan; Venkatesh, Shishir; Wu, Wei; Li, Robert K Y; Roy, V A L

    2016-11-16

    Previous investigations on rare-earth oxides (REOs) reveal their high possibility as dielectric films in electronic devices, while complicated physical methods impede their developments and applications. Herein, we report a facile route to fabricate 16 REOs thin insulating films through a general solution process and their applications in low-voltage thin-film transistors as dielectrics. The formation and properties of REOs thin films are analyzed by atomic force microscopy (AFM), X-ray diffraction (XRD), spectroscopic ellipsometry, water contact angle measurement, X-ray photoemission spectroscopy (XPS), and electrical characterizations, respectively. Ultrasmooth, amorphous, and hydrophilic REO films with thickness around 10 nm have been obtained through a combined spin-coating and postannealing method. The compositional analysis results reveal the formation of RE hydrocarbonates on the surface and silicates at the interface of REOs films annealed on Si substrate. The dielectric properties of REO films are investigated by characterizing capacitors with a Si/Ln2O3/Au (Ln = La, Gd, and Er) structure. The observed low leakage current densities and large areal capacitances indicate these REO films can be employed as alternative gate dielectrics in transistors. Thus, we have successfully fabricated a series of low-voltage organic thin-film transistors based on such sol-gel derived REO films to demonstrate their application in electronics. The optimization of REOs dielectrics in transistors through further surface modification has also been studied. The current study provides a simple solution process approach to fabricate varieties of REOs insulating films, and the results reveal their promising applications as alternative gate dielectrics in thin-film transistors.

  15. Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2017-05-01

    Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

  16. Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2017-01-01

    Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low-k). To supplement low-k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high-k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high-k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3.

  17. New Gate Dielectric Oxides for GaAs and Other Semiconductors*

    NASA Astrophysics Data System (ADS)

    Hong, M.

    2000-03-01

    It is well known that electrons move much faster in GaAs than in Si, and this attribute makes the GaAs-based metal oxide semiconductor field effect transistors (MOSFETs) very attractive for high-frequency, high-speed circuits applications. However, identifying a proper insulating oxide for GaAs has been a problem puzzling researchers over 35 years. Recently we discovered that the use of a mixed oxide dielectric Ga_2O_3(Gd_2O_3)^1 formed inversion and accumulation channels on GaAs surfaces, with a low interfacial density of states (D_it) of mid-10^10 cm-2eV-1. Subsequently, we have demonstrated the p- and n- inversion channel MOSFETs^2 and CMOS circuits^3. All oxides in this work were prepared by ultrahigh vacuum deposition from e-beam sources. The initial growth ( 10 Åof Ga_2O_3(Gd_2O_3) film on GaAs takes place from nucleating a thin epitaxial layer of pure Gd_2O_3. In fact, mono-domain, single crystalline Gd_2O3 films (ɛ =12) can be grown on GaAs (100) surface in the (110) Mn_2O3 structure, and that show leakage currents as low as 10-4 A/cm^2 at 10 MV/cm for a film only 25 Åthick^4. We have extended our studies to other rare earth oxides and other semiconductors. For example, low-D_it GaN MOS diodes and GaN MOSFETs operated at 400^circC were obtained. The GaN MOSFET has potential applications in high power switching and high temperature device operation. More remarkably, we have found recently that another rare earth oxide, Y_2O3 (ɛ = 18) showed excellent electrical properties as a gate dielectric for Si, to replace the current SiO_2, where the thickness is now approaching the quantum limit^5. *In collaboration with J. Kwo, A. R. Kortan, J. N. Baillargeon, J. P. Mannaerts, F. Ren, Y. C. Wang, T. S. Lay, H. Ng, R. Opila, K. L. Queeney, Y. J. Chabal, T. Boone, J. J. Krajewski, A. M. Sergent, J. M. Rosamilia, M. Passlack, D. W. Murphy, and A. Y. Cho. 1. M. Hong, et al, J. Vac. Sci. Technol. B14, 2297, (1996). 2. F. Ren et al, IEDM Technical Digest, p.943, (1996

  18. Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

    PubMed Central

    Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

    2017-01-01

    In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

  19. Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

    SciTech Connect

    Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin

    2015-05-15

    We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

  20. Effect of nitrogen incorporation into Al-based gate insulators in AlON/AlGaN/GaN metal-oxide-semiconductor structures

    NASA Astrophysics Data System (ADS)

    Asahara, Ryohei; Nozaki, Mikito; Yamada, Takahiro; Ito, Joyo; Nakazawa, Satoshi; Ishida, Masahiro; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2016-10-01

    The superior physical and electrical properties of aluminum oxynitride (AlON) gate dielectrics on AlGaN/GaN substrates in terms of thermal stability, reliability, and interface quality were demonstrated by direct AlON deposition and subsequent annealing. Nitrogen incorporation into alumina was proven to be beneficial both for suppressing intermixing at the insulator/AlGaN interface and reducing the number of electrical defects in Al2O3 films. Consequently, we achieved high-quality AlON/AlGaN/GaN metal-oxide-semiconductor capacitors with improved stability against charge injection and a reduced interface state density as low as 1.2 × 1011 cm-2 eV-1. The impact of nitrogen incorporation into the insulator will be discussed on the basis of experimental findings.

  1. Reliability Characterization of Digital Microcircuits - Investigation of an In-Process Oxide Reliability Screening Method

    DTIC Science & Technology

    1993-04-01

    Electrochem. Soc. vol.136, p. 14 7 4 (1989). 98. Ryden K. H., H. Norstrom, C. Nender and S. Berg, "Oxide Breakdown due to Charge Accumulation during Plasma...breakdown due to charge accumulation during plasma etching Author(s): Ryden , K.-H.; Norstrom, H.; Nender, C.; Berg, S. Author Affiliation: Inst. of...of charge accumulation during plasma etching Author(s): Ryden , K.-H.; Norstrom, H.; Nender, C.; Berg, S. Author Affiliation: Inst. of Microwave

  2. Correlations between structural and electrical properties of nitrided SiOx thin films used as power metal oxide semiconductor field effect transistor gate dielectric

    NASA Astrophysics Data System (ADS)

    Fazio, E.; Neri, F.; Camalleri, G. Curró M.; Calí, D.

    2008-11-01

    Correlations between the interface states and trap densities, in particular, the defect types that may be more or less strongly involved in power vertically diffused metal oxide semiconductor reliability performances, and the fine interface chemistry of the Ox-N-Siy bonds have been studied. The oxide preparation process is extracted from an STMicroelectronics proprietary standard for low voltage vertically diffused power metal oxide semiconductor field effect transistors with logic level gate driving. The oxynitride films were grown in N2O environment at temperatures equal to or higher than 900 °C and optionally subjected to a 1000 °C short annealing. Informations about the sample stoichiometry and the nitrogen bonding configurations were obtained by means of x-ray photoelectron spectroscopy. The results show that some peculiar linear and antilinear correlations exist between carrier traps across the oxide or at its interface and the amount of specific nitrogen bonding configurations. In particular, the role of the substitutional N(-SiO3)x bond as a marker of the electrical quality of Si/SiO2 interface is highlighted.

  3. Effect of top gate bias on photocurrent and negative bias illumination stress instability in dual gate amorphous indium-gallium-zinc oxide thin-film transistor

    SciTech Connect

    Lee, Eunji; Chowdhury, Md Delwar Hossain; Park, Min Sang; Jang, Jin

    2015-12-07

    We have studied the effect of top gate bias (V{sub TG}) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm{sup 2} intensity light with negative bottom gate bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the V{sub TG} from −15 to +15 V. By changing V{sub TG} from negative to positive, the Fermi level (E{sub F}) shifts toward conduction band edge (E{sub C}), which substantially controls the conversion of neutral vacancy to charged one (V{sub O} → V{sub O}{sup +}/V{sub O}{sup 2+} + e{sup −}/2e{sup −}), peroxide (O{sub 2}{sup 2−}) formation or conversion of ionized interstitial (O{sub i}{sup 2−}) to neutral interstitial (O{sub i}), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative bias illumination stress, the transfer curve shows −2.7 V shift at V{sub TG} = −15 V, which gradually decreases to −0.42 V shift at V{sub TG} = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (V{sub O}{sup +}/V{sub O}{sup 2+}/O{sub 2}{sup 2−}/O{sub i}) and/or hole trapping in the a-IGZO /interfaces.

  4. Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

    PubMed

    Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

    2016-04-20

    In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

  5. High-performance GaN metal-insulator-semiconductor ultraviolet photodetectors using gallium oxide as gate layer.

    PubMed

    Lee, Ming-Lun; Mue, T S; Huang, F W; Yang, J H; Sheu, J K

    2011-06-20

    In this study, gallium nitride (GaN)-based metal-insulator-semiconductor (MIS) ultraviolet (UV) photodetectors (PDs) with a gallium oxide (GaO(x)) gate layer formed by alternating current bias-assisted photoelectrochemical oxidation of n-GaN are presented. By introducing the GaO(x) gate layer to the GaN MIS UV PDs, the leakage current is reduced and a much larger UV-to-visible rejection ratio (R(UV/vis)) of spectral responsivity is achieved. In addition, a bias-dependent spectral response results in marked increase of the R(UV/vis) with bias voltage up to ~10(5). The bias-dependent responsivity suggests the possible existence of internal gain in of the GaN MIS PDs.

  6. Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

    NASA Astrophysics Data System (ADS)

    Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

    2011-05-01

    TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

  7. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    NASA Astrophysics Data System (ADS)

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-01

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiOx film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 1011 cm-2 eV-1 by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H2O molecules and facilitate dissociation of the molecules into H and OH-. The OH- ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H2O molecules. The ionization results in the electron stimulated dissociation of H2O molecules and the decreased interface trap density.

  8. Low-temperature formation of high-quality gate oxide by ultraviolet irradiation on spin-on-glass

    SciTech Connect

    Usuda, R.; Uchida, K.; Nozaki, S.

    2015-11-02

    Although a UV cure was found to effectively convert a perhydropolysilazane (PHPS) spin-on-glass film into a dense SiO{sub x} film at low temperature, the electrical characteristics were never reported in order to recommend the use of PHPS as a gate-oxide material that can be formed at low temperature. We have formed a high-quality gate oxide by UV irradiation on the PHPS film, and obtained an interface midgap trap density of 3.4 × 10{sup 11 }cm{sup −2} eV{sup −1} by the UV wet oxidation and UV post-metallization annealing (PMA), at a temperature as low as 160 °C. In contrast to the UV irradiation using short-wavelength UV light, which is well known to enhance oxidation by the production of the excited states of oxygen, the UV irradiation was carried out using longer-wavelength UV light from a metal halide lamp. The UV irradiation during the wet oxidation of the PHPS film generates electron-hole pairs. The electrons ionize the H{sub 2}O molecules and facilitate dissociation of the molecules into H and OH{sup −}. The OH{sup −} ions are highly reactive with Si and improve the stoichiometry of the oxide. The UV irradiation during the PMA excites the electrons from the accumulation layer, and the built-in electric field makes the electron injection into the oxide much easier. The electrons injected into the oxide recombine with the trapped holes, which have caused a large negative flat band voltage shift after the UV wet oxidation, and also ionize the H{sub 2}O molecules. The ionization results in the electron stimulated dissociation of H{sub 2}O molecules and the decreased interface trap density.

  9. Control of Subthreshold Characteristics of Narrow-Channel Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Transistor with Additional Side Gate Electrodes

    NASA Astrophysics Data System (ADS)

    Okuyama, Kiyoshi; Yoshikawa, Koji; Sunami, Hideo

    2007-04-01

    A silicon-on-insulator (SOI) n-type metal-oxide-semiconductor (MOS) transistor with additional side gate electrodes is fabricated and its subthreshold characteristics are discussed. Since its device structure provides independent biasing to gates, flexible device-characteristic control for the respective device is expected. The key fabrication process is the formation of transistor gates. Additional side gate electrodes are formed by reactive ion etching (RIE) with a SiO2-covered top gate as an etching mask. Subthreshold characteristics are improved by negative side-gate biasing. In addition, the side-gate voltage VSG required to decrease off-leakage current by one decade is around 100 mV. Since the sidewall oxide thickness is chosen to be 5 nm, which is the same as the top-oxide thickness, rather sensitive subthreshold-characteristic control compared with that of biasing through a thick buried-oxide layer is achieved in response to performance requirement. In the viewpoint of stand-by-power suppression, these provide a certain controllability to a circuit operation.

  10. Study of Strain Induction for Metal-Oxide-Semiconductor Field-Effect Transistors using Transparent Dummy Gates and Stress Liners

    NASA Astrophysics Data System (ADS)

    Kosemura, Daisuke; Takei, Munehisa; Nagata, Kohki; Akamatsu, Hiroaki; Kohno, Masayuki; Nishita, Tatsuo; Nakanishi, Toshio; Ogura, Atsushi

    2009-06-01

    Strain induction was studied on a sample that had a dummy gate tetraethyl orthosilicate-silicon dioxide (TEOS-SiO2) and SiN film by UV-Raman spectroscopy with high spatial and high wave-number resolution. The UV laser penetrated through the dummy gate that was transparent to UV light, which enabled us to evaluate strain in the channel of the metal-oxide-semiconductor field-effect transistor (MOSFET) model. Furthermore, we compared stress profiles obtained by finite element (FE) calculations with those obtained by UV-Raman measurements. There was a difference between the stress profiles in the line-and-space pattern sample and in the dummy-gate sample; large compressive (tensile) strains were concentrated at the channel edges in the dummy-gate sample with the compressive (tensile) stress liner, although both tensile and compressive strains existed at the channel edge in the line-and-space pattern sample. The results from UV-Raman spectroscopy were consistent with those obtained by the FE calculation.

  11. An oxidation-last annealing for enhancing the reliability of indium-gallium-zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Li, Jiapeng; Lu, Lei; Feng, Zhuoqun; Kwok, Hoi Sing; Wong, Man

    2017-04-01

    The dependence of device reliability against a variety of stress conditions on the annealing atmosphere was studied using a single metal-oxide thin-film transistor with thermally induced source/drain regions. A cyclical switch between an oxidizing and a non-oxidizing atmosphere induced a regular change in the stress-induced shift of the turn-on voltage, with the magnitude of the shift being consistently smaller after annealing in an oxidizing atmosphere. The observed behavior is discussed in terms of the dependence of the population of oxygen vacancies on the annealing atmosphere, and it is recommended the last of the sequence of thermal processes applied to a metal-oxide thin-film transistor be executed in an oxidizing atmosphere.

  12. Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

    SciTech Connect

    Lu, Cimang Lee, Choong Hyun; Zhang, Wenfeng; Nishimura, Tomonori; Nagashio, Kosuke; Toriumi, Akira

    2014-11-07

    A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scaling to 0.5 nm is also demonstrated based on these understandings.

  13. MIS and MFIS Devices: DyScO3 as a gate-oxide and buffer-layer

    NASA Astrophysics Data System (ADS)

    Melgarejo, R.; Karan, N. K.; Saavedra-Arias, J.; Pradhan, D. K.; Thomas, R.; Katiyar, R. S.

    2008-03-01

    Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure is of importance in nonvolatile memories, as insulating buffer layer that prevents interdiffusion between the ferroelectric (FE) and the Si substrate. However, insulating layer has some disadvantages viz. generation of depolarization field in FE film and increase of operation voltage. To overcome this, it is important to find a FE with low ɛr (compared to normal FE) and an insulating buffer layer with high ɛr (compared to ɛr = 3.9 of SiO2). High-k materials viz. LaAlO3, SiN, HfO2, HfAlO etc. have been studied as buffer layers in the MFIS structures and as gate-oxide in metal-insulator-silicon (MIS). Recently, a novel gate dielectric material, DyScO3 was considered and studies indicate that crystallization temperature significantly increased and the film on Si remained amorphous even at 1000 C annealing. Considering the requirements on crystallization temperature, ɛr, electrical stability for high-k buffer layers, DyScO3 seems to be very promising for future MFIS device applications. Therefore, the evaluations of MOCVD grown DyScO3 as gate-oxide for MIS and the buffer layers for Bi3.25La0.75Ti3O12 based MFIS structures are presented.

  14. Preoptic neuronal nitric oxide synthase induction by testosterone is consistent with a role in gating male copulatory behavior

    PubMed Central

    Sanderson, Nicholas S. R.; Le, Brandon; Zhou, Zifei; Crews, David

    2008-01-01

    Copulatory behaviors are generally dependent on testicular androgens in male vertebrates, being eliminated by castration and re-instated by testosterone administration. It is postulated that a critical factor in this hormonal gating is up-regulation of neuronal nitric oxide synthase (nNOS) in the preoptic area, and consequent enhanced nitric oxide synthesis in response to stimuli associated with a receptive female. Previous studies have suggested that nNOS protein is more abundant in behaviorally relevant preoptic regions of testosterone-exposed animals than in hormone-deprived controls. This study sought to elucidate the molecular events underlying this apparent up-regulation by examining preoptic nNOS mRNA abundance at several time points following testosterone administration in a castration and replacement paradigm. Castrated male whiptails (Cnemidophorus inornatus) were implanted with testosterone, and at four time points over the subsequent 18 days their sexual behavior was tested. A rostral periventricular area previously implicated in hormonal gating of male-typical copulatory behavior was then excised by laser microdissection, and nNOS transcript abundance was assessed by quantitative PCR. As neither this technique nor nNOS mRNA measurements have previously been performed in this area of the brain, expression was concommitantly assayed on adjacent sections by in situ hybridization or NADPH diaphorase histochemistry. Results are consistent with transcriptional up-regulation of nNOS by testosterone and a central role for the enzyme in mediating hormonal gating of copulatory behavior. PMID:18184320

  15. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    SciTech Connect

    Miranda, Andre

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  16. Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

    NASA Astrophysics Data System (ADS)

    Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

    2016-12-01

    The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP.

  17. Excitatory Post-Synaptic Potential Mimicked in Indium-Zinc-Oxide Synaptic Transistors Gated by Methyl Cellulose Solid Electrolyte

    PubMed Central

    Guo, Liqiang; Wen, Juan; Ding, Jianning; Wan, Changjin; Cheng, Guanggui

    2016-01-01

    The excitatory postsynaptic potential (EPSP) of biological synapses is mimicked in indium-zinc-oxide synaptic transistors gated by methyl cellulose solid electrolyte. These synaptic transistors show excellent electrical performance at an operating voltage of 0.8 V, Ion/off ratio of 2.5 × 106, and mobility of 38.4 cm2/Vs. After this device is connected to a resistance of 4 MΩ in series, it exhibits excellent characteristics as an inverter. A threshold potential of 0.3 V is achieved by changing the gate pulse amplitude, width, or number, which is analogous to biological EPSP. PMID:27924838

  18. Operational stability of solution based zinc tin oxide/SiO2 thin film transistors under gate bias stress

    NASA Astrophysics Data System (ADS)

    Kiazadeh, Asal; Salgueiro, Daniela; Branquinho, Rita; Pinto, Joana; Gomes, Henrique L.; Barquinha, Pedro; Martins, Rodrigo; Fortunato, Elvira

    2015-06-01

    In this study, we report solution-processed amorphous zinc tin oxide transistors exhibiting high operational stability under positive gate bias stress, translated by a recoverable threshold voltage shift of about 20% of total applied stress voltage. Under vacuum condition, the threshold voltage shift saturates showing that the gate-bias stress is limited by trap exhaustion or balance between trap filling and emptying mechanism. In ambient atmosphere, the threshold voltage shift no longer saturates, stability is degraded and the recovering process is impeded. We suggest that the trapping time during the stress and detrapping time in recovering are affected by oxygen adsorption/desorption processes. The time constants extracted from stretched exponential fitting curves are ≈106 s and 105 s in vacuum and air, respectively.

  19. A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

    SciTech Connect

    Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu

    2014-11-07

    A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulation results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.

  20. Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

    NASA Astrophysics Data System (ADS)

    Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

    2016-04-01

    Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

  1. Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

    NASA Astrophysics Data System (ADS)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2013-10-01

    In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

  2. Reliability of ^1^H NMR analysis for assessment of lipid oxidation at frying temperatures

    USDA-ARS?s Scientific Manuscript database

    The reliability of a method using ^1^H NMR analysis for assessment of oil oxidation at a frying temperature was examined. During heating and frying at 180 °C, changes of soybean oil signals in the ^1^H NMR spectrum including olefinic (5.16-5.30 ppm), bisallylic (2.70-2.88 ppm), and allylic (1.94-2.1...

  3. Simple and reliable method for determination of oxygen content in high- Tc copper oxides

    NASA Astrophysics Data System (ADS)

    Maeno, Yoshiteru; Teraoka, Hideki; Matsukuma, Kuniko; Yoshida, Koji; Sugiyama, Kimihiko; Nakamura, Fumihiko; Fujita, Toshizo

    1991-12-01

    We present the details of a simple and reliable iodine-titration method suited for high- Tc copper oxides, in which the use of a solution of ammonium acetate and acetic acid as a buffer agent substantially improves the operation. The results applied to La 2- xM xCuO 4- δ (M = Ba, Sr and Ca) are presented.

  4. Performance enhancement of multiple-gate ZnO metal-oxide-semiconductor field-effect transistors fabricated using self-aligned and laser interference photolithography techniques

    PubMed Central

    2014-01-01

    The simple self-aligned photolithography technique and laser interference photolithography technique were proposed and utilized to fabricate multiple-gate ZnO metal-oxide-semiconductor field-effect transistors (MOSFETs). Since the multiple-gate structure could improve the electrical field distribution along the ZnO channel, the performance of the ZnO MOSFETs could be enhanced. The performance of the multiple-gate ZnO MOSFETs was better than that of the conventional single-gate ZnO MOSFETs. The higher the drain-source saturation current (12.41 mA/mm), the higher the transconductance (5.35 mS/mm) and the lower the anomalous off-current (5.7 μA/mm) for the multiple-gate ZnO MOSFETs were obtained. PMID:24948884

  5. Effects of Rare-Earth Oxides on the Reliability of X7R Dielectrics

    NASA Astrophysics Data System (ADS)

    Sakabe, Yukio; Hamaji, Yukio; Sano, Harunobu; Wada, Nobuyuki

    2002-09-01

    The effects of rare-earth oxides, e.g., La, Nd, Sm, Dy and Yb, on the reliability of multilayer capacitors (MLCs) with X7R dielectrics and Ni electrodes were investigated. Microstructures of the dielectrics were analyzed by transmission electron microscopy (TEM) and electron probe microanalysis (EPMA) in order to characterize the rare-earth ions. Incorporation of rare-earth ions to BaTiO3 ceramics depended on their ionic radius, resulting in different microstructures and electric performances of dielectrics. Dy ions provided BaTiO3 ceramics with ideal X7R characteristics and high reliability. The mechanism governing leakage current was discussed in terms of the voltage dependence of leakage current. Electric properties and related reliability of the capacitors were attributed to solubility, distribution of rare-earth oxides and their occupation site in BaTiO3.

  6. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    PubMed

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  7. Rat Aquaporin-5 Is pH-Gated Induced by Phosphorylation and Is Implicated in Oxidative Stress

    PubMed Central

    Rodrigues, Claudia; Mósca, Andreia Filipa; Martins, Ana Paula; Nobre, Tatiana; Prista, Catarina; Antunes, Fernando; Cipak Gasparovic, Ana; Soveral, Graça

    2016-01-01

    Aquaporin-5 (AQP5) is a membrane water channel widely distributed in human tissues that was found up-regulated in different tumors and considered implicated in carcinogenesis in different organs and systems. Despite its wide distribution pattern and physiological importance, AQP5 short-term regulation was not reported and mechanisms underlying its involvement in cancer are not well defined. In this work, we expressed rat AQP5 in yeast and investigated mechanisms of gating, as well as AQP5’s ability to facilitate H2O2 plasma membrane diffusion. We found that AQP5 can be gated by extracellular pH in a phosphorylation-dependent manner, with higher activity at physiological pH 7.4. Moreover, similar to other mammalian AQPs, AQP5 is able to increase extracellular H2O2 influx and to affect oxidative cell response with dual effects: whereas in acute oxidative stress conditions AQP5 induces an initial higher sensitivity, in chronic stress AQP5 expressing cells show improved cell survival and resistance. Our findings support the involvement of AQP5 in oxidative stress and suggest AQP5 modulation by phosphorylation as a novel tool for therapeutics. PMID:27983600

  8. Reliability and manufacturability of 25G VCSELs with oxide apertures formed by in-situ monitoring

    NASA Astrophysics Data System (ADS)

    Pao, James J.; Wu, Ta-Chung; Kyi, Wilson; Riaziat, Majid; Lott, James A.

    2017-02-01

    Reliability and characterization of 850 nm 25 Gbit/s (25G) InGaAs/AlGaAs vertical-cavity surface-emitting lasers (VCSELs) with oxide apertures, fabricated at OEpic Semiconductors, Inc., are presented. These 25G VCSELs have demonstrated a threshold current of <1.0 mA and a slope efficiency of 0.45 W/A. An optical output power of >5.0 mW and rise and fall times of 18 and 25 ps, respectively, have been achieved. The non-hermetically sealed VCSELs were stress tested at 85o C under bias for up to 1200 hours to achieve accelerated failure modes to predict atmospheric-ambient reliability for applications such as board-to-board data communications. VCSEL failures are likely due to a combination of factors including the propagation of dislocation defects from the oxide layers, the incorporation of ambient oxygen into and near the active region, as well as layer cracking and separation near the active regions due to stress from the mechanical strain induced by the oxide layers. Our high-speed VCSELs use 0.5λ optical cavity lengths and oxide layers that are as close as 126 nm to the active region. OEpic's design uses two or more oxide apertures to increase current confinement, allowing for greater overall current density. The proximity of the oxide layers to the active region, coupled with the increased heating of the active region due to a higher current density, likely results in a non-radiative recombination-based lasing failure. An increase of the optical cavity length, a decrease of the selective oxidation rate, and a reduction of the oxide layer thickness are measures that are expected to improve the VCSEL reliability.

  9. New Analytical Model for Short-Channel Fully Depleted Dual-Material-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Te-Kuang Chiang,

    2010-07-01

    Using the exact solution of the two-dimensional Poisson equation, a new analytical model comprising two-dimensional potential and threshold voltage for short-channel fully depleted dual-material-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. The model shows that the minimum acceptable channel length can be sustained while repressing the short-channel effects if a thin gate oxide and a thin silicon body are employed in the device. Moreover, by increasing the ratio of the screen gate length to control gate length, the threshold voltage roll-off can be more effectively reduced. The model is verified by the close agreement of its results with those of a numerical simulation using the device simulator MEDICI. The model not only offers an insight into the device physics but is also an efficient model for circuit simulation.

  10. Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

    NASA Astrophysics Data System (ADS)

    Liuan, Li; Jiaqi, Zhang; Yang, Liu; Jin-Ping, Ao

    2016-03-01

    In this paper, TiN/AlOx gated AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 °C with the contact resistance approximately 1.6 Ω·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlOx gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AlGaN/GaN MOS-HFETs. Project supported by the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260).

  11. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    SciTech Connect

    Chao, Jin Yu; Zhu, Li Qiang Xiao, Hui; Yuan, Zhi Guo

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  12. Leakage current conduction behaviors of 0.65 nm equivalent-oxide-thickness HfZrLaO gate dielectrics

    NASA Astrophysics Data System (ADS)

    Lin, K. C.; Chen, J. Y.; Hsu, H. W.; Chen, H. W.; Liu, C. H.

    2012-11-01

    The high κ gate dielectrics of MOS capacitors with LaO/HfZrO stacked (denoted as HfZrLaO) have been fabricated by atomic-layer-deposited (ALD). In this study, the data show that the gate leakage current density (Jg) is about 1.9 A/cm2, and the equivalent oxide thickness (EOT) is about 0.65 nm with quantum effects taken into account. The analysis of the leakage current conduction characteristics is based on the temperature dependence of the leakage current from 300 to 475 K. The dominant current conduction behaviors are Schottky emission in the region of low electric fields (<1 MV/cm) and high temperatures (450-475 K), Poole-Frankel (P-F) emission in the region of medium electric fields (2.3-3.83 MV/cm) and low temperatures (300-350 K), and Fowler-Nordheim (F-N) tunneling in the region of high electric fields (>4 MV/cm) and low temperatures (<300 K). The electron barrier height (ΦB) at gate interface and the trap energy level (Φt) in the dielectric are extracted to be 1.07 and 1.38 eV, respectively.

  13. Improvement of Ron under AC Operation of Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)

    NASA Astrophysics Data System (ADS)

    Takaya, Hidefumi; Miyagi, Kyosuke; Hamada, Kimimori

    A MOSFET structure called a FITMOS (Floating Island and Thick Bottom Oxide Trench Gate MOSFET) that exhibits a record low loss in the 60V breakdown voltage (BVdss) range has been successfully developed. The following improvements achieved progress in the characteristic of FITMOS. (1) At the time of AC operation, the charges in the floating P islands that are a feature of the floating type device become greater, thereby increasing the on-resistance (Ron) due to the JFET effect. This issue was solved by forming passive hole gates in the end walls of the trenches. The Ron under AC operation is equivalent to the Ron under DC operation. This paper clarified the influence of the passive hole gate diffusion layer shape and the impurity concentration to BVdss and AC operation. (2) The trade-off of BVdss and Ron has been improved by making the floating island into an elliptical form. A BVdss of 83V and a specific on-resistance (RonA) of 36mΩmm2 were obtained.

  14. A high-mobility electronic system at an electrolyte-gated oxide surface

    NASA Astrophysics Data System (ADS)

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-03-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm-2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized.

  15. A high-mobility electronic system at an electrolyte-gated oxide surface

    PubMed Central

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor A.; Stanwyck, Sam W.; Williams, James R.; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-01-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities at a surface. Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the sample, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the electron system. Accordingly, electrolyte gating is well suited to studies of superconductivity and other phenomena robust to disorder, but of limited use when reactions or disorder must be avoided. Here we demonstrate that these limitations can be overcome by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride. We illustrate our technique with electrolyte-gated strontium titanate, whose mobility when protected with boron nitride improves more than 10-fold while achieving carrier densities nearing 1014 cm−2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized. PMID:25762485

  16. Sensitive and reliable ascorbic acid sensing by lanthanum oxide/reduced graphene oxide nanocomposite.

    PubMed

    Mogha, Navin Kumar; Sahu, Vikrant; Sharma, Meenakshi; Sharma, Raj Kishore; Masram, Dhanraj T

    2014-10-01

    A simple strategy for the detection and estimation of ascorbic acid (AA), using lanthanum oxide-reduced graphene oxide nanocomposite (LO/RGO) on indium tin oxide (ITO) substrate, is reported. LO/RGO displays high catalytic activity toward the oxidation of AA, and the synergism between lanthanum oxide and reduced graphene oxide was attributed to the successful and efficient detection. Detection mechanism and sensing efficacy of LO/RGO nanocomposite are investigated by electrochemical techniques. Chronoamperometric results under optimal conditions show a linear response range from 14 to 100 μM for AA detection. Commercially available vitamin C tablets were also analyzed using the proposed LO/RGO sensor, and the remarkable recovery percentage (97.64-99.7) shows the potential application in AA detection.

  17. Enzymatic AND logic gate with sigmoid response induced by photochemically controlled oxidation of the output.

    PubMed

    Privman, Vladimir; Fratto, Brian E; Zavalov, Oleksandr; Halámek, Jan; Katz, Evgeny

    2013-06-27

    We report a study of a system which involves an enzymatic cascade realizing an AND logic gate, with an added photochemical processing of the output, allowing the gate's response to be made sigmoid in both inputs. New functional forms are developed for quantifying the kinetics of such systems, specifically designed to model their response in terms of signal and information processing. These theoretical expressions are tested for the studied system, which also allows us to consider aspects of biochemical information processing such as noise transmission properties and control of timing of the chemical and physical steps.

  18. Effects of gate stack structural and process defectivity on high-k dielectric dependence of NBTI reliability in 32 nm technology node PMOSFETs.

    PubMed

    Hussin, H; Soin, N; Bukhori, M F; Hatta, S Wan Muhamad; Wahab, Y Abdul

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E' center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

  19. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    PubMed Central

    Hussin, H.; Soin, N.; Bukhori, M. F.; Wan Muhamad Hatta, S.; Abdul Wahab, Y.

    2014-01-01

    We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated. PMID:25221784

  20. Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

    PubMed

    Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

    2017-06-14

    We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al2O3), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al2O3-deposited KPI film. After the surface treatment by ODPA/α-Al2O3, the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C10), was increased. Ph-BTBT-C10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm(2) V(-1) s(-1) to 1.26 ± 0.06 cm(2) V(-1) s(-1), after the surface treatment. The surface treatment of α-Al2O3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO2 gate insulators.

  1. An easy and reliable automated method to estimate oxidative stress in the clinical setting.

    PubMed

    Vassalle, Cristina

    2008-01-01

    During the last few years, reliable and simple tests have been proposed to estimate oxidative stress in vivo. Many of them can be easily adapted to automated analyzers, permitting the simultaneous processing of a large number of samples in a greatly reduced time, avoiding manual sample and reagent handling, and reducing variability sources. In this chapter, description of protocols for the estimation of reactive oxygen metabolites and the antioxidant capacity (respectively the d-ROMs and OXY Adsorbent Test, Diacron, Grosseto, Italy) by using the clinical chemistry analyzer SYNCHRON, CX 9 PRO (Beckman Coulter, Brea, CA, USA) is reported as an example of such an automated procedure that can be applied in the clinical setting. Furthermore, a calculation to compute a global oxidative stress index (Oxidative-INDEX), reflecting both oxidative and antioxidant counterparts, and, therefore, a potentially more powerful parameter, is also described.

  2. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

    NASA Astrophysics Data System (ADS)

    Huoxi, Xu; Jingping, Xu

    2016-06-01

    LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV-1 cm-2), gate leakage property (3.6 × 10-3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials. Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

  3. Simulation of quantum dot floating gate MOSFET memory performance using various high-k material as tunnel oxide

    NASA Astrophysics Data System (ADS)

    Aji, Adha Sukma; Darma, Yudi

    2012-06-01

    In this paper, performance of quantum dot floating gate MOSFET memory is simulated by replacing the SiO2 tunnel oxide with high-Κ material. There are three high-k material simulated in this paper, HfO2, ZrO2, and Y2O3. As we know that high-Κ material is used nowadays to reduce leakage current, so this paper demonstrates the application of high-Κ material to reduce leakage current in non-volatile memory quantum dot based floating gate MOSFET. Simulation results of this paper show the leakage current can be suppressed by using high-Κ material as tunnel oxide up to 10 times. Furthermore, this paper also shows that the memory performance can be properly sustained. The writing and erasing time are depend on tunneling current probability which calculated using transfer matrix method. The writing time and erasing time for HfO2 and ZrO2 are 150 nanosecond and 15 nanosecond.

  4. Voltage-gated calcium channel currents in human coronary myocytes. Regulation by cyclic GMP and nitric oxide.

    PubMed Central

    Quignard, J F; Frapier, J M; Harricane, M C; Albat, B; Nargeot, J; Richard, S

    1997-01-01

    Voltage-gated Ca2+ channels contribute to the maintenance of contractile tone in vascular myocytes and are potential targets for vasodilating agents. There is no information available about their nature and regulation in human coronary arteries. We used the whole-cell voltage-clamp technique to characterize Ca2+-channel currents immediately after enzymatic dissociation and after primary culture of coronary myocytes taken from heart transplant patients. We recorded a dihydropyridine-sensitive L-type current in both freshly isolated and primary cultured cells. A T-type current was recorded only in culture. The L- (but not the T-) type current was inhibited by permeable analogues of cGMP in a dose-dependent manner. This effect was mimicked by the nitric oxide-generating agents S-nitroso-N-acetylpenicillamine (SNAP) and 3-morpholinosydnonimine which increased intracellular cGMP. Methylene blue, known to inhibit guanylate cyclase, antagonized the effect of SNAP. Inhibitions by SNAP and cGMP were not additive and seemed to occur through a common pathway. We conclude that (a) L-type Ca2+ channels are the major pathway for voltage-gated Ca2+ entry in human coronary myocytes; (b) their inhibition by agents stimulating nitric oxide and/or intracellular cGMP production is expected to contribute to vasorelaxation and may be involved in the therapeutic effect of nitrovasodilators; and (c) the expression of T-type Ca2+ channels in culture may be triggered by cell proliferation. PMID:9005986

  5. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    SciTech Connect

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji Shimura, Takayoshi; Watanabe, Heiji; Ogawa, Shingo; Yoshigoe, Akitaka; Teraoka, Yuden

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  6. Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone-Water-Last Treatment

    NASA Astrophysics Data System (ADS)

    Oshiyama, Itaru; Tai, Kaori; Hirano, Tomoyuki; Yamaguchi, Shinpei; Tanaka, Kazuaki; Hagimoto, Yoshiya; Uemura, Takayuki; Ando, Takashi; Watanabe, Koji; Yamamoto, Ryo; Kanda, Saori; Wang, Junli; Tateshita, Yasushi; Wakabayashi, Hitoshi; Tagawa, Yukio; Tsukamoto, Masanori; Iwamoto, Hayato; Saito, Masaki; Oshima, Masaharu; Toyoda, Satoshi; Nagashima, Naoki; Kadomura, Shingo

    2008-04-01

    In this paper, we demonstrate a wet treatment for the HfSix/HfO2 gate stack of n-type metal oxide semiconductor field effect transistor (nMOSFET) fabricated by a gate-last process in order to scale down the electrical thickness at inversion state Tinv value and reduce the gate leakage Jg. As a result, we succeeded in scaling down Tinv to 1.41 nm without mobility or Jg degradation by ozone-water-last treatment. We found that a high-density interfacial layer (IFL) is formed owing to the ozone-water-last treatment, and Hf diffusion to the IFL is suppressed, which was analyzed by high-resolution angle-resolved spectroscopy.

  7. A high-mobility electronic system at an electrolyte-gated oxide surface

    NASA Astrophysics Data System (ADS)

    Gallagher, Patrick; Lee, Menyoung; Petach, Trevor; Stanwyck, Sam; Williams, James; Watanabe, Kenji; Taniguchi, Takashi; Goldhaber-Gordon, David

    2015-03-01

    Electrolyte gating is a powerful technique for accumulating large carrier densities in surface two-dimensional electron systems (2DES). Yet this approach suffers from significant sources of disorder: electrochemical reactions can damage or alter the surface of interest, and the ions of the electrolyte and various dissolved contaminants sit Angstroms from the 2DES. In this talk, we demonstrate that this disorder can be minimized by protecting the sample with a chemically inert, atomically smooth sheet of hexagonal boron nitride (BN). We illustrate our technique with electrolyte-gated strontium titanate, whose mobility improves more than tenfold when protected with BN. We find this improvement even for our thinnest BN, of measured thickness 6 Angstrom, with which we can accumulate electron densities nearing 1014 cm-2. Our technique is portable to other materials, and should enable future studies where high carrier density modulation is required but electrochemical reactions and surface disorder must be minimized.

  8. High sensitivity carbon monoxide sensors made by zinc oxide modified gated GaN/AlGaN high electron mobility transistors under room temperature

    NASA Astrophysics Data System (ADS)

    Hung, S. C.; Chen, C. W.; Shieh, C. Y.; Chi, G. C.; Fan, R.; Pearton, S. J.

    2011-05-01

    AlGaN/GaN high electron mobility transistors (HEMTs) with zinc oxide (ZnO) nanowires modified gate exhibit significant changes in channel conductance upon expose to different concentration of carbon monoxide (CO) at room temperature. The ZnO nanowires, grown by chemical vapor deposition (CVD) with perfect crystal quality will attach CO molecules and release electrons, which will lead to a change in surface charge in the gate region of the HEMTs, inducing a higher positive charge on the AlGaN surface, and increasing the piezoinduced charge density in the HEMTs channel. These electrons create an image positive charge on the gate region for the required neutrality, thus increasing the drain current of the HEMTs. The HEMTs source-drain current was highly dependent on the CO concentration. The limit of detection achieved was 400 ppm in the open cavity with continuous gas flow using a 50×50 μm2 gate sensing area.

  9. Ultraviolet-assisted oxidation and nitridation of hafnium and hafnium aluminum alloys as potential gate dielectrics for metal oxide semiconductor applications

    NASA Astrophysics Data System (ADS)

    Essary, Chad Robert

    The continued miniaturization of silicon-based complimentary metal oxide semiconductor (CMOS) devices is pushing the limits of the silicon dioxide (SiO2) gate dielectric. As the channel widths are decreased to increase packing densities and functionality of new chips, proportional vertical scaling of the dielectric must be maintained to keep constant capacitances. Silicon dioxide is approaching its fundamental limit in which it can be used as the gate dielectric due to high leakage currents resulting from direct tunneling through the layer. In order for the continued use of current CMOS gate design, an alternative material with a higher dielectric constant must be found. Several materials have been proposed but are still not providing the electrical characteristics favorable for use in the devices due to problems with excessive leakage and hysteresis resulting from the quality of the film and oxygen defects. The goal of this study is to create higher quality films at lower processing temperatures with low leakage and less hysteresis than has been achieved with hafnium oxide films. This study first examines the formation of the interfacial layer in pulsed laser deposited hafnium oxide films to understand the kinetics behind its formation. The second section focuses on the oxidation of pulsed laser deposited (PLD) hafnium metal thin films using ultraviolet (UV) assisted post-deposition annealing. Another set of samples was deposited in an ammonia atmosphere in order to incorporate nitrogen into the films. Comparisons of microstructure and stoichiometry of oxidized hafnium and oxy-nitride films were made using x-ray photospectroscopy, variable angle spectroscopic ellipsometry, glancing angle x-ray spectroscopy, x-ray reflectivity, and atomic force microscopy. Analysis of the interface between the films and the silicon substrate was carried out using x-ray reflectivity. The electrical characteristics of the films were characterized using capacitance-voltage and current

  10. Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

    SciTech Connect

    Jo, Kwang-Won; Cho, Won-Ju

    2014-11-24

    In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔV{sub ON}) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

  11. Surface modification of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors.

    PubMed

    Jang, Kwang-Suk; Wee, Duyoung; Kim, Yun Ho; Kim, Jinsoo; Ahn, Taek; Ka, Jae-Won; Yi, Mi Hye

    2013-06-11

    We report a simple approach to modify the surface of a polyimide gate insulator with an yttrium oxide interlayer for aqueous-solution-processed ZnO thin-film transistors. It is expected that the yttrium oxide interlayer will provide a surface that is more chemically compatible with the ZnO semiconductor than is bare polyimde. The field-effect mobility and the on/off current ratio of the ZnO TFT with the YOx/polyimide gate insulator were 0.456 cm(2)/V·s and 2.12 × 10(6), respectively, whereas the ZnO TFT with the polyimide gate insulator was inactive.

  12. High K Oxide Insulated Gate Group III Nitride-Based FETs

    DTIC Science & Technology

    2014-03-21

    AND ADDRESS(ES) Kansas State University 2 Fairchild Hall Manhattan , KS 66506-1103 3. DATES COVERED (From - To) 04/05/2009-03/20/2014 5a. CONTRACT...NUMBER 5b. GRANT NUMBER N00014-09-1-1160 5c. PROGRAM ELEMENT NUMBER 5d. PROJECT NUMBER 09PRE09471-00 5e. TASK NUMBER 5f. WORK UNIT NUMBER 9...results indicate the promising potential of incorporation gate dielectric in future GaN devices. This project supported two students who completed

  13. High performance trench MOS barrier Schottky diode with high-k gate oxide

    NASA Astrophysics Data System (ADS)

    Zhai, Dong-Yuan; Zhu, Jun; Zhao, Yi; Cai, Yin-Fei; Shi, Yi; Zheng, You-Liao

    2015-07-01

    A novel trench MOS barrier Schottky diode (TMBS) device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS. Project supported by the National Basic Research Program of China (Grant No. 2011CBA00607), the National Natural Science Foundation of China (Grant Nos. 61106089 and 61376097), and the Zhejiang Provincial Natural Science Foundation of China (Grant No. LR14F040001).

  14. Liquid-Gated High Mobility and Quantum Oscillation of the Two-Dimensional Electron Gas at an Oxide Interface.

    PubMed

    Zeng, Shengwei; Lü, Weiming; Huang, Zhen; Liu, Zhiqi; Han, Kun; Gopinadhan, Kalon; Li, Changjian; Guo, Rui; Zhou, Wenxiong; Ma, Haijiao Harsan; Jian, Linke; Venkatesan, Thirumalai; Ariando

    2016-04-26

    Electric field effect in electronic double layer transistor (EDLT) configuration with ionic liquids as the dielectric materials is a powerful means of exploring various properties in different materials. Here, we demonstrate the modulation of electrical transport properties and extremely high mobility of two-dimensional electron gas at LaAlO3/SrTiO3 (LAO/STO) interface through ionic liquid-assisted electric field effect. With a change of the gate voltages, the depletion of charge carrier and the resultant enhancement of electron mobility up to 19 380 cm(2)/(V s) are realized, leading to quantum oscillations of the conductivity at the LAO/STO interface. The present results suggest that high-mobility oxide interfaces, which exhibit quantum phenomena, could be obtained by ionic liquid-assisted field effect.

  15. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    SciTech Connect

    Zhu, Li Qiang Chao, Jin Yu; Xiao, Hui

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  16. Recovery from ultraviolet-induced threshold voltage shift in indium gallium zinc oxide thin film transistors by positive gate bias

    SciTech Connect

    Liu, P.; Chen, T. P.; Li, X. D.; Wong, J. I.; Liu, Z.; Liu, Y.; Leong, K. C.

    2013-11-11

    The effect of short-duration ultraviolet (UV) exposure on the threshold voltage (V{sub th}) of amorphous indium gallium zinc oxide thin film transistors (TFTs) and its recovery characteristics were investigated. The V{sub th} exhibited a significant negative shift after UV exposure. The V{sub th} instability caused by UV illumination is attributed to the positive charge trapping in the dielectric layer and/or at the channel/dielectric interface. The illuminated devices showed a slow recovery in threshold voltage without external bias. However, an instant recovery can be achieved by the application of positive gate pulses, which is due to the elimination of the positive trapped charges as a result of the presence of a large amount of field-induced electrons in the interface region.

  17. Aqueous combustion synthesis of aluminum oxide thin films and application as gate dielectric in GZTO solution-based TFTs.

    PubMed

    Branquinho, Rita; Salgueiro, Daniela; Santos, Lídia; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2014-11-26

    Solution processing has been recently considered as an option when trying to reduce the costs associated with deposition under vacuum. In this context, most of the research efforts have been centered in the development of the semiconductors processes nevertheless the development of the most suitable dielectrics for oxide based transistors is as relevant as the semiconductor layer itself. In this work we explore the solution combustion synthesis and report on a completely new and green route for the preparation of amorphous aluminum oxide thin films; introducing water as solvent. Optimized dielectric layers were obtained for a water based precursor solution with 0.1 M concentration and demonstrated high capacitance, 625 nF cm(-2) at 10 kHz, and a permittivity of 7.1. These thin films were successfully applied as gate dielectric in solution processed gallium-zinc-tin oxide (GZTO) thin film transistors (TFTs) yielding good electrical performance such as subthreshold slope of about 0.3 V dec(-1) and mobility above 1.3 cm2 V(-1) s(-1).

  18. Band offsets of high K gate oxides on III-V semiconductors

    NASA Astrophysics Data System (ADS)

    Robertson, J.; Falabretti, B.

    2006-07-01

    III-V semiconductors have high mobility and will be used in field effect transistors with the appropriate gate dielectric. The dielectrics must have band offsets over 1eV to inhibit leakage. The band offsets of various gate dielectrics including HfO2, Al2O3, Gd2O3, Si3N4, and SiO2 on III-V semiconductors such as GaAs, InAs, GaSb, and GaN have been calculated using the method of charge neutrality levels. Generally, the conduction band offsets are found to be over 1eV, so they should inhibit leakage for these dielectrics. On the other hand, SrTiO3 has minimal conduction band offset. The valence band offsets are also reasonably large, except for Si nitride on GaN and Sc2O3 on GaN which are 0.6-0.8eV. There is reasonable agreement with experiment where it exists, although the GaAs :SrTiO3 case is even worse in experiment.

  19. Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

    SciTech Connect

    Esro, M.; Adamopoulos, G.; Mazzocco, R.; Kolosov, O.; Krier, A.; Vourlias, G.; Milne, W. I.

    2015-05-18

    We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currents (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.

  20. Series resistance and gate leakage correction for improved border trap analysis of Al2O3/InGaAs gate stacks

    NASA Astrophysics Data System (ADS)

    Tang, K.; Scheuermann, A. G.; Zhang, L.; McIntyre, P. C.

    2017-09-01

    As the size of electronic devices scales down, series resistance (RS) and gate leakage effects are commonly observed in electrical measurement of metal-oxide-semiconductor gate stacks. As a result of their effects on device characteristics, these phenomena complicate the analysis of border trap density (Nbt) in the gate insulator using capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. In this work, we develop methods to correct for the effects of RS and gate leakage in Al2O3/InGaAs gate stacks to enable reliable fitting of C-V and G-V data to determine Nbt. When tested using data from Pd/Al2O3/InGaAs gate stacks, the RS correction method successfully removes the RS-induced high frequency dispersion in the accumulation region of the C-V curves and provides an accurate extraction of RS and Nbt. The gate leakage correction method is tested on gate stacks with high gate leakage current of ˜25 μA at 2 V bias, and is found to effectively fit capacitance and conductance data, to achieve consistent Nbt extraction. The compatibility of these two methods is confirmed by analysis of data obtained from gate stacks with both substantial RS and gate leakage.

  1. Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

    NASA Astrophysics Data System (ADS)

    Kamei, Takahiro; Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

    2012-06-01

    Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage (Vt) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BVg) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO2) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source-drain (SD) breakdown voltage (BVDS) as high as 4.5 V was obtained even when the gate length (Lg) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage (Vg) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.

  2. Light-Induced Carrier Transfer in NiSi-Nanodots/Si-Quantum-Dots Hybrid Floating Gate in Metal-Oxide-Semiconductor Structures

    NASA Astrophysics Data System (ADS)

    Morisawa, Naoya; Ikeda, Mitsuhisa; Nakanishi, Sho; Kawanami, Akira; Makihara, Katsunori; Miyazaki, Seiichi

    2010-04-01

    We have fabricated a metal-oxide-semiconductor (MOS) capacitor with a hybrid floating gate stack consisting of silicon quantum dots (Si-QDs) and NiSi Nanodots (NiSi-NDs) with a 3-nm-thick interlayer SiO2, and studied the effect of 1310 nm light irradiation on charge distribution in a hybrid floating gate. The light irradiation resulted in a reduced flat-band voltage shift due to the charging of the hybrid floating gate under the application of gate biases in comparison to the shift in the dark. This result can be interpreted in terms of the shift of the charge centroid toward the gate side in the hybrid floating gate caused by the photoexcitation of electrons in NiSi-NDs and the subsequent electron tunneling to Si-QDs. When the light irradiation was turned off, the transferred charges moved back from the Si-QDs to the NiSi-NDs without being emitted to the Si substrate.

  3. High-performance GaAs metal-oxide-semiconductor capacitor by using NbAlON as high-k gate dielectric

    NASA Astrophysics Data System (ADS)

    Liu, L. N.; Choi, H. W.; Xu, J. P.; Lai, P. T.

    2017-03-01

    A GaAs metal-oxide-semiconductor (MOS) capacitor using NbAlON as a gate dielectric with different Nb contents is fabricated. Experimental results show that the k value and crystallization temperature of the AlON dielectric can be improved by Nb incorporation, together with reduction in negative oxide charges. However, the interface quality and gate leakage become poorer as the Nb content increases, as confirmed by TEM and X-ray photoelectron spectroscopy results. Therefore, through comprehensively considering the advantages and disadvantages, the sample with a Nb/(Al+Nb) atomic ratio of 62.5% exhibits the best characteristics: high k value (23.3), low interface-state density (2.7 × 1012 cm-2/eV), small hysteresis (55 mV), small frequency dispersion, and low gate leakage current (2.66 × 10-5A/cm2 at Vfb + 1 V). By comparing with reported GaAs MOS devices with different high-k gate dielectrics, it can be suggested that NbAlON is a promising gate dielectric material to achieve excellent electrical performance for GaAs MOS devices.

  4. The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

    PubMed Central

    Yang, Wen; Sun, Qing-Qing; Geng, Yang; Chen, Lin; Zhou, Peng; Ding, Shi-Jin; Zhang, David Wei

    2015-01-01

    The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics. PMID:26146017

  5. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy.

    PubMed

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-10-08

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band.

  6. Oxygen Defect-Induced Metastability in Oxide Semiconductors Probed by Gate Pulse Spectroscopy

    PubMed Central

    Lee, Sungsik; Nathan, Arokia; Jeon, Sanghun; Robertson, John

    2015-01-01

    We investigate instability mechanisms in amorphous In-Ga-Zn-O transistors based on bias and illumination stress-recovery experiments coupled with analysis using stretched exponentials and inverse Laplace transform to retrieve the distribution of activation energies associated with metastable oxygen defects. Results show that the recovery process after illumination stress is persistently slow by virtue of defect states with a broad range, 0.85 eV to 1.38 eV, suggesting the presence of ionized oxygen vacancies and interstitials. We also rule out charge trapping/detrapping events since this requires a much smaller activation energy ~0.53 eV, and which tends to be much quicker. These arguments are supported by measurements using a novel gate-pulse spectroscopy probing technique that reveals the post-stress ionized oxygen defect profile, including anti-bonding states within the conduction band. PMID:26446400

  7. Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability

    NASA Astrophysics Data System (ADS)

    Li, Weiyi; Zhang, Zhili; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Sun, Shichuang; Song, Liang; Hao, Ronghui; Fan, Yaming; Cai, Yong; Zhang, Baoshun

    2017-07-01

    We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field. Project supported by the Key Technologies Support Program of Jiangsu Province (No. BE2013002-2) and the National Key Scientific Instrument and Equipment Development Projects of China (No. 2013YQ470767).

  8. Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

    SciTech Connect

    Ceschia, M.; Paccagnella, A. |; Cester, A.; Scarpa, A.; Ghidini, G.

    1998-12-01

    Low-field leakage current has been measured in thin oxides after exposure to ionizing radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunneling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely being defects associated to trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

  9. Mechanical reliability and life prediction of coated metallic interconnects within solid oxide fuel cells

    DOE PAGES

    Xu, Zhijie; Xu, Wei; Stephens, Elizabeth; ...

    2017-07-03

    Metallic cell interconnects (IC) made of ferritic stainless steels, i.e., iron-based alloys, have been increasingly favored in the recent development of planar solid oxide fuel cells (SOFCs) because of their advantages in excellent imperviousness, low electrical resistance, ease in fabrication, and cost effectiveness. Typical SOFC operating conditions inevitably lead to the formation of oxide scales on the surface of ferritic stainless steel, which could cause delamination, buckling, and spallation resulting from the mismatch of the coefficient of thermal expansion and eventually reduce the lifetime of the interconnect components. Various protective coating techniques have been applied to alleviate these drawbacks. Inmore » the present work, a fracture-mechanics-based quantitative modeling framework has been established to predict the mechanical reliability and lifetime of the spinel-coated, surface-modified specimens under an isothermal cooling cycle. Analytical solutions have been formulated to evaluate the scale/substrate interfacial strength and determine the critical oxide thickness in terms of a variety of design factors, such as coating thickness, material properties, and uncertainties. In conclusion, the findings then are correlated with the experimentally measured oxide scale growth kinetics to quantify the predicted lifetime of the metallic interconnects.« less

  10. Reliability of thickness of oxide layer of stainless steels with chromium using cellular automaton model

    SciTech Connect

    Lan, K. C.; Chen, Y.; Yu, G. P.; Hung, T. C.

    2012-07-01

    A cellular automaton (CA) model based on the stochastic approach was proposed to simulate the process of oxidation and corrosion of stainless steels with different contents of chromium in-flowing lead bismuth eutectic (LBE). Chromium is a crucial alloying element added in stainless steels and nickel based alloys which have been proposed to be used in advanced nuclear reactors to improve resistance of the oxidation and corrosion. To verify the reliability of the thickness of the oxide layer by CA model, the influence of the stochastic character on the simulating results was investigated as changing parameter of chromium content of structure material in this study. Ten independent simulations were run for each specific environment. A stable and reasonable results were obtained according to the chi-square of goodness-of-fit test, the chi-square of the thickness of oxide layer for each case were significant smaller than critical chi-square value with a confidence level of 95% ({Chi}{sup 2}{alpha}, v = {Chi}{sup 2} 0.05,9 = 16.92). (authors)

  11. Effect of Oxide Interface Roughness on the Threshold Voltage Fluctuations in Decanano MOSFETs with Ultrathin Gate Oxides

    NASA Technical Reports Server (NTRS)

    Asenov, Asen; Kaya, S.

    2000-01-01

    In this paper we use the Density Gradient (DG) simulation approach to study, in 3-D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale. The random 2-D surfaces used to represent the interface are constructed using the standard assumptions for the auto-correlation function of the interface. The importance of the Quantum Mechanical effects when studying oxide thickness fluctuations are illustrated in several simulation examples.

  12. Oxidation of Phe454 in the Gating Segment Inactivates Trametes multicolor Pyranose Oxidase during Substrate Turnover

    PubMed Central

    Volc, Jindrich; Peterbauer, Clemens K.; Leitner, Christian; Haltrich, Dietmar

    2016-01-01

    The flavin-dependent enzyme pyranose oxidase catalyses the oxidation of several pyranose sugars at position C-2. In a second reaction step, oxygen is reduced to hydrogen peroxide. POx is of interest for biocatalytic carbohydrate oxidations, yet it was found that the enzyme is rapidly inactivated under turnover conditions. We studied pyranose oxidase from Trametes multicolor (TmPOx) inactivated either during glucose oxidation or by exogenous hydrogen peroxide using mass spectrometry. MALDI-MS experiments of proteolytic fragments of inactivated TmPOx showed several peptides with a mass increase of 16 or 32 Da indicating oxidation of certain amino acids. Most of these fragments contain at least one methionine residue, which most likely is oxidised by hydrogen peroxide. One peptide fragment that did not contain any amino acid residue that is likely to be oxidised by hydrogen peroxide (DAFSYGAVQQSIDSR) was studied in detail by LC-ESI-MS/MS, which showed a +16 Da mass increase for Phe454. We propose that oxidation of Phe454, which is located at the flexible active-site loop of TmPOx, is the first and main step in the inactivation of TmPOx by hydrogen peroxide. Oxidation of methionine residues might then further contribute to the complete inactivation of the enzyme. PMID:26828796

  13. CCD gate definition process

    NASA Astrophysics Data System (ADS)

    Bluzer

    1986-02-01

    The present invention utilizes a double masking step in a CCD gate definition process to eliminate the re-entrant oxide by using a thin film layer other than photoresist to define the polysilicon gates used by defining the thin film layer with a double masking process before any of the polysilicon gate layer is etched. It is one object of the present invention, therefore, to provide an improved process for CCD gate definition. It is another object of the invention to provide an improved CCD gate definition process wherein a profiled oxide layer is produced over a polysilicon layer without re-entrant oxide regions. It is another object of the invention to provide an improved CCD gate definition process wherein a thin film layer is utilized to define the polysilicon gate layers. It is another object of the invention to provide an improved CCD gate definition process wherein the thin film layer is defined by a double masking process before any polysilicon layer is etched.

  14. Low Threshold Voltage and High Mobility N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Using Hf-Si/HfO2 Gate Stack Fabricated by Gate-Last Process

    NASA Astrophysics Data System (ADS)

    Ando, Takashi; Hirano, Tomoyuki; Tai, Kaori; Yamaguchi, Shinpei; Yoshida, Shinichi; Iwamoto, Hayato; Kadomura, Shingo; Watanabe, Heiji

    2010-01-01

    Systematic characterization of Hf-Si/HfO2 gate stacks revealed two mobility degradation modes. One is carrier scattering by fixed charges and/or trapped charges induced by the crystallization in the thick HfO2 case (inversion oxide thickness, Tinv> 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate in the thin HfO2 case (Tinv< 1.6 nm) for the Hf-rich electrode. It was demonstrated that careful optimization of the HfO2 thickness and the Hf-Si composition can suppress both modes. As a result, a high electron mobility equivalent to that of n+polycrystalline silicon (poly-Si)/SiO2 (248 cm2 V-1 s-1 at Eeff=1 MV/cm) was obtained at Tinv of 1.47 nm. Moreover, the effective work function of the optimized Hf-Si/HfO2 gate stack is located within 50 mV from the Si band edge (Ec). An extremely high Ion of 1165 µA/µm (at Ioff = 81 nA/µm) at Vdd=1.0 V was demonstrated for a 45 nm gate n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) without strain enhanced technology.

  15. Digital power and performance analysis of inkjet printed ring oscillators based on electrolyte-gated oxide electronics

    NASA Astrophysics Data System (ADS)

    Cadilha Marques, Gabriel; Garlapati, Suresh Kumar; Dehm, Simone; Dasgupta, Subho; Hahn, Horst; Tahoori, Mehdi; Aghassi-Hagmann, Jasmin

    2017-09-01

    Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ≤2 V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ˜4 and 2.3 ms propagation delay time at 1 V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6 V with a frequency of ˜255 Hz and can reach frequencies up to ˜350 Hz at 2 V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits.

  16. Reliability and fatigue failure modes of implant-supported aluminum-oxide fixed dental prostheses

    PubMed Central

    Stappert, Christian F. J.; Baldassarri, Marta; Zhang, Yu; Hänssler, Felix; Rekow, Elizabeth D.; Thompson, Van P.

    2012-01-01

    Objectives To investigate failure modes and reliability of implant-supported aluminum-oxide three-unit fixed-dental-prostheses (FDPs) using two different veneering porcelains. Material and methods Thirty-six aluminum-oxide FDP-frameworks were CAD/CAM fabricated and either hand-veneered(n=18) or over-pressed(n=18). All FDPs were adhesively luted to custom-made zirconium-oxide-abutments attached to dental implant fixtures (RP-4×13mm). Specimens were stored in water prior to mechanical testing. A Step-Stress-Accelerated-Life-Test (SSALT) with three load/cycles varying profiles was developed based on initial single-load-to-failure testing. Failure was defined by veneer chipping or chipping in combination with framework fracture. SSALT was performed on each FDP inclined 30° with respect to the applied load direction. For all specimens, failure modes were analyzed using polarized-reflected-light-microscopy and scanning-electron-microscopy (SEM). Reliability was computed using Weibull analysis software (Reliasoft). Results The dominant failure mode for the over-pressed FDPs was buccal chipping of the porcelain in the loading area of the pontic, while hand-veneered specimens failed mainly by combined failure modes in the veneering porcelain, framework and abutments. Chipping of the porcelain occurred earlier in the over-pressed specimens (350 N/85k, load/cycles) than in the hand-veneered (600 N/110k)(profile I). Given a mission at 300 N load and 100k or 200 K cycles the computed Weibull reliability (2-sided at 90.0 % confidence bounds) was 0.99(1/0.98) and 0.99(1/0.98) for hand-veneered FDPs, and 0.45(0.76/0.10) and 0.05(0.63/0) for over-pressed FDPs, respectively. Conclusions In the range of average clinical loads (300–700 N), hand-veneered aluminum-oxide FDPs showed significantly less failure by chipping of the veneer than the over-pressed. Hand-veneered FDPs under fatigue loading failed at loads ≥ 600N. PMID:22093019

  17. Flatband voltage control in p-metal gate metal-oxide-semiconductor field effect transistor by insertion of TiO2 layer

    NASA Astrophysics Data System (ADS)

    Maeng, W. J.; Kim, Woo-Hee; Koo, Ja Hoon; Lim, S. J.; Lee, Chang-Soo; Lee, Taeyoon; Kim, Hyungjun

    2010-02-01

    Titanium oxide (TiO2) layer was used to control the flatband voltage (VFB) of p-type metal-oxide-semiconductor field effect transistors. TiO2 was deposited by plasma enhanced atomic layer deposition (PE-ALD) on hafnium oxide (HfO2) gate dielectrics. Comparative studies between TiO2 and Al2O3 as capping layer have shown that improved device properties with lower capacitance equivalent thickness (CET), interface state density (Dit), and flatband voltage (VFB) shift were achieved by PE-ALD TiO2 capping layer.

  18. Investigation of interface property in Al/SiO2/ n-SiC structure with thin gate oxide by illumination

    NASA Astrophysics Data System (ADS)

    Chang, P. K.; Hwu, J. G.

    2017-04-01

    The reverse tunneling current of Al/SiO2/ n-SiC structure employing thin gate oxide is introduced to examine the interface property by illumination. The gate current at negative bias decreases under blue LED illumination, yet increases under UV lamp illumination. Light-induced electrons captured by interface states may be emitted after the light sources are off, leading to the recovery of gate currents. Based on transient characteristics of gate current, the extracted trap level is close to the light energy for blue LED, indicating that electron capture induced by lighting may result in the reduction of gate current. Furthermore, bidirectional C- V measurements exhibit a positive voltage shift caused by electron trapping under blue LED illumination, while a negative voltage shift is observed under UV lamp illumination. Distinct trapping and detrapping behaviors can be observed from variations in I- V and C- V curves utilizing different light sources for 4H-SiC MOS capacitors with thin insulators.

  19. Floating Gate Memory with Biomineralized Nanodots Embedded in High-k Gate Dielectric

    NASA Astrophysics Data System (ADS)

    Ohara, Kosuke; Yamashita, Ichiro; Yaegashi, Toshitake; Moniwa, Masahiro; Yoshimaru, Masaki; Uraoka, Yukiharu

    2009-09-01

    The memory properties of a nanodot-type floating gate memory with Co bio-nanodots (Co-BNDs) embedded in HfO2 were investigated. High-density and uniform Co-BNDs were adsorbed on the HfO2 tunnel oxide using ferritin. The fabricated metal oxide semiconductor (MOS) capacitor exhibited a capacitance-voltage (C-V) curve with large hysteresis. The memory window size was 30 times higher than that of the MOS capacitor with a SiO2 gate oxide. Not only a large memory window but also excellent charge retention and reliability characteristics were obtained for a MOS field-effect transistor (MOSFET). This research confirmed that the proposed memory is promising for use in next-generation memory devices.

  20. Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks

    NASA Astrophysics Data System (ADS)

    Henkel, Christoph; Hellström, Per-Erik; Östling, Mikael; Stöger-Pollach, Michael; Bethge, Ole; Bertagnolli, Emmerich

    2012-08-01

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 1011 eV-1 cm-2 are demonstrated. The formation of the high-k LaxGeyOz layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  1. Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks.

    PubMed

    Henkel, Christoph; Hellström, Per-Erik; Ostling, Mikael; Stöger-Pollach, Michael; Bethge, Ole; Bertagnolli, Emmerich

    2012-08-01

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La x Ge y O z interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k La x Ge y O z layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  2. Atomic layer deposition TiO2-Al2O3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

    DOE PAGES

    Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

    2014-10-15

    This research focuses on the benefits and properties of TiO2-Al2O3 nano-stack thin films deposited on Ga2O3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO2, 7.1 nm Al2O3 and 2 nm Ga2O3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectron spectroscopy (XPS) depth profile, was negligible for GaN pretreated bymore » thermal oxidation in O2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO2-Al2O3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al2O3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 1011 cm-2. The gate leakage current density (J=2.81× 10-8 A/cm2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO2/Al2O3 for serving as the gate oxide on Ga2O3/GaN based MOS devices.« less

  3. Near-IR squaraine dye-loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device.

    PubMed

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-09-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use.

  4. Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

    PubMed Central

    Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

    2015-01-01

    Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

  5. Modeling of n-InAs metal oxide semiconductor capacitors with high-κ gate dielectric

    SciTech Connect

    Babadi, A. S. Lind, E.; Wernersson, L. E.

    2014-12-07

    A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holes even in depletion, so a full charge treatment is necessary.

  6. Simulation of Leakage Current in Si/Ge/Si Quantum Dot Floating Gate MOSFET Using High-K Material as Tunnel Oxide

    NASA Astrophysics Data System (ADS)

    Aji, Adha Sukma; Nugraha, Mohamad Insan; Yudhistira; Rahayu, Fitria; Darma, Yudi

    2011-12-01

    Leakage current in nano-scale MOSFET has been calculated using variety of tunnel oxides. Firstly, this paper evaluates the leakage current in MOSFET devices when using SiO2 as tunnel oxide. When the thickness of tunnel oxide decreases into 1,4 nm, the leakage current will raise and cause power dissipation about 40 percent. Leakage current can be reduced by using high-K materials as tunnel oxides. Thicker high-K materials as tunnel oxides are easier to fabricate than SiO2 tunnel oxides with the thickness down to 1,4 nm. In term of Equivalent Oxide Thickness (EOT), using high-K materials for tunnel oxides could give the better performance as 1,4nm SiO2 which is also more simple in the fabrication. Here, we also evaluates the leakage current as the function of temperature, channel length, and oxide thickness. Computational result shows that using HfO2 to replace SiO2 as tunnel oxides can make leakage current decrease up to seven times. For practically use, HfO2 were suiTable as tunnel oxide in memory devices, particularly in quantum dot (QD) floating gate memory. In this case we use heterostructure QD consisting Si/Ge/Si as electronic storage node. The results demonstrated that the memory operation using HfO2 as tunnel oxide has a better performance rather than SiO2.

  7. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    NASA Astrophysics Data System (ADS)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-01

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  8. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    SciTech Connect

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  9. Charge noise analysis of metal oxide semiconductor dual-gate Si/SiGe quantum point contacts

    SciTech Connect

    Kamioka, J.; Oda, S.; Kodera, T.; Takeda, K.; Obata, T.; Tarucha, S.

    2014-05-28

    The frequency dependence of conductance noise through a gate-defined quantum point contact fabricated on a Si/SiGe modulation doped wafer is characterized. The 1/f{sup 2} noise, which is characteristic of random telegraph noise, is reduced by application of a negative bias on the global top gate to reduce the local gate voltage. Direct leakage from the large global gate voltage also causes random telegraph noise, and therefore, there is a suitable point to operate quantum dot measurement.

  10. INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

    2010-10-01

    As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

  11. The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/InGaAs gate stack

    SciTech Connect

    Winter, R.; Krylov, I.; Eizenberg, M.; Ahn, J.; McIntyre, P. C.

    2014-05-19

    The effect of post oxide deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/ InGaAs gate stacks was investigated. Using a systematic method for effective work function extraction, a shift of 0.3 ± 0.1 eV was found between the effective work function of forming gas annealed samples and vacuum annealed samples. The electrical measurements enabled us to obtain the band alignment of the metal/Al{sub 2}O{sub 3}/InGaAs gate stack. This band alignment was confirmed by X-ray photoelectron spectroscopy. The measured shift in the effective work function between different annealing ambient may be attributed to indium out-diffusion during post oxide deposition annealing that is observed in forming gas anneal to a much larger extent than in vacuum.

  12. Zinc Oxide Nanorods Grown on Printed Circuit Board for Extended-Gate Field-Effect Transistor pH Sensor

    NASA Astrophysics Data System (ADS)

    Van Thanh, Pham; Nhu, Le Thi Quynh; Mai, Hong Hanh; Tuyen, Nguyen Viet; Doanh, Sai Cong; Viet, Nguyen Canh; Kien, Do Trung

    2017-02-01

    Zinc oxide (ZnO) nanorods (NRs) were grown directly on printed circuit boards with a 35-μm-thick copper layer using a seedless galvanic-cell hydrothermal process. The hexagonal structure of the synthesized ZnO NRs was observed by scanning electron microscopy. The microstructural characteristics of the as-grown ZnO NRs were investigated by x-ray diffraction analysis, revealing preferred (002) growth direction. Raman and photoluminescence spectra confirmed the high crystalline quality of the ZnO NRs. As-grown ZnO NRs were then grown for 7 h using the galvanic effect for use as the pH membrane of an extended-gate field-effect transistor pH sensor (pH-EGFET). The current-voltage characteristics showed sensitivity of 15.4 mV/pH and 0.26 (μA)1/2/pH in the linear and saturated region, respectively. Due to their cost effectiveness, low-temperature processing, and ease of fabrication, such devices are potential candidates for use as flexible, low-cost, disposable biosensors.

  13. Theoretical Study of Triboelectric-Potential Gated/Driven Metal-Oxide-Semiconductor Field-Effect Transistor.

    PubMed

    Peng, Wenbo; Yu, Ruomeng; He, Yongning; Wang, Zhong Lin

    2016-04-26

    Triboelectric nanogenerator has drawn considerable attentions as a potential candidate for harvesting mechanical energies in our daily life. By utilizing the triboelectric potential generated through the coupling of contact electrification and electrostatic induction, the "tribotronics" has been introduced to tune/control the charge carrier transport behavior of silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). Here, we perform a theoretical study of the performances of tribotronic MOSFET gated by triboelectric potential in two working modes through finite element analysis. The drain-source current dependence on contact-electrification generated triboelectric charges, gap separation distance, and externally applied bias are investigated. The in-depth physical mechanism of the tribotronic MOSFET operations is thoroughly illustrated by calculating and analyzing the charge transfer process, voltage relationship to gap separation distance, and electric potential distribution. Moreover, a tribotronic MOSFET working concept is proposed, simulated and studied for performing self-powered FET and logic operations. This work provides a deep understanding of working mechanisms and design guidance of tribotronic MOSFET for potential applications in micro/nanoelectromechanical systems (MEMS/NEMS), human-machine interface, flexible electronics, and self-powered active sensors.

  14. Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

    NASA Astrophysics Data System (ADS)

    Chakraborty, Chaitali; Bose, Chayanika

    2016-02-01

    The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal-oxide-semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si-substrate interface than to SiO2/Al-gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance-voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

  15. Zinc Oxide Nanorods Grown on Printed Circuit Board for Extended-Gate Field-Effect Transistor pH Sensor

    NASA Astrophysics Data System (ADS)

    Van Thanh, Pham; Nhu, Le Thi Quynh; Mai, Hong Hanh; Tuyen, Nguyen Viet; Doanh, Sai Cong; Viet, Nguyen Canh; Kien, Do Trung

    2017-06-01

    Zinc oxide (ZnO) nanorods (NRs) were grown directly on printed circuit boards with a 35- μm-thick copper layer using a seedless galvanic-cell hydrothermal process. The hexagonal structure of the synthesized ZnO NRs was observed by scanning electron microscopy. The microstructural characteristics of the as-grown ZnO NRs were investigated by x-ray diffraction analysis, revealing preferred (002) growth direction. Raman and photoluminescence spectra confirmed the high crystalline quality of the ZnO NRs. As-grown ZnO NRs were then grown for 7 h using the galvanic effect for use as the pH membrane of an extended-gate field-effect transistor pH sensor (pH-EGFET). The current-voltage characteristics showed sensitivity of 15.4 mV/pH and 0.26 ( μA)1/2/pH in the linear and saturated region, respectively. Due to their cost effectiveness, low-temperature processing, and ease of fabrication, such devices are potential candidates for use as flexible, low-cost, disposable biosensors.

  16. Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

    PubMed

    Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

    2014-01-01

    Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

  17. Multi-technique Approach for the Evaluation of the Crystalline Phase of Ultrathin High-k Gate Oxide Films

    NASA Astrophysics Data System (ADS)

    Bersch, E.; LaRose, J. D.; Wells, I.; Consiglio, S.; Clark, R. D.; Leusink, G. J.; Matyi, R. J.; Diebold, A. C.

    2011-11-01

    In order to continue scaling metal oxide semiconductor field effect transistors (MOSFETs) with HfO2 gate oxides, efforts are being made to further improve the deposited high-k film properties. Recently, a process whereby an HfO2 film is deposited through a series of depositions and anneals (so-called DADA process) has been shown to result in films that give rise to MOS capacitors (MOSCAPs) which are electrically scaled compared to MOSCAPs with HfO2 films that only received post deposition anneals (PDA) or no anneals. We have measured as-deposited, DADA and PDA HfO2 films using four measurement techniques, all of which are non-destructive and capable of being used for in-line processing, to evaluate their crystallinity and crystalline phases. Grazing incidence in-plane X-ray diffraction was used to determine the crystalline phases of the HfO2 films. We observed the crystalline phases of these films to be process dependent. Additionally, X-ray and UV photoelectron spectroscopy were used to show the presence of crystallinity in the films. As a fourth technique, spectroscopic ellipsometry was used to determine if the crystalline phases were monoclinic. The combination of techniques was useful in that XPS and UPS were able to confirm the amorphous nature of a 30 cycle DADA film, as measured by GIIXRD, and GIIXRD was able to help us interpret the SE data as being an indication of the monoclinic phase of HfO2.

  18. A reversible fluorescence nanoswitch based on bifunctional reduced graphene oxide: use for detection of Hg2+ and molecular logic gate operation.

    PubMed

    Huang, Wei Tao; Shi, Yan; Xie, Wan Yi; Luo, Hong Qun; Li, Nian Bing

    2011-07-21

    Herein, we demonstrate the first use of a reduced graphene oxide (rGO)-organic dye nanoswitch for the label-free, sensitive and selective detection of Hg(2+) using bifunctional rGO as an effective nanoquencher and highly selective nanosorbent. Moreover, a reversible on-off INHIBIT rGO logic gate based on a cysteine-Hg(2+) system has also been designed.

  19. Thermally oxidized 2D TaS2 as a high-κ gate dielectric for MoS2 field-effect transistors

    NASA Astrophysics Data System (ADS)

    Chamlagain, Bhim; Cui, Qingsong; Paudel, Sagar; Ming-Cheng Cheng, Mark; Chen, Pai-Yen; Zhou, Zhixian

    2017-09-01

    We report a new approach to integrating high-κ dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered two-dimensional (2D) TaS2. Combined x-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance-voltage (C-V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2 V-1 s-1 at room temperature, indicating high dielectric quality and low interface trap density.

  20. Reliability analysis of visual ranking of coronary artery calcification on low-dose CT of the thorax for lung cancer screening: comparison with ECG-gated calcium scoring CT.

    PubMed

    Kim, Yoon Kyung; Sung, Yon Mi; Cho, So Hyun; Park, Young Nam; Choi, Hye-Young

    2014-12-01

    Coronary artery calcification (CAC) is frequently detected on low-dose CT (LDCT) of the thorax. Concurrent assessment of CAC and lung cancer screening using LDCT is beneficial in terms of cost and radiation dose reduction. The aim of our study was to evaluate the reliability of visual ranking of positive CAC on LDCT compared to Agatston score (AS) on electrocardiogram (ECG)-gated calcium scoring CT. We studied 576 patients who were consecutively registered for health screening and undergoing both LDCT and ECG-gated calcium scoring CT. We excluded subjects with an AS of zero. The final study cohort included 117 patients with CAC (97 men; mean age, 53.4 ± 8.5). AS was used as the gold standard (mean score 166.0; range 0.4-3,719.3). Two board-certified radiologists and two radiology residents participated in an observer performance study. Visual ranking of CAC was performed according to four categories (1-10, 11-100, 101-400, and 401 or higher) for coronary artery disease risk stratification. Weighted kappa statistics were used to measure the degree of reliability on visual ranking of CAC on LDCT. The degree of reliability on visual ranking of CAC on LDCT compared to ECG-gated calcium scoring CT was excellent for board-certified radiologists and good for radiology residents. A high degree of association was observed with 71.6% of visual rankings in the same category as the Agatston category and 98.9% varying by no more than one category. Visual ranking of positive CAC on LDCT is reliable for predicting AS rank categorization.

  1. Reduction of surface roughening due to copper contamination prior to ultra-thin gate oxidation

    NASA Astrophysics Data System (ADS)

    Peterson, Charles A.; Vermeire, Bert; Sarid, Dror; Parks, Harold G.

    2001-09-01

    Roughening of the polished side of a silicon wafer caused by copper contamination present on the unpolished side of the wafer was quantified by tapping-mode atomic force microscopy (AFM). The copper contamination was introduced via a contaminated buffered hydrochloric acid solution on the unpolished side of the silicon wafer while the polished side was protected. The protection was then removed, and the wafer placed in a clean HF solution. As a result, the copper on the unpolished side catalyzed electrochemical dissolution of the polished side of the silicon. Power spectral density analysis of hundreds of AFM images showed a 10-fold increase in surface roughness with features between 30 and 300 nm in diameter. Time-dependant dielectric breakdown measurements showed a significant decrease in oxide quality in these wafers. However, the introduction of HCl to the HF solution significantly reduced the roughening process.

  2. Low-temperature processed Schottky-gated field-effect transistors based on amorphous gallium-indium-zinc-oxide thin films

    NASA Astrophysics Data System (ADS)

    Lorenz, M.; Lajn, A.; Frenzel, H.; v. Wenckstern, H.; Grundmann, M.; Barquinha, P.; Martins, R.; Fortunato, E.

    2010-12-01

    We have investigated the electrical properties of metal-semiconductor field-effect transistors (MESFET) based on amorphous oxide semiconductor channels. All functional parts of the devices were sputter-deposited at room temperature. The influence on the electrical properties of a 150 °C annealing step of the gallium-indium-zinc-oxide channel is investigated. The MESFET technology offers a simple route for processing of the transistors with excellent electrical properties such as low subthreshold swing of 112 mV/decade, gate sweep voltages of 2.5 V, and channel mobilities up to 15 cm2/V s.

  3. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating.

    PubMed

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S; Takeuchi, Ichiro; Greene, Richard L

    2016-05-25

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2-xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of -2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  4. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    NASA Astrophysics Data System (ADS)

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-05-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2‑xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of ‑2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected.

  5. Evolution of electronic states in n-type copper oxide superconductor via electric double layer gating

    PubMed Central

    Jin, Kui; Hu, Wei; Zhu, Beiyi; Kim, Dohun; Yuan, Jie; Sun, Yujie; Xiang, Tao; Fuhrer, Michael S.; Takeuchi, Ichiro; Greene, Richard. L.

    2016-01-01

    The occurrence of electrons and holes in n-type copper oxides has been achieved by chemical doping, pressure, and/or deoxygenation. However, the observed electronic properties are blurred by the concomitant effects such as change of lattice structure, disorder, etc. Here, we report on successful tuning the electronic band structure of n-type Pr2−xCexCuO4 (x = 0.15) ultrathin films, via the electric double layer transistor technique. Abnormal transport properties, such as multiple sign reversals of Hall resistivity in normal and mixed states, have been revealed within an electrostatic field in range of −2 V to + 2 V, as well as varying the temperature and magnetic field. In the mixed state, the intrinsic anomalous Hall conductivity invokes the contribution of both electron and hole-bands as well as the energy dependent density of states near the Fermi level. The two-band model can also describe the normal state transport properties well, whereas the carrier concentrations of electrons and holes are always enhanced or depressed simultaneously in electric fields. This is in contrast to the scenario of Fermi surface reconstruction by antiferromagnetism, where an anti-correlation is commonly expected. PMID:27221198

  6. Chemical Bonding, Interfaces and Defects in Hafnium Oxide/Germanium Oxynitride Gate Stacks on Ge (100)

    SciTech Connect

    Oshima, Yasuhiro; Sun, Yun; Kuzum, Duygu; Sugawara, Takuya; Saraswat, Krishna C.; Pianetta, Piero; McIntyre, Paul C.; /Stanford U., Materials Sci. Dept.

    2008-10-31

    Correlations among interface properties and chemical bonding characteristics in HfO{sub 2}/GeO{sub x}N{sub y}/Ge MIS stacks were investigated using in-situ remote nitridation of the Ge (100) surface prior to HfO{sub 2} atomic layer deposition (ALD). Ultra thin ({approx}1.1 nm), thermally stable and aqueous etch-resistant GeO{sub x}N{sub y} interfaces layers that exhibited Ge core level photoelectron spectra (PES) similar to stoichiometric Ge{sub 3}N{sub 4} were synthesized. To evaluate GeO{sub x}N{sub y}/Ge interface defects, the density of interface states (D{sub it}) was extracted by the conductance method across the band gap. Forming gas annealed (FGA) samples exhibited substantially lower D{sub it} ({approx} 1 x 10{sup 12} cm{sup -2} eV{sup -1}) than did high vacuum annealed (HVA) and inert gas anneal (IGA) samples ({approx} 1x 10{sup 13} cm{sup -2} eV{sup -1}). Germanium core level photoelectron spectra from similar FGA-treated samples detected out-diffusion of germanium oxide to the HfO{sub 2} film surface and apparent modification of chemical bonding at the GeO{sub x}N{sub y}/Ge interface, which is related to the reduced D{sub it}.

  7. Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high- k LaTiON gate dielectric

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Chan, C. L.; Lai, P. T.

    2010-06-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La2O3 ratio, a suitable Ti/La2O3 ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×1011 eV-1 cm-2, and relatively low gate-leakage current density of 2.0×10-3 A cm-2 at a gate voltage of 1 V.

  8. Role of PheE15 Gate in Ligand Entry and Nitric Oxide Detoxification Function of Mycobacterium tuberculosis Truncated Hemoglobin N

    PubMed Central

    Bidon-Chanal, Axel; Forti, Flavio; Martí, Marcelo A.; Boechi, Leonardo; Estrin, Dario A.; Dikshit, Kanak L.; Luque, F. Javier

    2012-01-01

    The truncated hemoglobin N, HbN, of Mycobacterium tuberculosis is endowed with a potent nitric oxide dioxygenase (NOD) activity that allows it to relieve nitrosative stress and enhance in vivo survival of its host. Despite its small size, the protein matrix of HbN hosts a two-branched tunnel, consisting of orthogonal short and long channels, that connects the heme active site to the protein surface. A novel dual-path mechanism has been suggested to drive migration of O2 and NO to the distal heme cavity. While oxygen migrates mainly by the short path, a ligand-induced conformational change regulates opening of the long tunnel branch for NO, via a phenylalanine (PheE15) residue that acts as a gate. Site-directed mutagenesis and molecular simulations have been used to examine the gating role played by PheE15 in modulating the NOD function of HbN. Mutants carrying replacement of PheE15 with alanine, isoleucine, tyrosine and tryptophan have similar O2/CO association kinetics, but display significant reduction in their NOD function. Molecular simulations substantiated that mutation at the PheE15 gate confers significant changes in the long tunnel, and therefore may affect the migration of ligands. These results support the pivotal role of PheE15 gate in modulating the diffusion of NO via the long tunnel branch in the oxygenated protein, and hence the NOD function of HbN. PMID:23145144

  9. Universal Superreplication of Unitary Gates

    NASA Astrophysics Data System (ADS)

    Chiribella, G.; Yang, Y.; Huang, C.

    2015-03-01

    Quantum states obey an asymptotic no-cloning theorem, stating that no deterministic machine can reliably replicate generic sequences of identically prepared pure states. In stark contrast, we show that generic sequences of unitary gates can be replicated deterministically at nearly quadratic rates, with an error vanishing on most inputs except for an exponentially small fraction. The result is not in contradiction with the no-cloning theorem, since the impossibility of deterministically transforming pure states into unitary gates prevents the application of the gate replication protocol to states. In addition to gate replication, we show that N parallel uses of a completely unknown unitary gate can be compressed into a single gate acting on O (log2N ) qubits, leading to an exponential reduction of the amount of quantum communication needed to implement the gate remotely.

  10. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    DOE PAGES

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; ...

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specificmore » contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.« less

  11. Determination of trap distributions from current characteristics of pentacene field-effect transistors with surface modified gate oxide

    NASA Astrophysics Data System (ADS)

    Scheinert, Susanne; Pernstich, Kurt P.; Batlogg, Bertram; Paasch, Gernot

    2007-11-01

    It has been demonstrated [K. P. Pernstich, S. Haas, D. Oberhoff, C. Goldmann, D. J. Gundlach, B. Batlogg, A. N. Rashid, and G. Schitter, J. Appl. Phys. 96, 6431 (2004)] that a controllable shift of the threshold voltage in pentacene thin film transistors is caused by the use of organosilanes with different functional groups forming a self-assembled monolayer (SAM) on the gate oxide. The observed broadening of the subthreshold region indicates that the SAM creates additional trap states. Indeed, it is well known that traps strongly influence the behavior of organic field-effect transistors (OFETs). Therefore, the so-called "amorphous silicon (a-Si) model" has been suggested to be an appropriate model to describe OFETs. The main specifics of this model are transport of carriers above a mobility edge obeying Boltzmann statistics and exponentially distributed tail states and deep trap states. Here, approximate trap distributions are determined by adjusting two-dimensional numerical simulations to the experimental data. It follows from a systematic variation of parameters describing the trap distributions that the existence of both donorlike and acceptorlike trap distributions near the valence band, respectively, and a fixed negative interface charge have to be assumed. For two typical devices with different organosilanes the electrical characteristics can be described well with a donorlike bulk trap distribution, an acceptorlike interface distribution, and/or a fixed negative interface charge. As expected, the density of the fixed or trapped interface charge depends strongly on the surface treatment of the dielectric. There are some limitations in determining the trap distributions caused by either slow time-dependent processes resulting in differences between transfer and output characteristics, or in the uncertainty of the effective mobility.

  12. Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    NASA Astrophysics Data System (ADS)

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-01

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in "gate-controlled-diode" configuration. The measurements revealed an anomalous non-steady conduction under negative bias (VG > |20 V|) through the SiO2/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (Ntrap ˜ 2 × 1011 cm-2).

  13. Non-volatile nano-floating gate memory with Pt-Fe2O3 composite nanoparticles and indium gallium zinc oxide channel

    NASA Astrophysics Data System (ADS)

    Hu, Quanli; Lee, Seung Chang; Baek, Yoon-Jae; Lee, Hyun Ho; Kang, Chi Jung; Kim, Hyun-Mi; Kim, Ki-Bum; Yoon, Tae-Sik

    2013-02-01

    Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe2O3 composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe2O3 nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of 3 × 1011 cm-2 by a solution-based dip-coating process. The Pt core ( 3 nm in diameter) and Fe2O3-shell ( 6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of 4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of 0.66 V after pulse programming at +20 V for 1 s with retention > 65 % after 104 s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

  14. High mobility field effect transistor based on BaSnO{sub 3} with Al{sub 2}O{sub 3} gate oxide

    SciTech Connect

    Park, Chulkwon; Kim, Useong; Ju, Chan Jong; Park, Ji Sung; Kim, Young Mo; Char, Kookrin

    2014-11-17

    We fabricated an n-type accumulation-mode field effect transistor based on BaSnO{sub 3} transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn){sub 2}O{sub 3} as the source, drain, and gate electrodes, Al{sub 2}O{sub 3} as the gate insulator, and La-doped BaSnO{sub 3} as the semiconducting channel. The Al{sub 2}O{sub 3} gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm{sup 2}/Vs and the I{sub on}/I{sub off} ratio value higher than 10{sup 5} for V{sub DS} = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO{sub 3} on SrTiO{sub 3} substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al{sub 2}O{sub 3} as well as the threading dislocations.

  15. Oxide thickness-dependent effects of source doping profile on the performance of single- and double-gate tunnel field-effect transistors

    NASA Astrophysics Data System (ADS)

    Chien, Nguyen Dang; Shih, Chun-Hsing

    2017-02-01

    Operated by the band-to-band tunneling at the source-channel junction, the source engineering has been considered as an efficient approach to enhance the performance of tunnel field-effect transistors (TFETs). In this paper, we report a new feature that the effects of source doping profile on the performance of single- and double-gate germanium TFETs depend on equivalent oxide thickness (EOT). Based on the numerical simulations, it is shown that the effect of source concentration on the on-current is stronger with decreasing the EOT, particularly in the double-gate configuration due to the higher gate control capability. Importantly, when the EOT is decreased below a certain value, abrupt source-channel junctions are not only unnecessary, but gradual source doping profiles even improve the performance of TFETs because of the increase in vertical tunneling generation. With the continuous trend of scaling EOT, the oxide thickness-dependent effects of source doping profile should be properly considered in designing TFET devices.

  16. Effect of Pr Valence State on Interfacial Structure and Electrical Properties of Pr Oxide/PrON/Ge Gate Stack Structure

    NASA Astrophysics Data System (ADS)

    Kato, Kimihiko; Sakashita, Mitsuo; Takeuchi, Wakana; Kondo, Hiroki; Nakatsuka, Osamu; Zaima, Shigeaki

    2011-04-01

    In this study, we investigated the valence state and chemical bonding state of Pr in a Pr oxide/PrON/Ge structure. We clarified the relationship between the valence state of Pr and the Pr oxide/Ge interfacial reaction using Pr oxide/Ge and Pr oxide/PrON/Ge samples. We found the formation of three Pr oxide phases in Pr oxide films; hexagonal Pr2O3 (h-Pr2O3) (Pr3+), cubic Pr2O3 (c-Pr2O3) (Pr3+), and c-PrO2 (Pr4+). We also investigated the effect of a nitride interlayer on the interfacial reaction in Pr oxide/Ge gate stacks. In a sample with a nitride interlayer (Pr oxide/PrON/Ge), metallic Pr-Pr bonds are also formed in the c-Pr2O3 film. After annealing in H2 ambient, the diffusion of Ge into Pr oxide is not observed in this sample. Pr-Pr bonds probably prevent the interfacial reaction and Ge oxide formation, considering that the oxygen chemical potential of this film is lower than that of a GeO2/Ge system. On the other hand, the rapid thermal oxidation (RTO) treatment terminates the O vacancies and defects in c-Pr2O3. As a result, c-PrO2 with tetravalent Pr is formed in the Pr oxide/PrON/Ge sample with RTO. In this sample, the leakage current density is effectively decreased in comparison with the sample without RTO. Hydrogen termination works effectively in Pr oxide/PrON/Ge samples with and without RTO, and we can achieve an interface state density of as low as 4 ×1011 eV-1·cm-2.

  17. CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

    NASA Astrophysics Data System (ADS)

    Hu, Shi-Gang; Hao, Yue; Ma, Xiao-Hua; Cao, Yan-Rong; Chen, Chi; Wu, Xiao-Feng

    2009-12-01

    This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

  18. High Performance Enhancement-Mode AlGaN/GaN MOSHEMT using Bimodal-Gate-Oxide and CF4 Plasma Treatment

    NASA Astrophysics Data System (ADS)

    Pang, Liang; Kim, Kyekyoon

    2013-03-01

    To realize GaN E-mode HEMTs, CF4 plasma treatment is commonly used. However, comparable performance as the D-mode counterpart has yet to be achieved, since the F-ions implanted into 2DEG degrade the electron mobility by impurity scattering. In this study, a bimodal-gate-oxide scheme is developed, where ALD-Al2O3is utilized to prevent deep ion implantation, and sputtered-SiO2 is employed to suppress plasma-induced leakage current. Firstly, with the Al2O3 energy barrier, the CF4-plasma-treated MOSHEMT increased Vth from -3 V to 0 V, while Imax was only reduced from 503 mA/mm to 460 mA/mm. SIMS measurements confirmed that F- ions were accumulated in the top 5 nm of Al2O3, and the 2DEG impurity concentration was 10 times smaller than the conventional structure. However, due to the gate leakage current through plasma-generated defects in Al2O3, the device exhibited small gate swing of 2 V. Therefore, before gate metal deposition, a SiO2 film was sputtered at room temperature in a self-aligned manner. The highly condensed sputtered-SiO2 was effective in blocking the leakage current. Thus-fabricated bimodal-MOSHEMT exhibited Vth of 0 V, gate swing of 5 V, and Imaxof 462 mA/mm. The small 8% current degradation when converting from D-mode to E-mode is better than previous results. The MOCVD AlGaN/GaN templates used in this work were provided by Kyungpook National University, Korea for which we are grateful to Prof. Jung-Hee Lee and Mr. Dong-Seok Kim.

  19. Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

    NASA Astrophysics Data System (ADS)

    Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

    2017-02-01

    This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm‑2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

  20. Normally-off AlGaN/GaN-on-Si metal-insulator-semiconductor heterojunction field-effect transistor with nitrogen-incorporated silicon oxide gate insulator

    NASA Astrophysics Data System (ADS)

    Roh, Seung-Hyun; Eom, Su-Keun; Choi, Gwang-Ho; Kang, Myoung-Jin; Kim, Dong-Hwan; Hwang, Il-Hwan; Seo, Kwang-Seok; Lee, Jae-Gil; Byun, Young-Chul; Cha, Ho-Young

    2017-08-01

    We have developed a nitrogen-incorporated silicon oxide (SiOxNy) deposition process using plasma enhanced atomic layer deposition (PEALD) for the gate insulator of recessed-gate Al-GaN/GaN metal-insulator-semiconductor heterojunction field-effect transistors. The SiOxNy film deposited on a recessed GaN surface exhibited a breakdown field of 13.2 MV/cm and a conduction band offset of 3.37 eV, which are the highest values reported for GaN MIS structures to the best of our knowledge. The fabricated normally-off transistor exhibited very promising characteristics such as a threshold voltage of 2.2 V, a maximum drain current density of 428 mA/mm, and a breakdown voltage of 928 V.

  1. Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

    SciTech Connect

    Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Oktyabrsky, Serge; Veksler, Dmitry; Hill, Richard

    2014-03-31

    In this work, we are using a gated Hall method for measurement of free carrier density and electron mobility in buried InGaAs quantum well metal-oxide-semiconductor field-effect-transistor channels. At room temperature, mobility over 8000 cm{sup 2}/Vs is observed at ∼1.4 × 10{sup 12} cm{sup −2}. Temperature dependence of the electron mobility gives the evidence that remote Coulomb scattering dominates at electron density <2 × 10{sup 11} cm{sup −2}. Spectrum of the interface/border traps is quantified from comparison of Hall data with capacitance-voltage measurements or electrostatic modeling. Above the threshold voltage, gate control is strongly limited by fast traps that cannot be distinguished from free channel carriers just by capacitance-based methods and can be the reason for significant overestimation of channel density and underestimation of carrier mobility from transistor measurements.

  2. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    SciTech Connect

    Niang, K. M.; Flewitt, A. J.; Barquinha, P. M. C.; Martins, R. F. P.

    2016-02-29

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.

  3. Polysilicon gate etching in high density plasmas. V. Comparison between quantitative chemical analysis of photoresist and oxide masked polysilicon gates etched in HBr/Cl{sub 2}/O{sub 2} plasmas

    SciTech Connect

    Bell, F.H.; Joubert, O.

    1997-01-01

    We have used x-ray photoelectron spectroscopy (XPS) to study the chemical constituents present on the surfaces after etching of poly-Si features masked with photoresist or oxide patterns. The wafers were etched in a low pressure, high density plasma, helicon source using a HBr/Cl{sub 2}/O{sub 2} gas mixture. The O{sub 2} gas flow rate was tuned to obtain anisotropic etching profiles by forming an SiO{sub 2} like layer on the sidewalls of the features and maximizing the polysilicon/gate oxide selectivity. Electrostatic charging of insulating surfaces and geometric shadowing of photoelectrons by adjacent photoresist lines were performed to differentiate the photoemission signals from the tops, sidewalls, and bottoms of the features. XPS analyses have shown that the passivation layer formed on the polysilicon sidewalls during etching is a chlorine rich silicon oxide film with both type of masks. This film contains a low carbon concentration when resist is used as a mask. The similar thickness and constitution of the sidewall for oxide and photoresist masked poly-Si samples indicate that the nature of the mask material has no significant effect on the sidewall passivation mechanism. {copyright} {ital 1997 American Vacuum Society.}

  4. Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Dib, Elias; Bescond, Marc; Cavassilas, Nicolas; Michelini, Fabienne; Raymond, Laurent; Lannoo, Michel

    2013-08-01

    Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

  5. Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation

    NASA Astrophysics Data System (ADS)

    Al-Shareef, H. N.; Karamcheti, A.; Luo, T. Y.; Bersuker, G.; Brown, G. A.; Murto, R. W.; Jackson, M. D.; Huff, H. R.; Kraus, P.; Lopes, D.; Olsen, C.; Miner, G.

    2001-06-01

    In situ steam generated (ISSG) oxides have recently attracted interest for use as gate dielectrics because of their demonstrated reliability improvement over oxides formed by dry oxidation. [G. Minor, G. Xing, H. S. Joo, E. Sanchez, Y. Yokota, C. Chen, D. Lopes, and A. Balakrishna, Electrochem. Soc. Symp. Proc. 99-10, 3 (1999); T. Y. Luo, H. N. Al-Shareef, G. A. Brown, M. Laughery, V. Watt, A. Karamcheti, M. D. Jackson, and H. R. Huff, Proc. SPIE 4181, 220 (2000).] We show in this letter that nitridation of ISSG oxide using a remote plasma decreases the gate leakage current of ISSG oxide by an order of magnitude without significantly degrading transistor performance. In particular, it is shown that the peak normalized transconductance of n-channel devices with an ISSG oxide gate dielectric decreases by only 4% and the normalized drive current by only 3% after remote plasma nitridation (RPN). In addition, it is shown that the reliability of the ISSG oxide exhibits only a small degradation after RPN. These observations suggest that the ISSG/RPN process holds promise for gate dielectric applications.

  6. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    SciTech Connect

    Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-04-25

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  7. Oxidation differentially modulates the recombinant voltage-gated Na(+) channel α-subunits Nav1.7 and Nav1.8.

    PubMed

    Schlüter, Friederike; Leffler, Andreas

    2016-10-01

    Voltage-gated Na(+) channels regulate neuronal excitability by generating the upstroke of action potentials. The α-subunits Nav1.7 and Nav1.8 are required for normal function of sensory neurons and thus for peripheral pain processing, but also for an increased excitability leading to an increased pain sensitivity under several conditions associated with oxidative stress. While little is known about the direct effects of oxidants on Nav1.7 and Nav1.8, a recent study on mouse dorsal root ganglion neurons suggested that oxidant-induced alterations of nociceptor excitability are primarily driven by Nav1.8. Here we performed whole-cell patch clamp recordings to explore how oxidation modulates functional properties of recombinant Nav1.7 and Nav1.8 channels. The strong oxidant chloramine-T (ChT) at 100 and 500µM induced a shift of the voltage-dependency of activation towards more hyperpolarized potentials. While fast inactivation was stabilized by 100µM ChT, it was partially removed by 500µM ChT on both α-subunits (Nav1.7oxidation promotes gating of Nav1.7 and Nav1.8 by reducing the threshold for activation and by abrogating fast inactivation. The resulting persistent currents are regulated by slow inactivation and appear to be more prominent for Nav1.8 as compared to Nav1.7. Copyright © 2016 Elsevier B.V. All rights reserved.

  8. Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

    NASA Astrophysics Data System (ADS)

    Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

    2012-06-01

    The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

  9. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    NASA Astrophysics Data System (ADS)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  10. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    NASA Astrophysics Data System (ADS)

    Roy, Sukhdev; Yadav, Chandresh

    2013-12-01

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  11. A New Analytical Subthreshold Behavior Model for Single-Halo, Dual-Material Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

    NASA Astrophysics Data System (ADS)

    Chiang, Te-Kuang

    2008-11-01

    On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the single-halo, dual-material gate (SHDMG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is developed. The model is verified by the good agreement with a numerical simulation using the device simulator MEDICI. The model not only offers a physical insight into device physics but is also an efficient device model for the circuit simulation.

  12. Femtosecond all-optical parallel logic gates based on tunable saturable to reverse saturable absorption in graphene-oxide thin films

    SciTech Connect

    Roy, Sukhdev Yadav, Chandresh

    2013-12-09

    A detailed theoretical analysis of ultrafast transition from saturable absorption (SA) to reverse saturable absorption (RSA) has been presented in graphene-oxide thin films with femtosecond laser pulses at 800 nm. Increase in pulse intensity leads to switching from SA to RSA with increased contrast due to two-photon absorption induced excited-state absorption. Theoretical results are in good agreement with reported experimental results. Interestingly, it is also shown that increase in concentration results in RSA to SA transition. The switching has been optimized to design parallel all-optical femtosecond NOT, AND, OR, XOR, and the universal NAND and NOR logic gates.

  13. Electric field-induced transport modulation in VO{sub 2} FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    SciTech Connect

    Wei, Tingting; Kanki, Teruo E-mail: h-tanaka@sanken.osaka-u.ac.jp; Chikanari, Masashi; Tanaka, Hidekazu E-mail: h-tanaka@sanken.osaka-u.ac.jp; Fujiwara, Kohei

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta{sub 2}O{sub 5}/organic parylene-C hybrid dielectric-gated VO{sub 2} thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO{sub 2} through the electrostatic field-induced transport modulation.

  14. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    NASA Astrophysics Data System (ADS)

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-01

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  15. Gate length and temperature dependence of negative differential transconductance in silicon quantum well metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Naquin, Clint; Lee, Mark; Edwards, Hal; Mathur, Guru; Chatterjee, Tathagata; Maggio, Ken

    2015-09-28

    Introducing quantum transport into silicon transistors in a manner compatible with industrial fabrication has the potential to transform the performance horizons of large scale integrated silicon devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) transistors fabricated using industrial silicon complementary metal-oxide-semiconductor processing. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (V{sub G}) spacing between NDTCs. The V{sub G} spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background.

  16. Hypoxic increase in nitric oxide generation of rat sensory neurons requires activation of mitochondrial complex II and voltage-gated calcium channels.

    PubMed

    Henrich, M; Paddenberg, R; Haberberger, R V; Scholz, A; Gruss, M; Hempelmann, G; Kummer, W

    2004-01-01

    Recently, we have demonstrated that sensory neurons of rat lumbar dorsal root ganglia (DRG) respond to hypoxia with an activation of endothelial nitric oxide (NO) synthase (eNOS) resulting in enhanced NO production associated with mitochondria which contributes to resistance against hypoxia. Extracellular calcium is essential to this effect. In the present study on rat DRG slices, we set out to determine what types of calcium channels operate under hypoxia, and which upstream events contribute to their activation, thereby focusing upon mitochondrial complex II. Both the metallic ions Cd2+ and Ni2+, known to inhibit voltage-gated calcium channels and T-type channels, respectively, and verapamil and nifedipine, typical blocker of L-type calcium channels completely prevented the hypoxic neuronal NO generation. Inhibition of complex II by thenoyltrifluoroacetone at the ubiquinon binding site or by 3-nitropropionic acid at the substrate binding site largely diminished hypoxic-induced NO production while having an opposite effect under normoxia. An additional blockade of voltage-gated calcium channels entirely abolished the hypoxic response. The complex II inhibitor malonate inhibited both normoxic and hypoxic NO generation. These data show that complex II activity is required for increased hypoxic NO production. Since succinate dehydrogenase activity of complex II decreased at hypoxia, as measured by histochemistry and densitometry, we propose a hypoxia-induced functional switch of complex II from succinate dehydrogenase to fumarate reductase, which subsequently leads to activation of voltage-gated calcium channels resulting in increased NO production by eNOS.

  17. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO{sub 2} gate dielectrics

    SciTech Connect

    Samanta, Piyas; Huang, Heng-Sheng; Chen, Shuang-Yuan; Liu, Chuan-Hsi; Cheng, Li-Wei

    2014-02-21

    We present a detailed investigation on positive-bias temperature stress (PBTS) induced degradation of nitrided hafnium silicate (HfSiON)/SiO{sub 2} gate stack in n{sup +}-poly crystalline silicon (polySi) gate p-type metal-oxide-semiconductor (pMOS) devices. The measurement results indicate that gate dielectric degradation is a composite effect of electron trapping in as-fabricated as well as newly generated neutral traps, resulting a significant amount of stress-induced leakage current and generation of surface states at the Si/SiO{sub 2} interface. Although, a significant amount of interface states are created during PBTS, the threshold voltage (V{sub T}) instability of the HfSiON based pMOS devices is primarily caused by electron trapping and detrapping. It is also shown that PBTS creates both acceptor- and donor-like interface traps via different depassivation mechanisms of the Si{sub 3} ≡ SiH bonds at the Si/SiO{sub 2} interface in pMOS devices. However, the number of donor-like interface traps ΔN{sub it}{sup D} is significantly greater than that of acceptor-like interface traps ΔN{sup A}{sub it}, resulting the PBTS induced net interface traps as donor-like.

  18. Electron Substrate and Gate Current Modeling for Single-Drain Buried-Channel p-Type Metal-Oxide-Semiconductor Field-Effect Transistors Including Tunneling Mechanisms

    NASA Astrophysics Data System (ADS)

    Sheu, Chorng-Jye

    2008-11-01

    A model of nonlocal electron substrate and gate currents is presented for single-drain (SD) buried-channel (BC) p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs). A nonlocal impact ionization coefficient with characteristic length dependence both in the exponential term and the pre-exponential factor is used in the electron substrate current model. The gate current model is developed by originating a modified lucky electron concept that includes quantum-mechanical tunneling effects in parallel. The channel electric field is first calculated by using an analytical pseudo-two-dimensional MOSFET model, and the spatial distribution of electron temperature along the channel is then derived using a simplified energy balance equation. Having calculated the nonlocal impact ionization coefficient and electron temperature, and modified the lucky electron concept, the nonlocal electron substrate and gate currents can be derived. This model is a time-saving computer-aided-design (CAD) model and is physics transparent for SD BC pMOSFETs.

  19. Reliability and failure modes of implant-supported zirconium-oxide fixed dental prostheses related to veneering techniques

    PubMed Central

    Baldassarri, Marta; Zhang, Yu; Thompson, Van P.; Rekow, Elizabeth D.; Stappert, Christian F. J.

    2011-01-01

    Summary Objectives To compare fatigue failure modes and reliability of hand-veneered and over-pressed implant-supported three-unit zirconium-oxide fixed-dental-prostheses(FDPs). Methods Sixty-four custom-made zirconium-oxide abutments (n=32/group) and thirty-two zirconium-oxide FDP-frameworks were CAD/CAM manufactured. Frameworks were veneered with hand-built up or over-pressed porcelain (n=16/group). Step-stress-accelerated-life-testing (SSALT) was performed in water applying a distributed contact load at the buccal cusp-pontic-area. Post failure examinations were carried out using optical (polarized-reflected-light) and scanning electron microscopy (SEM) to visualize crack propagation and failure modes. Reliability was compared using cumulative-damage step-stress analysis (Alta-7-Pro, Reliasoft). Results Crack propagation was observed in the veneering porcelain during fatigue. The majority of zirconium-oxide FDPs demonstrated porcelain chipping as the dominant failure mode. Nevertheless, fracture of the zirconium-oxide frameworks was also observed. Over-pressed FDPs failed earlier at a mean failure load of 696 ± 149 N relative to hand-veneered at 882 ± 61 N (profile I). Weibull-stress-number of cycles-unreliability-curves were generated. The reliability (2-sided at 90% confidence bounds) for a 400N load at 100K cycles indicated values of 0.84 (0.98-0.24) for the hand-veneered FDPs and 0.50 (0.82-0.09) for their over-pressed counterparts. Conclusions Both zirconium-oxide FDP systems were resistant under accelerated-life-time-testing. Over-pressed specimens were more susceptible to fatigue loading with earlier veneer chipping. PMID:21557985

  20. Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al2O3/InGaAs Gate Stacks.

    PubMed

    Tang, Kechao; Meng, Andrew C; Droopad, Ravi; McIntyre, Paul C

    2016-11-09

    Intentional oxidation of an As2-decapped (100) In0.57Ga0.43As substrate by additional H2O dosing during initial Al2O3 gate dielectric atomic layer deposition (ALD) increases the interface trap density (Dit), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al2O3 dielectric and which is not present without the additional H2O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H2O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al2O3/InGaAs interface display little change (<2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously reported HCl(aq) wet cleaning procedure prior to Al2O3 ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.

  1. Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides

    NASA Astrophysics Data System (ADS)

    Jiao, C.; Ahyi, A. C.; Dhar, S.; Morisette, D.; Myers-Ward, R.

    2017-04-01

    We report results on the interface trap density ( D it) of 4H- and 6H-SiC metal-oxide-semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C- ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C- V- or G- ω-based methods, the C- ψ s method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density ( N it) integrated from the C- ψ s method is several times that obtained from the high-low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal-oxide-semiconductor field-effect transistor (MOSFET) channels.

  2. Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors

    NASA Astrophysics Data System (ADS)

    Chen, Jone F.; Chang, Chun-Po; Liu, Yu Ming; Tsai, Yan-Lin; Hsu, Hao-Tang; Chen, Chih-Yuan; Hwang, Hann-Ping

    2016-01-01

    In this study, off-state breakdown voltage (VBD) and hot-carrier-induced degradation in high-voltage n-type metal-oxide-semiconductor transistors with various BF2 implantation doses in the n- drift region are investigated. Results show that a higher BF2 implantation dose results in a higher VBD but leads to a greater hot-carrier-induced device degradation. Experimental data and technology computer-aided design simulations suggest that the higher VBD is due to the suppression of gate-induced drain current. On the other hand, the greater hot-carrier-induced device degradation can be explained by a lower net donor concentration and a different current-flow path, which is closer to the Si-SiO2 interface.

  3. 20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF SUBMERSIBLE GATE, SHOWING GATE ARMS, GATE PIERS, TRUNNION PIN AND GATE GAUGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  4. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN, PIER AND GATE GAUGE, LOOKING EAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 10, Guttenberg, Clayton County, IA

  5. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, WITH ROLLER GATE HEADHOUSE IN BACKGROUND, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  6. 17. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS, GATE CHAINS AND SWITCHES, AND BRIDGE GIRDERS, LOOKING SOUTHWEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  7. 18. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS, GATE CHAINS AND SWITCHES, AND BRIDGE GIRDERS, LOOKING NORTHWEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  8. Hafnium zirconate gate dielectric for advanced gate stack applications

    NASA Astrophysics Data System (ADS)

    Hegde, R. I.; Triyoso, D. H.; Samavedam, S. B.; White, B. E.

    2007-04-01

    We report on the development of a hafnium zirconate (HfZrO4) alloy gate dielectric for advanced gate stack applications. The HfZrO4 and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. The HfZrO4 material properties were examined and compared with those of HfO2 by a wide variety of analytical methods. The dielectric properties, device performance, and reliability of HfZrO4 were investigated by fabricating HfZrO4/tantalum carbide (TaxCy) metal-oxide-semiconductor field effect transistor. The HfZrO4 dielectric film has smaller band gap, smaller and more uniform grains, less charge traps, and more uniform film quality than HfO2. The HfZrO4 dielectric films exhibited good thermal stability with silicon. Compared to HfO2, the HfZrO4 gate dielectric showed lower capacitance equivalent thickness value, higher transconductance, less charge trapping, higher drive current, lower threshold voltage (Vt), reduced capacitance-voltage (C-V ) hysteresis, lower interface state density, superior wafer level thickness uniformity, and longer positive bias temperature instability lifetime. Incorporation of zirconium dioxide (ZrO2) into HfO2 enhances the dielectric constant (k ) of the resulting HfZrO4 which is associated with structural phase transformation from mainly monoclinic to tetragonal. The tetragonal phase increases the k value of HfZrO4 dielectric to a large value as predicted. The improved device characteristics are attributed to less oxygen vacancy in the fine grained microstructure of HfZrO4 films.

  9. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper.

  10. Fabrication of a metal-oxide-semiconductor-type capacitive microtip array using SiO2 or HfO2 gate insulators

    NASA Astrophysics Data System (ADS)

    Kim, Kyung-Min; Choi, Byung Joon; Kim, Seong Keun; Hwang, Cheol Seong

    2004-11-01

    Capacitive tip arrays having a metal-insulator-semiconductor capacitor structure were fabricated using thermally oxidized SiO2 or atomic-layer-deposited HfO2 gate dielectric films for their application to scanning-probe-array-type memory devices. The SiO2 film showed a nonuniform thickness distribution over the flat and tip areas of the arrays owing to the different oxidation speeds of the flat and tip Si surfaces. This resulted in a smaller sensing margin of the device. However, the high-dielectric HfO2 film showed not only a higher capacitance value but also a more uniform growth behavior over the whole area, which would result in a better device performance. The capacitance-voltage characteristics of both devices coincide well with the simulation results based on conventional metal-insulator-semiconductor theories.

  11. Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

    NASA Astrophysics Data System (ADS)

    Medury, Aditya Sankar; Bhat, K. N.; Bhat, Navakanta

    2012-07-01

    We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (Vth) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φc) saturates to Φc(sat), and analyze the effects of oxide thickness (tox) and substrate doping (NA) variations on Vth. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed Vth definition, electrically corresponds to a condition where the inversion layer capacitance (Cinv) is equal to the oxide capacitance (Cox) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria Cinv=Cox is proposed to compute Φc(sat), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth ("x") of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film.

  12. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    SciTech Connect

    Han, Bin Takamizawa, Hisashi Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-13

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  13. Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

    NASA Astrophysics Data System (ADS)

    Han, Bin; Takamizawa, Hisashi; Shimizu, Yasuo; Inoue, Koji; Nagai, Yasuyoshi; Yano, Fumiko; Kunimune, Yorinobu; Inoue, Masao; Nishida, Akio

    2015-07-01

    The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

  14. Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

    PubMed

    Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

    2017-03-01

    For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm(2)), insulating property (leakage current densities <10(-7) A/cm(2)), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

  15. Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal-oxide-silicon field effect transistors

    NASA Astrophysics Data System (ADS)

    Jin, Xiaoshi; Liu, Xi; Lee, Jung-Hee; Lee, Jong-Ho

    2014-01-01

    A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement.

  16. Reliability of proton NMR spectroscopy for the assessment of frying oil oxidation

    USDA-ARS?s Scientific Manuscript database

    Although there are many analytical methods developed to assess oxidation of edible oil, it is still common to see a lack of consistency in results from different methods. This inconsistency is expected since there are numerous oxidation products and any analytical method measuring only one kind of o...

  17. Effect of Remote Surface Optical Phonon Scattering in Graphene Gated by Single Crystal Ferroelectric Oxide Thin Films

    NASA Astrophysics Data System (ADS)

    Xiao, Zhiyong; Rajapitamahuni, Anil; Schoeche, Stefan; Hoffman, Jason; Ahn, Charles; Schubert, Mathias; Hong, Xia

    2014-03-01

    We have studied the effect of remote surface optical (RSO) phonon on the carrier mobility in graphene gated by a ferroelectric Ba0.6Sr0.4TiO3 (BSTO) substrate. Single crystal 100-400nm BSTO films are grown epitaxially on Nb doped SrTiO3 substrates. Graphene flakes are mechanically exfoliated onto BSTO and single and bi-layer flakes are fabricated into field effect devices via e-beam lithography. All samples exhibit resistivity hysteresis induced by ferroelectric switching at low temperature, which can be used for nonvolatile memory operations. Single layer graphene exhibits high mobility with μHall ~ 10,000 cm2/Vs at carrier density of 3.5x1012 cm-2 at 10K. Above 80K, We observe a sharp rise in resistivity as a function of temperature ρ(T), which is attributed to the RSO phonon scattering form the BSTO gate. We have extracted the dominant RSO phonon mode from ρ(T) and compared it with results extracted from independent spectroscopic ellipsometry measurements. We will also discuss the temperature dependence of resistivity in bi-layer graphene gated by BSTO.

  18. Characterization of ALD Beryllium Oxide as a Potential High- k Gate Dielectric for Low-Leakage AlGaN/GaN MOSHEMTs

    NASA Astrophysics Data System (ADS)

    Johnson, Derek W.; Yum, Jung Hwan; Hudnall, Todd W.; Mushinski, Ryan M.; Bielawski, Christopher W.; Roberts, John C.; Wang, Wei-E.; Banerjee, Sanjay K.; Harris, H. Rusty

    2014-01-01

    The chemical and electrical characteristics of atomic layer deposited (ALD) beryllium oxide (BeO) on GaN were studied via x-ray photoelectron spectroscopy, current-voltage, and capacitance-voltage measurements and compared with those of ALD Al2O3 and HfO2 on GaN. Radiofrequency (RF) and power electronics based on AlGaN/GaN high-electron-mobility transistors are maturing rapidly, but leakage current reduction and interface defect ( D it) minimization remain heavily researched. BeO has received recent attention as a high- k gate dielectric due to its large band gap (10.6 eV) and thermal stability on InGaAs and Si, but little is known about its performance on GaN. Unintentionally doped GaN was cleaned in dilute aqueous HCl immediately prior to BeO deposition (using diethylberyllium and H2O precursors). Formation of an interfacial layer was observed in as-deposited samples, similar to the layer formed during ALD HfO2 deposition on GaN. Postdeposition anneal (PDA) at 700°C and 900°C had little effect on the observed BeO binding state, confirming the strength of the bond, but led to increased Ga oxide formation, indicating the presence of unincorporated oxygen in the dielectric. Despite the interfacial layer, gate leakage current of 1.1 × 10-7 A/cm2 was realized, confirming the potential of ALD BeO for use in low-leakage AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors.

  19. Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal-Oxide-Semiconductor Technology

    NASA Astrophysics Data System (ADS)

    Han, Jin-Ping; Shimizu, Takashi; Pan, Li-Hong; Voelker, Moritz; Bernicot, Christophe; Arnaud, Franck; Mocuta, Anda; Stahrenberg, Knut; Azuma, Atsushi; Eller, Manfred; Yang, Guoyong; Jaeger, Daniel; Zhuang, Haoren; Miyashita, Katsura; Stein, Kenneth; Nair, Deleep; Hoo Park, Jae; Kohler, Sabrina; Hamaguchi, Masafumi; Li, Weipeng; Kim, Kisang; Chanemougame, Daniel; Kim, Nam Sung; Uchimura, Sadaharu; Tsutsui, Gen; Wiedholz, Christian; Miyake, Shinich; van Meer, Hans; Liang, Jewel; Ostermayr, Martin; Lian, Jenny; Celik, Muhsin; Donaton, Ricardo; Barla, Kathy; Na, MyungHee; Goto, Yoshiro; Sherony, Melanie; Johnson, Frank S.; Wachnik, Richard; Sudijono, John; Kaste, Ed; Sampson, Ron; Ku, Ja-Hum; Steegen, An; Neumueller, Walter

    2011-04-01

    High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance Gm, conductance Gds, Gm/Id, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., Ion-Ioff, Ioff-Vtsat, DIBL, Cjswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

  20. 100-nm gate lithography for double-gate transistors

    NASA Astrophysics Data System (ADS)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  1. Ratiometric Time-Gated Luminescence Probe for Nitric Oxide Based on an Apoferritin-Assembled Lanthanide Complex-Rhodamine Luminescence Resonance Energy Transfer System.

    PubMed

    Tian, Lu; Dai, Zhichao; Liu, Xiangli; Song, Bo; Ye, Zhiqiang; Yuan, Jingli

    2015-11-03

    Using apoferritin (AFt) as a carrier, a novel ratiometric luminescence probe based on luminescence resonance energy transfer (LRET) between a Tb(3+) complex (PTTA-Tb(3+)) and a rhodamine derivative (Rh-NO), PTTA-Tb(3+)@AFt-Rh-NO, has been designed and prepared for the specific recognition and time-gated luminescence detection of nitric oxide (NO) in living samples. In this LRET probe, PTTA-Tb(3+) encapsulated in the core of AFt is the energy donor, and Rh-NO, a NO-responsive rhodamine derivative, bound on the surface of AFt is the energy acceptor. The probe only emits strong Tb(3+) luminescence because the emission of rhodamine is switched off in the absence of NO. Upon reaction with NO, accompanied by the turn-on of rhodamine emission, the LRET from Tb(3+) complex to rhodamine occurs, which results in the remarkable increase and decrease of the long-lived emissions of rhodamine and PTTA-Tb(3+), respectively. After the reaction, the intensity ratio of rhodamine emission to Tb(3+) emission, I565/I539, is ∼24.5-fold increased, and the dose-dependent enhancement of I565/I539 shows a good linearity in a wide concentration range of NO. This unique luminescence response allowed PTTA-Tb(3+)@AFt-Rh-NO to be conveniently used as a ratiometric probe for the time-gated luminescence detection of NO with I565/I539 as a signal. Taking advantages of high specificity and sensitivity of the probe as well as its good water-solubility, biocompatibility, and cell membrane permeability, PTTA-Tb(3+)@AFt-Rh-NO was successfully used for the luminescent imaging of NO in living cells and Daphnia magna. The results demonstrated the efficacy of the probe and highlighted it's advantages for the ratiometric time-gated luminescence bioimaging application.

  2. Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET Using Defect-Free Gate Recess and Laser Annealing

    DTIC Science & Technology

    2012-07-18

    For AlGaN, it is found that Al2O3, Ga2O3 and N-O states were detected on native oxide and HF-treated surfaces. During the course of the ALD process...the N-O bonds are seen to decrease to a level near XPS detection limits, as well as a small decrease in the Ga2O3 concentration, consistent with a...and the other at 1118.2 eV, indicative of a Ga 3+ oxidation state, likely due to Ga2O3 , consistent with previous reports.22,23 There is no evidence

  3. Oxidization of squalene, a human skin lipid: a new and reliable marker of environmental pollution studies.

    PubMed

    Pham, D-M; Boussouira, B; Moyal, D; Nguyen, Q L

    2015-08-01

    A review of the oxidization of squalene, a specific human compound produced by the sebaceous gland, is proposed. Such chemical transformation induces important consequences at various levels. Squalene by-products, mostly under peroxidized forms, lead to comedogenesis, contribute to the development of inflammatory acne and possibly modify the skin relief (wrinkling). Experimental conditions of oxidation and/or photo-oxidation mechanisms are exposed, suggesting that they could possibly be bio-markers of atmospheric pollution upon skin. Ozone, long UVA rays, cigarette smoke… are shown powerful oxidizing agents of squalene. Some in vitro, ex vivo and in vivo testings are proposed as examples, aiming at studying ingredients or products capable of boosting or counteracting such chemical changes that, globally, bring adverse effects to various cutaneous compartments.

  4. Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

    SciTech Connect

    Yang, Xu; Zeng, Zhen-Hua; Wang, Sheng-Kai E-mail: xzhang62@aliyun.com Sun, Bing; Zhao, Wei; Chang, Hu-Dong; Liu, Honggang E-mail: xzhang62@aliyun.com; Zhang, Xiong E-mail: xzhang62@aliyun.com

    2014-09-01

    Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

  5. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating.

    PubMed

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Tan, Leng Seow

    2015-09-14

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement.

  6. AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor with Polarized P(VDF-TrFE) Ferroelectric Polymer Gating

    PubMed Central

    Liu, Xinke; Lu, Youming; Yu, Wenjie; Wu, Jing; He, Jiazhu; Tang, Dan; Liu, Zhihong; Somasuntharam, Pannirselvam; Zhu, Deliang; Liu, Wenjun; Cao, Peijiang; Han, Sun; Chen, Shaojun; Seow Tan, Leng

    2015-01-01

    Effect of a polarized P(VDF-TrFE) ferroelectric polymer gating on AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) was investigated. The P(VDF-TrFE) gating in the source/drain access regions of AlGaN/GaN MOS-HEMTs was positively polarized (i.e., partially positively charged hydrogen were aligned to the AlGaN surface) by an applied electric field, resulting in a shift-down of the conduction band at the AlGaN/GaN interface. This increases the 2-dimensional electron gas (2-DEG) density in the source/drain access region of the AlGaN/GaN heterostructure, and thereby reduces the source/drain series resistance. Detailed material characterization of the P(VDF-TrFE) ferroelectric film was also carried out using the atomic force microscopy (AFM), X-ray Diffraction (XRD), and ferroelectric hysteresis loop measurement. PMID:26364872

  7. Optimization of a Solution-Processed SiO2 Gate Insulator by Plasma Treatment for Zinc Oxide Thin Film Transistors.

    PubMed

    Jeong, Yesul; Pearson, Christopher; Kim, Hyun-Gwan; Park, Man-Young; Kim, Hongdoo; Do, Lee-Mi; Petty, Michael C

    2016-01-27

    We report on the optimization of the plasma treatment conditions for a solution-processed silicon dioxide gate insulator for application in zinc oxide thin film transistors (TFTs). The SiO2 layer was formed by spin coating a perhydropolysilazane (PHPS) precursor. This thin film was subsequently thermally annealed, followed by exposure to an oxygen plasma, to form an insulating (leakage current density of ∼10(-7) A/cm(2)) SiO2 layer. Optimized ZnO TFTs (40 W plasma treatment of the gate insulator for 10 s) possessed a carrier mobility of 3.2 cm(2)/(V s), an on/off ratio of ∼10(7), a threshold voltage of -1.3 V, and a subthreshold swing of 0.2 V/decade. In addition, long-term exposure (150 min) of the pre-annealed PHPS to the oxygen plasma enabled the maximum processing temperature to be reduced from 180 to 150 °C. The resulting ZnO TFT exhibited a carrier mobility of 1.3 cm(2)/(V s) and on/off ratio of ∼10(7).

  8. Properties of c-axis-aligned crystalline indium-gallium-zinc oxide field-effect transistors fabricated through a tapered-trench gate process

    NASA Astrophysics Data System (ADS)

    Asami, Yoshinobu; Kurata, Motomu; Okazaki, Yutaka; Higa, Eiji; Matsubayashi, Daisuke; Okamoto, Satoru; Sasagawa, Shinya; Moriwaka, Tomoaki; Kakehata, Tetsuya; Yakubo, Yuto; Kato, Kiyoshi; Hamada, Takashi; Sakakura, Masayuki; Hayakawa, Masahiko; Yamazaki, Shunpei

    2016-04-01

    To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO (\\text{In}:\\text{Ga}:\\text{Zn} = 1:1:1 in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10-16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

  9. The role of the substrate on the dispersion in accumulation in III-V compound semiconductor based metal-oxide-semiconductor gate stacks

    SciTech Connect

    Krylov, Igor; Ritter, Dan; Eizenberg, Moshe

    2015-09-07

    Dispersion in accumulation is a widely observed phenomenon in metal-oxide-semiconductor gate stacks based on III-V compound semiconductors. The physical origin of this phenomenon is attributed to border traps located in the dielectric material adjacent to the semiconductor. Here, we study the role of the semiconductor substrate on the electrical quality of the first layers at atomic layer deposited (ALD) dielectrics. For this purpose, either Al{sub 2}O{sub 3} or HfO{sub 2} dielectrics with variable thicknesses were deposited simultaneously on two technology important semiconductors—InGaAs and InP. Significantly larger dispersion was observed in InP based gate stacks compared to those based on InGaAs. The observed difference is attributed to a higher border trap density in dielectrics deposited on InP compared to those deposited on InGaAs. We therefore conclude that the substrate plays an important role in the determination of the electrical quality of the first dielectric monolayers deposited by ALD. An additional observation is that larger dispersion was obtained in HfO{sub 2} based capacitors compared to Al{sub 2}O{sub 3} based capacitors, deposited on the same semiconductor. This phenomenon is attributed to the lower conduction band offset rather than to a higher border trap density.

  10. Comparison between chemical vapor deposited and physical vapor deposited WSi{sub 2} metal gate for InGaAs n-metal-oxide-semiconductor field-effect transistors

    SciTech Connect

    Ong, B. S.; Pey, K. L.; Ong, C. Y.; Tan, C. S.; Antoniadis, D. A.; Fitzgerald, E. A.

    2011-05-02

    We compare chemical vapor deposition (CVD) and physical vapor deposition (PVD) WSi{sub 2} metal gate process for In{sub 0.53}Ga{sub 0.47}As n-metal-oxide-semiconductor field-effect transistors using 10 and 6.5 nm Al{sub 2}O{sub 3} as dielectric layer. The CVD-processed metal gate device with 6.5 nm Al{sub 2}O{sub 3} shows enhanced transistor performance such as drive current, maximum transconductance and maximum effective mobility. These values are relatively better than the PVD-processed counterpart device with improvement of 51.8%, 46.4%, and 47.8%, respectively. The improvement for the performance of the CVD-processed metal gate device is due to the fluorine passivation at the oxide/semiconductor interface and a nondestructive deposition process.

  11. Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers.

    PubMed

    Wang, Lin; Chen, Xiaolong; Wang, Yang; Wu, Zefei; Li, Wei; Han, Yu; Zhang, Mingwei; He, Yuheng; Zhu, Chao; Fung, Kwok Kwong; Wang, Ning

    2013-02-07

    We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers.

  12. Dual-Gate Modulation of Carrier Density and Disorder in an Oxide Two-Dimensional Electron System

    SciTech Connect

    Chen, Zhuoyu; Yuan, Hongtao; Xie, Yanwu; Lu, Di; Inoue, Hisashi; Hikita, Yasuyuki; Bell, Christopher; Hwang, Harold Y.

    2016-09-08

    Carrier density and disorder are two crucial parameters that control the properties of correlated two-dimensional electron systems. Furthermore, in order to disentangle their individual contributions to quantum phenomena, independent tuning of these two parameters is required. By utilizing a hybrid liquid/solid electric dual-gate geometry acting on the conducting LaAlO3/SrTiO3 heterointerface, we obtain an additional degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independent from the carrier density. A dual-gate controlled nonlinear Hall effect is a direct manifestation of this profile, which can be quantitatively understood by a Poisson–Schrödinger sub-band model. In particular, the large nonlinear dielectric response of SrTiO3 enables a very wide range of tunable density and disorder, far beyond that for conventional semiconductors. This study provides a broad framework for understanding various reported phenomena at the LaAlO3/SrTiO3 interface.

  13. Dual-Gate Modulation of Carrier Density and Disorder in an Oxide Two-Dimensional Electron System

    DOE PAGES

    Chen, Zhuoyu; Yuan, Hongtao; Xie, Yanwu; ...

    2016-09-08

    Carrier density and disorder are two crucial parameters that control the properties of correlated two-dimensional electron systems. Furthermore, in order to disentangle their individual contributions to quantum phenomena, independent tuning of these two parameters is required. By utilizing a hybrid liquid/solid electric dual-gate geometry acting on the conducting LaAlO3/SrTiO3 heterointerface, we obtain an additional degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independent from the carrier density. A dual-gate controlled nonlinear Hall effect is a direct manifestation of this profile, which can be quantitatively understood by a Poisson–Schrödinger sub-band model. Inmore » particular, the large nonlinear dielectric response of SrTiO3 enables a very wide range of tunable density and disorder, far beyond that for conventional semiconductors. This study provides a broad framework for understanding various reported phenomena at the LaAlO3/SrTiO3 interface.« less

  14. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    SciTech Connect

    Tari, Alireza Lee, Czang-Ho; Wong, William S.

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  15. Dual-Gate Modulation of Carrier Density and Disorder in an Oxide Two-Dimensional Electron System

    SciTech Connect

    Chen, Zhuoyu; Yuan, Hongtao; Xie, Yanwu; Lu, Di; Inoue, Hisashi; Hikita, Yasuyuki; Bell, Christopher; Hwang, Harold Y.

    2016-09-08

    Carrier density and disorder are two crucial parameters that control the properties of correlated two-dimensional electron systems. Furthermore, in order to disentangle their individual contributions to quantum phenomena, independent tuning of these two parameters is required. By utilizing a hybrid liquid/solid electric dual-gate geometry acting on the conducting LaAlO3/SrTiO3 heterointerface, we obtain an additional degree of freedom to strongly modify the electron confinement profile and thus the strength of interfacial scattering, independent from the carrier density. A dual-gate controlled nonlinear Hall effect is a direct manifestation of this profile, which can be quantitatively understood by a Poisson–Schrödinger sub-band model. In particular, the large nonlinear dielectric response of SrTiO3 enables a very wide range of tunable density and disorder, far beyond that for conventional semiconductors. This study provides a broad framework for understanding various reported phenomena at the LaAlO3/SrTiO3 interface.

  16. GATED PORES IN THE FERRITIN PROTEIN NANOCAGE

    PubMed Central

    Theil, Elizabeth C.; Liu, Xiaofeng S.; Tosha, Takehiko

    2008-01-01

    Synopsis and pictogram: Gated pores in the ferritin family of protein nanocages, illustrated in the pictogram, control transfer of ferrous iron into and out of the cages by regulating contact between hydrated ferric oxide mineral inside the protein cage, and reductants such as FMNH2 on the outside. The structural and functional homology between the gated ion channel proteins in inaccessible membranes and gated ferritin pores in the stable, water soluble nanoprotein, make studies of ferritin pores models for gated pores in many ion channel proteins. Properties of ferritin gated pores, which control rates of FMNH2 reduction of ferric iron in hydrated oxide minerals inside the protein nanocage, are discussed in terms of the conserved pore gate residues (arginine 72-apspartate 122 and leucine 110-leucine 134), of pore sensitivity to heat at temperatures 30 °C below that of the nanocage itself, and of pore sensitivity to physiological changes in urea (1–10 mM). Conditions which alter ferritin pore structure/function in solution, coupled with the high evolutionary conservation of the pore gates, suggest the presence of molecular regulators in vivo that recognize the pore gates and hold them either closed or open, depending on biological iron need. The apparent homology between ferrous ion transport through gated pores in the ferritin nanocage and ion transport through gated pores in ion channel proteins embedded in cell membranes, make studies of water soluble ferritin and the pore gating folding/unfolding a useful model for other gated pores. PMID:19262678

  17. Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Gu, J. J.; Wu, Y. Q.; Ye, P. D.

    2011-03-01

    Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III-V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III-V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGaAs MOSFET without sulfur passivation, featuring optimized threshold voltage and negligible off-state degradation.

  18. 16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE, GATE ARM, TRUNNION PIN AND PIER, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  19. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATES, GATE ARMS, PIERS AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  20. Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides

    NASA Astrophysics Data System (ADS)

    Lai, Kafai; Hao, Ming-Yin; Chen, Wei-Ming; Lee, Jack C.

    1994-09-01

    A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (oxides (48 angstrom) and oxynitrides grown in N2O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

  1. High-performance bottom-gate poly-Si polysilicon-oxide-nitride-oxide-silicon thin film transistors crystallized by excimer laser irradiation for two-bit nonvolatile memory applications.

    PubMed

    Lee, I-Che; Kuo, Hsu-Hang; Tsai, Chun-Chien; Wang, Chao-Lung; Yang, Po-Yu; Wang, Jyh-Liang; Cheng, Huang-Chung

    2012-07-01

    High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm2/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.

  2. Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

    NASA Astrophysics Data System (ADS)

    Han, In-Shik; Kwon, Hyuk-Min; Bok, Jung-Deuk; Kwon, Sung-Kyu; Jung, Yi-Jung; Choi, Woon-il; Choi, Deuk-Sung; Lim, Min-Gyu; Chung, Yi-Sun; Lee, Jung-Hwan; Lee, Ga-Won; Lee, Hi-Deok

    2011-10-01

    In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID-RTS) noise shows similar values (70-78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

  3. Retention and switching kinetics of protonated gate field effect transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-05-23

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETS containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96{percent} after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  4. Retention and Switching Kinetics of Protonated Gate Field Effect Transistors

    SciTech Connect

    DEVINE,R.A.B.; HERRERA,GILBERT V.

    2000-06-27

    The switching and memory retention time has been measured in 50 {micro}m gatelength pseudo-non-volatile memory MOSFETs containing, protonated 40 nm gate oxides. Times of the order of 3.3 seconds are observed for fields of 3 MV cm{sup {minus}1}. The retention time with protons placed either at the gate oxide/substrate or gate oxide/gate electrode interfaces is found to better than 96% after 5,000 seconds. Measurement of the time dependence of the source-drain current during switching provides clear evidence for the presence of dispersive proton transport through the gate oxide.

  5. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  6. Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

    SciTech Connect

    Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio

    2016-07-04

    This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

  7. Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors

    NASA Astrophysics Data System (ADS)

    Kwon, Jang Yeon; Kyeong Jeong, Jae

    2015-02-01

    This review gives an overview of the recent progress in vacuum-based n-type transition metal oxide (TMO) thin film transistors (TFTs). Several excellent review papers regarding metal oxide TFTs in terms of fundamental electron structure, device process and reliability have been published. In particular, the required field-effect mobility of TMO TFTs has been increasing rapidly to meet the demands of the ultra-high-resolution, large panel size and three dimensional visual effects as a megatrend of flat panel displays, such as liquid crystal displays, organic light emitting diodes and flexible displays. In this regard, the effects of the TMO composition on the performance of the resulting oxide TFTs has been reviewed, and classified into binary, ternary and quaternary composition systems. In addition, the new strategic approaches including zinc oxynitride materials, double channel structures, and composite structures have been proposed recently, and were not covered in detail in previous review papers. Special attention is given to the advanced device architecture of TMO TFTs, such as back-channel-etch and self-aligned coplanar structure, which is a key technology because of their advantages including low cost fabrication, high driving speed and unwanted visual artifact-free high quality imaging. The integration process and related issues, such as etching, post treatment, low ohmic contact and Cu interconnection, required for realizing these advanced architectures are also discussed.

  8. Short-Term Ketamine Treatment Decreases Oxidative Stress Without Influencing TRPM2 and TRPV1 Channel Gating in the Hippocampus and Dorsal Root Ganglion of Rats.

    PubMed

    Demirdaş, Arif; Nazıroğlu, Mustafa; Övey, Ishak Suat

    2017-01-01

    Calcium ions (Ca(2+)) are important second messengers in neurons. Ketamine (KETAM) is an anesthetic and analgesic, with psychotomimetic effects and abuse potential. KETAM modulates the entry of Ca(2+) in neurons through glutamate receptors, but its effect on transient receptor potential melastatin 2 (TRPM2) and transient receptor potential vanilloid 1 (TRPV1) channels has not been clarified. This study investigated the short-term effects of KETAM on oxidative stress and TRPM2 and TRPV1 channel gating in hippocampal and dorsal root ganglion (DRG) neurons of rats. Freshly isolated hippocampal and DRG neurons were incubated for 24 h with KETAM (0.3 mM). The TRPM2 channel antagonist, N-(p-amylcinnamoyl)anthranilic acid (ACA), inhibited cumene hydroperoxide and ADP-ribose-induced TRPM2 currents in the neurons, and capsazepine (CPZ) inhibited capsaicin-induced TRPV1 currents. The TRPM2 and TRPV1 channel current densities and intracellular free calcium ion concentration of the neurons were lower in the neurons exposed to ACA and CPZ compared to the control neurons, respectively. However, the values were not further decreased by the KETAM + CPZ and KETAM + ACA treatments. KETAM decreased lipid peroxidation levels in the neurons but increased glutathione peroxidase activity. In conclusion, short-term KETAM treatment decreased oxidative stress levels but did not seem to influence TRPM2- and TRPV1-mediated Ca(2+) entry.

  9. Reliability of fast reactor mixed-oxide fuel during operational transients

    SciTech Connect

    Boltax, A.; Neimark, L.A.; Tsai, Hanchung ); Katsuragawa, M.; Shikakura, S. . Oarai Engineering Center)

    1991-07-01

    Results are presented from the cooperative DOE and PNC Phase 1 and 2 operational transient testing programs conducted in the EBR-2 reactor. The program includes second (D9 and PNC 316 cladding) and third (FSM, AST and ODS cladding) generation mixed-oxide fuel pins. The irradiation tests include duty cycle operation and extended overpower tests. the results demonstrate the capability of second generation fuel pins to survive a wide range of duty cycle and extended overpower events. 15 refs., 9 figs., 4 tabs.

  10. A reliable extraction method for source and drain series resistances in silicon nanowire metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on radio-frequency analysis.

    PubMed

    Hwa, Jae Hwa; Yoon, Young Jun; Lee, Hwan Gi; Yoo, Gwan Min; Cho, Eou-Sik; Cho, Seongjae; Lee, Jung-Hee; Kang, In Man

    2014-11-01

    This paper presents a new extraction method for source and drain (S/D) series resistances of silicon nanowire (SNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on small-signal radio-frequency (RF) analysis. The proposed method can be applied to the extraction of S/D series resistances for SNW MOSFETs with finite off-state channel resistance as well as gate bias-dependent on-state resistive components realized by 3-dimensional (3-D) device simulation. The series resistances as a function of frequency and gate voltage are presented and compared with the results obtained by an existing method with infinite off-state channel resistance model. The accuracy of the newly proposed parameter extraction method has been successfully verified by Z22- and Y-parameters up to 100 GHz operation frequency.

  11. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

    NASA Astrophysics Data System (ADS)

    Flewitt, A. J.; Powell, M. J.

    2014-04-01

    It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 106-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions

  12. Automatically closing swing gate closure assembly

    DOEpatents

    Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

    1988-01-01

    A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

  13. Electrostatic Gating of Ultrathin Films

    NASA Astrophysics Data System (ADS)

    Goldman, A. M.

    2014-07-01

    Electrostatic gating of ultrathin films can be used to modify electronic and magnetic properties of materials by effecting controlled alterations of carrier concentration while, in principle, not changing the level of disorder. As such, electrostatic gating can facilitate the development of novel devices and can serve as a means of exploring the fundamental properties of materials in a manner far simpler than is possible with the conventional approach of chemical doping. The entire phase diagram of a compound can be traversed by changing the gate voltage. In this review, we survey results involving conventional field effect devices as well as more recent progress, which has involved structures that rely on electrochemical configurations such as electric double-layer transistors. We emphasize progress involving thin films of oxide materials such as high-temperature superconductors, magnetic oxides, and oxides that undergo metal-insulator transitions.

  14. Ceramic bearing development. Silicon nitride bearing balls of improved reliability: Thermal oxidation. Final report, 1 January 1995-31 October 1996

    SciTech Connect

    Burk, C.B.

    1996-11-01

    The major objective of this work was to improve the reliability of silicon nitride bearing balls by means of an optimized thermal oxidation treatment. Previous work had shown that the thermal fracture resistance of silicon nitride bearing balls increased when the balls were heated and oxidized in air. An optimized oxidation treatment for NBD-200 silicon nitride balls was developed, using a thermal proof test matrix. This oxidation treatment increased the thermal fracture resistance of the balls. Ball-on-rod RCF testing of oxidized and non-oxidized balls was performed at 786 KSI contact stress, with nitrided M50-NIL rods. RCF testing did not produce a significant percentage of ball failures for either the oxidized or non-oxidized condition. Alternative methods, such as four ball fatigue testing, should be considered for future work. The oxidation treatment degraded ball surface and geometry, and is suspected as a contributing factor to short rod life. Oxidation treatment does not appear to be a useful technique for improving the reliability of NBD-200 bearing balls.

  15. The Reliability and Predictive Ability of a Biomarker of Oxidative DNA Damage on Functional Outcomes after Stroke Rehabilitation

    PubMed Central

    Hsieh, Yu-Wei; Lin, Keh-Chung; Korivi, Mallikarjuna; Lee, Tsong-Hai; Wu, Ching-Yi; Wu, Kuen-Yuh

    2014-01-01

    We evaluated the reliability of 8-hydroxy-2′-deoxyguanosine (8-OHdG), and determined its ability to predict functional outcomes in stroke survivors. The rehabilitation effect on 8-OHdG and functional outcomes were also assessed. Sixty-one stroke patients received a 4-week rehabilitation. Urinary 8-OHdG levels were determined by liquid chromatography–tandem mass spectrometry. The test-retest reliability of 8-OHdG was good (interclass correlation coefficient = 0.76). Upper-limb motor function and muscle power determined by the Fugl-Meyer Assessment (FMA) and Medical Research Council (MRC) scales before rehabilitation showed significant negative correlation with 8-OHdG (r = −0.38, r = −0.30; p < 0.05). After rehabilitation, we found a fair and significant correlation between 8-OHdG and FMA (r = −0.34) and 8-OHdG and pain (r = 0.26, p < 0.05). Baseline 8-OHdG was significantly correlated with post-treatment FMA, MRC, and pain scores (r = −0.34, −0.31, and 0.25; p < 0.05), indicating its ability to predict functional outcomes. 8-OHdG levels were significantly decreased, and functional outcomes were improved after rehabilitation. The exploratory study findings conclude that 8-OHdG is a reliable and promising biomarker of oxidative stress and could be a valid predictor of functional outcomes in patients. Monitoring of behavioral indicators along with biomarkers may have crucial benefits in translational stroke research. PMID:24743892

  16. The reliability and predictive ability of a biomarker of oxidative DNA damage on functional outcomes after stroke rehabilitation.

    PubMed

    Hsieh, Yu-Wei; Lin, Keh-Chung; Korivi, Mallikarjuna; Lee, Tsong-Hai; Wu, Ching-Yi; Wu, Kuen-Yuh

    2014-04-16

    We evaluated the reliability of 8-hydroxy-2'-deoxyguanosine (8-OHdG), and determined its ability to predict functional outcomes in stroke survivors. The rehabilitation effect on 8-OHdG and functional outcomes were also assessed. Sixty-one stroke patients received a 4-week rehabilitation. Urinary 8-OHdG levels were determined by liquid chromatography-tandem mass spectrometry. The test-retest reliability of 8-OHdG was good (interclass correlation coefficient=0.76). Upper-limb motor function and muscle power determined by the Fugl-Meyer Assessment (FMA) and Medical Research Council (MRC) scales before rehabilitation showed significant negative correlation with 8-OHdG (r=-0.38, r=-0.30; p<0.05). After rehabilitation, we found a fair and significant correlation between 8-OHdG and FMA (r=-0.34) and 8-OHdG and pain (r=0.26, p<0.05). Baseline 8-OHdG was significantly correlated with post-treatment FMA, MRC, and pain scores (r=-0.34, -0.31, and 0.25; p<0.05), indicating its ability to predict functional outcomes. 8-OHdG levels were significantly decreased, and functional outcomes were improved after rehabilitation. The exploratory study findings conclude that 8-OHdG is a reliable and promising biomarker of oxidative stress and could be a valid predictor of functional outcomes in patients. Monitoring of behavioral indicators along with biomarkers may have crucial benefits in translational stroke research.

  17. A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

    NASA Astrophysics Data System (ADS)

    Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

    2017-04-01

    The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

  18. The Role of Rare Earth Metals on Effective Work Function Modulation of Nickel Fully-Silicided Gate/High-k Dielectric Stacks for n-Channel Metal Oxide Semiconductor Device Applications

    NASA Astrophysics Data System (ADS)

    Lee, Bongmook; Novak, Steven R.; Biswas, Nivedita; Misra, Veena

    2012-01-01

    It was found that the structural properties with gadolinium (Gd) and europium (Eu) incorporation into nickel (Ni) fully silicided (FUSI) gate electrodes are markedly different and resulted in different degrees of effective work function modulation. It was found that Ni-Gd alloys tend to form stable compounds during silicidation and produced a Si-rich layer with amorphous/nanocystalline structure near the FUSI gate electrode/high-k dielectric interface. This compositional and structural change is the main mechanism responsible for effective work function modulation with Gd incorporation. However, in the case of Europium, Eu atoms tend to segregate outside the Ni-FUSI layer during silicidation and resulted in a uniform NixSiy layer with Eu pile-up layer at the FUSI gate electrode/high-k dielectric interface. This pile-up is believed to be the main cause of effective work function modulation with Eu incorporation. It was also found that the incorporation of Gd and Eu metals into Ni-FUSI gate can remotely scavenge the interfacial oxide layer resulting in lower equivalent oxide thickness (EOT) of the device.

  19. Properties of high k gate dielectric gadolinium oxide deposited on Si (1 0 0) by dual ion beam deposition (DIBD)

    NASA Astrophysics Data System (ADS)

    Zhou, Jian-Ping; Chai, Chun-Lin; Yang, Shao-Yan; Liu, Zhi-Kai; Song, Shu-Lin; Li, Yan-Li; Chen, Nuo-Fu

    2004-09-01

    Gadolinium oxide thin films have been prepared on silicon (1 0 0) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation (4 bar 0 2) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (2 0 2), and finally, the cubic structure appeared at the substrate temperature of 700 °C, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented.

  20. Day to Day Variability and Reliability of Blood Oxidative Stress Markers within a Four-Week Period in Healthy Young Men

    PubMed Central

    Goldfarb, A. H.; Garten, R. S.; Waller, J.; Labban, J. D.

    2014-01-01

    The present study aimed to determine the day to day variability and reliability of several blood oxidative stress markers at rest in a healthy young cohort over a four-week period. Twelve apparently healthy resistance trained males (24.6 ± 3.0 yrs) were tested over 7 visits within 4 weeks with at least 72 hrs between visits at the same time of day. Subjects rested 30 minutes prior to blood being obtained by vacutainer. Results. The highest IntraClass correlations (ICC's) were obtained for protein carbonyls (PC) and oxygen radical absorbance capacity (ORAC) (PC = 0.785 and ORAC = 0.780). Cronbach's α reliability score for PC was 0.967 and for ORAC was 0.961. The ICC's for GSH, GSSG, and the GSSG/TGH ratio ICC were 0.600, 0.573, and 0.570, respectively, with Cronbach's α being 0.913, 0.904, and 0.903, respectively. Xanthine oxidase ICC was 0.163 and Cronbach's α was 0.538. Conclusions. PC and ORAC demonstrated good to excellent reliability while glutathione factors had poor to excellent reliability. Xanthine oxidase showed poor reliability and high variability. These results suggest that the PC and ORAC markers were the most stable and reliable oxidative stress markers in blood and that daily changes across visits should be considered when interpreting resting blood oxidative stress markers. PMID:26317028

  1. Circadian phase-dependent effect of nitric oxide on L-type voltage-gated calcium channels in avian cone photoreceptors

    PubMed Central

    Ko, Michael L.; Shi, Liheng; Huang, Cathy Chia-Yu; Grushin, Kirill; Park, So-Young; Ko, Gladys Y.-P.

    2014-01-01

    Nitric oxide (NO) plays an important role in phase-shifting of circadian neuronal activities in the suprachiasmatic nucleus and circadian behavior activity rhythms. In the retina, NO production is increased in a light-dependent manner. While endogenous circadian oscillators in retinal photoreceptors regulate their physiological states, it is not clear whether NO also participates in the circadian regulation of photoreceptors. In the present study, we demonstrate that NO is involved in the circadian phase-dependent regulation of L-type voltage-gated calcium channels (L-VGCCs). In chick cone photoreceptors, the L-VGCCα1 subunit expression and the maximal L-VGCC currents are higher at night, and both Ras-MAPK (mitogen-activated protein kinase)-Erk (extracellular-signal-regulated kinase) and Ras-phosphatidylinositol 3 kinase (PI3K)-protein kinase B (Akt) are part of the circadian output pathways regulating L-VGCCs. The NO-cGMP-protein kinase G (PKG) pathway decreases L-VGCCα1 subunit expression and L-VGCC currents at night, but not during the day, and exogenous NO donor or cGMP decreases the phosphorylation of Erk and Akt at night. The protein expression of neural NO synthase (nNOS) is also under circadian control, with both nNOS and NO production being higher during the day. Taken together, NO/cGMP/PKG signaling is involved as part of the circadian output pathway to regulate L-VGCCs in cone photoreceptors. PMID:23895452

  2. Consecutive Gated Injection-Based Microchip Electrophoresis for Simultaneous Quantitation of Superoxide Anion and Nitric Oxide in Single PC-12 Cells.

    PubMed

    Li, Lu; Li, Qingling; Chen, Peilin; Li, Zhongyi; Chen, Zhenzhen; Tang, Bo

    2016-01-05

    As important reactive oxygen species (ROS) and reactive nitrogen species (RNS), cellular superoxide anion (O2(•-)) and nitric oxide (NO) play significant roles in numerous physiological and pathological processes. Cellular O2(•-) and NO also have a close relationship and always interact with each other. Thus, the simultaneous detection of intracellular O2(•-) and NO, especially at the single-cell level, is important. In this paper, we present a novel method to simultaneously detect and quantify O2(•-) and NO in single cells using microchip electrophoresis based on a new consecutive gated injection method. This novel injection method achieved consecutive manipulation of single cells, guaranteeing an almost constant volumetric flow rate and thus good quantitative reproducibility. After cellular content separation by microchip electrophoresis and detection by laser-induced fluorescence (MCE-LIF), O2(•-) and NO in single PC-12 cells were simultaneously quantified in an automated fashion. This is the first report of consecutive absolute quantitation at the single-cell level. The quantitative results obtained from single cells is beneficial for deep understanding of the biological roles of cellular O2(•-) and NO. This new method constitutes a consecutive, accurate way to study the synergistic function of O2(•-) and NO and other biomolecules in various biological events at the single-cell level.

  3. Multiple-stimuli responsive bioelectrocatalysis based on reduced graphene oxide/poly(N-isopropylacrylamide) composite films and its application in the fabrication of logic gates.

    PubMed

    Wang, Lei; Lian, Wenjing; Yao, Huiqin; Liu, Hongyun

    2015-03-11

    In the present work, reduced graphene oxide (rGO)/poly(N-isopropylacrylamide) (PNIPAA) composite films were electrodeposited onto the surface of Au electrodes in a fast and one-step manner from an aqueous mixture of a graphene oxide (GO) dispersion and N-isopropylacrylamide (NIPAA) monomer solutions. Reflection-absorption infrared (IR) and Raman spectroscopies were employed to characterize the successful construction of the rGO/PNIPAA composite films. The rGO/PNIPAA composite films exhibited reversible potential-, pH-, temperature-, and sulfate-sensitive cyclic voltammetric (CV) on-off behavior to the electroactive probe ferrocenedicarboxylic acid (Fc(COOH)2). For instance, after the composite films were treated at -0.7 V for 7 min, the CV responses of Fc(COOH)2 at the rGO/PNIPAA electrodes were quite large at pH 8.0, exhibiting the on state. However, after the films were treated at 0 V for 30 min, the CV peak currents became much smaller, demonstrating the off state. The mechanism of the multiple-stimuli switchable behaviors for the system was investigated not only by electrochemical methods but also by scanning electron microscopy and X-ray photoelectron spectroscopy. The potential-responsive behavior for this system was mainly attributed to the transformation between rGO and GO in the films at different potentials. The film system was further used to realize multiple-stimuli responsive bioelectrocatalysis of glucose catalyzed by the enzyme of glucose oxidase and mediated by the electroactive probe of Fc(COOH)2 in solution. On the basis of this, a four-input enabled OR (EnOR) logic gate network was established.

  4. Enhanced transport and transistor performance with oxide seeded high-κ gate dielectrics on wafer-scale epitaxial graphene.

    PubMed

    Hollander, Matthew J; Labella, Michael; Hughes, Zachary R; Zhu, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Wang, Xiaojun; Hwang, Euichul; Datta, Suman; Robinson, Joshua A

    2011-09-14

    We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer deposition that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Additionally, high-κ seeded dielectrics are shown to produce superior transistor performance relative to low-κ seeded dielectrics and the presence of heterogeneous seed/overlayer structures is found to be detrimental to transistor performance, reducing effective mobility by 30-40%. The direct deposition of high-purity oxide seed represents the first robust method for the deposition of uniform atomic layer deposited dielectrics on epitaxial graphene that improves carrier transport.

  5. Effect of H and OH desorption and diffusion on electronic structure in amorphous In-Ga-Zn-O metal-oxide-semiconductor diodes with various gate insulators

    NASA Astrophysics Data System (ADS)

    Hino, Aya; Morita, Shinya; Yasuno, Satoshi; Kishi, Tomoya; Hayashi, Kazushi; Kugimiya, Toshihiro

    2012-12-01

    Metal-oxide-semiconductor (MOS) diodes with various gate insulators (G/Is) were characterized by capacitance-voltage characteristics and isothermal capacitance transient spectroscopy (ICTS) to evaluate the effect of H and OH desorption and diffusion on the electronic structures in amorphous In-Ga-Zn-O (a-IGZO) thin films. The density and the distribution of the space charge were found to be varied depending on the nature of the G/I. In the case of thermally grown SiO2 (thermal SiO2) G/Is, a high space-charge region was observed near the a-IGZO and G/I interface. After thermal annealing, the space-charge density in the deeper region of the film decreased, whereas remained unchanged near the interface region. The ICTS spectra obtained from the MOS diodes with the thermal SiO2 G/Is consisted of two broad peaks at around 5 × 10-4 and 3 × 10-2 s before annealing, while one broad peak was observed at around 1 × 10-4 s at the interface and at around 1 × 10-3 s in the bulk after annealing. Further, the trap density was considerably high near the interface. In contrast, the space-charge density was high throughout the bulk region of the MOS diode when the G/I was deposited by chemical vapor deposition (CVD). The ICTS spectra from the MOS diodes with the CVD G/Is revealed the existence of continuously distributed trap states, suggesting formations of high-density tail states below the conduction band minimum. According to secondary ion mass spectroscopy analyses, desorption and outdiffusion of H and OH were clearly observed in the CVD G/I sample. These phenomena could introduce structural fluctuations in the a-IGZO films, resulting in the formation of the conduction band tail states. Thin-film transistors (TFTs) with the same gate structure as the MOS diodes were fabricated to correlate the electronic properties with the TFT performance, and it was found that TFTs with the CVD G/I showed a reduced saturation mobility. These results indicate that the electronic structures

  6. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets.

    PubMed

    Wang, A L; Gold, J M; Tompkins, N; Heymann, M; Harrington, K I; Fraden, S

    2016-02-01

    We investigate the Belousov-Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment.

  7. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    PubMed Central

    Wang, A.L.; Gold, J.M.; Tompkins, N.; Heymann, M.; Harrington, K.I.; Fraden, S.

    2016-01-01

    We investigate the Belousov–Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment. PMID:27168916

  8. Configurable NOR gate arrays from Belousov-Zhabotinsky micro-droplets

    NASA Astrophysics Data System (ADS)

    Wang, A. L.; Gold, J. M.; Tompkins, N.; Heymann, M.; Harrington, K. I.; Fraden, S.

    2016-02-01

    We investigate the Belousov-Zhabotinsky (BZ) reaction in an attempt to establish a basis for computation using chemical oscillators coupled via inhibition. The system consists of BZ droplets suspended in oil. Interdrop coupling is governed by the non-polar communicator of inhibition, Br2. We consider a linear arrangement of three droplets to be a NOR gate, where the center droplet is the output and the other two are inputs. Oxidation spikes in the inputs, which we define to be TRUE, cause a delay in the next spike of the output, which we read to be FALSE. Conversely, when the inputs do not spike (FALSE) there is no delay in the output (TRUE), thus producing the behavior of a NOR gate. We are able to reliably produce NOR gates with this behavior in microfluidic experiment.

  9. Buffer layer engineering on graphene via various oxidation methods for atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Takahashi, Nobuaki; Nagashio, Kosuke

    2016-12-01

    The integration of a high-k oxide on graphene using atomic layer deposition requires an electrically reliable buffer layer. In this study, Y was selected as the buffer layer due to its highest oxidation ability among the rare-earth elements, and various oxidation methods (atmospheric, and high-pressure O2 and ozone annealing) were applied to the Y metal buffer layer. By optimizing the oxidation conditions of the top-gate insulator, we successfully improved the capacitance of the top gate Y2O3 insulator and demonstrated a large I on/I off ratio for bilayer graphene under an external electric field.

  10. Side Gate Tunable Josephson Junctions at the LaAlO3/SrTiO3 Interface

    PubMed Central

    2017-01-01

    Novel physical phenomena arising at the interface of complex oxide heterostructures offer exciting opportunities for the development of future electronic devices. Using the prototypical LaAlO3/SrTiO3 interface as a model system, we employ a single-step lithographic process to realize gate-tunable Josephson junctions through a combination of lateral confinement and local side gating. The action of the side gates is found to be comparable to that of a local back gate, constituting a robust and efficient way to control the properties of the interface at the nanoscale. We demonstrate that the side gates enable reliable tuning of both the normal-state resistance and the critical (Josephson) current of the constrictions. The conductance and Josephson current show mesoscopic fluctuations as a function of the applied side gate voltage, and the analysis of their amplitude enables the extraction of the phase coherence and thermal lengths. Finally, we realize a superconducting quantum interference device in which the critical currents of each of the constriction-type Josephson junctions can be controlled independently via the side gates. PMID:28071920

  11. Effect of Oxidation Temperature on Physical and Electrical Properties of Sm2O3 Thin-Film Gate Oxide on Si Substrate

    NASA Astrophysics Data System (ADS)

    Goh, Kian Heng; Haseeb, A. S. M. A.; Wong, Yew Hoong

    2016-10-01

    Thermal oxidation of 150-nm sputtered pure samarium metal film on silicon substrate has been carried out in oxygen ambient at various temperatures (600°C to 900°C) for 15 min and the effect of the oxidation temperature on the structural, chemical, and electrical properties of the resulting Sm2O3 layers investigated. The crystallinity of the Sm2O3 films and the existence of an interfacial layer were evaluated by x-ray diffraction (XRD) analysis, Fourier-transform infrared (FTIR) spectroscopy, and Raman analysis. The crystallite size and microstrain of Sm2O3 were estimated by Williamson-Hall (W-H) plot analysis, with comparison of the former with the crystallite size of Sm2O3 as calculated using the Scherrer equation. High-resolution transmission electron microscopy (HRTEM) with energy-dispersive x-ray (EDX) spectroscopy analysis was carried out to investigate the cross-sectional morphology and chemical distribution of selected regions. The activation energy or growth rate of each stacked layer was calculated from Arrhenius plots. The surface roughness and topography of the Sm2O3 layers were examined by atomic force microscopy (AFM) analysis. A physical model based on semipolycrystalline nature of the interfacial layer is suggested and explained. Results supporting such a model were obtained by FTIR, XRD, Raman, EDX, and HRTEM analyses. Electrical characterization revealed that oxidation temperature at 700°C yielded the highest breakdown voltage, lowest leakage current density, and highest barrier height value.

  12. Prediction of Reliable Metal-PH₃ Bond Energies for Ni, Pd, and Pt in the 0 and +2 Oxidation States

    SciTech Connect

    Craciun, Raluca; Vincent, Andrew J.; Shaughnessy, Kevin H.; Dixon, David A.

    2010-06-21

    Phosphine-based catalysts play an important role in many metal-catalyzed carbon-carbon bond formation reactions yet reliable values of their bond energies are not available. We have been studying homogeneous catalysts consisting of a phosphine bonded to a Pt, Pd, or Ni. High level electronic structure calculations at the CCSD(T)/complete basis set level were used to predict the M-PH₃ bond energy (BE) for the 0 and +2 oxidation states for M=Ni, Pd, and Pt. The calculated bond energies can then be used, for example, in the design of new catalyst systems. A wide range of exchange-correlation functionals were also evaluated to assess the performance of density functional theory (DFT) for these important bond energies. None of the DFT functionals were able to predict all of the M-PH3 bond energies to within 5 kcal/mol, and the best functionals were generalized gradient approximation functionals in contrast to the usual hybrid functionals often employed for main group thermochemistry.

  13. On the applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells

    SciTech Connect

    Lara-Curzio, Edgar; Radovic, Miladin; Luttrell, Claire R

    2016-01-01

    The applicability of probabilistic analyses to assess the structural reliability of materials and components for solid-oxide fuel cells (SOFC) is investigated by measuring the failure rate of Ni-YSZ when subjected to a temperature gradient and comparing it with that predicted using the Ceramics Analysis and Reliability Evaluation of Structures (CARES) code. The use of a temperature gradient to induce stresses was chosen because temperature gradients resulting from gas flow patterns generate stresses during SOFC operation that are the likely to control the structural reliability of cell components The magnitude of the predicted failure rate was found to be comparable to that determined experimentally, which suggests that such probabilistic analyses are appropriate for predicting the structural reliability of materials and components for SOFCs. Considerations for performing more comprehensive studies are discussed.

  14. Evolution of the gate current in 32 nm MOSFETs under irradiation

    NASA Astrophysics Data System (ADS)

    Palumbo, F.; Debray, M.; Vega, N.; Quinteros, C.; Kalstein, A.; Guarin, F.

    2016-05-01

    Radiation induced currents on single 32 nm MOSFET transistors have been studied using consecutive runs of 16O at 25 MeV. The main feature is the generation of current peaks - in the gate and channel currents - due to the collection of the electro-hole pairs generated by the incident radiation runs. It has been observed that the incident ions cause damage in the dielectric layer and in the substrate affecting the collection of carriers, and hence the radiation-induced current peaks. It has been find out a decrease of the current peak due to the increase of the series resistance by non-ionizing energy loss in the semiconductor substrate, and an increase of the leakage current due to defects in the gate oxide by ionizing energy loss. For low levels of damage in the gate oxide, the main feature is the shift of the VTH. Hot carriers heated by the incident radiation in the depletion region and injected in the gate oxide cause the change of the VTH due to electron or hole trapping for n- or p-channel respectively. The overall results illustrate that these effects must be taken into consideration for an accurate reliability projection.

  15. Angiotensin II type 2 receptor-coupled nitric oxide production modulates free radical availability and voltage-gated Ca2+ currents in NTS neurons

    PubMed Central

    Coleman, Christal G.; Glass, Michael J.; Zhou, Ping; Yu, Qi; Park, Laibaik; Anrather, Josef; Pickel, Virginia M.; Iadecola, Costantino

    2012-01-01

    The medial region of the nucleus tractus solitarius (mNTS) is a key brain stem site controlling cardiovascular function, wherein ANG II modulates neuronal L-type Ca2+ currents via activation of ANG II type 1 receptors (AT1R) and production of reactive oxygen species (ROS). ANG II type 2 receptors (AT2R) induce production of nitric oxide (NO), which may interact with ROS and modulate AT1R signaling. We sought to determine whether AT2R-mediated NO production occurs in mNTS neurons and, if so, to elucidate the NO source and the functional interaction with AT1R-induced ROS or Ca2+ influx. Electron microscopic (EM) immunolabeling showed that AT2R and neuronal NO synthase (nNOS) are coexpressed in neuronal somata and dendrites receiving synapses in the mNTS. In the presence of the AT1R antagonist losartan, ANG II increased NO production in isolated mNTS neurons, an effect blocked by the AT2R antagonist PD123319, but not the angiotensin (1–7) antagonist D-Ala. Studies in mNTS neurons of nNOS-null or endothelial NOS (eNOS)-null mice established nNOS as the source of NO. ANG II-induced ROS production was enhanced by PD123319, the NOS inhibitor NG-nitro-l-arginine (LNNA), or in nNOS-null mice. Moreover, in the presence of losartan, ANG II reduced voltage-gated L-type Ca2+ current, an effect blocked by PD123319 or LNNA. We conclude that AT2R are closely associated and functionally coupled with nNOS in mNTS neurons. The resulting NO production antagonizes AT1R-mediated ROS and dampens L-type Ca2+ currents. The ensuing signaling changes in the NTS may counteract the deleterious effects of AT1R on cardiovascular function. PMID:22378773

  16. Sliding-gate valve for use with abrasive materials

    DOEpatents

    Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

    1985-01-01

    The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

  17. Improved electrical properties of Ge metal-oxide-semiconductor capacitors with high-k HfO2 gate dielectric by using La2O3 interlayer sputtered with/without N2 ambient

    NASA Astrophysics Data System (ADS)

    Xu, H. X.; Xu, J. P.; Li, C. X.; Lai, P. T.

    2010-07-01

    The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.

  18. Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

    SciTech Connect

    Kao, Tsung-Hsien; Chang, Shoou-Jinn Fang, Yean-Kuen; Huang, Po-Chin; Wu, Chung-Yi; Wu, San-Lein

    2014-08-11

    In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

  19. Agomelatine and duloxetine synergistically modulates apoptotic pathway by inhibiting oxidative stress triggered intracellular calcium entry in neuronal PC12 cells: role of TRPM2 and voltage-gated calcium channels.

    PubMed

    Akpinar, Abdullah; Uğuz, Abdülhadi Cihangir; Nazıroğlu, Mustafa

    2014-05-01

    Calcium ion (Ca(2+)) is one of the universal second messengers, which acts in a wide range of cellular processes. Results of recent studies indicated that ROS generated by depression leads to loss of endoplasmic reticulum-Ca(2+) homeostasis, oxidative stress, and apoptosis. Agomelatine and duloxetine are novel antidepressant and antioxidant drugs and may reduce oxidative stress, apoptosis, and Ca(2+) entry through TRPM2 and voltage-gated calcium channels. We tested the effects of agomelatine, duloxetine, and their combination on oxidative stress, Ca(2+) influx, mitochondrial depolarization, apoptosis, and caspase values in the PC-12 neuronal cells. PC-12 neuronal cells were exposed in cell culture and exposed to appropriate non-toxic concentrations and incubation times for agomelatine were determined in the neurons by assessing cell viability. Then PC-12 cells were incubated with agomelatine and duloxetine for 24 h. Treatment of cultured PC-12 cells with agomelatine, duloxetine, and their combination results in a protection on apoptosis, caspase-3, caspase-9, mitochondrial membrane depolarization, cytosolic ROS production, glutathione peroxidase, reduced glutathione, and lipid peroxidation, values. Ca(2+) entry through non-specific TRPM2 channel blocker (2-APB) and voltage-gated Ca(2+) channel blockers (verapamil and diltiazem) was modulated by agomelatine and duloxetine. However, effects of duloxetine on the Ca(2+) entry through TRPM2 channels were higher than in agomelatine. Results of current study suggest that the agomelatine and duloxetine are useful against apoptotic cell death and oxidative stress in PC-12 cells, which seem to be dependent on mitochondrial damage and increased levels of intracellular Ca(2+) through activation of TRPM2 and voltage-gated Ca(2+) channels.

  20. Corticostriatal output gating during selection from working memory.

    PubMed

    Chatham, Christopher H; Frank, Michael J; Badre, David

    2014-02-19

    Convergent evidence suggests that corticostriatal interactions act as a gate to select the input to working memory (WM). However, not all information in WM is relevant for behavior simultaneously. For this reason, a second "output gate" might advantageously govern which contents of WM influence behavior. Here, we test whether frontostriatal circuits previously implicated in input gating also support output gating during selection from WM. fMRI of a hierarchical rule task with dissociable input and output gating demands demonstrated greater lateral prefrontal cortex (PFC) recruitment and frontostriatal connectivity during output gating. Moreover, PFC and striatum correlated with distinct behavioral profiles. Whereas PFC recruitment correlated with mean efficiency of selection from WM, striatal recruitment and frontostriatal interactions correlated with its reliability, as though such dynamics stochastically gate WM's output. These results support the output gating hypothesis, suggesting that contextual representations in PFC influence striatum to select which information in WM drives responding.

  1. Gate stack engineering for GaN lateral power transistors

    NASA Astrophysics Data System (ADS)

    Yang, Shu; Liu, Shenghou; Liu, Cheng; Hua, Mengyuan; Chen, Kevin J.

    2016-02-01

    Developing optimal gate-stack technology is a key to enhancing the reliability and performance of GaN insulated-gate devices for high-voltage power switching applications. In this paper, we discuss current challenges and review our recent progresses in gate-stack technology development toward high-performance and high-reliability GaN power devices, including (1) interface engineering that creates a high-quality dielectric/III-nitride interface with low trap density; (2) barrier-layer engineering that enables optimal trade-off between performance and stability; (3) bulk quality and reliability enhancement of the gate dielectric. These gate-stack techniques in terms of new process development and device structure design are valuable to realize highly reliable and competitive GaN power devices.

  2. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    SciTech Connect

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specific contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.

  3. Effect of proton irradiation dose on InAlN/GaN metal-oxide semiconductor high electron mobility transistors with Al2O3 gate oxide

    SciTech Connect

    Ahn, Shihyun; Kim, Byung -Jae; Lin, Yi -Hsuan; Ren, Fan; Pearton, Stephen J.; Yang, Gwangseok; Kim, Jihyun; Kravchenko, Ivan I.

    2016-07-26

    The effects of proton irradiation on the dc performance of InAlN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) with Al2O3 as the gate oxide were investigated. The InAlN/GaN MOSHEMTs were irradiated with doses ranging from 1×1013 to 1×1015cm–2 at a fixed energy of 5MeV. There was minimal damage induced in the two dimensional electron gas at the lowest irradiation dose with no measurable increase in sheet resistance, whereas a 9.7% increase of the sheet resistance was observed at the highest irradiation dose. By sharp contrast, all irradiation doses created more severe degradation in the Ohmic metal contacts, with increases of specific contact resistance from 54% to 114% over the range of doses investigated. These resulted in source-drain current–voltage decreases ranging from 96 to 242 mA/mm over this dose range. The trap density determined from temperature dependent drain current subthreshold swing measurements increased from 1.6 × 1013 cm–2 V–1 for the reference MOSHEMTs to 6.7 × 1013 cm–2 V–1 for devices irradiated with the highest dose. In conclusion, the carrier removal rate was 1287 ± 64 cm–1, higher than the authors previously observed in AlGaN/GaN MOSHEMTs for the same proton energy and consistent with the lower average bond energy of the InAlN.

  4. Electrical properties of GaAs metal-oxide-semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal-organic vapor deposition/atomic layer deposition hybrid system

    NASA Astrophysics Data System (ADS)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2015-08-01

    This paper presents a compressive study on the fabrication and optimization of GaAs metal-oxide-semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal-organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance-voltage (C-V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm-2 eV-1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  5. Source-side injection single-polysilicon split-gate flash memory

    NASA Astrophysics Data System (ADS)

    Yamauchi, Yoshimitsu; Kamakura, Yoshinari; Matsuoka, Toshimasa; Ueda, Naoki

    2014-03-01

    The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

  6. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  7. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  8. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  9. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall...

  10. 49 CFR 234.255 - Gate arm and gate mechanism.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month....

  11. Characteristics of carbon monoxide sensors made by polar and nonpolar zinc oxide nanowires gated AlGaN/GaN high electron mobility transistor

    NASA Astrophysics Data System (ADS)

    Hung, S. C.; Woon, W. Y.; Lan, S. M.; Ren, F.; Pearton, S. J.

    2013-08-01

    AlGaN/GaN high electron mobility transistors (HEMTs) with polar and nonpolar ZnO nanowires modified gate exhibit significant changes in channel conductance upon exposure to different concentration of carbon monoxide (CO) at room temperature. The ZnO nanowires, grown by chemical vapor deposition, with perfect crystal quality will attach CO molecules and release electrons, which will lead to a change of surface charge in the gate region of the HEMTs, inducing a higher positive charge on the AlGaN surface, and increasing the piezo-induced charge density in the HEMTs channel. These electrons create an image positive charge on the gate region for the required neutrality, thus increasing the drain current of the HEMTs. The HEMTs source-drain current was highly dependent on the CO concentration. The limit of detection achieved was 400 ppm and 3200 ppm in the open cavity with continuous gas flow using a 50 × 50 μm2 gate sensing area for polar and nonpolar ZnO nanowire gated HEMTs sensor, respectively.

  12. Nitric oxide inhibits neuroendocrine CaV1 L-channel gating via cGMP-dependent protein kinase in cell-attached patches of bovine chromaffin cells

    PubMed Central

    Carabelli, Valentina; D'Ascenzo, Marcello; Carbone, Emilio; Grassi, Claudio

    2002-01-01

    Nitric oxide (NO) regulates the release of catecholamines from the adrenal medulla but the molecular targets of its action are not yet well identified. Here we show that the NO donor sodium nitroprusside (SNP, 200 μM) causes a marked depression of the single CaV1 L-channel activity in cell-attached patches of bovine chromaffin cells. SNP action was complete within 3-5 min of cell superfusion. In multichannel patches the open probability (NPo) decreased by ∼60 % between 0 and +20 mV. Averaged currents over a number of traces were proportionally reduced and showed no drastic changes to their time course. In single-channel patches the open probability (Po) at +10 mV decreased by the same amount as that of multichannel patches (∼61 %). Such a reduction was mainly associated with an increased probability of null sweeps and a prolongation of mean shut times, while first latency, mean open time and single-channel conductance were not significantly affected. Addition of the NO scavenger carboxy-PTIO or cell treatment with the guanylate cyclase inhibitor ODQ prevented the SNP-induced inhibition. 8-Bromo-cyclicGMP (8-Br-cGMP; 400 μM) mimicked the action of the NO donor and the protein kinase G blocker KT-5823 prevented this effect. The depressive action of SNP was preserved after blocking the cAMP-dependent up-regulatory pathway with the protein kinase A inhibitor H89. Similarly, the inhibitory action of 8-Br-cGMP proceeded regardless of the elevation of cAMP levels, suggesting that cGMP/PKG and cAMP/PKA act independently on L-channel gating. The inhibitory action of 8-Br-cGMP was also independent of the G protein-induced inhibition of L-channels mediated by purinergic and opiodergic autoreceptors. Since Ca2+ channels contribute critically to both the local production of NO and catecholamine release, the NO/PKG-mediated inhibition of neuroendocrine L-channels described here may represent an important autocrine signalling mechanism for controlling the rate of

  13. Gating of Permanent Molds for ALuminum Casting

    SciTech Connect

    David Schwam; John F. Wallace; Tom Engle; Qingming Chang

    2004-03-30

    This report summarizes a two-year project, DE-FC07-01ID13983 that concerns the gating of aluminum castings in permanent molds. The main goal of the project is to improve the quality of aluminum castings produced in permanent molds. The approach taken was determine how the vertical type gating systems used for permanent mold castings can be designed to fill the mold cavity with a minimum of damage to the quality of the resulting casting. It is evident that somewhat different systems are preferred for different shapes and sizes of aluminum castings. The main problems caused by improper gating are entrained aluminum oxide films and entrapped gas. The project highlights the characteristic features of gating systems used in permanent mold aluminum foundries and recommends gating procedures designed to avoid common defects. The study also provides direct evidence on the filling pattern and heat flow behavior in permanent mold castings.

  14. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    PubMed Central

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

  15. Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system.

    PubMed

    Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M; Avila-García, Alejandro; Vazquez-Acosta, E N; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

    2010-01-01

    Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe(2)O(3) layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  16. DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1977-01-01

    Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

  17. Ferroelectric/Dielectric Double Gate Insulator Spin-Coated Using Barium Titanate Nanocrystals for an Indium Oxide Nanocrystal-Based Thin-Film Transistor.

    PubMed

    Pham, Hien Thu; Yang, Jin Ho; Lee, Don-Sung; Lee, Byoung Hun; Jeong, Hyun-Dam

    2016-03-23

    Barium titanate nanocrystals (BT NCs) were prepared under solvothermal conditions at 200 °C for 24 h. The shape of the BT NCs was tuned from nanodot to nanocube upon changing the polarity of the alcohol solvent, varying the nanosize in the range of 14-22 nm. Oleic acid-passivated NCs showed good solubility in a nonpolar solvent. The effect of size and shape of the BT NCs on the ferroelectric properties was also studied. The maximum polarization value of 7.2 μC/cm(2) was obtained for the BT-5 NC thin film. Dielectric measurements of the films showed comparable dielectric constant values of BT NCs over 1-100 kHz without significant loss. Furthermore, the bottom gate In2O3 NC thin film transistors exhibited outstanding device performance with a field-effect mobility of 11.1 cm(2) V(-1) s(-1) at a low applied gate voltage with BT-5 NC/SiO2 as the gate dielectric. The low-density trapped state was observed at the interface between the In2O3 NC semiconductor and the BT-5 NCs/SiO2 dielectric film. Furthermore, compensation of the applied gate field by an electric dipole-induced dipole field within the BT-5 NC film was also observed.

  18. Influence of uniaxial strain in Si and Ge p-type double-gate metal-oxide-semiconductor field effect transistors

    NASA Astrophysics Data System (ADS)

    Moussavou, Manel; Cavassilas, Nicolas; Dib, Elias; Bescond, Marc

    2015-09-01

    We theoretically investigate the impact of uniaxial strain in extremely thin Si and Ge p-type double-gate transistors. Quantum transport modeling is treated using a 6-band k.p Hamiltonian and the non-equilibrium Green's function formalism including phonon scattering. Based on this framework, we analyze the influence of strain on current characteristics considering different transport directions and gate lengths. Our results first confirm the superiority of Ge over Si in long devices (15 nm gate length) for which best electrical performances are obtained considering channels along <110 > with a uni-axial compressive strain. For this configuration, Si devices suffer from inter-subband coupling which generates a strong hole-phonon scattering. Material dominance is reversed for shorter devices (7 nm gate length) where the small effective masses of Ge deteriorate the off-regime of the nano-transistor regardless of strain and crystallographic options. Due to weaker hole-phonon-scattering, <100 > -Si devices with a tensile strain are interestingly found to be more competitive than their <110 > -compressive counterparts. These results show that Si is still the most relevant material to reach the ultimate nanometer scale. More importantly, the same tensile strain can be considered to boost performances of both p- and n-type planar transistors which would lead to a significant simplification of the technological strain manufacturing.

  19. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal-Oxide-Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Azzah Bte Suleiman, Sumarlina; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal-oxide-semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel-Poole emission at high electric field. This Frenkel-Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel-Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley-Read-Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id∝T-0.37 observed for passivated device, in comparison to Id∝T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  20. Gate-Leakage and Carrier-Transport Mechanisms for Plasma-PH3 Passivated InGaAs N-Channel Metal--Oxide--Semiconductor Field-Effect Transistors

    NASA Astrophysics Data System (ADS)

    Suleiman, Sumarlina Azzah Bte; Lee, Sungjoo

    2012-02-01

    Gate leakage mechanism of the HfAlO plasma-PH3 passivated and non-passivated In0.53Ga0.47As N-channel metal--oxide--semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel--Poole emission at high electric field. This Frenkel--Poole emission is associated with energy trap levels of ˜0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3× 1019 cm-3 and the average activation energy given as ˜0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In0.53Ga0.47As interface. On the other hand, passivated device does not contain Frenkel--Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley--Read--Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From Id\\propto T-0.37 observed for passivated device, in comparison to Id\\propto T-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

  1. Hole mobility degradation by remote Coulomb scattering and charge distribution in Al2O3/GeO x gate stacks in bulk Ge pMOSFET with GeO x grown by ozone oxidation

    NASA Astrophysics Data System (ADS)

    Zhou, Lixing; Wang, Xiaolei; Ma, Xueli; Xiang, Jinjuan; Yang, Hong; Zhao, Chao; Ye, Tianchun; Wang, Wenwu

    2017-06-01

    Hole mobility degradation due to remote Coulomb scattering (RCS) from fixed charges of GeO x /Al2O3 gate stacks is experimentally investigated in bulk Ge p-type metal-oxide-semiconductor field effect transistor (pMOSFET), with GeO x grown by ozone oxidation. The hole mobility at 77 K is found to increase with GeO x thickness. The phonon scattering can be ignored at 77 K and the surface roughness scattering is insignificant at a low inversion carrier concentration. This indicates that the RCS is responsible for mobility degradation. Therefore, the fixed charges are investigated in terms of RCS. The charge distribution in GeO x /Al2O3 gate stacks is experimentally estimated. The bulk charge in GeO x and Al2O3 is negligible. The densities of interface charges are  +3.22  ×  1012 cm-2 and  -2.57  ×  1012 cm-2 at the GeO x /Ge and Al2O3/GeO x interface, respectively. The electric dipole at the Al2O3/GeO x interface is  +0.17 eV, corresponding to charge area density of 1.76  ×  1013 cm-2. Consequently, the dipole at the Al2O3/GeO x interface plays a dominant role in the mobility degradation. Our results show that the investigation of charges in a gate stack is valuable for enhancing device performance.

  2. 21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    21. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, GATE PIER, TRUNNION PIN AND GATE GAUGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  3. 6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    6. DETAIL VIEW OF ENTRANCE GATES, SHOWING IRON GATE, STONE WORK, AND GATE STOP FROM SOUTHEAST OF NORTHWEST ELEMENTS. - William Enston Home, Entrance Gate, 900 King Street, Charleston, Charleston County, SC

  4. Bulk and interface trap generation under negative bias temperature instability stress of p-channel metal-oxide-semiconductor field-effect transistors with nitrogen and silicon incorporated HfO2 gate dielectrics

    NASA Astrophysics Data System (ADS)

    Choi, Changhwan; Lee, Jack C.

    2011-02-01

    Negative bias temperature instabilities (NBTIs) of p-channel metal-oxide-semiconductor field-effect-transistor with HfO2, HfOxNy, and HfSiON were investigated. Higher bulk trap generation (ΔNot) is mainly attributed to threshold voltage shift rather than interface trap generation (ΔNit). ΔNit, ΔNot, activation energy (Ea), and lifetime were exacerbated with incorporated nitrogen while improved with adding Si into gate dielectrics. Compared to HfO2, HfOxNy showed worse NBTI due to nitrogen pile-up at Si interface. However, adding Si into HfOxNy placed nitrogen peak profile away from Si/oxide interface and NBTI was reduced. This improvement is ascribed to reduced ΔNot and ΔNit, resulting from less nitrogen at Si interface.

  5. Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

    NASA Astrophysics Data System (ADS)

    Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun; Bang, Tewook; Choi, Yang-Kyu; Park, Sang-Hee Ko; Choi, Kyung Cheol

    2016-05-01

    We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al2O3, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔVth) was 0 V even after a PBS time (tstress) of 3000 s under a gate voltage (VG) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔVth value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔVth values resulting from PBS quantitatively, the average oxide charge trap density (NT) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher NT resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of NT near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.

  6. First investigation at elevated pressures to confirm the exact nature of the gated electron-transfer systems: volume profiles of the gated reduction reaction and nongated reverse oxidation reaction involving a [Cu(dmp)2(solvent)]2+/[Cu(dmp)2]+ couple (dmp = 2,9-dimethyl-1,10-phenanthroline).

    PubMed

    Itoh, Sumitaka; Noda, Kyoko; Yamane, Ryouhei; Kishikawa, Nobuyuki; Takagi, Hideo D

    2007-02-19

    Redox reactions involving the [Cu(dmp)2]2+/+ couple (dmp = 2,9-dimethyl-1,10-phenanthroline) in acetonitrile were examined at elevated pressures up to 200 MPa. Activation volumes were determined as -8.8 and -6.3 cm3 mol-1 for the reduction cross-reaction by [Co(bipy)3]2+ (bipy = 2,2'-bipyridine) and for the oxidation cross-reaction by [Ni(tacn)2]3+ (tacn = 1,4,7-triazacyclononane), respectively. The activation volume for the hypothetical gated mode of the self-exchange reaction estimated from the reduction cross-reaction was -13.9 cm3 mol-1, indicating extensive electrostrictive rearrangement of solvent molecules around the CuII complex during the change in the coordination geometry before the electron-transfer step. On the other hand, the activation volume for the self-exchange reaction estimated from the oxidation cross-reaction was -2.7 +/- 1.5 cm3 mol-1. Although this value was within the range that can be interpreted by the concept of the ordinary concerted process, from theoretical considerations it was concluded that the reverse (oxidation) cross-reaction of the gated reduction reaction of the [Cu(dmp)2(CH3CN)]2+/[Cu(dmp)2]+ couple proceeds through the product excited state while the direct self-exchange reaction between [Cu(dmp)2(CH3CN)]2+ and [Cu(dmp)2]+ proceeds through an ordinary concerted process.

  7. Improvement in performance and reliability with CF4 plasma pretreatment on the buffer oxide layer for low-temperature polysilicon thin-film transistor

    NASA Astrophysics Data System (ADS)

    Fan, Ching-Lin; Lin, Yi-Yan; Yang, Chun-Chieh

    2012-03-01

    This study applies CF4 plasma pretreatment to a buffer oxide layer to improve the performance of low-temperature polysilicon thin-film transistors (LTPS TFTs). Results show that the fluorine atoms piled up at the interface between the bulk channel and buffer oxide layer and accumulated in the bulk channel. The reduction of the trap states density by fluorine passivation can improve the electrical characteristics of the LTPS TFTs. It is found that the threshold voltage reduced from 4.32 to 3.03 V and the field-effect mobility increased from 29.71 to 45.65 cm2 V-1 S-1. In addition, the on current degradation and threshold voltage shift after stressing were significantly improved about 31% and 70%, respectively. We believe that the proposed CF4 plasma pretreatment on the buffer oxide layer can passivate the trap states and avoid the plasma induced damage on the polysilicon channel surface, resulting in the improvement in performance and reliability for LTPS-TFT mass production application on AMOLED displays with critical reliability requirement.

  8. G4-FETs as Universal and Programmable Logic Gates

    NASA Technical Reports Server (NTRS)

    Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

    2007-01-01

    An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

  9. Parallelizable adiabatic gate teleportation

    NASA Astrophysics Data System (ADS)

    Nakago, Kosuke; Hajdušek, Michal; Nakayama, Shojun; Murao, Mio

    2015-12-01

    To investigate how a temporally ordered gate sequence can be parallelized in adiabatic implementations of quantum computation, we modify adiabatic gate teleportation, a model of quantum computation proposed by Bacon and Flammia [Phys. Rev. Lett. 103, 120504 (2009), 10.1103/PhysRevLett.103.120504], to a form deterministically simulating parallelized gate teleportation, which is achievable only by postselection. We introduce a twisted Heisenberg-type interaction Hamiltonian, a Heisenberg-type spin interaction where the coordinates of the second qubit are twisted according to a unitary gate. We develop parallelizable adiabatic gate teleportation (PAGT) where a sequence of unitary gates is performed in a single step of the adiabatic process. In PAGT, numeric calculations suggest the necessary time for the adiabatic evolution implementing a sequence of L unitary gates increases at most as O (L5) . However, we show that it has the interesting property that it can map the temporal order of gates to the spatial order of interactions specified by the final Hamiltonian. Using this property, we present a controlled-PAGT scheme to manipulate the order of gates by a control qubit. In the controlled-PAGT scheme, two differently ordered sequential unitary gates F G and G F are coherently performed depending on the state of a control qubit by simultaneously applying the twisted Heisenberg-type interaction Hamiltonians implementing unitary gates F and G . We investigate why the twisted Heisenberg-type interaction Hamiltonian allows PAGT. We show that the twisted Heisenberg-type interaction Hamiltonian has an ability to perform a transposed unitary gate by just modifying the space ordering of the final Hamiltonian implementing a unitary gate in adiabatic gate teleportation. The dynamics generated by the time-reversed Hamiltonian represented by the transposed unitary gate enables deterministic simulation of a postselected event of parallelized gate teleportation in adiabatic

  10. Adaptive quantum gate-set tomography

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    2013-03-01

    Quantum information hardware needs to be characterized and calibrated. This is the job of quantum state and process tomography, but standard tomographic methods have an Achilles heel: to characterize an unknown process, they rely on a set of absolutely calibrated measurements. But many technologies (e.g., solid-state qubits) admit only a single native measurement basis, and other bases are measured using unitary control. So tomography becomes circular - tomographic protocols are using gates to calibrate themselves! Gate-set tomography confronts this problem head-on and resolves it by treating gates relationally. We abandon all assumptions about what a given gate operation does, and characterize entire universal gate sets from the ground up using only the observed statistics of an [unknown] 2-outcome measurement after various strings of [unknown] gate operations. The accuracy and reliability of the resulting estimate depends critically on which gate strings are used, and benefits greatly from adaptivity. Sandia National Labs is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Dept. of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000

  11. Quantum gate decomposition algorithms.

    SciTech Connect

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  12. Reliability enhancement due to in-situ post-oxidation of sputtered MgO barrier in double MgO barrier magnetic tunnel junction

    NASA Astrophysics Data System (ADS)

    Yoshida, Chikako; Noshiro, Hideyuki; Yamazaki, Yuichi; Sugii, Toshihiro

    2017-06-01

    We have investigated the effects of in-situ post-oxidation (PO) of a sputtered MgO barrier in a double-MgO-barrier magnetic tunnel junction (MTJ) and found that the short error rate was significantly reduced, the magnetoresistance (MR) ratio was increased approximately 18%, and the endurance lifetime was extend. In addition, we found that the distribution of breakdown number (a measure of endurance) exhibits trimodal characteristics, which indicates competition between extrinsic and intrinsic failures. This improvement in reliability might be related to the suppression of Fe and Co diffusion to the MgO barrier, as revealed by electron energy-loss spectroscopy (EELS) analysis.

  13. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-04

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  14. Investigation of field induced trapping on floating gates

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1975-01-01

    The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

  15. Protocol Optimisation For Work-Function Measurements Of Metal Gates Using Kelvin Force Microscopy

    SciTech Connect

    Mariolle, D.; Kaja, K.; Bertin, F.; Martinez, E.; Martin, F.; Gassilloud, R.

    2007-09-26

    Currently, the work-functions of metal gates are determined using capacitance-versus-gate-voltage measurements of a dedicated MOS capacitor structure. Alternatively, Kelvin Force Microscopy (KFM) is a promising technique which allows the work-function to be measured with high spatial resolution (<100 nm) coupled with a high sensitivity (10 meV). Nevertheless, before becoming a standard technique, there are still challenges facing a reliable operating protocol such as careful specimen preparation and environmental control to avoid surface artifacts. In the paper we show that the presence of an oxide, confirmed by Auger Electron Spectroscopy (AES), on a WSi{sub x} metallic layer surface have a detrimental effect on the work-function measurement using KFM.

  16. Gated strip proportional detector

    DOEpatents

    Morris, Christopher L.; Idzorek, George C.; Atencio, Leroy G.

    1987-01-01

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10.sup.6. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  17. Gated strip proportional detector

    DOEpatents

    Morris, C.L.; Idzorek, G.C.; Atencio, L.G.

    1985-02-19

    A gated strip proportional detector includes a gas tight chamber which encloses a solid ground plane, a wire anode plane, a wire gating plane, and a multiconductor cathode plane. The anode plane amplifies the amount of charge deposited in the chamber by a factor of up to 10/sup 6/. The gating plane allows only charge within a narrow strip to reach the cathode. The cathode plane collects the charge allowed to pass through the gating plane on a set of conductors perpendicular to the open-gated region. By scanning the open-gated region across the chamber and reading out the charge collected on the cathode conductors after a suitable integration time for each location of the gate, a two-dimensional image of the intensity of the ionizing radiation incident on the detector can be made.

  18. Solution-processable LaZrOx/SiO2 gate dielectric at low temperature of 180 °C for high-performance metal oxide field-effect transistors.

    PubMed

    Je, So Yeon; Son, Byeong-Geun; Kim, Hyun-Gwan; Park, Man-Young; Do, Lee-Mi; Choi, Rino; Jeong, Jae Kyeong

    2014-11-12

    Although solution-processable high-k inorganic dielectrics have been implemented as a gate insulator for high-performance, low-cost transition metal oxide field-effect transistors (FETs), the high-temperature annealing (>300 °C) required to achieve acceptable insulating properties still limits the facile realization of flexible electronics. This study reports that the addition of a 2-dimetylamino-1-propanol (DMAPO) catalyst to a perhydropolysilazane (PHPS) solution enables a significant reduction of the curing temperature for the resulting SiO2 dielectrics to as low as 180 °C. The hydrolysis and condensation of the as-spun PHPS film under humidity conditions were enhanced greatly by the presence of DMAPO, even at extremely low curing temperatures, which allowed a smooth surface (roughness of 0.31 nm) and acceptable leakage characteristics (1.8 × 10(-6) A/cm(2) at an electric field of 1MV/cm) of the resulting SiO2 dielectric films. Although the resulting indium zinc oxide (IZO) FETs exhibited an apparent high mobility of 261.6 cm(2)/(V s), they suffered from a low on/off current (ION/OFF) ratio and large hysteresis due to the hygroscopic property of silazane-derived SiO2 film. The ION/OFF value and hysteresis instability of IZO FETs was improved by capping the high-k LaZrOx dielectric on a solution-processed SiO2 film via sol-gel processing at a low temperature of 180 °C while maintaining a high mobility of 24.8 cm(2)/(V s). This superior performance of the IZO FETs with a spin-coated LaZrOx/SiO2 bilayer gate insulator can be attributed to the efficient intercalation of the 5s orbital of In(3+) ion in the IZO channel, the good interface matching of IZO/LaZrOx and the carrier blocking ability of PHPS-derived SiO2 dielectric film. Therefore, the solution-processable LaZrOx/SiO2 stack can be a promising candidate as a gate dielectric for low-temperature, high-performance, and low-cost flexible metal oxide FETs.

  19. A two-dimensional semiconductor transistor with boosted gate control and sensing ability

    PubMed Central

    Xu, Jing; Chen, Lin; Dai, Ya-Wei; Cao, Qian; Sun, Qing-Qing; Ding, Shi-Jin; Zhu, Hao; Zhang, David Wei

    2017-01-01

    Transistors with exfoliated two-dimensional (2D) materials on a SiO2/Si substrate have been applied and have been proven effective in a wide range of applications, such as circuits, memory, photodetectors, gas sensors, optical modulators, valleytronics, and spintronics. However, these devices usually suffer from limited gate control because of the thick SiO2 gate dielectric and the lack of reliable transfer method. We introduce a new back-gate transistor scheme fabricated on a novel Al2O3/ITO (indium tin oxide)/SiO2/Si “stack” substrate, which was engineered with distinguishable optical identification of exfoliated 2D materials. High-quality exfoliated 2D materials could be easily obtained and recognized on this stack. Two typical 2D materials, MoS2 and ReS2, were implemented to demonstrate the enhancement of gate controllability. Both transistors show excellent electrical characteristics, including steep subthreshold swing (62 mV dec−1 for MoS2 and 83 mV dec−1 for ReS2), high mobility (61.79 cm2 V−1 s−1 for MoS2 and 7.32 cm2 V−1 s−1 for ReS2), large on/off ratio (~107), and reasonable working gate bias (below 3 V). Moreover, MoS2 and ReS2 photodetectors fabricated on the basis of the scheme have impressively leading photoresponsivities of 4000 and 760 A W−1 in the depletion area, respectively, and both have exceeded 106 A W−1 in the accumulation area, which is the best ever obtained. This opens up a suite of applications of this novel platform in 2D materials research with increasing needs of enhanced gate control. PMID:28560330

  20. High quality PECVD SiO2 process for recessed MOS-gate of AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistors

    NASA Astrophysics Data System (ADS)

    Lee, Jae-Gil; Kim, Hyun-Seop; Seo, Kwang-Seok; Cho, Chun-Hyung; Cha, Ho-Young

    2016-08-01

    A high quality SiO2 deposition process using a plasma enhanced chemical vapor deposition system has been developed for the gate insulator process of normally-off recessed-gate AlGaN/GaN metal-oxide-semiconductor-heterostructure field-effect transistors (MOS-HFETs). SiO2 films were deposited by using SiH4 and N2O mixtures as reactant gases. The breakdown field increased with increasing the N2O flow rate. The optimum SiH4/N2O ratio was 0.05, which resulted in a maximum breakdown field of 11 MV/cm for the SiO2 film deposited on recessed GaN surface. The deposition conditions were optimized as follows; a gas flow rate of SiH4/N2O (=27/540 sccm), a source RF power of 100 W, a pressure of 2 Torr, and a deposition temperature of 350 °C. A fabricated normally-off MOS-HFET exhibited a threshold voltage of 3.2 V, a specific on-resistance of 4.46 mΩ cm2, and a breakdown voltage of 810 V.

  1. Range gated imaging experiments using gated intensifiers

    SciTech Connect

    McDonald, T.E. Jr.; Yates, G.J.; Cverna, F.H.; Gallegos, R.A.; Jaramillo, S.A.; Numkena, D.M.; Payton, J.; Pena-Abeyta, C.R.

    1999-03-01

    A variety of range gated imaging experiments using high-speed gated/shuttered proximity focused microchannel plate image intensifiers (MCPII) are reported. Range gated imaging experiments were conducted in water for detection of submerged mines in controlled turbidity tank test and in sea water for the Naval Coastal Sea Command/US Marine Corps. Field experiments have been conducted consisting of kilometer range imaging of resolution targets and military vehicles in atmosphere at Eglin Air Force Base for the US Air Force, and similar imaging experiments, but in smoke environment, at Redstone Arsenal for the US Army Aviation and Missile Command (AMCOM). Wavelength of the illuminating laser was 532 nm with pulse width ranging from 6 to 12 ns and comparable gate widths. These tests have shown depth resolution in the tens of centimeters range from time phasing reflected LADAR images with MCPII shutter opening.

  2. Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

    NASA Technical Reports Server (NTRS)

    Berg, M.; Kim, H.; Phan, A.; Seidleck, C.; LaBel, K.; Pellish, J.; Campola, M.

    2015-01-01

    Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

  3. Analyzing Single-Event Gate Ruptures In Power MOSFET's

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.

    1993-01-01

    Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

  4. Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors

    SciTech Connect

    Kim, Eungtaek; Kim, Choong-Ki; Lee, Myung Keun; Bang, Tewook; Choi, Yang-Kyu; Choi, Kyung Cheol E-mail: kyungcc@kaist.ac.kr; Park, Sang-Hee Ko E-mail: kyungcc@kaist.ac.kr

    2016-05-02

    We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{sub G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.

  5. Amorphous Indium Gallium Zinc Oxide Semiconductor Thin Film Transistors Using O2 Plasma Treatment on the SiNx Gate Insulator

    NASA Astrophysics Data System (ADS)

    Kim, Woong-Sun; Moon, Yeon-Keon; Lee, Sih; Kang, Byung-Woo; Kim, Kyung-Taek; Lee, Je-Hun; Kim, Joo-Han; Ahn, Byung-Du; Park, Jong-Wan

    2010-08-01

    In this study, we investigated the role of processing parameters on the electrical characteristics of amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFTs) fabricated using DC magnetron sputtering at room temperature. Processing parameters including the oxygen partial pressure, annealing temperature, and channel thickness have a great influence on TFT performance and better devices are obtained at a low oxygen partial pressure, annealing at 200 °C, and a low channel thickness. We attempted to improve the a-IGZO TFT performance and stability under a gate bias stress using O2 plasma treatment. With an O2 plasma treated gate insulator, remarkable properties including excellent bias stability as well as a field effect mobility (µFE) of 11.5 cm2 V-1 s-1, a subthreshold swing (S) of 0.59 V/decade, a turn-on voltage (VON) of -1.3 V, and an on/off current ratio (ION/IOFF) of 105 were achieved.

  6. Molecular doping for control of gate bias stress in organic thin film transistors

    NASA Astrophysics Data System (ADS)

    Hein, Moritz P.; Zakhidov, Alexander A.; Lüssem, Björn; Jankowski, Jens; Tietze, Max L.; Riede, Moritz K.; Leo, Karl

    2014-01-01

    The key active devices of future organic electronic circuits are organic thin film transistors (OTFTs). Reliability of OTFTs remains one of the most challenging obstacles to be overcome for broad commercial applications. In particular, bias stress was identified as the key instability under operation for numerous OTFT devices and interfaces. Despite a multitude of experimental observations, a comprehensive mechanism describing this behavior is still missing. Furthermore, controlled methods to overcome these instabilities are so far lacking. Here, we present the approach to control and significantly alleviate the bias stress effect by using molecular doping at low concentrations. For pentacene and silicon oxide as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias stress behavior is explained in terms of the shift of Fermi Level and, thus, exponentially reduced proton generation at the pentacene/oxide interface.

  7. Gate-set tomography and beyond

    NASA Astrophysics Data System (ADS)

    Blume-Kohout, Robin

    Four years ago, there was no reliable way to characterize and debug quantum gates. Process tomography required perfectly pre-calibrated gates, while randomized benchmarking only yielded an overall error rate. Gate-set tomography (GST) emerged around 2012-13 in several variants (most notably at IBM; see PRA 87, 062119) to address this need, providing complete and calibration-free characterization of gates. At Sandia, we have pushed the capabilities of GST well beyond these initial goals. In this talk, I'll demonstrate our open web interface, show how we characterize gates with accuracy at the Heisenberg limit, discuss how we put error bars on the results, and present experimental GST estimates with 1e-5 error bars. I'll also present preliminary results of GST on 2-qubit gates, including a brief survey of the tricks we use to make it possible. I'll conclude with an analysis of GST's limitations (e.g., it scales poorly), and the techniques under development for characterizing and debugging larger (3+ qubit) systems.

  8. VLSI reliability

    SciTech Connect

    Sabnis, A.G. )

    1990-01-01

    This book presents major topics in IC reliability from basic concepts to packaging issues. Other topics covered include failure analysis techniques, radiation effects, and reliability assurance and qualification. This book offers insight into the practical aspects of VLSI reliability.

  9. Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

    SciTech Connect

    Vedam, S.; Archambault, L.; Starkschall, G.; Mohan, R.; Beddar, S.

    2007-11-15

    and delivery gate thresholds to within 0.3%. For patient data analysis, differences between simulation and delivery gate thresholds are reported as a fraction of the total respiratory motion range. For the smaller phase interval, the differences between simulation and delivery gate thresholds are 8{+-}11% and 14{+-}21% with and without audio-visual biofeedback, respectively, when the simulation gate threshold is determined based on the mean respiratory displacement within the 40%-60% gating phase interval. For the longer phase interval, corresponding differences are 4{+-}7% and 8{+-}15% with and without audio-visual biofeedback, respectively. Alternatively, when the simulation gate threshold is determined based on the maximum average respiratory displacement within the gating phase interval, greater differences between simulation and delivery gate thresholds are observed. A relationship between retrospective simulation gate threshold and prospective delivery gate threshold for respiratory gating is established and validated for regular and nonregular respiratory motion. Using this relationship, the delivery gate threshold can be reliably estimated at the time of 4D CT simulation, thereby improving the accuracy and efficiency of respiratory-gated radiation delivery.

  10. Evaluation of hydrogen and ammonia gas mixtures with the suspended- gate field-effect transistor sensor array

    SciTech Connect

    Domansky, K.; Li, H.S.; Josowicz, M.; Janata, J.

    1995-12-01

    Generation of hydrogen represents a severe industrial hazard primarily because the mixture of hydrogen with air in the ratio 4.0--74.2 vol % is explosive. In some industrial applications, such as waste remediation, hydrogen, as a product of radiolysis and corrosion, occurs in the presence of ammonia, nitrous oxide, water vapor and other molecules. A low cost, reliable method for monitoring these gaseous mixtures is essential. Palladium-based layers have been used successfully as hydrogen sensitive layers in several potentiometric sensors for many years. Since the sensing mechanism is based on the catalytic decomposition of hydrogen molecules, other hydrogen-bearing gases can also produce a response. From this viewpoint, using an array of sensing elements with catalytic and noncatalytic chemically selective layers in these applications can be highly effective. Moreover, integration of this array on a single chip can be routinely achieved. The Suspended Gate Field-Effect Transistor (SGFET) is microfabricated in silicon. The metal gate of the transistor is separated from the substrate by an air gap. The chemically sensitive layer is electrodeposited on the bottom of the suspended gate. Chemical species can penetrate into the gate area and interact with the sensing layer. This interaction modulates the work function of the layer. The change in the work function results in the shift of the transistor threshold voltage. The measured threshold voltage shift is a function of the gas concentration in the sensor vicinity. By passing a small current through the suspended gate, it is possible to control the operating temperature of the sensing layer (up to 200{degrees}C) and, therefore, to modulate the sensor sensitivity, selectivity, response and recovery times. Due to the very low thermal mass, the heat is localized on the gate so that many devices can be operated on a single chip, each with the gate at different temperature.

  11. Steep sub-threshold current slope (∼2 mV/dec) Pt/Cu2S/Pt gated memristor with lon/Ioff > 100

    NASA Astrophysics Data System (ADS)

    Mou, N. I.; Zhang, Y.; Pai, P.; Tabib-Azar, M.

    2017-01-01

    Memristors with steep off-on transitions and high "on" currents are excellent candidates for very low power and efficient electronics. Owing to their switching mechanism based on ion motion and oxidation/reduction process, memristors bridge the gap between MEMS and MOSFETs. They have better reliability similar to MOSFETS and at the same time have the more desirable off-to-on current ratios of MEMS. Here we show that by adding a gate electrode to memristors, the SET/RESET voltages in electrochemical memristors can be controlled enabling their applications in circuits with high input/output isolations. We discuss devices with 2 mV/dec sub-threshold slope and show that the gate field effect can be used to modify the SET/RESET voltages considerably. In addition to enabling very low power switches using memristors, the gate can also be used as a global RESET.

  12. MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

    NASA Astrophysics Data System (ADS)

    Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

    2014-10-01

    Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

  13. Optical Logic Gates

    NASA Technical Reports Server (NTRS)

    Du Fresne, E. R.; Dowler, W. L.

    1985-01-01

    Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.

  14. Hydrogen storage on metal oxide model clusters using density-functional methods and reliable van der Waals corrections.

    PubMed

    Gebhardt, Julian; Viñes, Francesc; Bleiziffer, Patrick; Hieringer, Wolfgang; Görling, Andreas

    2014-03-21

    We investigate the capability of low-coordinated sites on small model clusters to act as active centers for hydrogen storage. A set of small magic clusters with the formula (XY)6 (X = Mg, Ba, Be, Zn, Cd, Na, Li, B and Y = O, Se, S, F, I, N) and a "drumlike" hexagonal shape showing a low coordination number of three was screened. Oxide clusters turned out to be the most promising candidates for hydrogen storage. For these ionic compounds we explored the suitability of different van der Waals (vdW) corrections to density-functional calculations by comparing the respective H2 physisorption profile to highly accurate CCSD(T) (Coupled Cluster Singles Doubles with perturbative Triples) calculations. The Grimme D3 vdW correction in combination with the Perdew-Burke-Ernzerhof exchange-correlation functional was found to be the best approach compared to CCSD(T) hydrogen physisorption profiles and is, therefore, suited to study these and other light metal oxide systems. H2 adsorption on sites of oxide model clusters is found to meet the adsorption energy criteria for H2 storage, with bond strengths ranging from 0.15 to 0.21 eV. Energy profiles and estimates of kinetic constants for the H2 splitting reaction reveal that H2 is likely to be adsorbed molecularly on sites of (MgO)6, (BaO)6, and (BeO)6 clusters, suggesting a rapid H2 uptake/release at operating temperatures and moderate pressures. The small mass of beryllium and magnesium makes such systems appealing for meeting the gravimetric criterion for H2 storage.

  15. Reliability properties of metal-oxide-semiconductor capacitors using LaAlO3 high-k dielectric

    NASA Astrophysics Data System (ADS)

    Yeh, Lingyen; Chang, Ingram Yin-Ku; Chen, Chun-Heng; Lee, Joseph Ya-Min

    2009-10-01

    In this study, metal-oxide-semiconductor (MOS) capacitors with high dielectric constant LaAlO3 film were fabricated. Furthermore, the characteristic time-to-breakdown, TBD, of the MOS capacitors was investigated. The TBD was measured and the corresponding Weibull slopes, β, of the MOS capacitors with various LaAlO3 thicknesses were calculated. In addition, a modified percolation model was proposed to consider the extrinsic factors of breakdown. These extrinsic factors were described by an equivalent reduction of the path-to-breakdown, tex, in the model. Using this model, the calculated tex of the MOS capacitor was 5.8 nm.

  16. 15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    15. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATES AND GATE ARMS, PIERS AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  17. 4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL VIEW OF TAINTER GATE PIER AND TAINTER GATE NO. 7 AND NON-SUBMERSIBLE TAINTER GATES, LOOKING WEST (UPSTREAM) - Upper Mississippi River 9-Foot Channel Project, Lock & Dam 26R, Alton, Madison County, IL

  18. 19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    19. DETAIL VIEW OF SUBMERSIBLE TAINTER GATE, SHOWING GATE ARM, PIER, TRUNNION PIN AND GATE GAUGE, LOOKING NORTH - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  19. 20. DETAIL VIEW OF TAINTER GATE, SHOWING GATE ARMS, PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    20. DETAIL VIEW OF TAINTER GATE, SHOWING GATE ARMS, PIERS, TRUNNION PINS, AND GATE GAUGE, LOOKING SOUTHWEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  20. 16. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, PIERS, BRIDGE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    16. DETAIL VIEW OF TAINTER GATE, SHOWING GATES, PIERS, BRIDGE GIRDERS AND ROLLER GATE BULKHEADS STORED ON PIER ABUTMENTS, LOOKING WEST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  1. 12. DETAIL VIEW OF ROLLER GATE, SHOWING GATE FLANGE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    12. DETAIL VIEW OF ROLLER GATE, SHOWING GATE FLANGE AND TUBE, ROLLER TRACK, CHAIN AND GATE HEATER, LOOKING EAST - Upper Mississippi River 9-Foot Channel Project, Lock & Dam No. 5, Minneiska, Winona County, MN

  2. 10. DETAIL VIEW OF ROLLER GATE, SHOWING GATE FLANGE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    10. DETAIL VIEW OF ROLLER GATE, SHOWING GATE FLANGE AND TUBE, ROLLER TRACK AND GATE HEATER, LOOKING SOUTHWEST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  3. An enzyme-free and DNA-based Feynman gate for logically reversible operation.

    PubMed

    Zhou, Chunyang; Wang, Kun; Fan, Daoqing; Wu, Changtong; Liu, Dali; Liu, Yaqing; Wang, Erkang

    2015-06-28

    A logically reversible Feynman gate was successfully realized under enzyme-free conditions by integrating graphene oxide and DNA for the first time. The gate has a one-to-one mapping function to identify inputs from the corresponding outputs. This type of reversible logic gate may have great potential applications in information processing and biosensing systems.

  4. Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects

    NASA Astrophysics Data System (ADS)

    Smaani, Billel; Latreche, Saida; Iñiguez, Benjamín

    2013-12-01

    In this paper, we present a compact model for undoped short-channel cylindrical surrounding-gate MOSFETs. The drain-current model is expressed as a function of the mobile charge density, which is calculated using the analytical expressions of the surface potential and the difference between surface and center potentials model. The short-channel effects are well incorporated in the drain-current model, such as the drain-induced barrier lowering, the charge sharing effect (VT Roll-off), the subthreshold slope degradation, and the channel length modulation. A comparison of the model results with 3D numerical simulations using Silvaco Atlas-TCAD presents a good agreement from subthreshold to strong inversion regime and for different bias voltages.

  5. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  6. Sliding-gate valve

    DOEpatents

    Usnick, George B.; Ward, Gene T.; Blair, Henry O.; Roberts, James W.; Warner, Terry N.

    1979-01-01

    This invention is a novel valve of the slidable-gate type. The valve is designed especially for long-term use with highly abrasive slurries. The sealing surfaces of the gate are shielded by the valve seats when the valve is fully open or closed, and the gate-to-seat clearance is swept with an inflowing purge gas while the gate is in transit. A preferred form of the valve includes an annular valve body containing an annular seat assembly defining a flow channel. The seat assembly comprises a first seat ring which is slidably and sealably mounted in the body, and a second seat ring which is tightly fitted in the body. These rings cooperatively define an annular gap which, together with passages in the valve body, forms a guideway extending normal to the channel. A plate-type gate is mounted for reciprocation in the guideway between positions where a portion of the plate closes the channel and where a circular aperture in the gate is in register with the channel. The valve casing includes opposed chambers which extend outwardly from the body along the axis of the guideway to accommodate the end portions of the gate. The chambers are sealed from atmosphere; when the gate is in transit, purge gas is admitted to the chambers and flows inwardly through the gate-to-seat-ring, clearance, minimizing buildup of process solids therein. A shaft reciprocated by an external actuator extends into one of the sealed chambers through a shaft seal and is coupled to an end of the gate. Means are provided for adjusting the clearance between the first seat ring and the gate while the valve is in service.

  7. Confirming Pseudomonas putida as a reliable bioassay for demonstrating biocompatibility enhancement by solar photo-oxidative processes of a biorecalcitrant effluent.

    PubMed

    García-Ripoll, A; Amat, A M; Arques, A; Vicente, R; Ballesteros Martín, M M; Pérez, J A Sánchez; Oller, I; Malato, S

    2009-03-15

    Experiments based on Vibrio fischeri, activated sludge and Pseudomonas putida have been employed to check variation in the biocompatibility of an aqueous solution of a commercial pesticide, along solar photo-oxidative process (TiO(2) and Fenton reagent). Activated sludge-based experiments have demonstrated a complete detoxification of the solution, although important toxicity is still detected according to the more sensitive V. fischeri assays. In parallel, the biodegradability of organic matter is strongly enhanced, with BOD(5)/COD ratio above 0.8. Bioassays run with P. putida have given similar trends, remarking the convenience of using P. putida culture as a reliable and reproducible method for assessing both toxicity and biodegradability, as a substitute to other more time consuming methods.

  8. Gates for electron confinement in Si/SiGe 2DEGs at cryogenic temperatures

    NASA Astrophysics Data System (ADS)

    Slinker, K. A.; Klein, L. J.; Goswami, S.; Truitt, J. L.; Savage, D. E.; Lagally, M. G.; van der Weide, D. W.; Coppersmith, S. N.; Eriksson, M. A.; Chu, J. O.; Ott, J. A.; Mooney, P. M.

    2004-03-01

    A major challenge is the fabrication of ultra-low leakage gates for 2DEG confinement in Si/SiGe at cryogenic temperatures. Here we report results on the fabrication of gates by four different methods: metallic Schottky gates, metal-oxide-silicon, metal-dielectric-silicon using spin-on glass, and lateral etch-defined gates. Lateral etch-defined gates are shown to produce quantum dots displaying Coulomb blockade. We discuss the prospects for producing similar structures using truly metallic gates in combination with etch-defined trenches.

  9. Adiabatically implementing quantum gates

    SciTech Connect

    Sun, Jie; Lu, Songfeng Liu, Fang

    2014-06-14

    We show that, through the approach of quantum adiabatic evolution, all of the usual quantum gates can be implemented efficiently, yielding running time of order O(1). This may be considered as a useful alternative to the standard quantum computing approach, which involves quantum gates transforming quantum states during the computing process.

  10. Optical NAND gate

    DOEpatents

    Skogen, Erik J.; Raring, James; Tauke-Pedretti, Anna

    2011-08-09

    An optical NAND gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator and a photodetector. One pair of the optical waveguide devices is electrically connected in parallel to operate as an optical AND gate; and the other pair of the optical waveguide devices is connected in series to operate as an optical NOT gate (i.e. an optical inverter). The optical NAND gate utilizes two digital optical inputs and a continuous light input to provide a NAND function output. The optical NAND gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  11. A quantum dot-labelled aptamer/graphene oxide system for the construction of a half-adder and half-subtractor with high resettability.

    PubMed

    Hu, Xianyun; Liu, Yuqian; Qu, Xiaojun; Sun, Qingjiang

    2017-10-18

    By a combination of quantum dot-labelled aptamers and graphene oxide, a hybrid molecular system was developed for the integration of multiple logic gates to implement half adder and half subtractor functions. On the merits of quantum dots, repetitious arithmetic operations and a reliable fluorescent switch were demonstrated.

  12. Improved Reading Gate For Vertical-Bloch-Line Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

  13. Hafnium dioxide gate dielectrics, metal gate electrodes, and phenomena occurring at their interfaces

    NASA Astrophysics Data System (ADS)

    Schaeffer, James Kenyon, III

    As metal-oxide-semiconductor field-effect transistor (MOSFET) gate lengths scale down below 45 nm, the gate oxide thickness approaches 1 nm equivalent oxide thickness. At this thickness, conventional silicon dioxide (SiO 2) gate dielectrics suffer from excessive gate leakage. Higher permittivity dielectrics are required to counter the increase in gate leakage. Hafnium dioxide (HfO2) has emerged as a promising dielectric candidate. HfO2 films deposited using metal organic chemical vapor deposition are being studied to determine the impact of process and annealing conditions on the physical and electrical properties of the gate dielectric. This study indicates that deposition and annealing temperatures influence the microstructure, density, impurity concentration, chemical environment of the impurities, and band-gap of the HfO2 dielectric. Correlations of the electrical and physical properties of the films indicate that impurities in the form of segregated carbon clusters, and low HfO2 density are detrimental to the leakage properties of the gate dielectric. Additionally, as the HfO2 thickness scales, the additional series capacitance due to poly-silicon depletion plays a larger roll in reducing the total gate capacitance. To solve this problem, high performance bulk MOSFETs will require dual metal gate electrodes possessing work functions near the silicon band edges for optimized drive current. This investigation evaluates TiN, Ta-Si-N, Ti-Al-N, WN, TaN, TaSi, Ir and IrO2 electrodes as candidate electrodes on HfO2 dielectrics. The metal-dielectric compatibility was studied by annealing the gate stacks at different temperatures. The physical stability and effective work functions of metal electrodes on HfO2 are discussed. Finally, Fermi level pinning of the metal is a barrier to identifying materials with appropriate threshold voltages. The contributions to the Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the

  14. Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

    2016-11-01

    Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

  15. Auditory sensory gating deficit and cortical thickness in schizophrenia.

    PubMed

    Thoma, R J; Hanlon, F M; Sanchez, N; Weisend, M P; Huang, M; Jones, A; Miller, G A; Canive, J M

    2004-11-30

    Both an EEG P50 sensory gating deficit and abnormalities of the temporal lobe structure are considered characteristic of schizophrenia. The standard P50 sensory gating measure does not foster differential assessment of left- and right-hemisphere contributions, but its analogous MEG M50 component may be used to measure gating of distinct auditory source dipoles localizing to left- and right-hemisphere primary auditory cortex. The present study sought to determine how sensory gating ratio may relate to cortical thickness at the site of the auditory dipole localization. A standard auditory paired-click paradigm was used during MEG for patients (n=22) and normal controls (n=11). Sensory gating ratios were determined by measuring the strength of the 50 ms response to the second click divided by that of the first click (S2/S1). Cortical thickness was assessed by two reliable raters using 3D sMRI. Results showed that: (1) patients had a P50 and left M50 sensory gating deficit relative to controls; (2) cortex in both hemispheres was thicker in the control group; (3) in schizophrenia, poorer left-hemisphere M50 sensory gating correlated with thinner left-hemisphere auditory cortical thickness; and (4) poorer right-hemisphere M50 auditory sensory gating ratio correlated with thinner right-hemisphere auditory cortical thickness in patients. The MEG-assessed hemisphere-specific auditory sensory gating ratio may be driven by this structural abnormality in auditory cortex.

  16. Melatonin modulates wireless (2.45 GHz)-induced oxidative injury through TRPM2 and voltage gated Ca(2+) channels in brain and dorsal root ganglion in rat.

    PubMed

    Nazıroğlu, M; Çelik, Ö; Özgül, C; Çiğ, B; Doğan, S; Bal, R; Gümral, N; Rodríguez, A B; Pariente, J A

    2012-02-01

    We aimed to investigate the protective effects of melatonin and 2.45 GHz electromagnetic radiation (EMR) on brain and dorsal root ganglion (DRG) neuron antioxidant redox system, Ca(2+) influx, cell viability and electroencephalography (EEG) records in the rat. Thirty two rats were equally divided into four different groups namely group A1: Cage control, group A2: Sham control, group B: 2.45 GHz EMR, group C: 2.45 GHz EMR+melatonin. Groups B and C were exposed to 2.45 GHz EMR during 60 min/day for 30 days. End of the experiments, EEG records and the brain cortex and DRG samples were taken. Lipid peroxidation (LP), cell viability and cytosolic Ca(2+) values in DRG neurons were higher in group B than in groups A1 and A2 although their concentrations were increased by melatonin, 2-aminoethyldiphenyl borinate (2-APB), diltiazem and verapamil supplementation. Spike numbers of EEG records in group C were lower than in group B. Brain cortex vitamin E concentration was higher in group C than in group B. In conclusion, Melatonin supplementation in DRG neurons and brain seems to have protective effects on the 2.45 GHz-induced increase Ca(2+) influx, EEG records and cell viability of the hormone through TRPM2 and voltage gated Ca(2+) channels. Copyright © 2011 Elsevier Inc. All rights reserved.

  17. Gallium arsenide processing for gate array logic

    NASA Astrophysics Data System (ADS)

    Cole, Eric D.

    1989-09-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  18. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  19. Gallium arsenide processing for gate array logic

    NASA Technical Reports Server (NTRS)

    Cole, Eric D.

    1989-01-01

    The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

  20. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

    PubMed Central

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-01-01

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs. PMID:26674338

  1. Fractioned exhaled nitric oxide (FE(NO)) is not a sufficiently reliable test for monitoring asthma in pregnancy.

    PubMed

    Nittner-Marszalska, Marita; Liebhart, Jerzy; Pawłowicz, Robert; Kazimierczak, Anna; Marszalska, Hanna; Kraus-Filarska, Maria; Panaszek, Bernard; Dor-Wojnarowska, Anna

    2013-09-01

    It has been reported that fractioned exhaled nitric oxide (FENO) can be used for monitoring airway inflammation and for asthma management but conclusions drawn by different researchers are controversial. The aim of our study was to evaluate the clinical usefulness of FENO assessment for monitoring asthma during pregnancy. We monitored 72 pregnant asthmatics aged 18-38years (Me=29 years) who underwent monthly investigations including: the level of asthma control according to GINA (Global Initiative for Asthma), the occurrence of exacerbations, ACT (Asthma Control Test), as well as FENO and spirometry measurements. In 50 women, during all visits, asthma was well-controlled. In the remaining 22 women, asthma was periodically uncontrolled. FENO measured at the beginning of the study did not show significant correlation with retrospectively evaluated asthma severity (r=0.07; p=0.97). An analysis of data collected during all 254 visits showed that FENO correlated significantly but weakly with ACT scores (r=0.25; p=0.0004) and FEV1 (r=0.21; p=0.0014). FENO at consecutive visits in women with well-controlled asthma (N=50) showed large variability expressed by median coefficient of variation (CV)=32.0% (Min 2.4%, Max 121.9%). This concerned both: atopic and nonatopic groups (35.5%; and 26.7%, respectively). Large FENO variability (35.5%) was also found in a subgroup of women (N=11) with ACT=25 constantly throughout the study. FENO measured at visits when women temporarily lost control of asthma (N=22; 38 visits), showed an increasing tendency (64.2 ppb; 9.5 ppb-188.3 ppb), but did not differ significantly (p=0.13) from measurements taken at visits during which asthma was well-controlled (27.6 ppb; 6.2 ppb-103.4 ppb). The comparison of FENO in consecutive months of pregnancy in women who had well-controlled asthma did not show significant differences in FENO values during the time of observation. The assessment of asthma during pregnancy by means of monitoring FENO is of

  2. Inversion gate capacitance of undoped single-gate and double-gate field-effect transistor geometries in the extreme quantum limit

    SciTech Connect

    Majumdar, Amlan

    2015-05-28

    We present first-principle analytical derivations and numerically modeled data to show that the gate capacitance per unit gate area C{sub G} of extremely thin undoped-channel single-gate and double-gate field-effect transistor geometries in the extreme quantum limit with single-subband occupancy can be written as 1/C{sub G} = 1/C{sub OX} + N{sub G}/C{sub DOS} + N{sub G}/ηC{sub WF}, where N{sub G} is the number of gates, C{sub OX} is the oxide capacitance per unit area, C{sub DOS} is the density-of-states capacitance per unit area, C{sub WF} is the wave function spreading capacitance per unit area, and η is a constant on the order of 1.

  3. 18. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    18. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARMS, GATE PIER AND DAM BRIDGE, LOOKING NORTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  4. 17. DETAIL VIEW OF NONSUBMERSIBLE TAINTER GATE, SHOWING GATE AND ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    17. DETAIL VIEW OF NON-SUBMERSIBLE TAINTER GATE, SHOWING GATE AND GATE ARM, GATE PIER AND DAM BRIDGE, LOOKING SOUTHEAST - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 8, On Mississippi River near Houston County, MN, Genoa, Vernon County, WI

  5. Optical NOR gate

    DOEpatents

    Skogen, Erik J.; Tauke-Pedretti, Anna

    2011-09-06

    An optical NOR gate is formed from two pair of optical waveguide devices on a substrate, with each pair of the optical waveguide devices consisting of an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical NOR gate utilizes two digital optical inputs and a continuous light input to provide a NOR function digital optical output. The optical NOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  6. Optical XOR gate

    SciTech Connect

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  7. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

    NASA Astrophysics Data System (ADS)

    Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

    2015-09-01

    In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

  8. Demonstrating 1 nm-oxide-equivalent-thickness HfO2/InSb structure with unpinning Fermi level and low gate leakage current density

    NASA Astrophysics Data System (ADS)

    Trinh, Hai-Dang; Lin, Yueh-Chin; Nguyen, Minh-Thuy; Nguyen, Hong-Quan; Duong, Quoc-Van; Luc, Quang-Ho; Wang, Shin-Yuan; Nguyen, Manh-Nghia; Yi Chang, Edward

    2013-09-01

    In this work, the band alignment, interface, and electrical characteristics of HfO2/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO2 layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO2/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10-4 A/cm-2. The Dit value of smaller than 1012 eV-1cm-2 has been obtained using conduction method.

  9. Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

    NASA Astrophysics Data System (ADS)

    Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

    2016-12-01

    The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

  10. Non-Adiabatic Holonomic Quantum Gates in an atomic system

    NASA Astrophysics Data System (ADS)

    Azimi Mousolou, Vahid; Canali, Carlo M.; Sjoqvist, Erik

    2012-02-01

    Quantum computation is essentially the implementation of a universal set of quantum gate operations on a set of qubits, which is reliable in the presence of noise. We propose a scheme to perform robust gates in an atomic four-level system using the idea of non-adiabatic holonomic quantum computation proposed in [1]. The gates are realized by applying sequences of short laser pulses that drive transitions between the four energy levels in such a way that the dynamical phases vanish. [4pt] [1] E. Sjoqvist, D.M. Tong, B. Hessmo, M. Johansson, K. Singh, arXiv:1107.5127v2 [quant-ph

  11. The human respiratory gate

    NASA Technical Reports Server (NTRS)

    Eckberg, Dwain L.

    2003-01-01

    Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

  12. Advanced insulated gate bipolar transistor gate drive

    DOEpatents

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  13. Gate contact resistive random access memory in nano scaled FinFET logic technologies

    NASA Astrophysics Data System (ADS)

    Hsu, Meng-Yin; Shih, Yi-Hong; Chih, Yue-Der; Lin, Chrong Jung; King, Ya-Chin

    2017-04-01

    A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gate contact plug and interlayer dielectric (ILD) in the middle, and a gate contact and an n-type epitaxial drain terminal as the top and bottom electrodes, respectively. It features low-voltage operation and reset current, compact cell size, and a stable read window. As a promising embedded NVM solution, the compact one transistor and one resistor (1T1R) cell is highly scalable as the technology node progresses. Excellent data retention and cycling capability have also been demonstrated by the reliability testing results. These superior characteristics make GC-RRAM one of a few viable candidates for logic NVM for future FinFET circuits.

  14. AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors with high on/off current ratio of over 5 × 1010 achieved by ozone pretreatment and using ozone oxidant for Al2O3 gate insulator

    NASA Astrophysics Data System (ADS)

    Tokuda, Hirokuni; Asubar, Joel T.; Kuzuhara, Masaaki

    2016-12-01

    This letter describes DC characteristics of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with Al2O3 deposited by atomic layer deposition (ALD) as gate dielectric. Comparison was made for the samples deposited using ozone (O3) or water as oxidant. The effect of pretreatment, where O3 was solely supplied prior to depositing Al2O3, was also investigated. The MIS-HEMT with O3 pretreatment and Al2O3 gate dielectric deposited using O3 as the oxidant exhibited the most desirable characteristics with an excellent high on/off current ratio of 7.1 × 1010, and a low sub-threshold swing (SS) of 73 mV/dec.

  15. Redox control of 20S proteasome gating.

    PubMed

    Silva, Gustavo M; Netto, Luis E S; Simões, Vanessa; Santos, Luiz F A; Gozzo, Fabio C; Demasi, Marcos A A; Oliveira, Cristiano L P; Bicev, Renata N; Klitzke, Clécio F; Sogayar, Mari C; Demasi, Marilene

    2012-06-01

    The proteasome is the primary contributor in intracellular proteolysis. Oxidized or unstructured proteins can be degraded via a ubiquitin- and ATP-independent process by the free 20S proteasome (20SPT). The mechanism by which these proteins enter the catalytic chamber is not understood thus far, although the 20SPT gating conformation is considered to be an important barrier to allowing proteins free entrance. We have previously shown that S-glutathiolation of the 20SPT is a post-translational modification affecting the proteasomal activities. The goal of this work was to investigate the mechanism that regulates 20SPT activity, which includes the identification of the Cys residues prone to S-glutathiolation. Modulation of 20SPT activity by proteasome gating is at least partially due to the S-glutathiolation of specific Cys residues. The gate was open when the 20SPT was S-glutathiolated, whereas following treatment with high concentrations of dithiothreitol, the gate was closed. S-glutathiolated 20SPT was more effective at degrading both oxidized and partially unfolded proteins than its reduced form. Only 2 out of 28 Cys were observed to be S-glutathiolated in the proteasomal α5 subunit of yeast cells grown to the stationary phase in glucose-containing medium. We demonstrate a redox post-translational regulatory mechanism controlling 20SPT activity. S-glutathiolation is a post-translational modification that triggers gate opening and thereby activates the proteolytic activities of free 20SPT. This process appears to be an important regulatory mechanism to intensify the removal of oxidized or unstructured proteins in stressful situations by a process independent of ubiquitination and ATP consumption. Antioxid. Redox Signal. 16, 1183-1194.

  16. Redox Control of 20S Proteasome Gating

    PubMed Central

    Silva, Gustavo M.; Simões, Vanessa; Santos, Luiz F.A.; Gozzo, Fabio C.; Demasi, Marcos A.A.; Oliveira, Cristiano L.P.; Bicev, Renata N.; Klitzke, Clécio F.; Sogayar, Mari C.

    2012-01-01

    Abstract The proteasome is the primary contributor in intracellular proteolysis. Oxidized or unstructured proteins can be degraded via a ubiquitin- and ATP-independent process by the free 20S proteasome (20SPT). The mechanism by which these proteins enter the catalytic chamber is not understood thus far, although the 20SPT gating conformation is considered to be an important barrier to allowing proteins free entrance. We have previously shown that S-glutathiolation of the 20SPT is a post-translational modification affecting the proteasomal activities. Aims: The goal of this work was to investigate the mechanism that regulates 20SPT activity, which includes the identification of the Cys residues prone to S-glutathiolation. Results: Modulation of 20SPT activity by proteasome gating is at least partially due to the S-glutathiolation of specific Cys residues. The gate was open when the 20SPT was S-glutathiolated, whereas following treatment with high concentrations of dithiothreitol, the gate was closed. S-glutathiolated 20SPT was more effective at degrading both oxidized and partially unfolded proteins than its reduced form. Only 2 out of 28 Cys were observed to be S-glutathiolated in the proteasomal α5 subunit of yeast cells grown to the stationary phase in glucose-containing medium. Innovation: We demonstrate a redox post-translational regulatory mechanism controlling 20SPT activity. Conclusion: S-glutathiolation is a post-translational modification that triggers gate opening and thereby activates the proteolytic activities of free 20SPT. This process appears to be an important regulatory mechanism to intensify the removal of oxidized or unstructured proteins in stressful situations by a process independent of ubiquitination and ATP consumption. Antioxid. Redox Signal. 16, 1183–1194. PMID:22229461

  17. Sidewall electrode TiO x /TiO x N y resistive random access memory with excellent memory window control and reliability using plasma oxidation and a novel degradation-detecting writing algorithm

    NASA Astrophysics Data System (ADS)

    Lai, Erh-Kun; Lee, Dai-Ying; Wu, Jau-Yi; Lee, Ming-Hsiu; Khwa, Win-San; Lin, Yu-Hsuan; Chen, Wei-Chen; Chiang, Kuang-Hao; Horng, Sheng-Fu; Gong, Jeng; Lung, Hsiang-Lan; Hsieh, Kuang-Yeu; Lu, Chih-Yuan

    2017-04-01

    A TiO x /TiO x N y resistive random access memory (ReRAM) with a sidewall bottom electrode (BE) is demonstrated for the first time. Several interesting characteristics that are very desirable for high reliability memory applications are observed: (1) a stable RESET and SET resistance switching window even without write verification, (2) good 250 °C data retention, (3) ReRAM switching instability after cycling is monitored and corrected, resulting in good reliability, and (4) using only complementary metal oxide semiconductor (CMOS) familiar materials and processes, thus very manufacture-friendly. The thickness and quality of TiO x and TiO x N y are well controlled by plasma oxidation, and a large resistance switching window (>10×), a low operation voltage, and good reliability are realized.

  18. Low interfacial trap density and sub-nm equivalent oxide thickness in In{sub 0.53}Ga{sub 0.47}As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO{sub 2}/Al{sub 2}O{sub 3} as gate dielectrics

    SciTech Connect

    Chu, L. K.; Merckling, C.; Dekoster, J.; Caymax, M.; Alian, A.; Heyns, M.; Kwo, J.; Hong, M.

    2011-07-25

    We investigated the passivation of In{sub 0.53}Ga{sub 0.47}As (001) surface by molecular beam epitaxy techniques. After growth of strained In{sub 0.53}Ga{sub 0.47}As on InP (001) substrate, HfO{sub 2}/Al{sub 2}O{sub 3} high-{kappa} oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (D{sub it}) of the Al{sub 2}O{sub 3}/In{sub 0.53}Ga{sub 0.47}As interface have been revealed by conductance measurement, indicating a downward D{sub it} profile from the energy close to the valence band (medium 10{sup 12} cm{sup -2}eV{sup -1}) towards that close to the conduction band (10{sup 11} cm{sup -2}eV{sup -1}). The low D{sub it}'s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO{sub 2} has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO{sub 2} thickness (dielectric constant of HfO{sub 2}{approx}20) and the remained low D{sub it}'s due to the thin Al{sub 2}O{sub 3} passivation layer. The sample with HfO{sub 2} (3.4 nm)/Al{sub 2}O{sub 3} (1.2 nm) as the gate dielectrics has exhibited an equivalent oxide thickness of {approx}0.93 nm.

  19. Impact of transient currents caused by alternating drain stress in oxide semiconductors.

    PubMed

    Lee, Hyeon-Jun; Cho, Sung Haeng; Abe, Katsumi; Lee, Myoung-Jae; Jung, Minkyung

    2017-08-29

    Reliability issues associated with driving metal-oxide semiconductor thin film transistors (TFTs), which may arise from various sequential drain/gate pulse voltage stresses and/or certain environmental parameters, have not received much attention due to the competing desire to characterise the shift in the transistor characteristics caused by gate charging. In this paper, we report on the reliability of these devices under AC bias stress conditions because this is one of the major sources of failure. In our analysis, we investigate the effects of the driving frequency, pulse shape, strength of the applied electric field, and channel current, and the results are compared with those from a general reliability test in which the devices were subjected to negative/positive bias, temperature, and illumination stresses, which are known to cause the most stress to oxide semiconductor TFTs. We also report on the key factors that affect the sub-gap defect states, and suggest a possible origin of the current degradation observed with an AC drive. Circuit designers should apply a similar discovery and analysis method to ensure the reliable design of integrated circuits with oxide semiconductor devices, such as the gate driver circuits used in display devices.

  20. Quantification of F2-isoprostanes as a reliable index of oxidative stress in vivo using gas chromatography-mass spectrometry (GC-MS) method.

    PubMed

    Liu, Wei; Morrow, Jason D; Yin, Huiyong

    2009-10-15

    Free radical-induced lipid peroxidation has been implicated in a number of human diseases including atherosclerosis, cancer, and neurodegenerative diseases. F(2)-Isoprostanes (IsoPs) are isomers of prostaglandin PGF(2alpha) that are generated in vivo from the free radical-initiated peroxidation of arachidonic acid independent of cyclooxygenase enzymes. Since the discovery of the IsoPs in the early 1990s, a large body of evidence has been accumulated to indicate that quantification of these F(2)-IsoPs represents the most reliable biomarker to assess oxidative stress in vivo. A variety of analytical approaches have been developed for the quantification of these novel compounds; these methods include mass spectrometry (MS) detection coupled to gas chromatography (GC) or liquid chromatography (LC) separation, and detection using immunological approaches. This article summarizes our current methodology to quantify F(2)-IsoPs in biological fluids and tissues using GC-MS. This method includes solid-phase extraction (SPE), thin-layer chromatography (TLC) purification, chemical derivatization, and MS detection using negative ion chemical ionization (NICI) coupled with GC. The protocol described herein has been optimized and validated to provide the best sensitivity and selectivity for quantification of F(2)-IsoPs from a variety of biological sources.

  1. Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal-oxide-silicon fin field-effect transistors

    NASA Astrophysics Data System (ADS)

    Mizubayashi, Wataru; Onoda, Hiroshi; Nakashima, Yoshiki; Ishikawa, Yuki; Matsukawa, Takashi; Endo, Kazuhiko; Liu, Yongxun; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Migita, Shinji; Morita, Yukinori; Ota, Hiroyuki; Masahara, Meishoku

    2015-04-01

    We have investigated the impact of heated ion implantation (I/I) on the performance and reliability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) fin field-effect transistors (FinFETs). An implantation temperature equal to and higher than 400 °C is needed to maintain the crystallinity of the Si substrate during I/I within the experimental conditions of ion species, implantation energy, and ion dose in this study. By heated I/I at 500 °C, the 11-nm-thick SOI layer perfectly maintains the crystallinity even after I/I, and a defect-free crystal is obtained by activation annealing. It was clarified that the cap layer is essential for the suppression of the out-diffusion during heated I/I. Heated I/I on the source and drain improves the on-current-off-current (Ion-Ioff), threshold voltage (Vth) variability, and bias temperature instability (BTI) characteristics of nMOS and pMOS FinFETs as compared with those after room-temperature I/I.

  2. Round-robin evaluation of a solid-phase microextraction-gas chromatographic method for reliable determination of trace level ethylene oxide in sterilized medical devices.

    PubMed

    Harper, Thomas; Cushinotto, Lisa; Blaszko, Nancy; Arinaga, Julie; Davis, Frank; Cummins, Calvin; DiCicco, Michael

    2008-02-01

    Medical devices that are sterilized with ethylene oxide (EtO) retain small quantities of EtO residuals, which may cause negative systemic and local irritating effects, and must be accurately quantified to ensure non-toxicity. The goal of this round-robin study is to investigate the capability of a novel solid-phase microextraction-gas chromatographic (SPME-GC) method for trace-level EtO residuals analysis: three independent laboratories conducted a guided experiment using this SPME-GC method, in assessing method performance, ruggedness and the feasibility of SPME fibers. These were satisfactory across the independent laboratories, at the 0.05-5.00 ppm EtO range. This method was then successfully applied to analyze EtO residuals in several sterilized/aerated medical devices of various polymeric composition, reliably detecting and quantifying the trace levels of EtO residuals present ( approximately 0.05 ppm EtO). SPME is a feasible alternative for quantifying trace-level EtO residuals in sterilized medical devices, thereby lowering the limit of quantification (LOQ) by as much as two to three orders of magnitude over the current GC methodology of direct liquid injection.

  3. Exceptional capability of nanosized CeO(2) materials to "dissolve" lanthanide oxides established by time-gated excitation and emission spectroscopy.

    PubMed

    Tiseanu, Carmen; Parvulescu, Vasile; Avram, Daniel; Cojocaru, Bogdan; Sanchez-Dominguez, Margarita

    2014-05-28

    The atomic scale homogeneity of Ce and Zr oxygen bonds represents the main reason for enhanced total oxygen storage capability of CeO2-ZrO2 (Ce/Zr = 1) as compared to that of CeO2. Here, we demonstrate that the addition of 10% Eu(3+) by wet impregnation on preformed nanosized CeO2-ZrO2 (Ce/Zr = 1) followed by calcination induces a remarkable homogeneity of 10% Eu(3+)-CeO2-ZrO2 solid solution. By use of time-resolved emission and excitation spectroscopies, the improvement of the nanoscale chemical and structural homogeneity of 10% Eu(3+)-CeO2-ZrO2 calcined at 1000 as compared to sample calcined at 750 °C is demonstrated. Based on the comparison of luminescence properties of 10% Eu(3+) impregnated on preformed nanosized CeO2-ZrO2 and CeO2, we also show that the presence of zirconium does not only preserve the ability of cerium oxide to "dissolve" lanthanide oxide, but also determines an important stabilization of defects (oxygen vacancies) generated upon Eu(3+) doping.

  4. Demonstrating 1 nm-oxide-equivalent-thickness HfO{sub 2}/InSb structure with unpinning Fermi level and low gate leakage current density

    SciTech Connect

    Trinh, Hai-Dang; Lin, Yueh-Chin; Nguyen, Hong-Quan; Luc, Quang-Ho; Nguyen, Minh-Thuy; Duong, Quoc-Van; Nguyen, Manh-Nghia; Wang, Shin-Yuan; Yi Chang, Edward

    2013-09-30

    In this work, the band alignment, interface, and electrical characteristics of HfO{sub 2}/InSb metal-oxide-semiconductor structure have been investigated. By using x-ray photoelectron spectroscopy analysis, the conduction band offset of 1.78 ± 0.1 eV and valence band offset of 3.35 ± 0.1 eV have been extracted. The transmission electron microscopy analysis has shown that HfO{sub 2} layer would be a good diffusion barrier for InSb. As a result, 1 nm equivalent-oxide-thickness in the 4 nm HfO{sub 2}/InSb structure has been demonstrated with unpinning Fermi level and low leakage current of 10{sup −4} A/cm{sup −2}. The D{sub it} value of smaller than 10{sup 12} eV{sup −1}cm{sup −2} has been obtained using conduction method.

  5. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    PubMed

    Khan, Z N; Ahmed, S; Ali, M

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  6. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

    PubMed Central

    Khan, Z. N.; Ahmed, S.; Ali, M.

    2016-01-01

    Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

  7. Reliability Design Handbook

    DTIC Science & Technology

    1976-03-01

    prediction, failure modes and effects analysis ( FMEA ) and reliability growth techniques represent those prediction and design evaluation methods that...Assessment Production Operation Ö Maintenance MIL-HDBK- 217 Bayesian Techniques Probabilistic Design FMEA I R Growth " I...devices suffer thermal aging; oxidation and other chemical reactions are enhanced; viscosity reduction and evaporation of lubricants are problems

  8. CFTR Gating I

    PubMed Central

    Bompadre, Silvia G.; Ai, Tomohiko; Cho, Jeong Han; Wang, Xiaohui; Sohma, Yoshiro; Li, Min; Hwang, Tzyh-Chang

    2005-01-01

    The CFTR chloride channel is activated by phosphorylation of serine residues in the regulatory (R) domain and then gated by ATP binding and hydrolysis at the nucleotide binding domains (NBDs). Studies of the ATP-dependent gating process in excised inside-out patches are very often hampered by channel rundown partly caused by membrane-associated phosphatases. Since the severed ΔR-CFTR, whose R domain is completely removed, can bypass the phosphorylation-dependent regulation, this mutant channel might be a useful tool to explore the gating mechanisms of CFTR. To this end, we investigated the regulation and gating of the ΔR-CFTR expressed in Chinese hamster ovary cells. In the cell-attached mode, basal ΔR-CFTR currents were always obtained in the absence of cAMP agonists. Application of cAMP agonists or PMA, a PKC activator, failed to affect the activity, indicating that the activity of ΔR-CFTR channels is indeed phosphorylation independent. Consistent with this conclusion, in excised inside-out patches, application of the catalytic subunit of PKA did not affect ATP-induced currents. Similarities of ATP-dependent gating between wild type and ΔR-CFTR make this phosphorylation-independent mutant a useful system to explore more extensively the gating mechanisms of CFTR. Using the ΔR-CFTR construct, we studied the inhibitory effect of ADP on CFTR gating. The Ki for ADP increases as the [ATP] is increased, suggesting a competitive mechanism of inhibition. Single channel kinetic analysis reveals a new closed state in the presence of ADP, consistent with a kinetic mechanism by which ADP binds at the same site as ATP for channel opening. Moreover, we found that the open time of the channel is shortened by as much as 54% in the presence of ADP. This unexpected result suggests another ADP binding site that modulates channel closing. PMID:15767295

  9. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  10. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  11. Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

    NASA Astrophysics Data System (ADS)

    Lina, Shi; Yiqi, Zhuang; Cong, Li; Dechang, Li

    2014-03-01

    An analytical direct tunneling gate current model for cylindrical surrounding gate (CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current. Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

  12. Electrolytic gate for quantum efficiency enhancement in thinned CCDs

    NASA Astrophysics Data System (ADS)

    Damento, Michael A.; Watson, Mary; Sims, Gary R.

    1993-07-01

    A transparent, semi-solid, electrolytic gate has been applied to the backside of thinned CCDs for quantum efficiency enhancement. The gate is applied by spreading a water solution of phosphoric acid and polyvinyl alcohol onto the silicon and drying it to form a thin plastic film. When a negative voltage of less than one volt with respect to substrate ground is applied to the gate, a QE pinned condition (100% internal quantum efficiency) is produced. An insulating layer is not needed with this gate (as it is with electronic conductors) since a threshold voltage of about 1.2 V is required before conduction into the silicon can occur. The mechanism of charging is believed to involve a pile-up of negative ions at the silicon-electrolyte interface which compensates for the positive oxide charge. Conduction into the silicon at low voltages is restricted by the oxidation potential of the negative ions in the electrolyte.

  13. A nanomechanical Fredkin gate.

    PubMed

    Wenzler, Josef-Stefan; Dunn, Tyler; Toffoli, Tommaso; Mohanty, Pritiraj

    2014-01-08

    Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing.

  14. 2. CANNON GATES. DETAIL OF NORTHWEST GATE STONE WALL TO ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    2. CANNON GATES. DETAIL OF NORTHWEST GATE STONE WALL TO LEFT IS A REMNANT OF THE ORIGINAL FACILITY BOUNDARY FENCE. IT IS CONSTRUCTED IN BLUE PUDDING STONE. - Picatinny Arsenal, State Route 15 near I-80, Dover, Morris County, NJ

  15. 7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    7. DETAIL VIEW OF DAM, SHOWING ROLLER GATES, GATE PIERS, HEADHOUSES AND DAM BRIDGE, LOOKING NORTHWEST, UPSTREAM - Upper Mississippi River 9-Foot Channel, Lock & Dam No. 9, Lynxville, Crawford County, WI

  16. Amplifying genetic logic gates.

    PubMed

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  17. Cardiac gated ventilation

    SciTech Connect

    Hanson, C.W. III; Hoffman, E.A.

    1995-12-31

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart.

  18. Review paper: Transparent amorphous oxide semiconductor thin film transistor

    NASA Astrophysics Data System (ADS)

    Kwon, Jang-Yeon; Lee, Do-Joong; Kim, Ki-Bum

    2011-03-01

    Thin film transistors (TFTs) with oxide semiconductors have drawn great attention in the last few years, especially for large area electronic applications, such as high resolution active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs), because of their high electron mobility and spatial uniform property. This paper reviews and summarizes recent emerging reports that include potential applications, oxide semiconductor materials, and the impact of the fabrication process on electrical performance. We also address the stability behavior of such devices under bias/illumination stress and critical factors related to reliability, such as the gate insulator, the ambient and the device structure.

  19. On the Asymmetric Splitting of CBED HOLZ Lines under the Gate of Recessed SiGe Source/Drain Transistors

    NASA Astrophysics Data System (ADS)

    Benedetti, A.; Bender, H.

    The behaviour of the CBED HOLZ line splitting under the gate of transistor structures with recessed SiGe in the source/drain regions is investigated. Structures with nitride/oxide dummy gates or with poly gates and nitride spacers are studied. In the gate region as well as below the SiGe, splitting of the HOLZ lines in the CBED patterns is observed with increasing magnitude towards the interface. The splitting under the gate shows an asymmetry for equivalent lines which inverts along horizontal cutlines under the gate. The behaviour is explained by a 3-dimensional relaxation of the stress.

  20. Investigation of carbonitrided components of the valve gates of Christmas trees and tubing heads

    SciTech Connect

    Kakhramanov, K.T.; Fataliev, N.S.; Levitan, Y.A.; Safarov, R.S.

    1985-07-01

    The authors evaluate the effectiveness of carbonitride hardening of the valve gates of Christmas trees and tubing heads. Measurements of microhardness, resistance to seizing, corrosion resistance, and durability demonstrate that carbonitriding helps to ensure strength, tightness, and reliable operation of the gate in the pressure range up to 35 MPa. Therefore, gates with carbonitrided components are durable and fully satisfy the requirements of the technique and technology of operation.

  1. Adiabatic gate teleportation.

    PubMed

    Bacon, Dave; Flammia, Steven T

    2009-09-18

    The difficulty in producing precisely timed and controlled quantum gates is a significant source of error in many physical implementations of quantum computers. Here we introduce a simple universal primitive, adiabatic gate teleportation, which is robust to timing errors and many control errors and maintains a constant energy gap throughout the computation above a degenerate ground state space. This construction allows for geometric robustness based upon the control of two independent qubit interactions. Further, our piecewise adiabatic evolution easily relates to the quantum circuit model, enabling the use of standard methods from fault-tolerance theory for establishing thresholds.

  2. Outlet side of gate, showing the Radial Gate, hoist mechanism ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Outlet side of gate, showing the Radial Gate, hoist mechanism and concrete walkway across the canal. The concrete baffle separating the afterbay and the cipoletti weir is in the foreground - Wellton-Mohawk Irrigation System, Radial Gate Check with Drop, Wellton Canal 9.9, West of Avenue 34 East & north of County Ninth Street, Wellton, Yuma County, AZ

  3. Exterior, looking northwest towards Main Gate, Gate House on left, ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking northwest towards Main Gate, Gate House on left, Technical Equipment Building (Building 5760) in background to right - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  4. Exterior, looking southeast from within compound towards Main Gate, Gate ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    Exterior, looking southeast from within compound towards Main Gate, Gate House center left - Beale Air Force Base, Perimeter Acquisition Vehicle Entry Phased-Array Warning System, Gate House, End of Spencer Paul Road, north of Warren Shingle Road (14th Street), Marysville, Yuba County, CA

  5. Reliability training

    NASA Technical Reports Server (NTRS)

    Lalli, Vincent R. (Editor); Malec, Henry A. (Editor); Dillard, Richard B.; Wong, Kam L.; Barber, Frank J.; Barina, Frank J.

    1992-01-01

    Discussed here is failure physics, the study of how products, hardware, software, and systems fail and what can be done about it. The intent is to impart useful information, to extend the limits of production capability, and to assist in achieving low cost reliable products. A review of reliability for the years 1940 to 2000 is given. Next, a review of mathematics is given as well as a description of what elements contribute to product failures. Basic reliability theory and the disciplines that allow us to control and eliminate failures are elucidated.

  6. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    NASA Astrophysics Data System (ADS)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  7. Leaf senescence signaling: the Ca2+-conducting Arabidopsis cyclic nucleotide gated channel2 acts through nitric oxide to repress senescence programming.

    PubMed

    Ma, Wei; Smigel, Andries; Walker, Robin K; Moeder, Wolfgang; Yoshioka, Keiko; Berkowitz, Gerald A

    2010-10-01

    Ca(2+) and nitric oxide (NO) are essential components involved in plant senescence signaling cascades. In other signaling pathways, NO generation can be dependent on cytosolic Ca(2+). The Arabidopsis (Arabidopsis thaliana) mutant dnd1 lacks a plasma membrane-localized cation channel (CNGC2). We recently demonstrated that this channel affects plant response to pathogens through a signaling cascade involving Ca(2+) modulation of NO generation; the pathogen response phenotype of dnd1 can be complemented by application of a NO donor. At present, the interrelationship between Ca(2+) and NO generation in plant cells during leaf senescence remains unclear. Here, we use dnd1 plants to present genetic evidence consistent with the hypothesis that Ca(2+) uptake and NO production play pivotal roles in plant leaf senescence. Leaf Ca(2+) accumulation is reduced in dnd1 leaves compared to the wild type. Early senescence-associated phenotypes (such as loss of chlorophyll, expression level of senescence-associated genes, H(2)O(2) generation, lipid peroxidation, tissue necrosis, and increased salicylic acid levels) were more prominent in dnd1 leaves compared to the wild type. Application of a Ca(2+) channel blocker hastened senescence of detached wild-type leaves maintained in the dark, increasing the rate of chlorophyll loss, expression of a senescence-associated gene, and lipid peroxidation. Pharmacological manipulation of Ca(2+) signaling provides evidence consistent with genetic studies of the relationship between Ca(2+) signaling and senescence with the dnd1 mutant. Basal levels of NO in dnd1 leaf tissue were lower than that in leaves of wild-type plants. Application of a NO donor effectively rescues many dnd1 senescence-related phenotypes. Our work demonstrates that the CNGC2 channel is involved in Ca(2+) uptake during plant development beyond its role in pathogen defense response signaling. Work presented here suggests that this function of CNGC2 may impact downstream basal

  8. Leaf Senescence Signaling: The Ca2+-Conducting Arabidopsis Cyclic Nucleotide Gated Channel2 Acts through Nitric Oxide to Repress Senescence Programming1[W][OA

    PubMed Central

    Ma, Wei; Smigel, Andries; Walker, Robin K.; Moeder, Wolfgang; Yoshioka, Keiko; Berkowitz, Gerald A.

    2010-01-01

    Ca2+ and nitric oxide (NO) are essential components involved in plant senescence signaling cascades. In other signaling pathways, NO generation can be dependent on cytosolic Ca2+. The Arabidopsis (Arabidopsis thaliana) mutant dnd1 lacks a plasma membrane-localized cation channel (CNGC2). We recently demonstrated that this channel affects plant response to pathogens through a signaling cascade involving Ca2+ modulation of NO generation; the pathogen response phenotype of dnd1 can be complemented by application of a NO donor. At present, the interrelationship between Ca2+ and NO generation in plant cells during leaf senescence remains unclear. Here, we use dnd1 plants to present genetic evidence consistent with the hypothesis that Ca2+ uptake and NO production play pivotal roles in plant leaf senescence. Leaf Ca2+ accumulation is reduced in dnd1 leaves compared to the wild type. Early senescence-associated phenotypes (such as loss of chlorophyll, expression level of senescence-associated genes, H2O2 generation, lipid peroxidation, tissue necrosis, and increased salicylic acid levels) were more prominent in dnd1 leaves compared to the wild type. Application of a Ca2+ channel blocker hastened senescence of detached wild-type leaves maintained in the dark, increasing the rate of chlorophyll loss, expression of a senescence-associated gene, and lipid peroxidation. Pharmacological manipulation of Ca2+ signaling provides evidence consistent with genetic studies of the relationship between Ca2+ signaling and senescence with the dnd1 mutant. Basal levels of NO in dnd1 leaf tissue were lower than that in leaves of wild-type plants. Application of a NO donor effectively rescues many dnd1 senescence-related phenotypes. Our work demonstrates that the CNGC2 channel is involved in Ca2+ uptake during plant development beyond its role in pathogen defense response signaling. Work presented here suggests that this function of CNGC2 may impact downstream basal NO production in addition

  9. Person Reliability

    ERIC Educational Resources Information Center

    Lumsden, James

    1977-01-01

    Person changes can be of three kinds: developmental trends, swells, and tremors. Person unreliability in the tremor sense (momentary fluctuations) can be estimated from person characteristic curves. Average person reliability for groups can be compared from item characteristic curves. (Author)

  10. Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

    PubMed

    Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

    2017-04-12

    The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10(6), effective mobility up to 30 cm(2) V(-1) s(-1), small hysteresis, and small subthreshold swing (90-140 mV dec(-1)), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 Vdd = 1 V) and a voltage gain as high as 30 (at Vdd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at Vdd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

  11. Reliability automation tool (RAT) for fault tolerance computation

    NASA Astrophysics Data System (ADS)

    Singh, N. S. S.; Hamid, N. H.; Asirvadam, V. S.

    2012-09-01

    As CMOS transistors reduced in size, the circuit built using these nano-scale transistors naturally becomes less reliable. The reliability reduction, which is the measure of circuit performance, has brought up so many challenges in designing modern logic integrated circuit. Therefore, reliability modeling is increasingly important subject to be considered in designing modern logic integrated circuit. This drives a need to compute reliability measures for nano-scale circuits. This paper looks into the development of reliability automation tool (RAT) for circuit's reliability computation. The tool is developed using Matlab programming language based on the reliability evaluation model called Probabilistic Transfer Matrix (PTM). RAT allows users to significantly speed-up the reliability assessments of nano-scale circuits. Users have to provide circuit's netlist as the input to RAT for its reliability computation. The netlist signifies the circuit's description in terms of Gate Profile Matrix (GPM), Adjacency Computation Matrix (ACM) and Grid Layout Matrix (GLM). GPM, ACM and GLM indicate the types of logic gates, the interconnection between these logic gates and the layout matrix of these logic gates respectively in a given circuit design. Here, the reliability assessment by RAT is carried out on Full Adder circuit as the benchmark test circuit.

  12. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  13. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  14. The four-gate transistor

    NASA Technical Reports Server (NTRS)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  15. Stanford, Duke, Rice,... and Gates?

    ERIC Educational Resources Information Center

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  16. Modeling and simulation of floating gate nanocrystal FET devices and circuits

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed A. M.

    The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

  17. Nanoparticle Based Logic Gates

    NASA Astrophysics Data System (ADS)

    Berven, Christopher; Wybourne, Martin; Longstreth, Lydia

    2003-05-01

    Ligand stabilized gold nanoparticles have novel properties that can be exploited for their use as possible building blocks for room-temperature single electron devices. With a core of 70 gold atoms or less (diameter <= 1.4 nm), the self-capacitance of these particles is a fraction of an atto-Farad. This small capacitance translates into an electrostatic charging energy well in excess of the thermal energy at room temperature. Single electron behavior has been demonstrated in one- and two-dimensional arrays of nanoparticles. In traditional single electron devices, the self-capacitance is negligible, whereas the self-capacitance in nanoparticle based devices can be the dominant capacitance. This means that the effect of charging a nanoparticle chain is highly localized which is in contrast to traditional single electron devices where the induced potential due to an excess electron on an island is felt by many neighboring islands. As a result, the current-voltage characteristics and plots of stable electron occupancy in the arrays have different behavior to that found in traditional devices. We show that this new regime of tunneling behavior can be exploited to create a novel family of single-electron logic gate devices. Using numerical simulation we have found that when a one-dimensional array of nanoparticles is gated in an electron-pump arrangement and properly biased, the behavior is that of an AND gate. The addition of an inverter circuit results in NAND gate behavior, the inverter providing the power necessary for the cascading of multiple NAND gates and the generation of arbitrary logic circuits.

  18. Dosimetry applications in GATE Monte Carlo toolkit.

    PubMed

    Papadimitroulas, Panagiotis

    2017-02-21

    Monte Carlo (MC) simulations are a well-established method for studying physical processes in medical physics. The purpose of this review is to present GATE dosimetry applications on diagnostic and therapeutic simulated protocols. There is a significant need for accurate quantification of the absorbed dose in several specific applications such as preclinical and pediatric studies. GATE is an open-source MC toolkit for simulating imaging, radiotherapy (RT) and dosimetry applications in a user-friendly environment, which is well validated and widely accepted by the scientific community. In RT applications, during treatment planning, it is essential to accurately assess the deposited energy and the absorbed dose per tissue/organ of interest, as well as the local statistical uncertainty. Several types of realistic dosimetric applications are described including: molecular imaging, radio-immunotherapy, radiotherapy and brachytherapy. GATE has been efficiently used in several applications, such as Dose Point Kernels, S-values, Brachytherapy parameters, and has been compared against various MC codes which are considered as standard tools for decades. Furthermore, the presented studies show reliable modeling of particle beams when comparing experimental with simulated data. Examples of different dosimetric protocols are reported for individualized dosimetry and simulations combining imaging and therapy dose monitoring, with the use of modern computational phantoms. Personalization of medical protocols can be achieved by combining GATE MC simulations with anthropomorphic computational models and clinical anatomical data. This is a review study, covering several dosimetric applications of GATE, and the different tools used for modeling realistic clinical acquisitions with accurate dose assessment. Copyright © 2017 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

  19. Self-aligned inversion n-channel In 0.2Ga 0.8As/GaAs metal-oxide-semiconductor field-effect-transistors with TiN gate and Ga 2O 3(Gd 2O 3) dielectric

    NASA Astrophysics Data System (ADS)

    Chen, C. P.; Lin, T. D.; Lee, Y. J.; Chang, Y. C.; Hong, M.; Kwo, J.

    2008-10-01

    A self-aligned process for fabricating inversion n-channel metal-oxide-semiconductor field-effect-transistors (MOSFET's) of strained In 0.2Ga 0.8As on GaAs using TiN as gate metal and Ga 2O 3(Gd 2O 3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of <10 -7 A/cm 2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ˜10 5 in drain current. For comparison, a TiN/Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10 -8-10 -9 A/cm 2, well-behaved capacitance-voltage ( C- V) characteristics giving a high dielectric constant of ˜16 and a low interfacial density of state of ˜(2˜6) × 10 11 cm -2 eV -1, and an atomically sharp smooth Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As interface.

  20. Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

    NASA Technical Reports Server (NTRS)

    Lauenstein, Jean-Marie

    2011-01-01

    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR