Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Dissociating Working Memory Updating and Automatic Updating: The Reference-Back Paradigm

ERIC Educational Resources Information Center

Rac-Lubashevsky, Rachel; Kessler, Yoav

2016-01-01

Working memory (WM) updating is a controlled process through which relevant information in the environment is selected to enter the gate to WM and substitute its contents. We suggest that there is also an automatic form of updating, which influences performance in many tasks and is primarily manifested in reaction time sequential effects. The goal…

Strategy Selection for Cognitive Skill Acquisition Depends on Task Demands and Working Memory Capacity

ERIC Educational Resources Information Center

Hinze, Scott R.; Bunting, Michael F; Pellegrino, James W.

2009-01-01

The involvement of working memory capacity (WMC) in ruled-based cognitive skill acquisition is well-established, but the duration of its involvement and its role in learning strategy selection are less certain. Participants (N=610) learned four logic rules, their corresponding symbols, or logic gates, and the appropriate input-output combinations…

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

2016-05-01

The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00505e

Selective updating of working memory content modulates meso-cortico-striatal activity.

PubMed

Murty, Vishnu P; Sambataro, Fabio; Radulescu, Eugenia; Altamura, Mario; Iudicello, Jennifer; Zoltick, Bradley; Weinberger, Daniel R; Goldberg, Terry E; Mattay, Venkata S

2011-08-01

Accumulating evidence from non-human primates and computational modeling suggests that dopaminergic signals arising from the midbrain (substantia nigra/ventral tegmental area) mediate striatal gating of the prefrontal cortex during the selective updating of working memory. Using event-related functional magnetic resonance imaging, we explored the neural mechanisms underlying the selective updating of information stored in working memory. Participants were scanned during a novel working memory task that parses the neurophysiology underlying working memory maintenance, overwriting, and selective updating. Analyses revealed a functionally coupled network consisting of a midbrain region encompassing the substantia nigra/ventral tegmental area, caudate, and dorsolateral prefrontal cortex that was selectively engaged during working memory updating compared to the overwriting and maintenance of working memory content. Further analysis revealed differential midbrain-dorsolateral prefrontal interactions during selective updating between low-performing and high-performing individuals. These findings highlight the role of this meso-cortico-striatal circuitry during the selective updating of working memory in humans, which complements previous research in behavioral neuroscience and computational modeling. Published by Elsevier Inc.

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Multi-bit dark state memory: Double quantum dot as an electronic quantum memory

NASA Astrophysics Data System (ADS)

Aharon, Eran; Pozner, Roni; Lifshitz, Efrat; Peskin, Uri

2016-12-01

Quantum dot clusters enable the creation of dark states which preserve electrons or holes in a coherent superposition of dot states for a long time. Various quantum logic devices can be envisioned to arise from the possibility of storing such trapped particles for future release on demand. In this work, we consider a double quantum dot memory device, which enables the preservation of a coherent state to be released as multiple classical bits. Our unique device architecture uses an external gating for storing (writing) the coherent state and for retrieving (reading) the classical bits, in addition to exploiting an internal gating effect for the preservation of the coherent state.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Ionic Liquid Gating Control of Spin Reorientation Transition and Switching of Perpendicular Magnetic Anisotropy.

PubMed

Zhao, Shishun; Wang, Lei; Zhou, Ziyao; Li, Chunlei; Dong, Guohua; Zhang, Le; Peng, Bin; Min, Tai; Hu, Zhongqiang; Ma, Jing; Ren, Wei; Ye, Zuo-Guang; Chen, Wei; Yu, Pu; Nan, Ce-Wen; Liu, Ming

2018-05-29

Electric field (E-field) modulation of perpendicular magnetic anisotropy (PMA) switching, in an energy-efficient manner, is of great potential to realize magnetoelectric (ME) memories and other ME devices. Voltage control of the spin-reorientation transition (SRT) that allows the magnetic moment rotating between the out-of-plane and the in-plane direction is thereby crucial. In this work, a remarkable magnetic anisotropy field change up to 1572 Oe is achieved under a small operation voltage of 4 V through ionic liquid (IL) gating control of SRT in Au/[DEME] + [TFSI] - /Pt/(Co/Pt) 2 /Ta capacitor heterostructures at room temperature, corresponding to a large ME coefficient of 378 Oe V -1 . As revealed by both ferromagnetic resonance measurements and magnetic domain evolution observation, the magnetization can be switched stably and reversibly between the out-of-plane and in-plane directions via IL gating. The key mechanism, revealed by the first-principles calculation, is that the IL gating process influences the interfacial spin-orbital coupling as well as net Rashba magnetic field between the Co and Pt layers, resulting in the modulation of the SRT and in-plane/out-of-plane magnetization switching. This work demonstrates a unique IL-gated PMA with large ME tunability and paves a way toward IL gating spintronic/electronic devices such as voltage tunable PMA memories. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

The Association of Schizophrenia Risk -Amino Acid Oxidase Polymorphisms With Sensorimotor Gating, Working Memory and Personality in Healthy Males

PubMed Central

Roussos, Panos; Giakoumaki, Stella G; Adamaki, Eva; Anastasios, Georgakopoulos; Nikos, Robakis K; Bitsios, Panos

2011-01-01

There is evidence supporting a role for the -amino acid oxidase (DAO) locus in schizophrenia. This study aimed to determine the relationship of five single-nucleotide polymorphisms (SNPs) within the DAO gene identified as promising schizophrenia risk genes (rs4623951, rs2111902, rs3918346, rs3741775, and rs3825251) to acoustic startle, prepulse inhibition (PPI), working memory, and personality dimensions. A highly homogeneous study entry cohort (n=530) of healthy, young male army conscripts (n=703) originating from the Greek LOGOS project (Learning On Genetics Of Schizophrenia Spectrum) underwent PPI of the acoustic startle reflex, working memory, and personality assessment. The QTPHASE from the UNPHASED package was used for the association analysis of each SNP or haplotype data, with p-values corrected for multiple testing by running 10 000 permutations of the data. The rs4623951_T-rs3741775_G and rs4623951_T-rs2111902_T diplotypes were associated with reduced PPI and worse performance in working memory tasks and a personality pattern characterized by attenuated anxiety. Median stratification analysis of the risk diplotype group (ie, those individuals homozygous for the T and G alleles (TG+)) showed reduced PPI and working memory performance only in TG+ individuals with high trait anxiety. The rs4623951_T allele, which is the DAO polymorphism most strongly associated with schizophrenia, might tag a haplotype that affects PPI, cognition, and personality traits in general population. Our findings suggest an influence of the gene in the neural substrate mediating sensorimotor gating and working memory, especially when combined with high anxiety and further validate DAO as a candidate gene for schizophrenia and spectrum disorders. PMID:21471957

Instantons in Self-Organizing Logic Gates

NASA Astrophysics Data System (ADS)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Working memory capacity affects the interference control of distractors at auditory gating.

PubMed

Tsuchida, Yukio; Katayama, Jun'ichi; Murohashi, Harumitsu

2012-05-10

It is important to understand the role of individual differences in working memory capacity (WMC). We investigated the relation between differences in WMC and N1 in event-related brain potentials as a measure of early selective attention for an auditory distractor in three-stimulus oddball tasks that required minimum memory. A high-WMC group (n=13) showed a smaller N1 in response to a distractor and target than did a low-WMC group (n=13) in the novel condition with high distraction. However, in the simple condition with low distraction, there was no difference in N1 between the groups. For all participants (n=52), the correlation between the scores for WMC and N1 peak amplitude was strong for distractors in the novel condition, whereas there was no relation in the simple condition. These results suggest that WMC can predict the interference control for a salient distractor at auditory gating even during a selective attention task. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Locomotor activity, emotionality, sensori-motor gating, learning and memory in the APPswe/PS1dE9 mouse model of Alzheimer's disease.

PubMed

O'Leary, Timothy P; Hussin, Ahmed T; Gunn, Rhian K; Brown, Richard E

2018-06-02

The APPswe/PS1dE9 mouse (line 85) is a double transgenic model of Alzheimer's disease (AD) with familial amyloid precursor protein and presenilin-1 mutations. These mice develop age-related behavioral changes reflective of the neuropsychiatric symptoms (altered anxiety-like behaviour, hyperactivity) and cognitive dysfunction (impaired learning and memory) observed in AD. The APPswe/PS1dE9 mouse has been used to examine the efficacy of therapeutic interventions on behaviour, despite previous difficulties in replicating behavioural phenotypes. Therefore, the purpose of this study was to establish the reliability of these phenotypes by further characterizing the behaviour of male APPswe/PS1dE9 and wild-type mice between 7 and 14 months of age. Mice were tested on the open-field over 5-days to examine emotionality, locomotor activity and inter-session habituation. Mice were also tested on the repeated-reversal water maze task and spontaneous alternation on the Y-maze to assess working memory. Sensori-motor gating was examined with acoustic startle and pre-pulse inhibition. Lastly contextual and cued (trace) memory was assessed with fear conditioning. The results show that among non-cognitive behaviours, APPswe/PS1dE9 mice have normal locomotor activity, anxiety-like behavior, habituation and sensori-motor gating. However, APPswe/PS1dE9 mice show impaired working memory on the repeated-reversal water-maze and impaired memory in contextual but not trace-cued fear conditioning. These results indicate that the APPswe/PS1dE9 (line 85) mice have deficits in some types of hippocampal-dependent learning and memory and, at the ages tested, APPswe/PS1dE9 mice model cognitive dysfunction but not neuropsychiatric symptoms. Copyright © 2018. Published by Elsevier Inc.

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Working memory capacity and visual-verbal cognitive load modulate auditory-sensory gating in the brainstem: toward a unified view of attention.

PubMed

Sörqvist, Patrik; Stenfelt, Stefan; Rönnberg, Jerker

2012-11-01

Two fundamental research questions have driven attention research in the past: One concerns whether selection of relevant information among competing, irrelevant, information takes place at an early or at a late processing stage; the other concerns whether the capacity of attention is limited by a central, domain-general pool of resources or by independent, modality-specific pools. In this article, we contribute to these debates by showing that the auditory-evoked brainstem response (an early stage of auditory processing) to task-irrelevant sound decreases as a function of central working memory load (manipulated with a visual-verbal version of the n-back task). Furthermore, individual differences in central/domain-general working memory capacity modulated the magnitude of the auditory-evoked brainstem response, but only in the high working memory load condition. The results support a unified view of attention whereby the capacity of a late/central mechanism (working memory) modulates early precortical sensory processing.

Gating of memory encoding of time-delayed cross-frequency MEG networks revealed by graph filtration based on persistent homology

PubMed Central

Hahm, Jarang; Lee, Hyekyoung; Park, Hyojin; Kang, Eunjoo; Kim, Yu Kyeong; Chung, Chun Kee; Kang, Hyejin; Lee, Dong Soo

2017-01-01

To explain gating of memory encoding, magnetoencephalography (MEG) was analyzed over multi-regional network of negative correlations between alpha band power during cue (cue-alpha) and gamma band power during item presentation (item-gamma) in Remember (R) and No-remember (NR) condition. Persistent homology with graph filtration on alpha-gamma correlation disclosed topological invariants to explain memory gating. Instruction compliance (R-hits minus NR-hits) was significantly related to negative coupling between the left superior occipital (cue-alpha) and the left dorsolateral superior frontal gyri (item-gamma) on permutation test, where the coupling was stronger in R than NR. In good memory performers (R-hits minus false alarm), the coupling was stronger in R than NR between the right posterior cingulate (cue-alpha) and the left fusiform gyri (item-gamma). Gating of memory encoding was dictated by inter-regional negative alpha-gamma coupling. Our graph filtration over MEG network revealed these inter-regional time-delayed cross-frequency connectivity serve gating of memory encoding. PMID:28169281

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

DefenseLink.mil - Special Report - Travels With Gates

Science.gov Websites

Force in Afghanistan to the NATO and partner-nation defense ministers here today.Story New Memorial Attends NATO Defense Ministers' Conference Gates Tours Netherlands American Cemetery and Memorial MEMORIAL DEDICATION - NATO officials dedicate a memorial to those who have lost their lives in alliance operations

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

The dopamine D2 receptor antagonist sulpiride modulates striatal BOLD signal during the manipulation of information in working memory.

PubMed

Dodds, Chris M; Clark, Luke; Dove, Anja; Regenthal, Ralf; Baumann, Frank; Bullmore, Ed; Robbins, Trevor W; Müller, Ulrich

2009-11-01

Dopamine (DA) plays an important role in working memory. However, the precise functions supported by different DA receptor subtypes in different neural regions remain unclear. The present study used pharmacological, event-related fMRI to test the hypothesis that striatal dopamine is important for the manipulation of information in working memory. Twenty healthy human subjects were scanned twice, once after placebo and once after sulpiride 400 mg, a selective DA D2 receptor antagonist, while performing a verbal working memory task requiring different levels of manipulation. Whilst there was no overall effect of sulpiride on task-dependent activation, individual variation in sulpiride plasma levels predicted the effect of working memory manipulation on activation in the putamen, suggesting a dose-dependent effect of DA antagonism on a striatally based manipulation process. These effects occurred in the context of a drug-induced improvement in performance on trials requiring the manipulation of information in working memory but not on simple retrieval trials. No significant drug effects were observed in the prefrontal cortex. These results support models of dopamine function that posit a 'gating' function for dopamine D2 receptors in the striatum, which enables the flexible updating and manipulation of information in working memory.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ADMINISTRATION BUILDING IN BACKGROUND. VIEW TO NORTHWEST. - Mountain Home National Cemetery, Mountain Home, Washington County, TN

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Skyrmion domain wall collision and domain wall-gated skyrmion logic

NASA Astrophysics Data System (ADS)

Xing, Xiangjun; Pong, Philip W. T.; Zhou, Yan

2016-08-01

Skyrmions and domain walls are significant spin textures of great technological relevance to magnetic memory and logic applications, where they can be used as carriers of information. The unique topology of skyrmions makes them display emergent dynamical properties as compared with domain walls. Some studies have demonstrated that the two topologically inequivalent magnetic objects could be interconverted by using cleverly designed geometric structures. Here, we numerically address the skyrmion domain wall collision in a magnetic racetrack by introducing relative motion between the two objects based on a specially designed junction. An electric current serves as the driving force that moves a skyrmion toward a trapped domain wall pair. We see different types of collision dynamics depending on the driving parameters. Most importantly, the modulation of skyrmion transport using domain walls is realized in this system, allowing a set of domain wall-gated logical NOT, NAND, and NOR gates to be constructed. This work provides a skyrmion-based spin-logic architecture that is fully compatible with racetrack memories.

Auditory post-processing in a passive listening task is deficient in Alzheimer's disease.

PubMed

Bender, Stephan; Bluschke, Annet; Dippel, Gabriel; Rupp, André; Weisbrod, Matthias; Thomas, Christine

2014-01-01

To investigate whether automatic auditory post-processing is deficient in patients with Alzheimer's disease and is related to sensory gating. Event-related potentials were recorded during a passive listening task to examine the automatic transient storage of auditory information (short click pairs). Patients with Alzheimer's disease were compared to a healthy age-matched control group. A young healthy control group was included to assess effects of physiological aging. A bilateral frontal negativity in combination with deep temporal positivity occurring 500 ms after stimulus offset was reduced in patients with Alzheimer's disease, but was unaffected by physiological aging. Its amplitude correlated with short-term memory capacity, but was independent of sensory gating in healthy elderly controls. Source analysis revealed a dipole pair in the anterior temporal lobes. Results suggest that auditory post-processing is deficient in Alzheimer's disease, but is not typically related to sensory gating. The deficit could neither be explained by physiological aging nor by problems in earlier stages of auditory perception. Correlations with short-term memory capacity and executive control tasks suggested an association with memory encoding and/or overall cognitive control deficits. An auditory late negative wave could represent a marker of auditory working memory encoding deficits in Alzheimer's disease. Copyright © 2013 International Federation of Clinical Neurophysiology. Published by Elsevier Ireland Ltd. All rights reserved.

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Knockdown of phospholipase C-β1 in the medial prefrontal cortex of male mice impairs working memory among multiple schizophrenia endophenotypes

PubMed Central

Kim, Seong-Wook; Seo, Misun; Kim, Duk-Soo; Kang, Moonkyung; Kim, Yeon-Soo; Koh, Hae-Young; Shin, Hee-Sup

2015-01-01

Background Decreased expression of phospholipase C-β1 (PLC-β1) has been observed in the brains of patients with schizophrenia, but, to our knowledge, no studies have shown a possible association between this altered PLC-β1 expression and the pathogenesis of schizophrenia. Although PLC-β1-null (PLC-β1−/−) mice exhibit multiple endophenotypes of schizophrenia, it remains unclear how regional decreases in PLC-β1 expression in the brain contribute to specific behavioural defects. Methods We selectively knocked down PLC-β1 in the medial prefrontal cortex (mPFC) using a small hairpin RNA strategy in mice. Results Silencing PLC-β1 in the mPFC resulted in working memory deficits, as assayed using the delayed non-match-to-sample T-maze task. Notably, however, other schizophrenia- related behaviours observed in PLC-β1−/− mice, including phenotypes related to locomotor activity, sociability and sensorimotor gating, were normal in PLC-β1 knockdown mice. Limitations Phenotypes of PLC-β1 knockdown mice, such as locomotion, anxiety and sensorimotor gating, have already been published in our previous studies. Further, the neural mechanisms underlying the working memory deficit in mice may be different from those in human schizophrenia. Conclusion These results indicate that PLC-β1 signalling in the mPFC is required for working memory. Importantly, these results support the notion that the decrease in PLC-β1 expression in the brains of patients with schizophrenia is a pathogenically relevant molecular marker of the disorder. PMID:25268789

Role of prefrontal cortex and the midbrain dopamine system in working memory updating

PubMed Central

D’Ardenne, Kimberlee; Eshel, Neir; Luka, Joseph; Lenartowicz, Agatha; Nystrom, Leigh E.; Cohen, Jonathan D.

2012-01-01

Humans are adept at switching between goal-directed behaviors quickly and effectively. The prefrontal cortex (PFC) is thought to play a critical role by encoding, updating, and maintaining internal representations of task context in working memory. It has also been hypothesized that the encoding of context representations in PFC is regulated by phasic dopamine gating signals. Here we use multimodal methods to test these hypotheses. First we used functional MRI (fMRI) to identify regions of PFC associated with the representation of context in a working memory task. Next we used single-pulse transcranial magnetic stimulation (TMS), guided spatially by our fMRI findings and temporally by previous event-related EEG recordings, to disrupt context encoding while participants performed the same working memory task. We found that TMS pulses to the right dorsolateral PFC (DLPFC) immediately after context presentation, and well in advance of the response, adversely impacted context-dependent relative to context-independent responses. This finding causally implicates right DLPFC function in context encoding. Finally, using the same paradigm, we conducted high-resolution fMRI measurements in brainstem dopaminergic nuclei (ventral tegmental area and substantia nigra) and found phasic responses after presentation of context stimuli relative to other stimuli, consistent with the timing of a gating signal that regulates the encoding of representations in PFC. Furthermore, these responses were positively correlated with behavior, as well as with responses in the same region of right DLPFC targeted in the TMS experiment, lending support to the hypothesis that dopamine phasic signals regulate encoding, and thereby the updating, of context representations in PFC. PMID:23086162

Minimal-memory realization of pearl-necklace encoders of general quantum convolutional codes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Houshmand, Monireh; Hosseini-Khayat, Saied

2011-02-15

Quantum convolutional codes, like their classical counterparts, promise to offer higher error correction performance than block codes of equivalent encoding complexity, and are expected to find important applications in reliable quantum communication where a continuous stream of qubits is transmitted. Grassl and Roetteler devised an algorithm to encode a quantum convolutional code with a ''pearl-necklace'' encoder. Despite their algorithm's theoretical significance as a neat way of representing quantum convolutional codes, it is not well suited to practical realization. In fact, there is no straightforward way to implement any given pearl-necklace structure. This paper closes the gap between theoretical representation andmore » practical implementation. In our previous work, we presented an efficient algorithm to find a minimal-memory realization of a pearl-necklace encoder for Calderbank-Shor-Steane (CSS) convolutional codes. This work is an extension of our previous work and presents an algorithm for turning a pearl-necklace encoder for a general (non-CSS) quantum convolutional code into a realizable quantum convolutional encoder. We show that a minimal-memory realization depends on the commutativity relations between the gate strings in the pearl-necklace encoder. We find a realization by means of a weighted graph which details the noncommutative paths through the pearl necklace. The weight of the longest path in this graph is equal to the minimal amount of memory needed to implement the encoder. The algorithm has a polynomial-time complexity in the number of gate strings in the pearl-necklace encoder.« less

Efficient Parallel Algorithms on Restartable Fail-Stop Processors

DTIC Science & Technology

1991-01-01

resource (memory), and ( 3 ) that processors, memory and their interconnection must be The model of parallel computation known as the Par- perfectly...setting), arid ure an(I restart errors. We describe these arguments if] [AAtPS 871 (in a deterministic setting). Fault-tolerance Section 3 . of...grannmarity at the processor level --- for recent work on where Al is the nmber of failures during this step’s gate granilarities see [All 90, Pip 85

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

Improper activation of D1 and D2 receptors leads to excess noise in prefrontal cortex

PubMed Central

Avery, Michael C.; Krichmar, Jeffrey L.

2015-01-01

The dopaminergic system has been shown to control the amount of noise in the prefrontal cortex (PFC) and likely plays an important role in working memory and the pathophysiology of schizophrenia. We developed a model that takes into account the known receptor distributions of D1 and D2 receptors, the changes these receptors have on neuron response properties, as well as identified circuitry involved in working memory. Our model suggests that D1 receptor under-stimulation in supragranular layers gates internal noise into the PFC leading to cognitive symptoms as has been proposed in attention disorders, while D2 over-stimulation gates noise into the PFC by over-activation of cortico-striatal projecting neurons in infragranular layers. We apply this model in the context of a memory-guided saccade paradigm and show deficits similar to those observed in schizophrenic patients. We also show set-shifting impairments similar to those observed in rodents with D1 and D2 receptor manipulations. We discuss how the introduction of noise through changes in D1 and D2 receptor activation may account for many of the symptoms of schizophrenia depending on where this dysfunction occurs in the PFC. PMID:25814948

Improved Reading Gate For Vertical-Bloch-Line Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1994-01-01

Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th}more » was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.« less

Design, processing, and testing of lsi arrays for space station

NASA Technical Reports Server (NTRS)

Lile, W. R.; Hollingsworth, R. J.

1972-01-01

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW TO EAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

Striatal contributions to declarative memory retrieval

PubMed Central

Scimeca, Jason M.; Badre, David

2012-01-01

Declarative memory is known to depend on the medial temporal lobe memory system. Recently, there has been renewed focus on the relationship between the basal ganglia and declarative memory, including the involvement of striatum. However, the contribution of striatum to declarative memory retrieval remains unknown. Here, we review neuroimaging and neuropsychological evidence for the involvement of the striatum in declarative memory retrieval. From this review, we propose that, along with the prefrontal cortex (PFC), the striatum primarily supports cognitive control of memory retrieval. We conclude by proposing three hypotheses for the specific role of striatum in retrieval: (1) Striatum modulates the re-encoding of retrieved items in accord with their expected utility (adaptive encoding), (2) striatum selectively admits information into working memory that is expected to increase the likelihood of successful retrieval (adaptive gating), and (3) striatum enacts adjustments in cognitive control based on the outcome of retrieval (reinforcement learning). PMID:22884322

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Bilinearity, Rules, and Prefrontal Cortex

PubMed Central

Dayan, Peter

2007-01-01

Humans can be instructed verbally to perform computationally complex cognitive tasks; their performance then improves relatively slowly over the course of practice. Many skills underlie these abilities; in this paper, we focus on the particular question of a uniform architecture for the instantiation of habitual performance and the storage, recall, and execution of simple rules. Our account builds on models of gated working memory, and involves a bilinear architecture for representing conditional input-output maps and for matching rules to the state of the input and working memory. We demonstrate the performance of our model on two paradigmatic tasks used to investigate prefrontal and basal ganglia function. PMID:18946523

A boost and bounce theory of temporal attention.

PubMed

Olivers, Christian N L; Meeter, Martijn

2008-10-01

What is the time course of visual attention? Attentional blink studies have found that the 2nd of 2 targets is often missed when presented within about 500 ms from the 1st target, resulting in theories about relatively long-lasting capacity limitations or bottlenecks. Earlier studies, however, reported quite the opposite finding: Attention is transiently enhanced, rather than reduced, for several hundreds of milliseconds after a relevant event. The authors present a general theory, as well as a working computational model, that integrate these findings. There is no central role for capacity limitations or bottlenecks. Central is a rapidly responding gating system (or attentional filter) that seeks to enhance relevant and suppress irrelevant information. When items sufficiently match the target description, they elicit transient excitatory feedback activity (a "boost" function), meant to provide access to working memory. However, in the attentional blink task, the distractor after the target is accidentally boosted, resulting in subsequent strong inhibitory feedback response (a "bounce"), which, in effect, closes the gate to working memory. The theory explains many findings that are problematic for limited-capacity accounts, including a new experiment showing that the attentional blink can be postponed.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene

NASA Astrophysics Data System (ADS)

Heidler, Jonas; Yang, Sheng; Feng, Xinliang; Müllen, Klaus; Asadi, Kamal

2018-06-01

Memories based on graphene that could be mass produced using low-cost methods have not yet received much attention. Here we demonstrate graphene ferroelectric (dual-gate) field effect transistors. The graphene has been obtained using electrochemical exfoliation of graphite. Field-effect transistors are realized using a monolayer of graphene flakes deposited by the Langmuir-Blodgett protocol. Ferroelectric field effect transistor memories are realized using a random ferroelectric copolymer poly(vinylidenefluoride-co-trifluoroethylene) in a top gated geometry. The memory transistors reveal ambipolar behaviour with both electron and hole accumulation channels. We show that the non-ferroelectric bottom gate can be advantageously used to tune the on/off ratio.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Configurable unitary transformations and linear logic gates using quantum memories.

PubMed

Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K

2014-08-08

We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin

1989-01-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Astrophysics Data System (ADS)

Chao, Tien-Hsin

1989-06-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Project Golden Gate: towards real-time Java in space missions

NASA Technical Reports Server (NTRS)

Dvorak, Daniel; Bollella, Greg; Canham, Tim; Carson, Vanessa; Champlin, Virgil; Giovannoni, Brian; Indictor, Mark; Meyer, Kenny; Murray, Alex; Reinholtz, Kirk

2004-01-01

This paper describes the problem domain and our experimentation with the first commercial implementation of the Real Time Specification for Java. The two main issues explored in this report are: (1) the effect of RTSJ's non-heap memory on the programming model, and (2) performance benchmarking of RTSJ/Linux relative to C++/VxWorks.

Activity-Dependent Inhibitory Gating in Molecular Signaling Cascades Induces a Novel Form of Intermediate-Term Synaptic Facilitation in "Aplysia Californica"

ERIC Educational Resources Information Center

Fischbach, Soren; Kopec, Ashley M.; Carew, Thomas J.

2014-01-01

Mechanistically distinct forms of long-lasting plasticity and memory can be induced by a variety of different training patterns. Although several studies have identified distinct molecular pathways that are engaged during these different training patterns, relatively little work has explored potential interactions between pathways when they are…

Dynamic memory of a single voltage-gated potassium ion channel: A stochastic nonequilibrium thermodynamic analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Banerjee, Kinshuk, E-mail: kbpchem@gmail.com

2015-05-14

In this work, we have studied the stochastic response of a single voltage-gated potassium ion channel to a periodic external voltage that keeps the system out-of-equilibrium. The system exhibits memory, resulting from time-dependent driving, that is reflected in terms of dynamic hysteresis in the current-voltage characteristics. The hysteresis loop area has a maximum at some intermediate voltage frequency and disappears in the limits of low and high frequencies. However, the (average) dissipation at long-time limit increases and finally goes to saturation with rising frequency. This raises the question: how diminishing hysteresis can be associated with growing dissipation? To answer this,more » we have studied the nonequilibrium thermodynamics of the system and analyzed different thermodynamic functions which also exhibit hysteresis. Interestingly, by applying a temporal symmetry analysis in the high-frequency limit, we have analytically shown that hysteresis in some of the periodic responses of the system does not vanish. On the contrary, the rates of free energy and internal energy change of the system as well as the rate of dissipative work done on the system show growing hysteresis with frequency. Hence, although the current-voltage hysteresis disappears in the high-frequency limit, the memory of the ion channel is manifested through its specific nonequilibrium thermodynamic responses.« less

Using a Large-scale Neural Model of Cortical Object Processing to Investigate the Neural Substrate for Managing Multiple Items in Short-term Memory.

PubMed

Liu, Qin; Ulloa, Antonio; Horwitz, Barry

2017-11-01

Many cognitive and computational models have been proposed to help understand working memory. In this article, we present a simulation study of cortical processing of visual objects during several working memory tasks using an extended version of a previously constructed large-scale neural model [Tagamets, M. A., & Horwitz, B. Integrating electrophysiological and anatomical experimental data to create a large-scale model that simulates a delayed match-to-sample human brain imaging study. Cerebral Cortex, 8, 310-320, 1998]. The original model consisted of arrays of Wilson-Cowan type of neuronal populations representing primary and secondary visual cortices, inferotemporal (IT) cortex, and pFC. We added a module representing entorhinal cortex, which functions as a gating module. We successfully implemented multiple working memory tasks using the same model and produced neuronal patterns in visual cortex, IT cortex, and pFC that match experimental findings. These working memory tasks can include distractor stimuli or can require that multiple items be retained in mind during a delay period (Sternberg's task). Besides electrophysiology data and behavioral data, we also generated fMRI BOLD time series from our simulation. Our results support the involvement of IT cortex in working memory maintenance and suggest the cortical architecture underlying the neural mechanisms mediating particular working memory tasks. Furthermore, we noticed that, during simulations of memorizing a list of objects, the first and last items in the sequence were recalled best, which may implicate the neural mechanism behind this important psychological effect (i.e., the primacy and recency effect).

Memory operation mechanism of fullerene-containing polymer memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakajima, Anri, E-mail: anakajima@hiroshima-u.ac.jp; Fujii, Daiki

2015-03-09

The memory operation mechanism in fullerene-containing nanocomposite gate insulators was investigated while varying the kind of fullerene in a polymer gate insulator. It was cleared what kind of traps and which positions in the nanocomposite the injected electrons or holes are stored in. The reason for the difference in the easiness of programming was clarified taking the role of the charging energy of an injected electron into account. The dependence of the carrier dynamics on the kind of fullerene molecule was investigated. A nonuniform distribution of injected carriers occurred after application of a large magnitude programming voltage due to themore » width distribution of the polystyrene barrier between adjacent fullerene molecules. Through the investigations, we demonstrated a nanocomposite gate with fullerene molecules having excellent retention characteristics and a programming capability. This will lead to the realization of practical organic memories with fullerene-containing polymer nanocomposites.« less

Photoresponse and photo-induced memory effect in the organic field-effect transistor based on AlOX nanoparticles at the interface of semiconductor/dielectric

NASA Astrophysics Data System (ADS)

Cheng, Yunfei; Wang, Wu

2017-10-01

In this work, the photoresponse and photo-induced memory effect were demonstrated in an organic field-effect transistor (OFET) with semiconductor pentacene and SiO2 as the active and gate dielectric layers, respectively. By inserting AlOX nanoparticles (NPs) at the interface of pentacene/SiO2, obvious enhancing photoresponse was obtained in the OFET with the maximum responsivity and photosensitivity of about 15 A/W and 100, respectively. Moreover, the stable photoinduced memory effect was achieved in the OFET, attributing to the photogenerated electrons captured by the interface traps of the AlOX NPs/SiO2.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Modulation of learning and memory by the genetic disruption of circadian oscillator populations.

PubMed

Snider, Kaitlin H; Obrietan, Karl

2018-06-23

While a rich literature has documented that the efficiency of learning and memory varies across circadian time, a close survey of that literature reveals extensive heterogeneity in the time of day (TOD) when peak cognitive performance occurs. Moreover, most previous experiments in rodents have not focused on the question of discriminating which memory processes (e.g., working memory, memory acquisition, or retrieval) are modulated by the TOD. Here, we use assays of contextual fear conditioning and spontaneous alternation in WT (C57Bl/6 J) mice to survey circadian modulation of hippocampal-dependent memory at multiple timescales - including working memory (seconds to a few minutes), intermediate-term memory (a delay of thirty minutes), and acquisition and retrieval of long-term memory (a delay of two days). Further, in order to test the relative contributions of circadian timing mechanisms to the modulation of memory, a parallel set of studies were performed in mice lacking clock timing mechanisms. These transgenic mice lacked the essential circadian gene Bmal1, either globally (Bmal1 null) or locally (floxed Bmal1 mice which lack Bmal1 in excitatory forebrain neurons, e.g. cortical and hippocampal neurons). Here, we show that in WT mice, retrieval (but not working memory, intermediate-term memory, or acquisition of long-term memory) is modulated by TOD. However, transgenic mouse models lacking Bmal1 - both globally, and only in forebrain excitatory neurons - show deficits regardless of the memory process tested (and lack circadian modulation of retrieval). These results provide new clarity regarding the impact of TOD on hippocampal-dependent memory and support the key role of hippocampal and cortical circadian oscillations in circadian gating of cognition. Copyright © 2018. Published by Elsevier Inc.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Energy reduction through voltage scaling and lightweight checking

NASA Astrophysics Data System (ADS)

Kadric, Edin

As the semiconductor roadmap reaches smaller feature sizes and the end of Dennard Scaling, design goals change, and managing the power envelope often dominates delay minimization. Voltage scaling remains a powerful tool to reduce energy. We find that it results in about 60% geomean energy reduction on top of other common low-energy optimizations with 22nm CMOS technology. However, when voltage is reduced, it becomes easier for noise and particle strikes to upset a node, potentially causing Silent Data Corruption (SDC). The 60% energy reduction, therefore, comes with a significant drop in reliability. Duplication with checking and triple-modular redundancy are traditional approaches used to combat transient errors, but spending 2--3x the energy for redundant computation can diminish or reverse the benefits of voltage scaling. As an alternative, we explore the opportunity to use checking operations that are cheaper than the base computation they are guarding. We devise a classification system for applications and their lightweight checking characteristics. In particular, we identify and evaluate the effectiveness of lightweight checks in a broad set of common tasks in scientific computing and signal processing. We find that the lightweight checks cost only a fraction of the base computation (0-25%) and allow us to recover the reliability losses from voltage scaling. Overall, we show about 50% net energy reduction without compromising reliability compared to operation at the nominal voltage. We use FPGAs (Field-Programmable Gate Arrays) in our work, although the same ideas can be applied to different systems. On top of voltage scaling, we explore other common low-energy techniques for FPGAs: transmission gates, gate boosting, power gating, low-leakage (high-Vth) processes, and dual-V dd architectures. We do not scale voltage for memories, so lower voltages help us reduce logic and interconnect energy, but not memory energy. At lower voltages, memories become dominant, and we get diminishing returns from continuing to scale voltage. To ensure that memories do not become a bottleneck, we also design an energy-robust FPGA memory architecture, which attempts to minimize communication energy due to mismatches between application and architecture. We do this alongside application parallelism tuning. We show our techniques on a wide range of applications, including a large real-time system used for Wide-Area Motion Imaging (WAMI).

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

From Three-Photon Greenberger-Horne-Zeilinger States to Ballistic Universal Quantum Computation.

PubMed

Gimeno-Segovia, Mercedes; Shadbolt, Pete; Browne, Dan E; Rudolph, Terry

2015-07-10

Single photons, manipulated using integrated linear optics, constitute a promising platform for universal quantum computation. A series of increasingly efficient proposals have shown linear-optical quantum computing to be formally scalable. However, existing schemes typically require extensive adaptive switching, which is experimentally challenging and noisy, thousands of photon sources per renormalized qubit, and/or large quantum memories for repeat-until-success strategies. Our work overcomes all these problems. We present a scheme to construct a cluster state universal for quantum computation, which uses no adaptive switching, no large memories, and which is at least an order of magnitude more resource efficient than previous passive schemes. Unlike previous proposals, it is constructed entirely from loss-detecting gates and offers a robustness to photon loss. Even without the use of an active loss-tolerant encoding, our scheme naturally tolerates a total loss rate ∼1.6% in the photons detected in the gates. This scheme uses only 3 Greenberger-Horne-Zeilinger states as a resource, together with a passive linear-optical network. We fully describe and model the iterative process of cluster generation, including photon loss and gate failure. This demonstrates that building a linear-optical quantum computer needs to be less challenging than previously thought.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Effects of Prenatal Exposure to Nicotine on Working Memory, Activity, Sensory Gating, and Dopamine Receptor Binding in Adolescent and Adult Male and Female Rats

DTIC Science & Technology

1999-01-08

28 Physical Chemistry ........... • . ... •. . . . . • .•...... . ... 28 Synthesis and Degradation...12 Figure 13 Figure 14 List of Figures Structure of dopamine and related compounds .. •. •.•. .... 28 Metabolism of dopamine...31 Structure of nicotine ............................ •.... . 33 Example of video software output. ............... • . • ..... 44 Placement of

MURI Center for Photonic Quantum Information Systems

DTIC Science & Technology

2009-10-16

conversion; solid- state quantum gates based on quantum dots in semiconductors and on NV centers in diamond; quantum memories using optical storage...of our high-speed quantum cryptography systems, and also by continuing to work on quantum information encoding into transverse spatial modes. 14...make use of cavity QED effects for quantum information processing, the quantum dot needs to be addressed coherently . We have probed the QD-cavity

Generalisation benefits of output gating in a model of prefrontal cortex

NASA Astrophysics Data System (ADS)

Kriete, Trent; Noelle, David C.

2011-06-01

The prefrontal cortex (PFC) plays a central role in flexible cognitive control, including the suppression of habitual responding in favour of situation-appropriate behaviours that can be quite novel. PFC provides a kind of working memory, maintaining the rules, goals, and/or actions that are to control behaviour in the current context. For flexible control, these PFC representations must be sufficiently componential to support systematic generalisation to novel situations. The anatomical structure of PFC can be seen as implementing a componential 'slot-filler' structure, with different components encoded over isolated pools of neurons. Previous PFC models have highlighted the importance of a dynamic gating mechanism to selectively update individual 'slot' contents. In this article, we present simulation results that suggest that systematic generalisation also requires an 'output gating' mechanism that limits the influence of PFC on more posterior brain areas to reflect a small number of representational components at any one time.

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

NASA Astrophysics Data System (ADS)

Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

2014-02-01

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

Gated Auditory Speech Perception in Elderly Hearing Aid Users and Elderly Normal-Hearing Individuals: Effects of Hearing Impairment and Cognitive Capacity

PubMed Central

Lidestam, Björn; Hällgren, Mathias; Rönnberg, Jerker

2014-01-01

This study compared elderly hearing aid (EHA) users and elderly normal-hearing (ENH) individuals on identification of auditory speech stimuli (consonants, words, and final word in sentences) that were different when considering their linguistic properties. We measured the accuracy with which the target speech stimuli were identified, as well as the isolation points (IPs: the shortest duration, from onset, required to correctly identify the speech target). The relationships between working memory capacity, the IPs, and speech accuracy were also measured. Twenty-four EHA users (with mild to moderate hearing impairment) and 24 ENH individuals participated in the present study. Despite the use of their regular hearing aids, the EHA users had delayed IPs and were less accurate in identifying consonants and words compared with the ENH individuals. The EHA users also had delayed IPs for final word identification in sentences with lower predictability; however, no significant between-group difference in accuracy was observed. Finally, there were no significant between-group differences in terms of IPs or accuracy for final word identification in highly predictable sentences. Our results also showed that, among EHA users, greater working memory capacity was associated with earlier IPs and improved accuracy in consonant and word identification. Together, our findings demonstrate that the gated speech perception ability of EHA users was not at the level of ENH individuals, in terms of IPs and accuracy. In addition, gated speech perception was more cognitively demanding for EHA users than for ENH individuals in the absence of semantic context. PMID:25085610

The misnomer of attention-deficit hyperactivity disorder.

PubMed

Wasserman, Theodore; Wasserman, Lori Drucker

2015-01-01

We propose that attention-deficit disorder represents an inefficiency of an integrated system designed to allocate working memory to designated tasks rather than the absence or dysfunction of a particular form of attention. A significant portion of this inefficiency in the allocation of working memory represents poor engagement of the reward circuit with distinct circuits of learning and performance that control instrumental conditioning (learning). Efficient attention requires the interaction of these circuits. For a significant percentage of individuals who present with attention-deficit disorder, their problems represent the engagement, or lack thereof, of the motivational and reward circuit as opposed to problems, or disorders of attention traditionally defined as problems with orienting, focusing, and sustaining. We demonstrate that there is an integrated system of working-memory allocation that responds by recruiting relevant aspects of both cortex and subcortex to the demands of the task being encountered. In this model, attention is viewed as a gating function determined by novelty, flight-or-fight response, and reward history/valence affecting motivation. We view the traditional models of attention, rather than describe specific types of attention per se, as representing the description of the behavioral output of this integrated orienting and engagement system designed to allocate working memory to task-specific stimuli.

Vertical bloch line memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-chuan (Inventor)

1995-01-01

A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Reconfigurable Fault Tolerance for FPGAs

NASA Technical Reports Server (NTRS)

Shuler, Robert, Jr.

2010-01-01

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Auto and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

On the simple random-walk models of ion-channel gate dynamics reflecting long-term memory.

PubMed

Wawrzkiewicz, Agata; Pawelek, Krzysztof; Borys, Przemyslaw; Dworakowska, Beata; Grzywna, Zbigniew J

2012-06-01

Several approaches to ion-channel gating modelling have been proposed. Although many models describe the dwell-time distributions correctly, they are incapable of predicting and explaining the long-term correlations between the lengths of adjacent openings and closings of a channel. In this paper we propose two simple random-walk models of the gating dynamics of voltage and Ca(2+)-activated potassium channels which qualitatively reproduce the dwell-time distributions, and describe the experimentally observed long-term memory quite well. Biological interpretation of both models is presented. In particular, the origin of the correlations is associated with fluctuations of channel mass density. The long-term memory effect, as measured by Hurst R/S analysis of experimental single-channel patch-clamp recordings, is close to the behaviour predicted by our models. The flexibility of the models enables their use as templates for other types of ion channel.

Implicity Defined Neural Networks for Sequence Labeling

DTIC Science & Technology

2017-02-13

popularity of the Long Short - Term Memory (LSTM) (Hochreiter and Schmidhuber, 1997) and variants such as the Gated Recurrent Unit (GRU) (Cho et al., 2014...bidirectional lstm and other neural network architectures. Neural Net- works 18(5):602–610. Sepp Hochreiter and Jürgen Schmidhuber. 1997. Long short - term ...hid- den states of the network to coupled together, allowing potential improvement on problems with complex, long -distance dependencies. Initial

Role of working memory and lexical knowledge in perceptual restoration of interrupted speech.

PubMed

Nagaraj, Naveen K; Magimairaj, Beula M

2017-12-01

The role of working memory (WM) capacity and lexical knowledge in perceptual restoration (PR) of missing speech was investigated using the interrupted speech perception paradigm. Speech identification ability, which indexed PR, was measured using low-context sentences periodically interrupted at 1.5 Hz. PR was measured for silent gated, low-frequency speech noise filled, and low-frequency fine-structure and envelope filled interrupted conditions. WM capacity was measured using verbal and visuospatial span tasks. Lexical knowledge was assessed using both receptive vocabulary and meaning from context tests. Results showed that PR was better for speech noise filled condition than other conditions tested. Both receptive vocabulary and verbal WM capacity explained unique variance in PR for the speech noise filled condition, but were unrelated to performance in the silent gated condition. It was only receptive vocabulary that uniquely predicted PR for fine-structure and envelope filled conditions. These findings suggest that the contribution of lexical knowledge and verbal WM during PR depends crucially on the information content that replaced the silent intervals. When perceptual continuity was partially restored by filler speech noise, both lexical knowledge and verbal WM capacity facilitated PR. Importantly, for fine-structure and envelope filled interrupted conditions, lexical knowledge was crucial for PR.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

PubMed

Park, Jae Hyo; Son, Se Wan; Byun, Chang Woo; Kim, Hyung Yoon; Joo, So Na; Lee, Yong Woo; Yun, Seung Jae; Joo, Seung Ki

2013-10-01

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

NASA Astrophysics Data System (ADS)

Sadoghifar, Ali; Heikalabad, Saeed Rasouli

2018-05-01

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

Unifying Gate Synthesis and Magic State Distillation.

PubMed

Campbell, Earl T; Howard, Mark

2017-02-10

The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

Alpha power gates relevant information during working memory updating.

PubMed

Manza, Peter; Hau, Chui Luen Vera; Leung, Hoi-Chung

2014-04-23

Human working memory (WM) is inherently limited, so we must filter out irrelevant information in our environment or our mind while retaining limited important relevant contents. Previous work suggests that neural oscillations in the alpha band (8-14 Hz) play an important role in inhibiting incoming distracting information during attention and selective encoding tasks. However, whether alpha power is involved in inhibiting no-longer-relevant content or in representing relevant WM content is still debated. To clarify this issue, we manipulated the amount of relevant/irrelevant information using a task requiring spatial WM updating while measuring neural oscillatory activity via EEG and localized current sources across the scalp using a surface Laplacian transform. An initial memory set of two, four, or six spatial locations was to be memorized over a delay until an updating cue was presented indicating that only one or three locations remained relevant for a subsequent recognition test. Alpha amplitude varied with memory maintenance and updating demands among a cluster of left frontocentral electrodes. Greater postcue alpha power was associated with the high relevant load conditions (six and four dots cued to reduce to three relevant) relative to the lower load conditions (four and two dots reduced to one). Across subjects, this difference in alpha power was correlated with condition differences in performance accuracy. In contrast, no significant effects of irrelevant load were observed. These findings demonstrate that, during WM updating, alpha power reflects maintenance of relevant memory contents rather than suppression of no-longer-relevant memory traces.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Load-Dependent Increases in Delay-Period Alpha-Band Power Track the Gating of Task-Irrelevant Inputs to Working Memory.

PubMed

Heinz, Andrew J; Johnson, Jeffrey S

2017-01-01

Studies exploring the role of neural oscillations in cognition have revealed sustained increases in alpha-band power (ABP) during the delay period of verbal and visual working memory (VWM) tasks. There have been various proposals regarding the functional significance of such increases, including the inhibition of task-irrelevant cortical areas as well as the active retention of information in VWM. The present study examines the role of delay-period ABP in mediating the effects of interference arising from on-going visual processing during a concurrent VWM task. Specifically, we reasoned that, if set-size dependent increases in ABP represent the gating out of on-going task-irrelevant visual inputs, they should be predictive with respect to some modulation in visual evoked potentials resulting from a task-irrelevant delay period probe stimulus. In order to investigate this possibility, we recorded the electroencephalogram while subjects performed a change detection task requiring the retention of two or four novel shapes. On a portion of trials, a novel, task-irrelevant bilateral checkerboard probe was presented mid-way through the delay. Analyses focused on examining correlations between set-size dependent increases in ABP and changes in the magnitude of the P1, N1 and P3a components of the probe-evoked response and how such increases might be related to behavior. Results revealed that increased delay-period ABP was associated with changes in the amplitude of the N1 and P3a event-related potential (ERP) components, and with load-dependent changes in capacity when the probe was presented during the delay. We conclude that load-dependent increases in ABP likely play a role in supporting short-term retention by gating task-irrelevant sensory inputs and suppressing potential sources of disruptive interference.

Load-Dependent Increases in Delay-Period Alpha-Band Power Track the Gating of Task-Irrelevant Inputs to Working Memory

PubMed Central

Heinz, Andrew J.; Johnson, Jeffrey S.

2017-01-01

Studies exploring the role of neural oscillations in cognition have revealed sustained increases in alpha-band power (ABP) during the delay period of verbal and visual working memory (VWM) tasks. There have been various proposals regarding the functional significance of such increases, including the inhibition of task-irrelevant cortical areas as well as the active retention of information in VWM. The present study examines the role of delay-period ABP in mediating the effects of interference arising from on-going visual processing during a concurrent VWM task. Specifically, we reasoned that, if set-size dependent increases in ABP represent the gating out of on-going task-irrelevant visual inputs, they should be predictive with respect to some modulation in visual evoked potentials resulting from a task-irrelevant delay period probe stimulus. In order to investigate this possibility, we recorded the electroencephalogram while subjects performed a change detection task requiring the retention of two or four novel shapes. On a portion of trials, a novel, task-irrelevant bilateral checkerboard probe was presented mid-way through the delay. Analyses focused on examining correlations between set-size dependent increases in ABP and changes in the magnitude of the P1, N1 and P3a components of the probe-evoked response and how such increases might be related to behavior. Results revealed that increased delay-period ABP was associated with changes in the amplitude of the N1 and P3a event-related potential (ERP) components, and with load-dependent changes in capacity when the probe was presented during the delay. We conclude that load-dependent increases in ABP likely play a role in supporting short-term retention by gating task-irrelevant sensory inputs and suppressing potential sources of disruptive interference. PMID:28555099

The Role of Long-Term Memory in a Test of Visual Working Memory: Proactive Facilitation but no Proactive Interference

PubMed Central

Oberauer, Klaus; Awh, Edward; Sutterer, David W.

2016-01-01

We report four experiments examining whether associations in visual working memory are subject to proactive interference from long term memory (LTM). Following a long-term learning phase in which participants learned the colors of 120 unique objects, a working memory (WM) test was administered in which participants recalled the precise colors of three concrete objects in an array. Each array in the WM test consisted of one old (previously learned) object with a new color (old-mismatch), one old object with its old color (old-match), and one new object. Experiments 1 to 3 showed that WM performance was better in the old-match condition than in the new condition, reflecting a beneficial contribution from long term memory. In the old mismatch condition, participants sometimes reported colors associated with the relevant shape in LTM, but the probability of successful recall was equivalent to that in the new condition. Thus, information from LTM only intruded in the absence of reportable information in WM. Experiment 4 tested for, and failed to find, proactive interference from the preceding trial in the WM test: Performance in the old-mismatch condition, presenting an object from the preceding trial with a new color, was equal to performance with new objects. Experiment 5 showed that long-term memory for object-color associations is subject to proactive interference. We conclude that the exchange of information between LTM and WM appears to be controlled by a gating mechanism that protects the contents of WM from proactive interference but admits LTM information when it is useful. PMID:27685018

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Gate fidelity and coherence of an electron spin in an Si/SiGe quantum dot with micromagnet

DOE PAGES

Kawakami, Erika; Jullien, Thibaut; Scarlino, Pasquale; ...

2016-10-03

The gate fidelity and the coherence time of a quantum bit (qubit) are important benchmarks for quantum computation. We construct a qubit using a single electron spin in an Si/SiGe quantum dot and control it electrically via an artificial spin-orbit field from a micromagnet. We measure an average single-qubit gate fidelity of ~99% using randomized benchmarking, which is consistent with dephasing from the slowly evolving nuclear spins in the substrate. The coherence time measured using dynamical decoupling extends up to ~400 μs for 128 decoupling pulses, with no sign of saturation. We find evidence that the coherence time is limitedmore » by noise in the 10-kHz to 1-MHz range, possibly because charge noise affects the spin via the micromagnet gradient. Furthermore, this work shows that an electron spin in an Si/SiGe quantum dot is a good candidate for quantum information processing as well as for a quantum memory, even without isotopic purification.« less

Gate fidelity and coherence of an electron spin in an Si/SiGe quantum dot with micromagnet

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawakami, Erika; Jullien, Thibaut; Scarlino, Pasquale

The gate fidelity and the coherence time of a quantum bit (qubit) are important benchmarks for quantum computation. We construct a qubit using a single electron spin in an Si/SiGe quantum dot and control it electrically via an artificial spin-orbit field from a micromagnet. We measure an average single-qubit gate fidelity of ~99% using randomized benchmarking, which is consistent with dephasing from the slowly evolving nuclear spins in the substrate. The coherence time measured using dynamical decoupling extends up to ~400 μs for 128 decoupling pulses, with no sign of saturation. We find evidence that the coherence time is limitedmore » by noise in the 10-kHz to 1-MHz range, possibly because charge noise affects the spin via the micromagnet gradient. Furthermore, this work shows that an electron spin in an Si/SiGe quantum dot is a good candidate for quantum information processing as well as for a quantum memory, even without isotopic purification.« less

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel †

PubMed Central

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-01

We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e−/s at 60 °C. PMID:29370146

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel.

PubMed

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-25

Abstract : We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e - /s at 60 °C.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Cyclic Nucleotide-Gated Channels, Calmodulin, Adenylyl Cyclase, and Calcium/Calmodulin-Dependent Protein Kinase II Are Required for Late, but Not Early, Long-Term Memory Formation in the Honeybee

ERIC Educational Resources Information Center

Matsumoto, Yukihisa; Sandoz, Jean-Christophe; Devaud, Jean-Marc; Lormant, Flore; Mizunami, Makoto; Giurfa, Martin

2014-01-01

Memory is a dynamic process that allows encoding, storage, and retrieval of information acquired through individual experience. In the honeybee "Apis mellifera," olfactory conditioning of the proboscis extension response (PER) has shown that besides short-term memory (STM) and mid-term memory (MTM), two phases of long-term memory (LTM)…

Toxoplasma gondii strain-dependent effects on mouse behaviour.

PubMed

Kannan, Geetha; Moldovan, Krisztina; Xiao, Jian-Chun; Yolken, Robert H; Jones-Brando, Lorraine; Pletnikov, Mikhail V

2010-06-01

Toxoplasma gondii reportedly manipulates rodent behaviour to increase transmission to its definitive feline host. We compared the effects of mouse infection by two Type II strains of T. gondii, Prugniaud (PRU) and ME49, on attraction to cat odour, locomotor activity, anxiety, sensorimotor gating, and spatial working and recognition memory 2 months post-infection (mpi). Attraction to cat odour was reassessed 7 mpi. At 2 mpi, mice infected with either strain exhibited significantly more attraction to cat odour than uninfected animals did, but only PRU-infected mice exhibited this behaviour 7 mpi. PRU-infected mice had significantly greater body weights and hyperactivity, while ME49-infected mice exhibited impaired spatial working memory. No differences in parasite antibody titres were seen between PRU- and ME49-infected mice. The present data suggest the effect of T. gondii infection on mouse behaviour is parasite strain-dependent.

Upsets in Erased Floating Gate Cells With High-Energy Protons

DOE PAGES

Gerardin, S.; Bagatin, M.; Paccagnella, A.; ...

2017-01-01

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Synthesis of energy-efficient FSMs implemented in PLD circuits

NASA Astrophysics Data System (ADS)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

NASA Astrophysics Data System (ADS)

Pavel, Akeed A.; Khan, Mehjabeen A.; Kirawanich, Phumin; Islam, N. E.

2008-10-01

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al 2O 3 has been compared with similar structure consisting of Si nanocrystals in SiO 2 to validate the concept.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

NASA Technical Reports Server (NTRS)

Nelson, G. L.; Krahn, D. R.; Dean, R. H.; Paul, M. C.; Lo, D. S.; Amundsen, D. L.; Stein, G. A.

1985-01-01

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Attention Gating in Short-Term Visual Memory.

ERIC Educational Resources Information Center

Reeves, Adam; Sperling, George

1986-01-01

An experiment is conducted showing that an attention shift to a stream of numerals presented in rapid serial visual presentation mode produces not a total loss, but a systematic distortion of order. An attention gating model (AGM) is developed from a more general attention model. (Author/LMO)

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klymenko, M. V.; Klein, M.; Levine, R. D.

2016-07-14

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states correspondsmore » to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.« less

State memory in solution gated epitaxial graphene

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Y.; Lebedev, S. P.; Lebedev, A. A.; Davydov, V. Y.; Smirnov, A. N.; Eliseyev, I. A.; Dunaevskiy, M. S.; Kumzerov, Y. A.

2018-06-01

We studied electrical transport in transistors fabricated on a surface of high quality epitaxial graphene with density of defects as low as 5·1010 cm-2 and observed quasistatic hysteresis with a time constant in a scale of hours. This constant is in a few orders of magnitude greater than the constant previously reported in CVD graphene. The hysteresis observed here can be described as a shift of ∼+2V of the Dirac point measured during a gate voltage increase from the position of the Dirac point measured during a gate voltage decrease. This hysteresis can be characterized as a nonvolatile quasistatic state memory effect in which the state of the gated graphene is determined by its initial state prior to entering the hysteretic region. Due to this effect the difference in resistance of the gated graphene measured in the hysteretic region at the same applied voltages can be as high as 70%. The observed effect can be explained by assuming that charge carriers in graphene and oppositely charged molecular ions from the solution form quasistable interfacial complexes at the graphene interface. These complexes likely preserve the initial state by preventing charge carriers in graphene from discharging in the hysteretic region.

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

The Role of Anterior Nuclei of the Thalamus: A Subcortical Gate in Memory Processing: An Intracerebral Recording Study.

PubMed

Štillová, Klára; Jurák, Pavel; Chládek, Jan; Chrastina, Jan; Halámek, Josef; Bočková, Martina; Goldemundová, Sabina; Říha, Ivo; Rektor, Ivan

2015-01-01

To study the involvement of the anterior nuclei of the thalamus (ANT) as compared to the involvement of the hippocampus in the processes of encoding and recognition during visual and verbal memory tasks. We studied intracerebral recordings in patients with pharmacoresistent epilepsy who underwent deep brain stimulation (DBS) of the ANT with depth electrodes implanted bilaterally in the ANT and compared the results with epilepsy surgery candidates with depth electrodes implanted bilaterally in the hippocampus. We recorded the event-related potentials (ERPs) elicited by the visual and verbal memory encoding and recognition tasks. P300-like potentials were recorded in the hippocampus by visual and verbal memory encoding and recognition tasks and in the ANT by the visual encoding and visual and verbal recognition tasks. No significant ERPs were recorded during the verbal encoding task in the ANT. In the visual and verbal recognition tasks, the P300-like potentials in the ANT preceded the P300-like potentials in the hippocampus. The ANT is a structure in the memory pathway that processes memory information before the hippocampus. We suggest that the ANT has a specific role in memory processes, especially memory recognition, and that memory disturbance should be considered in patients with ANT-DBS and in patients with ANT lesions. ANT is well positioned to serve as a subcortical gate for memory processing in cortical structures.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Adult forebrain NMDA receptors gate social motivation and social memory.

PubMed

Jacobs, Stephanie; Tsien, Joe Z

2017-02-01

Motivation to engage in social interaction is critical to ensure normal social behaviors, whereas dysregulation in social motivation can contribute to psychiatric diseases such as schizophrenia, autism, social anxiety disorders and post-traumatic stress disorder (PTSD). While dopamine is well known to regulate motivation, its downstream targets are poorly understood. Given the fact that the dopamine 1 (D1) receptors are often physically coupled with the NMDA receptors, we hypothesize that the NMDA receptor activity in the adult forebrain principal neurons are crucial not only for learning and memory, but also for the proper gating of social motivation. Here, we tested this hypothesis by examining sociability and social memory in inducible forebrain-specific NR1 knockout mice. These mice are ideal for exploring the role of the NR1 subunit in social behavior because the NR1 subunit can be selectively knocked out after the critical developmental period, in which NR1 is required for normal development. We found that the inducible deletion of the NMDA receptors prior to behavioral assays impaired, not only object and social recognition memory tests, but also resulted in profound deficits in social motivation. Mice with ablated NR1 subunits in the forebrain demonstrated significant decreases in sociability compared to their wild type counterparts. These results suggest that in addition to its crucial role in learning and memory, the NMDA receptors in the adult forebrain principal neurons gate social motivation, independent of neuronal development. Copyright © 2016 Elsevier Inc. All rights reserved.

Comparisons of single event vulnerability of GaAs SRAMS

NASA Astrophysics Data System (ADS)

Weatherford, T. R.; Hauser, J. R.; Diehl, S. E.

1986-12-01

A GaAs MESFET/JFET model incorporated into SPICE has been used to accurately describe C-EJFET, E/D MESFET and D MESFET/resistor GaAs memory technologies. These cells have been evaluated for critical charges due to gate-to-drain and drain-to-source charge collection. Low gate-to-drain critical charges limit conventional GaAs SRAM soft error rates to approximately 1E-6 errors/bit-day. SEU hardening approaches including decoupling resistors, diodes, and FETs have been investigated. Results predict GaAs RAM cell critical charges can be increased to over 0.1 pC. Soft error rates in such hardened memories may approach 1E-7 errors/bit-day without significantly reducing memory speed. Tradeoffs between hardening level, performance and fabrication complexity are discussed.

All-optical XNOR/NOT logic gates and LATCH based on a reflective vertical cavity semiconductor saturable absorber.

PubMed

Pradhan, Rajib

2014-06-10

This work proposes a scheme of all-optical XNOR/NOT logic gates based on a reflective vertical cavity semiconductor (quantum wells, QWs) saturable absorber (VCSSA). In a semiconductor Fabry-Perot cavity operated with a low-intensity resonance wavelength, both intensity-dependent saturating phase-shift and thermal phase-shift occur, which are considered in the proposed logic operations. The VCSSA-based logics are possible using the saturable behavior of reflectivity under the typical operating conditions. The low-intensity saturable reflectivity is reported for all-optical logic operations where all possible nonlinear phase-shifts are ignored. Here, saturable absorption (SA) and the nonlinear phase-shift-based all-optical XNOR/NOT gates and one-bit memory or LATCH are proposed under new operating conditions. All operations are demonstrated for a VCSSA based on InGaAs/InP QWs. These types of SA-based logic devices can be comfortably used for a signal bit rate of about 10 GHz corresponding to the carrier recovery time of the semiconductor material.

The role of long-term memory in a test of visual working memory: Proactive facilitation but no proactive interference.

PubMed

Oberauer, Klaus; Awh, Edward; Sutterer, David W

2017-01-01

We report 4 experiments examining whether associations in visual working memory are subject to proactive interference from long-term memory (LTM). Following a long-term learning phase in which participants learned the colors of 120 unique objects, a working memory (WM) test was administered in which participants recalled the precise colors of 3 concrete objects in an array. Each array in the WM test consisted of 1 old (previously learned) object with a new color (old-mismatch), 1 old object with its old color (old-match), and 1 new object. Experiments 1 to 3 showed that WM performance was better in the old-match condition than in the new condition, reflecting a beneficial contribution from LTM. In the old-mismatch condition, participants sometimes reported colors associated with the relevant shape in LTM, but the probability of successful recall was equivalent to that in the new condition. Thus, information from LTM only intruded in the absence of reportable information in WM. Experiment 4 tested for, and failed to find, proactive interference from the preceding trial in the WM test: Performance in the old-mismatch condition, presenting an object from the preceding trial with a new color, was equal to performance with new objects. Experiment 5 showed that long-term memory for object-color associations is subject to proactive interference. We conclude that the exchange of information between LTM and WM appears to be controlled by a gating mechanism that protects the contents of WM from proactive interference but admits LTM information when it is useful. (PsycINFO Database Record (c) 2017 APA, all rights reserved).

A risk PRODH haplotype affects sensorimotor gating, memory, schizotypy, and anxiety in healthy male subjects.

PubMed

Roussos, Panos; Giakoumaki, Stella G; Bitsios, Panos

2009-06-15

Significant associations have been shown for haplotypes comprising three PRODH single nucleotide polymorphisms (SNPs; 1945T/C, 1766A/G, 1852G/A) located in the 3' region of the gene, suggesting a role of these variants in the etiopathogenesis of schizophrenia. We assessed the relationship between these high-risk PRODH polymorphisms and schizophrenia-related endophenotypes in a large and highly homogeneous cohort of healthy males. Participants (n = 217) were tested in prepulse inhibition (PPI), verbal and working memory, trait anxiety and schizotypy. The QTPHASE from the UNPHASED package was used for the association analysis of each SNP or haplotype data. This procedure revealed significant phenotypic impact of the risk CGA haplotype. Subjects were then divided in two groups; levels of PPI, anxiety, and schizotypy, verbal and working memory were compared with analysis of variance. CGA carriers (n = 32) exhibited attenuated PPI (p < .001) and verbal memory (p < .001) and higher anxiety (p < .004) and schizotypy (p < .008) compared with the noncarriers (n = 185). There were no differences in baseline startle, demographics, and working memory. The main significant correlations were schizotypy x PPI [85-dB, 120-msec trials] in the carriers and schizotypy x anxiety in the entire group and the noncarriers but not the carriers group. Our results strongly support PPI as a valid schizophrenia endophenotype and highlight the importance of examining the role of risk haplotypes on multiple endophenotypes and have implications for understanding the continuum from normality to psychosis, transitional states, and the genetics of schizophrenia-related traits.

A cog in cognition: how the alpha 7 nicotinic acetylcholine receptor is geared towards improving cognitive deficits.

PubMed

Leiser, Steven C; Bowlby, Mark R; Comery, Thomas A; Dunlop, John

2009-06-01

Cognition, memory, and attention and arousal have been linked to nicotinic acetylcholine receptors (nAChRs). Thus it is not surprising that nAChRs have been strongly implicated as therapeutic targets for treating cognitive deficits in disorders such as schizophrenia and Alzheimer's disease (AD). In particular the alpha7 (alpha7) nAChR has been closely linked with normalization of P50 auditory evoked potential (AEP) gating deficits, and to a lesser extent improvements in pre-pulse inhibition (PPI) of the acoustic startle response. These two brain phenomena can be considered as pre-attentive, occurring while sensory information is being processed, and are important endophenotypes in schizophrenia with deficits likely contributing to the cognitive fragmentation associated with the disease. In addition alpha7 nAChRs have been implicated in attention, in particular under high attentional demand, and in more demanding working memory tasks such as long delays in delayed matching tasks. Efficacy of alpha7 nAChR agonists across a range of cognitive processes ranging from pre-attentive to attentive states and working and recognition memory provides a solid basis for their pro-cognitive effects. This review will focus on the recent work highlighting the role of alpha7 in cognition and cognitive processes.

Beyond capacity limitations II: Effects of lexical processes on word recall in verbal working memory tasks in children with and without specific language impairment

PubMed Central

Mainela-Arnold, Elina; Evans, Julia L.; Coady, Jeffry

2010-01-01

Purpose This study investigated the impact of lexical processes on target word recall in sentence span tasks in children with and without specific language impairment (SLI). Method Participants were 42 children (ages 8;2–12;3), 21 with SLI and 21 typically developing peers matched on age and nonverbal IQ. Children completed a sentence span task where target words to be recalled varied in word frequency and neighborhood density. Two measures of lexical processes were examined, the number of non-target competitor words activated during a gating task (lexical cohort competition) and word definitions. Results Neighborhood density had no effect on word recall for either group. However, both groups recalled significantly more high than low frequency words. Lexical cohort competition and specificity of semantic representations accounted for unique variance in the number of target word recalled in the SLI and CA groups combined. Conclusions Performance on verbal working memory span tasks for both SLI and CA children is influenced by word frequency, lexical cohorts, and semantic representations. Future studies need to examine the extent to which verbal working memory capacity is a cognitive construct independent of extant language knowledge representations. PMID:20705747

SONOS Nonvolatile Memory Cell Programming Characteristics

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Histone Deacetylase Inhibition via RGFP966 Releases the Brakes on Sensory Cortical Plasticity and the Specificity of Memory Formation.

PubMed

Bieszczad, Kasia M; Bechay, Kiro; Rusche, James R; Jacques, Vincent; Kudugunti, Shashi; Miao, Wenyan; Weinberger, Norman M; McGaugh, James L; Wood, Marcelo A

2015-09-23

Research over the past decade indicates a novel role for epigenetic mechanisms in memory formation. Of particular interest is chromatin modification by histone deacetylases (HDACs), which, in general, negatively regulate transcription. HDAC deletion or inhibition facilitates transcription during memory consolidation and enhances long-lasting forms of synaptic plasticity and long-term memory. A key open question remains: How does blocking HDAC activity lead to memory enhancements? To address this question, we tested whether a normal function of HDACs is to gate information processing during memory formation. We used a class I HDAC inhibitor, RGFP966 (C21H19FN4O), to test the role of HDAC inhibition for information processing in an auditory memory model of learning-induced cortical plasticity. HDAC inhibition may act beyond memory enhancement per se to instead regulate information in ways that lead to encoding more vivid sensory details into memory. Indeed, we found that RGFP966 controls memory induction for acoustic details of sound-to-reward learning. Rats treated with RGFP966 while learning to associate sound with reward had stronger memory and additional information encoded into memory for highly specific features of sounds associated with reward. Moreover, behavioral effects occurred with unusually specific plasticity in primary auditory cortex (A1). Class I HDAC inhibition appears to engage A1 plasticity that enables additional acoustic features to become encoded in memory. Thus, epigenetic mechanisms act to regulate sensory cortical plasticity, which offers an information processing mechanism for gating what and how much is encoded to produce exceptionally persistent and vivid memories. Significance statement: Here we provide evidence of an epigenetic mechanism for information processing. The study reveals that a class I HDAC inhibitor (Malvaez et al., 2013; Rumbaugh et al., 2015; RGFP966, chemical formula C21H19FN4O) alters the formation of auditory memory by enabling more acoustic information to become encoded into memory. Moreover, RGFP966 appears to affect cortical plasticity: the primary auditory cortex reorganized in a manner that was unusually "tuned-in" to the specific sound cues and acoustic features that were related to reward and subsequently remembered. We propose that HDACs control "informational capture" at a systems level for what and how much information is encoded by gating sensory cortical plasticity that underlies the sensory richness of newly formed memories. Copyright © 2015 the authors 0270-6474/15/3513125-09$15.00/0.

Histone Deacetylase Inhibition via RGFP966 Releases the Brakes on Sensory Cortical Plasticity and the Specificity of Memory Formation

PubMed Central

Bechay, Kiro; Rusche, James R.; Jacques, Vincent; Kudugunti, Shashi; Miao, Wenyan; Weinberger, Norman M.; McGaugh, James L.

2015-01-01

Research over the past decade indicates a novel role for epigenetic mechanisms in memory formation. Of particular interest is chromatin modification by histone deacetylases (HDACs), which, in general, negatively regulate transcription. HDAC deletion or inhibition facilitates transcription during memory consolidation and enhances long-lasting forms of synaptic plasticity and long-term memory. A key open question remains: How does blocking HDAC activity lead to memory enhancements? To address this question, we tested whether a normal function of HDACs is to gate information processing during memory formation. We used a class I HDAC inhibitor, RGFP966 (C21H19FN4O), to test the role of HDAC inhibition for information processing in an auditory memory model of learning-induced cortical plasticity. HDAC inhibition may act beyond memory enhancement per se to instead regulate information in ways that lead to encoding more vivid sensory details into memory. Indeed, we found that RGFP966 controls memory induction for acoustic details of sound-to-reward learning. Rats treated with RGFP966 while learning to associate sound with reward had stronger memory and additional information encoded into memory for highly specific features of sounds associated with reward. Moreover, behavioral effects occurred with unusually specific plasticity in primary auditory cortex (A1). Class I HDAC inhibition appears to engage A1 plasticity that enables additional acoustic features to become encoded in memory. Thus, epigenetic mechanisms act to regulate sensory cortical plasticity, which offers an information processing mechanism for gating what and how much is encoded to produce exceptionally persistent and vivid memories. SIGNIFICANCE STATEMENT Here we provide evidence of an epigenetic mechanism for information processing. The study reveals that a class I HDAC inhibitor (Malvaez et al., 2013; Rumbaugh et al., 2015; RGFP966, chemical formula C21H19FN4O) alters the formation of auditory memory by enabling more acoustic information to become encoded into memory. Moreover, RGFP966 appears to affect cortical plasticity: the primary auditory cortex reorganized in a manner that was unusually “tuned-in” to the specific sound cues and acoustic features that were related to reward and subsequently remembered. We propose that HDACs control “informational capture” at a systems level for what and how much information is encoded by gating sensory cortical plasticity that underlies the sensory richness of newly formed memories. PMID:26400942

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Because advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

DTIC Science & Technology

2008-10-01

memory interface, arbiter/ schedulers for rescheduling the memory requests according to some schedule policy, and memory channels for communicating...between the power-savings and the wakeup overhead with respect to both wakeup power and wakeup delay. For example, dream mode can save 50% more static...power than sleep mode, but at the expense of twice the wake delay and three times the wakeup energy. The user can specify power-gating modes for various components.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Microdose Induced Data Loss on Floating Gate Memories

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Nguyen, Duc M.; Patterson, Jeffrey D.

2006-01-01

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

Cobalt germanide nanostructure formation and memory characteristic enhancement in silicon oxide films

NASA Astrophysics Data System (ADS)

Joo, Beom Soo; Kim, Hyunseung; Jang, Seunghun; Han, Dongwoo; Han, Moonsup

2018-08-01

We investigated nano-floating gate memory having a charge trap layer (CTL) composed of cobalt germanide nanostructure (ns-CoGe). A tunneling oxide layer; a CTL containing Co, Ge, and Si; and a blocking oxide layer were sequentially deposited on a p-type silicon substrate by RF magnetron sputtering and low-pressure chemical vapor deposition. We optimized the CTL formation conditions by rapid thermal annealing at a somewhat low temperature (about 830 °C) by considering the differences in Gibbs free energy and chemical enthalpy among the components. To characterize the charge storage properties, capacitance-voltage (C-V) measurements were performed. Further, we used X-ray photoelectron spectroscopy for chemical analysis of the CTL. In this work, we not only report that the C-V measurement shows a remarkable opening of the memory window for the ns-CoGe compared with those of nanostructures composed of Co or Ge alone, but also clarify that the improvement in the memory characteristics originates in the nanostructure formation, which consists mainly of Co-Ge bonds. We expect ns-CoGe to be a strong candidate for fabrication of next-generation memory devices.

Ferroelectric memory based on molybdenum disulfide and ferroelectric hafnium oxide

NASA Astrophysics Data System (ADS)

Yap, Wui Chung; Jiang, Hao; Xia, Qiangfei; Zhu, Wenjuan

Recently, ferroelectric hafnium oxide (HfO2) was discovered as a new type of ferroelectric material with the advantages of high coercive field, excellent scalability (down to 2.5 nm), and good compatibility with CMOS processing. In this work, we demonstrate, for the first time, 2D ferroelectric memories with molybdenum disulfide (MoS2) as the channel material and aluminum doped HfO2 as the ferroelectric gate dielectric. A 16 nm thick layer of HfO2, doped with 5.26% aluminum, was deposited via atomic layer deposition (ALD), then subjected to rapid thermal annealing (RTA) at 1000 °C, and the polarization-voltage characteristics of the resulting metal-ferroelectric-metal (MFM) capacitors were measured, showing a remnant polarization of 0.6 μC/cm2. Ferroelectric memories with embedded ferroelectric hafnium oxide stacks and monolayer MoS2 were fabricated. The transfer characteristics after program and erase pulses revealed a clear ferroelectric memory window. In addition, endurance (up to 10,000 cycles) of the devices were tested and effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, were observed. This research can potentially lead to advances of 2D materials in low-power logic and memory applications.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

PubMed

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

Causes and consequences of limitations in visual working memory

PubMed Central

Zokaei, Nahid; Husain, Masud

2016-01-01

Recent methodological and conceptual advances have led to a fundamental reappraisal of the nature of visual working memory (WM). A large corpus of evidence now suggests that there might not be a hard limit on the number of items that can be stored. Instead, WM may be better captured by a highly limited––but flexible––resource model. More resource can be allocated to prioritized items but, crucially, at a cost of reduced recall precision for other stored items. Expectations may modulate resource distribution, for example, through neural oscillations in the alpha band increasing inhibition of irrelevant cortical regions. Our understanding of the neural architecture of WM is also undergoing radical revision. Whereas the prefrontal cortex has previously dominated research endeavors, other cortical regions, such as early visual areas, are now considered to make an essential contribution, for example holding one or more items in a privileged state or “focus of attention” within WM. By contrast, the striatum is increasingly viewed as crucial in determining why and how items are gated into memory, while the hippocampus, it has controversially been argued, might be critical in the formation of temporally resilient conjunctions across features of stored items in WM. PMID:26773268

Thermal Stress Analysis of Floating-Gate Tunneling Oxide Electrically Erasable Programmable Read Only Memory During Manufacturing Process

NASA Astrophysics Data System (ADS)

Zong, Xiang-fu; Wang, Xu; Weng, Yu-min; Yan, Ren-jin; Tang, Guo-an; Zhang, Zhao-qiang

1998-10-01

In this study, finite element modeling was used to evaluate the residual thermal stress in floating-gate tunneling oxide electrically erasable programmable read only memory (FLOTOX E2 PROMs) manufacturing process. Special attention is paid to the tunnel oxide region, in which high field electron injection is the basis to E2 PROMs operation. Calculated results show the presence of large stresses and stress gradients at the fringe. This may contribute to the invalidation of E2 PROMs. A possible failure mechanism of E2 PROM related to residual thermal stress-induced leakage is proposed.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

The Role of Anterior Nuclei of the Thalamus: A Subcortical Gate in Memory Processing: An Intracerebral Recording Study

PubMed Central

Štillová, Klára; Jurák, Pavel; Chládek, Jan; Chrastina, Jan; Halámek, Josef; Bočková, Martina; Goldemundová, Sabina; Říha, Ivo; Rektor, Ivan

2015-01-01

Objective To study the involvement of the anterior nuclei of the thalamus (ANT) as compared to the involvement of the hippocampus in the processes of encoding and recognition during visual and verbal memory tasks. Methods We studied intracerebral recordings in patients with pharmacoresistent epilepsy who underwent deep brain stimulation (DBS) of the ANT with depth electrodes implanted bilaterally in the ANT and compared the results with epilepsy surgery candidates with depth electrodes implanted bilaterally in the hippocampus. We recorded the event-related potentials (ERPs) elicited by the visual and verbal memory encoding and recognition tasks. Results P300-like potentials were recorded in the hippocampus by visual and verbal memory encoding and recognition tasks and in the ANT by the visual encoding and visual and verbal recognition tasks. No significant ERPs were recorded during the verbal encoding task in the ANT. In the visual and verbal recognition tasks, the P300-like potentials in the ANT preceded the P300-like potentials in the hippocampus. Conclusions The ANT is a structure in the memory pathway that processes memory information before the hippocampus. We suggest that the ANT has a specific role in memory processes, especially memory recognition, and that memory disturbance should be considered in patients with ANT-DBS and in patients with ANT lesions. ANT is well positioned to serve as a subcortical gate for memory processing in cortical structures. PMID:26529407

A parallel algorithm for multi-level logic synthesis using the transduction method. M.S. Thesis

NASA Technical Reports Server (NTRS)

Lim, Chieng-Fai

1991-01-01

The Transduction Method has been shown to be a powerful tool in the optimization of multilevel networks. Many tools such as the SYLON synthesis system (X90), (CM89), (LM90) have been developed based on this method. A parallel implementation is presented of SYLON-XTRANS (XM89) on an eight processor Encore Multimax shared memory multiprocessor. It minimizes multilevel networks consisting of simple gates through parallel pruning, gate substitution, gate merging, generalized gate substitution, and gate input reduction. This implementation, called Parallel TRANSduction (PTRANS), also uses partitioning to break large circuits up and performs inter- and intra-partition dynamic load balancing. With this, good speedups and high processor efficiencies are achievable without sacrificing the resulting circuit quality.

FPGA Vision Data Architecture

NASA Technical Reports Server (NTRS)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

Deterministic quantum controlled-PHASE gates based on non-Markovian environments

NASA Astrophysics Data System (ADS)

Zhang, Rui; Chen, Tian; Wang, Xiang-Bin

2017-12-01

We study the realization of the quantum controlled-PHASE gate in an atom-cavity system beyond the Markovian approximation. The general description of the dynamics for the atom-cavity system without any approximation is presented. When the spectral density of the reservoir has the Lorentz form, by making use of the memory backflow from the reservoir, we can always construct the deterministic quantum controlled-PHASE gate between a photon and an atom, no matter the atom-cavity coupling strength is weak or strong. While, the phase shift in the output pulse hinders the implementation of quantum controlled-PHASE gates in the sub-Ohmic, Ohmic or super-Ohmic reservoirs.

Investigation of multi-state charge-storage properties of redox-active organic molecules in silicon-molecular hybrid devices for DRAM and Flash applications

NASA Astrophysics Data System (ADS)

Gowda, Srivardhan Shivappa

Molecular electronics has recently spawned a considerable amount of interest with several molecules possessing charge-conduction and charge-storage properties proposed for use in electronic devices. Hybrid silicon-molecular technology has the promise of augmenting the current silicon technology and provide for a transitional path to future molecule-only technology. The focus of this dissertation work has been on developing a class of hybrid silicon-molecular electronic devices for DRAM and Flash memory applications utilizing redox-active molecules. This work exploits the ability of molecules to store charges with single-electron precision at room temperature. The hybrid devices are fabricated by forming self-assembled monolayers of redox-active molecules on Si and oxide (SiO2 and HfO2) surfaces via formation of covalent linkages. The molecules possess discrete quantum states from which electrons can tunnel to the Si substrate at discrete applied voltages (oxidation process, cell write), leaving behind a positively charged layer of molecules. The reduction (erase) process, which is the process of electrons tunneling back from Si to the molecules, neutralizes the positively charged molecular monolayer. Hybrid silicon-molecular capacitor test structures were electrically characterized with an electrolyte gate using cyclic voltammetry (CyV) and impedance spectroscopy (CV) techniques. The redox voltages, kinetics (write/erase speeds) and charge-retention characteristics were found to be strongly dependent on the Si doping type and densities, and ambient light. It was also determined that the redox energy states in the molecules communicate with the valence band of the Si substrate. This allows tuning of write and read states by modulating minority carriers in n- and p-Si substrates. Ultra-thin dielectric tunnel barriers (SiO2, HfO2) were placed between the molecules and the Si substrate to augment charge-retention for Flash memory applications. The redox response was studied as a function of tunnel oxide thickness, dielectric permittivity and energy barrier, and modified Butler-Volmer expressions were postulated to describe the redox kinetics. The speed vs. retention performance of the devices was improved via asymmetric layered tunnel barriers. The properties of molecules can be tailored by molecular design and synthetic chemistry. In this work, it was demonstrated that an alternate route to tune/enhance the properties of the hybrid device is to engineer the substrate (silicon) component. The molecules were attached to diode surfaces to tune redox voltages and improve charge-retention characteristics. N+ pockets embedded in P-Si well were utilized to obtain multiple states from a two-state molecule. The structure was also employed as a characterization tool in investigating the intrinsic properties of the molecules such as lateral conductivity within the monolayer. Redox molecules were also incorporated on an ultra thin gate-oxide of Si MOSFETs with the intent of studying the interaction of redox states with Si MOSFETs. The discrete molecular states were manifested in the drain current and threshold voltage characteristics of the device. This work demonstrates the multi-state modulation of Si-MOSFETs' drain current via redox-active molecular monolayers. Polymeric films of redox-active molecules were incorporated to improve the charge-density (ON/OFF ratio) and these structures may be employed for multi-state, low-voltage Flash memory applications. The most critical aspect of this research effort is to build a reliable and high density solid state memory technology. To this end, efforts were directed towards replacement of the electrolytic gate, which forms an extremely thin insulating double layer (˜10 nm) at the electrolyte-molecule interface, with a combination of an ultra-thin high-K dielectric layer and a metal gate. Several interesting observations were made in the research approaches towards integration and provided valuable insights into the electrolyte-redox systems. In summary, this work provides fundamental insights into the interaction of redox-energy states with silicon substrate and realistic approaches for exploiting the unique properties of the molecules that may enable solutions for nanoscale high density, low-voltage, long retention and multiple bit memory applications.

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Quantum random access memory.

PubMed

Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

2008-04-25

A random access memory (RAM) uses n bits to randomly address N=2(n) distinct memory cells. A quantum random access memory (QRAM) uses n qubits to address any quantum superposition of N memory cells. We present an architecture that exponentially reduces the requirements for a memory call: O(logN) switches need be thrown instead of the N used in conventional (classical or quantum) RAM designs. This yields a more robust QRAM algorithm, as it in general requires entanglement among exponentially less gates, and leads to an exponential decrease in the power needed for addressing. A quantum optical implementation is presented.

Calcium homeostasis and protein kinase/phosphatase balance participate in nicotine-induced memory improvement in passive avoidance task in mice.

PubMed

Michalak, Agnieszka; Biala, Grazyna

2017-01-15

Long-term potentiation (LTP) and long-term depression (LTD) depend on specific postsynaptic Ca 2+ /calmodulin concentration. LTP results from Ca 2+ influx through the activated NMDA receptors or voltage-gated calcium channels (VGCCs) and is linked with activation of protein kinases including mitogen-activated protein kinase (MAPK). Weaker synaptic stimulation, as a result of low Ca 2+ influx, leads to activation of Ca 2+ /calmodulin-dependent phosphatase (calcineurin - CaN) and triggers LTD. Interestingly, both memory formation and drug addiction share similar neuroplastic changes. Nicotine, which is one of the most common addictive drugs, manifests its memory effects through nicotinic acetylcholine receptors (nAChRs). Because nAChRs may also gate Ca 2+ , it is suggested that calcium signaling pathways are involved in nicotine-induced memory effects. Within the scope of the study was to evaluate the importance of calcium homeostasis and protein kinase/phosphatase balance in nicotine-induced short- and long-term memory effects. To assess memory function in mice passive avoidance test was used. The presented results confirm that acute nicotine (0.1mg/kg) improves short- and long-term memory. Pretreatment with L-type VGCC blockers (amlodipine, nicardipine verapamil) increased nicotine-induced memory improvement in the context of short- and long-term memory. Pretreatment with FK-506 (a potent CaN inhibitor) enhanced short- but not long-term memory effects of nicotine, while SL-327 (a selective MAPK/ERK kinase inhibitor) attenuated both nicotine-induced short- and long-term memory improvement. Acute nicotine enhances both types of memory via L-type VGCC blockade and via ERK1/2 activation. Only short- but not long-term memory enhancement induced by nicotine is dependent on CaN inhibition. Copyright © 2016 Elsevier B.V. All rights reserved.

Memristors in plants

PubMed Central

Volkov, Alexander G; Tucket, Clayton; Reedus, Jada; Volkova, Maya I; Markin, Vladislav S; Chua, Leon

2014-01-01

We investigated electrical circuitry of the Venus flytrap, Mimosa pudica and Aloe vera. The goal was to discover if these plants might have a new electrical component—a resistor with memory. This element has attracted great interest recently and the researchers were looking for its presence in different systems. The analysis was based on cyclic current-voltage characteristic where the resistor with memory should manifest itself. We found that the electrostimulation of plants by bipolar sinusoidal or triangle periodic waves induces electrical responses in the Venus flytrap, Mimosa pudica and Aloe vera with fingerprints of memristors. Tetraethylammonium chloride, an inhibitor of voltage gated K+ channels, transforms a memristor to a resistor in plant tissue. Our results demonstrate that a voltage gated K+ channel in the excitable tissue of plants has properties of a memristor. This study can be a starting point for understanding mechanisms of memory, learning, circadian rhythms, and biological clocks. PMID:24556876

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Persistent anterograde amnesia following limbic encephalitis associated with antibodies to the voltage-gated potassium channel complex.

PubMed

Butler, Christopher R; Miller, Thomas D; Kaur, Manveer S; Baker, Ian W; Boothroyd, Georgie D; Illman, Nathan A; Rosenthal, Clive R; Vincent, Angela; Buckley, Camilla J

2014-04-01

Limbic encephalitis (LE) associated with antibodies to the voltage-gated potassium channel complex (VGKC) is a potentially reversible cause of cognitive impairment. Despite the prominence of cognitive dysfunction in this syndrome, little is known about patients' neuropsychological profile at presentation or their long-term cognitive outcome. We used a comprehensive neuropsychological test battery to evaluate cognitive function longitudinally in 19 patients with VGKC-LE. Before immunotherapy, the group had significant impairment of memory, processing speed and executive function, whereas language and perceptual organisation were intact. At follow-up, cognitive impairment was restricted to the memory domain, with processing speed and executive function having returned to the normal range. Residual memory function was predicted by the antibody titre at presentation. The results show that, despite broad cognitive dysfunction in the acute phase, patients with VGKC-LE often make a substantial recovery with immunotherapy but may be left with permanent anterograde amnesia.

Phosphodiesterase 9A regulates central cGMP and modulates responses to cholinergic and monoaminergic perturbation in vivo.

PubMed

Kleiman, Robin J; Chapin, Douglas S; Christoffersen, Curt; Freeman, Jody; Fonseca, Kari R; Geoghegan, Kieran F; Grimwood, Sarah; Guanowsky, Victor; Hajós, Mihály; Harms, John F; Helal, Christopher J; Hoffmann, William E; Kocan, Geralyn P; Majchrzak, Mark J; McGinnis, Dina; McLean, Stafford; Menniti, Frank S; Nelson, Fredrick; Roof, Robin; Schmidt, Anne W; Seymour, Patricia A; Stephenson, Diane T; Tingley, Francis David; Vanase-Frawley, Michelle; Verhoest, Patrick R; Schmidt, Christopher J

2012-05-01

Cyclic nucleotides are critical regulators of synaptic plasticity and participate in requisite signaling cascades implicated across multiple neurotransmitter systems. Phosphodiesterase 9A (PDE9A) is a high-affinity, cGMP-specific enzyme widely expressed in the rodent central nervous system. In the current study, we observed neuronal staining with antibodies raised against PDE9A protein in human cortex, cerebellum, and subiculum. We have also developed several potent, selective, and brain-penetrant PDE9A inhibitors and used them to probe the function of PDE9A in vivo. Administration of these compounds to animals led to dose-dependent accumulation of cGMP in brain tissue and cerebrospinal fluid, producing a range of biological effects that implied functional significance for PDE9A-regulated cGMP in dopaminergic, cholinergic, and serotonergic neurotransmission and were consistent with the widespread distribution of PDE9A. In vivo effects of PDE9A inhibition included reversal of the respective disruptions of working memory by ketamine, episodic and spatial memory by scopolamine, and auditory gating by amphetamine, as well as potentiation of risperidone-induced improvements in sensorimotor gating and reversal of the stereotypic scratching response to the hallucinogenic 5-hydroxytryptamine 2A agonist mescaline. The results suggested a role for PDE9A in the regulation of monoaminergic circuitry associated with sensory processing and memory. Thus, PDE9A activity regulates neuronal cGMP signaling downstream of multiple neurotransmitter systems, and inhibition of PDE9A may provide therapeutic benefits in psychiatric and neurodegenerative diseases promoted by the dysfunction of these diverse neurotransmitter systems.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Type III Neuregulin-1 is required for normal sensorimotor gating, memory related behaviors and cortico-striatal circuit components

PubMed Central

Chen, Ying-Jiun J.; Johnson, Madeleine A.; Lieberman, Michael D.; Goodchild, Rose E.; Schobel, Scott; Lewandowski, Nicole; Rosoklija, Gorazd; Liu, Ruei-Che; Gingrich, Jay A.; Small, Scott; Moore, Holly; Dwork, Andrew J.; Talmage, David A.; Role, Lorna W.

2008-01-01

Neuregulin-1 (Nrg1)/erbB signaling regulates neuronal development, migration, myelination, and synaptic maintenance. The Nrg1 gene is a schizophrenia susceptibility gene. To understand the contribution of Nrg1 signaling to adult brain structure and behaviors, we have studied the regulation of Type III Nrg1 expression and evaluated the effect of decreased expression of the Type III Nrg1 isoforms. Type III Nrg1 is transcribed by a promoter distinct from those for other Nrg1 isoforms and, in the adult brain, is expressed in the medial prefrontal cortex, ventral hippocampus and ventral subiculum, regions involved in the regulation of sensorimotor gating and short term memory. Adult heterozygous mutant mice with a targeted disruption for Type III Nrg1 (Nrg1tm1.1Lwr+/-) have enlarged lateral ventricles and decreased dendritic spine density on subicular pyramidal neurons. MRI imaging of Type III Nrg1 heterozygous mice revealed hypo-function in the medial prefrontal cortex and the hippocampal CA1 and subiculum regions. Type III Nrg1 heterozygous mice also have impaired performance on delayed alternation memory tasks, and deficits in prepulse inhibition (PPI). Chronic nicotine treatment eliminated differences in PPI between Type III Nrg1 heterozygous mice and their wild type littermates. Our findings demonstrate a role of Type III Nrg1-signaling in the maintenance of cortico-striatal components, and in the neural circuits involved in sensorimotor gating and short term memory. PMID:18596162

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

A 100 Mfps image sensor for biological applications

NASA Astrophysics Data System (ADS)

Etoh, T. Goji; Shimonomura, Kazuhiro; Nguyen, Anh Quang; Takehara, Kosei; Kamakura, Yoshinari; Goetschalckx, Paul; Haspeslagh, Luc; De Moor, Piet; Dao, Vu Truong Son; Nguyen, Hoang Dung; Hayashi, Naoki; Mitsui, Yo; Inumaru, Hideo

2018-02-01

Two ultrahigh-speed CCD image sensors with different characteristics were fabricated for applications to advanced scientific measurement apparatuses. The sensors are BSI MCG (Backside-illuminated Multi-Collection-Gate) image sensors with multiple collection gates around the center of the front side of each pixel, placed like petals of a flower. One has five collection gates and one drain gate at the center, which can capture consecutive five frames at 100 Mfps with the pixel count of about 600 kpixels (512 x 576 x 2 pixels). In-pixel signal accumulation is possible for repetitive image capture of reproducible events. The target application is FLIM. The other is equipped with four collection gates each connected to an in-situ CCD memory with 305 elements, which enables capture of 1,220 (4 x 305) consecutive images at 50 Mfps. The CCD memory is folded and looped with the first element connected to the last element, which also makes possible the in-pixel signal accumulation. The sensor is a small test sensor with 32 x 32 pixels. The target applications are imaging TOF MS, pulse neutron tomography and dynamic PSP. The paper also briefly explains an expression of the temporal resolution of silicon image sensors theoretically derived by the authors in 2017. It is shown that the image sensor designed based on the theoretical analysis achieves imaging of consecutive frames at the frame interval of 50 ps.

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

PubMed

Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

2015-10-07

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A neural mechanism for background information-gated learning based on axonal-dendritic overlaps.

PubMed

Mainetti, Matteo; Ascoli, Giorgio A

2015-03-01

Experiencing certain events triggers the acquisition of new memories. Although necessary, however, actual experience is not sufficient for memory formation. One-trial learning is also gated by knowledge of appropriate background information to make sense of the experienced occurrence. Strong neurobiological evidence suggests that long-term memory storage involves formation of new synapses. On the short time scale, this form of structural plasticity requires that the axon of the pre-synaptic neuron be physically proximal to the dendrite of the post-synaptic neuron. We surmise that such "axonal-dendritic overlap" (ADO) constitutes the neural correlate of background information-gated (BIG) learning. The hypothesis is based on a fundamental neuroanatomical constraint: an axon must pass close to the dendrites that are near other neurons it contacts. The topographic organization of the mammalian cortex ensures that nearby neurons encode related information. Using neural network simulations, we demonstrate that ADO is a suitable mechanism for BIG learning. We model knowledge as associations between terms, concepts or indivisible units of thought via directed graphs. The simplest instantiation encodes each concept by single neurons. Results are then generalized to cell assemblies. The proposed mechanism results in learning real associations better than spurious co-occurrences, providing definitive cognitive advantages.

A Neural Mechanism for Background Information-Gated Learning Based on Axonal-Dendritic Overlaps

PubMed Central

Mainetti, Matteo; Ascoli, Giorgio A.

2015-01-01

Experiencing certain events triggers the acquisition of new memories. Although necessary, however, actual experience is not sufficient for memory formation. One-trial learning is also gated by knowledge of appropriate background information to make sense of the experienced occurrence. Strong neurobiological evidence suggests that long-term memory storage involves formation of new synapses. On the short time scale, this form of structural plasticity requires that the axon of the pre-synaptic neuron be physically proximal to the dendrite of the post-synaptic neuron. We surmise that such “axonal-dendritic overlap” (ADO) constitutes the neural correlate of background information-gated (BIG) learning. The hypothesis is based on a fundamental neuroanatomical constraint: an axon must pass close to the dendrites that are near other neurons it contacts. The topographic organization of the mammalian cortex ensures that nearby neurons encode related information. Using neural network simulations, we demonstrate that ADO is a suitable mechanism for BIG learning. We model knowledge as associations between terms, concepts or indivisible units of thought via directed graphs. The simplest instantiation encodes each concept by single neurons. Results are then generalized to cell assemblies. The proposed mechanism results in learning real associations better than spurious co-occurrences, providing definitive cognitive advantages. PMID:25767887

The flash memory battle: How low can we go?

NASA Astrophysics Data System (ADS)

van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

2008-03-01

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Design and construction of a double inversion recombination switch for heritable sequential genetic memory.

PubMed

Ham, Timothy S; Lee, Sung K; Keasling, Jay D; Arkin, Adam P

2008-07-30

Inversion recombination elements present unique opportunities for computing and information encoding in biological systems. They provide distinct binary states that are encoded into the DNA sequence itself, allowing us to overcome limitations posed by other biological memory or logic gate systems. Further, it is in theory possible to create complex sequential logics by careful positioning of recombinase recognition sites in the sequence. In this work, we describe the design and synthesis of an inversion switch using the fim and hin inversion recombination systems to create a heritable sequential memory switch. We have integrated the two inversion systems in an overlapping manner, creating a switch that can have multiple states. The switch is capable of transitioning from state to state in a manner analogous to a finite state machine, while encoding the state information into DNA. This switch does not require protein expression to maintain its state, and "remembers" its state even upon cell death. We were able to demonstrate transition into three out of the five possible states showing the feasibility of such a switch. We demonstrate that a heritable memory system that encodes its state into DNA is possible, and that inversion recombination system could be a starting point for more complex memory circuits. Although the circuit did not fully behave as expected, we showed that a multi-state, temporal memory is achievable.

Design and Construction of a Double Inversion Recombination Switch for Heritable Sequential Genetic Memory

PubMed Central

Ham, Timothy S.; Lee, Sung K.; Keasling, Jay D.; Arkin, Adam P.

2008-01-01

Background Inversion recombination elements present unique opportunities for computing and information encoding in biological systems. They provide distinct binary states that are encoded into the DNA sequence itself, allowing us to overcome limitations posed by other biological memory or logic gate systems. Further, it is in theory possible to create complex sequential logics by careful positioning of recombinase recognition sites in the sequence. Methodology/Principal Findings In this work, we describe the design and synthesis of an inversion switch using the fim and hin inversion recombination systems to create a heritable sequential memory switch. We have integrated the two inversion systems in an overlapping manner, creating a switch that can have multiple states. The switch is capable of transitioning from state to state in a manner analogous to a finite state machine, while encoding the state information into DNA. This switch does not require protein expression to maintain its state, and “remembers” its state even upon cell death. We were able to demonstrate transition into three out of the five possible states showing the feasibility of such a switch. Conclusions/Significance We demonstrate that a heritable memory system that encodes its state into DNA is possible, and that inversion recombination system could be a starting point for more complex memory circuits. Although the circuit did not fully behave as expected, we showed that a multi-state, temporal memory is achievable. PMID:18665232

Improved charge trapping properties by embedded graphene oxide quantum-dots for flash memory application

NASA Astrophysics Data System (ADS)

Jia, Xinlei; Yan, Xiaobing; Wang, Hong; Yang, Tao; Zhou, Zhenyu; Zhao, Jianhui

2018-06-01

In this work, we have investigated two kinds of charge trapping memory devices with Pd/Al2O3/ZnO/SiO2/p-Si and Pd/Al2O3/ZnO/graphene oxide quantum-dots (GOQDs)/ZnO/SiO2/p-Si structure. Compared with the single ZnO sample, the memory window of the ZnO-GOQDs-ZnO sample reaches a larger value (more than doubled) of 2.7 V under the sweeping gate voltage ± 7 V, indicating a better charge storage capability and the significant charge trapping effects by embedding the GOQDs trapping layer. The ZnO-GOQDs-ZnO devices have better date retention properties with the high and low capacitances loss of ˜ 1.1 and ˜ 6.9%, respectively, as well as planar density of the trapped charges of 1.48 × 1012 cm- 2. It is proposed that the GOQDs play an important role in the outstanding memory characteristics due to the deep quantum potential wells and the discrete distribution of the GOQDs. The long date retention time might have resulted from the high potential barrier which suppressed both the back tunneling and the leakage current. Intercalating GOQDs in the memory device is a promising method to realize large memory window, low-power consumption and excellent retention properties.

Factor Structure and Heritability of Endophenotypes in Schizophrenia: Findings from the Consortium on the Genetics of Schizophrenia (COGS-1)

PubMed Central

Seidman, Larry J.; Hellemann, Gerhard; Nuechterlein, Keith H.; Greenwood, Tiffany A.; Braff, David L.; Cadenhead, Kristin S.; Calkins, Monica E.; Freedman, Robert; Gur, Raquel E.; Gur, Ruben C.; Lazzeroni, Laura C.; Light, Gregory A.; Olincy, Ann; Radant, Allen D.; Siever, Larry J.; Silverman, Jeremy M.; Sprock, Joyce; Stone, William S.; Sugar, Catherine; Swerdlow, Neal R.; Tsuang, Debby W.; Tsuang, Ming T.; Turetsky, Bruce I.; Green, Michael F.

2018-01-01

Background Although many endophenotypes for schizophrenia have been studied individually, few studies have examined the extent to which common neurocognitive and neurophysiological measures reflect shared versus unique endophenotypic factors. It may be possible to distill individual endophenotypes into composite measures that reflect dissociable, genetically informative elements. Methods The first phase of the Consortium on the Genetics of Schizophrenia (COGS-1) is a multisite family study that collected neurocognitive and neurophysiological data between 2003–2008. For these analyses, participants included schizophrenia probands (n=83), their nonpsychotic siblings (n=151), and community comparison subjects (n=209) with complete data on a battery of 12 neurocognitive tests (assessing domains of working memory, declarative memory, vigilance, spatial ability, abstract reasoning, facial emotion processing, and motor speed) and 3 neurophysiological tasks reflecting inhibitory processing (P50 gating, prepulse inhibition and antisaccade tasks). Factor analyses were conducted on the measures for each subject group and across the entire sample. Heritability analyses of factors were performed using SOLAR. Results Analyses yielded 5 distinct factors: 1) Episodic Memory, 2) Working Memory, 3) Perceptual Vigilance, 4) Visual Abstraction, and 5) Inhibitory Processing. Neurophysiological measures had low associations with these factors. The factor structure of endophenotypes was largely comparable across probands, siblings and controls. Significant heritability estimates for the factors ranged from 22% (Episodic Memory) to 39% (Visual Abstraction). Conclusions Neurocognitive measures reflect a meaningful amount of shared variance whereas the neurophysiological measures reflect largely unique contributions as endophenotypes for schizophrenia. Composite endophenotype measures may inform our neurobiological and genetic understanding of schizophrenia. PMID:25682549

Factor structure and heritability of endophenotypes in schizophrenia: findings from the Consortium on the Genetics of Schizophrenia (COGS-1).

PubMed

Seidman, Larry J; Hellemann, Gerhard; Nuechterlein, Keith H; Greenwood, Tiffany A; Braff, David L; Cadenhead, Kristin S; Calkins, Monica E; Freedman, Robert; Gur, Raquel E; Gur, Ruben C; Lazzeroni, Laura C; Light, Gregory A; Olincy, Ann; Radant, Allen D; Siever, Larry J; Silverman, Jeremy M; Sprock, Joyce; Stone, William S; Sugar, Catherine; Swerdlow, Neal R; Tsuang, Debby W; Tsuang, Ming T; Turetsky, Bruce I; Green, Michael F

2015-04-01

Although many endophenotypes for schizophrenia have been studied individually, few studies have examined the extent to which common neurocognitive and neurophysiological measures reflect shared versus unique endophenotypic factors. It may be possible to distill individual endophenotypes into composite measures that reflect dissociable, genetically informative elements. The first phase of the Consortium on the Genetics of Schizophrenia (COGS-1) is a multisite family study that collected neurocognitive and neurophysiological data between 2003 and 2008. For these analyses, participants included schizophrenia probands (n=83), their nonpsychotic siblings (n=151), and community comparison subjects (n=209) with complete data on a battery of 12 neurocognitive tests (assessing domains of working memory, declarative memory, vigilance, spatial ability, abstract reasoning, facial emotion processing, and motor speed) and 3 neurophysiological tasks reflecting inhibitory processing (P50 gating, prepulse inhibition and antisaccade tasks). Factor analyses were conducted on the measures for each subject group and across the entire sample. Heritability analyses of factors were performed using SOLAR. Analyses yielded 5 distinct factors: 1) Episodic Memory, 2) Working Memory, 3) Perceptual Vigilance, 4) Visual Abstraction, and 5) Inhibitory Processing. Neurophysiological measures had low associations with these factors. The factor structure of endophenotypes was largely comparable across probands, siblings and controls. Significant heritability estimates for the factors ranged from 22% (Episodic Memory) to 39% (Visual Abstraction). Neurocognitive measures reflect a meaningful amount of shared variance whereas the neurophysiological measures reflect largely unique contributions as endophenotypes for schizophrenia. Composite endophenotype measures may inform our neurobiological and genetic understanding of schizophrenia. Copyright © 2015 Elsevier B.V. All rights reserved.

Benefits of flexible prioritization in working memory can arise without costs.

PubMed

Myers, Nicholas E; Chekroud, Sammi R; Stokes, Mark G; Nobre, Anna C

2018-03-01

Most recent models conceptualize working memory (WM) as a continuous resource, divided up according to task demands. When an increasing number of items need to be remembered, each item receives a smaller chunk of the memory resource. These models predict that the allocation of attention to high-priority WM items during the retention interval should be a zero-sum game: improvements in remembering cued items come at the expense of uncued items because resources are dynamically transferred from uncued to cued representations. The current study provides empirical data challenging this model. Four precision retrocueing WM experiments assessed cued and uncued items on every trial. This permitted a test for trade-off of the memory resource. We found no evidence for trade-offs in memory across trials. Moreover, robust improvements in WM performance for cued items came at little or no cost to uncued items that were probed afterward, thereby increasing the net capacity of WM relative to neutral cueing conditions. An alternative mechanism of prioritization proposes that cued items are transferred into a privileged state within a response-gating bottleneck, in which an item uniquely controls upcoming behavior. We found evidence consistent with this alternative. When an uncued item was probed first, report of its orientation was biased away from the cued orientation to be subsequently reported. We interpret this bias as competition for behavioral control in the output-driving bottleneck. Other items in WM did not bias each other, making this result difficult to explain with a shared resource model. (PsycINFO Database Record (c) 2018 APA, all rights reserved).

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Light-induced negative differential resistance in gate-controlled graphene-silicon photodiode

NASA Astrophysics Data System (ADS)

Liu, Wei; Guo, Hongwei; Li, Wei; Wan, Xia; Bodepudi, Srikrishna Chanakya; Shehzad, Khurram; Xu, Yang

2018-05-01

In this letter, we investigated light-induced negative differential resistance (L-NDR) effects in a hybrid photodiode formed by a graphene-silicon (GS) junction and a neighboring graphene-oxide-Si (GOS) capacitor. We observed two distinct L-NDR effects originating from the gate-dependent surface recombination and the potential-well-induced confinement of photo-carriers in the GOS region. We verified this by studying the gate-controlled GS diode, which can distinguish the photocurrent from the GS region with that from the GOS region (gate). A large peak-to-valley ratio of up to 12.1 has been obtained for the L-NDR due to gate-dependent surface recombination. Such strong L-NDR effect provides an opportunity to further engineer the optoelectronic properties of GS junctions along with exploring its potential applications in photodetectors, photo-memories, and position sensitive devices.

Error correction in short time steps during the application of quantum gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castro, L.A. de, E-mail: leonardo.castro@usp.br; Napolitano, R.D.J.

2016-04-15

We propose a modification of the standard quantum error-correction method to enable the correction of errors that occur due to the interaction with a noisy environment during quantum gates without modifying the codification used for memory qubits. Using a perturbation treatment of the noise that allows us to separate it from the ideal evolution of the quantum gate, we demonstrate that in certain cases it is necessary to divide the logical operation in short time steps intercalated by correction procedures. A prescription of how these gates can be constructed is provided, as well as a proof that, even for themore » cases when the division of the quantum gate in short time steps is not necessary, this method may be advantageous for reducing the total duration of the computation.« less

All-optical 10Gb/s ternary-CAM cell for routing look-up table applications.

PubMed

Mourgias-Alexandris, George; Vagionas, Christos; Tsakyridis, Apostolos; Maniotis, Pavlos; Pleros, Nikos

2018-03-19

We experimentally demonstrate the first all-optical Ternary-Content Addressable Memory (T-CAM) cell that operates at 10Gb/s and comprises two monolithically integrated InP Flip-Flops (FF) and a SOA-MZI optical XOR gate. The two FFs are responsible for storing the data bit and the ternary state 'X', respectively, with the XOR gate used for comparing the stored FF-data and the search bit. The experimental results reveal error-free operation at 10Gb/s for both Write and Ternary Content Addressing of the T-CAM cell, indicating that the proposed optical T-CAM cell could in principle lead to all-optical T-CAM-based Address Look-up memory architectures for high-end routing applications.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

A SONOS device with a separated charge trapping layer for improvement of charge injection

NASA Astrophysics Data System (ADS)

Ahn, Jae-Hyuk; Moon, Dong-Il; Ko, Seung-Won; Kim, Chang-Hoon; Kim, Jee-Yeon; Kim, Moon-Seok; Seol, Myeong-Lok; Moon, Joon-Bae; Choi, Ji-Min; Oh, Jae-Sub; Choi, Sung-Jin; Choi, Yang-Kyu

2017-03-01

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.

Quantum memory and gates using a Λ -type quantum emitter coupled to a chiral waveguide

NASA Astrophysics Data System (ADS)

Li, Tao; Miranowicz, Adam; Hu, Xuedong; Xia, Keyu; Nori, Franco

2018-06-01

By coupling a Λ -type quantum emitter to a chiral waveguide, in which the polarization of a photon is locked to its propagation direction, we propose a controllable photon-emitter interface for quantum networks. We show that this chiral system enables the swap gate and a hybrid-entangling gate between the emitter and a flying single photon. It also allows deterministic storage and retrieval of single-photon states with high fidelities and efficiencies. In short, this chirally coupled emitter-photon interface can be a critical building block toward a large-scale quantum network.

Protected quantum computing: interleaving gate operations with dynamical decoupling sequences.

PubMed

Zhang, Jingfu; Souza, Alexandre M; Brandao, Frederico Dias; Suter, Dieter

2014-02-07

Implementing precise operations on quantum systems is one of the biggest challenges for building quantum devices in a noisy environment. Dynamical decoupling attenuates the destructive effect of the environmental noise, but so far, it has been used primarily in the context of quantum memories. Here, we experimentally demonstrate a general scheme for combining dynamical decoupling with quantum logical gate operations using the example of an electron-spin qubit of a single nitrogen-vacancy center in diamond. We achieve process fidelities >98% for gate times that are 2 orders of magnitude longer than the unprotected dephasing time T2.

MHC Class I Immune Proteins Are Critical for Hippocampus-Dependent Memory and Gate NMDAR-Dependent Hippocampal Long-Term Depression

ERIC Educational Resources Information Center

Nelson, P. Austin; Sage, Jennifer R.; Wood, Suzanne C.; Davenport, Christopher M.; Anagnostaras, Stephan G.; Boulanger, Lisa M.

2013-01-01

Memory impairment is a common feature of conditions that involve changes in inflammatory signaling in the brain, including traumatic brain injury, infection, neurodegenerative disorders, and normal aging. However, the causal importance of inflammatory mediators in cognitive impairments in these conditions remains unclear. Here we show that…

A richness that cures.

PubMed

Pizzorusso, Tommaso; Berardi, Nicoletta; Maffei, Lamberto

2007-05-24

A study in Nature by Fischer et al. shows that environmental enrichment or increasing histone acetylation rescue the ability to form new memories and re-establish access to remote memories even in the presence of brain degeneration. Chromatin remodeling may be the final gate environmental enrichment opens to enhance plasticity and represents a promising target for therapeutical intervention in neurodegenerative diseases.

Repeat-until-success cubic phase gate for universal continuous-variable quantum computation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marshall, Kevin; Pooser, Raphael; Siopsis, George

2015-03-24

We report that to achieve universal quantum computation using continuous variables, one needs to jump out of the set of Gaussian operations and have a non-Gaussian element, such as the cubic phase gate. However, such a gate is currently very difficult to implement in practice. Here we introduce an experimentally viable “repeat-until-success” approach to generating the cubic phase gate, which is achieved using sequential photon subtractions and Gaussian operations. Ultimately, we find that our scheme offers benefits in terms of the expected time until success, as well as the fact that we do not require any complex off-line resource state,more » although we require a primitive quantum memory.« less

A model of individualized canonical microcircuits supporting cognitive operations

PubMed Central

Peterson, Andre D. H.; Haueisen, Jens; Knösche, Thomas R.

2017-01-01

Major cognitive functions such as language, memory, and decision-making are thought to rely on distributed networks of a large number of basic elements, called canonical microcircuits. In this theoretical study we propose a novel canonical microcircuit model and find that it supports two basic computational operations: a gating mechanism and working memory. By means of bifurcation analysis we systematically investigate the dynamical behavior of the canonical microcircuit with respect to parameters that govern the local network balance, that is, the relationship between excitation and inhibition, and key intrinsic feedback architectures of canonical microcircuits. We relate the local behavior of the canonical microcircuit to cognitive processing and demonstrate how a network of interacting canonical microcircuits enables the establishment of spatiotemporal sequences in the context of syntax parsing during sentence comprehension. This study provides a framework for using individualized canonical microcircuits for the construction of biologically realistic networks supporting cognitive operations. PMID:29200435

Coherent all-optical control of ultracold atoms arrays in permanent magnetic traps.

PubMed

Abdelrahman, Ahmed; Mukai, Tetsuya; Häffner, Hartmut; Byrnes, Tim

2014-02-10

We propose a hybrid architecture for quantum information processing based on magnetically trapped ultracold atoms coupled via optical fields. The ultracold atoms, which can be either Bose-Einstein condensates or ensembles, are trapped in permanent magnetic traps and are placed in microcavities, connected by silica based waveguides on an atom chip structure. At each trapping center, the ultracold atoms form spin coherent states, serving as a quantum memory. An all-optical scheme is used to initialize, measure and perform a universal set of quantum gates on the single and two spin-coherent states where entanglement can be generated addressably between spatially separated trapped ultracold atoms. This allows for universal quantum operations on the spin coherent state quantum memories. We give detailed derivations of the composite cavity system mediated by a silica waveguide as well as the control scheme. Estimates for the necessary experimental conditions for a working hybrid device are given.

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula J.; Torgerson, J. Leigh

2006-01-01

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Nootropic α7 nicotinic receptor allosteric modulator derived from GABAA receptor modulators

PubMed Central

Ng, Herman J.; Whittemore, Edward R.; Tran, Minhtam B.; Hogenkamp, Derk J.; Broide, Ron S.; Johnstone, Timothy B.; Zheng, Lijun; Stevens, Karen E.; Gee, Kelvin W.

2007-01-01

Activation of brain α7 nicotinic acetylcholine receptors (α7 nAChRs) has broad therapeutic potential in CNS diseases related to cognitive dysfunction, including Alzheimer's disease and schizophrenia. In contrast to direct agonist activation, positive allosteric modulation of α7 nAChRs would deliver the clinically validated benefits of allosterism to these indications. We have generated a selective α7 nAChR-positive allosteric modulator (PAM) from a library of GABAA receptor PAMs. Compound 6 (N-(4-chlorophenyl)-α-[[(4-chloro-phenyl)amino]methylene]-3-methyl-5-isoxazoleacet-amide) evokes robust positive modulation of agonist-induced currents at α7 nAChRs, while preserving the rapid native characteristics of desensitization, and has little to no efficacy at other ligand-gated ion channels. In rodent models, it corrects sensory-gating deficits and improves working memory, effects consistent with cognitive enhancement. Compound 6 represents a chemotype for allosteric activation of α7 nAChRs, with therapeutic potential in CNS diseases with cognitive dysfunction. PMID:17470817

Complete hyperentangled-Bell-state analysis for photonic qubits assisted by a three-level Λ-type system

NASA Astrophysics Data System (ADS)

Wang, Tie-Jun; Wang, Chuan

2016-01-01

Hyperentangled Bell-state analysis (HBSA) is an essential method in high-capacity quantum communication and quantum information processing. Here by replacing the two-qubit controlled-phase gate with the two-qubit SWAP gate, we propose a scheme to distinguish the 16 hyperentangled Bell states completely in both the polarization and the spatial-mode degrees of freedom (DOFs) of two-photon systems. The proposed scheme reduces the use of two-qubit interaction which is fragile and cumbersome, and only one auxiliary particle is required. Meanwhile, it reduces the requirement for initializing the auxiliary particle which works as a temporary quantum memory, and does not have to be actively controlled or measured. Moreover, the state of the auxiliary particle remains unchanged after the HBSA operation, and within the coherence time, the auxiliary particle can be repeatedly used in the next HBSA operation. Therefore, the engineering complexity of our HBSA operation is greatly simplified. Finally, we discuss the feasibility of our scheme with current technologies.

Efficient Graph Based Assembly of Short-Read Sequences on Hybrid Core Architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sczyrba, Alex; Pratap, Abhishek; Canon, Shane

2011-03-22

Advanced architectures can deliver dramatically increased throughput for genomics and proteomics applications, reducing time-to-completion in some cases from days to minutes. One such architecture, hybrid-core computing, marries a traditional x86 environment with a reconfigurable coprocessor, based on field programmable gate array (FPGA) technology. In addition to higher throughput, increased performance can fundamentally improve research quality by allowing more accurate, previously impractical approaches. We will discuss the approach used by Convey?s de Bruijn graph constructor for short-read, de-novo assembly. Bioinformatics applications that have random access patterns to large memory spaces, such as graph-based algorithms, experience memory performance limitations on cache-based x86more » servers. Convey?s highly parallel memory subsystem allows application-specific logic to simultaneously access 8192 individual words in memory, significantly increasing effective memory bandwidth over cache-based memory systems. Many algorithms, such as Velvet and other de Bruijn graph based, short-read, de-novo assemblers, can greatly benefit from this type of memory architecture. Furthermore, small data type operations (four nucleotides can be represented in two bits) make more efficient use of logic gates than the data types dictated by conventional programming models.JGI is comparing the performance of Convey?s graph constructor and Velvet on both synthetic and real data. We will present preliminary results on memory usage and run time metrics for various data sets with different sizes, from small microbial and fungal genomes to very large cow rumen metagenome. For genomes with references we will also present assembly quality comparisons between the two assemblers.« less

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

NASA Astrophysics Data System (ADS)

Verma, Madhulika; Sharma, Dheeraj; Pandey, Sunil; Nigam, Kaushal; Kondekar, P. N.

2017-01-01

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM 1 and ϕM 2 are used in short-gate DMTFET, where ϕM 1 represents the work-function of gate M1 near to the drain end, while ϕM 2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

NASA Astrophysics Data System (ADS)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Field Programmable Gate Array Apparatus, Method, and Computer Program

NASA Technical Reports Server (NTRS)

Morfopoulos, Arin C. (Inventor); Pham, Thang D. (Inventor)

2014-01-01

An apparatus is provided that includes a plurality of modules, a plurality of memory banks, and a multiplexor. Each module includes at least one agent that interfaces between a module and a memory bank. Each memory bank includes an arbiter that interfaces between the at least one agent of each module and the memory bank. The multiplexor is configured to assign data paths between the at least one agent of each module and a corresponding arbiter of each memory bank based on the assigned data path. The at least one agent of each module is configured to read data from the corresponding arbiter of the memory bank or write modified data to the corresponding arbiter of the memory bank.

Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures

NASA Astrophysics Data System (ADS)

Fitsios, D.; Alexoudi, T.; Vagionas, C.; Miliou, A.; Kanellos, G. T.; Pleros, N.

2013-03-01

Optical RAM has emerged as a promising solution for overcoming the "Memory Wall" of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Thermally activated hysteresis in high quality graphene/h-BN devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cadore, A. R., E-mail: alissoncadore@gmail.com, E-mail: lccampos@fisica.ufmg.br; Mania, E.; Lacerda, R. G.

2016-06-06

We report on gate hysteresis of resistance in high quality graphene/hexagonal boron nitride (h-BN) devices. We observe a thermally activated hysteretic behavior in resistance as a function of the applied gate voltage at temperatures above 375 K. In order to investigate the origin of the hysteretic phenomenon, we compare graphene/h-BN heterostructure devices with SiO{sub 2}/Si back gate electrodes to devices with graphite back gate electrodes. The gate hysteretic behavior of the resistance is present only in devices with an h-BN/SiO{sub 2} interface and is dependent on the orientation of the applied gate electric field and sweep rate. We describe a phenomenologicalmore » model which captures all of our findings based on charges trapped at the h-BN/SiO{sub 2} interface. Such hysteretic behavior in graphene resistance must be considered in high temperature applications for graphene devices and may open new routes for applications in digital electronics and memory devices.« less

Synthesizing Biomolecule-based Boolean Logic Gates

PubMed Central

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2012-01-01

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

Synthesizing biomolecule-based Boolean logic gates.

PubMed

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2013-02-15

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

NASA Astrophysics Data System (ADS)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Virtex-5QV Self Scrubber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojahn, Christopher K.

2015-10-20

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

The Calmodulin-Binding Transcription Activator CAMTA1 Is Required for Long-Term Memory Formation in Mice

ERIC Educational Resources Information Center

Bas-Orth, Carlos; Tan, Yan-Wei; Oliveira, Ana M. M.; Bengtson, C. Peter; Bading, Hilmar

2016-01-01

The formation of long-term memory requires signaling from the synapse to the nucleus to mediate neuronal activity-dependent gene transcription. Synapse-to-nucleus communication is initiated by influx of calcium ions through synaptic NMDA receptors and/or L-type voltage-gated calcium channels and involves the activation of transcription factors by…

Transient Hippocampal Down-Regulation of Kv1.1 Subunit mRNA during Associative Learning in Rats

ERIC Educational Resources Information Center

Kourrich, Said; Manrique, Christine; Salin, Pascal; Mourre, Christiane

2005-01-01

Voltage-gated potassium channels (Kv) are critically involved in learning and memory processes. It is not known, however, whether the expression of the Kv1.1 subunit, constituting Kv1 channels, can be specifically regulated in brain areas important for learning and memory processing. Radioactive in situ hybridization was used to evaluate the…

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Spin-based single-photon transistor, dynamic random access memory, diodes, and routers in semiconductors

NASA Astrophysics Data System (ADS)

Hu, C. Y.

2016-12-01

The realization of quantum computers and quantum Internet requires not only quantum gates and quantum memories, but also transistors at single-photon levels to control the flow of information encoded on single photons. Single-photon transistor (SPT) is an optical transistor in the quantum limit, which uses a single photon to open or block a photonic channel. In sharp contrast to all previous SPT proposals which are based on single-photon nonlinearities, here I present a design for a high-gain and high-speed (up to THz) SPT based on a linear optical effect: giant circular birefringence induced by a single spin in a double-sided optical microcavity. A gate photon sets the spin state via projective measurement and controls the light propagation in the optical channel. This spin-cavity transistor can be directly configured as diodes, routers, DRAM units, switches, modulators, etc. Due to the duality as quantum gate and transistor, the spin-cavity unit provides a solid-state platform ideal for future Internet: a mixture of all-optical Internet with quantum Internet.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

A neural mechanism of dynamic gating of task-relevant information by top-down influence in primary visual cortex.

PubMed

Kamiyama, Akikazu; Fujita, Kazuhisa; Kashimori, Yoshiki

2016-12-01

Visual recognition involves bidirectional information flow, which consists of bottom-up information coding from retina and top-down information coding from higher visual areas. Recent studies have demonstrated the involvement of early visual areas such as primary visual area (V1) in recognition and memory formation. V1 neurons are not passive transformers of sensory inputs but work as adaptive processor, changing their function according to behavioral context. Top-down signals affect tuning property of V1 neurons and contribute to the gating of sensory information relevant to behavior. However, little is known about the neuronal mechanism underlying the gating of task-relevant information in V1. To address this issue, we focus on task-dependent tuning modulations of V1 neurons in two tasks of perceptual learning. We develop a model of the V1, which receives feedforward input from lateral geniculate nucleus and top-down input from a higher visual area. We show here that the change in a balance between excitation and inhibition in V1 connectivity is necessary for gating task-relevant information in V1. The balance change well accounts for the modulations of tuning characteristic and temporal properties of V1 neuronal responses. We also show that the balance change of V1 connectivity is shaped by top-down signals with temporal correlations reflecting the perceptual strategies of the two tasks. We propose a learning mechanism by which synaptic balance is modulated. To conclude, top-down signal changes the synaptic balance between excitation and inhibition in V1 connectivity, enabling early visual area such as V1 to gate context-dependent information under multiple task performances. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Magneto-Ionic Control of Interfacial Magnetic Anisotorpy

NASA Astrophysics Data System (ADS)

Bauer, Uwe; Emori, Satoru; Beach, Geoffrey

2014-03-01

Voltage control of magnetism could bring about revolutionary new spintronic memory and logic devices. Here, we examine domain wall (DW) dynamics in ultrathin Co films and nanowires under the influence of a voltage applied across a gadolinium oxide gate dielectric that simultaneously acts as an oxygen ion conductor. We investigate two electrode configurations, one with a continuous gate dielectric and the other with a patterned gate dielectric which exhibits an open oxide edge right underneath the electrode perimeter. We demonstrate that the open oxide edge acts as a fast diffusion path for oxygen ions and allows voltage-induced switching of magnetic anisotropy at the nanoscale by modulating interfacial chemistry rather than charge density. At room temperature this effect is limited to the vicinity of the open oxide edge, but at a temperature of 100°C it allows complete control over magnetic anisotropy across the whole electrode area, due to higher oxygen ion mobility at elevated temperature. We then harness this novel ``magneto-ionic'' effect to create unprecedentedly strong voltage-induced anisotropy modifications of 3000 fJ/Vm and create electrically programmable DW traps with pinning strengths of 650 Oe, enough to bring to a standstill DWs travelling at speeds of at least 20 m/s. This work is supported by the National Science Foundation through grant ECCS-1128439.

Design, processing, and testing of LSI arrays for space station

NASA Technical Reports Server (NTRS)

Schneider, W. C.

1974-01-01

At wafer probe, units of the TA6567 circuit, a beam leaded COS/MOS/SOS 256-bit RAM, were demonstrated to be functionally perfect. An aluminum gate current-sense version and a silicon-gate voltage-sense version of this memory were developed. Initial base line data for the beam lead SOS process using the TA5388 circuit show the stability of the dc device characteristics through the beam lead processing.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Memory and executive functions in persons with type 2 diabetes: a meta-analysis.

PubMed

Sadanand, Shilpa; Balachandar, Rakesh; Bharath, Srikala

2016-02-01

Literature suggests that persons with type 2 diabetes mellitus (T2DM) are at risk for cognitive impairment, hence dementia. Common domains reported to be affected in those with T2DM are memory and executive functions. The extent of influence of T2DM on these domains has varied among studies. A systematic review and meta-analysis was carried out to understand whether sub-domains contributed to the variations observed in published research. We searched 'PubMed', 'ScienceDirect', 'SciVerseHub', 'Psychinfo', 'Proquest' 'Ebsco' and 'J-gate Plus' databases for published studies on cognition and T2DM among persons aged 50 years and older. Memory, executive functions and processing speed domain and sub-domain scores were extracted; effect sizes (Cohen's d) were calculated and analysed. Eight hundred seventeen articles were found. After various levels of filtering, 15 articles met the inclusion criteria for quantitative analyses. The analyses indicated that in comparison to controls, persons with T2DM showed decrements in episodic memory (d = -0.51), logical memory (d = -0.24), sub-domain of executive functions which included phonemic fluency (d = -0.35) and cognitive flexibility (d = 0.52), and speed of processing (d = -0.22). We found no difference in the sub-domains of verbal short-term memory and working memory. The meta-analysis revealed a detrimental effect of T2DM on cognitive sub-domains, namely, episodic memory and cognitive flexibility. There was a trend for the logical memory, phonemic fluency and processing speed to be affected. The analysis indicates that T2DM is a detrimental factor on certain cognitive sub-domains, rendering the person vulnerable to subsequent dementia. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2015 John Wiley & Sons, Ltd.

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

DOEpatents

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Chip architecture - A revolution brewing

NASA Astrophysics Data System (ADS)

Guterl, F.

1983-07-01

Techniques being explored by microchip designers and manufacturers to both speed up memory access and instruction execution while protecting memory are discussed. Attention is given to hardwiring control logic, pipelining for parallel processing, devising orthogonal instruction sets for interchangeable instruction fields, and the development of hardware for implementation of virtual memory and multiuser systems to provide memory management and protection. The inclusion of microcode in mainframes eliminated logic circuits that control timing and gating of the CPU. However, improvements in memory architecture have reduced access time to below that needed for instruction execution. Hardwiring the functions as a virtual memory enhances memory protection. Parallelism involves a redundant architecture, which allows identical operations to be performed simultaneously, and can be directed with microcode to avoid abortion of intermediate instructions once on set of instructions has been completed.

Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2012-01-01

Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gatemore » bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.« less

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

NASA Astrophysics Data System (ADS)

Khan, J.; Lingalugari, M.; Al-Amoody, F.; Jain, F.

2013-11-01

As conventional memories approach scaling limitations, new storage methods must be utilized to increase Si yield and produce higher on-chip memory density. Use of II-VI Zn0.56Cd0.44Se quantum dots (QDs) is compatible with epitaxial gate insulators such as ZnS-ZnMgS. Voltage-dependent charging effects in cladded Zn0.56Cd0.44Se QDs are presented in a conventional metal-oxide-semiconductor capacitor structure. Charge storage capabilities in Si and ZnMgS QDs have been reported by various researchers; this work is focused on II-VI material Zn0.56Cd0.44Se QDs nucleated using photoassisted microwave plasma metalorganic chemical vapor deposition. Using capacitance-voltage hysteresis characterization, the multistep charging and discharging capabilities of the QDs at room temperature are presented. Three charging states are presented within a 10 V charging voltage range. These characteristics exemplify discrete charge states in the QD layer, perfect for multibit, QD-functionalized high-density memory applications. Multiple charge states with low operating voltage provide device characteristics that can be used for multibit storage by allowing varying charges to be stored in a QD layer based on the applied "write" voltage.

Leucine-Rich Glioma Inactivated-1 and Voltage-Gated Potassium Channel Autoimmune Encephalitis Associated with Ischemic Stroke: A Case Report

PubMed Central

McGinley, Marisa; Morales-Vidal, Sarkis; Ruland, Sean

2016-01-01

Autoimmune encephalitis is associated with a wide variety of antibodies and clinical presentations. Voltage-gated potassium channel (VGKC) antibodies are a cause of autoimmune non-paraneoplastic encephalitis characterized by memory impairment, psychiatric symptoms, and seizures. We present a case of VGKC encephalitis likely preceding an ischemic stroke. Reports of autoimmune encephalitis associated with ischemic stroke are rare. Several hypotheses linking these two disease processes are proposed. PMID:27242653

More than Memory Impairment in Voltage-Gated Potassium Channel Complex Encephalopathy

PubMed Central

Bettcher, Brianne M.; Gelfand, Jeffrey M.; Irani, Sarosh R.; Neuhaus, John; Forner, Sven; Hess, Christopher P.; Geschwind, Michael D.

2014-01-01

Objective Autoimmune encephalopathies (AE) are a heterogeneous group of neurological disorders that affect cognition. Although memory difficulties are commonly endorsed, few reports of AE inclusively assess all cognitive domains in detail. Our aim was to perform an unbiased cognitive evaluation of AE patients with voltage-gated potassium channel complex antibodies (VGKCC-Abs) in order to delineate cognitive strengths and weaknesses. Methods We assessed serial VGKCC-Abs AE subjects (n=12) with a comprehensive evaluation of memory, executive functions, visuospatial skills, and language. Clinical MRI (n=10/12) was evaluated. Five subjects had serial cognitive testing available, permitting descriptive analysis of change. Results Subjects demonstrated mild to moderate impairment in memory (mean Z=−1.9) and executive functions (mean Z=−1.5), with variable impairments in language and sparing of visuospatial skills. MRI findings showed T2 hyperintensities in medial temporal lobe (10/10) and basal ganglia (2/10). Serial cognitive examination revealed heterogeneity in cognitive function; whereas most patients improved in one or more domains, residual impairments were observed in some patients. Conclusions This study augments prior neuropsychological analyses in VGKCC-Ab AE by identifying not only memory and executive function deficits, but also language impairments, with preservation of visuospatial functioning. This study further highlights the importance of domain-specific testing to parse out the complex cognitive phenotypes of VGKCC-Ab AE. PMID:24981998

Causes and consequences of limitations in visual working memory.

PubMed

Fallon, Sean James; Zokaei, Nahid; Husain, Masud

2016-04-01

Recent methodological and conceptual advances have led to a fundamental reappraisal of the nature of visual working memory (WM). A large corpus of evidence now suggests that there might not be a hard limit on the number of items that can be stored. Instead, WM may be better captured by a highly limited--but flexible--resource model. More resource can be allocated to prioritized items but, crucially, at a cost of reduced recall precision for other stored items. Expectations may modulate resource distribution, for example, through neural oscillations in the alpha band increasing inhibition of irrelevant cortical regions. Our understanding of the neural architecture of WM is also undergoing radical revision. Whereas the prefrontal cortex has previously dominated research endeavors, other cortical regions, such as early visual areas, are now considered to make an essential contribution, for example holding one or more items in a privileged state or "focus of attention" within WM. By contrast, the striatum is increasingly viewed as crucial in determining why and how items are gated into memory, while the hippocampus, it has controversially been argued, might be critical in the formation of temporally resilient conjunctions across features of stored items in WM. © 2016 The Authors. Annals of the New York Academy of Sciences published by Wiley Periodicals Inc. on behalf of The New York Academy of Sciences.

Dendritic nonlinearities reduce network size requirements and mediate ON and OFF states of persistent activity in a PFC microcircuit model.

PubMed

Papoutsi, Athanasia; Sidiropoulou, Kyriaki; Poirazi, Panayiota

2014-07-01

Technological advances have unraveled the existence of small clusters of co-active neurons in the neocortex. The functional implications of these microcircuits are in large part unexplored. Using a heavily constrained biophysical model of a L5 PFC microcircuit, we recently showed that these structures act as tunable modules of persistent activity, the cellular correlate of working memory. Here, we investigate the mechanisms that underlie persistent activity emergence (ON) and termination (OFF) and search for the minimum network size required for expressing these states within physiological regimes. We show that (a) NMDA-mediated dendritic spikes gate the induction of persistent firing in the microcircuit. (b) The minimum network size required for persistent activity induction is inversely proportional to the synaptic drive of each excitatory neuron. (c) Relaxation of connectivity and synaptic delay constraints eliminates the gating effect of NMDA spikes, albeit at a cost of much larger networks. (d) Persistent activity termination by increased inhibition depends on the strength of the synaptic input and is negatively modulated by dADP. (e) Slow synaptic mechanisms and network activity contain predictive information regarding the ability of a given stimulus to turn ON and/or OFF persistent firing in the microcircuit model. Overall, this study zooms out from dendrites to cell assemblies and suggests a tight interaction between dendritic non-linearities and network properties (size/connectivity) that may facilitate the short-memory function of the PFC.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Memory and Spin Injection Devices Involving Half Metals

DOE PAGES

Shaughnessy, M.; Snow, Ryan; Damewood, L.; ...

2011-01-01

We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

Hybrid quantum processors: molecular ensembles as quantum memory for solid state circuits.

PubMed

Rabl, P; DeMille, D; Doyle, J M; Lukin, M D; Schoelkopf, R J; Zoller, P

2006-07-21

We investigate a hybrid quantum circuit where ensembles of cold polar molecules serve as long-lived quantum memories and optical interfaces for solid state quantum processors. The quantum memory realized by collective spin states (ensemble qubit) is coupled to a high-Q stripline cavity via microwave Raman processes. We show that, for convenient trap-surface distances of a few microm, strong coupling between the cavity and ensemble qubit can be achieved. We discuss basic quantum information protocols, including a swap from the cavity photon bus to the molecular quantum memory, and a deterministic two qubit gate. Finally, we investigate coherence properties of molecular ensemble quantum bits.

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Magnetoelectric domain wall dynamics and its implications for magnetoelectric memory

DOE PAGES

Belashchenko, K. D.; Tchernyshyov, O.; Kovalev, Alexey A.; ...

2016-03-30

Domain wall dynamics in a magnetoelectric antiferromagnet is analyzed, and its implications for magnetoelectric memory applications are discussed. Cr 2O 3 is used in the estimates of the materials parameters. It is found that the domain wall mobility has a maximum as a function of the electric field due to the gyrotropic coupling induced by it. In Cr 2O 3, the maximal mobility of 0.1 m/(s Oe) is reached at E≈0.06 V/nm. Fields of this order may be too weak to overcome the intrinsic depinning field, which is estimated for B-doped Cr 2O 3. These major drawbacks for device implementationmore » can be overcome by applying a small in-plane shear strain, which blocks the domain wall precession. Domain wall mobility of about 0.7 m/(s Oe) can then be achieved at E = 0.2 V/nm. Furthermore, a split-gate scheme is proposed for the domain-wall controlled bit element; its extension to multiple-gate linear arrays can offer advantages in memory density, programmability, and logic functionality.« less

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Fixed weight Hopfield Neural Network based on optical implementation of all-optical MZI-XNOR logic gate

NASA Astrophysics Data System (ADS)

Nugamesh Mutter, Kussay; Mat Jafri, Mohd Zubir; Abdul Aziz, Azlan

2010-05-01

Many researches are conducted to improve Hopfield Neural Network (HNN) performance especially for speed and memory capacity in different approaches. However, there is still a significant scope of developing HNN using Optical Logic Gates. We propose here a new model of HNN based on all-optical XNOR logic gates for real time color image recognition. Firstly, we improved HNN toward optimum learning and converging operations. We considered each unipolar image as a set of small blocks of 3-pixels as vectors for HNN. This enables to save large number of images in the net with best reaching into global minima, and because there are only eight fixed states of weights so that only single iteration performed to construct a vector with stable state at minimum energy. HNN is useless in dealing with data not in bipolar representation. Therefore, HNN failed to work with color images. In RGB bands each represents different values of brightness, for d-bit RGB image it is simply consists of d-layers of unipolar. Each layer is as a single unipolar image for HNN. In addition, the weight matrices with stability of unity at the diagonal perform clear converging in comparison with no self-connecting architecture. Synchronously, each matrix-matrix multiplication operation would run optically in the second part, since we propose an array of all-optical XOR gates, which uses Mach-Zehnder Interferometer (MZI) for neurons setup and a controlling system to distribute timely signals with inverting to achieve XNOR function. The primary operation and simulation of the proposal HNN is demonstrated.

Fault-tolerance in Two-dimensional Topological Systems

NASA Astrophysics Data System (ADS)

Anderson, Jonas T.

This thesis is a collection of ideas with the general goal of building, at least in the abstract, a local fault-tolerant quantum computer. The connection between quantum information and topology has proven to be an active area of research in several fields. The introduction of the toric code by Alexei Kitaev demonstrated the usefulness of topology for quantum memory and quantum computation. Many quantum codes used for quantum memory are modeled by spin systems on a lattice, with operators that extract syndrome information placed on vertices or faces of the lattice. It is natural to wonder whether the useful codes in such systems can be classified. This thesis presents work that leverages ideas from topology and graph theory to explore the space of such codes. Homological stabilizer codes are introduced and it is shown that, under a set of reasonable assumptions, any qubit homological stabilizer code is equivalent to either a toric code or a color code. Additionally, the toric code and the color code correspond to distinct classes of graphs. Many systems have been proposed as candidate quantum computers. It is very desirable to design quantum computing architectures with two-dimensional layouts and low complexity in parity-checking circuitry. Kitaev's surface codes provided the first example of codes satisfying this property. They provided a new route to fault tolerance with more modest overheads and thresholds approaching 1%. The recently discovered color codes share many properties with the surface codes, such as the ability to perform syndrome extraction locally in two dimensions. Some families of color codes admit a transversal implementation of the entire Clifford group. This work investigates color codes on the 4.8.8 lattice known as triangular codes. I develop a fault-tolerant error-correction strategy for these codes in which repeated syndrome measurements on this lattice generate a three-dimensional space-time combinatorial structure. I then develop an integer program that analyzes this structure and determines the most likely set of errors consistent with the observed syndrome values. I implement this integer program to find the threshold for depolarizing noise on small versions of these triangular codes. Because the threshold for magic-state distillation is likely to be higher than this value and because logical CNOT gates can be performed by code deformation in a single block instead of between pairs of blocks, the threshold for fault-tolerant quantum memory for these codes is also the threshold for fault-tolerant quantum computation with them. Since the advent of a threshold theorem for quantum computers much has been improved upon. Thresholds have increased, architectures have become more local, and gate sets have been simplified. The overhead for magic-state distillation has been studied, but not nearly to the extent of the aforementioned topics. A method for greatly reducing this overhead, known as reusable magic states, is studied here. While examples of reusable magic states exist for Clifford gates, I give strong reasons to believe they do not exist for non-Clifford gates.

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-07-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells.

PubMed

Paydavosi, Sarah; Aidala, Katherine E; Brown, Patrick R; Hashemi, Pouya; Supran, Geoffrey J; Osedach, Timothy P; Hoyt, Judy L; Bulović, Vladimir

2012-03-14

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells. © 2012 American Chemical Society

A Cognitive Neural Architecture Able to Learn and Communicate through Natural Language.

PubMed

Golosio, Bruno; Cangelosi, Angelo; Gamotina, Olesya; Masala, Giovanni Luca

2015-01-01

Communicative interactions involve a kind of procedural knowledge that is used by the human brain for processing verbal and nonverbal inputs and for language production. Although considerable work has been done on modeling human language abilities, it has been difficult to bring them together to a comprehensive tabula rasa system compatible with current knowledge of how verbal information is processed in the brain. This work presents a cognitive system, entirely based on a large-scale neural architecture, which was developed to shed light on the procedural knowledge involved in language elaboration. The main component of this system is the central executive, which is a supervising system that coordinates the other components of the working memory. In our model, the central executive is a neural network that takes as input the neural activation states of the short-term memory and yields as output mental actions, which control the flow of information among the working memory components through neural gating mechanisms. The proposed system is capable of learning to communicate through natural language starting from tabula rasa, without any a priori knowledge of the structure of phrases, meaning of words, role of the different classes of words, only by interacting with a human through a text-based interface, using an open-ended incremental learning process. It is able to learn nouns, verbs, adjectives, pronouns and other word classes, and to use them in expressive language. The model was validated on a corpus of 1587 input sentences, based on literature on early language assessment, at the level of about 4-years old child, and produced 521 output sentences, expressing a broad range of language processing functionalities.

Cascading of molecular logic gates for advanced functions: a self-reporting, activatable photosensitizer.

PubMed

Erbas-Cakmak, Sundus; Akkaya, Engin U

2013-10-18

Logical progress: Independent molecular logic gates have been designed and characterized. Then, the individual molecular logic gates were coerced to work together within a micelle. Information relay between the two logic gates was achieved through the intermediacy of singlet oxygen. Working together, these concatenated logic gates result in a self-reporting and activatable photosensitizer. GSH=glutathione. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Early auditory evoked potential is modulated by selective attention and related to individual differences in visual working memory capacity.

PubMed

Giuliano, Ryan J; Karns, Christina M; Neville, Helen J; Hillyard, Steven A

2014-12-01

A growing body of research suggests that the predictive power of working memory (WM) capacity for measures of intellectual aptitude is due to the ability to control attention and select relevant information. Crucially, attentional mechanisms implicated in controlling access to WM are assumed to be domain-general, yet reports of enhanced attentional abilities in individuals with larger WM capacities are primarily within the visual domain. Here, we directly test the link between WM capacity and early attentional gating across sensory domains, hypothesizing that measures of visual WM capacity should predict an individual's capacity to allocate auditory selective attention. To address this question, auditory ERPs were recorded in a linguistic dichotic listening task, and individual differences in ERP modulations by attention were correlated with estimates of WM capacity obtained in a separate visual change detection task. Auditory selective attention enhanced ERP amplitudes at an early latency (ca. 70-90 msec), with larger P1 components elicited by linguistic probes embedded in an attended narrative. Moreover, this effect was associated with greater individual estimates of visual WM capacity. These findings support the view that domain-general attentional control mechanisms underlie the wide variation of WM capacity across individuals.

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

Proposal for a graphene-based all-spin logic gate

NASA Astrophysics Data System (ADS)

Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Zhang, Youguang; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud

2015-02-01

In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (˜μm), higher data throughput, faster computing speed (˜ns), and lower power consumption (˜μA) can be expected from the G-ASLG.

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

NASA Astrophysics Data System (ADS)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values. The CNT transistors with field tunable band gaps would facilitate field programmable circuits based on the self-organized CNTs, and might also lead to novel analog memory, neuromorphic, and photonic devices.

Stimulation of nicotinic acetylcholine alpha7 receptors rescue schizophrenia-like cognitive impairments in rats.

PubMed

Potasiewicz, Agnieszka; Nikiforuk, Agnieszka; Hołuj, Małgorzata; Popik, Piotr

2017-02-01

Alpha7 nicotinic acetylcholine receptor (α7 nAChR) dysfunction plays an important role in schizophrenia. Positive allosteric modulators of α7 nAChR have emerged as a promising therapeutic approach to manage cognitive deficits that are inadequately treated in schizophrenic patients. The aim of the present study was to evaluate the ability of type I (CCMI) and type II (PNU120596) α7 nAChR positive allosteric modulators to counteract MK-801-induced cognitive and sensorimotor gating deficits. The activity of these compounds was compared with the action of the α7 nAChR agonist A582941. CCMI, PNU120596 and A582941 reversed the sensorimotor gating impairment evoked by MK-801 based on the prepulse inhibition of the startle response. Additionally, no MK-801-evoked working memory deficits were observed with α7 nAChR ligand pretreatment as assessed in a discrete paired-trial delayed alternation task. However, these compounds did not affect the rats' attentional performances in the five-choice serial reaction time test. The α7 nAChR agents demonstrated a beneficial effect on sensorimotor gating and some aspects of cognition tested in a rat model of schizophrenia. Therefore, these results support the use of α7 nAChR positive allosteric modulators as a potential treatment strategy in schizophrenia.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Optical imaging through turbid media with a degenerate four-wave mixing correlation time gate

DOEpatents

Sappey, Andrew D.

1998-04-14

Optical imaging through turbid media is demonstrated using a degenerate four-wave mixing correlation time gate. An apparatus and method for detecting ballistic and/or snake light while rejecting unwanted diffusive light for imaging structures within highly scattering media are described. Degenerate four-wave mixing (DFWM) of a doubled YAG laser in rhodamine 590 is used to provide an ultrafast correlation time gate to discriminate against light that has undergone multiple scattering and therefore has lost memory of the structures within the scattering medium. Images have been obtained of a test cross-hair pattern through highly turbid suspensions of whole milk in water that are opaque to the naked eye, which demonstrates the utility of DFWM for imaging through turbid media. Use of DFWM as an ultrafast time gate for the detection of ballistic and/or snake light in optical mammography is discussed.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

NASA Astrophysics Data System (ADS)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

Protein-Based Three-Dimensional Memories and Associative Processors

NASA Astrophysics Data System (ADS)

Birge, Robert

2008-03-01

The field of bioelectronics has benefited from the fact that nature has often solved problems of a similar nature to those which must be solved to create molecular electronic or photonic devices that operate with efficiency and reliability. Retinal proteins show great promise in bioelectronic devices because they operate with high efficiency (˜0.65%), high cyclicity (>10^7), operate over an extended wavelength range (360 -- 630 nm) and can convert light into changes in voltage, pH, absorption or refractive index. This talk will focus on a retinal protein called bacteriorhodopsin, the proton pump of the organism Halobacterium salinarum. Two memories based on this protein will be described. The first is an optical three-dimensional memory. This memory stores information using volume elements (voxels), and provides as much as a thousand-fold improvement in effective capacity over current technology. A unique branching reaction of a variant of bacteriorhodopsin is used to turn each protein into an optically addressed latched AND gate. Although three working prototypes have been developed, a number of cost/performance and architectural issues must be resolved prior to commercialization. The major issue is that the native protein provides a very inefficient branching reaction. Genetic engineering has improved performance by nearly 500-fold, but a further order of magnitude improvement is needed. Protein-based holographic associative memories will also be discussed. The human brain stores and retrieves information via association, and human intelligence is intimately connected to the nature and enormous capacity of this associative search and retrieval process. To a first order approximation, creativity can be viewed as the association of two seemingly disparate concepts to form a totally new construct. Thus, artificial intelligence requires large scale associative memories. Current computer hardware does not provide an optimal environment for creating artificial intelligence due to the serial nature of random access memories. Software cannot provide a satisfactory work-around that does not introduce unacceptable latency. Holographic associative memories provide a useful approach to large scale associative recall. Bacteriorhodopsin has long been recognized for its outstanding holographic properties, and when utilized in the Paek and Psaltis design, provides a high-speed real-time associative memory with variable thresholding and feedback. What remains is to make an associative memory capable of high-speed association and long-term data storage. The use of directed evolution to create a protein with the necessary unique properties will be discussed.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Memory elements in the electrical network of Mimosa pudica L.

PubMed Central

Volkov, Alexander G; Reedus, Jada; Mitchell, Colee M; Tuckett, Clayton; Volkova, Maya I; Markin, Vladislav S; Chua, Leon

2014-01-01

The fourth basic circuit element, a memristor, is a resistor with memory that was postulated by Chua in 1971. Here we found that memristors exist in vivo. The electrostimulation of the Mimosa pudica by bipolar sinusoidal or triangle periodic waves induce electrical responses with fingerprints of memristors. Uncouplers carbonylcyanide-3-chlorophenylhydrazone and carbonylcyanide-4-trifluoromethoxy-phenyl hydrazone decrease the amplitude of electrical responses at low and high frequencies of bipolar sinusoidal or triangle periodic electrostimulating waves. Memristive behavior of an electrical network in the Mimosa pudica is linked to the properties of voltage gated ion channels: the channel blocker TEACl reduces the electric response to a conventional resistor. Our results demonstrate that a voltage gated K+ channel in the excitable tissue of plants has properties of a memristor. The discovery of memristors in plants creates a new direction in the modeling and understanding of electrical phenomena in plants. PMID:25482796

Memory elements in the electrical network of Mimosa pudica L.

PubMed

Volkov, Alexander G; Reedus, Jada; Mitchell, Colee M; Tuckett, Clayton; Volkova, Maya I; Markin, Vladislav S; Chua, Leon

2014-01-01

The fourth basic circuit element, a memristor, is a resistor with memory that was postulated by Chua in 1971. Here we found that memristors exist in vivo. The electrostimulation of the Mimosa pudica by bipolar sinusoidal or triangle periodic waves induce electrical responses with fingerprints of memristors. Uncouplers carbonylcyanide-3-chlorophenylhydrazone and carbonylcyanide-4-trifluoromethoxy-phenyl hydrazone decrease the amplitude of electrical responses at low and high frequencies of bipolar sinusoidal or triangle periodic electrostimulating waves. Memristive behavior of an electrical network in the Mimosa pudica is linked to the properties of voltage gated ion channels: the channel blocker TEACl reduces the electric response to a conventional resistor. Our results demonstrate that a voltage gated K(+) channel in the excitable tissue of plants has properties of a memristor. The discovery of memristors in plants creates a new direction in the modeling and understanding of electrical phenomena in plants.

Ferroelectric polarization induces electric double layer bistability in electrolyte-gated field-effect transistors.

PubMed

Fabiano, Simone; Crispin, Xavier; Berggren, Magnus

2014-01-08

The dense surface charges expressed by a ferroelectric polymeric thin film induce ion displacement within a polyelectrolyte layer and vice versa. This is because the density of dipoles along the surface of the ferroelectric thin film and its polarization switching time matches that of the (Helmholtz) electric double layers formed at the ferroelectric/polyelectrolyte and polyelectrolyte/semiconductor interfaces. This combination of materials allows for introducing hysteresis effects in the capacitance of an electric double layer capacitor. The latter is advantageously used to control the charge accumulation in the semiconductor channel of an organic field-effect transistor. The resulting memory transistors can be written at a gate voltage of around 7 V and read out at a drain voltage as low as 50 mV. The technological implication of this large difference between write and read-out voltages lies in the non-destructive reading of this ferroelectric memory.

All-optical clocked flip-flops and random access memory cells using the nonlinear polarization rotation effect of low-polarization-dependent semiconductor optical amplifiers

NASA Astrophysics Data System (ADS)

Wang, Yongjun; Liu, Xinyu; Tian, Qinghua; Wang, Lina; Xin, Xiangjun

2018-03-01

Basic configurations of various all-optical clocked flip-flops (FFs) and optical random access memory (RAM) based on the nonlinear polarization rotation (NPR) effect of low-polarization-dependent semiconductor optical amplifiers (SOA) are proposed. As the constituent elements, all-optical logic gates and all-optical SR latches are constructed by taking advantage of the SOA's NPR switch. Different all-optical FFs (AOFFs), including SR-, D-, T-, and JK-types as well as an optical RAM cell were obtained by the combination of the proposed all-optical SR latches and logic gates. The effectiveness of the proposed schemes were verified by simulation results and demonstrated by a D-FF and 1-bit RAM cell experimental system. The proposed all-optical clocked FFs and RAM cell are significant to all-optical signal processing.

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Short- and long-term memory effects in intensified array detectors - Influence on airborne laser fluorosensor measurements

NASA Astrophysics Data System (ADS)

Bristow, Michael P.; Edmonds, Curtis M.; Bundy, Donald H.; Turner, Rudolpha M.

1989-02-01

Phosphorescence and thermoluminescence memory effects in the phosphors of image intensifiers are investigated, with application to the performance improvement of intensified optical multichannel analyzers. Algorithms have been developed which can be used to remove these effects from airborne measurements of laser-induced fluorescence spectra of aquatic and terrestrial targets. The present method can be adapted to situations involving different gating routines, repetition rates, and diode group sizes.

Fast, noise-free memory for photon synchronization at room temperature.

PubMed

Finkelstein, Ran; Poem, Eilon; Michel, Ohad; Lahad, Ohr; Firstenberg, Ofer

2018-01-01

Future quantum photonic networks require coherent optical memories for synchronizing quantum sources and gates of probabilistic nature. We demonstrate a fast ladder memory (FLAME) mapping the optical field onto the superposition between electronic orbitals of rubidium vapor. Using a ladder-level system of orbital transitions with nearly degenerate frequencies simultaneously enables high bandwidth, low noise, and long memory lifetime. We store and retrieve 1.7-ns-long pulses, containing 0.5 photons on average, and observe short-time external efficiency of 25%, memory lifetime (1/ e ) of 86 ns, and below 10 -4 added noise photons. Consequently, coupling this memory to a probabilistic source would enhance the on-demand photon generation probability by a factor of 12, the highest number yet reported for a noise-free, room temperature memory. This paves the way toward the controlled production of large quantum states of light from probabilistic photon sources.

Resonant tunneling based graphene quantum dot memristors.

PubMed

Pan, Xuan; Skafidas, Efstratios

2016-12-08

In this paper, we model two-terminal all graphene quantum dot (GQD) based resistor-type memory devices (memristors). The resistive switching is achieved by resonant electron tunneling. We show that parallel GQDs can be used to create multi-state memory circuits. The number of states can be optimised with additional voltage sources, whilst the noise margin for each state can be controlled by appropriately choosing the branch resistance. A three-terminal GQD device configuration is also studied. The addition of an isolated gate terminal can be used to add further or modify the states of the memory device. The proposed devices provide a promising route towards volatile memory devices utilizing only atomically thin two-dimensional graphene.

High efficiency coherent optical memory with warm rubidium vapour

PubMed Central

Hosseini, M.; Sparkes, B.M.; Campbell, G.; Lam, P.K.; Buchler, B.C.

2011-01-01

By harnessing aspects of quantum mechanics, communication and information processing could be radically transformed. Promising forms of quantum information technology include optical quantum cryptographic systems and computing using photons for quantum logic operations. As with current information processing systems, some form of memory will be required. Quantum repeaters, which are required for long distance quantum key distribution, require quantum optical memory as do deterministic logic gates for optical quantum computing. Here, we present results from a coherent optical memory based on warm rubidium vapour and show 87% efficient recall of light pulses, the highest efficiency measured to date for any coherent optical memory suitable for quantum information applications. We also show storage and recall of up to 20 pulses from our system. These results show that simple warm atomic vapour systems have clear potential as a platform for quantum memory. PMID:21285952

High efficiency coherent optical memory with warm rubidium vapour.

PubMed

Hosseini, M; Sparkes, B M; Campbell, G; Lam, P K; Buchler, B C

2011-02-01

By harnessing aspects of quantum mechanics, communication and information processing could be radically transformed. Promising forms of quantum information technology include optical quantum cryptographic systems and computing using photons for quantum logic operations. As with current information processing systems, some form of memory will be required. Quantum repeaters, which are required for long distance quantum key distribution, require quantum optical memory as do deterministic logic gates for optical quantum computing. Here, we present results from a coherent optical memory based on warm rubidium vapour and show 87% efficient recall of light pulses, the highest efficiency measured to date for any coherent optical memory suitable for quantum information applications. We also show storage and recall of up to 20 pulses from our system. These results show that simple warm atomic vapour systems have clear potential as a platform for quantum memory.

Computing with volatile memristors: an application of non-pinched hysteresis

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Shevchenko, S. N.

2017-02-01

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated theoretically. We have adopted a hysteretic graphene-based field emission structure as a prototype of a volatile memristor, which is characterized by a non-pinched hysteresis loop. A memristive model of the structure is developed and used to simulate a polymorphic circuit implementing stateful logic gates, such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices, such as certain NEMS switches.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

GABAergic contributions to gating, timing, and phase precession of hippocampal neuronal activity during theta oscillations.

PubMed

Cutsuridis, Vassilis; Hasselmo, Michael

2012-07-01

Successful spatial exploration requires gating, storage, and retrieval of spatial memories in the correct order. The hippocampus is known to play an important role in the temporal organization of spatial information. Temporally ordered spatial memories are encoded and retrieved by the firing rate and phase of hippocampal pyramidal cells and inhibitory interneurons with respect to ongoing network theta oscillations paced by intra- and extrahippocampal areas. Much is known about the anatomical, physiological, and molecular characteristics as well as the connectivity and synaptic properties of various cell types in the hippocampal microcircuits, but how these detailed properties of individual neurons give rise to temporal organization of spatial memories remains unclear. We present a model of the hippocampal CA1 microcircuit based on observed biophysical properties of pyramidal cells and six types of inhibitory interneurons: axo-axonic, basket, bistratistified, neurogliaform, ivy, and oriens lacunosum-moleculare cells. The model simulates a virtual rat running on a linear track. Excitatory transient inputs come from the entorhinal cortex (EC) and the CA3 Schaffer collaterals and impinge on both the pyramidal cells and inhibitory interneurons, whereas inhibitory inputs from the medial septum impinge only on the inhibitory interneurons. Dopamine operates as a gate-keeper modulating the spatial memory flow to the PC distal dendrites in a frequency-dependent manner. A mechanism for spike-timing-dependent plasticity in distal and proximal PC dendrites consisting of three calcium detectors, which responds to the instantaneous calcium level and its time course in the dendrite, is used to model the plasticity effects. The model simulates the timing of firing of different hippocampal cell types relative to theta oscillations, and proposes functional roles for the different classes of the hippocampal and septal inhibitory interneurons in the correct ordering of spatial memories as well as in the generation and maintenance of theta phase precession of pyramidal cells (place cells) in CA1. The model leads to a number of experimentally testable predictions that may lead to a better understanding of the biophysical computations in the hippocampus and medial septum. Copyright © 2011 Wiley Periodicals, Inc.

Quasi-classical modeling of molecular quantum-dot cellular automata multidriver gates

NASA Astrophysics Data System (ADS)

Rahimi, Ehsan; Nejad, Shahram Mohammad

2012-05-01

Molecular quantum-dot cellular automata (mQCA) has received considerable attention in nanoscience. Unlike the current-based molecular switches, where the digital data is represented by the on/off states of the switches, in mQCA devices, binary information is encoded in charge configuration within molecular redox centers. The mQCA paradigm allows high device density and ultra-low power consumption. Digital mQCA gates are the building blocks of circuits in this paradigm. Design and analysis of these gates require quantum chemical calculations, which are demanding in computer time and memory. Therefore, developing simple models to probe mQCA gates is of paramount importance. We derive a semi-classical model to study the steady-state output polarization of mQCA multidriver gates, directly from the two-state approximation in electron transfer theory. The accuracy and validity of this model are analyzed using full quantum chemistry calculations. A complete set of logic gates, including inverters and minority voters, are implemented to provide an appropriate test bench in the two-dot mQCA regime. We also briefly discuss how the QCADesigner tool could find its application in simulation of mQCA devices.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Solid State Research, 1981-1

DTIC Science & Technology

1981-02-15

Pine J. Mol. Spectrosc. 84, 132 v I + v 3 Combination Band of SO 2 M. Dang-Nhu* (1980) 5076 Formation of the XeBr Exciplex D. J. Ehrlich J. Chem. Phys...heteroepitaxial Ge film deposited on (I00>Si at Ts 550*C. III 0 5P.m 130- ol III --- SURFACEIGe,-,Si, ALLOY (b) * *I (b)) ,0, ++, p...:l: Fig. 111-8. (a) Bright...with the 32 input samples in the CCD ( ol wells. Center cross section: With the write voltage applied to the memory gate and the first transfer gate

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Radiation Effects on Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Guertin, S.; Swift, G. M.; Johnston, A. H.

1998-01-01

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

On the robustness of bucket brigade quantum RAM

NASA Astrophysics Data System (ADS)

Arunachalam, Srinivasan; Gheorghiu, Vlad; Jochym-O'Connor, Tomas; Mosca, Michele; Varshinee Srinivasan, Priyaa

2015-12-01

We study the robustness of the bucket brigade quantum random access memory model introduced by Giovannetti et al (2008 Phys. Rev. Lett.100 160501). Due to a result of Regev and Schiff (ICALP ’08 733), we show that for a class of error models the error rate per gate in the bucket brigade quantum memory has to be of order o({2}-n/2) (where N={2}n is the size of the memory) whenever the memory is used as an oracle for the quantum searching problem. We conjecture that this is the case for any realistic error model that will be encountered in practice, and that for algorithms with super-polynomially many oracle queries the error rate must be super-polynomially small, which further motivates the need for quantum error correction. By contrast, for algorithms such as matrix inversion Harrow et al (2009 Phys. Rev. Lett.103 150502) or quantum machine learning Rebentrost et al (2014 Phys. Rev. Lett.113 130503) that only require a polynomial number of queries, the error rate only needs to be polynomially small and quantum error correction may not be required. We introduce a circuit model for the quantum bucket brigade architecture and argue that quantum error correction for the circuit causes the quantum bucket brigade architecture to lose its primary advantage of a small number of ‘active’ gates, since all components have to be actively error corrected.

Ontogeny of sensorimotor gating and short-term memory processing throughout the adolescent period in rats.

PubMed

Goepfrich, Anja A; Friemel, Chris M; Pauen, Sabina; Schneider, Miriam

2017-06-01

Adolescence and puberty are highly susceptible developmental periods during which the neuronal organization and maturation of the brain is completed. The endocannabinoid (eCB) system, which is well known to modulate cognitive processing, undergoes profound and transient developmental changes during adolescence. With the present study we were aiming to examine the ontogeny of cognitive skills throughout adolescence in male rats and clarify the potential modulatory role of CB1 receptor signalling. Cognitive skills were assessed repeatedly every 10th day in rats throughout adolescence. All animals were tested for object recognition memory and prepulse inhibition of the acoustic startle reflex. Although cognitive performance in short-term memory as well as sensorimotor gating abilities were decreased during puberty compared to adulthood, both tasks were found to show different developmental trajectories throughout adolescence. A low dose of the CB1 receptor antagonist/inverse agonist SR141716 was found to improve recognition memory specifically in pubertal animals while not affecting behavioral performance at other ages tested. The present findings demonstrate that the developmental trajectory of cognitive abilities does not occur linearly for all cognitive processes and is strongly influenced by pubertal maturation. Developmental alterations within the eCB system at puberty onset may be involved in these changes in cognitive processing. Copyright © 2016 The Authors. Published by Elsevier Ltd.. All rights reserved.

Cusps enable line attractors for neural computation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiao, Zhuocheng; Zhang, Jiwei; Sornborger, Andrew T.

Here, line attractors in neuronal networks have been suggested to be the basis of many brain functions, such as working memory, oculomotor control, head movement, locomotion, and sensory processing. In this paper, we make the connection between line attractors and pulse gating in feed-forward neuronal networks. In this context, because of their neutral stability along a one-dimensional manifold, line attractors are associated with a time-translational invariance that allows graded information to be propagated from one neuronal population to the next. To understand how pulse-gating manifests itself in a high-dimensional, nonlinear, feedforward integrate-and-fire network, we use a Fokker-Planck approach to analyzemore » system dynamics. We make a connection between pulse-gated propagation in the Fokker-Planck and population-averaged mean-field (firing rate) models, and then identify an approximate line attractor in state space as the essential structure underlying graded information propagation. An analysis of the line attractor shows that it consists of three fixed points: a central saddle with an unstable manifold along the line and stable manifolds orthogonal to the line, which is surrounded on either side by stable fixed points. Along the manifold defined by the fixed points, slow dynamics give rise to a ghost. We show that this line attractor arises at a cusp catastrophe, where a fold bifurcation develops as a function of synaptic noise; and that the ghost dynamics near the fold of the cusp underly the robustness of the line attractor. Understanding the dynamical aspects of this cusp catastrophe allows us to show how line attractors can persist in biologically realistic neuronal networks and how the interplay of pulse gating, synaptic coupling, and neuronal stochasticity can be used to enable attracting one-dimensional manifolds and, thus, dynamically control the processing of graded information.« less

Cusps enable line attractors for neural computation

NASA Astrophysics Data System (ADS)

Xiao, Zhuocheng; Zhang, Jiwei; Sornborger, Andrew T.; Tao, Louis

2017-11-01

Line attractors in neuronal networks have been suggested to be the basis of many brain functions, such as working memory, oculomotor control, head movement, locomotion, and sensory processing. In this paper, we make the connection between line attractors and pulse gating in feed-forward neuronal networks. In this context, because of their neutral stability along a one-dimensional manifold, line attractors are associated with a time-translational invariance that allows graded information to be propagated from one neuronal population to the next. To understand how pulse-gating manifests itself in a high-dimensional, nonlinear, feedforward integrate-and-fire network, we use a Fokker-Planck approach to analyze system dynamics. We make a connection between pulse-gated propagation in the Fokker-Planck and population-averaged mean-field (firing rate) models, and then identify an approximate line attractor in state space as the essential structure underlying graded information propagation. An analysis of the line attractor shows that it consists of three fixed points: a central saddle with an unstable manifold along the line and stable manifolds orthogonal to the line, which is surrounded on either side by stable fixed points. Along the manifold defined by the fixed points, slow dynamics give rise to a ghost. We show that this line attractor arises at a cusp catastrophe, where a fold bifurcation develops as a function of synaptic noise; and that the ghost dynamics near the fold of the cusp underly the robustness of the line attractor. Understanding the dynamical aspects of this cusp catastrophe allows us to show how line attractors can persist in biologically realistic neuronal networks and how the interplay of pulse gating, synaptic coupling, and neuronal stochasticity can be used to enable attracting one-dimensional manifolds and, thus, dynamically control the processing of graded information.

Cusps enable line attractors for neural computation

DOE PAGES

Xiao, Zhuocheng; Zhang, Jiwei; Sornborger, Andrew T.; ...

2017-11-07

Here, line attractors in neuronal networks have been suggested to be the basis of many brain functions, such as working memory, oculomotor control, head movement, locomotion, and sensory processing. In this paper, we make the connection between line attractors and pulse gating in feed-forward neuronal networks. In this context, because of their neutral stability along a one-dimensional manifold, line attractors are associated with a time-translational invariance that allows graded information to be propagated from one neuronal population to the next. To understand how pulse-gating manifests itself in a high-dimensional, nonlinear, feedforward integrate-and-fire network, we use a Fokker-Planck approach to analyzemore » system dynamics. We make a connection between pulse-gated propagation in the Fokker-Planck and population-averaged mean-field (firing rate) models, and then identify an approximate line attractor in state space as the essential structure underlying graded information propagation. An analysis of the line attractor shows that it consists of three fixed points: a central saddle with an unstable manifold along the line and stable manifolds orthogonal to the line, which is surrounded on either side by stable fixed points. Along the manifold defined by the fixed points, slow dynamics give rise to a ghost. We show that this line attractor arises at a cusp catastrophe, where a fold bifurcation develops as a function of synaptic noise; and that the ghost dynamics near the fold of the cusp underly the robustness of the line attractor. Understanding the dynamical aspects of this cusp catastrophe allows us to show how line attractors can persist in biologically realistic neuronal networks and how the interplay of pulse gating, synaptic coupling, and neuronal stochasticity can be used to enable attracting one-dimensional manifolds and, thus, dynamically control the processing of graded information.« less

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Dexras1 a unique ras-GTPase interacts with NMDA receptor activity and provides a novel dissociation between anxiety, working memory and sensory gating.

PubMed

Carlson, G C; Lin, R E; Chen, Y; Brookshire, B R; White, R S; Lucki, I; Siegel, S J; Kim, S F

2016-05-13

Dexras1 is a novel GTPase that acts at a confluence of signaling mechanisms associated with psychiatric and neurological disease including NMDA receptors, NOS1AP and nNOS. Recent work has shown that Dexras1 mediates iron trafficking and NMDA-dependent neurodegeneration but a role for Dexras1 in normal brain function or psychiatric disease has not been studied. To test for such a role, mice with germline knockout (KO) of Dexras1 were assayed for behavioral abnormalities as well as changes in NMDA receptor subunit protein expression. Because Dexras1 is up-regulated during stress or by dexamethasone treatment, we included measures associated with emotion including anxiety and depression. Baseline anxiety-like measures (open field and zero maze) were not altered, nor were depression-like behavior (tail suspension). Measures of memory function yielded mixed results, with no changes in episodic memory (novel object recognition) but a significant decrement on working memory (T-maze). Alternatively, there was an increase in pre-pulse inhibition (PPI), without concomitant changes in either startle amplitude or locomotor activity. PPI data are consistent with the direction of change seen following exposure to dopamine D2 antagonists. An examination of NMDA subunit expression levels revealed an increased expression of the NR2A subunit, contrary to previous studies demonstrating down-regulation of the receptor following antipsychotic exposure (Schmitt et al., 2003) and up-regulation after exposure to isolation rearing (Turnock-Jones et al., 2009). These findings suggest a potential role for Dexras1 in modulating a selective subset of psychiatric symptoms, possibly via its interaction with NMDARs and/or other disease-related binding-partners. Furthermore, data suggest that modulating Dexras1 activity has contrasting effects on emotional, sensory and cognitive domains. Copyright © 2016 IBRO. Published by Elsevier Ltd. All rights reserved.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

Effects of Transcranial Direct Current Stimulation over Left Dorsolateral pFC on the Attentional Blink Depend on Individual Baseline Performance.

PubMed

London, Raquel E; Slagter, Heleen A

2015-12-01

Selection mechanisms that dynamically gate only relevant perceptual information for further processing and sustained representation in working memory are critical for goal-directed behavior. We examined whether this gating process can be modulated by anodal transcranial direct current stimulation (tDCS) over left dorsolateral pFC (DLPFC)--a region known to play a key role in working memory and conscious access. Specifically, we examined the effects of tDCS on the magnitude of the so-called "attentional blink" (AB), a deficit in identifying the second of two targets presented in rapid succession. Thirty-four participants performed a standard AB task before (baseline), during, and after 20 min of 1-mA anodal and cathodal tDCS in two separate sessions. On the basis of previous reports linking individual differences in AB magnitude to individual differences in DLPFC activity and on suggestions that effects of tDCS depend on baseline brain activity levels, we hypothesized that anodal tDCS over left DLPFC would modulate the magnitude of the AB as a function of individual baseline AB magnitude. Indeed, individual differences analyses revealed that anodal tDCS decreased the AB in participants with a large baseline AB but increased the AB in participants with a small baseline AB. This effect was only observed during (but not after) stimulation, was not found for cathodal tDCS, and could not be explained by regression to the mean. Notably, the effects of tDCS were not apparent at the group level, highlighting the importance of taking individual variability in performance into account when evaluating the effectiveness of tDCS. These findings support the idea that left DLPFC plays a critical role in the AB and in conscious access more generally. They are also in line with the notion that there is an optimal level of prefrontal activity for cognitive function, with both too little and too much activity hurting performance.

Multi-element logic gates for trapped-ion qubits

NASA Astrophysics Data System (ADS)

Tan, T. R.; Gaebler, J. P.; Lin, Y.; Wan, Y.; Bowler, R.; Leibfried, D.; Wineland, D. J.

2015-12-01

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a 9Be+ ion and a 25Mg+ ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

Multi-element logic gates for trapped-ion qubits.

PubMed

Tan, T R; Gaebler, J P; Lin, Y; Wan, Y; Bowler, R; Leibfried, D; Wineland, D J

2015-12-17

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a (9)Be(+) ion and a (25)Mg(+) ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

The Longevity of Hippocampus-Dependent Memory Is Orchestrated by the Locus Coeruleus-Noradrenergic System

PubMed Central

2017-01-01

The locus coeruleus is connected to the dorsal hippocampus via strong fiber projections. It becomes activated after arousal and novelty, whereupon noradrenaline is released in the hippocampus. Noradrenaline from the locus coeruleus is involved in modulating the encoding, consolidation, retrieval, and reversal of hippocampus-based memory. Memory storage can be modified by the activation of the locus coeruleus and subsequent facilitation of hippocampal long-term plasticity in the forms of long-term depression and long-term potentiation. Recent evidence indicates that noradrenaline and dopamine are coreleased in the hippocampus from locus coeruleus terminals, thus fostering neuromodulation of long-term synaptic plasticity and memory. Noradrenaline is an inductor of epigenetic modifications regulating transcriptional control of synaptic long-term plasticity to gate the endurance of memory storage. In conclusion, locus coeruleus activation primes the persistence of hippocampus-based long-term memory. PMID:28695015

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

2004-01-01

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

An integrative theory of the phasic and tonic modes of dopamine modulation in the prefrontal cortex.

PubMed

Dreher, Jean-Claude; Burnod, Yves

2002-01-01

This paper presents a model of both tonic and phasic dopamine (DA) effects on maintenance of working memory representations in the prefrontal cortex (PFC). The central hypothesis is that DA modulates the efficacy of inputs to prefrontal pyramidal neurons to prevent interferences for active maintenance. Phasic DA release, due to DA neurons discharges, acts at a short time-scale (a few seconds), while the tonic mode of DA release, independent of DA neurons firing, acts at a long time-scale (a few minutes). The overall effect of DA modulation is modeled as a threshold restricting incoming inputs arriving on PFC neurons. Phasic DA release temporary increases this threshold while tonic DA release progressively increases the basal level of this threshold. Thus, unlike the previous gating theory of phasic DA release, proposing that it facilitates incoming inputs at the time of their arrival, the effect of phasic DA release is supposed to restrict incoming inputs during a period of time after DA neuron discharges. The model links the cellular and behavioral levels during performance of a working memory task. It allows us to understand why a critical range of DA D1 receptors stimulation is required for optimal working memory performance and how D1 receptor agonists (respectively antagonists) increase perseverations (respectively distractability). Finally, the model leads to several testable predictions, including that the PFC regulates DA neurons firing rate to adapt to the delay of the task and that increase in tonic DA release may either improve or decrease performance, depending on the level of DA receptors stimulation at the beginning of the task.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Aspects of the homeostaic plasticity of GABAA receptor-mediated inhibition

PubMed Central

Mody, Istvan

2005-01-01

Plasticity of ligand-gated ion channels plays a critical role in nervous system development, circuit formation and refinement, and pathological processes. Recent advances have mainly focused on the plasticity of channels gated by excitatory amino acids, including their acclaimed role in learning and memory. These receptors, together with voltage-gated ion channels, have also been known to be subjected to a homeostatic form of plasticity that prevents destabilization of the neurone's function and that of the network during various physiological processes. To date, the plasticity of GABAA receptors has been examined mainly from a developmental and a pathological point of view. Little is known about homeostatic mechanisms governing their plasticity. This review summarizes some of the findings on the homeostatic plasticity of tonic and phasic inhibitory activity. PMID:15528237

Short-Term Synaptic Plasticity Regulation in Solution-Gated Indium-Gallium-Zinc-Oxide Electric-Double-Layer Transistors.

PubMed

Wan, Chang Jin; Liu, Yang Hui; Zhu, Li Qiang; Feng, Ping; Shi, Yi; Wan, Qing

2016-04-20

In the biological nervous system, synaptic plasticity regulation is based on the modulation of ionic fluxes, and such regulation was regarded as the fundamental mechanism underlying memory and learning. Inspired by such biological strategies, indium-gallium-zinc-oxide (IGZO) electric-double-layer (EDL) transistors gated by aqueous solutions were proposed for synaptic behavior emulations. Short-term synaptic plasticity, such as paired-pulse facilitation, high-pass filtering, and orientation tuning, was experimentally emulated in these EDL transistors. Most importantly, we found that such short-term synaptic plasticity can be effectively regulated by alcohol (ethyl alcohol) and salt (potassium chloride) additives. Our results suggest that solution gated oxide-based EDL transistors could act as the platforms for short-term synaptic plasticity emulation.

Analogue spin-orbit torque device for artificial-neural-network-based associative memory operation

NASA Astrophysics Data System (ADS)

Borders, William A.; Akima, Hisanao; Fukami, Shunsuke; Moriya, Satoshi; Kurihara, Shouta; Horio, Yoshihiko; Sato, Shigeo; Ohno, Hideo

2017-01-01

We demonstrate associative memory operations reminiscent of the brain using nonvolatile spintronics devices. Antiferromagnet-ferromagnet bilayer-based Hall devices, which show analogue-like spin-orbit torque switching under zero magnetic fields and behave as artificial synapses, are used. An artificial neural network is used to associate memorized patterns from their noisy versions. We develop a network consisting of a field-programmable gate array and 36 spin-orbit torque devices. An effect of learning on associative memory operations is successfully confirmed for several 3 × 3-block patterns. A discussion on the present approach for realizing spintronics-based artificial intelligence is given.

Capacity of a quantum memory channel correlated by matrix product states

NASA Astrophysics Data System (ADS)

Mulherkar, Jaideep; Sunitha, V.

2018-04-01

We study the capacity of a quantum channel where channel acts like controlled phase gate with the control being provided by a one-dimensional quantum spin chain environment. Due to the correlations in the spin chain, we get a quantum channel with memory. We derive formulas for the quantum capacity of this channel when the spin state is a matrix product state. Particularly, we derive exact formulas for the capacity of the quantum memory channel when the environment state is the ground state of the AKLT model and the Majumdar-Ghosh model. We find that the behavior of the capacity for the range of the parameters is analytic.

Radiation-Tolerant Intelligent Memory Stack - RTIMS

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2011-01-01

This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Min Kim, Sung; Lee, Youngmin; Seo, David H.; Seo, Sunae; Wang, Kang L.

2012-12-01

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Verma, Abhishek; Sharma, Dheeraj; Tirkey, Sukeshni; Raad, Bhagwan Ram

2017-11-01

Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS ≤ 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION) and decrement of ambipolar conduction (Iambi) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit.

Recent Trends in Spintronics-Based Nanomagnetic Logic

NASA Astrophysics Data System (ADS)

Das, Jayita; Alam, Syed M.; Bhanja, Sanjukta

2014-09-01

With the growing concerns of standby power in sub-100-nm CMOS technologies, alternative computing techniques and memory technologies are explored. Spin transfer torque magnetoresistive RAM (STT-MRAM) is one such nonvolatile memory relying on magnetic tunnel junctions (MTJs) to store information. It uses spin transfer torque to write information and magnetoresistance to read information. In 2012, Everspin Technologies, Inc. commercialized the first 64Mbit Spin Torque MRAM. On the computing end, nanomagnetic logic (NML) is a promising technique with zero leakage and high data retention. In 2000, Cowburn and Welland first demonstrated its potential in logic and information propagation through magnetostatic interaction in a chain of single domain circular nanomagnetic dots of Supermalloy (Ni80Fe14Mo5X1, X is other metals). In 2006, Imre et al. demonstrated wires and majority gates followed by coplanar cross wire systems demonstration in 2010 by Pulecio et al. Since 2004 researchers have also investigated the potential of MTJs in logic. More recently with dipolar coupling between MTJs demonstrated in 2012, logic-in-memory architecture with STT-MRAM have been investigated. The architecture borrows the computing concept from NML and read and write style from MRAM. The architecture can switch its operation between logic and memory modes with clock as classifier. Further through logic partitioning between MTJ and CMOS plane, a significant performance boost has been observed in basic computing blocks within the architecture. In this work, we have explored the developments in NML, in MTJs and more recent developments in hybrid MTJ/CMOS logic-in-memory architecture and its unique logic partitioning capability.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Apparatus for sensing patterns of electrical field variations across a surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, William L.; Devine, Roderick A. B.

An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials createdmore » by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.« less

Early Auditory Evoked Potential Is Modulated by Selective Attention and Related to Individual Differences in Visual Working Memory Capacity

PubMed Central

Giuliano, Ryan J.; Karns, Christina M.; Neville, Helen J.; Hillyard, Steven A.

2015-01-01

A growing body of research suggests that the predictive power of working memory (WM) capacity for measures of intellectual aptitude is due to the ability to control attention and select relevant information. Crucially, attentional mechanisms implicated in controlling access to WM are assumed to be domain-general, yet reports of enhanced attentional abilities in individuals with larger WM capacities are primarily within the visual domain. Here, we directly test the link between WM capacity and early attentional gating across sensory domains, hypothesizing that measures of visual WM capacity should predict an individual’s capacity to allocate auditory selective attention. To address this question, auditory ERPs were recorded in a linguistic dichotic listening task, and individual differences in ERP modulations by attention were correlated with estimates of WM capacity obtained in a separate visual change detection task. Auditory selective attention enhanced ERP amplitudes at an early latency (ca. 70–90 msec), with larger P1 components elicited by linguistic probes embedded in an attended narrative. Moreover, this effect was associated with greater individual estimates of visual WM capacity. These findings support the view that domain-general attentional control mechanisms underlie the wide variation of WM capacity across individuals. PMID:25000526

Dissociable Frontal–Striatal and Frontal–Parietal Networks Involved in Updating Hierarchical Contexts in Working Memory

PubMed Central

Nee, Derek Evan; Brown, Joshua W.

2013-01-01

Recent theories propose that the prefrontal cortex (PFC) is organized in a hierarchical fashion with more abstract, higher level information represented in anterior regions and more concrete, lower level information represented in posterior regions. This hierarchical organization affords flexible adjustments of action plans based on the context. Computational models suggest that such hierarchical organization in the PFC is achieved through interactions with the basal ganglia (BG) wherein the BG gate relevant contexts into the PFC. Here, we tested this proposal using functional magnetic resonance imaging (fMRI). Participants were scanned while updating working memory (WM) with 2 levels of hierarchical contexts. Consistent with PFC abstraction proposals, higher level context updates involved anterior portions of the PFC (BA 46), whereas lower level context updates involved posterior portions of the PFC (BA 6). Computational models were only partially supported as the BG were sensitive to higher, but not lower level context updates. The posterior parietal cortex (PPC) showed the opposite pattern. Analyses examining changes in functional connectivity confirmed dissociable roles of the anterior PFC–BG during higher level context updates and posterior PFC–PPC during lower level context updates. These results suggest that hierarchical contexts are organized by distinct frontal–striatal and frontal–parietal networks. PMID:22798339

Dopamine Alters the Fidelity of Working Memory Representations according to Attentional Demands

PubMed Central

Fallon, Sean James; Zokaei, Nahid; Norbury, Agnes; Manohar, Sanjay G.; Husain, Masud

2018-01-01

Capacity limitations in working memory (WM) necessitate the need to effectively control its contents. Here, we examined the effect of cabergoline, a dopamine D2 receptor agonist, on WM using a continuous report paradigm that allowed us to assess the fidelity with which items are stored. We assessed recall performance under three different gating conditions: remembering only one item, being cued to remember one target among distractors, and having to remember all items. Cabergoline had differential effects on recall performance according to whether distractors had to be ignored and whether mnemonic resources could be deployed exclusively to the target. Compared with placebo, cabergoline improved mnemonic performance when there were no distractors but significantly reduced performance when distractors were presented in a precue condition. No significant difference in performance was observed under cabergoline when all items had to be remembered. By applying a stochastic model of response selection, we established that the causes of drug-induced changes in performance were due to changes in the precision with which items were stored in WM. However, there was no change in the extent to which distractors were mistaken for targets. Thus, D2 agonism causes changes in the fidelity of mnemonic representations without altering interference between memoranda. PMID:27897674

Reconfigurable Gabor Filter For Fingerprint Recognition Using FPGA Verilog

NASA Astrophysics Data System (ADS)

Rosshidi, H. T.; Hadi, A. R.

2009-06-01

This paper present the implementations of Gabor filter for fingerprint recognition using Verilog HDL. This work demonstrates the application of Gabor Filter technique to enhance the fingerprint image. The incoming signal in form of image pixel will be filter out or convolute by the Gabor filter to define the ridge and valley regions of fingerprint. This is done with the application of a real time convolve based on Field Programmable Gate Array (FPGA) to perform the convolution operation. The main characteristic of the proposed approach are the usage of memory to store the incoming image pixel and the coefficient of the Gabor filter before the convolution matrix take place. The result was the signal convoluted with the Gabor coefficient.

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

NASA Astrophysics Data System (ADS)

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-01

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

34. OUTLET WORKS: GATES ELEVATIONS AND SECTION. Sheet 43, ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

34. OUTLET WORKS: GATES - ELEVATIONS AND SECTION. Sheet 43, August 20, 1938. File no. SA 121/89(?). - Prado Dam, Outlet Works, Santa Ana River near junction of State Highways 71 & 91, Corona, Riverside County, CA

35. OUTLET WORKS: GATE HOIST ASSEMBLY. Sheet 44, August 20, ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

35. OUTLET WORKS: GATE HOIST ASSEMBLY. Sheet 44, August 20, 1938. File no. SA 121/84(?). - Prado Dam, Outlet Works, Santa Ana River near junction of State Highways 71 & 91, Corona, Riverside County, CA

Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch

NASA Astrophysics Data System (ADS)

Mandal, Sumana; Mandal, Dhoumendra; Mandal, Mrinal Kanti; Garai, Sisir Kumar

2017-06-01

An optical data processing and communication system provides enormous potential bandwidth and a very high processing speed, and it can fulfill the demands of the present generation. For an optical computing system, several data processing units that work in the optical domain are essential. Memory elements are undoubtedly essential to storing any information. Optical flip-flops can store one bit of optical information. From these flip-flop registers, counters can be developed. Here, the authors proposed an optical master-slave (MS)-JK flip-flop with the help of two-input and three-input optical NAND gates. Optical NAND gates have been developed using semiconductor optical amplifiers (SOAs). The nonlinear polarization switching property of an SOA has been exploited here, and it acts as a polarization switch in the proposed scheme. A frequency encoding technique is adopted for representing data. A specific frequency of an optical signal represents a binary data bit. This technique of data representation is helpful because frequency is the fundamental property of a signal, and it remains unaltered during reflection, refraction, absorption, etc. throughout the data propagation. The simulated results enhance the admissibility of the scheme.

Parsing recursive sentences with a connectionist model including a neural stack and synaptic gating.

PubMed

Fedor, Anna; Ittzés, Péter; Szathmáry, Eörs

2011-02-21

It is supposed that humans are genetically predisposed to be able to recognize sequences of context-free grammars with centre-embedded recursion while other primates are restricted to the recognition of finite state grammars with tail-recursion. Our aim was to construct a minimalist neural network that is able to parse artificial sentences of both grammars in an efficient way without using the biologically unrealistic backpropagation algorithm. The core of this network is a neural stack-like memory where the push and pop operations are regulated by synaptic gating on the connections between the layers of the stack. The network correctly categorizes novel sentences of both grammars after training. We suggest that the introduction of the neural stack memory will turn out to be substantial for any biological 'hierarchical processor' and the minimalist design of the model suggests a quest for similar, realistic neural architectures. Copyright © 2010 Elsevier Ltd. All rights reserved.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Extraction of sub-gap density of states via capacitance-voltage measurement for the erasing process in a TFT charge-trapping memory

NASA Astrophysics Data System (ADS)

Chiang, Yen-Chang; Hsiao, Yang-Hsuan; Li, Jeng-Ting; Chen, Jen-Sue

2018-02-01

Charge-trapping memories (CTMs) based on zinc tin oxide (ZTO) semiconductor thin-film transistors (TFTs) can be programmed by a positive gate voltage and erased by a negative gate voltage in conjunction with light illumination. To understand the mechanism involved, the sub-gap density of states associated with ionized oxygen vacancies in the ZTO active layer is extracted from optical response capacitance-voltage (C-V) measurements. The corresponding energy states of ionized oxygen vacancies are observed below the conduction band minimum at approximately 0.5-1.0 eV. From a comparison of the fitted oxygen vacancy concentration in the CTM-TFT after the light-bias erasing operation, it is found that the pristine-erased device contains more oxygen vacancies than the program-erased device because the trapped electrons in the programmed device are pulled into the active layer and neutralized by the oxygen vacancies that are present there.

Electric-field-induced magnetic domain writing in a Co wire

NASA Astrophysics Data System (ADS)

Tanaka, Yuki; Hirai, Takamasa; Koyama, Tomohiro; Chiba, Daichi

2018-05-01

We have demonstrated that the local magnetization in a Co microwire can be switched by an application of a gate voltage without using any external magnetic fields. The electric-field-induced reversible ferromagnetic phase transition was used to realize this. An internal stray field from a ferromagnetic gate electrode assisted the local domain reversal in the Co wire. This new concept of electrical domain switching may be useful for dramatically reducing the power consumption of writing information in a magnetic racetrack memory, in which a shift of a magnetic domain by electric current is utilized.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

NASA Astrophysics Data System (ADS)

Maity, H.; Biswas, A.; Bhattacharjee, A. K.; Pal, A.

In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

NASA Astrophysics Data System (ADS)

Choe, Byeong-In; Park, Byung-Gook; Lee, Jong-Ho

2013-06-01

The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

PubMed

Liu, Chunsen; Yan, Xiao; Wang, Jianlu; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-05-01

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe 2 and a 3D Al 2 O 3 /HfO 2 /Al 2 O 3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe 2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Copper atomic-scale transistors

PubMed Central

Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors. PMID:28382242

Light programmable organic transistor memory device based on hybrid dielectric

NASA Astrophysics Data System (ADS)

Ren, Xiaochen; Chan, Paddy K. L.

2013-09-01

We have fabricated the transistor memory devices based on SiO2 and polystyrene (PS) hybrid dielectric. The trap states densities with different semiconductors have been investigated and a maximum 160V memory window between programming and erasing is realized. For DNTT based transistor, the trapped electron density is limited by the number of mobile electrons in semiconductor. The charge transport mechanism is verified by light induced Vth shift effect. Furthermore, in order to meet the low operating power requirement of portable electronic devices, we fabricated the organic memory transistor based on AlOx/self-assembly monolayer (SAM)/PS hybrid dielectric, the effective capacitance of hybrid dielectric is 210 nF cm-2 and the transistor can reach saturation state at -3V gate bias. The memory window in transfer I-V curve is around 1V under +/-5V programming and erasing bias.

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy.

PubMed

Jaiswal, Akhilesh; Agrawal, Amogh; Roy, Kaushik

2018-04-10

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

NASA Astrophysics Data System (ADS)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Electronics. Module 3: Digital Logic Application. Instructor's Guide.

ERIC Educational Resources Information Center

Carter, Ed; Murphy, Mark

This guide contains instructor's materials for a 10-unit secondary school course on digital logic application. The units are introduction to digital, logic gates, digital integrated circuits, combination logic, flip-flops, counters and shift registers, encoders and decoders, arithmetic circuits, memory, and analog/digital and digital/analog…

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

NASA Astrophysics Data System (ADS)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage shift of 5.0 V has been achieved. For comparison purposes, metal nanocrystals have also been investigated by utilizing both of the physical deposition methods as mentioned above. Silver (Ag) nanocrystals with size of 10--40 nm have been embedded in HfAlO matrix in the trilayer capacitor structure and a flat-band voltage shift of 2.0 V has been achieved.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Reciprocal Interaction of Dendrite Geometry and Nuclear Calcium-VEGFD Signaling Gates Memory Consolidation and Extinction.

PubMed

Hemstedt, Thekla J; Bengtson, C Peter; Ramírez, Omar; Oliveira, Ana M M; Bading, Hilmar

2017-07-19

Nuclear calcium is an important signaling end point in synaptic excitation-transcription coupling that is critical for long-term neuroadaptations. Here, we show that nuclear calcium acting via a target gene, VEGFD, is required for hippocampus-dependent fear memory consolidation and extinction in mice. Nuclear calcium-VEGFD signaling upholds the structural integrity and complexity of the dendritic arbor of CA1 neurons that renders those cells permissive for the efficient generation of synaptic input-evoked nuclear calcium transients driving the expression of plasticity-related genes. Therefore, the gating of memory functions rests on the reciprocally reinforcing maintenance of an intact dendrite geometry and a functional synapse-to-nucleus communication axis. In psychiatric and neurodegenerative disorders, therapeutic application of VEGFD may help to stabilize dendritic structures and network connectivity, which may prevent cognitive decline and could boost the efficacy of extinction-based exposure therapies. SIGNIFICANCE STATEMENT This study uncovers a reciprocal relationship between dendrite geometry, the ability to generate nuclear calcium transients in response to synaptic inputs, and the subsequent induction of expression of plasticity-related and dendritic structure-preserving genes. Insufficient nuclear calcium signaling in CA1 hippocampal neurons and, consequently, reduced expression of the nuclear calcium target gene VEGFD, a dendrite maintenance factor, leads to reduced-complexity basal dendrites of CA1 neurons, which severely compromises the animals' consolidation of both memory and extinction memory. The structure-protective function of VEGFD may prove beneficial in psychiatric disorders as well as neurodegenerative and aging-related conditions that are associated with loss of neuronal structures, dysfunctional excitation-transcription coupling, and cognitive decline. Copyright © 2017 the authors 0270-6474/17/376946-10$15.00/0.

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Hybrid quantum logic and a test of Bell's inequality using two different atomic isotopes.

PubMed

Ballance, C J; Schäfer, V M; Home, J P; Szwer, D J; Webster, S C; Allcock, D T C; Linke, N M; Harty, T P; Aude Craik, D P L; Stacey, D N; Steane, A M; Lucas, D M

2015-12-17

Entanglement is one of the most fundamental properties of quantum mechanics, and is the key resource for quantum information processing (QIP). Bipartite entangled states of identical particles have been generated and studied in several experiments, and post-selected or heralded entangled states involving pairs of photons, single photons and single atoms, or different nuclei in the solid state, have also been produced. Here we use a deterministic quantum logic gate to generate a 'hybrid' entangled state of two trapped-ion qubits held in different isotopes of calcium, perform full tomography of the state produced, and make a test of Bell's inequality with non-identical atoms. We use a laser-driven two-qubit gate, whose mechanism is insensitive to the qubits' energy splittings, to produce a maximally entangled state of one (40)Ca(+) qubit and one (43)Ca(+) qubit, held 3.5 micrometres apart in the same ion trap, with 99.8 ± 0.6 per cent fidelity. We test the CHSH (Clauser-Horne-Shimony-Holt) version of Bell's inequality for this novel entangled state and find that it is violated by 15 standard deviations; in this test, we close the detection loophole but not the locality loophole. Mixed-species quantum logic is a powerful technique for the construction of a quantum computer based on trapped ions, as it allows protection of memory qubits while other qubits undergo logic operations or are used as photonic interfaces to other processing units. The entangling gate mechanism used here can also be applied to qubits stored in different atomic elements; this would allow both memory and logic gate errors caused by photon scattering to be reduced below the levels required for fault-tolerant quantum error correction, which is an essential prerequisite for general-purpose quantum computing.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, G. M.; Yui, C. C.; Carmichael, C.; Koga, R.; George, J. S.

2003-01-01

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

3D memory: etch is the new litho

NASA Astrophysics Data System (ADS)

Petti, Christopher

2018-03-01

This paper discusses the process challenges and limitations for 3D NAND processes, focusing on vertical 3D architectures. The effect of deep memory hole etches on die cost is calculated, with die cost showing a minimum at a given number of layers because of aspect-ratio dependent etch effects. Techniques to mitigate these etch effects are summarized, as are other etch issues, such as bowing and twisting. Metal replacement gate processes and their challenges are also described. Lastly, future directions of vertical 3D NAND technologies are explored.

Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Supinski, B.; Caliga, D.

2017-09-28

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

NASA Astrophysics Data System (ADS)

Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

2017-08-01

A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

The Exclusive Induction of Extinction Is Gated by BDNF

ERIC Educational Resources Information Center

Kirtley, Anne; Thomas, Kerrie L.

2010-01-01

We have previously reported that the reconsolidation and extinction of hippocampal-dependent contextual fear memory can be initiated by a single context conditioned stimulus (CS) presentation of either short or long duration, and that both processes require protein synthesis in this brain region. Furthermore, reconsolidation depends on Zif268…

DefenseLink Feature: Travels with Gates

Science.gov Websites

| Photos Gates Seeks to Build on Positive Momentum in Iraq Defense Secretary Robert Gates meets with local build on recent momentum. Story Commanders Urge Vigilance, Say Strategy Working Field commanders

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

Ionic liquid versus SiO 2 gated a-IGZO thin film transistors: A direct comparison

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2015-08-12

Here, ionic liquid gated field effect transistors have been extensively studied due to their low operation voltage, ease of processing and the realization of high electric fields at low bias voltages. Here, we report ionic liquid (IL) gated thin film transistors (TFTs) based on amorphous Indium Gallium Zinc Oxide (a-IGZO) active layers and directly compare the characteristics with a standard SiO 2 gated device. The transport measurements of the top IL gated device revealed the n-channel property of the IGZO thin film with a current ON/OFF ratio ~10 5, a promising field effect mobility of 14.20 cm 2V –1s –1,more » and a threshold voltage of 0.5 V. Comparable measurements on the bottom SiO2 gate insulator revealed a current ON/OFF ratio >108, a field effect mobility of 13.89 cm 2V –1s –1 and a threshold voltage of 2.5 V. Furthermore, temperature-dependent measurements revealed that the ionic liquid electric double layer can be “frozen-in” by cooling below the glass transition temperature with an applied electrical bias. Positive and negative freezing bias locks-in the IGZO TFT “ON” and “OFF” state, respectively, which could lead to new switching and possibly non-volatile memory applications.« less

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET.

PubMed

Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Wang, Qianqiong

2017-09-06

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool-Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding "1". The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading "1" to reading "0" (10 7 ) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2017-08-01

This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson's equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Gating Out Misinformation: Can Young Children Follow Instructions to Ignore False Information?

PubMed

Schaaf, Jennifer M; Bederian-Gardner, Daniel; Goodman, Gail S

2015-08-01

The current study investigated the effects of misinformation on children's memory reports after practice with the logic-of-opposition instruction at time of test. Four- and 6-year-old children participated in a play event in Session 1. During a two-week delay, parents presented their children with either misinformation or correct information about the play event. Prior to a memory interview in Session 2, some misled children were given a developmentally appropriate logic-of-opposition instruction to not report information provided by their parents. Results indicated that children were misled by the incorrect information, but that the logic-of-opposition instruction aided in the children's retrieval of the original memory, particularly for the 6-year-olds. Implications of the results for memory malleability and social demand effects in children are discussed. Copyright © 2015 John Wiley & Sons, Ltd.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Hysteresis free negative total gate capacitance in junctionless transistors

NASA Astrophysics Data System (ADS)

Gupta, Manish; Kranti, Abhinav

2017-09-01

In this work, we report on the hysteresis free impact ionization induced off-to-on transition while preserving sub-60 mV/decade Subthreshold swing (S-swing) using asymmetric mode operation in double gate silicon (Si) and germanium (Ge) junctionless (JL) transistor. It is shown that sub-60 mV/decade steep switching due to impact ionization implies a negative value of the total gate capacitance. The performance of asymmetric gate JL transistor is compared with symmetric gate operation of JL device, and the condition for hysteresis free current transition with a sub-60 mV/decade switching is analyzed through the product of current density (J) and electric field (E). It is shown that asymmetric gate operation limits the degree of impact ionization inherent in the semiconductor film to levels sufficient for negative total gate capacitance but lower than that required for the occurrence of hysteresis. The work highlights new viewpoints related to the suppression of hysteresis associated with steep switching JL transistors while maintaining S-swing within the range 6-15 mV/decade leading to the negative value of total gate capacitance.

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

p - n Junction Dynamics Induced in a Graphene Channel by Ferroelectric-Domain Motion in the Substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kurchak, Anatolii I.; Eliseev, Eugene A.; Kalinin, Sergei V.

The p - n junction dynamics induced in a graphene channel by stripe-domain nucleation, motion, and reversal in a ferroelectric substrate is explored using a self-consistent approach based on Landau-Ginzburg-Devonshire phenomenology combined with classical electrostatics. Relatively low gate voltages are required to induce the hysteresis of ferroelectric polarization and graphene charge in response to the periodic gate voltage. Pronounced nonlinear hysteresis of graphene conductance with a wide memory window corresponds to high amplitudes of gate voltage. Also, we reveal the extrinsic size effect in the dependence of the graphene-channel conductivity on its length. We predict that the top-gate–dielectric-layer–graphene-channel–ferroelectric-substrate nanostructure consideredmore » here can be a promising candidate for the fabrication of the next generation of modulators and rectifiers based on the graphene p - n junctions.« less

Ferroelectric control of a Mott insulator

PubMed Central

Yamada, Hiroyuki; Marinova, Maya; Altuntas, Philippe; Crassous, Arnaud; Bégon-Lours, Laura; Fusil, Stéphane; Jacquet, Eric; Garcia, Vincent; Bouzehouane, Karim; Gloter, Alexandre; Villegas, Javier E.; Barthélémy, Agnès; Bibes, Manuel

2013-01-01

The electric field control of functional properties is an important goal in oxide-based electronics. To endow devices with memory, ferroelectric gating is interesting, but usually weak compared to volatile electrolyte gating. Here, we report a very large ferroelectric field-effect in perovskite heterostructures combining the Mott insulator CaMnO3 and the ferroelectric BiFeO3 in its “supertetragonal” phase. Upon polarization reversal of the BiFeO3 gate, the CaMnO3 channel resistance shows a fourfold variation around room temperature, and a tenfold change at ~200 K. This is accompanied by a carrier density modulation exceeding one order of magnitude. We have analyzed the results for various CaMnO3 thicknesses and explain them by the electrostatic doping of the CaMnO3 layer and the presence of a fixed dipole at the CaMnO3/BiFeO3 interface. Our results suggest the relevance of ferroelectric gates to control orbital- or spin-ordered phases, ubiquitous in Mott systems, and pave the way toward efficient Mott-tronics devices. PMID:24089020

A 65k pixel, 150k frames-per-second camera with global gating and micro-lenses suitable for fluorescence lifetime imaging

NASA Astrophysics Data System (ADS)

Burri, Samuel; Powolny, François; Bruschini, Claudio E.; Michalet, Xavier; Regazzoni, Francesco; Charbon, Edoardo

2014-05-01

This paper presents our work on a 65k pixel single-photon avalanche diode (SPAD) based imaging sensor realized in a 0.35μm standard CMOS process. At a resolution of 512 by 128 pixels the sensor is read out in 6.4μs to deliver over 150k monochrome frames per second. The individual pixel has a size of 24μm2 and contains the SPAD with a 12T quenching and gating circuitry along with a memory element. The gating signals are distributed across the chip through a balanced tree to minimize the signal skew between the pixels. The array of pixels is row-addressable and data is sent out of the chip on 128 lines in parallel at a frequency of 80MHz. The system is controlled by an FPGA which generates the gating and readout signals and can be used for arbitrary real-time computation on the frames from the sensor. The communication protocol between the camera and a conventional PC is USB2. The active area of the chip is 5% and can be significantly improved with the application of a micro-lens array. A micro-lens array, for use with collimated light, has been designed and its performance is reviewed in the paper. Among other high-speed phenomena the gating circuitry capable of generating illumination periods shorter than 5ns can be used for Fluorescence Lifetime Imaging (FLIM). In order to measure the lifetime of fluorophores excited by a picosecond laser, the sensor's illumination period is synchronized with the excitation laser pulses. A histogram of the photon arrival times relative to the excitation is then constructed by counting the photons arriving during the sensitive time for several positions of the illumination window. The histogram for each pixel is transferred afterwards to a computer where software routines extract the lifetime at each location with an accuracy better than 100ps. We show results for fluorescence lifetime measurements using different fluorophores with lifetimes ranging from 150ps to 5ns.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

NASA Astrophysics Data System (ADS)

Condori Quispe, Hugo O.; Encomendero-Risco, Jimy J.; Xing, Huili Grace; Sensale-Rodriguez, Berardi

2016-08-01

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Terahertz amplification in RTD-gated HEMTs with a grating-gate wave coupling topology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Condori Quispe, Hugo O.; Sensale-Rodriguez, Berardi; Encomendero-Risco, Jimy J.

2016-08-08

We theoretically analyze the operation of a terahertz amplifier consisting of a resonant-tunneling-diode gated high-electron-mobility transistor (RTD-gated HEMT) in a grating-gate topology. In these devices, the key element enabling substantial power gain is the efficient coupling of terahertz waves into and out of plasmons in the RTD-gated HEMT channel, i.e., the gain medium, via the grating-gate itself, part of the active device, rather than by an external antenna structure as discussed in previous works, therefore potentially enabling terahertz amplification with associated power gains >40 dB.

Sleep extension normalizes ERP of waking auditory sensory gating in healthy habitually short sleeping individuals.

PubMed

Gumenyuk, Valentina; Korzyukov, Oleg; Roth, Thomas; Bowyer, Susan M; Drake, Christopher L

2013-01-01

Chronic sleep loss has been associated with increased daytime sleepiness, as well as impairments in memory and attentional processes. In the present study, we evaluated the neuronal changes of a pre-attentive process of wake auditory sensory gating, measured by brain event-related potential (ERP)--P50 in eight normal sleepers (NS) (habitual total sleep time (TST) 7 h 32 m) vs. eight chronic short sleeping individuals (SS) (habitual TST ≤6 h). To evaluate the effect of sleep extension on sensory gating, the extended sleep condition was performed in chronic short sleeping individuals. Thus, one week of time in bed (6 h 11 m) corresponding to habitual short sleep (hSS), and one week of extended time (∼ 8 h 25 m) in bed corresponding to extended sleep (eSS), were counterbalanced in the SS group. The gating ERP assessment was performed on the last day after each sleep condition week (normal sleep and habitual short and extended sleep), and was separated by one week with habitual total sleep time and monitored by a sleep diary. We found that amplitude of gating was lower in SS group compared to that in NS group (0.3 µV vs. 1.2 µV, at Cz electrode respectively). The results of the group × laterality interaction showed that the reduction of gating amplitude in the SS group was due to lower amplitude over the left hemisphere and central-midline sites relative to that in the NS group. After sleep extension the amplitude of gating increased in chronic short sleeping individuals relative to their habitual short sleep condition. The sleep condition × frontality interaction analysis confirmed that sleep extension significantly increased the amplitude of gating over frontal and central brain areas compared to parietal brain areas.

Reliability study of refractory gate gallium arsenide MESFETS

NASA Technical Reports Server (NTRS)

Yin, J. C. W.; Portnoy, W. M.

1981-01-01

Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

Reliability study of refractory gate gallium arsenide MESFETS

NASA Astrophysics Data System (ADS)

Yin, J. C. W.; Portnoy, W. M.

Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

Occipital Alpha Activity during Stimulus Processing Gates the Information Flow to Object-Selective Cortex

PubMed Central

Zumer, Johanna M.; Scheeringa, René; Schoffelen, Jan-Mathijs; Norris, David G.; Jensen, Ole

2014-01-01

Given the limited processing capabilities of the sensory system, it is essential that attended information is gated to downstream areas, whereas unattended information is blocked. While it has been proposed that alpha band (8–13 Hz) activity serves to route information to downstream regions by inhibiting neuronal processing in task-irrelevant regions, this hypothesis remains untested. Here we investigate how neuronal oscillations detected by electroencephalography in visual areas during working memory encoding serve to gate information reflected in the simultaneously recorded blood-oxygenation-level-dependent (BOLD) signals recorded by functional magnetic resonance imaging in downstream ventral regions. We used a paradigm in which 16 participants were presented with faces and landscapes in the right and left hemifields; one hemifield was attended and the other unattended. We observed that decreased alpha power contralateral to the attended object predicted the BOLD signal representing the attended object in ventral object-selective regions. Furthermore, increased alpha power ipsilateral to the attended object predicted a decrease in the BOLD signal representing the unattended object. We also found that the BOLD signal in the dorsal attention network inversely correlated with visual alpha power. This is the first demonstration, to our knowledge, that oscillations in the alpha band are implicated in the gating of information from the visual cortex to the ventral stream, as reflected in the representationally specific BOLD signal. This link of sensory alpha to downstream activity provides a neurophysiological substrate for the mechanism of selective attention during stimulus processing, which not only boosts the attended information but also suppresses distraction. Although previous studies have shown a relation between the BOLD signal from the dorsal attention network and the alpha band at rest, we demonstrate such a relation during a visuospatial task, indicating that the dorsal attention network exercises top-down control of visual alpha activity. PMID:25333286

Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Circadian modulation of short-term memory in Drosophila.

PubMed

Lyons, Lisa C; Roman, Gregg

2009-01-01

Endogenous biological clocks are widespread regulators of behavior and physiology, allowing for a more efficient allocation of efforts and resources over the course of a day. The extent that different processes are regulated by circadian oscillators, however, is not fully understood. We investigated the role of the circadian clock on short-term associative memory formation using a negatively reinforced olfactory-learning paradigm in Drosophila melanogaster. We found that memory formation was regulated in a circadian manner. The peak performance in short-term memory (STM) occurred during the early subjective night with a twofold performance amplitude after a single pairing of conditioned and unconditioned stimuli. This rhythm in memory is eliminated in both timeless and period mutants and is absent during constant light conditions. Circadian gating of sensory perception does not appear to underlie the rhythm in short-term memory as evidenced by the nonrhythmic shock avoidance and olfactory avoidance behaviors. Moreover, central brain oscillators appear to be responsible for the modulation as cryptochrome mutants, in which the antennal circadian oscillators are nonfunctional, demonstrate robust circadian rhythms in short-term memory. Together these data suggest that central, rather than peripheral, circadian oscillators modulate the formation of short-term associative memory and not the perception of the stimuli.

Electrophysiology of pumpkin seeds: Memristors in vivo.

PubMed

Volkov, Alexander G; Nyasani, Eunice K; Tuckett, Clayton; Greeman, Esther A; Markin, Vladislav S

2016-01-01

Leon Chua, the discoverer of a memristor, theoretically predicted that voltage gated ion channels can be memristors. We recently found memristors in different plants such as the Venus flytrap, Mimosa pudica, Aloe vera, apple fruits, and in potato tubers. There are no publications in literature about the existence of memristors in seeds. The goal of this work was to discover if pumpkin seeds might have memristors. We selected Cucurbita pepo L., cv. Cinderella, Cucurbita maxima L. cv Warty Goblin, and Cucurbita maxima L., cv. Jarrahdale seeds for this analysis. In these seeds, we found the presence of resistors with memory. The analysis was based on cyclic voltammetry where a memristor should manifest itself as a nonlinear two-terminal electrical element, which exhibits a pinched hysteresis loop on a current-voltage plane for any bipolar cyclic voltage input signal. Dry dormant pumpkin seeds have very high electrical resistance without memristive properties. The electrostimulation by bipolar sinusoidal or triangular periodic waves induces electrical responses in imbibed pumpkin seeds with fingerprints of memristors. Tetraethylammonium chloride, an inhibitor of voltage gated K(+) channels, transforms a memristor to a resistor in pumpkin seeds. NPPB (5-Nitro-2-(3-phenylpropylamino)benzoic acid) inhibits the memristive properties of imbibed pumpkin seeds. The discovery of memristors in pumpkin seeds creates a new direction in the understanding of electrophysiological phenomena in seeds.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

A single-atom quantum memory in silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Freer, Solomon; Simmons, Stephanie; Laucht, Arne

Long coherence times and fast gate operations are desirable but often conflicting requirements for physical qubits. This conflict can be resolved by resorting to fast qubits for operations, and by storing their state in a ‘quantum memory’ while idle. The 31P donor in silicon comes naturally equipped with a fast qubit (the electron spin) and a long-lived qubit (the 31P nuclear spin), coexisting in a bound state at cryogenic temperatures. Here, we demonstrate storage and retrieval of quantum information from a single donor electron spin to its host phosphorus nucleus in isotopically-enriched 28Si. The fidelity of the memory process ismore » characterised via both state and process tomography. We report an overall process fidelity Fp ! 81%, a memory fidelity Fm ! 92%, and memory storage times up to 80 ms. These values are limited by a transient shift of the electron spin resonance frequency following highpower radiofrequency pulses.« less

A single-atom quantum memory in silicon

DOE PAGES

Freer, Solomon; Simmons, Stephanie; Laucht, Arne; ...

2017-03-20

Long coherence times and fast gate operations are desirable but often conflicting requirements for physical qubits. This conflict can be resolved by resorting to fast qubits for operations, and by storing their state in a ‘quantum memory’ while idle. The 31P donor in silicon comes naturally equipped with a fast qubit (the electron spin) and a long-lived qubit (the 31P nuclear spin), coexisting in a bound state at cryogenic temperatures. Here, we demonstrate storage and retrieval of quantum information from a single donor electron spin to its host phosphorus nucleus in isotopically-enriched 28Si. The fidelity of the memory process ismore » characterised via both state and process tomography. We report an overall process fidelity Fp ! 81%, a memory fidelity Fm ! 92%, and memory storage times up to 80 ms. These values are limited by a transient shift of the electron spin resonance frequency following highpower radiofrequency pulses.« less

Memcomputing with membrane memcapacitive systems

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Traversa, F. L.; Di Ventra, M.

2015-06-01

We show theoretically that networks of membrane memcapacitive systems—capacitors with memory made out of membrane materials—can be used to perform a complete set of logic gates in a massively parallel way by simply changing the external input amplitudes, but not the topology of the network. This polymorphism is an important characteristic of memcomputing (computing with memories) that closely reproduces one of the main features of the brain. A practical realization of these membrane memcapacitive systems, using, e.g., graphene or other 2D materials, would be a step forward towards a solid-state realization of memcomputing with passive devices.

Top-Down Control of Visual Alpha Oscillations: Sources of Control Signals and Their Mechanisms of Action

PubMed Central

Wang, Chao; Rajagovindan, Rajasimhan; Han, Sahng-Min; Ding, Mingzhou

2016-01-01

Alpha oscillations (8–12 Hz) are thought to inversely correlate with cortical excitability. Goal-oriented modulation of alpha has been studied extensively. In visual spatial attention, alpha over the region of visual cortex corresponding to the attended location decreases, signifying increased excitability to facilitate the processing of impending stimuli. In contrast, in retention of verbal working memory, alpha over visual cortex increases, signifying decreased excitability to gate out stimulus input to protect the information held online from sensory interference. According to the prevailing model, this goal-oriented biasing of sensory cortex is effected by top-down control signals from frontal and parietal cortices. The present study tests and substantiates this hypothesis by (a) identifying the signals that mediate the top-down biasing influence, (b) examining whether the cortical areas issuing these signals are task-specific or task-independent, and (c) establishing the possible mechanism of the biasing action. High-density human EEG data were recorded in two experimental paradigms: a trial-by-trial cued visual spatial attention task and a modified Sternberg working memory task. Applying Granger causality to both sensor-level and source-level data we report the following findings. In covert visual spatial attention, the regions exerting top-down control over visual activity are lateralized to the right hemisphere, with the dipoles located at the right frontal eye field (FEF) and the right inferior frontal gyrus (IFG) being the main sources of top-down influences. During retention of verbal working memory, the regions exerting top-down control over visual activity are lateralized to the left hemisphere, with the dipoles located at the left middle frontal gyrus (MFG) being the main source of top-down influences. In both experiments, top-down influences are mediated by alpha oscillations, and the biasing effect is likely achieved via an inhibition-disinhibition mechanism. PMID:26834601

SOVEREIGN: An autonomous neural system for incrementally learning planned action sequences to navigate towards a rewarded goal.

PubMed

Gnadt, William; Grossberg, Stephen

2008-06-01

How do reactive and planned behaviors interact in real time? How are sequences of such behaviors released at appropriate times during autonomous navigation to realize valued goals? Controllers for both animals and mobile robots, or animats, need reactive mechanisms for exploration, and learned plans to reach goal objects once an environment becomes familiar. The SOVEREIGN (Self-Organizing, Vision, Expectation, Recognition, Emotion, Intelligent, Goal-oriented Navigation) animat model embodies these capabilities, and is tested in a 3D virtual reality environment. SOVEREIGN includes several interacting subsystems which model complementary properties of cortical What and Where processing streams and which clarify similarities between mechanisms for navigation and arm movement control. As the animat explores an environment, visual inputs are processed by networks that are sensitive to visual form and motion in the What and Where streams, respectively. Position-invariant and size-invariant recognition categories are learned by real-time incremental learning in the What stream. Estimates of target position relative to the animat are computed in the Where stream, and can activate approach movements toward the target. Motion cues from animat locomotion can elicit head-orienting movements to bring a new target into view. Approach and orienting movements are alternately performed during animat navigation. Cumulative estimates of each movement are derived from interacting proprioceptive and visual cues. Movement sequences are stored within a motor working memory. Sequences of visual categories are stored in a sensory working memory. These working memories trigger learning of sensory and motor sequence categories, or plans, which together control planned movements. Predictively effective chunk combinations are selectively enhanced via reinforcement learning when the animat is rewarded. Selected planning chunks effect a gradual transition from variable reactive exploratory movements to efficient goal-oriented planned movement sequences. Volitional signals gate interactions between model subsystems and the release of overt behaviors. The model can control different motor sequences under different motivational states and learns more efficient sequences to rewarded goals as exploration proceeds.

Operation mode switchable charge-trap memory based on few-layer MoS2

NASA Astrophysics Data System (ADS)

Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-03-01

Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

NASA Astrophysics Data System (ADS)

Liu, Anjun; Wang, Jing; Lu, Jian-Yu

2002-05-01

Recently, a method has been developed for high frame rate medical imaging [Jian-yu Lu, ``2D and 3D high frame rate imaging with limited diffraction beams,'' IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839-856 (1997)]. To realize this method, a complicated system [multiple-channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12-bit resolution, time-variable-gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto-refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.

Remote hardware-reconfigurable robotic camera

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

[Voltage-gated potassium channels and human neurological diseases].

PubMed

Jin, Hong-Wei; Wang, Xiao-Liang

2002-01-01

Voltage-gated potassium channels (Kv) is the largest, most complex in potassium channel superfamily. It can be divided into Kv alpha subunit and auxiliary two groups. The roles of some Kv channels types, e.g. rapidly inactivating (A-Type channel) and muscarine sensitive channels (M-type channel) are beginning to be understood. They are prominent in nervous system, acting in delicate and accurate ways to control or modify many physiological and pathological functions including membrane excitability, neurotransmitter release, cell proliferation or degeneration, signal transduction in neuronal network. Many human neurological disease pathogenesis are found to be related to mutant of Kv-channels subunit or subtype, such as, learning and memory impairing, ataxia, epilepsy, deafness, etc.

Is the Link from Working Memory to Analogy Causal? No Analogy Improvements following Working Memory Training Gains

PubMed Central

Richey, J. Elizabeth; Phillips, Jeffrey S.; Schunn, Christian D.; Schneider, Walter

2014-01-01

Analogical reasoning has been hypothesized to critically depend upon working memory through correlational data [1], but less work has tested this relationship through experimental manipulation [2]. An opportunity for examining the connection between working memory and analogical reasoning has emerged from the growing, although somewhat controversial, body of literature suggests complex working memory training can sometimes lead to working memory improvements that transfer to novel working memory tasks. This study investigated whether working memory improvements, if replicated, would increase analogical reasoning ability. We assessed participants’ performance on verbal and visual analogy tasks after a complex working memory training program incorporating verbal and spatial tasks [3], [4]. Participants’ improvements on the working memory training tasks transferred to other short-term and working memory tasks, supporting the possibility of broad effects of working memory training. However, we found no effects on analogical reasoning. We propose several possible explanations for the lack of an impact of working memory improvements on analogical reasoning. PMID:25188356

Fast quantum logic gates with trapped-ion qubits

NASA Astrophysics Data System (ADS)

Schäfer, V. M.; Ballance, C. J.; Thirumalai, K.; Stephenson, L. J.; Ballance, T. G.; Steane, A. M.; Lucas, D. M.

2018-03-01

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural ‘speed limit’ of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds—less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually associated with solid-state devices.

Fast quantum logic gates with trapped-ion qubits.

PubMed

Schäfer, V M; Ballance, C J; Thirumalai, K; Stephenson, L J; Ballance, T G; Steane, A M; Lucas, D M

2018-02-28

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural 'speed limit' of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds-less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually associated with solid-state devices.

High voltage and current, gate assisted, turn-off thyristor development

NASA Technical Reports Server (NTRS)

Nowalk, T. P.; Brewster, J. B.; Kao, Y. C.

1972-01-01

An improved high speed power switch with unique turn-off capability was developed. This gate assisted turn-off thyristor (GATT) was rated 1000 volts and 100 amperes with turn-off times of 2 microseconds. Fifty units were delivered for evaluation. In addition, test circuits designed to relate to the series inverter application were built and demonstrated. In the course of this work it was determined that the basic device design is adequate to meet the static characteristics and dynamic turn-off specification. It was further determined that the turn-on specification is critically dependent on the gate drive circuit due to the distributive nature of the cathode-gate geometry. Future work should emphasize design modifications which reduce the gate current required for fast turn-on, thereby opening the way to higher power (current) devices.

Happiness increases verbal and spatial working memory capacity where sadness does not: Emotion, working memory and executive control.

PubMed

Storbeck, Justin; Maswood, Raeya

2016-08-01

The effects of emotion on working memory and executive control are often studied in isolation. Positive mood enhances verbal and impairs spatial working memory, whereas negative mood enhances spatial and impairs verbal working memory. Moreover, positive mood enhances executive control, whereas negative mood has little influence. We examined how emotion influences verbal and spatial working memory capacity, which requires executive control to coordinate between holding information in working memory and completing a secondary task. We predicted that positive mood would improve both verbal and spatial working memory capacity because of its influence on executive control. Positive, negative and neutral moods were induced followed by completing a verbal (Experiment 1) or spatial (Experiment 2) working memory operation span task to assess working memory capacity. Positive mood enhanced working memory capacity irrespective of the working memory domain, whereas negative mood had no influence on performance. Thus, positive mood was more successful holding information in working memory while processing task-irrelevant information, suggesting that the influence mood has on executive control supersedes the independent effects mood has on domain-specific working memory.

Effect of ancilla's structure on quantum error correction using the seven-qubit Calderbank-Shor-Steane code

NASA Astrophysics Data System (ADS)

Salas, P. J.; Sanz, A. L.

2004-05-01

In this work we discuss the ability of different types of ancillas to control the decoherence of a qubit interacting with an environment. The error is introduced into the numerical simulation via a depolarizing isotropic channel. The ranges of values considered are 10-4 ⩽ɛ⩽ 10-2 for memory errors and 3× 10-5 ⩽γ/7⩽ 10-2 for gate errors. After the correction we calculate the fidelity as a quality criterion for the qubit recovered. We observe that a recovery method with a three-qubit ancilla provides reasonably good results bearing in mind its economy. If we want to go further, we have to use fault tolerant ancillas with a high degree of parallelism, even if this condition implies introducing additional ancilla verification qubits.

Fidelity of Majorana-based quantum operations

NASA Astrophysics Data System (ADS)

Tanhayi Ahari, Mostafa; Ortiz, Gerardo; Seradjeh, Babak

2015-03-01

It is well known that one-dimensional p-wave superconductor, the so-called Kitaev model, has topologically distinct phases that are distinguished by the presence of Majorana fermions. Owing to their topological protection, these Majorana fermions have emerged as candidates for fault-tolerant quantum computation. They furnish the operation of such a computation via processes that produce, braid, and annihilate them in pairs. In this work we study some of these processes from the dynamical perspective. In particular, we determine the fidelity of the Majorana fermions when they are produced or annihilated by tuning the system through the corresponding topological phase transition. For a simple linear protocol, we derive analytical expressions for fidelity and test various perturbative schemes. For more general protocols, we present exact numerics. Our results are relevant for the operation of Majorana-based quantum gates and quantum memories.

Controllable transport of a skyrmion in a ferromagnetic narrow channel with voltage-controlled magnetic anisotropy

NASA Astrophysics Data System (ADS)

Wang, Junlin; Xia, Jing; Zhang, Xichao; Zhao, G. P.; Ye, Lei; Wu, Jing; Xu, Yongbing; Zhao, Weisheng; Zou, Zhigang; Zhou, Yan

2018-05-01

Magnetic skyrmions have potential applications in next-generation spintronic devices with ultralow energy consumption. In this work, the current-driven skyrmion motion in a narrow ferromagnetic nanotrack with voltage-controlled magnetic anisotropy (VCMA) is studied numerically. By utilizing the VCMA effect, the transport of skyrmion can be unidirectional in the nanotrack, leading to a one-way information channel. The trajectory of the skyrmion can also be modulated by periodically located VCMA gates, which protects the skyrmion from destruction by touching the track edge. In addition, the location of the skyrmion can be controlled by adjusting the driving pulse length in the presence of the VCMA effect. Our results provide guidelines for practical realization of the skyrmion-based information channel, diode, and skyrmion-based electronic devices such as racetrack memory.

Novel organic semiconductors and a high capacitance gate dielectric for organic thin film transistors

NASA Astrophysics Data System (ADS)

Cai, Xiuyu

2007-12-01

Organic semiconductors are attracting more and more interest as a promising set of materials in the field of electronics research. This thesis focused on several new organic semiconductors and a novel high-kappa dielectric thin film (SrTiO3), which are two essential parts in Organic Thin Film Transistors (OTFTs). Structure and morphology of thin films of tricyanovinyl capped oligothiophenes were studied using atomic force microscopy and x-ray diffraction. Thin film transistors of one compound exhibited a reasonable electron mobility of 0.02 cm2/Vs. Temperature dependent measurements on the thin film transistor based on this compound revealed shallow trap states that were interpreted in terms of a multiple trap and release model. Moreover, inversion of the majority charge carrier type from electrons to holes was observed when the number of oligothiophene rings increased to six and ambipolar transport behavior was observed for tricyanovinyl sexithiophene. Another interesting organic semiconductor compound is the fluoalkylquarterthiophene, which showed ambipolar transport and large hysteresis in the transfer curve. Due to the bistable state at floating gate, the thin film transistor was exploited to study non-volatile floating gate memory effects. The temperature dependence of the retention time for this memory device revealed that the electron trapping was an activated process. Following the earlier work on hybrid acene-thiophene organic semiconductors, new compounds with similar structure were studied to reveal the mechanism of the air-stability exhibited by some compounds. They all formed highly crystalline thin films and showed reasonable device performances which are well correlated with the molecular structures, thin film microstructures, and solid state packing. The most air-stable compound had no observable degradation with exposure to air for 15 months. SrTiO3 was developed to be employed in OTFTs. Optimization of thin film growth was performed using reactive sputtering growth. Excellent SrTiO3 epitaixal thin film growth was revealed on conductive SrTiO 3:Nb substrates. A maximum charge carrier density of 1014 cm-2 was obtained based on pentacene and perylene diimide thin film transistors. Some new physical phenomena, such as step-like transfer characteristic curve and negative transconductance, were observed at such high field effect induced charge carrier density.

Sensory Cortical Plasticity Participates in the Epigenetic Regulation of Robust Memory Formation

PubMed Central

Phan, Mimi L.; Bieszczad, Kasia M.

2016-01-01

Neuroplasticity remodels sensory cortex across the lifespan. A function of adult sensory cortical plasticity may be capturing available information during perception for memory formation. The degree of experience-dependent remodeling in sensory cortex appears to determine memory strength and specificity for important sensory signals. A key open question is how plasticity is engaged to induce different degrees of sensory cortical remodeling. Neural plasticity for long-term memory requires the expression of genes underlying stable changes in neuronal function, structure, connectivity, and, ultimately, behavior. Lasting changes in transcriptional activity may depend on epigenetic mechanisms; some of the best studied in behavioral neuroscience are DNA methylation and histone acetylation and deacetylation, which, respectively, promote and repress gene expression. One purpose of this review is to propose epigenetic regulation of sensory cortical remodeling as a mechanism enabling the transformation of significant information from experiences into content-rich memories of those experiences. Recent evidence suggests how epigenetic mechanisms regulate highly specific reorganization of sensory cortical representations that establish a widespread network for memory. Thus, epigenetic mechanisms could initiate events to establish exceptionally persistent and robust memories at a systems-wide level by engaging sensory cortical plasticity for gating what and how much information becomes encoded. PMID:26881129

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ultrathin strain-gated field effect transistor based on In-doped ZnO nanobelts

NASA Astrophysics Data System (ADS)

Zhang, Zheng; Du, Junli; Li, Bing; Zhang, Shuhao; Hong, Mengyu; Zhang, Xiaomei; Liao, Qingliang; Zhang, Yue

2017-08-01

In this work, we fabricated a strain-gated piezoelectric transistor based on single In-doped ZnO nanobelt with ±(0001) top/bottom polar surfaces. In the vertical structured transistor, the Pt tip of the AFM and Au film are used as source and drain electrode. The electrical transport performance of the transistor is gated by compressive strains. The working mechanism is attributed to the Schottky barrier height changed under the coupling effect of piezoresistive and piezoelectric. Uniquely, the transistor turns off under the compressive stress of 806 nN. The strain-gated transistor is likely to have important applications in high resolution mapping device and MEMS devices.

Joint image and motion reconstruction for PET using a B-spline motion model.

PubMed

Blume, Moritz; Navab, Nassir; Rafecas, Magdalena

2012-12-21

We present a novel joint image and motion reconstruction method for PET. The method is based on gated data and reconstructs an image together with a motion function. The motion function can be used to transform the reconstructed image to any of the input gates. All available events (from all gates) are used in the reconstruction. The presented method uses a B-spline motion model, together with a novel motion regularization procedure that does not need a regularization parameter (which is usually extremely difficult to adjust). Several image and motion grid levels are used in order to reduce the reconstruction time. In a simulation study, the presented method is compared to a recently proposed joint reconstruction method. While the presented method provides comparable reconstruction quality, it is much easier to use since no regularization parameter has to be chosen. Furthermore, since the B-spline discretization of the motion function depends on fewer parameters than a displacement field, the presented method is considerably faster and consumes less memory than its counterpart. The method is also applied to clinical data, for which a novel purely data-driven gating approach is presented.

Psychotomimetic effects of different doses of MK-801 and the underlying mechanisms in a selective memory impairment model.

PubMed

Liu, Weiqing; Wang, Dong; Hong, Wenjuan; Yu, Yi; Tang, Jinsong; Wang, Jicai; Liu, Fang; Xu, Xiufeng; Tan, Liwen; Chen, Xiaogang

2017-03-01

Although N-methyl-d-aspartate receptor antagonists-induced hypoglutamate rodent models are the most well-established models for preclinical studies of schizophrenia-related deficits, they also evoke a wide spectrum of psychotomimetic side effects. It is significant to increase the specificity of hypoglutamate rodent models. In this study, the recognition memory was evaluated in rats by object recognition test (ORT), sensorimotor gating was evaluated by prepulse inhibition of the startle reflex (PPI), and locomotor activity was measured using open field test. High-performance liquid chromatography was used to measure neurotransmitters content in the medial prefrontal cortex (mPFC) and thalamus (THA). Total Akt and phospho-Akt protein was measured by Western blots. Results showed that 0.3mg/kg of MK-801 was most effective in inducing locomotion. 0.3mg/kg of MK-801 was most effective in decreasing PPI. 0.03mg/kg of MK-801 was most effective in decreasing object memory while not affecting exploration manners in the training session. 0.03mg/kg of MK-801 significantly increased HVA and Glu content in the mPFC. 0.1mg/kg of MK-801 significantly decreased GABA content in the THA. 0.03mg/kg of MK-801 significantly decreased Akt phosphorylation in the mPFC, which was related to the ORT index. In conclusion, a dose of 0.03mg/kg MK-801 can establish a "pure" memory impairment model without contaminations of sensorimotor gating and locomotor activity. MK-801-induced cognitive deficits is associated with increased DA metabolites and glutamate content in the mPFC and decreased GABA content in the THA as well as decrease in Akt phosphorylation in the mPFC. Copyright © 2016. Published by Elsevier B.V.

A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism

NASA Astrophysics Data System (ADS)

Nigam, Kaushal; Kondekar, Pravin; Sharma, Dheeraj; Raad, Bhagwan Ram

2016-10-01

For the first time, a distinctive approach based on electrically doped concept is used for the formation of novel double gate tunnel field effect transistor (TFET). For this, the initially heavily doped n+ substrate is converted into n+-i-n+-i (Drain-Channel-Source) by the selection of appropriate work functions of control gate (CG) and polarity gate (PG) as 4.7 eV. Further, the formation of p+ region for source is performed by applying -1.2 V at PG. Hence, the structure behave like a n+-i-n+-p+ gated TFET, whereas, the control gate is used to modulate the effective tunneling barrier width. The physical realization of delta doped n+ layer near to source region is a challenging task for improving the device performance in terms of ON current and subthreshold slope. So, the proposed work will provide a better platform for fabrication of n+-i-n+-p+ TFET with low cost and suppressed random dopant fluctuation (RDF) effects. ATLAS TCAD device simulator is used to carry out the simulation work.

A comparison study: image-based vs signal-based retrospective gating on microCT

NASA Astrophysics Data System (ADS)

Liu, Xuan; Salmon, Phil L.; Laperre, Kjell; Sasov, Alexander

2017-09-01

Retrospective gating on animal studies with microCT has gained popularity in recent years. Previously, we use ECG signals for cardiac gating and breathing airflow or video signals of abdominal motion for respiratory gating. This method is adequate and works well for most applications. However, through the years, researchers have noticed some pitfalls in the method. For example, the additional signal acquisition step may increase failure rate in practice. X-Ray image-based gating, on the other hand, does not require any extra step in the scanning. Therefore we investigate imagebased gating techniques. This paper presents a comparison study of the image-based versus signal-based approach to retrospective gating. The two application areas we have studied are respiratory and cardiac imaging for both rats and mice. Image-based respiratory gating on microCT is relatively straightforward and has been done by several other researchers and groups. This method retrieves an intensity curve of a region of interest (ROI) placed in the lung area on all projections. From scans on our systems based on step-and-shoot scanning mode, we confirm that this method is very effective. A detailed comparison between image-based and signal-based gating methods is given. For cardiac gating, breathing motion is not negligible and has to be dealt with. Another difficulty in cardiac gating is the relatively smaller amplitude of cardiac movements comparing to the respirational movements, and the higher heart rate. Higher heart rate requires high speed image acquisition. We have been working on our systems to improve the acquisition speed. A dual gating technique has been developed to achieve adequate cardiac imaging.

Quantum logic gates based on ballistic transport in graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dragoman, Daniela; Academy of Romanian Scientists, Splaiul Independentei 54, 050094 Bucharest; Dragoman, Mircea, E-mail: mircea.dragoman@imt.ro

2016-03-07

The paper presents various configurations for the implementation of graphene-based Hadamard, C-phase, controlled-NOT, and Toffoli gates working at room temperature. These logic gates, essential for any quantum computing algorithm, involve ballistic graphene devices for qubit generation and processing and can be fabricated using existing nanolithographical techniques. All quantum gate configurations are based on the very large mean-free-paths of carriers in graphene at room temperature.

LOGIC NETS, THEIR CHARACTERIZATION, RELIABILITY, AND EFFICIENT SYNTHESIS.

DTIC Science & Technology

The report consists of two parts. The first discusses a problem in the dual-support approach to network synthesis using threshold gates, gives new...asymptotic results on the number of threshold gates and the size of threshold gate networks, and summarizes the work in threshold logic supported by...this contract, including programs to facilitate experimentation in the design of networks of threshold gates. The second summarizes CDL1 - Computer

From Tls Survey to 3d Solid Modeling for Documentation of Built Heritage: the Case Study of Porta Savonarola in Padua

NASA Astrophysics Data System (ADS)

Guarnieri, A.; Fissore, F.; Masiero, A.; Vettore, A.

2017-08-01

It is a matter of fact that 3D visualisation and proper documentation of cultural objects helps to preserve the history and memories of historic buildings, archaeological sites and cultural landscapes, and supports economic growth by stimulating cultural tourism. Preservation, visualisation and recreation of valuable historical and architectural objects and places has always been a serious challenge for specialists in the field. Today, the rapid developments in the fields of close-range photogrammetry, terrestrial laser scanning (TLS) and computer vision (CV) enable to carry out highly accurate 3D models so as to be extremely effective and intuitive for users who have stringent requirements and high expectations. In this note we present the results of the survey and 3D modeling of an ancient gate, Porta Savonarola, located within the remains of the medieval town walls surrounding the historical city center of Padua, Italy. The work has been undertaken within the framework of the project "Walls Multimedia Museum" (WMM) promoted by the local private association "Padua Walls Committee". The goal of the project was to develop a prototype of an "extended" virtual museum, spreaded along most interesting locations of the town walls. The survey of the ancient gate was performed with a Leica C10 and P20 terrestrial laser scanners. Once the acquired scans were properly merged together, a solid model was generated from the global point cloud, and plans and elevations were extracted from it for restoration purposes. A short multimedia video was also created for the "Walls Multimedia Museum", showing both the outer and inner part of the gate. In the paper we will discuss all the steps and challenges addressed to provide the 3D solid model of Porta Savonarola from the TLS data.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could enable complex neuromorphic learning and the study of the physics of defect kinetics in two-dimensional materials.

All-optical switch and transistor gated by one stored photon.

PubMed

Chen, Wenlan; Beck, Kristin M; Bücker, Robert; Gullans, Michael; Lukin, Mikhail D; Tanji-Suzuki, Haruka; Vuletić, Vladan

2013-08-16

The realization of an all-optical transistor, in which one "gate" photon controls a "source" light beam, is a long-standing goal in optics. By stopping a light pulse in an atomic ensemble contained inside an optical resonator, we realized a device in which one stored gate photon controls the resonator transmission of subsequently applied source photons. A weak gate pulse induces bimodal transmission distribution, corresponding to zero and one gate photons. One stored gate photon produces fivefold source attenuation and can be retrieved from the atomic ensemble after switching more than one source photon. Without retrieval, one stored gate photon can switch several hundred source photons. With improved storage and retrieval efficiency, our work may enable various new applications, including photonic quantum gates and deterministic multiphoton entanglement.

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

40. HYDRAULIC OIL LINES, VALVES AND GAUGE FOR SLIDE GATE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

40. HYDRAULIC OIL LINES, VALVES AND GAUGE FOR SLIDE GATE HOISTS IN MACHINERY CHAMBER FOR SLUICE GATE WORKS ON GALLERY 1. NOTE HYDRAULIC OIL TANK AT UPPER RIGHT AND SCHEMATIC DRAWING OF PUMPING SYSTEM AT LEFT. VIEW TO NORTHWEST. - Owyhee Dam, Across Owyhee River, Nyssa, Malheur County, OR

Spin measurement in an undoped Si/SiGe double quantum dot incorporating a micromagnet

NASA Astrophysics Data System (ADS)

Wu, Xian; Ward, Daniel; Prance, Jonathan; Kim, Dohun; Shi, Zhan; Mohr, Robert; Gamble, John; Savage, Donald; Lagally, Max; Friesen, Mark; Coppersmith, Susan; Eriksson, Mark

2014-03-01

We present measurements on a double dot formed in an accumulation-mode undoped Si/SiGe heterostructure. The double dot incorporates a proximal micromagnet to generate a stable magnetic field difference between the quantum dots. The gate design incorporates two layers of gates, and the upper layer of gates is split into five different sections to decrease crosstalk between different gates. A novel pattern of the lower layer gates enhances the tunability of tunnel rates. We will describe our attempts to create a singlet-triplet qubit in this device. This work was supported in part by ARO(W911NF-12-0607), NSF(DMR-1206915), and the United States Department of Defense. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the US Government. Now works at Lancaster University, UK.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Origins of Chaos in Autonomous Boolean Networks

NASA Astrophysics Data System (ADS)

Socolar, Joshua; Cavalcante, Hugo; Gauthier, Daniel; Zhang, Rui

2010-03-01

Networks with nodes consisting of ideal Boolean logic gates are known to display either steady states, periodic behavior, or an ultraviolet catastrophe where the number of logic-transition events circulating in the network per unit time grows as a power-law. In an experiment, non-ideal behavior of the logic gates prevents the ultraviolet catastrophe and may lead to deterministic chaos. We identify certain non-ideal features of real logic gates that enable chaos in experimental networks. We find that short-pulse rejection and the asymmetry between the logic states tends to engender periodic behavior. On the other hand, a memory effect termed ``degradation'' can generate chaos. Our results strongly suggest that deterministic chaos can be expected in a large class of experimental Boolean-like networks. Such devices may find application in a variety of technologies requiring fast complex waveforms or flat power spectra. The non-ideal effects identified here also have implications for the statistics of attractors in large complex networks.

Consciousness and working memory: Current trends and research perspectives.

PubMed

Velichkovsky, Boris B

2017-10-01

Working memory has long been thought to be closely related to consciousness. However, recent empirical studies show that unconscious content may be maintained within working memory and that complex cognitive computations may be performed on-line. This promotes research on the exact relationships between consciousness and working memory. Current evidence for working memory being a conscious as well as an unconscious process is reviewed. Consciousness is shown to be considered a subset of working memory by major current theories of working memory. Evidence for unconscious elements in working memory is shown to come from visual masking and attentional blink paradigms, and from the studies of implicit working memory. It is concluded that more research is needed to explicate the relationship between consciousness and working memory. Future research directions regarding the relationship between consciousness and working memory are discussed. Copyright © 2017 Elsevier Inc. All rights reserved.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baart, T. A.; Vandersypen, L. M. K.; Kavli Institute of Nanoscience, Delft University of Technology, P.O. Box 5046, 2600 GA Delft

We report the computer-automated tuning of gate-defined semiconductor double quantum dots in GaAs heterostructures. We benchmark the algorithm by creating three double quantum dots inside a linear array of four quantum dots. The algorithm sets the correct gate voltages for all the gates to tune the double quantum dots into the single-electron regime. The algorithm only requires (1) prior knowledge of the gate design and (2) the pinch-off value of the single gate T that is shared by all the quantum dots. This work significantly alleviates the user effort required to tune multiple quantum dot devices.

Investigations on the effects of electrode materials on the device characteristics of ferroelectric memory thin film transistors fabricated on flexible substrates

NASA Astrophysics Data System (ADS)

Yang, Ji-Hee; Yun, Da-Jeong; Seo, Gi-Ho; Kim, Seong-Min; Yoon, Myung-Han; Yoon, Sung-Min

2018-03-01

For flexible memory device applications, we propose memory thin-film transistors using an organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] gate insulator and an amorphous In-Ga-Zn-O (a-IGZO) active channel. The effects of electrode materials and their deposition methods on the characteristics of memory devices exploiting the ferroelectric field effect were investigated for the proposed ferroelectric memory thin-film transistors (Fe-MTFTs) at flat and bending states. It was found that the plasma-induced sputtering deposition and mechanical brittleness of the indium-tin oxide (ITO) markedly degraded the ferroelectric-field-effect-driven memory window and bending characteristics of the Fe-MTFTs. The replacement of ITO electrodes with metal aluminum (Al) electrodes prepared by plasma-free thermal evaporation greatly enhanced the memory device characteristics even under bending conditions owing to their mechanical ductility. Furthermore, poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) was introduced to achieve robust bending performance under extreme mechanical stress. The Fe-MTFTs using PEDOT:PSS source/drain electrodes were successfully fabricated and showed the potential for use as flexible memory devices. The suitable choice of electrode materials employed for the Fe-MTFTs is concluded to be one of the most important control parameters for highly functional flexible Fe-MTFTs.

Low-voltage-operated organic one-time programmable memory using printed organic thin-film transistors and antifuse capacitors.

PubMed

Jung, Soon-Won; Na, Bock Soon; Park, Chan Woo; Koo, Jae Bon

2014-11-01

We demonstrate an organic one-time programmable memory cell formed entirely at plastic-compatible temperatures. All the processes are performed at below 130 degrees C. Our memory cell consists of a printed organic transistor and an organic capacitor. Inkjet-printed organic transistors are fabricated by using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) for low-voltage operation. P(NDI2OD-T2) transistors have a high field-effect mobility of 0.2 cm2/Vs and a low operation gate voltage of less than 10 V. The operation voltage effectively decreases owing to the high permittivity of the P(VDF-TrFE):PMMA blended film. The data in the memory cell are programmed by electrically breaking the organic capacitor. The organic capacitor acts like an antifuse capacitor, because it is initially open, and it becomes permanently short-circuited by applying a high voltage. The organic memory cells are programmed with 4 V, and they are read out with 2 V. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for applications storing small amount of data, such as low-cost radio-frequency identification (RFID) tag.

The Relationships of Working Memory, Secondary Memory, and General Fluid Intelligence: Working Memory is Special

PubMed Central

Shelton, Jill Talley; Elliott, Emily M.; Matthews, Russell A.; Hill, B. D.; Gouvier, Wm. Drew

2010-01-01

Recent efforts have been made to elucidate the commonly observed link between working memory and reasoning ability. The results have been inconsistent, with some work suggesting the emphasis placed on retrieval from secondary memory by working memory tests is the driving force behind this association (Mogle, Lovett, Stawski, & Sliwinski, 2008), while other research suggests retrieval from secondary memory is only partly responsible for the observed link between working memory and reasoning (Unsworth & Engle, 2006, 2007b). The present study investigates the relationship between processing speed, working memory, secondary memory, primary memory, and fluid intelligence. Although our findings show all constructs are significantly correlated with fluid intelligence, working memory, but not secondary memory, accounts for significant unique variance in fluid intelligence. Our data support predictions made by Unsworth and Engle, and suggest that the combined need for maintenance and retrieval processes present in working memory tests makes them “special” in their prediction of higher-order cognition. PMID:20438278

Working Memory From the Psychological and Neurosciences Perspectives: A Review.

PubMed

Chai, Wen Jia; Abd Hamid, Aini Ismafairus; Abdullah, Jafri Malin

2018-01-01

Since the concept of working memory was introduced over 50 years ago, different schools of thought have offered different definitions for working memory based on the various cognitive domains that it encompasses. The general consensus regarding working memory supports the idea that working memory is extensively involved in goal-directed behaviors in which information must be retained and manipulated to ensure successful task execution. Before the emergence of other competing models, the concept of working memory was described by the multicomponent working memory model proposed by Baddeley and Hitch. In the present article, the authors provide an overview of several working memory-relevant studies in order to harmonize the findings of working memory from the neurosciences and psychological standpoints, especially after citing evidence from past studies of healthy, aging, diseased, and/or lesioned brains. In particular, the theoretical framework behind working memory, in which the related domains that are considered to play a part in different frameworks (such as memory's capacity limit and temporary storage) are presented and discussed. From the neuroscience perspective, it has been established that working memory activates the fronto-parietal brain regions, including the prefrontal, cingulate, and parietal cortices. Recent studies have subsequently implicated the roles of subcortical regions (such as the midbrain and cerebellum) in working memory. Aging also appears to have modulatory effects on working memory; age interactions with emotion, caffeine and hormones appear to affect working memory performances at the neurobiological level. Moreover, working memory deficits are apparent in older individuals, who are susceptible to cognitive deterioration. Another younger population with working memory impairment consists of those with mental, developmental, and/or neurological disorders such as major depressive disorder and others. A less coherent and organized neural pattern has been consistently reported in these disadvantaged groups. Working memory of patients with traumatic brain injury was similarly affected and shown to have unusual neural activity (hyper- or hypoactivation) as a general observation. Decoding the underlying neural mechanisms of working memory helps support the current theoretical understandings concerning working memory, and at the same time provides insights into rehabilitation programs that target working memory impairments from neurophysiological or psychological aspects.

The Nature of Individual Differences in Working Memory Capacity: Active Maintenance in Primary Memory and Controlled Search from Secondary Memory

ERIC Educational Resources Information Center

Unsworth, Nash; Engle, Randall W.

2007-01-01

Studies examining individual differences in working memory capacity have suggested that individuals with low working memory capacities demonstrate impaired performance on a variety of attention and memory tasks compared with individuals with high working memory capacities. This working memory limitation can be conceived of as arising from 2…

Error budgeting single and two qubit gates in a superconducting qubit

NASA Astrophysics Data System (ADS)

Chen, Z.; Chiaro, B.; Dunsworth, A.; Foxen, B.; Neill, C.; Quintana, C.; Wenner, J.; Martinis, John. M.; Google Quantum Hardware Team Team

Superconducting qubits have shown promise as a platform for both error corrected quantum information processing and demonstrations of quantum supremacy. High fidelity quantum gates are crucial to achieving both of these goals, and superconducting qubits have demonstrated two qubit gates exceeding 99% fidelity. In order to improve gate fidelity further, we must understand the remaining sources of error. In this talk, I will demonstrate techniques for quantifying the contributions of control, decoherence, and leakage to gate error, for both single and two qubit gates. I will also discuss the near term outlook for achieving quantum supremacy using a gate-based approach in superconducting qubits. This work is supported Google Inc., and by the National Science Foundation Graduate Research Fellowship under Grant No. DGE 1605114.

Contrasting single and multi-component working-memory systems in dual tasking.

PubMed

Nijboer, Menno; Borst, Jelmer; van Rijn, Hedderik; Taatgen, Niels

2016-05-01

Working memory can be a major source of interference in dual tasking. However, there is no consensus on whether this interference is the result of a single working memory bottleneck, or of interactions between different working memory components that together form a complete working-memory system. We report a behavioral and an fMRI dataset in which working memory requirements are manipulated during multitasking. We show that a computational cognitive model that assumes a distributed version of working memory accounts for both behavioral and neuroimaging data better than a model that takes a more centralized approach. The model's working memory consists of an attentional focus, declarative memory, and a subvocalized rehearsal mechanism. Thus, the data and model favor an account where working memory interference in dual tasking is the result of interactions between different resources that together form a working-memory system. Copyright © 2016 Elsevier Inc. All rights reserved.

The contributions of handedness and working memory to episodic memory.

PubMed

Sahu, Aparna; Christman, Stephen D; Propper, Ruth E

2016-11-01

Past studies have independently shown associations of working memory and degree of handedness with episodic memory retrieval. The current study takes a step ahead by examining whether handedness and working memory independently predict episodic memory. In agreement with past studies, there was an inconsistent-handed advantage for episodic memory; however, this advantage was absent for working memory tasks. Furthermore, regression analyses showed handedness, and complex working memory predicted episodic memory performance at different times. Results are discussed in light of theories of episodic memory and hemispheric interaction.

Working Memory From the Psychological and Neurosciences Perspectives: A Review

PubMed Central

Chai, Wen Jia; Abd Hamid, Aini Ismafairus; Abdullah, Jafri Malin

2018-01-01

Since the concept of working memory was introduced over 50 years ago, different schools of thought have offered different definitions for working memory based on the various cognitive domains that it encompasses. The general consensus regarding working memory supports the idea that working memory is extensively involved in goal-directed behaviors in which information must be retained and manipulated to ensure successful task execution. Before the emergence of other competing models, the concept of working memory was described by the multicomponent working memory model proposed by Baddeley and Hitch. In the present article, the authors provide an overview of several working memory-relevant studies in order to harmonize the findings of working memory from the neurosciences and psychological standpoints, especially after citing evidence from past studies of healthy, aging, diseased, and/or lesioned brains. In particular, the theoretical framework behind working memory, in which the related domains that are considered to play a part in different frameworks (such as memory’s capacity limit and temporary storage) are presented and discussed. From the neuroscience perspective, it has been established that working memory activates the fronto-parietal brain regions, including the prefrontal, cingulate, and parietal cortices. Recent studies have subsequently implicated the roles of subcortical regions (such as the midbrain and cerebellum) in working memory. Aging also appears to have modulatory effects on working memory; age interactions with emotion, caffeine and hormones appear to affect working memory performances at the neurobiological level. Moreover, working memory deficits are apparent in older individuals, who are susceptible to cognitive deterioration. Another younger population with working memory impairment consists of those with mental, developmental, and/or neurological disorders such as major depressive disorder and others. A less coherent and organized neural pattern has been consistently reported in these disadvantaged groups. Working memory of patients with traumatic brain injury was similarly affected and shown to have unusual neural activity (hyper- or hypoactivation) as a general observation. Decoding the underlying neural mechanisms of working memory helps support the current theoretical understandings concerning working memory, and at the same time provides insights into rehabilitation programs that target working memory impairments from neurophysiological or psychological aspects. PMID:29636715

Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMs

NASA Astrophysics Data System (ADS)

Diehl, S. E.; Ochoa, A., Jr.; Dressendorfer, P. V.; Koga, P.; Kolasinski, W. A.

1982-12-01

Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Coaching positively influences the effects of working memory training on visual working memory as well as mathematical ability.

PubMed

Nelwan, Michel; Vissers, Constance; Kroesbergen, Evelyn H

2018-05-01

The goal of the present study was to test whether the amount of coaching influenced the results of working memory training on both visual and verbal working memory. Additionally, the effects of the working memory training on the amount of progress after specific training in mathematics were evaluated. In this study, 23 children between 9 and 12 years of age with both attentional and mathematical difficulties participated in a working memory training program with a high amount of coaching, while another 25 children received no working memory training. Results of these groups were compared to 21 children who completed the training with a lower amount of coaching. The quality of working memory, as well as mathematic skills, were measured three times using untrained transfer tasks. Bayesian statistics were used to test informative hypotheses. After receiving working memory training, the highly coached group performed better than the group that received less coaching on visual working memory and mathematics, but not on verbal working memory. The highly coached group retained their advantage in mathematics, even though the effect on visual working memory decreased. However, no added effect of working memory training was found on the learning curve during mathematical training. Moreover, the less-coached group was outperformed by the group that did not receive working memory training, both in visual working memory and mathematics. These results suggest that motivation and proper coaching might be crucial for ensuring compliance and effects of working memory training, and that far transfer might be possible. Copyright © 2018 Elsevier Ltd. All rights reserved.

An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Khosroshahy, Milad Bagherian; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

Nanotechnologies, notably quantum-dot cellular automata, have achieved major attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, high switching speed and ultra-low energy consumption, is considered as a potential alternative for the CMOS technology. As the memory unit is one of the most essential components in a digital system, designing a well-optimized QCA random access memory (RAM) cell is an important area of research. In this paper, a new five-input majority gate is presented which is suitable for implementing efficient single-layer QCA circuits. In addition, a new RAM cell with set and reset capabilities is designed based on the proposed majority gate, which has an efficient and low-energy structure. The functionality, performance and energy consumption of the proposed designs are evaluated based on the QCADesigner and QCAPro tools. According to the simulation results, the proposed RAM design leads to on average 38% lower total energy dissipation, 25% smaller area, 20% lower cell count, 28% lower delay and 60% lower QCA cost as compared to its previous counterparts.

Noise-Resilient Quantum Computing with a Nitrogen-Vacancy Center and Nuclear Spins.

PubMed

Casanova, J; Wang, Z-Y; Plenio, M B

2016-09-23

Selective control of qubits in a quantum register for the purposes of quantum information processing represents a critical challenge for dense spin ensembles in solid-state systems. Here we present a protocol that achieves a complete set of selective electron-nuclear gates and single nuclear rotations in such an ensemble in diamond facilitated by a nearby nitrogen-vacancy (NV) center. The protocol suppresses internuclear interactions as well as unwanted coupling between the NV center and other spins of the ensemble to achieve quantum gate fidelities well exceeding 99%. Notably, our method can be applied to weakly coupled, distant spins representing a scalable procedure that exploits the exceptional properties of nuclear spins in diamond as robust quantum memories.

Hysteresis in the transfer characteristics of MoS2 transistors

NASA Astrophysics Data System (ADS)

Di Bartolomeo, Antonio; Genovese, Luca; Giubileo, Filippo; Iemmo, Laura; Luongo, Giuseppe; Foller, Tobias; Schleberger, Marika

2018-01-01

We investigate the origin of the hysteresis observed in the transfer characteristics of back-gated field-effect transistors with an exfoliated MoS2 channel. We find that the hysteresis is strongly enhanced by increasing either gate voltage, pressure, temperature or light intensity. Our measurements reveal a step-like behavior of the hysteresis around room temperature, which we explain as water-facilitated charge trapping at the MoS2/SiO2 interface. We conclude that intrinsic defects in MoS2, such as S vacancies, which result in effective positive charge trapping, play an important role, besides H2O and O2 adsorbates on the unpassivated device surface. We show that the bistability associated to the hysteresis can be exploited in memory devices.

Further characterization of the effect of ethanol on voltage-gated Ca(2+) channel function in developing CA3 hippocampal pyramidal neurons.

PubMed

Morton, Russell A; Valenzuela, C Fernando

2016-02-15

Developmental ethanol exposure damages the hippocampus, a brain region involved in learning and memory. Alterations in synaptic transmission and plasticity may play a role in this effect of ethanol. We previously reported that acute and repeated exposure to ethanol during the third trimester-equivalent inhibits long-term potentiation of GABAA receptor-dependent synaptic currents in CA3 pyramidal neurons through a mechanism that depends on retrograde release of brain-derived neurotrophic factor driven by activation of voltage-gated Ca(2+) channels (Zucca and Valenzuela, 2010). We found evidence indicating that voltage-gated Ca(2+) channels are inhibited in the presence of ethanol, an effect that may play a role in its mechanism of action. Here, we further investigated the acute effect of ethanol on the function of voltage-gated Ca(2+) channels in CA3 pyramidal neurons using Ca(2+) imaging techniques. These experiments revealed that acute ethanol exposure inhibits voltage-gated Ca(2+) channels both in somatic and proximal dendritic compartments. To investigate the long-term consequences of ethanol on voltage-gated Ca(2+) channels, we used patch-clamp electrophysiological techniques to assess the function of L-type voltage-gated Ca(2+) channels during and following ten days of vapor ethanol exposure. During ethanol withdrawal periods, the function of these channels was not significantly affected by vapor chamber exposure. Taken together with our previous findings, our results suggest that 3(rd) trimester-equivalent ethanol exposure transiently inhibits L-type voltage-gated Ca(2+) channel function in CA3 pyramidal neurons and that compensatory mechanisms restore their function during ethanol withdrawal. Transient inhibition of these channels by ethanol may be, in part, responsible for the hippocampal abnormalities associated with developmental exposure to this agent. Copyright © 2015 Elsevier B.V. All rights reserved.

Power-Law Dynamics of Membrane Conductances Increase Spiking Diversity in a Hodgkin-Huxley Model.

PubMed

Teka, Wondimu; Stockton, David; Santamaria, Fidel

2016-03-01

We studied the effects of non-Markovian power-law voltage dependent conductances on the generation of action potentials and spiking patterns in a Hodgkin-Huxley model. To implement slow-adapting power-law dynamics of the gating variables of the potassium, n, and sodium, m and h, conductances we used fractional derivatives of order η≤1. The fractional derivatives were used to solve the kinetic equations of each gate. We systematically classified the properties of each gate as a function of η. We then tested if the full model could generate action potentials with the different power-law behaving gates. Finally, we studied the patterns of action potential that emerged in each case. Our results show the model produces a wide range of action potential shapes and spiking patterns in response to constant current stimulation as a function of η. In comparison with the classical model, the action potential shapes for power-law behaving potassium conductance (n gate) showed a longer peak and shallow hyperpolarization; for power-law activation of the sodium conductance (m gate), the action potentials had a sharp rise time; and for power-law inactivation of the sodium conductance (h gate) the spikes had wider peak that for low values of η replicated pituitary- and cardiac-type action potentials. With all physiological parameters fixed a wide range of spiking patterns emerged as a function of the value of the constant input current and η, such as square wave bursting, mixed mode oscillations, and pseudo-plateau potentials. Our analyses show that the intrinsic memory trace of the fractional derivative provides a negative feedback mechanism between the voltage trace and the activity of the power-law behaving gate variable. As a consequence, power-law behaving conductances result in an increase in the number of spiking patterns a neuron can generate and, we propose, expand the computational capacity of the neuron.

Sleep Extension Normalizes ERP of Waking Auditory Sensory Gating in Healthy Habitually Short Sleeping Individuals

PubMed Central

Gumenyuk, Valentina; Korzyukov, Oleg; Roth, Thomas; Bowyer, Susan M.; Drake, Christopher L.

2013-01-01

Chronic sleep loss has been associated with increased daytime sleepiness, as well as impairments in memory and attentional processes. In the present study, we evaluated the neuronal changes of a pre-attentive process of wake auditory sensory gating, measured by brain event-related potential (ERP) – P50 in eight normal sleepers (NS) (habitual total sleep time (TST) 7 h 32 m) vs. eight chronic short sleeping individuals (SS) (habitual TST ≤6 h). To evaluate the effect of sleep extension on sensory gating, the extended sleep condition was performed in chronic short sleeping individuals. Thus, one week of time in bed (6 h 11 m) corresponding to habitual short sleep (hSS), and one week of extended time (∼ 8 h 25 m) in bed corresponding to extended sleep (eSS), were counterbalanced in the SS group. The gating ERP assessment was performed on the last day after each sleep condition week (normal sleep and habitual short and extended sleep), and was separated by one week with habitual total sleep time and monitored by a sleep diary. We found that amplitude of gating was lower in SS group compared to that in NS group (0.3 µV vs. 1.2 µV, at Cz electrode respectively). The results of the group × laterality interaction showed that the reduction of gating amplitude in the SS group was due to lower amplitude over the left hemisphere and central-midline sites relative to that in the NS group. After sleep extension the amplitude of gating increased in chronic short sleeping individuals relative to their habitual short sleep condition. The sleep condition × frontality interaction analysis confirmed that sleep extension significantly increased the amplitude of gating over frontal and central brain areas compared to parietal brain areas. PMID:23520548

76 FR 57763 - Alaska Region's Subsistence Resource Commission (SRC) Program

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-16

...) program. SUMMARY: The Gates of the Arctic National Park SRC will meet to develop and continue work on NPS... changed based on inclement weather or exceptional circumstances. Gates of the Arctic National Park SRC Meeting Dates and Location: The Gates of the Arctic National Park SRC will meet at Sophie Station Hotel...

Rooting through the Past

ERIC Educational Resources Information Center

Dodson, Angela P.

2012-01-01

Henry Louis Gates Jr., the Harvard professor and cultural critic, has been so prolific as a writer that the idea of fitting his essential works into a single volume of a manageable size seems preposterous. It has been done, however, in the recently published "The Henry Louis Gates, Jr. Reader." The Gates reader contains his favorite stories which…

Universal quantum gates for photon-atom hybrid systems assisted by bad cavities

PubMed Central

Wang, Guan-Yu; Liu, Qian; Wei, Hai-Rui; Li, Tao; Ai, Qing; Deng, Fu-Guo

2016-01-01

We present two deterministic schemes for constructing a CNOT gate and a Toffoli gate on photon-atom and photon-atom-atom hybrid quantum systems assisted by bad cavities, respectively. They are achieved by cavity-assisted photon scattering and work in the intermediate coupling region with bad cavities, which relaxes the difficulty of their implementation in experiment. Also, bad cavities are feasible for fast quantum operations and reading out information. Compared with previous works, our schemes do not need any auxiliary qubits and measurements. Moreover, the schematic setups for these gates are simple, especially that for our Toffoli gate as only a quarter wave packet is used to interact the photon with each of the atoms every time. These atom-cavity systems can be used as the quantum nodes in long-distance quantum communication as their relatively long coherence time is suitable for multi-time operations between the photon and the system. Our calculations show that the average fidelities and efficiencies of our two universal hybrid quantum gates are high with current experimental technology. PMID:27067992

Can verbal working memory training improve reading?

PubMed

Banales, Erin; Kohnen, Saskia; McArthur, Genevieve

2015-01-01

The aim of the current study was to determine whether poor verbal working memory is associated with poor word reading accuracy because the former causes the latter, or the latter causes the former. To this end, we tested whether (a) verbal working memory training improves poor verbal working memory or poor word reading accuracy, and whether (b) reading training improves poor reading accuracy or verbal working memory in a case series of four children with poor word reading accuracy and verbal working memory. Each child completed 8 weeks of verbal working memory training and 8 weeks of reading training. Verbal working memory training improved verbal working memory in two of the four children, but did not improve their reading accuracy. Similarly, reading training improved word reading accuracy in all children, but did not improve their verbal working memory. These results suggest that the causal links between verbal working memory and reading accuracy may not be as direct as has been assumed.

Fluorescently labeled dengue viruses as probes to identify antigen-specific memory B cells by multiparametric flow cytometry

PubMed Central

Woda, Marcia; Mathew, Anuja

2015-01-01

Low frequencies of memory B cells in the peripheral blood make it challenging to measure the functional and phenotypic characteristics of this antigen experienced subset of B cells without in vitro culture. To date, reagents are lacking to measure ex vivo frequencies of dengue virus (DENV)-specific memory B cells. We wanted to explore the possibility of using fluorescently labeled DENV as probes to detect antigen-specific memory B cells in the peripheral blood of DENV immune individuals. Alexa Fluor dye-labeled DENV yielded viable virus that could be stored at −80°C for long periods of time. Using a careful gating strategy and methods to decrease non-specific binding, we were able to identify a small frequency of B cells from dengue immune individuals that bound labeled DENV. Sorted DENV+ B cells from immune, but not naïve donors secreted antibodies that bound intact virions after in vitro stimulation. Overall, Alexa Fluor dye labeled -DENV are useful reagents to enable the detection and characterization of memory B cells in DENV immune individuals. PMID:25497702

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

Organic transistor memory with a charge storage molecular double-floating-gate monolayer.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2015-05-13

A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor. The monolayer-forming molecule contains a phosphonic acid group as the anchoring moiety and a charge-trapping core group flanked between two alkyl chain spacers as the charge trapping site. The memory characteristics strongly depend on the monolayer used due to the localized charge-trapping capability for different core groups, including the diacetylenic (DA) unit as the hole carrier trap, the naphthalenetetracarboxyldiimide (ND) unit as the electron carrier trap, and the one with both DA and ND units present, respectively. The device with the monolayer carrying both DA and ND groups has a larger memory window than that for the one containing DA only and a longer retention time than that for the one containing DA or ND only, giving a memory window of 1.4 V and a retention time around 10(9) s. This device with hybrid organic monolayer/inorganic dielectrics also exhibited rather stable device characteristics upon bending of the polymeric substrate.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Visual working memory buffers information retrieved from visual long-term memory.

PubMed

Fukuda, Keisuke; Woodman, Geoffrey F

2017-05-16

Human memory is thought to consist of long-term storage and short-term storage mechanisms, the latter known as working memory. Although it has long been assumed that information retrieved from long-term memory is represented in working memory, we lack neural evidence for this and need neural measures that allow us to watch this retrieval into working memory unfold with high temporal resolution. Here, we show that human electrophysiology can be used to track information as it is brought back into working memory during retrieval from long-term memory. Specifically, we found that the retrieval of information from long-term memory was limited to just a few simple objects' worth of information at once, and elicited a pattern of neurophysiological activity similar to that observed when people encode new information into working memory. Our findings suggest that working memory is where information is buffered when being retrieved from long-term memory and reconcile current theories of memory retrieval with classic notions about the memory mechanisms involved.

Visual working memory buffers information retrieved from visual long-term memory

PubMed Central

Fukuda, Keisuke; Woodman, Geoffrey F.

2017-01-01

Human memory is thought to consist of long-term storage and short-term storage mechanisms, the latter known as working memory. Although it has long been assumed that information retrieved from long-term memory is represented in working memory, we lack neural evidence for this and need neural measures that allow us to watch this retrieval into working memory unfold with high temporal resolution. Here, we show that human electrophysiology can be used to track information as it is brought back into working memory during retrieval from long-term memory. Specifically, we found that the retrieval of information from long-term memory was limited to just a few simple objects’ worth of information at once, and elicited a pattern of neurophysiological activity similar to that observed when people encode new information into working memory. Our findings suggest that working memory is where information is buffered when being retrieved from long-term memory and reconcile current theories of memory retrieval with classic notions about the memory mechanisms involved. PMID:28461479

Working and strategic memory deficits in schizophrenia

NASA Technical Reports Server (NTRS)

Stone, M.; Gabrieli, J. D.; Stebbins, G. T.; Sullivan, E. V.

1998-01-01

Working memory and its contribution to performance on strategic memory tests in schizophrenia were studied. Patients (n = 18) and control participants (n = 15), all men, received tests of immediate memory (forward digit span), working memory (listening, computation, and backward digit span), and long-term strategic (free recall, temporal order, and self-ordered pointing) and nonstrategic (recognition) memory. Schizophrenia patients performed worse on all tests. Education, verbal intelligence, and immediate memory capacity did not account for deficits in working memory in schizophrenia patients. Reduced working memory capacity accounted for group differences in strategic memory but not in recognition memory. Working memory impairment may be central to the profile of impaired cognitive performance in schizophrenia and is consistent with hypothesized frontal lobe dysfunction associated with this disease. Additional medial-temporal dysfunction may account for the recognition memory deficit.

Memory systems interaction in the pigeon: working and reference memory.

PubMed

Roberts, William A; Strang, Caroline; Macpherson, Krista

2015-04-01

Pigeons' performance on a working memory task, symbolic delayed matching-to-sample, was used to examine the interaction between working memory and reference memory. Reference memory was established by training pigeons to discriminate between the comparison cues used in delayed matching as S+ and S- stimuli. Delayed matching retention tests then measured accuracy when working and reference memory were congruent and incongruent. In 4 experiments, it was shown that the interaction between working and reference memory is reciprocal: Strengthening either type of memory leads to a decrease in the influence of the other type of memory. A process dissociation procedure analysis of the data from Experiment 4 showed independence of working and reference memory, and a model of working memory and reference memory interaction was shown to predict the findings reported in the 4 experiments. (PsycINFO Database Record (c) 2015 APA, all rights reserved).

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Voltage-controlled low-energy switching of nanomagnets through Ruderman-Kittel-Kasuya-Yosida interactions for magnetoelectric device applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ghosh, Bahniman, E-mail: bghosh@utexas.edu; Dey, Rik; Register, Leonard F.

2016-07-21

In this article, we consider through simulation low-energy switching of nanomagnets via electrostatically gated inter-magnet Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions on the surface of three-dimensional topological insulators, for possible memory and nonvolatile logic applications. We model the possibility and dynamics of RKKY-based switching of one nanomagnet by coupling to one or more nanomagnets of set orientation. Potential applications to both memory and nonvolatile logic are illustrated. Sub-attojoule switching energies, far below conventional spin transfer torque (STT)-based memories and even below CMOS logic appear possible. Switching times on the order of a few nanoseconds, comparable to times for STT switching, are estimated formore » ferromagnetic nanomagnets, but the approach also appears compatible with the use of antiferromagnets which may allow for faster switching.« less

Recent Advances of Flexible Data Storage Devices Based on Organic Nanoscaled Materials.

PubMed

Zhou, Li; Mao, Jingyu; Ren, Yi; Han, Su-Ting; Roy, Vellaisamy A L; Zhou, Ye

2018-03-01

Following the trend of miniaturization as per Moore's law, and facing the strong demand of next-generation electronic devices that should be highly portable, wearable, transplantable, and lightweight, growing endeavors have been made to develop novel flexible data storage devices possessing nonvolatile ability, high-density storage, high-switching speed, and reliable endurance properties. Nonvolatile organic data storage devices including memory devices on the basis of floating-gate, charge-trapping, and ferroelectric architectures, as well as organic resistive memory are believed to be favorable candidates for future data storage applications. In this Review, typical information on device structure, memory characteristics, device operation mechanisms, mechanical properties, challenges, and recent progress of the above categories of flexible data storage devices based on organic nanoscaled materials is summarized. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

DC and analog/RF performance optimisation of source pocket dual work function TFET

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Sharma, Dheeraj; Kondekar, Pravin; Nigam, Kaushal; Baronia, Sagar

2017-12-01

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

Interactions Between Modality of Working Memory Load and Perceptual Load in Distractor Processing.

PubMed

Koshino, Hideya; Olid, Pilar

2015-01-01

The present study investigated interactions between working memory load and perceptual load. The load theory (Lavie, Hirst, de Fockert, & Viding, 2004 ) claims that perceptual load decreases distractor interference, whereas working memory load increases interference. However, recent studies showed that effects of working memory might depend on the relationship between modalities of working memory and task stimuli. Here, we examined whether the relationship between working memory load and perceptual load would remain the same across modalities. The results of Experiment 1 showed that verbal working memory load did not affect a compatibility effect for low perceptual load, whereas it increased the compatibility effect for high perceptual load. In Experiment 2, the compatibility effect remained the same regardless of visual working memory load. These results suggest that the effects of working memory load and perceptual load depend on the relationship between the modalities of working memory and stimuli.

Working-memory performance is related to spatial breadth of attention.

PubMed

Kreitz, Carina; Furley, Philip; Memmert, Daniel; Simons, Daniel J

2015-11-01

Working memory and attention are closely related constructs. Models of working memory often incorporate an attention component, and some even equate working memory and attentional control. Although some attention-related processes, including inhibitory control of response conflict and interference resolution, are strongly associated with working memory, for other aspects of attention the link is less clear. We examined the association between working-memory performance and attentional breadth, the ability to spread attention spatially. If the link between attention and working memory is broader than inhibitory and interference resolution processes, then working-memory performance might also be associated with other attentional abilities, including attentional breadth. We tested 123 participants on a variety of working-memory and attentional-breadth measures, finding a strong correlation between performances on these two types of tasks. This finding demonstrates that the link between working memory and attention extends beyond inhibitory processes.