Science.gov

Sample records for hardware reuseable gateware

  1. Movable Ground Based Recovery System for Reuseable Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Sarver, George L. (Inventor)

    2013-01-01

    A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

  2. Hardware

    NASA Technical Reports Server (NTRS)

    1999-01-01

    The full complement of EDOMP investigations called for a broad spectrum of flight hardware ranging from commercial items, modified for spaceflight, to custom designed hardware made to meet the unique requirements of testing in the space environment. In addition, baseline data collection before and after spaceflight required numerous items of ground-based hardware. Two basic categories of ground-based hardware were used in EDOMP testing before and after flight: (1) hardware used for medical baseline testing and analysis, and (2) flight-like hardware used both for astronaut training and medical testing. To ensure post-landing data collection, hardware was required at both the Kennedy Space Center (KSC) and the Dryden Flight Research Center (DFRC) landing sites. Items that were very large or sensitive to the rigors of shipping were housed permanently at the landing site test facilities. Therefore, multiple sets of hardware were required to adequately support the prime and backup landing sites plus the Johnson Space Center (JSC) laboratories. Development of flight hardware was a major element of the EDOMP. The challenges included obtaining or developing equipment that met the following criteria: (1) compact (small size and light weight), (2) battery-operated or requiring minimal spacecraft power, (3) sturdy enough to survive the rigors of spaceflight, (4) quiet enough to pass acoustics limitations, (5) shielded and filtered adequately to assure electromagnetic compatibility with spacecraft systems, (6) user-friendly in a microgravity environment, and (7) accurate and efficient operation to meet medical investigative requirements.

  3. Controls concepts for next generation reuseable rocket engines

    NASA Technical Reports Server (NTRS)

    Lorenzo, Carl F.; Merrill, Walter C.; Musgrave, Jefferey L.; Ray, Asok

    1995-01-01

    Three primary issues will drive the design and control used in next generation reuseable rocket engines. In addition to steady-state and dynamic performance, the requirements for increased durability, reliability and operability (with faults) will dictate which new controls and design technologies and features will be brought to bear. An array of concepts which have been brought forward will be tested against the measures of cost and benefit as reflected in the above 'ilities'. This paper examines some of the new concepts and looks for metrics to judge their value.

  4. [The effectiveness of a system using re-useable linens to reduce the expense of surgical operations].

    PubMed

    Nagano, Kazuko; Morita, Saori; Shinoda, Maiko; Kawana, Yuki; Satou, Yuu; Yokozuka, Makito

    2013-10-01

    We introduced a system that uses re-useable linens for surgical operations in 2008. After 3 years from introduction we were able to reduce the expense of about yen 4,340,000 per year and CO2 production of 9,548 kg CO2 x m(-2) per year. We were convinced of the effect on reducing the expense of surgical operations and of decreasing the level of CO2 production that leads to global warming.

  5. Hardly Hardware

    ERIC Educational Resources Information Center

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  6. Hardware Review: What Hardware Should We Buy?

    ERIC Educational Resources Information Center

    Tinker, Robert

    1984-01-01

    Discusses trends and changes in hardware production. For example Sinclair/Timex has stopped mass marketing its computers while others (such as the IBM junior) has finally made its appearance. Strongly advises schools to re-evaluate their hardware purchasing programs in light of these and other changes. (JN)

  7. Hardware description languages

    NASA Technical Reports Server (NTRS)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  8. Hardware removal - extremity

    MedlinePlus

    ... enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help fix a broken bone ... SW, Hotchkiss RN, Pederson WC, Kozin SH, Cohen MS, eds. Green's Operative Hand Surgery . 7th ed. Philadelphia, ...

  9. Initial Hardware Development Schedule

    NASA Technical Reports Server (NTRS)

    Culpepper, William X.

    1991-01-01

    The hardware development schedule for the Common Lunar Lander's (CLLs) tracking system is presented. Among the topics covered are the following: historical perspective, solution options, industry contacts, and the rationale for selection.

  10. NASA HUNCH Hardware

    NASA Technical Reports Server (NTRS)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  11. Skylab biomedical hardware development

    NASA Technical Reports Server (NTRS)

    Huffstetler, W. J., Jr.; Lem, J. D.

    1974-01-01

    The development of hardware to support biomedical experimentation and operations in the Skylab vehicle presented unique technical problems. Designs were required to enable the accurate measurement of many varied physiological parameters and to compensate for zero g such that uninhibited equipment operation would be possible. Because of problems that occurred during the orbital workshop launch, special tests were run and new equipment was designed and built for use by the first Skylab crew. Design concepts used in the development of hardware to support cardiovascular, pulmonary, vestibular, body, and specimen mass measuring experiments are discussed. Additionally, major problem areas and the corresponding design solutions, as well as knowledge gained that will be pertinent for future life sciences hardware development, are presented.

  12. Computer hardware fault administration

    DOEpatents

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  13. Removal of broken hardware.

    PubMed

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful.

  14. DCSP hardware maintenance system

    SciTech Connect

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  15. Hardware Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  16. Sterilization of space hardware.

    NASA Technical Reports Server (NTRS)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  17. RRFC hardware operation manual

    SciTech Connect

    Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

    1996-05-01

    The Research Reactor Fuel Counter (RRFC) system was developed to assay the {sup 235}U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the {sup 235}U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics.

  18. Parameterized hardware description as object oriented hardware model implementation

    NASA Astrophysics Data System (ADS)

    Drabik, Pawel K.

    2010-09-01

    The paper introduces novel model for design, visualization and management of complex, highly adaptive hardware systems. The model settles component oriented environment for both hardware modules and software application. It is developed on parameterized hardware description research. Establishment of stable link between hardware and software, as a purpose of designed and realized work, is presented. Novel programming framework model for the environment, named Graphic-Functional-Components is presented. The purpose of the paper is to present object oriented hardware modeling with mentioned features. Possible model implementation in FPGA chips and its management by object oriented software in Java is described.

  19. GRASS Hardware Configurations Guide

    DTIC Science & Technology

    1989-03-01

    portability rather than limit users to a single brand of hardware. Within GRASS, there are many processor inten- sive functions. Therefore, processor...Expansion Unit 2,000 558 RR13 2 60 MB. 1 4V tape drive 1.233 SYSI,2 2-User Licene N, C Total $ 26,710 $ 23,290 IhLs erem is not supplij, bv ,un Nficrosyterms...DOS world there are a ’arge number of vendors that can supply you with the basic 386 personal computer that wili work in place of the brand of computer

  20. Mir hardware heritage

    NASA Technical Reports Server (NTRS)

    Portree, David S. F.

    1995-01-01

    The heritage of the major Mir complex hardware elements is described. These elements include Soyuz-TM and Progress-M; the Kvant, Kvant 2, and Kristall modules; and the Mir base block. Configuration changes and major mission events of the Salyut 6, Salyut 7, and Mir multiport space stations are described in detail for the period 1977-1994. A comparative chronology of U.S. and Soviet/Russian manned spaceflight is also given for that period. The 68 illustrations include comparative scale drawings of U.S. and Russian spacecraft as well as sequential drawings depicting missions and mission events.

  1. Robustness in Digital Hardware

    NASA Astrophysics Data System (ADS)

    Woods, Roger; Lightbody, Gaye

    The growth in electronics has probably been the equivalent of the Industrial Revolution in the past century in terms of how much it has transformed our daily lives. There is a great dependency on technology whether it is in the devices that control travel (e.g., in aircraft or cars), our entertainment and communication systems, or our interaction with money, which has been empowered by the onset of Internet shopping and banking. Despite this reliance, there is still a danger that at some stage devices will fail within the equipment's lifetime. The purpose of this chapter is to look at the factors causing failure and address possible measures to improve robustness in digital hardware technology and specifically chip technology, giving a long-term forecast that will not reassure the reader!

  2. Hardware multiplier processor

    DOEpatents

    Pierce, P.E.

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  3. Hardware multiplier processor

    DOEpatents

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  4. Hardware Removal in Craniomaxillofacial Trauma

    PubMed Central

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  5. CHeCS Commanding Hardware

    NASA Technical Reports Server (NTRS)

    Moore, Jamie

    2010-01-01

    This slide presentation reviews the Crew Health Care System (CHeCS) commanding hardware. It includes information on the hardware status, commanding plan, and command training status with specific information the EV-CPDS 2 and 3, TEPC, MEC, and T2

  6. Flight Avionics Hardware Roadmap

    NASA Technical Reports Server (NTRS)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  7. NDAS Hardware Translation Layer Development

    NASA Technical Reports Server (NTRS)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  8. Hardware Index to Permutation Converter

    DTIC Science & Technology

    2012-05-01

    Hardware Index to Permutation Converter J. T. Butler T. Sasao Department of Electrical and Computer Engineering Department of Computer Science...generates a permutation in response to an index. Since there are n! n-element permutations , the index ranges from 0 to n! − 1. Such a circuit is needed...in the hardware implementation of unique- permutation hash functions to specify how parallel machines interact through a shared memory. Such a circuit

  9. Hardware cleanliness methodology and certification

    NASA Technical Reports Server (NTRS)

    Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

    1995-01-01

    Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

  10. Microcomputer Hardware. Energy Technology Series.

    ERIC Educational Resources Information Center

    Technical Education Research Centre-Southwest, Waco, TX.

    This course in microcomputer hardware is one of 16 courses in the Energy Technology Series developed for an Energy Conservation-and-Use Technology curriculum. Intended for use in two-year postsecondary technical institutions to prepare technicians for employment, the courses are also useful in industry for updating employees in company-sponsored…

  11. Hardware Selection: A Nontechnical Approach.

    ERIC Educational Resources Information Center

    Kiteka, Sebastian F.

    Presented in nontechnical language, this guide suggests criteria for the selection of three computer hardware essentials--a microcomputer, a monitor, and a printer. Factors to be considered in selecting the microcomputer are identified and discussed, including what the computer is to be used for, dealer support, software availability, modem…

  12. Satellite Communication Hardware Emulation System (SCHES)

    NASA Technical Reports Server (NTRS)

    Kaplan, Ted

    1993-01-01

    Satellite Communication Hardware Emulator System (SCHES) is a powerful simulator that emulates the hardware used in TDRSS links. SCHES is a true bit-by-bit simulator that models communications hardware accurately enough to be used as a verification mechanism for actual hardware tests on user spacecraft. As a credit to its modular design, SCHES is easily configurable to model any user satellite communication link, though some development may be required to tailor existing software to user specific hardware.

  13. Modular hardware synthesis using an HDL. [Hardware Description Language

    NASA Technical Reports Server (NTRS)

    Covington, J. A.; Shiva, S. G.

    1981-01-01

    Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

  14. Microbiologic assay of space hardware.

    NASA Technical Reports Server (NTRS)

    Favero, M. S.

    1971-01-01

    Review of the procedures used in the microbiological examination of space hardware. The general procedure for enumerating aerobic and anaerobic microorganisms and spores is outlined. Culture media and temperature-time cycles used for incubation are reviewed, along with assay systems designed for the enumeration of aerobic and anaerobic spores. The special problems which are discussed are involved in the precise and accurate enumeration of microorganisms on surfaces and in the neutralization of viable organisms buried inside solid materials that could be released to a planet's surface if the solid should be fractured. Special attention is given to sampling procedures including also the indirect techniques of surface assays of space hardware such as those using detachable or fallout strips. Some data on comparative levels of microbial contamination on lunar and planetary spacecraft are presented.

  15. Hardware-Accelerated Simulated Radiography

    SciTech Connect

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  16. Hardware Support for Software Debugging

    DTIC Science & Technology

    2011-05-01

    Architecture • Concurrency Debugging - ReEnact • Conclusions Cost of Software Defects • Financial Costs • In a study by NIST in 2002 it was found that... ReEnact • Leverages modified Thread-Level Speculation (TLS) hardware • Create partial orderings of threads in a multithreaded program using...logical vector clocks • Using these orderings, ReEnact is able to detect and often repair data race conditions in a multithreaded program • Experiments

  17. Hunting for hardware changes in data centres

    NASA Astrophysics Data System (ADS)

    Coelho dos Santos, M.; Steers, I.; Szebenyi, I.; Xafi, A.; Barring, O.; Bonfillou, E.

    2012-12-01

    With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

  18. A novel visual hardware behavioral language

    NASA Technical Reports Server (NTRS)

    Li, Xueqin; Cheng, H. D.

    1992-01-01

    Most hardware behavioral languages just use texts to describe the behavior of the desired hardware design. This is inconvenient for VLSI designers who enjoy using the schematic approach. The proposed visual hardware behavioral language has the ability to graphically express design information using visual parallel models (blocks), visual sequential models (processes) and visual data flow graphs (which consist of primitive operational icons, control icons, and Data and Synchro links). Thus, the proposed visual hardware behavioral language can not only specify hardware concurrent and sequential functionality, but can also visually expose parallelism, sequentiality, and disjointness (mutually exclusive operations) for the hardware designers. That would make the hardware designers capture the design ideas easily and explicitly using this visual hardware behavioral language.

  19. Hardware and software reliability estimation using simulations

    NASA Technical Reports Server (NTRS)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  20. Door Hardware and Installations; Carpentry: 901894.

    ERIC Educational Resources Information Center

    Dade County Public Schools, Miami, FL.

    The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

  1. Solid-Liquid Interface Characterization Hardware

    NASA Technical Reports Server (NTRS)

    Peters, Palmer N.

    2000-01-01

    The objective is to develop enabling technology to characterize the solid-liquid interface during directional solidification to unprecedented levels with real-time measurement hardware. Existing x-ray imaging hardware is combined with compact Seebeck furnaces and thermal profiling hardware, under development, to accomplish the measurements. Furnace thermal profiles are continuously measured in addition to the sample characteristics.

  2. Exascale Hardware Architectures Working Group

    SciTech Connect

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared to memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is

  3. GENI: Grid Hardware and Software

    SciTech Connect

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  4. Electronic processing and control system with programmable hardware

    NASA Technical Reports Server (NTRS)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  5. Product Assurance for Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Monroe, Mike

    1995-01-01

    This report contains information about the tasks I have completed and the valuable experience I have gained at NASA. The report is divided into two different sections followed by a program summary sheet. The first section describes the two reports I have completed for the Office of Mission Assurance (OMA). I describe the approach and the resources and facilities used to complete each report. The second section describes my experience working in the Receipt Inspection/Quality Assurance Lab (RI/QA). The first report described is a Product Assurance Plan for the Gas Permeable Polymer Materials (GPPM) mission. The purpose of the Product Assurance Plan is to define the various requirements which are to be met through completion of the GPPM mission. The GPPM experiment is a space payload which will be flown in the shuttle's SPACEHAB module. The experiment will use microgravity to enable production of complex polymeric gas permeable materials. The second report described in the first section is a Fracture Analysis for the Mir Environmental Effects Payload (MEEP). The Fracture Analysis report is a summary of the fracture control classifications for all structural elements of the MEEP. The MEEP hardware consists of four experiment carriers, each of which contains an experiment container holding a passive experiment. The MEEP hardware will be attached to the cargo bay of the space shuttle. It will be transferred by Extravehicular Activity and mounted on the Mir space station. The second section of this report describes my experiences in the RVQA lab. I listed the different equipment I used at the lab and their functions. I described the extensive inspection process that must be completed for spaceflight hardware. Included, at the end of this section, are pictures of most of the equipment used in the lab. There is a summary sheet located at the end of this report. It briefly describes the valuable experience I have gained at NASA this summer and what I will be able to take

  6. Automated reuseable components system study results

    NASA Technical Reports Server (NTRS)

    Gilroy, Kathy

    1989-01-01

    The Automated Reusable Components System (ARCS) was developed under a Phase 1 Small Business Innovative Research (SBIR) contract for the U.S. Army CECOM. The objectives of the ARCS program were: (1) to investigate issues associated with automated reuse of software components, identify alternative approaches, and select promising technologies, and (2) to develop tools that support component classification and retrieval. The approach followed was to research emerging techniques and experimental applications associated with reusable software libraries, to investigate the more mature information retrieval technologies for applicability, and to investigate the applicability of specialized technologies to improve the effectiveness of a reusable component library. Various classification schemes and retrieval techniques were identified and evaluated for potential application in an automated library system for reusable components. Strategies for library organization and management, component submittal and storage, and component search and retrieval were developed. A prototype ARCS was built to demonstrate the feasibility of automating the reuse process. The prototype was created using a subset of the classification and retrieval techniques that were investigated. The demonstration system was exercised and evaluated using reusable Ada components selected from the public domain. A requirements specification for a production-quality ARCS was also developed.

  7. Electronic hardware implementations of neutral networks

    NASA Technical Reports Server (NTRS)

    Thakoor, A. P.; Moopenn, A.; Lambe, John; Khanna, S. K.

    1987-01-01

    This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

  8. Hardware Implementation of Singular Value Decomposition

    NASA Astrophysics Data System (ADS)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  9. Constructing Hardware in a Scale Embedded Language

    SciTech Connect

    Bachan, John

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

  10. Open-source hardware for medical devices

    PubMed Central

    2016-01-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device. PMID:27158528

  11. Thermal Hardware for the Thermal Analyst

    NASA Technical Reports Server (NTRS)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  12. Manipulation hardware for microgravity research

    SciTech Connect

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. ); Rohn, D.A. . Lewis Research Center); Miller, J.H. )

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  13. Life Sciences Division Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Yost, B.

    1999-01-01

    The Ames Research Center (ARC) is responsible for the development, integration, and operation of non-human life sciences payloads in support of NASA's Gravitational Biology and Ecology (GB&E) program. To help stimulate discussion and interest in the development and application of novel technologies for incorporation within non-human life sciences experiment systems, three hardware system models will be displayed with associated graphics/text explanations. First, an Animal Enclosure Model (AEM) will be shown to communicate the nature and types of constraints physiological researchers must deal with during manned space flight experiments using rodent specimens. Second, a model of the Modular Cultivation System (MCS) under development by ESA will be presented to highlight technologies that may benefit cell-based research, including advanced imaging technologies. Finally, subsystems of the Cell Culture Unit (CCU) in development by ARC will also be shown. A discussion will be provided on candidate technology requirements in the areas of specimen environmental control, biotelemetry, telescience and telerobotics, and in situ analytical techniques and imaging. In addition, an overview of the Center for Gravitational Biology Research facilities will be provided.

  14. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  15. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib....

  16. 16 CFR 1509.7 - Hardware.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be... abuse. (b) Non-full-size baby cribs shall incorporate locking or latching devices for dropsides or... non-full-size baby crib....

  17. 16 CFR 1508.6 - Hardware.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 16 Commercial Practices 2 2011-01-01 2011-01-01 false Hardware. 1508.6 Section 1508.6 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner...

  18. Computer hardware description languages - A tutorial

    NASA Technical Reports Server (NTRS)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  19. Tinker's Toys: Lessons from Bank Street: Hardware.

    ERIC Educational Resources Information Center

    Tinker, Robert

    1985-01-01

    Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

  20. Returned Solar Max hardware degradation study results

    NASA Technical Reports Server (NTRS)

    Triolo, Jack J.; Ousley, Gilbert W.

    1989-01-01

    The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized.

  1. Hardware survey for the avionics test bed

    NASA Technical Reports Server (NTRS)

    Cobb, J. M.

    1981-01-01

    A survey of maor hardware items that could possibly be used in the development of an avionics test bed for space shuttle attached or autonomous large space structures was conducted in NASA Johnson Space Center building 16. The results of the survey are organized to show the hardware by laboratory usage. Computer systems in each laboratory are described in some detail.

  2. An evaluation of Skylab habitability hardware

    NASA Technical Reports Server (NTRS)

    Stokes, J.

    1974-01-01

    For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

  3. Hardware Removal after Osseous Free Flap Reconstruction

    PubMed Central

    Day, Kristine E.; Desmond, Renee; Magnuson, J. Scott; Carroll, William R.; Rosenthal, Eben L.

    2015-01-01

    Objective Identifying risk factors for hardware removal in patients undergoing mandibular reconstruction with vascularized osseous free flaps remains a challenge. The purpose of this study is to identify potential risk factors, including osteocutaneous radial forearm versus fibular flap, for need for removal and to describe the fate of implanted hardware. Study Design Case series with chart review. Setting Academic tertiary care medical center. Subjects and Methods Two hundred thirteen patients undergoing 227 vascularized osseous mandibular reconstructions between the years 2004 and 2012. Data were compiled through a manual chart review, and patients incurring hardware removals were identified. Results Thirty-four of 213 evaluable vascularized osseous free flaps (16%) underwent surgical removal of hardware. The average length of time to removal was 16.2 months (median 10 months), with the majority of removals occurring within the first year. Osteocutaneous radial forearm free flaps (OCRFFF) incurred a slightly higher percentage of hardware removals (9.9%) compared to fibula flaps (6.1%). Partial removal was performed in 8 of 34 cases, and approximately 38% of these required additional surgery for removal. Conclusion Hardware removal was associated with continued tobacco use after mandibular reconstruction (P = .03). Removal of the supporting hardware most commonly occurs from infection or exposure in the first year. In the majority of cases the bone is well healed and the problem resolves with removal. PMID:24201061

  4. Space shuttle main engine hardware simulation

    NASA Technical Reports Server (NTRS)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  5. Applying a Genetic Algorithm to Reconfigurable Hardware

    NASA Technical Reports Server (NTRS)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  6. Optical Properties of Nanosatellite Hardware

    NASA Technical Reports Server (NTRS)

    Finckenor, M. M.; Coker, R. F.

    2014-01-01

    Over the last decade, a number of very small satellites have been launched into space. These have been called nanosatellites (generally of a weight between 1 and 10 kg) or picosatellites (weight <1 kg). This also includes CubeSats, which are based on 10-cm cube units. With the addition of the Japanese Experiment Module (JEM) Small Satellite Orbital Deployer (J-SSOD) to the International Space Station (ISS), CubeSats are easily cycled through the JEM airlock and deployed into space (fig. 1). The number of CubeSats launched since 2003 was approaching 100 at the time of publication, and the authors expect this trend in research to continue, particularly for high school and college flight experiments. Because these spacecraft are so small, there is usually no allowance for shielding or active heating or cooling of the avionics and other hardware. Parts that are usually ignored in the thermal analysis of larger spacecraft may contribute significantly to the heat load of a tiny satellite. In addition, many small satellites have commercial-off-the-shelf (COTS) components. To reduce costs, many providers of COTS components do not include the optical and physical parameters necessary for accurate thermal analysis. Marshall Space Flight Center participated in the development and analysis of the Space Missile Defense Command-Operational Nanosatellite Effect (SMDC-ONE) and the Edison Demonstration of Smallsat Networks (EDSN) nanosatellites. These optical property measurements are documented here in hopes that they may benefit future nanosatellite and picosatellite programs and aid thermal analysis to ensure project goals are met, with the understanding that material properties may vary by vendor, batch, manufacturing process, and preflight handling. Where possible, complementary data are provided from ground simulations of the space environment and flight experiments, such as the Materials on International Space Station Experiment (MISSE) series. NASA gives no recommendation

  7. Rapid Production of Composite Prototype Hardware

    NASA Technical Reports Server (NTRS)

    DeLay, T. K.

    2000-01-01

    The objective of this research was to provide a mechanism to cost-effectively produce composite hardware prototypes. The task was to take a hands-on approach to developing new technologies that could benefit multiple future programs.

  8. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    Inertial Upper Stage (IUS) and DoD Communication Interface Unit (CIU) communication system design, hardware specifications, and interfaces were evaluated to determine their compatibility with the Orbiter payload communication and data handling equipment and the Orbiter network communication equipment.

  9. Hardware device binding and mutual authentication

    DOEpatents

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  10. Development of robotics facility docking test hardware

    NASA Technical Reports Server (NTRS)

    Loughead, T. E.; Winkler, R. V.

    1984-01-01

    Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

  11. IDD Archival Hardware Architecture and Workflow

    SciTech Connect

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  12. Towards composition of verified hardware devices

    NASA Technical Reports Server (NTRS)

    Schubert, E. Thomas; Levitt, K.; Cohen, G. C.

    1991-01-01

    Computers are being used where no affordable level of testing is adequate. Safety and life critical systems must find a replacement for exhaustive testing to guarantee their correctness. Through a mathematical proof, hardware verification research has focused on device verification and has largely ignored system composition verification. To address these deficiencies, we examine how the current hardware verification methodology can be extended to verify complete systems.

  13. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    SciTech Connect

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  14. VEG-01: Veggie Hardware Verification Testing

    NASA Technical Reports Server (NTRS)

    Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

    2013-01-01

    The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

  15. Economic impact of syndesmosis hardware removal.

    PubMed

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system.

  16. Extravehicular Activity training and hardware design considerations

    NASA Technical Reports Server (NTRS)

    Thuot, Pierre J.; Harbaugh, Gregory J.

    1993-01-01

    Designing hardware that can be successfully operated by EVA astronauts for EVA tasks required to assemble and maintain Space Station Freedom requires a thorough understanding of human factors and of the capabilities and limitations of the space-suited astronaut, as well as of the effect of microgravity environment on the crew member's capabilities and on the overhead associated with EVA. This paper describes various training methods and facilities that are being designed for training EVA astronauts for Space Station assembly and maintenance, taking into account the above discussed factors. Particular attention is given to the user-friendly hardware design for EVA and to recent EVA flight experience.

  17. Language of CTO interventions - Focus on hardware.

    PubMed

    Mishra, Sundeep

    2016-01-01

    The knowledge of variety of chronic total occlusion (CTO) hardware and the ability to use them represents the key to success of any CTO interventions. However, the multiplicity of CTO hardware and their physical character and the terminology used by experts create confusion in the mind of an average interventional cardiologist, particularly a beginner in this field. This knowledge is available but is scattered. We aim to classify and compare the currently used devices based on their properties focusing on how physical character of each device can be utilized in a specific situation, thus clarifying and simplifying the technical discourse.

  18. Human Centered Hardware Modeling and Collaboration

    NASA Technical Reports Server (NTRS)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  19. Circulation control lift generation experiment: Hardware development

    NASA Technical Reports Server (NTRS)

    Panontin, T. L.

    1985-01-01

    A circulation control airfoil and its accompanying hardware were developed to allow the investigation of lift generation that is independent of airfoil angle of attack and relative flow velocity. The test equipment, designed for use in a water tunnel, includes the blown airfoil, the support systems for both flow visualization and airfoil load measurement, and the fluid control system, which utilizes hydraulic technology. The primary design tasks, the selected solutions, and the unforseen problems involved in the development of these individual components of hardware are described.

  20. Magnetic Field Apparatus (MFA) Hardware Test

    NASA Technical Reports Server (NTRS)

    Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

    1999-01-01

    The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

  1. Defining and Enforcing Hardware Security Requirements

    DTIC Science & Technology

    2011-12-01

    26. Suffix implication example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. Checker automaton example...Programmable Gate Array FSM Finite State Machine HDL Hardware Design Language IBM International Business Machines Corporation IC Integrated Circuit IEEE...notes, “almost all Field Programmable Gate Arrays (FPGAs) are now made at foundries outside the U.S., about 80 percent of them in Taiwan. Defense

  2. Support for Diagnosis of Custom Computer Hardware

    NASA Technical Reports Server (NTRS)

    Molock, Dwaine S.

    2008-01-01

    The Coldfire SDN Diagnostics software is a flexible means of exercising, testing, and debugging custom computer hardware. The software is a set of routines that, collectively, serve as a common software interface through which one can gain access to various parts of the hardware under test and/or cause the hardware to perform various functions. The routines can be used to construct tests to exercise, and verify the operation of, various processors and hardware interfaces. More specifically, the software can be used to gain access to memory, to execute timer delays, to configure interrupts, and configure processor cache, floating-point, and direct-memory-access units. The software is designed to be used on diverse NASA projects, and can be customized for use with different processors and interfaces. The routines are supported, regardless of the architecture of a processor that one seeks to diagnose. The present version of the software is configured for Coldfire processors on the Subsystem Data Node processor boards of the Solar Dynamics Observatory. There is also support for the software with respect to Mongoose V, RAD750, and PPC405 processors or their equivalents.

  3. Microprocessor Design Using Hardware Description Language

    ERIC Educational Resources Information Center

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  4. Digital Hardware Design Teaching: An Alternative Approach

    ERIC Educational Resources Information Center

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  5. Simultaneous-Frequency Nonlinear Radar: Hardware Simulation

    DTIC Science & Technology

    2015-08-01

    Army Research Laboratory Simultaneous-Frequency Nonlinear Radar : Hardware Simulation by Gregory J Mazzaro, Kenneth I Ranney, Kyle A Gallagher...distribution unlimited. NOTICES Disclaimers The findings in this report are not to be construed as an official Department of the Army position

  6. Postflight hardware evaluation (RSRM-29, STS-54)

    NASA Astrophysics Data System (ADS)

    1993-09-01

    This document is the final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-29 flight set. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64221), represents a summary of the RSRM-29 hardware evaluation. Disassembly evaluation photograph numbers are logged in TWA-1990. The RSRM-29 flight set disassembly evaluations described in this document were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on September 9, 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  7. Formal hardware verification of digital circuits

    NASA Technical Reports Server (NTRS)

    Joyce, J.; Seger, C.-J.

    1991-01-01

    The use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.

  8. Computer hardware for radiologists: Part I.

    PubMed

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  9. Transistor Level Circuit Experiments using Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  10. Hardware Acceleration of Sparse Cognitive Algorithms

    DTIC Science & Technology

    2016-05-01

    15. SUBJECT TERMS Cortical Algorithms; Machine Learning ; Hardware; VLSI; ASIC 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT: SAR...Approved for public release; distribution unlimited. Table of Contents Section Page List of Figures... integrated circuit (ASIC) in which certain parameters can be changed at compile time and/or run time. However, it can only run one version of the

  11. Shuttle mission simulator hardware conceptual design report

    NASA Technical Reports Server (NTRS)

    Burke, J. F.

    1973-01-01

    The detailed shuttle mission simulator hardware requirements are discussed. The conceptual design methods, or existing technology, whereby those requirements will be fulfilled are described. Information of a general nature on the total design problem plus specific details on how these requirements are to be satisfied are reported. The configuration of the simulator is described and the capabilities for various types of training are identified.

  12. Codem: software/hardware codesign for embedded multicore systems supporting hardware services

    NASA Astrophysics Data System (ADS)

    Wang, Chao; Li, Xi; Zhou, Xuehai; Nedjah, Nadia; Wang, Aili

    2015-01-01

    Efficient software/hardware codesign is posing significant challenges to embedded systems. This paper proposes Codem, a software/hardware codesign flow for embedded systems, which models both processors and Intellectual Property (IP) cores as services. Tasks are regarded as abstract instructions which can be scheduled to IP cores for parallel execution automatically. In order to guide the hardware implementations of the hot spot functions, this paper incorporates a novel hot spot-based profiling technique to observe the hot spot functions while the application is being simulated. Furthermore, based on the hot spot of various applications, an adaptive mapping algorithm is presented to partition the application into multiple software/hardware tasks. We test the profiling-based design flow with classic Sort applications. Experimental results demonstrate that Codem can efficiently help researchers to identify the hot spots, and also outline a new direction to combine profiling techniques with state-of-the-art reconfigurable computing platforms for specific task acceleration.

  13. Design guidelines for robotically serviceable hardware

    NASA Technical Reports Server (NTRS)

    Gordon, Scott A.

    1988-01-01

    Research being conducted at the Goddard Space Flight Center into the development of guidelines for the design of robotically serviceable spaceflight hardware is described. A mock-up was built based on an existing spaceflight system demonstrating how these guidelines can be applied to actual hardware. The report examines the basic servicing philosophy being studied and how this philosophy is reflected in the formulation of design guidelines for robotic servicing. A description of the mock-up is presented with emphasis on the design features that make it robot friendly. Three robotic servicing schemes fulfilling the design guidelines were developed for the mock-up. These servicing schemes are examined as to how their implementation was affected by the constraints of the spacecraft system on which the mock-up is based.

  14. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    SciTech Connect

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  15. Verifying Dissolution Of Wax From Hardware Surfaces

    NASA Technical Reports Server (NTRS)

    Montoya, Benjamina G.

    1995-01-01

    Wax removed by cleaning solvent revealed by cooling solution with liquid nitrogen. Such improved procedure and test needed in case of hardware that must be protected by wax during machining or plating but required to be free of wax during subsequent use. Improved cleaning procedure and test take less than 5 minutes. Does not require special skill or equipment and performs at cleaning site. In addition, enables recovery of all cleaning solvent.

  16. Hardware-Independent Proofs of Numerical Programs

    NASA Technical Reports Server (NTRS)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  17. Testing Microshutter Arrays Using Commercial FPGA Hardware

    NASA Technical Reports Server (NTRS)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  18. Reconfigurable Hardware Adapts to Changing Mission Demands

    NASA Technical Reports Server (NTRS)

    2003-01-01

    A new class of computing architectures and processing systems, which use reconfigurable hardware, is creating a revolutionary approach to implementing future spacecraft systems. With the increasing complexity of electronic components, engineers must design next-generation spacecraft systems with new technologies in both hardware and software. Derivation Systems, Inc., of Carlsbad, California, has been working through NASA s Small Business Innovation Research (SBIR) program to develop key technologies in reconfigurable computing and Intellectual Property (IP) soft cores. Founded in 1993, Derivation Systems has received several SBIR contracts from NASA s Langley Research Center and the U.S. Department of Defense Air Force Research Laboratories in support of its mission to develop hardware and software for high-assurance systems. Through these contracts, Derivation Systems began developing leading-edge technology in formal verification, embedded Java, and reconfigurable computing for its PF3100, Derivational Reasoning System (DRS ), FormalCORE IP, FormalCORE PCI/32, FormalCORE DES, and LavaCORE Configurable Java Processor, which are designed for greater flexibility and security on all space missions.

  19. Fast Hardware Implementation Of The DOLP Transform

    NASA Astrophysics Data System (ADS)

    Waltz, Frederick M.

    1988-03-01

    The Difference-of-Low-Pass (DOLP) Transform uses a hierarchy of bandpass filters to perform size discrimination and pattern matching of objects and features in a visual field. Like the Discrete Fourier Transform (DFT), it "sorts" entities according to their size or spatial frequencies; but unlike the DFT, it also retains positional information.This positional information is essential for the very common industrial web inspection problem in which a "flaw map" must be produced - mere flaw detection (as provided by the DFT) is not enough. The DOLP Transform is usually implemented using finite-impulse-response difference-of-Gaussian (DOG) filters of progressively increasing kernel size. Various potential industrial applications have been described and demonstrated, but implementations have been hampered by the heavy computational burden involved in the generation of the Transform. This paper describes a fast implementation of Crowley's resampled DOLP Transform using commercially-available board-level hardware. With a moderate investment in hardware modules, a nine-band DOLP Transform can be computed for a 485 by 512 image in about one second. Additional hardware modules could be added to bring the speed up to 30 complete 9-band Transforms per second, if desired. Additional bands beyond the first nine, while seldom needed, require very little additional time, because the image has been repeatedly resampled down to a small size.

  20. "Greenbook Algorithms and Hardware Needs Analysis"

    SciTech Connect

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  1. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    NASA Technical Reports Server (NTRS)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  2. The Impact of Flight Hardware Scavenging on Space Logistics

    NASA Technical Reports Server (NTRS)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  3. Summary of materials and hardware performance on LDEF

    NASA Technical Reports Server (NTRS)

    Dursch, Harry; Pippin, Gary; Teichman, Lou

    1993-01-01

    A wide variety of materials and experiment support hardware were flown on the Long Duration Exposure Facility (LDEF). Postflight testing has determined the effects of the almost 6 years of low-earth orbit (LEO) exposure on this hardware. An overview of the results are presented. Hardware discussed includes adhesives, fasteners, lubricants, data storage systems, solar cells, seals, and the LDEF structure. Lessons learned from the testing and analysis of LDEF hardware is also presented.

  4. Safe to Fly: Certifying COTS Hardware for Spaceflight

    NASA Technical Reports Server (NTRS)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  5. CHeCS: International Space Station Medical Hardware Catalog

    NASA Technical Reports Server (NTRS)

    2008-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  6. Is Hardware Removal Recommended after Ankle Fracture Repair?

    PubMed Central

    Jung, Hong-Geun; Kim, Jin-Il; Park, Jae-Yong; Park, Jong-Tae; Eom, Joon-Sang

    2016-01-01

    The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients' daily activities. This study was conducted on 80 consecutive cases (78 patients) treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6) and decreased to 1.3 (range 0 to 6) after removal. 58 (72.5%) patients experienced improved ankle stiffness and 65 (81.3%) less discomfort while walking on uneven ground and 63 (80.8%) patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal. PMID:27819005

  7. Computer hardware for radiologists: Part 2

    PubMed Central

    Indrajit, IK; Alam, A

    2010-01-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future. PMID:21423895

  8. Open Source Hardware for DIY Environmental Sensing

    NASA Astrophysics Data System (ADS)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  9. Computer hardware for radiologists: Part 2.

    PubMed

    Indrajit, Ik; Alam, A

    2010-11-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

  10. A building block for hardware belief networks

    PubMed Central

    Behin-Aein, Behtash; Diep, Vinh; Datta, Supriyo

    2016-01-01

    Belief networks represent a powerful approach to problems involving probabilistic inference, but much of the work in this area is software based utilizing standard deterministic hardware based on the transistor which provides the gain and directionality needed to interconnect billions of them into useful networks. This paper proposes a transistor like device that could provide an analogous building block for probabilistic networks. We present two proof-of-concept examples of belief networks, one reciprocal and one non-reciprocal, implemented using the proposed device which is simulated using experimentally benchmarked models. PMID:27443521

  11. Orbiter CIU/IUS communications hardware evaluation

    NASA Technical Reports Server (NTRS)

    Huth, G. K.

    1979-01-01

    The DOD and NASA inertial upper stage communication system design, hardware specifications and interfaces were analyzed to determine their compatibility with the Orbiter payload communications equipment (Payload Interrogator, Payload Signal Processors, Communications Interface Unit, and the Orbiter operational communications equipment (the S-Band and Ku-band systems). Topics covered include (1) IUS/shuttle Orbiter communications interface definition; (2) Orbiter avionics equipment serving the IUS; (3) IUS communication equipment; (4) IUS/shuttle Orbiter RF links; (5) STDN/TDRS S-band related activities; and (6) communication interface unit/Orbiter interface issues. A test requirement plan overview is included.

  12. Open Hardware for CERN's accelerator control systems

    NASA Astrophysics Data System (ADS)

    van der Bij, E.; Serrano, J.; Wlostowski, T.; Cattin, M.; Gousiou, E.; Alvarez Sanchez, P.; Boccardi, A.; Voumard, N.; Penacoba, G.

    2012-01-01

    The accelerator control systems at CERN will be upgraded and many electronics modules such as analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on the FPGA Mezzanine Card, PCI Express and VME64x standards while the Wishbone specification is used as a system on a chip bus. To attract partners, the projects are developed in an `Open' fashion. Within this Open Hardware project new ways of working with industry are being evaluated and it has been proven that industry can be involved at all stages, from design to production and support.

  13. Reconfigurable Hardware for Compressing Hyperspectral Image Data

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

    2010-01-01

    High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

  14. FORTE hardware-in-loop simulation

    SciTech Connect

    Ruud, K.K.; Murray, H.S.; Moore, T.K.

    1997-12-01

    Fast On-Orbit Recording of Transient Events (FORTE) is a small, low Earth orbit satellite scheduled for launch in August 1997. FORTE is a momentum-biased, gravity-gradient stabilized spacecraft. This paper describes the use of a hardware-in-loop simulator, developed by Ithaco Inc. and Los Alamos National Laboratory, in performing FORTE mission simulations. Scenarios studied include separation, acquisition on orbit, control system parameter sensitivity studies, sensor noise simulations, antenna deployment and momentum desaturation. Use of the simulator to refine control algorithms and sequences is also described.

  15. Workmanship Challenges for NASA Mission Hardware

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette

    2010-01-01

    This slide presentation reviews several challenges in workmanship for NASA mission hardware development. Several standards for NASA workmanship exist, that are required for all programs, projects, contracts and subcontracts. These Standards contain our best known methods for avoiding past assembly problems and defects. These best practices may not be available if suppliers are used who are not compliant with them. Compliance includes having certified operators and inspectors. Some examples of problems that have occured from the lack of requirements flow-down to contractors are reviewed. The presentation contains a detailed example of the challenge in regards to The Packaging "Design" Dilemma.

  16. INTEGRATED MONITORING HARDWARE DEVELOPMENTS AT LOS ALAMOS

    SciTech Connect

    R. PARKER; J. HALBIG; ET AL

    1999-09-01

    The hardware of the integrated monitoring system supports a family of instruments having a common internal architecture and firmware. Instruments can be easily configured from application-specific personality boards combined with common master-processor and high- and low-voltage power supply boards, and basic operating firmware. The instruments are designed to function autonomously to survive power and communication outages and to adapt to changing conditions. The personality boards allow measurement of gross gammas and neutrons, neutron coincidence and multiplicity, and gamma spectra. In addition, the Intelligent Local Node (ILON) provides a moderate-bandwidth network to tie together instruments, sensors, and computers.

  17. Cathode side hardware for carbonate fuel cells

    DOEpatents

    Xu, Gengfu; Yuh, Chao-Yi

    2011-04-05

    Carbonate fuel cathode side hardware having a thin coating of a conductive ceramic formed from one of Perovskite AMeO.sub.3, wherein A is at least one of lanthanum and a combination of lanthanum and strontium and Me is one or more of transition metals, lithiated NiO (Li.sub.xNiO, where x is 0.1 to 1) and X-doped LiMeO.sub.2, wherein X is one of Mg, Ca, and Co.

  18. Available hardware for automated entry control

    SciTech Connect

    Holmes, J.P.

    1990-11-01

    Automated entry control has become an increasingly important issue at facilities where budget constraints are limiting options for manned entry control points. Three questions are immediately raised when automated entry control is considered: What hardware is available How much does it cost How effective is it in maintaining security Ongoing work at Sandia National Labs is attempting to answer these questions and establish a data base for use by facility security managers working the problem of how to maintain security on a limited budget. 14 refs.

  19. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    NASA Technical Reports Server (NTRS)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  20. Analysis of systems hardware flown on LDEF: New findings and comparison to other retrieved spacecraft hardware

    NASA Technical Reports Server (NTRS)

    Dursch, Harry; Bohnhoff-Hlavacek, Gail; Blue, Donald; Hansen, Patricia

    1995-01-01

    The Long Duration Exposure Facility (LDEF) was retrieved in 1990 after spending 69 months in low-earth-orbit (LEO). A wide variety of mechanical, electrical, thermal, and optical systems, subsystems, and components were flown on LDEF. The Systems Special Investigation Group (Systems SIG) was formed by NASA to investigate the effects of the 69 month exposure on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware. This report is the Systems SIG final report which updates earlier findings and compares LDEF systems findings to results from other retrieved spacecraft hardware such as Hubble Space Telescope. Also included are sections titled (1) Effects of Long Duration Space Exposure on Optical Scatter, (2) Contamination Survey of LDEF, and (3) Degradation of Optical Materials in Space.

  1. Combined hardware and software models of reliability and availability for configuration with redundant hardware

    NASA Astrophysics Data System (ADS)

    Xu, Bin; Yao, Yiping

    This paper consists of three parts; in the first part, the development of combined hardware and software reliability analysis methods is summarized. In the second part, the prerequisite of modeling and two combined HW/SW reliability and availability models are presented. While the theoretical analytical model is based on Markov renewal processes, the numerical model is based on Markov processes. In the third part, the numerical model has been used to analyze the HW/SW reliability and availability for Fly-By-Wire flight control system configuration with redundant hardware in numerical quantities.

  2. ISS Logistics Hardware Disposition and Metrics Validation

    NASA Technical Reports Server (NTRS)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  3. CASIS Fact Sheet: Hardware and Facilities

    NASA Technical Reports Server (NTRS)

    Solomon, Michael R.; Romero, Vergel

    2016-01-01

    Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

  4. Hardware development process for Human Research facility applications

    NASA Astrophysics Data System (ADS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. .

  5. HOP: (Hardware Viewed as Objects and Processes). A Process Model for Synchronous Hardware Systems

    DTIC Science & Technology

    1988-01-01

    that was based on an abstract data type view of hardware systems into a new, simple, and deterministic process model that we have invented. Our process ... model is inspired by the works of Mil82, Mil83, and Hoa85. Secondly it is believed that not only should an HSL be founded in mathematical principles

  6. Locating hardware faults in a parallel computer

    DOEpatents

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  7. Extensible Hardware Architecture for Mobile Robots

    NASA Technical Reports Server (NTRS)

    Park, Eric; Kobayashi, Linda; Lee, Susan Y.

    2005-01-01

    The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

  8. Extravehicular Activity (EVA) Hardware & Operations Overview

    NASA Technical Reports Server (NTRS)

    Moore, Sandra; Marmolejo, Jose

    2014-01-01

    The objectives of this presentation are to: Define Extravehicular Activity (EVA), identify the reasons for conducting an EVA, and review the role that EVA has played in the space program; Identify the types of EVAs that may be performed; Describe some of the U.S. Space Station equipment and tools that are used during an EVA, such as the Extravehicular Mobility Unit (EMU), the Simplified Aid For EVA Rescue (SAFER), the International Space Station (ISS) Joint Airlock and Russian Docking Compartment 1 (DC-1), and EVA Tools & Equipment; Outline the methods and procedures of EVA Preparation, EVA, and Post-EVA operations; Describe the Russian spacesuit used to perform an EVA; Provide a comparison between U.S. and Russian spacesuit hardware and EVA support; and Define the roles that different training facilities play in EVA training.

  9. Hardware implementation of stochastic spiking neural networks.

    PubMed

    Rosselló, Josep L; Canals, Vincent; Morro, Antoni; Oliver, Antoni

    2012-08-01

    Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

  10. Compressive Sensing Image Sensors-Hardware Implementation

    PubMed Central

    Dadkhah, Mohammadreza; Deen, M. Jamal; Shirani, Shahram

    2013-01-01

    The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed. PMID:23584123

  11. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discuss the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of the population, n, and the number of generations required for the population to converge, ngen, based on L, the length of the programming string. We show that the processing time of the computer becomes negligible for intrinsic EHW since the selection/crossover/mutation steps are only done once per generation, suggesting there is room for use of more complex evolutionary algorithms m intrinsic EHW. F i y , we review the state of the practice and discuss the notion of a system design approach for intrinsic EHW.

  12. EPICS: Allen-Bradley hardware reference manual

    SciTech Connect

    Nawrocki, G.

    1993-04-05

    This manual covers the following hardware: Allen-Bradley 6008 -- SV VMEbus I/O scanner; Allen-Bradley universal I/O chassis 1771-A1B, -A2B, -A3B, and -A4B; Allen-Bradley power supply module 1771-P4S; Allen-Bradley 1771-ASB remote I/O adapter module; Allen-Bradley 1771-IFE analog input module; Allen-Bradley 1771-OFE analog output module; Allen-Bradley 1771-IG(D) TTL input module; Allen-Bradley 1771-OG(d) TTL output; Allen-Bradley 1771-IQ DC selectable input module; Allen-Bradley 1771-OW contact output module; Allen-Bradley 1771-IBD DC (10--30V) input module; Allen-Bradley 1771-OBD DC (10--60V) output module; Allen-Bradley 1771-IXE thermocouple/millivolt input module; and the Allen-Bradley 2705 RediPANEL push button module.

  13. Hardware development for Gravity Probe-B

    NASA Technical Reports Server (NTRS)

    Bardas, D.; Cheung, W. S.; Gill, D.; Hacker, R.; Keiser, G. M.

    1986-01-01

    Gravity Probe-B (GP-B), also known as the Stanford Relativity Gyroscope Experiment, will test two fundamental predictions of Einstein's General Theory of Relativity by precise measurement of the precessions of nearly perfect gyroscopes in earth orbit. This endeavor embodies state-of-the-art technologies in many fields, including gyroscope fabrication and readout, cryogenics, superconductivity, magnetic shielding, precision optics and alignment methods, and satellite control systems. These technologies are necessary to enable measurement of the predicted precession rates to the milliarcsecond/year level, and to reduce to 'near zero' all non-General Relativistic torques on the gyroscopes. This paper provides a brief overview of the experiment followed by descriptions of several specific hardware items with highlights on progress to date and plans for future development and tests.

  14. Dual control vibration tests of flight hardware

    NASA Astrophysics Data System (ADS)

    Scharton, Terry D.

    A vibration retest of a spacecraft flight instrument, the Mars Observer Camera (MOC), was conducted using extremal dual control to automatically limit the shaker force and notch the shaker acceleration at resonances. This was the first application of extremal dual control with flight hardware at JPL. The retest was successful in that the environment was representative of flight plus some margin, the instrument survived without any structural or performance degradation, and the force limiting worked very well. The test set-up, force limiting procedure, and test results are described herein. It is concluded that dual control should be utilized when there is a concern about overtesting in hard-base-drive tests and the instrumentation for force measurement and control is available. Recommendations for improving the implementation of dual control are provided as a result of this first experience.

  15. Design Space Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

  16. Environmental testing for new SOFIA flight hardware

    NASA Astrophysics Data System (ADS)

    Lachenmann, Michael; Wolf, Jürgen; Strecker, Rainer; Weckenmann, Benedikt; Trimpe, Fritz; Hall, Helen J.

    2014-07-01

    New flight hardware for the Stratospheric Observatory for Infrared Astronomy (SOFIA) has to be tested to prove its safety and functionality and to measure its performance under flight conditions. Although it is not expected to experience critical issues inside the pressurized cabin with close-to-normal conditions, all equipment has to be tested for safety margins in case of a decompression event and/or for unusual high temperatures, e.g. inside an electronic unit caused by a malfunction as well as unusual high ambient temperatures inside the cabin, when the aircraft is parked in a desert. For equipment mounted on the cavity side of the telescope, stratospheric conditions apply, i.e., temperatures from -40 °C to -60°C and an air pressure of about 0.1 bar. Besides safety aspects as not to endanger personnel or equipment, new hardware inside the cavity has to function and to perform to specifications under such conditions. To perform these tests, an environmental test laboratory was set up at the SOFIA Science Center at the NASA Ames Research Center, including a thermal vacuum chamber, temperature measurement equipment, and a control and data logging workstation. This paper gives an overview of the test and measurement equipment, shows results from the commissioning and characterization of the thermal vacuum chamber, and presents examples of the component tests that were performed so far. To test the focus position stability of optics when cooling them to stratospheric temperatures, an auto-collimation device has been developed. We will present its design and results from measurements on commercial off-the-shelf optics as candidates for the new Wide Field Imager for SOFIA as an example.

  17. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    SciTech Connect

    Williamson, D.A.

    1991-12-31

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas & Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States` utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste.

  18. APHID: Anomaly Processor in Hardware for Intrusion Detection

    DTIC Science & Technology

    2007-03-01

    APHID : Anomaly Processor in Hardware for Intrusion Detection THESIS Samuel Hart, Captain, USAF AFIT/GCE/ENG/07-04 DEPARTMENT OF THE AIR FORCE AIR...the United States Government. AFIT/GCE/ENG/07-04 APHID : Anomaly Processor in Hardware for Intrusion Detection THESIS Presented to the Faculty...Captain, USAF March 2007 APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED. AFIT/GCE/ENG/07-04 APHID : Anomaly Processor in Hardware for Intrusion

  19. Architectural Support for Detection and Recovery using Hardware Wrappers

    DTIC Science & Technology

    2013-04-01

    SECRYPT 2011, Seville, Spain 2011. 5. A. Baumgarten, M. Steffen, M. Clausman, and J. Zambreno. "A Case Study in Hardware Trojan Design and...AFRL-OSR-VA-TR-2013-0204 Architectural Support for Detection and Recovery using Hardware Wrappers Bhagirath Narahari Rahul...Include area code) 02-26-2013 FINAL REPORT March 1, 2009 - Nov 30, 2012 Architectural Support for Detection and Recovery using Hardware Wrappers

  20. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    PubMed

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  1. Environmental Friendly Coatings and Corrosion Prevention For Flight Hardware Project

    NASA Technical Reports Server (NTRS)

    Calle, Luz

    2014-01-01

    Identify, test and develop qualification criteria for environmentally friendly corrosion protective coatings and corrosion preventative compounds (CPC's) for flight hardware an ground support equipment.

  2. Hubble (HST) hardware is inspected in PHSF

    NASA Technical Reports Server (NTRS)

    1999-01-01

    In the Payload Hazardous Servicing Facility, part of the servicing equipment for the third Hubble Space Telescope Servicing Mission (SM-3A), STS-103, is given a black light inspection. The hardware is undergoing final testing and integration of payload elements. Mission STS-103 is a 'call-up' due to the need to replace portions of the Hubble's pointing system, the gyros, which have begun to fail. Although Hubble is operating normally and conducting its scientific observations, only three of its six gyroscopes are working properly. The gyroscopes allow the telescope to point at stars, galaxies and planets. The STS-103 crew will not only replace gyroscopes, it will also replace a Fine Guidance Sensor and an older computer with a new enhanced model, an older data tape recorder with a solid state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. The scheduled launch date in October is under review.

  3. Employing ISRU Models to Improve Hardware Design

    NASA Technical Reports Server (NTRS)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  4. Nanorobot Hardware Architecture for Medical Defense.

    PubMed

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C

    2008-05-06

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  5. Tests characterizing bioprocessor hardware for analytical modeling

    NASA Technical Reports Server (NTRS)

    Gustavino, S.; Mccormack, A.

    1992-01-01

    The tests outlined in this paper were used to characterize the hardware components of the Salad Machine, a small NASA-developed bioprocessor. The data from these tests are presented, and the methods by which this data can be integrated into system mathematical models are briefly discussed. The subsystems and physical processes discussed include the lighting system, the air loop (condensing heat exchanger and the blower), heat transfer to the surroundings, and leakage. Through this effort it was learned that in the development of a test protocol, care should be taken to order the tests such that environmental parameters, particularly humidity, require as few large adjustments as possible. Sensor calibration and installation take a substantial amount of time, which should be built into the test schedule. Two properties were particularly hard to quantify: the air flow rate and the energy from the lighting system entering into the growth volume. Flow rate can be measured using the appropriate device for the system configuration and airflow. Lighting system radiation level was measured using three methods. The results of these methods varied substantially, putting off conclusive quantification of this value.

  6. Fast Sparse Level Sets on Graphics Hardware.

    PubMed

    Jalba, Andrei C; van der Laan, Wladimir J; Roerdink, Jos B T M

    2013-01-01

    The level-set method is one of the most popular techniques for capturing and tracking deformable interfaces. Although level sets have demonstrated great potential in visualization and computer graphics applications, such as surface editing and physically based modeling, their use for interactive simulations has been limited due to the high computational demands involved. In this paper, we address this computational challenge by leveraging the increased computing power of graphics processors, to achieve fast simulations based on level sets. Our efficient, sparse GPU level-set method is substantially faster than other state-of-the-art, parallel approaches on both CPU and GPU hardware. We further investigate its performance through a method for surface reconstruction, based on GPU level sets. Our novel multiresolution method for surface reconstruction from unorganized point clouds compares favorably with recent, existing techniques and other parallel implementations. Finally, we point out that both level-set computations and rendering of level-set surfaces can be performed at interactive rates, even on large volumetric grids. Therefore, many applications based on level sets can benefit from our sparse level-set method.

  7. Live HDR video streaming on commodity hardware

    NASA Astrophysics Data System (ADS)

    McNamee, Joshua; Hatchett, Jonathan; Debattista, Kurt; Chalmers, Alan

    2015-09-01

    High Dynamic Range (HDR) video provides a step change in viewing experience, for example the ability to clearly see the soccer ball when it is kicked from the shadow of the stadium into sunshine. To achieve the full potential of HDR video, so-called true HDR, it is crucial that all the dynamic range that was captured is delivered to the display device and tone mapping is confined only to the display. Furthermore, to ensure widespread uptake of HDR imaging, it should be low cost and available on commodity hardware. This paper describes an end-to-end HDR pipeline for capturing, encoding and streaming high-definition HDR video in real-time using off-the-shelf components. All the lighting that is captured by HDR-enabled consumer cameras is delivered via the pipeline to any display, including HDR displays and even mobile devices with minimum latency. The system thus provides an integrated HDR video pipeline that includes everything from capture to post-production, archival and storage, compression, transmission, and display.

  8. Mechanics of Granular Materials labeled hardware

    NASA Technical Reports Server (NTRS)

    2000-01-01

    Mechanics of Granular Materials (MGM) flight hardware takes two twin double locker assemblies in the Space Shuttle middeck or the Spacehab module. Sand and soil grains have faces that can cause friction as they roll and slide against each other, or even cause sticking and form small voids between grains. This complex behavior can cause soil to behave like a liquid under certain conditions such as earthquakes or when powders are handled in industrial processes. MGM experiments aboard the Space Shuttle use the microgravity of space to simulate this behavior under conditions that carnot be achieved in laboratory tests on Earth. MGM is shedding light on the behavior of fine-grain materials under low effective stresses. Applications include earthquake engineering, granular flow technologies (such as powder feed systems for pharmaceuticals and fertilizers), and terrestrial and planetary geology. Nine MGM specimens have flown on two Space Shuttle flights. Another three are scheduled to fly on STS-107. The principal investigator is Stein Sture of the University of Colorado at Boulder. (Credit: NASA/MSFC).

  9. Nanorobot Hardware Architecture for Medical Defense

    PubMed Central

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C.

    2008-01-01

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease. PMID:27879858

  10. Developing a Decision Support System: The Software and Hardware Tools.

    ERIC Educational Resources Information Center

    Clark, Phillip M.

    1989-01-01

    Describes some of the available software and hardware tools that can be used to develop a decision support system implemented on microcomputers. Activities that should be supported by software are discussed, including data entry, data coding, finding and combining data, and data compatibility. Hardware considerations include speed, storage…

  11. The Microcomputer in the Library: II. Hardware and Operating Systems.

    ERIC Educational Resources Information Center

    Leggate, Peter; Dyer, Hilary

    1985-01-01

    This second in a series of six articles introducing microcomputer applications in smaller libraries describes the main microcomputer hardware components--processors, internal and external memory, buses, printers, communications, hardware. Importance of ergonomic factors in equipment design, multi-user and network configurations, and the role of…

  12. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    ERIC Educational Resources Information Center

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  13. Hardware packet pacing using a DMA in a parallel computer

    DOEpatents

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  14. Videodisc Levels: A Case Study in Hardware Obsession.

    ERIC Educational Resources Information Center

    Hofmeister, Alan M.; Thorkildsen, Ron J.

    1989-01-01

    The article reviews a 10-year history of research on videodisc programs with handicapped and nonhandicapped students. A trend from hardware-intensive programs concerned with physical individualization and self-pacing to more modest hardware involvement and a greater attention to the teacher's role in both group and individual instructional…

  15. Hardware-Efficient Monitoring of I/O Signals

    NASA Technical Reports Server (NTRS)

    Driscoll, Kevin R.; Hall, Brendan; Paulitsch, Michael

    2009-01-01

    In this invention, command and monitor functionality is moved between the two independent pieces of hardware, in which one had been dedicated to command and the other had been dedicated to monitor, such that some command and some monitor functionality appears in each. The only constraint is that the monitor for signal cannot be in the same hardware as the command I/O it is monitoring. The splitting of the command outputs between independent pieces of hardware may require some communication between them, i.e. an intra-switch trunk line. This innovation reduces the amount of wasted hardware and allows the two independent pieces of hardware to be designed identically in order to save development costs.

  16. Hardware efficient monitoring of input/output signals

    NASA Technical Reports Server (NTRS)

    Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

    2012-01-01

    A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

  17. VME rollback hardware for time warp multiprocessor systems

    NASA Technical Reports Server (NTRS)

    Robb, Michael J.; Buzzell, Calvin A.

    1992-01-01

    The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

  18. Hardware Development Process for Human Research Facility Applications

    NASA Technical Reports Server (NTRS)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

  19. The Art of Space Flight Exercise Hardware: Design and Implementation

    NASA Technical Reports Server (NTRS)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  20. Monitoring Particulate Matter with Commodity Hardware

    NASA Astrophysics Data System (ADS)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  1. Issues Related to Large Flight Hardware Acoustic Qualification Testing

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Perry, Douglas C.; Kern, Dennis L.

    2011-01-01

    The characteristics of acoustical testing volumes generated by reverberant chambers or a circle of loudspeakers with and without large flight hardware within the testing volume are significantly different. The parameters attributing to these differences are normally not accounted for through analysis or acoustic tests prior to the qualification testing without the test hardware present. In most cases the control microphones are kept at least 2-ft away from hardware surfaces, chamber walls, and speaker surfaces to minimize the impact of the hardware in controlling the sound field. However, the acoustic absorption and radiation of sound by hardware surfaces may significantly alter the sound pressure field controlled within the chamber/speaker volume to a given specification. These parameters often result in an acoustic field that may provide under/over testing scenarios for flight hardware. In this paper the acoustic absorption by hardware surfaces will be discussed in some detail. A simple model is provided to account for some of the observations made from Mars Science Laboratory spacecraft that recently underwent acoustic qualification tests in a reverberant chamber.

  2. New Approaches in Reuseable Booster System Life Cycle Cost Modeling

    NASA Technical Reports Server (NTRS)

    Zapata, Edgar

    2013-01-01

    This paper presents the results of a 2012 life cycle cost (LCC) study of hybrid Reusable Booster Systems (RBS) conducted by NASA Kennedy Space Center (KSC) and the Air Force Research Laboratory (AFRL). The work included the creation of a new cost estimating model and an LCC analysis, building on past work where applicable, but emphasizing the integration of new approaches in life cycle cost estimation. Specifically, the inclusion of industry processes/practices and indirect costs were a new and significant part of the analysis. The focus of LCC estimation has traditionally been from the perspective of technology, design characteristics, and related factors such as reliability. Technology has informed the cost related support to decision makers interested in risk and budget insight. This traditional emphasis on technology occurs even though it is well established that complex aerospace systems costs are mostly about indirect costs, with likely only partial influence in these indirect costs being due to the more visible technology products. Organizational considerations, processes/practices, and indirect costs are traditionally derived ("wrapped") only by relationship to tangible product characteristics. This traditional approach works well as long as it is understood that no significant changes, and by relation no significant improvements, are being pursued in the area of either the government acquisition or industry?s indirect costs. In this sense then, most launch systems cost models ignore most costs. The alternative was implemented in this LCC study, whereby the approach considered technology and process/practices in balance, with as much detail for one as the other. This RBS LCC study has avoided point-designs, for now, instead emphasizing exploring the trade-space of potential technology advances joined with potential process/practice advances. Given the range of decisions, and all their combinations, it was necessary to create a model of the original model and use genetic algorithms to explore results. A strong business case occurs when viable paths are identified for an affordable up-front investment, and these paths can credibly achieve affordable, responsive operations, characterized by smaller direct touch labor efforts at the wing level from flight to flight. The results supporting this approach, its potential, and its conclusions are presented here.

  3. Unlined Reuseable Filament Wound Composite Cryogenic Tank Testing

    NASA Technical Reports Server (NTRS)

    Murphy, A. W.; Lake, R. E.; Wilkerson, C.

    1999-01-01

    An unlined reusable filament wound composite cryogenic tank was tested at the Marshall Space Flight Center using LH2 cryogen and pressurization to 320 psig. The tank was fabricated by Phillips Laboratory and Wilson Composite Group, Inc., using an EnTec five-axis filament winder and sand mandrels. The material used was IM7/977-2 (graphite/epoxy).

  4. Reuseable lightweight modular multi-layer insulation for space shuttle

    NASA Technical Reports Server (NTRS)

    Burr, K. F.

    1973-01-01

    The adaptation of the Self Evacuating Multilayer Insulation System to the space shuttle orbiter liquid hydrogen tanks was investigated. Small scale material screening tests and subscale panel tests demonstrated the potential of the insulation to withstand the anticipated 100 flight cycles. The composition of the material and the process for producing the finished insulation are described. Results of the various tests to determine the durability of the material are presented.

  5. Hardware support for collecting performance counters directly to memory

    DOEpatents

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  6. Hardware implementation of an electrostatic MEMS-actuator linearization

    NASA Astrophysics Data System (ADS)

    Mair, F.; Egretzberger, M.; Kugi, A.

    2011-06-01

    In this paper, an electrostatic actuator linearization will be introduced, which is based on an existing hardware-efficient iterative square root algorithm. The algorithm is solely based on add and shift operations while just needing n/2 iterations for an n bit wide input signal. As a practical example, the nonlinear input transformation will be utilized for the design of the primary mode controller of a capacitive MEMS gyroscope and an implementation of the algorithm in the Verilog hardware description language will be instantiated. Finally, measurement results will validate the feasibility of the presented control concept and its hardware implementation.

  7. A fast, programmable hardware architecture for spaceborne SAR processing

    NASA Technical Reports Server (NTRS)

    Bennett, J. R.; Cumming, I. G.; Lim, J.; Wedding, R. M.

    1983-01-01

    The launch of spaceborne SARs during the 1980's is discussed. The satellite SARs require high quality and high throughput ground processors. Compression ratios in range and azimuth of greater than 500 and 150 respectively lead to frequency domain processing and data computation rates in excess of 2000 million real operations per second for C-band SARs under consideration. Various hardware architectures are examined and two promising candidates and proceeds to recommend a fast, programmable hardware architecture for spaceborne SAR processing are selected. Modularity and programmability are introduced as desirable attributes for the purpose of HTSP hardware selection.

  8. Comparison of leading parallel NAS file systems on commodity hardware

    SciTech Connect

    Hedges, R; Fitzgerald, K; Gary, M; Stearman, D M

    2010-11-08

    High performance computing has experienced tremendous gains in system performance over the past 20 years. Unfortunately other system capabilities, such as file I/O, have not grown commensurately. In this activity, we present the results of our tests of two leading file systems (GPFS and Lustre) on the same physical hardware. This hardware is the standard commodity storage solution in use at LLNL and, while much smaller in size, is intended to enable us to learn about differences between the two systems in terms of performance, ease of use and resilience. This work represents the first hardware consistent study of the two leading file systems that the authors are aware of.

  9. The JPL telerobot operator control station. Part 1: Hardware

    NASA Technical Reports Server (NTRS)

    Kan, Edwin P.; Tower, John T.; Hunka, George W.; Vansant, Glenn J.

    1989-01-01

    The Operator Control Station of the Jet Propulsion Laboratory (JPL)/NASA Telerobot Demonstrator System provides the man-machine interface between the operator and the system. It provides all the hardware and software for accepting human input for the direct and indirect (supervised) manipulation of the robot arms and tools for task execution. Hardware and software are also provided for the display and feedback of information and control data for the operator's consumption and interaction with the task being executed. The hardware design, system architecture, and its integration and interface with the rest of the Telerobot Demonstrator System are discussed.

  10. Using Ozone To Clean and Passivate Oxygen-Handling Hardware

    NASA Technical Reports Server (NTRS)

    Torrance, Paul; Biesinger, Paul

    2009-01-01

    A proposed method of cleaning, passivating, and verifying the cleanliness of oxygen-handling hardware would extend the established art of cleaning by use of ozone. As used here, "cleaning" signifies ridding all exposed surfaces of combustible (in particular, carbon-based) contaminants. The method calls for exposing the surfaces of the hardware to ozone while monitoring the ozone effluent for carbon dioxide. The ozone would passivate the hardware while oxidizing carbon-based residues, converting the carbon in them to carbon dioxide. The exposure to ozone would be continued until no more carbon dioxide was detected, signifying that cleaning and passivation were complete.

  11. Hardware Implementation of Serially Concatenated PPM Decoder

    NASA Technical Reports Server (NTRS)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  12. Hardware Implementation of a Bilateral Subtraction Filter

    NASA Technical Reports Server (NTRS)

    Huertas, Andres; Watson, Robert; Villalpando, Carlos; Goldberg, Steven

    2009-01-01

    A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for

  13. Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation

    NASA Technical Reports Server (NTRS)

    Kizhner, Semion; Petrick, David J.; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Day, John H. (Technical Monitor)

    2002-01-01

    Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.

  14. Status of neural network hardware in high energy physics

    NASA Astrophysics Data System (ADS)

    Denby, Bruce

    2001-08-01

    This paper examines the current status of hardware implementations of neural networks in high energy physics experiments, as reflected in the applications presented at ACAT 2000, Fermilab, October, 2000.

  15. Former Baldwin Hardware Corp. – Reading, PA PAD00235083

    EPA Pesticide Factsheets

    EPA is announcing its proposed decision that includes groundwater remediation, soil vapor capture and treatment as well as restrictions on land and groundwater uses under RCRA for the Baldwin Hardware Corporation facility in Reading PA, EPA ID PAD00235083

  16. Hardware device to physical structure binding and authentication

    DOEpatents

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  17. Hardware acceleration of image recognition through a visual cortex model

    NASA Astrophysics Data System (ADS)

    Rice, Kenneth L.; Taha, Tarek M.; Vutsinas, Christopher N.

    2008-09-01

    Recent findings in neuroscience have led to the development of several new models describing the processes in the neocortex. These models excel at cognitive applications such as image analysis and movement control. This paper presents a hardware architecture to speed up image content recognition through a recently proposed model of the visual cortex. The system is based on a set of parallel computation nodes implemented in an FPGA. The design was optimized for hardware by reducing the data storage requirements, and removing the need for multiplies and divides. The reconfigurable logic hardware implementation running at 121 MHz provided a speedup of 148 times over a 2 GHz AMD Opteron processor. The results indicate the feasibility of specialized hardware to accelerate larger biological scale implementations of the model.

  18. A versatile hardware platform for brain computer interfaces.

    PubMed

    Garcia, Pablo A; Haberman, Marcelo; Spinelli, Enrique M

    2010-01-01

    This article presents the development of a versatile hardware platform for brain computer interfaces (BCI). The aim of this work is to produce a small, autonomous and configurable BCI platform adaptable to the user's needs.

  19. Transient vibration test criteria for spacecraft hardware. [galileo spacecraft

    NASA Technical Reports Server (NTRS)

    Kern, D. L.; Hayes, C. D.

    1984-01-01

    Transient vibration test criteria, developed for spacecraft hardware, provide a test rationale to verify the capability of the hardware to withstand the low and mid frequency transient vibration environments induced by launch vehicle events. A test method, consisting of a series of discrete frequency, limited cycle, modulated sine wave pulses, was developed to avoid the slow swept sine drawbacks, yet provide a repeatable test that would excite all frequencies. The shape of the waveform is that of the classic response of the mass of a one degree of freedom system when it is base-excited by an exponentially decayed sine wave transient. Criteria were developed to define pulse amplitudes, shapes, and center frequencies from spacecraft loads analyses. Test tolerance criteria were also developed and specified. The transient vibration test criteria were implemented on spacecraft flight hardware and provided a more realistic test simulation (i.e., less conservative) for qualification of spacecraft hardware without risk of undertest.

  20. Hierarchical image-based rendering using texture mapping hardware

    SciTech Connect

    Max, N

    1999-01-15

    Multi-layered depth images containing color and normal information for subobjects in a hierarchical scene model are precomputed with standard z-buffer hardware for six orthogonal views. These are adaptively selected according to the proximity of the viewpoint, and combined using hardware texture mapping to create ''reprojected'' output images for new viewpoints. (If a subobject is too close to the viewpoint, the polygons in the original model are rendered.) Specific z-ranges are selected from the textures with the hardware alpha test to give accurate 3D reprojection. The OpenGL color matrix is used to transform the precomputed normals into their orientations in the final view, for hardware shading.

  1. Hardware problems encountered in solar heating and cooling systems

    NASA Technical Reports Server (NTRS)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  2. Simulation of imaging radar using graphics hardware acceleration

    NASA Astrophysics Data System (ADS)

    Peinecke, Niklas; Döhler, Hans-Ullrich; Korn, Bernd R.

    2008-04-01

    Extending previous works by Doehler and Bollmeyer we describe a new implementation of an imaging radar simulator. Our approach is based on using modern computer graphics hardware making heavy use of recent technologies like vertex and fragment shaders. Furthermore, to allow for a nearly realistic image we generate radar shadows implementing shadow map techniques in the programmable graphics hardware. The particular implementation is tailored to imitate millimeter wave (MMW) radar but could be extended for other types of radar systems easily.

  3. Capabilities and constraints of typical space flight hardware

    NASA Technical Reports Server (NTRS)

    Koudelka, John M.

    1993-01-01

    The Space Experiments Division is in the business of performing ground based low gravity testing and designing experiment hardware for space flight on the Space Shuttle and in the future, Space Station Freedom. As witnessed in combustion work, the reduction of gravity brings forward previously negligible processes and parameters. In a similar manner, the design of experiments for microgravity operation aboard the Space Shuttle must consider parameters that are often not factors for laboratory hardware.

  4. The aerospace energy systems laboratory: Hardware and software implementation

    NASA Technical Reports Server (NTRS)

    Glover, Richard D.; Oneil-Rood, Nora

    1989-01-01

    For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

  5. Hardware Realization of a Transform Domain Communication System

    DTIC Science & Technology

    2007-03-01

    interference are identified [8]. Periodogram [1], autoregressive [1], and wavelet - based [4] estimation techniques have previously been used... based hardware platform. 2. The implementation of a wavelet - based spectrum estimation algorithm in hardware. A WDCS could be implemented as a standalone...Domain Communication System (WDCS): Packet- Based Wavelet Spectral Estimation and M-ary Signaling. MS thesis, AFIT/GE/ENG/02M-14. Graduate School

  6. Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property

    DTIC Science & Technology

    2015-05-22

    microprocessor IPs or cryptographic cores, and automate parts or all of the extra duties imposed by the PCHIP on hardware IP developers. PCHIP...fundamental PCHIP framework, enhance its capabilities to be usable for various hardware types with different requirements, e.g. microprocessor IPs or...of formal proofs for those security theorems. We established a set of security properties which ensure the trustworthiness of microprocessor IPs and

  7. Hardware-Assisted Large-Scale Neuroevolution for Multiagent Learning

    DTIC Science & Technology

    2014-12-30

    SECURITY CLASSIFICATION OF: This DURIP equipment award was used to purchase, install, and bring on-line two Berkeley Emulation Engines (BEEs) and two... Berkeley Emulation Engine) hardware platforms has costed $201,500.00 in total. To accelerate both the multiagent software simulation and hardware...install, and bring on-line two Berkeley Emulation Engines (BEEs) and two mini-BEE machines to establish an FPGA-based high-performance multiagent

  8. Hardware Evolution of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a Field Programmable Transistor Array (FPTA). The performance of these evolved controllers is compared to that of a conventional proportional-integral (PI) controller.

  9. PLC Hardware Discrimination using RF-DNA fingerprinting

    DTIC Science & Technology

    2014-06-19

    PLC HARDWARE DISCRIMINATION USING RF- DNA FINGERPRINTING THESIS Bradley C. Wright, Civilian, USAF AFIT-ENG-T-14-J-12 DEPARTMENT OF THE AIR FORCE AIR...protection in the United States. AFIT-ENG-T-14-J-12 PLC HARDWARE DISCRIMINATION USING RF- DNA FINGERPRINTING THESIS Presented to the Faculty Department...DISCRIMINATION USING RF- DNA FINGERPRINTING Bradley C. Wright, B.S.E.E. Civilian, USAF Approved: /signed/ Maj Samuel J. Stone, PhD (Chairman) /signed/ Michael A

  10. STS-118 Astronaut Dave Williams Trains Using Virtual Reality Hardware

    NASA Technical Reports Server (NTRS)

    2007-01-01

    STS-118 astronaut and mission specialist Dafydd R. 'Dave' Williams, representing the Canadian Space Agency, uses Virtual Reality Hardware in the Space Vehicle Mock Up Facility at the Johnson Space Center to rehearse some of his duties for the upcoming mission. This type of virtual reality training allows the astronauts to wear special gloves and other gear while looking at a computer that displays simulating actual movements around the various locations on the station hardware which with they will be working.

  11. Apollo Guidance, Navigation, and Control (GNC) Hardware Overview

    NASA Technical Reports Server (NTRS)

    Interbartolo, Michael

    2009-01-01

    This viewgraph presentation reviews basic guidance, navigation and control (GNC) concepts, examines the Command and Service Module (CSM) and Lunar Module (LM) GNC organization and discusses the primary GNC and the CSM Stabilization and Control System (SCS), as well as other CSM-specific hardware. The LM Abort Guidance System (AGS), Control Electronics System (CES) and other LM-specific hardware are also addressed. Three subsystems exist on each vehicle: the computer subsystem (CSS), the inertial subsystem (ISS) and the optical subsystem (OSS). The CSS and ISS are almost identical between CSM and LM and each is designed to operate independently. CSM SCS hardware are highlighted, including translation control, rotation controls, gyro assemblies, a gyro display coupler and flight director attitude indicators. The LM AGS hardware are also highlighted and include the abort electronics assembly and the abort sensor assembly; while the LM CES hardware includes the attitude controller assembly, thrust/translation controller assemblies and the ascent engine arming assemble. Other common hardware including the Orbital Rate Display - Earth and Lunar (ORDEAL) and the Crewman Optical Alignment Sight (COAS), a docking aid, are also highlighted.

  12. On the use of inexact, pruned hardware in atmospheric modelling

    PubMed Central

    Düben, Peter D.; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V.; Palmer, T. N.

    2014-01-01

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz ‘96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models. PMID:24842031

  13. Evaluation of next generation hardware for lithography processing

    NASA Astrophysics Data System (ADS)

    Shimoaoki, T.; Enomoto, M.; Nafus, K.; Marumoto, H.; Kosugi, H.; Mallmann, J.; Maas, R.; Verspaget, C.; van der Heijden, E.; Wang, S.

    2010-04-01

    This work is the summary of improvements in processing capability implemented and tested on the LITHIUS ProTM -i / TWINSCANTM XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested. For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

  14. MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

    NASA Technical Reports Server (NTRS)

    Crossin, Kent R.

    2005-01-01

    The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

  15. Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

    NASA Technical Reports Server (NTRS)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Blacknall, Carolyn; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

  16. An FPGA-based reconfigurable DDC algorithm

    NASA Astrophysics Data System (ADS)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  17. Fast DRR splat rendering using common consumer graphics hardware.

    PubMed

    Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

    2007-11-01

    Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2 x 10(6) voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine.

  18. Fast DRR splat rendering using common consumer graphics hardware

    SciTech Connect

    Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

    2007-11-15

    Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2x10{sup 6} voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine.

  19. Final postflight hardware evaluation report RSRM-28 (STS-53)

    NASA Technical Reports Server (NTRS)

    Starrett, William David, Jr.

    1993-01-01

    The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-28 (STS-53) RSRM flight set is presented. All observed hardware conditions were documented on PFOR's and are included in Appendices A through C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64215), represents a summary of the RSRM-28 hardware evaluation. The as-flown hardware configuration is documented in TWR-63638. Disassembly evaluation photograph numbers are logged in TWA-1989. The RSRM-28 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on July 15, 1993. Additional time was required to perform the evaluation of the stiffener rings per special issue 4.1.5.2 because of the washout schedule. The release of this report was after completion of all special issues per program management direction. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable team and tracked through the PFAR system.

  20. OS friendly microprocessor architecture: Hardware level computer security

    NASA Astrophysics Data System (ADS)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  1. Postflight hardware evaluation 360T026 (RSRM-26, STS-47)

    NASA Technical Reports Server (NTRS)

    Nielson, Greg

    1993-01-01

    The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the 360T026 (STS-47) Redesigned Solid Rocket Motor (RSRM) flight set is provided. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64203), represents a summary of the 360T026 hardware evaluation. The as-flown hardware configuration is documented in TWR-60472. Disassembly evaluation photograph numbers are logged in TWA-1987. The 360T026 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on 12 April 1993. Detailed evaluations were performed in accordance with the Clearfield Postflight Engineering Evaluation Plan (PEEP), TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  2. Scalable digital hardware for a trapped ion quantum computer

    NASA Astrophysics Data System (ADS)

    Mount, Emily; Gaultney, Daniel; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2016-12-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for loading, cooling, initialization, and detection of the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  3. Hardware friendly adaptive support-weight approach for stereo matching

    NASA Astrophysics Data System (ADS)

    Hou, Zuoxun; Han, Pei; Zhang, Hongwei; An, Ran

    2016-10-01

    In this paper, the hardware friendly adaptive support-weight approach is proposed to simplify the weight calculation process of the standard approach, which employs the support region to simplify the calculation of the similarity and uses the fixed distance dependent weight to present the proximity. In addition, the complete stereo matching algorithm and the hardware structure for FPGA implementation compatible with the approach is proposed. The experimental results show that the algorithm produces the disparity map accurately in different illumination conditions and different scenes, and its processing average bad pixel rate is only 6.65% for the standard test images of the Middlebury database, which is approximate to the performance of the standard adaptive support-weight approach. The proposed hardware structure provides a basis for design and implementation of real-time accurate stereo matching FPGA system.

  4. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    PubMed

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  5. Development of Enhanced Avionics Flight Hardware Selection Process

    NASA Technical Reports Server (NTRS)

    Smith, K.; Watson, G. L.

    2003-01-01

    The primary objective of this research was to determine the processes and feasibility of using commercial off-the-shelf PC104 hardware for flight applications. This would lead to a faster, better, and cheaper approach to low-budget programs as opposed to the design, procurement. and fabrication of space flight hardware. This effort will provide experimental evaluation with results of flight environmental testing. Also, a method and/or suggestion used to bring test hardware up to flight standards will be given. Several microgravity programs, such as the Equiaxed Dendritic Solidification Experiment, Self-Diffusion in Liquid Elements, and various other programs, are interested in PC104 environmental testing to establish the limits of this technology.

  6. Final postflight hardware evaluation report RSRM-32 (STS-57)

    NASA Astrophysics Data System (ADS)

    Nielson, Greg

    1993-11-01

    This document is the final report for the postflight assessment of the RSRM-32 (STS-57) flight set. This report presents the disassembly evaluations performed at the Thiokol facilities in Utah and is a continuation of the evaluations performed at KSC (TWR-64239). The PEEP for this assessment is outlined in TWR-50051, Revision B. The PEEP defines the requirements for evaluating RSRM hardware. Special hardware issues pertaining to this flight set requiring additional or modified assessment are outlined in TWR-64237. All observed hardware conditions were documented on PFOR's which are included in Appendix A. Observations were compared against limits defined in the PEEP. Any observation that was categorized as reportable or had no defined limits was documented on a preliminary PFAR by the assessment engineers. Preliminary PFAR's were reviewed by the Thiokol SPAT Executive Board to determine if elevation to PFAR's was required.

  7. Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

    PubMed Central

    Biasizzo, Anton; Novak, Franc

    2013-01-01

    Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load. PMID:23673680

  8. Hardware accelerated compression of LIDAR data using FPGA devices.

    PubMed

    Biasizzo, Anton; Novak, Franc

    2013-05-14

    Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

  9. Mapping of topological quantum circuits to physical hardware.

    PubMed

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-04-11

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  10. Hardware Architecture Study for NASA's Space Software Defined Radios

    NASA Technical Reports Server (NTRS)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  11. On Issues of Precision for Hardware-based Volume Visualization

    SciTech Connect

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  12. Surface moisture measurement system hardware acceptance test report

    SciTech Connect

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  13. Mini-O, simple Omega receiver hardware for user education

    NASA Technical Reports Server (NTRS)

    Burhans, R. W.

    1976-01-01

    A problem with the Omega system is a lack of suitable low cost hardware for the small user community. A collection of do it yourself circuit modules are under development intended for use by educational institutions, small boat owners, aviation enthusiasts, and others who have some skills in fabricating their own electronic equipment. Applications of the hardware to time frequency standards measurements, signal propagation monitoring, and navigation experiments are presented. A family of Mini-O systems have been constructed varying from the simplest RF preamplifiers and narrowband filters front-ends, to sophisticated microcomputer interface adapters.

  14. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    NASA Technical Reports Server (NTRS)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  15. Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

    NASA Technical Reports Server (NTRS)

    Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

    2003-01-01

    Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

  16. Low-power hardware for neural spike compression in BMIs.

    PubMed

    Lapolli, Ângelo C; Coppa, Bertrand; Héliot, Rodolphe

    2013-01-01

    Within brain-machine interface systems, cortically implanted microelectrode arrays and associated hardware have a low-power budget for data sampling, processing, and transmission. Recent studies have shown the feasibility of data transmission rate reduction using compressed sensing on detected neural spikes. They provide power savings while maintaining clustering and classification abilities. We propose and analyze here a low-power hardware implementation for spike detection and compression. The resulting integrated circuit, designed in CMOS 65 nm technology, consumes 2.83 µW and provides 97% of data rate reduction.

  17. Postflight hardware evaluation 360T021 (RSRM-21, STS-45), revision A

    NASA Technical Reports Server (NTRS)

    Maccauly, Linda E.

    1992-01-01

    The Final Postflight Hardware Evaluation Report 360T021 (RSRM-21, STS-45) is included. All observed hardware conditions were documented on Postflight Observation Reports (PFOR's) and included in Appendices A through E. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report represents a summary of the 360T021 hardware evaluation.

  18. The Certification of Environmental Chambers for Testing Flight Hardware

    NASA Technical Reports Server (NTRS)

    Fields, Keith

    2009-01-01

    The JPL chamber certification process for ensuring that test chambers used to test flight hardware meet a minimum standard is critical to the safety of the hardware and personnel. Past history as demonstrated that this process is important due to the catastrophic incidents that could occur if the chamber is not set up correctly. Environmental testing is one of the last phases in the development of a subsystem, and it typically occurs just before integration of flight hardware into the fully assembled flight system. A seemingly insignificant -miscalculation or missed step can necessitate rebuilding or replacing a subsystem due to over-testing or damage from the test chamber. Conversely, under-testing might fail to detect weaknesses that might cause failure when the hardware is in service. This paper describes the process that identifies the many variables that comprise the testing scenario and screening of as built chambers, the training of qualified operators, and a general "what-to-look-for" in minimum standards.

  19. The Certification of Environmental Chambers for Testing Flight Hardware

    NASA Technical Reports Server (NTRS)

    Fields, Keith

    2010-01-01

    The JPL chamber certification process for ensuring that test chambers used to test flight hardware meet a minimum standard is critical to the safety of the hardware and personnel. Past history has demonstrated that this process is important due to the catastrophic incidents that could occur if the chamber is not set up correctly. Environmental testing is one of the last phases in the development of a subsystem, and it typically occurs just before integration of flight hardware into the fully assembled flight system. A seemingly insignificant -miscalculation or missed step can necessitate rebuilding or replacing a subsystem due to over-testing or damage from the test chamber. Conversely, under-testing might fail to detect weaknesses that might cause failure when the hardware is in service. This paper describes the process that identifies the many variables that comprise the testing scenario and screening of as built chambers, the training of qualified operators, and a general "what-to-look-for" in minimum standards.

  20. Rapid space hardware development through computer-automated testing

    SciTech Connect

    Masters, D.S.; Ruud, K.K.

    1997-10-01

    FORTE, the Fast On-Orbit Recording of Transient Events small satellite designed and built by Los Alamos and Sandia National Laboratories, is scheduled for launch in August, 1997. In the spirit of {open_quotes}better, cheaper, faster{close_quotes} satellites, the RF experiment hardware (receiver and trigger sub-systems) necessitated rapid prototype testing and characterization in the development of space-flight components. This was accomplished with the assembly of engineering model hardware prior to construction of flight hardware and the design of component-specific, PC-based software control libraries. Using the LabVIEW{reg_sign} graphical programming language, together with off-the-shelf PC digital I/O and GPIB interface cards, hardware control and complete automation of test equipment was possible from one PC. Because the receiver and trigger sub-systems employed complex functions for signal discrimination and transient detection, thorough validation of all functions and illumination of any faults were priorities. These methods were successful in accelerating the development and characterization of space-flight components prior to integration and allowed more complete data to be gathered than could have been accomplished without automation. Additionally, automated control of input signal sources was carried over from bench-level to system-level with the use of networked Linux workstation utilizing a GPIB interface.

  1. Direct Satellite Communication. Easy-to-Prepare Hardware.

    ERIC Educational Resources Information Center

    Tillery, John

    1990-01-01

    Described is the use of the microcomputer and interfacing equipment to obtain weather data from meteorological satellites. Equipment necessary for this type of remote sensing, including constructing and/or obtaining the necessary hardware and software is discussed. Ideas for the integration of this material into the curriculum are presented. (CW)

  2. Motion compensation in digital subtraction angiography using graphics hardware.

    PubMed

    Deuerling-Zheng, Yu; Lell, Michael; Galant, Adam; Hornegger, Joachim

    2006-07-01

    An inherent disadvantage of digital subtraction angiography (DSA) is its sensitivity to patient motion which causes artifacts in the subtraction images. These artifacts could often reduce the diagnostic value of this technique. Automated, fast and accurate motion compensation is therefore required. To cope with this requirement, we first examine a method explicitly designed to detect local motions in DSA. Then, we implement a motion compensation algorithm by means of block matching on modern graphics hardware. Both methods search for maximal local similarity by evaluating a histogram-based measure. In this context, we are the first who have mapped an optimizing search strategy on graphics hardware while paralleling block matching. Moreover, we provide an innovative method for creating histograms on graphics hardware with vertex texturing and frame buffer blending. It turns out that both methods can effectively correct the artifacts in most case, as the hardware implementation of block matching performs much faster: the displacements of two 1024 x 1024 images can be calculated at 3 frames/s with integer precision or 2 frames/s with sub-pixel precision. Preliminary clinical evaluation indicates that the computation with integer precision could already be sufficient.

  3. Leveraging Information Technology. Track VI: Hardware/Software Strategies.

    ERIC Educational Resources Information Center

    CAUSE, Boulder, CO.

    Seven papers from the 1987 CAUSE conference's Track VI, Hardware/Software Strategies, are presented. They include: "Integrated Systems--The Next Steps" (Morris A. Hicks); "Administrative Microcomputing--Roads Traveled, Lessons Learned" (David L. Smallen); "Murphy's First Law and Its Application to Administrative…

  4. Differences Between VLBI2010 and S/X Hardware

    NASA Technical Reports Server (NTRS)

    Corey, Brian

    2010-01-01

    While the overall architecture is similar for the station hardware in current S/X systems and in the VLBI2010 systems under development, various functions are implemented differently. Some of these differences, and the reasons behind them, are described here.

  5. 4. DETAIL OF STONE BLOCK CONSTRUCTION AND IRON HARDWARE (Original ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    4. DETAIL OF STONE BLOCK CONSTRUCTION AND IRON HARDWARE (Original Fabric) - Bald Eagle Cross-Cut Canal Lock, North of Water Street along West Branch of Susquehanna River South bank, 500 feet East of Jay Street Bridge, Lock Haven, Clinton County, PA

  6. Hardware-in-the-loop tow missile system simulator

    SciTech Connect

    Waldman, G.S.; Wootton, J.R.; Hobson, G.L.; Holder, D.L.

    1993-07-06

    A missile system simulator is described for use in training people for target acquisition, missile launch, and missile guidance under simulated battlefield conditions comprising: simulating means for producing a digital signal representing a simulated battlefield environment including at least one target movable therewithin, the simulating means generating an infrared map representing the field-of-view and the target; interface means for converting said digital signals to an infrared image; missile system hardware including the missile acquisition, tracking, and guidance portions thereof, said hardware sensing the infrared image to determine the location of the target in a field-of-view; and, image means for generating an infrared image of a missile launched at the target and guided thereto, the image means imposing the missile image onto the field-of-view for the missile hardware to acquire the image of the missile in addition to that of the target, and to generate guidance signals to guide the missile image to the target image, wherein the interfacing means is responsive to a guidance signal from the hardware to simulate, in real-time, the response of the missile to the guidance signal, the image means including a blackbody, laser means for irradiating the blackbody to heat it to a temperature at which it emits infrared radiation, and optic means for integrating the radiant image produced by heating the blackbody into the infrared map.

  7. Evaluation of the HARDMAN (Hardware vs. Manpower) Comparability Methodology

    DTIC Science & Technology

    1984-08-01

    Analysis Comparison with Methodology conformed with other known, accepted other MPT methods MPT modeling schemes, and data foundations Audits Methodology ...majority of mandatory user needs Operational Analysis Comparison with other Methodology conformed with other known, MPT methods accepted MPT modeling...Technical Report 646 Evaluation of the HARDMAN (Hardware vs. Manpower) Comparability Methodology El Wayne Zimmerman, Robert Butler, Valerie Gray, and

  8. Efficient Architecture for Spike Sorting in Reconfigurable Hardware

    PubMed Central

    Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

    2013-01-01

    This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation. PMID:24189331

  9. Fundamentals of Hardware. Curriculum Improvement Project. Region II.

    ERIC Educational Resources Information Center

    Onabajo, Femi

    This course curriculum is intended for use by community college instructors and administrators in implementing a fundamentals in hardware course. A student's course syllabus provides this information: credit hours, catalog description, prerequisites, required text, instructional process, objectives, student evaluation, and class schedule. A…

  10. Alternate Protocol for Detecting Biological Contamination on Sensitive Hardware

    NASA Technical Reports Server (NTRS)

    Berlin, David; Lalime, Erin; Carosso, Nancy

    2015-01-01

    The purpose of this project is to develop a sterile water based rapid bioburden test. Contamination engineers use two tests to assess the level of biological contamination on hardware: the rapid five minute bioburden test, which is a molecular screening for Adenosine triphosphate (ATP), a molecule found in all cells on the hardware, and a slower colony growth test, which is used to give a more accurate representation of the amount of microbes on the hardware. However, the rapid bioburden test has limited application because it leaves a residue that can be detrimental to sensitive hardware. This can cause project delays while waiting for the results from the three day colony growth test. We address this problem by adapting the commercial germicide based ATP system to a sterile water based system. The test works by reacting ATP with D-Luciferin and Luciferase protein to yield light. The light is then detected by a luminometer that outputs a Relative Light Unit (RLU) amount depending on how much ATP is present. To analyze the effectiveness of the new test, we developed a correlation between amounts of ATP and the RLU produced using the germicide based system. From these experiments, we've generated a consistent relationship between the two in the form of a power curve. From there, we developed a correlation curve between the amount of colonies and the RLU they produced. Initial tests of the new protocol have shown that the water based system isn't as sensitive as the germicide based test.

  11. Neural Networks Based Approach to Enhance Space Hardware Reliability

    NASA Technical Reports Server (NTRS)

    Zebulum, Ricardo S.; Thakoor, Anilkumar; Lu, Thomas; Franco, Lauro; Lin, Tsung Han; McClure, S. S.

    2011-01-01

    This paper demonstrates the use of Neural Networks as a device modeling tool to increase the reliability analysis accuracy of circuits targeted for space applications. The paper tackles a number of case studies of relevance to the design of Flight hardware. The results show that the proposed technique generates more accurate models than the ones regularly used to model circuits.

  12. Improved guidance hardware study for the scout launch vehicle

    NASA Technical Reports Server (NTRS)

    Schappell, R. T.; Salis, M. L.; Mueller, R.; Best, L. E.; Bradt, A. J.; Harrison, R.; Burrell, J. H.

    1972-01-01

    A market survey and evaluation of inertial guidance systems (inertial measurement units and digital computers) were made. Comparisons were made to determine the candidate systems for use in the Scout launch vehicle. Error analyses were made using typical Scout trajectories. A reaction control system was sized for the fourth stage. The guidance hardware to Scout vehicle interface was listed.

  13. Fastener Retention Requirements and Practices in Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Dasgupta, Rajib

    2004-01-01

    This presentation reviews the requirements for safety critical fasteners in spaceflight hardware. Included in the presentation are design guidelines and information for Locking Helicoils, key locked inserts and thinwalled inserts, self locking screws and bolts. locknuts, and a locking adhesives, Loctite and Vibratite.

  14. Towards automated construction of dependable software/hardware systems

    SciTech Connect

    Yakhnis, A.; Yakhnis, V.

    1997-11-01

    This report contains viewgraphs on the automated construction of dependable computer architecture systems. The outline of this report is: examples of software/hardware systems; dependable systems; partial delivery of dependability; proposed approach; removing obstacles; advantages of the approach; criteria for success; current progress of the approach; and references.

  15. Combine Security and Safety with the Right Door Hardware.

    ERIC Educational Resources Information Center

    Olmstead, Patrick R.

    1999-01-01

    Discusses how door design and construction can add safety and security to educational facilities. Exit device variations, and electromagnetic locks and access control are explored. Also discussed are inexpensive ways to improve the safety and security profiles of a building using door hardware. (GR)

  16. Use of Heritage Hardware on MPCV Exploration Flight Test One

    NASA Technical Reports Server (NTRS)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  17. USAFSAM Waiver File Intelligent Terminal: Hardware Reference Manual.

    DTIC Science & Technology

    1980-04-01

    I. SBC 80/20 single - board computer for the central processing unit (CPU) 2. SBC 104 general purpose input/output (I/0) and memory board 3. SBC 108...5 5 Carousel TXR 15 r APPENDIX A. REFERENCE MANUAL LIST 1. SBC 80/20 Single Board Computer Hardware Reference Manual. Intel, 1977. 2. SBC 104/108/116

  18. Measuring Auroral and Arctic Ozone Using Student Made Hardware

    NASA Astrophysics Data System (ADS)

    Pina, M.

    2015-12-01

    This project is twofold to test the feasibility of student made hardware and teach students more about atmospheric instrumentation by providing students with education and materials, instructing them in design and building of hardware, and testing the hardware against commercial models in terms of weight, cost, and features. The Gaseous Compounds team of the University of Houston Undergraduate Student Instrument Project (USIP) selected the parts and the students of the team are assembling the payload. The payload will launch on a latex balloon in Houston and Fairbanks, Alaska. The instrument will gather data on the concentration of certain gases in the atmosphere as well as a meteorological profile of the atmosphere. The students plan to have the instrument collect and transmit data on carbon monoxide, nitric oxide, nitrogen dioxide, and ozone, as well as temperature, humidity, and barometric pressure. The data will also be stored on an SD card as a backup in case transmission fails. These payloads will fly at night and day to get an accurate vertical profile of the atmosphere and these results will be tested against the results of commercial hardware with the same capabilities.

  19. VIEW LOOKING WEST THROUGH LOCK 70. NOTE THE EXTANT HARDWARE ...

    Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

    VIEW LOOKING WEST THROUGH LOCK 70. NOTE THE EXTANT HARDWARE EMBEDED IN THE TOP OF THE LOCK WALLS, THE RECESSES IN THE LOCK WALLS, AND THE LATER-ERA CONCRETE WEIR APPROXIMATELY WHERE THE LOCK GATE SHOULD BE. - New York State Barge Canal, Lockport Locks, Richmond Avenue, Lockport, Niagara County, NY

  20. RDV77 VLBA Hardware/Software Correlator Comparisons

    NASA Technical Reports Server (NTRS)

    Gordon, David

    2010-01-01

    Results of a hardware vs. software correlation of the RDV77 session are presented. Group delays are found to agree (WRMS differences) at an average level of 4.2 psec and with a noise floor of 2.5 psec. These RDV77 comparisons agree well with several previous correlator comparison studies.

  1. Accounting for hardware imperfections in EIT image reconstruction algorithms.

    PubMed

    Hartinger, Alzbeta E; Gagnon, Hervé; Guardo, Robert

    2007-07-01

    Electrical impedance tomography (EIT) is a non-invasive technique for imaging the conductivity distribution of a body section. Different types of EIT images can be reconstructed: absolute, time difference and frequency difference. Reconstruction algorithms are sensitive to many errors which translate into image artefacts. These errors generally result from incorrect modelling or inaccurate measurements. Every reconstruction algorithm incorporates a model of the physical set-up which must be as accurate as possible since any discrepancy with the actual set-up will cause image artefacts. Several methods have been proposed in the literature to improve the model realism, such as creating anatomical-shaped meshes, adding a complete electrode model and tracking changes in electrode contact impedances and positions. Absolute and frequency difference reconstruction algorithms are particularly sensitive to measurement errors and generally assume that measurements are made with an ideal EIT system. Real EIT systems have hardware imperfections that cause measurement errors. These errors translate into image artefacts since the reconstruction algorithm cannot properly discriminate genuine measurement variations produced by the medium under study from those caused by hardware imperfections. We therefore propose a method for eliminating these artefacts by integrating a model of the system hardware imperfections into the reconstruction algorithms. The effectiveness of the method has been evaluated by reconstructing absolute, time difference and frequency difference images with and without the hardware model from data acquired on a resistor mesh phantom. Results have shown that artefacts are smaller for images reconstructed with the model, especially for frequency difference imaging.

  2. The 1986/87 Classroom Computer Learning Hardware Buyers' Guide.

    ERIC Educational Resources Information Center

    Classroom Computer Learning, 1986

    1986-01-01

    Provides information on selected computer peripherals which seem most appropriate for education in terms of availability, price, and application. Hardware includes modems, local area networks, printers, graphics tables (as well as touch tablets and alternate keyboards), and joysticks. Each item listed includes company, computer capability, price,…

  3. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  4. Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

    NASA Technical Reports Server (NTRS)

    Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

    2013-01-01

    This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

  5. High-Speed Isolation Board for Flight Hardware Testing

    NASA Technical Reports Server (NTRS)

    Yamamoto, Clifford K.; Goodpasture, Richard L.

    2011-01-01

    There is a need to provide a portable and cost-effective galvanic isolation between ground support equipment and flight hardware such that any unforeseen voltage differential between ground and power supplies is eliminated. An interface board was designed for use between the ground support equipment and the flight hardware that electrically isolates all input and output signals and faithfully reproduces them on each side of the interface. It utilizes highly integrated multi-channel isolating devices to minimize size and reduce assembly time. This single-board solution provides appropriate connector hardware and breakout of required flight signals to individual connectors as needed for various ground support equipment. The board utilizes multi-channel integrated circuits that contain transformer coupling, thereby allowing input and output signals to be isolated from one another while still providing high-fidelity reproduction of the signal up to 90 MHz. The board also takes in a single-voltage power supply input from the ground support equipment and in turn provides a transformer-derived isolated voltage supply to power the portion of the circuitry that is electrically connected to the flight hardware. Prior designs used expensive opto-isolated couplers that were required for each signal to isolate and were time-consuming to assemble. In addition, these earlier designs were bulky and required a 2U rack-mount enclosure. The new design is smaller than a piece of 8.5 11-in. (.22 28-mm) paper and can be easily hand-carried where needed. The flight hardware in question is based on a lineage of existing software-defined radios (SDRs) that utilize a common interface connector with many similar input-output signals present. There are currently four to five variations of this SDR, and more upcoming versions are planned based on the more recent design.

  6. Web tools to monitor and debug DAQ hardware

    SciTech Connect

    Eugene Desavouret; Jerzy M. Nogiec

    2003-06-04

    A web-based toolkit to monitor and diagnose data acquisition hardware has been developed. It allows for remote testing, monitoring, and control of VxWorks data acquisition computers and associated instrumentation using the HTTP protocol and a web browser. This solution provides concurrent and platform independent access, supplementary to the standard single-user rlogin mechanism. The toolkit is based on a specialized web server, and allows remote access and execution of select system commands and tasks, execution of test procedures, and provides remote monitoring of computer system resources and connected hardware. Various DAQ components such as multiplexers, digital I/O boards, analog to digital converters, or current sources can be accessed and diagnosed remotely in a uniform and well-organized manner. Additionally, the toolkit application supports user authentication and is able to enforce specified access restrictions.

  7. International Space Station (ISS) Water Transfer Hardware Logistics

    NASA Technical Reports Server (NTRS)

    Shkedi, Brienne D.

    2006-01-01

    Water transferred from the Space Shuttle to the International Space Station (ISS) is generated as a by-product from the Shuttle fuel cells, and is generally preferred over the Progress which has to launch water from the ground. However, launch mass and volume are still required for the transfer and storage hardware. Some of these up-mass requirements have been reduced since ISS assembly began due to changes in the storage hardware (CWC). This paper analyzes the launch mass and volume required to transfer water from the Shuttle and analyzes the up-mass savings due to modifications in the CWC. Suggestions for improving the launch mass and volume are also provided.

  8. Fast image interpolation for motion estimation using graphics hardware

    NASA Astrophysics Data System (ADS)

    Kelly, Francis; Kokaram, Anil

    2004-05-01

    Motion estimation and compensation is the key to high quality video coding. Block matching motion estimation is used in most video codecs, including MPEG-2, MPEG-4, H.263 and H.26L. Motion estimation is also a key component in the digital restoration of archived video and for post-production and special effects in the movie industry. Sub-pixel accurate motion vectors can improve the quality of the vector field and lead to more efficient video coding. However sub-pixel accuracy requires interpolation of the image data. Image interpolation is a key requirement of many image processing algorithms. Often interpolation can be a bottleneck in these applications, especially in motion estimation due to the large number pixels involved. In this paper we propose using commodity computer graphics hardware for fast image interpolation. We use the full search block matching algorithm to illustrate the problems and limitations of using graphics hardware in this way.

  9. Follow-the-Leader Control for the PIPS Prototype Hardware

    NASA Technical Reports Server (NTRS)

    Williams, Robert L. II; Lippitt, Thimas

    1996-01-01

    This report describes the payload inspection and processing system (PIPS), an automated system programmed off-line for inspection of space shuttle payloads after integration and prior to launch. PIPS features a hyper-redundant 18-degree of freedom (DOF) serpentine truss manipulator capable of snake like motions to avoid obstacles. During the summer of 1995, the author worked on the same project, developing a follow-the-leader (FTL) algorithm in graphical simulation which ensures whole arm collision avoidance by forcing ensuing links to follow the same tip trajectory. The summer 1996 work was to control the prototype PIPS hardware in follow-the-leader mode. The project was successful in providing FTL control in hardware. The STS-82 payload mockup was used in the laboratory to demonstrate serpentine motions to avoid obstacles in a realistic environment.

  10. Summary of multi-core hardware and programming model investigations

    SciTech Connect

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  11. Design Tools for Reconfigurable Hardware in Orbit (RHinO)

    NASA Technical Reports Server (NTRS)

    French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

    2004-01-01

    The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

  12. Outline of a fast hardware implementation of Winograd's DFT algorithm

    NASA Technical Reports Server (NTRS)

    Zohar, S.

    1980-01-01

    The main characteristics of the discrete Fourier transform (DFT) algorithm considered by Winograd (1976) is a significant reduction in the number of multiplications. Its primary disadvantage is a higher structural complexity. It is, therefore, difficult to translate the reduced number of multiplications into faster execution of the DFT by means of a software implementation of the algorithm. For this reason, a hardware implementation is considered in the current study, taking into account a design based on the algorithm prescription discussed by Zohar (1979). The hardware implementation of a FORTRAN subroutine is proposed, giving attention to a pipelining scheme in which 5 consecutive data batches are being operated on simultaneously, each batch undergoing one of 5 processing phases.

  13. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  14. The LISA Pathfinder interferometry—hardware and system testing

    NASA Astrophysics Data System (ADS)

    Audley, H.; Danzmann, K.; García Marín, A.; Heinzel, G.; Monsky, A.; Nofrarias, M.; Steier, F.; Gerardi, D.; Gerndt, R.; Hechenblaikner, G.; Johann, U.; Luetzow-Wentzky, P.; Wand, V.; Antonucci, F.; Armano, M.; Auger, G.; Benedetti, M.; Binetruy, P.; Boatella, C.; Bogenstahl, J.; Bortoluzzi, D.; Bosetti, P.; Caleno, M.; Cavalleri, A.; Cesa, M.; Chmeissani, M.; Ciani, G.; Conchillo, A.; Congedo, G.; Cristofolini, I.; Cruise, M.; De Marchi, F.; Diaz-Aguilo, M.; Diepholz, I.; Dixon, G.; Dolesi, R.; Fauste, J.; Ferraioli, L.; Fertin, D.; Fichter, W.; Fitzsimons, E.; Freschi, M.; García Marirrodriga, C.; Gesa, L.; Gibert, F.; Giardini, D.; Grimani, C.; Grynagier, A.; Guillaume, B.; Guzmán, F.; Harrison, I.; Hewitson, M.; Hollington, D.; Hough, J.; Hoyland, D.; Hueller, M.; Huesler, J.; Jeannin, O.; Jennrich, O.; Jetzer, P.; Johlander, B.; Killow, C.; Llamas, X.; Lloro, I.; Lobo, A.; Maarschalkerweerd, R.; Madden, S.; Mance, D.; Mateos, I.; McNamara, P. W.; Mendes, J.; Mitchell, E.; Nicolini, D.; Nicolodi, D.; Pedersen, F.; Perreur-Lloyd, M.; Perreca, A.; Plagnol, E.; Prat, P.; Racca, G. D.; Rais, B.; Ramos-Castro, J.; Reiche, J.; Romera Perez, J. A.; Robertson, D.; Rozemeijer, H.; Sanjuan, J.; Schulte, M.; Shaul, D.; Stagnaro, L.; Strandmoe, S.; Sumner, T. J.; Taylor, A.; Texier, D.; Trenkel, C.; Tombolato, D.; Vitale, S.; Wanner, G.; Ward, H.; Waschke, S.; Wass, P.; Weber, W. J.; Zweifel, P.

    2011-05-01

    Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

  15. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    NASA Technical Reports Server (NTRS)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  16. Hardware Design of the Energy Efficient Fall Detection Device

    NASA Astrophysics Data System (ADS)

    Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

    2016-04-01

    Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

  17. IDEAS and App Development Internship in Hardware and Software Design

    NASA Technical Reports Server (NTRS)

    Alrayes, Rabab D.

    2016-01-01

    In this report, I will discuss the tasks and projects I have completed while working as an electrical engineering intern during the spring semester of 2016 at NASA Kennedy Space Center. In the field of software development, I completed tasks for the G-O Caching Mobile App and the Asbestos Management Information System (AMIS) Web App. The G-O Caching Mobile App was written in HTML, CSS, and JavaScript on the Cordova framework, while the AMIS Web App is written in HTML, CSS, JavaScript, and C# on the AngularJS framework. My goals and objectives on these two projects were to produce an app with an eye-catching and intuitive User Interface (UI), which will attract more employees to participate; to produce a fully-tested, fully functional app which supports workforce engagement and exploration; to produce a fully-tested, fully functional web app that assists technicians working in asbestos management. I also worked in hardware development on the Integrated Display and Environmental Awareness System (IDEAS) wearable technology project. My tasks on this project were focused in PCB design and camera integration. My goals and objectives for this project were to successfully integrate fully functioning custom hardware extenders on the wearable technology headset to minimize the size of hardware on the smart glasses headset for maximum user comfort; to successfully integrate fully functioning camera onto the headset. By the end of this semester, I was able to successfully develop four extender boards to minimize hardware on the headset, and assisted in integrating a fully-functioning camera into the system.

  18. Low extractable wipers for cleaning space flight hardware

    NASA Technical Reports Server (NTRS)

    Tijerina, Veronica; Gross, Frederick C.

    1986-01-01

    There is a need for low extractable wipers for solvent cleaning of space flight hardware. Soxhlet extraction is the method utilized today by most NASA subcontractors, but there may be alternate methods to achieve the same results. The need for low non-volatile residue materials, the history of soxhlet extraction, and proposed alternate methods are discussed, as well as different types of wipers, test methods, and current standards.

  19. TH-C-BRB-01: Open Source Hardware: General Overview.

    PubMed

    Therriault-Proulx, F

    2016-06-01

    By definition, Open Source Hardware (OSH) is "hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design". The advantages of OSH are multiple and the movement has been growing exponentially over the last couple years, leading to the spread and evolution of 3D printing technologies, the creation of affordable and easy to use micro-controller boards (Arduino, Raspberry Pi, etc.), as well as a plurality of other "hands-on"/DIY projects. As we have seen over the past few years with 3D printing, where the number of projects benefiting clinical practice as grown significantly, the highly educated and technology savvy Medical Physics community is positioned to take advantage of and benefit from paradigm-shifting movements. Sharing of knowledge, know-how, and technology can be a key factor in furthering the impact medical physicists can have. Whether it is to develop phantoms, applicators, detector holders or devices based on the use of motors and sensors, sharing design files significantly enables further development. Because these designs would be massively peer-reviewed through their online publication, improvements would be made, and the creators of the design would be rewarded with an increase number of citation of their work. A curated database of software and hardware projects can be an invaluable to the field, but a critical mass of contributors is likely needed to guarantee the most impact. This symposium will discuss the benefits and hurdles for such an endeavor.

  20. The technological future of 7 T MRI hardware.

    PubMed

    Webb, A G; Van de Moortele, P F

    2016-09-01

    In this article we present our projections of future hardware developments on 7 T human MRI systems. These include compact cryogen-light magnets, improved gradient performance, integrated RF-receive and direct current shimming coil arrays, new RF technology with adaptive impedance matching, patient-specific specific absorption rate estimation and monitoring, and increased integration of physiological monitoring systems. Copyright © 2015 John Wiley & Sons, Ltd.

  1. Nimble Compiler Environment for Agile Hardware. Volume 1

    DTIC Science & Technology

    2001-10-01

    programs to be compiled directly into custom silicon or reconfigurable architectures. Some other novel hardware synthesis systems compile Java 24, Matlab ...appreciable acceleration in some compute intensive applications. Such systems have been very difficult to program though and thus have not been explo ited...for their benefits. The problem is the lack of an appropriate design environment for system engineers like those typically found in digital signal

  2. TMS communications hardware. Volume 2: Bus interface unit

    NASA Technical Reports Server (NTRS)

    Brown, J. S.; Hopkins, G. T.

    1979-01-01

    A prototype coaxial cable bus communication system used in the Trend Monitoring System to interconnect intelligent graphics terminals to a host minicomputer is described. The terminals and host are connected to the bus through a microprocessor-based RF modem termed a Bus Interface Unit (BIU). The BIU hardware and the Carrier Sense Multiple Access Listen-While-Talk protocol used on the network are described.

  3. Environmental Conditions for Space Flight Hardware: A Survey

    NASA Technical Reports Server (NTRS)

    Plante, Jeannette; Lee, Brandon

    2005-01-01

    Interest in generalization of the physical environment experienced by NASA hardware from the natural Earth environment (on the launch pad), man-made environment on Earth (storage acceptance an d qualification testing), the launch environment, and the space environment, is ed to find commonality among our hardware in an effort to reduce cost and complexity. NASA is entering a period of increase in its number of planetary missions and it is important to understand how our qualification requirements will evolve with and track these new environments. Environmental conditions are described for NASA projects in several ways for the different periods of the mission life cycle. At the beginning, the mission manager defines survivability requirements based on the mission length, orbit, launch date, launch vehicle, and other factors . such as the use of reactor engines. Margins are then applied to these values (temperature extremes, vibration extremes, radiation tolerances, etc,) and a new set of conditions is generalized for design requirements. Mission assurance documents will then assign an additional margin for reliability, and a third set of values is provided for during testing. A fourth set of environmental condition values may evolve intermittently from heritage hardware that has been tested to a level beyond the actual mission requirement. These various sets of environment figures can make it quite confusing and difficult to capture common hardware environmental requirements. Environmental requirement information can be found in a wide variety of places. The most obvious is with the individual projects. We can easily get answers to questions about temperature extremes being used and radiation tolerance goals, but it is more difficult to map the answers to the process that created these requirements: for design, for qualification, and for actual environment with no margin applied. Not everyone assigned to a NASA project may have that kind of insight, as many have

  4. Hardware Trojans - Prevention, Detection, Countermeasures (A Literature Review)

    DTIC Science & Technology

    2011-07-01

    Testing Given the huge logical space in a modern IC, constructing a test vector that covers the entire IC logic space is computationally infeasible...20 5.2.2.3 Side-Channel Analysis . . . . . . . . . . . . . . . . . . 21 6 Countermeasures 23 6.1 Data Guards...spectrum of Hardware Trojans – their capabilities, size, trigger mechanisms, and payloads – is enormous, and the state- space of IC development both

  5. Real-Time GPS-Alternative Navigation Using Commodity Hardware

    DTIC Science & Technology

    2007-06-01

    Hypothesis The thrust of this research was to improve a state-of-the- art image-aided inertial navigation system developed in previous research at AFIT...novel, and even now is state-of-the- art GPS-alternative navigation. The previous system was built to test and demonstrate image-aided inertial...of-the- art . There have been a few attempts to augment CPU-based image processing by using programmable hardware. The objective of this type of

  6. FY16 ISCP Nuclear Counting Facility Hardware Expansion Summary

    SciTech Connect

    Church, Jennifer A.; Kashgarian, Michaele; Wooddy, Todd; Haslett, Bob; Torretto, Phil

    2016-09-15

    Hardware expansion and detector calibrations were the focus of FY 16 ISCP efforts in the Nuclear Counting Facility. Work focused on four main objectives: 1) Installation, calibration, and validation of 4 additional HPGe gamma spectrometry systems; including two Low Energy Photon Spectrometers (LEPS). 2) Re-Calibration and validation of 3 previously installed gamma-ray detectors, 3) Integration of the new systems into the NCF IT infrastructure, and 4) QA/QC and maintenance of current detector systems.

  7. Sorting and hardware assisted rendering for volume visualization

    SciTech Connect

    Stein, C.; Becker, B.; Max, N.

    1994-03-01

    We present some techniques for volume rendering unstructured data. Interpolation between vertex colors and opacities is performed using hardware assisted texture mapping, and color is integrated for use with a volume rendering system. We also present an O(n{sup 2}) method for sorting n arbitrarily shaped convex polyhedra prior to visualization. It generalizes the Newell, Newell and Sancha sort for polygons to 3-D volume elements.

  8. Hardware implementation of fuzzy Petri net as a controller.

    PubMed

    Gniewek, Lesław; Kluska, Jacek

    2004-06-01

    The paper presents a new approach to fuzzy Petri net (FPN) and its hardware implementation. The authors' motivation is as follows. Complex industrial processes can be often decomposed into many parallelly working subprocesses, which can, in turn, be modeled using Petri nets. If all the process variables (or events) are assumed to be two-valued signals, then it is possible to obtain a hardware or software control device, which works according to the algorithm described by conventional Petri net. However, the values of real signals are contained in some bounded interval and can be interpreted as events which are not only true or false, but rather true in some degree from the interval [0, 1]. Such a natural interpretation from multivalued logic (fuzzy logic) point of view, concerns sensor outputs, control signals, time expiration, etc. It leads to the idea of FPN as a controller, which one can rather simply obtain, and which would be able to process both analog, and binary signals. In the paper both graphical, and algebraic representations of the proposed FPN are given. The conditions under which transitions can be fired are described. The algebraic description of the net and a theorem which enables computation of new marking in the net, based on current marking, are formulated. Hardware implementation of the FPN, which uses fuzzy JK flip-flops and fuzzy gates, are proposed. An example illustrating usefulness of the proposed FPN for control algorithm description and its synthesis as a controller device for the concrete production process are presented.

  9. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  10. Weight and the Future of Space Flight Hardware Cost Modeling

    NASA Technical Reports Server (NTRS)

    Prince, Frank A.

    2003-01-01

    Weight has been used as the primary input variable for cost estimating almost as long as there have been parametric cost models. While there are good reasons for using weight, serious limitations exist. These limitations have been addressed by multi-variable equations and trend analysis in models such as NAFCOM, PRICE, and SEER; however, these models have not be able to address the significant time lags that can occur between the development of similar space flight hardware systems. These time lags make the cost analyst's job difficult because insufficient data exists to perform trend analysis, and the current set of parametric models are not well suited to accommodating process improvements in space flight hardware design, development, build and test. As a result, people of good faith can have serious disagreement over the cost for new systems. To address these shortcomings, new cost modeling approaches are needed. The most promising approach is process based (sometimes called activity) costing. Developing process based models will require a detailed understanding of the functions required to produce space flight hardware combined with innovative approaches to estimating the necessary resources. Particularly challenging will be the lack of data at the process level. One method for developing a model is to combine notional algorithms with a discrete event simulation and model changes to the total cost as perturbations to the program are introduced. Despite these challenges, the potential benefits are such that efforts should be focused on developing process based cost models.

  11. Efficient Execution of Recursive Programs on Commodity Vector Hardware

    SciTech Connect

    Ren, Bin; Jo, Youngjoon; Krishnamoorthy, Sriram; Agrawal, Kunal; Kulkarni, Milind

    2015-06-13

    The pursuit of computational efficiency has led to the proliferation of throughput-oriented hardware, from GPUs to increasingly-wide vector units on commodity processors and accelerators. This hardware is designed to efficiently execute data-parallel computations in a vectorized manner. However, many algorithms are more naturally expressed as divide-and-conquer, recursive, task-parallel computations; in the absence of data parallelism, it seems that such algorithms are not well-suited to throughput-oriented architectures. This paper presents a set of novel code transformations that expose the data-parallelism latent in recursive, task-parallel programs. These transformations facilitate straightforward vectorization of task-parallel programs on commodity hardware. We also present scheduling policies that maintain high utilization of vector resources while limiting space usage. Across several task-parallel benchmarks, we demonstrate both efficient vector resource utilization and substantial speedup on chips using Intel's SSE4.2 vector units as well as accelerators using Intel's AVX512 units.

  12. Hardware demonstration of high-speed networks for satellite applications.

    SciTech Connect

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  13. Accelerating reconstruction of reference digital tomosynthesis using graphics hardware.

    PubMed

    Yan, Hui; Ren, Lei; Godfrey, Devon J; Yin, Fang-Fang

    2007-10-01

    The successful implementation of digital tomosynthesis (DTS) for on-board image guided radiation therapy (IGRT) requires fast DTS image reconstruction. Both target and reference DTS image sets are required to support an image registration application for IGRT. Target images are usually DTS image sets reconstructed from on-board projections, which can be accomplished quickly using the conventional filtered backprojection algorithm. Reference images are DTS image sets reconstructed from digitally reconstructed radiographs (DRRs) previously generated from conventional planning CT data. Generating a set of DRRs from planning CT is relatively slow using the conventional ray-casting algorithm. In order to facilitate DTS reconstruction within a clinically acceptable period of time, we implemented a high performance DRR reconstruction algorithm on a graphics processing unit of commercial PC graphics hardware. The performance of this new algorithm was evaluated and compared with that which is achieved using the conventional software-based ray-casting algorithm. DTS images were reconstructed from DRRs previously generated by both hardware and software algorithms. On average, the DRR reconstruction efficiency using the hardware method is improved by a factor of 67 over the software method. The image quality of the DRRs was comparable to those generated using the software-based ray-casting algorithm. Accelerated DRR reconstruction significantly reduces the overall time required to produce a set of reference DTS images from planning CT and makes this technique clinically practical for target localization for radiation therapy.

  14. Hardware Design Improvements to the Major Constituent Analyzer

    NASA Technical Reports Server (NTRS)

    Combs, Scott; Schwietert, Daniel; Anaya, Marcial; DeWolf, Shannon; Merrill, Dave; Gardner, Ben D.; Thoresen, Souzan; Granahan, John; Belcher, Paul; Matty, Chris

    2011-01-01

    The Major Constituent Analyzer (MCA) onboard the International Space Station (ISS) is designed to monitor the major constituents of the ISS's internal atmosphere. This mass spectrometer based system is an integral part of the Environmental Control and Life Support System (ECLSS) and is a primary tool for the management of ISS atmosphere composition. As a part of NASA Change Request CR10773A, several alterations to the hardware have been made to accommodate improved MCA logistics. First, the ORU 08 verification gas assembly has been modified to allow the verification gas cylinder to be installed on orbit. The verification gas is an essential MCA consumable that requires periodic replenishment. Designing the cylinder for subassembly transport reduces the size and weight of the maintained item for launch. The redesign of the ORU 08 assembly includes a redesigned housing, cylinder mounting apparatus, and pneumatic connection. The second hardware change is a redesigned wiring harness for the ORU 02 analyzer. The ORU 02 electrical connector interface was damaged in a previous on-orbit installation, and this necessitated the development of a temporary fix while a more permanent solution was developed. The new wiring harness design includes flexible cable as well as indexing fasteners and guide-pins, and provides better accessibility during the on-orbit maintenance operation. This presentation will describe the hardware improvements being implemented for MCA as well as the expected improvement to logistics and maintenance.

  15. 2D neural hardware versus 3D biological ones

    SciTech Connect

    Beiu, V.

    1998-12-31

    This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

  16. Advanced Technology Development: Solid-Liquid Interface Characterization Hardware

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Characterizing the solid-liquid interface during directional solidification is key to understanding and improving material properties. The goal of this Advanced Technology Development (ATD) has been to develop hardware, which will enable real-time characterization of practical materials, such as aluminum (Al) alloys, to unprecedented levels. Required measurements include furnace and sample temperature gradients, undercooling at the growing interface, interface shape, or morphology, and furnace translation and sample growth rates (related). These and other parameters are correlated with each other and time. A major challenge was to design and develop all of the necessary hardware to measure the characteristics, nearly simultaneously, in a smaller integral furnace compatible with existing X-ray Transmission Microscopes, XTMs. Most of the desired goals have been accomplished through three generations of Seebeck furnace brassboards, several varieties of film thermocouple arrays, heaters, thermal modeling of the furnaces, and data acquisition and control (DAC) software. Presentations and publications have resulted from these activities, and proposals to use this hardware for further materials studies have been submitted as sequels to this last year of the ATD.

  17. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

    PubMed

    Ly, Daniel Le; Chow, Paul

    2010-11-01

    Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

  18. NCERA-101 STATION REPORT - KENNEDY SPACE CENTER: Large Plant Growth Hardware for the International Space Station

    NASA Technical Reports Server (NTRS)

    Massa, Gioia D.

    2013-01-01

    This is the station report for the national controlled environments meeting. Topics to be discussed will include the Veggie and Advanced Plant Habitat ISS hardware. The goal is to introduce this hardware to a potential user community.

  19. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 34 Education 3 2010-07-01 2010-07-01 false What limit applies to purchasing computer hardware and... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f))...

  20. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... 34 Education 3 2011-07-01 2011-07-01 false What limit applies to purchasing computer hardware and... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f))...

  1. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 34 Education 3 2012-07-01 2012-07-01 false What limit applies to purchasing computer hardware and... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f))...

  2. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 34 Education 3 2014-07-01 2014-07-01 false What limit applies to purchasing computer hardware and... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f))...

  3. 34 CFR 464.42 - What limit applies to purchasing computer hardware and software?

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 34 Education 3 2013-07-01 2013-07-01 false What limit applies to purchasing computer hardware and... computer hardware and software? Not more than ten percent of funds received under any grant under this part may be used to purchase computer hardware or software. (Authority: 20 U.S.C. 1208aa(f))...

  4. 49 CFR 238.105 - Train electronic hardware and software safety.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... 49 Transportation 4 2012-10-01 2012-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions...

  5. 49 CFR 238.105 - Train electronic hardware and software safety.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... 49 Transportation 4 2013-10-01 2013-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions...

  6. 49 CFR 238.105 - Train electronic hardware and software safety.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... 49 Transportation 4 2014-10-01 2014-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions...

  7. 49 CFR 238.105 - Train electronic hardware and software safety.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions...

  8. 49 CFR 238.105 - Train electronic hardware and software safety.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... 49 Transportation 4 2011-10-01 2011-10-01 false Train electronic hardware and software safety. 238... and General Requirements § 238.105 Train electronic hardware and software safety. The requirements of this section apply to electronic hardware and software used to control or monitor safety functions...

  9. Using Innovative Techniques for Manufacturing Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, Erin M.; Reynolds, David C.; Eddleman, David E.; Hardin, Andy

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using the Workhorse Gas Generator (WHGG) test setup at MSFC?s East Test Area test stand 116, the duct was subject to extreme J-2X gas generator environments and endured a total of 538 seconds of hot-fire time. The duct survived the testing and was inspected after the test. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  10. An update on SCARLET hardware development and flight programs

    NASA Technical Reports Server (NTRS)

    Jones, P. Alan; Murphy, David M.; Piszczor, Michael F.; Allen, Douglas M.

    1995-01-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the 'array level' and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  11. Multi-User Hardware Solutions to Combustion Science ISS Research

    NASA Technical Reports Server (NTRS)

    Otero, Angel M.

    2001-01-01

    In response to the budget environment and to expand on the International Space Station (ISS) Fluids and Combustion Facility (FCF) Combustion Integrated Rack (CIR), common hardware approach, the NASA Combustion Science Program shifted focus in 1999 from single investigator PI (Principal Investigator)-specific hardware to multi-user 'Minifacilities'. These mini-facilities would take the CIR common hardware philosophy to the next level. The approach that was developed re-arranged all the investigations in the program into sub-fields of research. Then common requirements within these subfields were used to develop a common system that would then be complemented by a few PI-specific components. The sub-fields of research selected were droplet combustion, solids and fire safety, and gaseous fuels. From these research areas three mini-facilities have sprung: the Multi-user Droplet Combustion Apparatus (MDCA) for droplet research, Flow Enclosure for Novel Investigations in Combustion of Solids (FEANICS) for solids and fire safety, and the Multi-user Gaseous Fuels Apparatus (MGFA) for gaseous fuels. These mini-facilities will develop common Chamber Insert Assemblies (CIA) and diagnostics for the respective investigators complementing the capability provided by CIR. Presently there are four investigators for MDCA, six for FEANICS, and four for MGFA. The goal of these multi-user facilities is to drive the cost per PI down after the initial development investment is made. Each of these mini-facilities will become a fixture of future Combustion Science NASA Research Announcements (NRAs), enabling investigators to propose against an existing capability. Additionally, an investigation is provided the opportunity to enhance the existing capability to bridge the gap between the capability and their specific science requirements. This multi-user development approach will enable the Combustion Science Program to drive cost per investigation down while drastically reducing the time

  12. Advances in metered dose inhaler technology: hardware development.

    PubMed

    Stein, Stephen W; Sheth, Poonam; Hodson, P David; Myrdal, Paul B

    2014-04-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering valve capable of delivering a consistent amount of drug with each dose delivered, an actuator mouthpiece that atomizes the formulation and serves as a conduit to deliver the aerosol to the patient, and often an indicating mechanism that provides information to the patient on the number of doses remaining. This review focuses on the current state-of-the-art of MDI hardware and includes discussion of enhancements made to the device's core subsystems. In addition, technologies that aid the correct use of MDIs will be discussed. These include spacers, valved holding chambers, and breath-actuated devices. Many of the improvements discussed in this article increase the ability of MDI systems to meet regulatory specifications. Innovations that enhance the functionality of MDIs continue to be balanced by the fact that a key advantage of MDI systems is their low cost per dose. The expansion of the health care market in developing countries and the increased focus on health care costs in many developed countries will ensure that MDIs remain a cost-effective crucial delivery system for treating pulmonary conditions for many years to come.

  13. Using Innovative Technologies for Manufacturing Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  14. Defining Exercise Performance Metrics for Flight Hardware Development

    NASA Technical Reports Server (NTRS)

    Beyene, Nahon M.

    2004-01-01

    The space industry has prevailed over numerous design challenges in the spirit of exploration. Manned space flight entails creating products for use by humans and the Johnson Space Center has pioneered this effort as NASA's center for manned space flight. NASA Astronauts use a suite of flight exercise hardware to maintain strength for extravehicular activities and to minimize losses in muscle mass and bone mineral density. With a cycle ergometer, treadmill, and the Resistive Exercise Device available on the International Space Station (ISS), the Space Medicine community aspires to reproduce physical loading schemes that match exercise performance in Earth s gravity. The resistive exercise device presents the greatest challenge with the duty of accommodating 20 different exercises and many variations on the core set of exercises. This paper presents a methodology for capturing engineering parameters that can quantify proper resistive exercise performance techniques. For each specified exercise, the method provides engineering parameters on hand spacing, foot spacing, and positions of the point of load application at the starting point, midpoint, and end point of the exercise. As humans vary in height and fitness levels, the methodology presents values as ranges. In addition, this method shows engineers the proper load application regions on the human body. The methodology applies to resistive exercise in general and is in use for the current development of a Resistive Exercise Device. Exercise hardware systems must remain available for use and conducive to proper exercise performance as a contributor to mission success. The astronauts depend on exercise hardware to support extended stays aboard the ISS. Future plans towards exploration of Mars and beyond acknowledge the necessity of exercise. Continuous improvement in technology and our understanding of human health maintenance in space will allow us to support the exploration of Mars and the future of space

  15. An update on SCARLET hardware development and flight programs

    SciTech Connect

    Jones, P.A.; Murphy, D.M.; Piszczor, M.F.; Allen, D.M. |

    1995-10-01

    Solar Concentrator Array with Refractive Linear Element Technology (SCARLET) is one of the first practical photovoltaic concentrator array technologies that offers a number of benefits for space applications (i.e. high array efficiency, protection from space radiation effects, a relatively light weight system, minimized plasma interactions, etc.) The line-focus concentrator concept, however, also offers two very important advantages: (1) low-cost mass production potential of the lens material; and (2) relaxation of precise array tracking requirements to only a single axis. These benefits offer unique capabilities to both commercial and government spacecraft users, specifically those interested in high radiation missions, such as MEO orbits, and electric-powered propulsion LEO-to-GEO orbit raising applications. SCARLET is an aggressive hardware development and flight validation program sponsored by the Ballistic Missile Defense Organization (BMDO) and NASA Lewis Research Center. Its intent is to bring technology to the level of performance and validation necessary for use by various government and commercial programs. The first phase of the SCARLET program culminated with the design, development and fabrication of a small concentrator array for flight on the METEOR satellite. This hardware will be the first in-space demonstration of concentrator technology at the `array level` and will provide valuable in-orbit performance measurements. The METEOR satellite is currently planned for a September/October 1995 launch. The next phase of the program is the development of large array for use by one of the NASA New Millenium Program missions. This hardware will incorporate a number of the significant improvements over the basic METEOR design. This presentation will address the basic SCARLET technology, examine its benefits to users, and describe the expected improvements for future missions.

  16. Evolvable hardware: genetic search in a physical realm

    NASA Astrophysics Data System (ADS)

    Raichman, Nadav; Segev, Ronen; Ben-Jacob, Eshel

    2003-08-01

    The application of evolution-inspired strategies to hardware design and circuit self-configuration leads to the concept of evolvable hardware (EHW). EHW refers to self-configuration of electronic hardware by evolutionary/genetic algorithms (EA and GA, respectively). Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing for EHW. Here we applied an evolutionary algorithm on a configurable digital FPGA chip in order to evolve analog-behavior circuits. Though the configurable chip is explicitly built for digital designs, analog circuits were successfully evolved by allowing feedback routings and by disabling the general clock. The results were unconventional circuits that were well fitted both to the task for which the circuits were evolved, and to the environment in which the evolution took place. We analyzed the morphotype (configuration) changes in circuit size and circuit operation through evolutionary time. The results showed that the evolved circuit structure had two distinct areas: an active area in which signal processing took place and a surrounding neutral area. The active area of the evolved circuits was small in size, but complex in structure. Results showed that the active area may grow during evolution, indicating that progress is achieved through the addition of units taken from the neutral area. Monitor views of the circuit outputs through evolution indicate that several distinct stages occurred in which evolution evolved. This is in accordance with the plots of fitness that show a progressive climb in a stair-like manner. Competitive studies were also performed of evolutions with various population sizes. Results showed that the smaller the size of the evolved population, the faster was the evolutionary process. This was attributed to the high degeneracy in gene variance within the large population, resulting in a futile search.

  17. Spray drying technique. I: Hardware and process parameters.

    PubMed

    Cal, Krzysztof; Sollohub, Krzysztof

    2010-02-01

    Spray drying is a transformation of feed from a fluid state into a dried particulate form by spraying the feed into a hot drying medium. The main aim of drying by this method in pharmaceutical technology is to obtain dry particles with desired properties. This review presents the hardware and process parameters that affect the properties of the dried product. The atomization devices, drying chambers, air-droplet contact systems, the collection of dried product, auxiliary devices, the conduct of the spray drying process, and the significance of the individual parameters in the drying process, as well as the obtained product, are described and discussed.

  18. Hardware structures of hydronic systems for speed control

    NASA Astrophysics Data System (ADS)

    Avram, M.; Spânu, A.; Bucşan, C.; Besnea, D.

    2016-08-01

    Most hydraulic actuating systems use constant flow pumps, for economic reasons. The resistive method is then used to control the speed of the actuated load. In the case of high performance systems the flow area is modified using analogical or numeric electric commands applied to proportional flow control devices. In the first part of the paper some hardware structures of hydronic actuating systems used for speed control are presented, and in the second part two experimental models of such systems are presented. Some aspects regarding the output improvement of such a system are also considered.

  19. Benchmarking and Hardware-In-The-Loop Operation of a ...

    EPA Pesticide Factsheets

    Engine Performance evaluation in support of LD MTE. EPA used elements of its ALPHA model to apply hardware-in-the-loop (HIL) controls to the SKYACTIV engine test setup to better understand how the engine would operate in a chassis test after combined with future leading edge technologies, advanced high-efficiency transmission, reduced mass, and reduced roadload. Predict future vehicle performance with Atkinson engine. As part of its technology assessment for the upcoming midterm evaluation of the 2017-2025 LD vehicle GHG emissions regulation, EPA has been benchmarking engines and transmissions to generate inputs for use in its ALPHA model

  20. Hardware-based Rendering of Full-parallax Synthetic Holograms

    NASA Astrophysics Data System (ADS)

    Ritter, Alf; Böttger, Joachim; Deussen, Oliver; König, Matthias; Strothotte, Thomas

    1999-03-01

    We present a method for efficiently calculating the interference of complex-valued two-dimensional wave patterns that is useful during the generation of synthetic holograms. These patterns are represented as a special kind of images (textures), and the interference is calculated in a computer graphics rendering process. This enables us to leverage hardware support for holographic imaging that is implemented in many state-of-the-art computer workstations. Using this approach, we gain a speedup of a factor of 60 90 compared with conventional calculation methods for interfering wave patterns. Our method is evaluated numerically, examples are shown, and the program code is outlined.

  1. Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

    NASA Astrophysics Data System (ADS)

    Hasan, M. A.; Reaz, M. B. I.

    2012-01-01

    The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

  2. Parallel Processing with Digital Signal Processing Hardware and Software

    NASA Technical Reports Server (NTRS)

    Swenson, Cory V.

    1995-01-01

    The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

  3. Resolution-independent surface rendering using programmable graphics hardware

    DOEpatents

    Loop, Charles T.; Blinn, James Frederick

    2008-12-16

    Surfaces defined by a Bezier tetrahedron, and in particular quadric surfaces, are rendered on programmable graphics hardware. Pixels are rendered through triangular sides of the tetrahedra and locations on the shapes, as well as surface normals for lighting evaluations, are computed using pixel shader computations. Additionally, vertex shaders are used to aid interpolation over a small number of values as input to the pixel shaders. Through this, rendering of the surfaces is performed independently of viewing resolution, allowing for advanced level-of-detail management. By individually rendering tetrahedrally-defined surfaces which together form complex shapes, the complex shapes can be rendered in their entirety.

  4. Study of hardware implementations of fast tracking algorithms

    NASA Astrophysics Data System (ADS)

    Song, Z.; De Lentdecker, G.; Dong, J.; Huang, G.; Léonard, A.; Robert, F.; Wang, D.; Yang, Y.

    2017-02-01

    Real-time track reconstruction at high event rates is a major challenge for future experiments in high energy physics. To perform pattern-recognition and track fitting, artificial retina or Hough transformation methods have been introduced in the field which have to be implemented in FPGA firmware. In this note we report on a case study of a possible FPGA hardware implementation approach of the retina algorithm based on a Floating-Point core. Detailed measurements with this algorithm are investigated. Retina performance and capabilities of the FPGA are discussed along with perspectives for further optimization and applications.

  5. Configurable Hardware And Software For Multiple Related Uses

    NASA Technical Reports Server (NTRS)

    Uhrlaub, David R.; Gaines, James M.; Snoddy, William E.; Bard, Richard D.; Robinson, Lawrence W.

    1996-01-01

    Control Monitor Unit (CMU) is system of configurable hardware and software undergoing development for use in controlling and monitoring complex systems of equipment. Provides comprehensive array of capabilities for such functions as processing equipment-test data for calibration and diagnosis, controlling operation of equipment in real time, simulating operation of equipment, and processing large streams of scientific-measurement data. Automates many of ground operations involved in preparing and testing spacecraft prior to launch. Also useful in variety of similar applications; for example, testing aircraft, ships, power plants, and automated production lines.

  6. Hardware support for software controlled fast reconfiguration of performance counters

    DOEpatents

    Salapura, Valentina; Wisniewski, Robert W

    2013-09-24

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  7. Data storage technology: Hardware and software, Appendix B

    NASA Technical Reports Server (NTRS)

    Sable, J. D.

    1972-01-01

    This project involves the development of more economical ways of integrating and interfacing new storage devices and data processing programs into a computer system. It involves developing interface standards and a software/hardware architecture which will make it possible to develop machine independent devices and programs. These will interface with the machine dependent operating systems of particular computers. The development project will not be to develop the software which would ordinarily be the responsibility of the manufacturer to supply, but to develop the standards with which that software is expected to confirm in providing an interface with the user or storage system.

  8. Hardware support for software controlled fast reconfiguration of performance counters

    DOEpatents

    Salapura, Valentina; Wisniewski, Robert W.

    2013-06-18

    Hardware support for software controlled reconfiguration of performance counters may include a plurality of performance counters collecting one or more counts of one or more selected activities. A storage element stores data value representing a time interval, and a timer element reads the data value and detects expiration of the time interval based on the data value and generates a signal. A plurality of configuration registers stores a set of performance counter configurations. A state machine receives the signal and selects a configuration register from the plurality of configuration registers for reconfiguring the one or more performance counters.

  9. Modern hardware architectures accelerate porous media flow computations

    NASA Astrophysics Data System (ADS)

    Kulczewski, Michal; Kurowski, Krzysztof; Kierzynka, Michal; Dohnalik, Marek; Kaczmarczyk, Jan; Borujeni, Ali Takbiri

    2012-05-01

    Investigation of rock properties, porosity and permeability particularly, which determines transport media characteristic, is crucial to reservoir engineering. Nowadays, micro-tomography (micro-CT) methods allow to obtain vast of petro-physical properties. The micro-CT method facilitates visualization of pores structures and acquisition of total porosity factor, determined by sticking together 2D slices of scanned rock and applying proper absorption cut-off point. Proper segmentation of pores representation in 3D is important to solve the permeability of porous media. This factor is recently determined by the means of Computational Fluid Dynamics (CFD), a popular method to analyze problems related to fluid flows, taking advantage of numerical methods and constantly growing computing powers. The recent advent of novel multi-, many-core and graphics processing unit (GPU) hardware architectures allows scientists to benefit even more from parallel processing and built-in new features. The high level of parallel scalability offers both, the time-to-solution decrease and greater accuracy - top factors in reservoir engineering. This paper aims to present research results related to fluid flow simulations, particularly solving the total porosity and permeability of porous media, taking advantage of modern hardware architectures. In our approach total porosity is calculated by the means of general-purpose computing on multiple GPUs. This application sticks together 2D slices of scanned rock and by the means of a marching tetrahedra algorithm, creates a 3D representation of pores and calculates the total porosity. Experimental results are compared with data obtained via other popular methods, including Nuclear Magnetic Resonance (NMR), helium porosity and nitrogen permeability tests. Then CFD simulations are performed on a large-scale high performance hardware architecture to solve the flow and permeability of porous media. In our experiments we used Lattice Boltzmann

  10. System for processing an encrypted instruction stream in hardware

    SciTech Connect

    Griswold, Richard L.; Nickless, William K.; Conrad, Ryan C.

    2016-04-12

    A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal.

  11. Evaluation of pressurized water cleaning systems for hardware refurbishment

    NASA Technical Reports Server (NTRS)

    Dillard, Terry W.; Deweese, Charles D.; Hoppe, David T.; Vickers, John H.; Swenson, Gary J.; Hutchens, Dale E.

    1995-01-01

    Historically, refurbishment processes for RSRM motor cases and components have employed environmentally harmful materials. Specifically, vapor degreasing processes consume and emit large amounts of ozone depleting compounds. This program evaluates the use of pressurized water cleaning systems as a replacement for the vapor degreasing process. Tests have been conducted to determine if high pressure water washing, without any form of additive cleaner, is a viable candidate for replacing vapor degreasing processes. This paper discusses the findings thus far of Engineering Test Plan - 1168 (ETP-1168), 'Evaluation of Pressurized Water Cleaning Systems for Hardware Refurbishment.'

  12. Verification Challenges of Dynamic Testing of Space Flight Hardware

    NASA Technical Reports Server (NTRS)

    Winnitoy, Susan

    2010-01-01

    The Six Degree-of-Freedom Dynamic Test System (SDTS) is a test facility at the National Aeronautics and Space Administration (NASA) Johnson Space Center in Houston, Texas for performing dynamic verification of space structures and hardware. Some examples of past and current tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility is able to integrate a dynamic simulation of on-orbit spacecraft mating or demating using flight-like mechanical interface hardware. A force moment sensor is utilized for input to the simulation during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents many unique challenges, one particular area of interest is with respect to the use of external measurement systems to ensure accurate feedback of dynamic contact. There are many commercial off-the-shelf (COTS) measurement systems available on the market, and the test facility measurement systems have evolved over time to include two separate COTS systems. The first system incorporates infra-red sensing cameras, while the second system employs a laser interferometer to determine position and orientation data. The specific technical challenges with the measurement systems in a large dynamic environment include changing thermal and humidity levels, operational area and measurement volume, dynamic tracking, and data synchronization. The facility is located in an expansive high-bay area that is occasionally exposed to outside temperature when large retractable doors at each end of the building are opened. The laser interferometer system, in particular, is vulnerable to the environmental changes in the building. The operational area of the test facility itself is sizeable, ranging from seven meters wide and five meters deep to as much as seven meters high. Both facility measurement systems have desirable measurement volumes and the accuracies vary

  13. Development of Hardware-in-the-loop Microgrid Testbed

    SciTech Connect

    Xiao, Bailu; Prabakar, Kumaraguru; Starke, Michael R; Liu, Guodong; Dowling, Kevin; Ollis, T Ben; Irminger, Philip; Xu, Yan; Dimitrovski, Aleksandar D

    2015-01-01

    A hardware-in-the-loop (HIL) microgrid testbed for the evaluation and assessment of microgrid operation and control system has been presented in this paper. The HIL testbed is composed of a real-time digital simulator (RTDS) for modeling of the microgrid, multiple NI CompactRIOs for device level control, a prototype microgrid energy management system (MicroEMS), and a relay protection system. The applied communication-assisted hybrid control system has been also discussed. Results of function testing of HIL controller, communication, and the relay protection system are presented to show the effectiveness of the proposed HIL microgrid testbed.

  14. Evolvable Hardware for Extreme Environments: Hot or Cold

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Thakoor, A.; Keymeulen, D.; Zebulum, R.; Daud, T.; Toomarian, B.

    2001-01-01

    Temperature tolerant electronics and long life survivability are key capabilities required for future NASA/JPL missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. Compensation techniques, e.g., as offered by bias cancellation circuits, have also been employed. This paper presents a novel approach, based on evolvable hardware technology, which allows adaptive in situ circuit redesign/reconfiguration during the operation in the environment. This technology would complement material/device advancements and bring closer the success of missions in harsh environments. Additional information is contained in the original extended abstract.

  15. Energy Efficient Engine combustor test hardware detailed design report

    NASA Technical Reports Server (NTRS)

    Burrus, D. L.; Chahrour, C. A.; Foltz, H. L.; Sabla, P. E.; Seto, S. P.; Taylor, J. R.

    1984-01-01

    The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

  16. First Light with the NRAO Transient Event Capture Hardware

    NASA Astrophysics Data System (ADS)

    Langston, Glen; Rumberg, B.; Brandt, P.

    2007-12-01

    The design, implementation and testing of the first NRAO Event Capture data acquisition system is presented. The NRAO in Green Bank is developing a set of new data acquisition systems based on the U.C. Berkeley CASPER IBOB/ADC/BEE2 hardware. We describe the hardware configuration and initial experiences with the development system. We present first astronomical tests of the Event Capture system, using the 43m telescope (140ft). These observations were carried out at 900 MHz. The observations were made on 2007 July 8 and 9 towards the Crab pulsar, the galactic center, the Moon and two test observations while the 43m was pointed at Zenith (straight up). The Event Capture is one of several on-going FPGA based data acquisition projects being implemented for the Robert C. Byrd Green Bank Telescope (GBT) and for the 43m telescopes. The NRAO Configurable Instrument Collaboration for Agile Data Acquisition (CICADA) program is described at: http://wikio.nrao.edu/bin/view/CICADA

  17. Investigation of Cleanliness Verification Techniques for Rocket Engine Hardware

    NASA Technical Reports Server (NTRS)

    Fritzemeier, Marilyn L.; Skowronski, Raymund P.

    1994-01-01

    Oxidizer propellant systems for liquid-fueled rocket engines must meet stringent cleanliness requirements for particulate and nonvolatile residue. These requirements were established to limit residual contaminants which could block small orifices or ignite in the oxidizer system during engine operation. Limiting organic residues in high pressure oxygen systems, such as in the Space Shuttle Main Engine (SSME), is particularly important. The current method of cleanliness verification for the SSME uses an organic solvent flush of the critical hardware surfaces. The solvent is filtered and analyzed for particulate matter followed by gravimetric determination of the nonvolatile residue (NVR) content of the filtered solvent. The organic solvents currently specified for use (1, 1, 1-trichloroethane and CFC-113) are ozone-depleting chemicals slated for elimination by December 1995. A test program is in progress to evaluate alternative methods for cleanliness verification that do not require the use of ozone-depleting chemicals and that minimize or eliminate the use of solvents regulated as hazardous air pollutants or smog precursors. Initial results from the laboratory test program to evaluate aqueous-based methods and organic solvent flush methods for NVR verification are provided and compared with results obtained using the current method. Evaluation of the alternative methods was conducted using a range of contaminants encountered in the manufacture of rocket engine hardware.

  18. Hubble (HST) hardware is uncrated in the PHSF

    NASA Technical Reports Server (NTRS)

    1999-01-01

    In the Payload Hazardous Servicing Facility (PHSF), a crane lifts equipment for mission STS-103 out of its shipping container to move it to a workstand. The equipment is the first part of payload flight hardware for the third Hubble Space Telescope Servicing Mission (SM-3A). The hardware will undergo final testing and integration of payload elements in the PHSF. Mission STS-103 is a 'call-up' mission which is being planned due to the need to replace portions of the Hubble's pointing system, the gyros, which have begun to fail. Although Hubble is operating normally and conducting its scientific observations, only three of its six gyroscopes are working properly. The gyroscopes allow the telescope to point at stars, galaxies and planets. The STS-103 crew will not only replace gyroscopes, it will also replace a Fine Guidance Sensor and an older computer with a new enhanced model, an older data tape recorder with a solid state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Launch of STS-103 is currently targeted for Oct. 14 but the date is under review.

  19. The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

    NASA Astrophysics Data System (ADS)

    Kathiara, Jainik

    There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

  20. Hubble (HST) hardware is unwrapped in the PHSF

    NASA Technical Reports Server (NTRS)

    1999-01-01

    Inside the Payload Hazardous Servicing Facility (PHSF), a part of payload flight hardware, intended for the third Hubble Space Telescope Servicing Mission (SM-3A), is revealed after its protective cover has been removed. The hardware will undergo final testing and integration of payload elements in the PHSF. Mission STS-103 is a 'call-up' mission which is being planned due to the need to replace portions of the Hubble's pointing system, the gyros, which have begun to fail. Although Hubble is operating normally and conducting its scientific observations, only three of its six gyroscopes are working properly. The gyroscopes allow the telescope to point at stars, galaxies and planets. The STS-103 crew will not only replace gyroscopes, it will also replace a Fine Guidance Sensor and an older computer with a new enhanced model, an older data tape recorder with a solid state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Launch of STS-103 is currently targeted for Oct. 14 but the date is under review.

  1. Proposed hardware architectures of particle filter for object tracking

    NASA Astrophysics Data System (ADS)

    Abd El-Halym, Howida A.; Mahmoud, Imbaby Ismail; Habib, SED

    2012-12-01

    In this article, efficient hardware architectures for particle filter (PF) are presented. We propose three different architectures for Sequential Importance Resampling Filter (SIRF) implementation. The first architecture is a two-step sequential PF machine, where particle sampling, weight, and output calculations are carried out in parallel during the first step followed by sequential resampling in the second step. For the weight computation step, a piecewise linear function is used instead of the classical exponential function. This decreases the complexity of the architecture without degrading the results. The second architecture speeds up the resampling step via a parallel, rather than a serial, architecture. This second architecture targets a balance between hardware resources and the speed of operation. The third architecture implements the SIRF as a distributed PF composed of several processing elements and central unit. All the proposed architectures are captured using VHDL synthesized using Xilinx environment, and verified using the ModelSim simulator. Synthesis results confirmed the resource reduction and speed up advantages of our architectures.

  2. A hardware fast tracker for the ATLAS trigger

    NASA Astrophysics Data System (ADS)

    Asbah, Nedaa

    2016-09-01

    The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

  3. Investigation of cleanliness verification techniques for rocket engine hardware

    NASA Astrophysics Data System (ADS)

    Fritzemeier, Marilyn L.; Skowronski, Raymund P.

    1995-03-01

    Oxidizer propellant systems for liquid-fueled rocket engines must meet stringent cleanliness requirements for particulate and nonvolatile residue. These requirements were established to limit residual contaminants which could block small orifices or ignite in the oxidizer system during engine operation. Limiting organic residues in high pressure oxygen systems is particularly important. The current method of cleanliness verification used by Rocketdyne requires an organic solvent flush of the critical hardware surfaces. The solvent is filtered and analyzed for particulate matter, followed by gravimetric determination of the nonvolatile residue (NVR) content of the filtered solvent. The organic solvents currently specified for use (1,1,1-trichloroethane and CFC-113) are ozone-depleting chemicals slated for elimination by December 1995. A test program is in progress to evaluate alternative methods for cleanliness verification that do not require the use of ozone-depleting chemicals and that minimize or eliminate the use of solvents regulated as hazardous air pollutants or smog precursors. Initial results from the laboratory test program to evaluate aqueous-based methods and organic solvent flush methods for NVR verification are provided and compared with results obtained using the current method. Evaluation of the alternative methods was conducted using a range of contaminants encountered in the manufacture of rocket engine hardware.

  4. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry

    NASA Astrophysics Data System (ADS)

    Wang, Xin; Yang, James N.; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-01

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm2. The results showed that the rod increased the dose to water by ˜6% at the water-rod interface because of electron backscattering and decreased the dose by ˜7% in the shadow of the rod because of photon attenuation. The Pinnacle3 treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm-3 was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm-3 (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm-3 to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  5. Testing of hardware implementation of infrared image enhancing algorithm

    NASA Astrophysics Data System (ADS)

    Dulski, R.; Sosnowski, T.; PiÄ tkowski, T.; Trzaskawka, P.; Kastek, M.; Kucharz, J.

    2012-10-01

    The interpretation of IR images depends on radiative properties of observed objects and surrounding scenery. Skills and experience of an observer itself are also of great importance. The solution to improve the effectiveness of observation is utilization of algorithm of image enhancing capable to improve the image quality and the same effectiveness of object detection. The paper presents results of testing the hardware implementation of IR image enhancing algorithm based on histogram processing. Main issue in hardware implementation of complex procedures for image enhancing algorithms is high computational cost. As a result implementation of complex algorithms using general purpose processors and software usually does not bring satisfactory results. Because of high efficiency requirements and the need of parallel operation, the ALTERA's EP2C35F672 FPGA device was used. It provides sufficient processing speed combined with relatively low power consumption. A digital image processing and control module was designed and constructed around two main integrated circuits: a FPGA device and a microcontroller. Programmable FPGA device performs image data processing operations which requires considerable computing power. It also generates the control signals for array readout, performs NUC correction and bad pixel mapping, generates the control signals for display module and finally executes complex image processing algorithms. Implemented adaptive algorithm is based on plateau histogram equalization. Tests were performed on real IR images of different types of objects registered in different spectral bands. The simulations and laboratory experiments proved the correct operation of the designed system in executing the sophisticated image enhancement.

  6. A hardware overview of the RHIC LLRF platform

    SciTech Connect

    Hayes, T.; Smith, K.S.

    2011-03-28

    The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

  7. FFT and cone-beam CT reconstruction on graphics hardware

    NASA Astrophysics Data System (ADS)

    Després, Philippe; Sun, Mingshan; Hasegawa, Bruce H.; Prevrhal, Sven

    2007-03-01

    Graphics processing units (GPUs) are increasingly used for general purpose calculations. Their pipelined architecture can be exploited to accelerate various parallelizable algorithms. Medical imaging applications are inherently well suited to benefit from the development of GPU-based computational platforms. We evaluate in this work the potential of GPUs to improve the execution speed of two common medical imaging tasks, namely Fourier transforms and tomographic reconstructions. A two-dimensional fast Fourier transform (FFT) algorithm was GPU-implemented and compared, in terms of execution speed, to two popular CPU-based FFT routines. Similarly, the Feldkamp, David and Kress (FDK) algorithm for cone-beam tomographic reconstruction was implemented on the GPU and its performance compared to a CPU version. Different reconstruction strategies were employed to assess the performance of various GPU memory layouts. For the specific hardware used, GPU implementations of the FFT were up to 20 times faster than their CPU counterparts, but slower than highly optimized CPU versions of the algorithm. Tomographic reconstructions were faster on the GPU by a factor up to 30, allowing 256 3 voxel reconstructions of 256 projections in about 20 seconds. Overall, GPUs are an attractive alternative to other imaging-dedicated computing hardware like application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) in terms of cost, simplicity and versatility. With the development of simpler language extensions and programming interfaces, GPUs are likely to become essential tools in medical imaging.

  8. Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

    PubMed Central

    Dondo Gazzano, Julio; Sanchez Molina, Francisco; Rincon, Fernando; López, Juan Carlos

    2015-01-01

    FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process. PMID:25874241

  9. A modular suite of hardware enabling spaceflight cell culture research

    NASA Technical Reports Server (NTRS)

    Hoehn, Alexander; Klaus, David M.; Stodieck, Louis S.

    2004-01-01

    BioServe Space Technologies, a NASA Research Partnership Center (RPC), has developed and operated various middeck payloads launched on 23 shuttle missions since 1991 in support of commercial space biotechnology projects. Modular cell culture systems are contained within the Commercial Generic Bioprocessing Apparatus (CGBA) suite of flight-qualified hardware, compatible with Space Shuttle, SPACEHAB, Spacelab and International Space Station (ISS) EXPRESS Rack interfaces. As part of the CGBA family, the Isothermal Containment Module (ICM) incubator provides thermal control, data acquisition and experiment manipulation capabilities, including accelerometer launch detection for automated activation and thermal profiling for culture incubation and sample preservation. The ICM can accommodate up to 8 individually controlled temperature zones. Command and telemetry capabilities allow real-time downlink of data and video permitting remote payload operation and ground control synchronization. Individual cell culture experiments can be accommodated in a variety of devices ranging from 'microgravity test tubes' or standard 100 mm Petri dishes, to complex, fed-batch bioreactors with automated culture feeding, waste removal and multiple sample draws. Up to 3 levels of containment can be achieved for chemical fixative addition, and passive gas exchange can be provided through hydrophobic membranes. Many additional options exist for designing customized hardware depending on specific science requirements.

  10. Health Maintenance System (HMS) Hardware Research, Design, and Collaboration

    NASA Technical Reports Server (NTRS)

    Gonzalez, Stefanie M.

    2010-01-01

    The Space Life Sciences division (SLSD) concentrates on optimizing a crew member's health. Developments are translated into innovative engineering solutions, research growth, and community awareness. This internship incorporates all those areas by targeting various projects. The main project focuses on integrating clinical and biomedical engineering principles to design, develop, and test new medical kits scheduled for launch in the Spring of 2011. Additionally, items will be tagged with Radio Frequency Interference Devices (RFID) to keep track of the inventory. The tags will then be tested to optimize Radio Frequency feed and feed placement. Research growth will occur with ground based experiments designed to measure calcium encrusted deposits in the International Space Station (ISS). The tests will assess the urine calcium levels with Portable Clinical Blood Analyzer (PCBA) technology. If effective then a model for urine calcium will be developed and expanded to microgravity environments. To support collaboration amongst the subdivisions of SLSD the architecture of the Crew Healthcare Systems (CHeCS) SharePoint site has been redesigned for maximum efficiency. Community collaboration has also been established with the University of Southern California, Dept. of Aeronautical Engineering and the Food and Drug Administration (FDA). Hardware disbursements will transpire within these communities to support planetary surface exploration and to serve as an educational tool demonstrating how ground based medicine influenced the technological development of space hardware.

  11. Hubble (HST) hardware is uncrated in the PHSF

    NASA Technical Reports Server (NTRS)

    1999-01-01

    In the Payload Hazardous Servicing Facility (PHSF), a crane lifts equipment for mission STS-103 out of its shipping container. The equipment is the first part of payload flight hardware for the third Hubble Space Telescope Servicing Mission (SM-3A). The hardware will undergo final testing and integration of payload elements in the PHSF. Mission STS-103 is a 'call-up' mission which is being planned due to the need to replace portions of the Hubble's pointing system, the gyros, which have begun to fail. Although Hubble is operating normally and conducting its scientific observations, only three of its six gyroscopes are working properly. The gyroscopes allow the telescope to point at stars, galaxies and planets. The STS-103 crew will not only replace gyroscopes, it will also replace a Fine Guidance Sensor and an older computer with a new enhanced model, an older data tape recorder with a solid state digital recorder, a failed spare transmitter with a new one, and degraded insulation on the telescope with new thermal insulation. The crew will also install a Battery Voltage/Temperature Improvement Kit to protect the spacecraft batteries from overcharging and overheating when the telescope goes into a safe mode. Launch of STS-103 is currently targeted for Oct. 14 but the date is under review.

  12. HSCT Sector Combustor Hardware Modifications for Improved Combustor Design

    NASA Technical Reports Server (NTRS)

    Greenfield, Stuart C.; Heberling, Paul V.; Moertle, George E.

    2005-01-01

    An alternative to the stepped-dome design for the lean premixed prevaporized (LPP) combustor has been developed. The new design uses the same premixer types as the stepped-dome design: integrated mixer flameholder (IMFH) tubes and a cyclone swirler pilot. The IMFH fuel system has been taken to a new level of development. Although the IMFH fuel system design developed in this Task is not intended to be engine-like hardware, it does have certain characteristics of engine hardware, including separate fuel circuits for each of the fuel stages. The four main stage fuel circuits are integrated into a single system which can be withdrawn from the combustor as a unit. Additionally, two new types of liner cooling have been designed. The resulting lean blowout data was found to correlate well with the Lefebvre parameter. As expected, CO and unburned hydrocarbons emissions were shown to have an approximately linear relationship, even though some scatter was present in the data, and the CO versus flame temperature data showed the typical cupped shape. Finally, the NOx emissions data was shown to agree well with a previously developed correlation based on emissions data from Configuration 3 tests performed at GEAE. The design variations of the cyclone swirler pilot that were investigated in this study did not significantly change the NOx emissions from the baseline design (GEAE Configuration 3) at supersonic cruise conditions.

  13. ESA hardware for plant research on the International Space Station

    NASA Astrophysics Data System (ADS)

    Brinckmann, E.

    The long awaited launch of the European Modular Cultivation System (EMCS) will provide a platform on which long-term and shorter experiments with plants will be performed on the International Space Station (ISS). EMCS is equipped with two centrifuge rotors (600 mm diameter), which can be used for in-flight 1 g controls and for studies with acceleration levels from 0.001 g to 2.0 g. Several experiments are in preparation investigating gravity relating to gene expression, gravisensing and phototropism of Arabidopsis thaliana and lentil roots. The experiment-specific hardware provides growth chambers for seedlings and whole A. thaliana plants and is connected to the EMCS Life Support System. Besides in-flight video observation, the experiments will be evaluated post-flight by means of fixed or frozen material. EMCS will have for the first time the possibility to fix samples on the rotating centrifuge, allowing a detailed analysis of the process of gravisensing. About two years after the EMCS launch, ESA's Biolab will be launched in the European "Columbus" Module. In a similar way as in EMCS, Biolab will accommodate experiments with plant seedlings and automatic fixation processes on the centrifuge. The hardware concepts for these experiments are presented in this communication.

  14. New Developments in Spaceflight Hardware for Plant Research

    NASA Astrophysics Data System (ADS)

    Brinckmann, E.

    The long awaited launch of the European Modular Cultivation System (EMCS) will provide a platform to perform long term and shorter experiments with plants on the International Space Station (ISS). EMCS is equipped with two centrifuge rotors (600 mm diameter), which can be used for flight 1xg controls and for studies with accelerations from 0.001xg to 2.0xg. Several experiments are in preparation, investigating gravity related gene expressions, gravisensing and phototropism of Arabidopsis thaliana, fern spores and lentil rots. The experiment specific hardware provides growth chambers for seedlings and whole A. thaliana plants, connected to the EMCS Life Support System. Besides video observation, the experiments will be evaluated on ground by means of fixed or frozen material. EMCS will have for the first time the possibility to fix samples on the rotating centrifuge, allowing a detailed analysis of the process of gravisensing. Two years after EMCS, ESA's BIOLAB will be launched in the European "Columbus" Module. In a similar way as in EMCS, BIOLAB accommodates experiments with plant seedlings and automatic fixation processes on the centrifuge. The hardware concepts for these experiments will be presented in this communication.

  15. Investigation of cleanliness verification techniques for rocket engine hardware

    NASA Technical Reports Server (NTRS)

    Fritzemeier, Marilyn L.; Skowronski, Raymund P.

    1995-01-01

    Oxidizer propellant systems for liquid-fueled rocket engines must meet stringent cleanliness requirements for particulate and nonvolatile residue. These requirements were established to limit residual contaminants which could block small orifices or ignite in the oxidizer system during engine operation. Limiting organic residues in high pressure oxygen systems is particularly important. The current method of cleanliness verification used by Rocketdyne requires an organic solvent flush of the critical hardware surfaces. The solvent is filtered and analyzed for particulate matter, followed by gravimetric determination of the nonvolatile residue (NVR) content of the filtered solvent. The organic solvents currently specified for use (1,1,1-trichloroethane and CFC-113) are ozone-depleting chemicals slated for elimination by December 1995. A test program is in progress to evaluate alternative methods for cleanliness verification that do not require the use of ozone-depleting chemicals and that minimize or eliminate the use of solvents regulated as hazardous air pollutants or smog precursors. Initial results from the laboratory test program to evaluate aqueous-based methods and organic solvent flush methods for NVR verification are provided and compared with results obtained using the current method. Evaluation of the alternative methods was conducted using a range of contaminants encountered in the manufacture of rocket engine hardware.

  16. Spinal fusion-hardware construct: Basic concepts and imaging review

    PubMed Central

    Nouh, Mohamed Ragab

    2012-01-01

    The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging. PMID:22761979

  17. Space hardware compatibility tests with hydrogen peroxide gas plasma sterilization

    NASA Astrophysics Data System (ADS)

    Faye, Delphine; Aguila, Alexandre; Debus, Andre; Remaury, Stephanie; Nabarra, Pascale; Darbord, Jacques C.; Soufflet, Caroline; Destrez, Philippe; Coll, Patrice; Coscia, David

    The exploration of the Solar System shall comply with planetary protection requirements handled presently by the Committee of Space Research (COSPAR). The goal of planetary protection is to protect celestial bodies from terrestrial contamination and also to protect the Earth environment from an eventual contamination carried by return samples or by space systems. For project teams, avoiding the biological contamination of other Solar System bodies such as Mars imposes to perform unusual tasks at technical and operational constraints point of view. The main are the reduction of bioburden on space hardware, the sterile integration of landers, the control of the biological cleanliness and the limitation of crash probability. In order to reduce the bioburden on spacecraft, the use of qualified sterilization processes may be envisaged. Since 1992 now, with the Mars96 mission, one of the most often used is the Sterrad(R) process working with hydrogen peroxide gas plasma. In the view of future Mars exploration programs, after tests performed in the frame of previous missions, a new test campaign has been performed on thermal coatings and miscellaneous materials coming from an experiment in order to assess the compatibility of space hardware and material with this sterilization process.

  18. The use of inexact hardware to mimic subgrid-scale variability

    NASA Astrophysics Data System (ADS)

    Düben, Peter D.; Palmer, Tim

    2014-05-01

    We study the use of inexact hardware in numerical weather and climate models. The different setups of inexact hardware promise large savings in power consumption and an increase in computational performance. However, simulations with inexact hardware show numerical errors, such as rounding errors or bit flips. The effect of these errors can be described as an additional forcing term which is added to the governing differential equations. Since hardware errors are hardly correlated in space and time, the forcing term due to inexact hardware has some similarities to a stochastic forcing. Stochastic forcings, however, are used successfully in stochastic parametrisation schemes to mimic subgrid-scale variability within a numerical model and are motivated by physical reasons. We investigate a model of the 1D Burgers equation that is using the stochastic parametrisation scheme of Dolaptchiev et al. based on the MTV stochastic mode reduction strategy. We emulate the use of inexact hardware within the model. The forcing of the stochastic parametrisation scheme is compared to the forcing caused by hardware errors. We show that the forcing of inexact hardware can replace the stochastic forcing of the stochastic parametrisation scheme and lead to a similar quality of solutions, when only small changes are made within the numerical code. We conclude that numerical errors of inexact hardware can be beneficial for physical reasons, at least in idealised setups, while inexact hardware will provide significant savings in computational cost. We will also present results on the use of inexact hardware to setup ensemble simulations.

  19. Ultra-low noise miniaturized neural amplifier with hardware averaging

    NASA Astrophysics Data System (ADS)

    Dweiri, Yazan M.; Eggers, Thomas; McCallum, Grant; Durand, Dominique M.

    2015-08-01

    Objective. Peripheral nerves carry neural signals that could be used to control hybrid bionic systems. Cuff electrodes provide a robust and stable interface but the recorded signal amplitude is small (<3 μVrms 700 Hz-7 kHz), thereby requiring a baseline noise of less than 1 μVrms for a useful signal-to-noise ratio (SNR). Flat interface nerve electrode (FINE) contacts alone generate thermal noise of at least 0.5 μVrms therefore the amplifier should add as little noise as possible. Since mainstream neural amplifiers have a baseline noise of 2 μVrms or higher, novel designs are required. Approach. Here we apply the concept of hardware averaging to nerve recordings obtained with cuff electrodes. An optimization procedure is developed to minimize noise and power simultaneously. The novel design was based on existing neural amplifiers (Intan Technologies, LLC) and is validated with signals obtained from the FINE in chronic dog experiments. Main results. We showed that hardware averaging leads to a reduction in the total recording noise by a factor of 1/√N or less depending on the source resistance. Chronic recording of physiological activity with FINE using the presented design showed significant improvement on the recorded baseline noise with at least two parallel operation transconductance amplifiers leading to a 46.1% reduction at N = 8. The functionality of these recordings was quantified by the SNR improvement and shown to be significant for N = 3 or more. The present design was shown to be capable of generating <1.5 μVrms total recording baseline noise when connected to a FINE placed on the sciatic nerve of an awake animal. An algorithm was introduced to find the value of N that can minimize both the power consumption and the noise in order to design a miniaturized ultralow-noise neural amplifier. Significance. These results demonstrate the efficacy of hardware averaging on noise improvement for neural recording with cuff electrodes, and can accommodate the

  20. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    PubMed Central

    2009-01-01

    Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR) is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs) have more memory bandwidth and computational capability than Central Processing Units (CPUs) and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective performance while leaving the CPU

  1. Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

    PubMed Central

    Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

    2011-01-01

    Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

  2. A CLIPS based personal computer hardware diagnostic system

    NASA Technical Reports Server (NTRS)

    Whitson, George M.

    1991-01-01

    Often the person designated to repair personal computers has little or no knowledge of how to repair a computer. Described here is a simple expert system to aid these inexperienced repair people. The first component of the system leads the repair person through a number of simple system checks such as making sure that all cables are tight and that the dip switches are set correctly. The second component of the system assists the repair person in evaluating error codes generated by the computer. The final component of the system applies a large knowledge base to attempt to identify the component of the personal computer that is malfunctioning. We have implemented and tested our design with a full system to diagnose problems for an IBM compatible system based on the 8088 chip. In our tests, the inexperienced repair people found the system very useful in diagnosing hardware problems.

  3. Hardware Testing for the Optical PAyload for Lasercomm Science (OPALS)

    NASA Technical Reports Server (NTRS)

    Slagle, Amanda

    2011-01-01

    Hardware for several subsystems of the proposed Optical PAyload for Lasercomm Science (OPALS), including the gimbal and avionics, was tested. Microswitches installed on the gimbal were evaluated to verify that their point of actuation would remain within the acceptable range even if the switches themselves move slightly during launch. An inspection of the power board was conducted to ensure that all power and ground signals were isolated, that polarized components were correctly oriented, and that all components were intact and securely soldered. Initial testing on the power board revealed several minor problems, but once they were fixed the power board was shown to function correctly. All tests and inspections were documented for future use in verifying launch requirements.

  4. Hardware accelerator design for tracking in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

  5. Acquisition of reliable vacuum hardware for large accelerator systems

    SciTech Connect

    Welch, K.M.

    1995-09-06

    Credible and effective communications prove to be the major challenge in the acquisition of reliable vacuum hardware. Technical competence is necessary but not sufficient. The authors must effectively communicate with management, sponsoring agencies, project organizations, service groups, staff and with vendors. Most of Deming`s 14 quality assurance tenants relate to creating an enlightened environment of good communications. All projects progress along six distinct, closely coupled, dynamic phases. All six phases are in a state of perpetual change. These phases and their elements are discussed, with emphasis given to the acquisition phase and its related vocabulary. Large projects require great clarity and rigor as poor communications can be costly. For rigor to be cost effective, it can`t be pedantic. Clarity thrives best in a low-risk, team environment.

  6. [A hybrid volume rendering method using general hardware].

    PubMed

    Li, Bin; Tian, Lianfang; Chen, Ping; Mao, Zongyuan

    2008-06-01

    In order to improve the effect and efficiency of the reconstructed image after hybrid volume rendering of different kinds of volume data from medical sequential slices or polygonal models, we propose a hybrid volume rendering method based on Shear-Warp with economical hardware. First, the hybrid volume data are pre-processed by Z-Buffer method and RLE (Run-Length Encoded) data structure. Then, during the process of compositing intermediate image, a resampling method based on the dual-interpolation and the intermediate slice interpolation methods is used to improve the efficiency and the effect. Finally, the reconstructed image is rendered by the texture-mapping technology of OpenGL. Experiments demonstrate the good performance of the proposed method.

  7. Veggie Hardware Validation Test Preliminary Results and Lessons Learned

    NASA Technical Reports Server (NTRS)

    Massa, Gioia D.; Dufour, Nicole F.; Smith, T. M.

    2014-01-01

    The Veggie hardware validation test, VEG-01, was conducted on the International Space Station during Expeditions 39 and 40 from May through June of 2014. The Veggie hardware and the VEG-01 experiment payload were launched to station aboard the SpaceX-3 resupply mission in April, 2014. Veggie was installed in an Expedite-the-Processing-of-Experiments-to-Space-Station (ExPRESS) rack in the Columbus module, and the VEG-01 validation test was initiated. Veggie installation was successful, and power was supplied to the unit. The hardware was programmed and the root mat reservoir and plant pillows were installed without issue. As expected, a small amount of growth media was observed in the sealed bags which enclosed the plant pillows when they were destowed. Astronaut Steve Swanson used the wet/dry vacuum to clean up the escaped particles. Water insertion or priming the first plant pillow was unsuccessful as an issue prevented water movement through the quick disconnect. All subsequent pillows were successfully primed, and the initial pillow was replaced with a backup pillow and successfully primed. Six pillows were primed, but only five pillows had plants which germinated. After about a week and a half it was observed that plants were not growing well and that pillow wicks were dry. This indicated that the reservoir was not supplying sufficient water to the pillows via wicking, and so the team reverted to an operational fix which added water directly to the plant pillows. Direct watering of the pillows led to a recovery in several of the stressed plants; a couple of which did not recover. An important lesson learned involved Veggie's bellows. The bellows tended to float and interfere with operations when opened, so Steve secured them to the baseplate during plant tending operations. Due to the perceived intensity of the LED lights, the crew found it challenging to both work under the lights and read crew procedures on their computer. Although the lights are not a safety

  8. Hardware accelerator design for change detection in smart camera

    NASA Astrophysics Data System (ADS)

    Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Chaudhury, Santanu; Vohra, Anil

    2011-10-01

    Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

  9. Motion and force controlled vibration testing. [of aerospace hardware

    NASA Technical Reports Server (NTRS)

    Scharton, Terry D.; Boatman, David J.; Kern, Dennis L.

    1990-01-01

    A technique for controlling both the input acceleration and force in vibration tests is proposed to alleviate the overtesting risks and the problems associated with response limiting in conventional vibration tests of aerospace hardware. Previous research on impedance and force controlled vibration tests is reviewed and a simple equation governing the dual control of acceleration and force is derived. A practical method for implementing the dual control technique in random vibration tests has been demonstrated in JPL's environmental test facility using a conventional digital controller operating in the extremal mode. The dual control technique provides appropriate real-time notching of the input acceleration and a corresponding reduction of the test item response at resonances. Issues concerning the need for force and acceleration phase information, the adequacy of specifying the blocked force, and the derivation of the total force for multipoint supports are discussed.

  10. Hardware for a real-time multiprocessor simulator

    NASA Technical Reports Server (NTRS)

    Blech, R. A.; Arpasi, D. J.

    1984-01-01

    The hardware for a real time multiprocessor simulator (RTMPS) developed at the NASA Lewis Research Center is described. The RTMPS is a multiple microprocessor system used to investigate the application of parallel processing concepts to real time simulation. It is designed to provide flexible data exchange paths between processors by using off the shelf microcomputer boards and minimal customized interfacing. A dedicated operator interface allows easy setup of the simulator and quick interpreting of simulation data. Simulations for the RTMPS are coded in a NASA designed real time multiprocessor language (RTMPL). This language is high level and geared to the multiprocessor environment. A real time multiprocessor operating system (RTMPOS) has also been developed that provides a user friendly operator interface. The RTMPS and supporting software are currently operational and are being evaluated at Lewis. The results of this evaluation will be used to specify the design of an optimized parallel processing system for real time simulation of dynamic systems.

  11. Magnetic Gimbal Proof-of-Concept Hardware performance results

    NASA Astrophysics Data System (ADS)

    Stuart, Keith O.

    The Magnetic Gimbal Proof-of-Concept Hardware activities, accomplishments, and test results are discussed. The Magnetic Gimbal Fabrication and Test (MGFT) program addressed the feasibility of using a magnetic gimbal to isolate an Electro-Optical (EO) sensor from the severe angular vibrations induced during the firing of divert and attitude control system (ACS) thrusters during space flight. The MGFT effort was performed in parallel with the fabrication and testing of a mechanically gimballed, flex pivot based isolation system by the Hughes Aircraft Missile Systems Group. Both servo systems supported identical EO sensor assembly mockups to facilitate direct comparison of performance. The results obtained from the MGFT effort indicate that the magnetic gimbal exhibits the ability to provide significant performance advantages over alternative mechanically gimballed techniques.

  12. Variable length data formats. [in hardware-software engineering

    NASA Technical Reports Server (NTRS)

    Brakefield, J. C.; Quinn, M. J.

    1978-01-01

    The purpose of this paper is to discuss a number of variable length floating point and integer formats and to give the various advantages and disadvantages of their use. Often it is known in advance that a given integer will not exceed a certain magnitude or that a particular floating point number is accurate to only 'n' places of accuracy. Faced with this, it is good engineering to choose variable length floating point and integer formats which require the least amount of hardware or the minimum amount of software or which have some other dominant advantage. The formats discussed have the advantage that length change algorithms are invariant with respect to data types (unsigned, signed, floating point, integers, and complex numbers). The STARAN associative array processor, which uses a completely variable fixed point and floating point formats, is described.

  13. Multimode guidance project low frequency ECM simulator: Hardware description

    NASA Astrophysics Data System (ADS)

    Kaye, H. M.

    1982-10-01

    The Multimode Guidance(MMG) Project, part of the Army/Navy Area Defense SAM Technology Prototyping Program, was established to conduct a feasibility demonstration of multimode guidance concepts. Prototype guidance units for advanced, long range missiles are being built and tested under MMG Project sponsorship. The Johns Hopkins University Applied Physics Laboratory has been designated as Government Agent for countermeasures for this project. In support of this effort, a family of computer-controlled ECM simulators is being developed for validation of contractor's multimode guidance prototype designs. The design of the Low Frequency ECM Simulator is documented in two volumes. This report, Volume A, describes the hardware design of the simulator; Volume B describes the software design. This computer-controlled simulator can simulate up to six surveillance frequency jammers in B through F bands and will be used to evaluate the performance of home-on-jamming guidance modes in multiple jammer environments.

  14. Advanced protein crystal growth flight hardware for the Space Station

    NASA Technical Reports Server (NTRS)

    Herrmann, Frederick T.

    1988-01-01

    The operational environment of the Space Station will differ considerably from the previous short term missions such as the Spacelabs. Limited crew availability combined with the near continuous operation of Space Station facilities will require a high degree of facility automation. This paper will discuss current efforts to develop automated flight hardware for advanced protein crystal growth on the Space Station. Particular areas discussed will be the automated monitoring of key growth parameters for vapor diffusion growth and proposed mechanisms for control of these parameters. A history of protein crystal growth efforts will be presented in addition to the rationale and need for improved protein crystals for X-ray diffraction. The facility will be capable of simultaneously processing several hundred protein samples at various temperatures, pH's, concentrations etc., and provide allowances for real time variance of growth parameters.

  15. Hardware assist for IPv6 routing table lookup

    NASA Astrophysics Data System (ADS)

    Harbaum, T.; Meier, D.; Zitterbart, Martina; Broekelmann, D.

    1998-09-01

    Routers are key building blocks in networks. They need to cope with high data rates in the range of multiple gigabit per second that are flowing through them. Therefore, specifically performance critical functions should be implemented in dedicated hardware units in order to speed up the forwarding task. These units can be embedded within regular workstations or into dedicated router architectures. This paper we address one of the most performance critical components of a router, the routing table and its access and search mechanisms. Earlier work has shown that this is more critical with respect to the resulting performance than IP processing itself. A simple but efficient organization of the routing table using binary trees and off-the-shelf SRAMs is presented together with a suited search algorithm.

  16. Hardware-Efficient Bilateral Filtering for Stereo Matching.

    PubMed

    Yang, Qingxiong

    2014-05-01

    This paper presents a new bilateral filtering method specially designed for practical stereo vision systems. Parallel algorithms are preferred in these systems due to the real-time performance requirement. Edge-preserving filters like the bilateral filter have been demonstrated to be very effective for high-quality local stereo matching. A hardware-efficient bilateral filter is thus proposed in this paper. When moved to an NVIDIA GeForce GTX 580 GPU, it can process a one megapixel color image at around 417 frames per second. This filter can be directly used for cost aggregation required in any local stereo matching algorithm. Quantitative evaluation shows that it outperforms all the other local stereo methods both in terms of accuracy and speed on Middlebury benchmark. It ranks 12th out of over 120 methods on Middlebury data sets, and the average runtime (including the matching cost computation, occlusion handling, and post processing) is only 15 milliseconds (67 frames per second).

  17. Calibration Hardware for the Muon Detectors at CDF

    NASA Astrophysics Data System (ADS)

    Vickey, Trevor

    2001-04-01

    The muon detector system at CDF consists of the following subsystems: Central Muon Detector (CMU), the Central Muon Upgrade (CMP), the Central Muon Extension (CMX), and the Intermediate Muon Detector (IMU). Each subsystem is a collection of drift chambers and all but the CMU also incorporate scintillation counters for trigger and timing purposes. We will describe the muon calibration system hardware, which performs diagnostics and calibrations on the above detectors. The muon calibration system injects charge into each channel of the CDF muon detectors to generate a signal similar to that of a muon traversing the chamber. Reading this pulse out with the data acquisition system allows us to spot problems with the muon system electronics as well as to calibrate detector timing and response to different amounts of charge.

  18. Plasma arc welding repair of space flight hardware

    NASA Technical Reports Server (NTRS)

    Hoffman, David S.

    1993-01-01

    Repair and refurbishment of flight and test hardware can extend the useful life of very expensive components. A technique to weld repair the main combustion chamber of space shuttle main engines has been developed. The technique uses the plasma arc welding process and active cooling to seal cracks and pinholes in the hot-gas wall of the main combustion chamber liner. The liner hot-gas wall is made of NARloyZ, a copper alloy previously thought to be unweldable using conventional arc welding processes. The process must provide extensive heat input to melt the high conductivity NARloyZ while protecting the delicate structure of the surrounding material. The higher energy density of the plasma arc process provides the necessary heat input while active water cooling protects the surrounding structure. The welding process is precisely controlled using a computerized robotic welding system.

  19. An open-hardware platform for optogenetics and photobiology

    PubMed Central

    Gerhardt, Karl P.; Olson, Evan J.; Castillo-Hair, Sebastian M.; Hartsough, Lucas A.; Landry, Brian P.; Ekness, Felix; Yokoo, Rayka; Gomez, Eric J.; Ramakrishnan, Prabha; Suh, Junghae; Savage, David F.; Tabor, Jeffrey J.

    2016-01-01

    In optogenetics, researchers use light and genetically encoded photoreceptors to control biological processes with unmatched precision. However, outside of neuroscience, the impact of optogenetics has been limited by a lack of user-friendly, flexible, accessible hardware. Here, we engineer the Light Plate Apparatus (LPA), a device that can deliver two independent 310 to 1550 nm light signals to each well of a 24-well plate with intensity control over three orders of magnitude and millisecond resolution. Signals are programmed using an intuitive web tool named Iris. All components can be purchased for under $400 and the device can be assembled and calibrated by a non-expert in one day. We use the LPA to precisely control gene expression from blue, green, and red light responsive optogenetic tools in bacteria, yeast, and mammalian cells and simplify the entrainment of cyanobacterial circadian rhythm. The LPA dramatically reduces the entry barrier to optogenetics and photobiology experiments. PMID:27805047

  20. Using EPICS enabled industrial hardware for upgrading control systems

    SciTech Connect

    Bjorkland, Eric A; Veeramani, Arun; Debelle, Thierry

    2009-01-01

    Los Alamos National Laboratory has been working with National Instruments (NI) and Cosy lab to implement EPICS Input Output Controller (IOC) software that runs directly on NI CompactRIO Real Time Controller (RTC) and communicates with NI LabVIEW through a shared memory interface. In this presentation, we will discuss our current progress in upgrading the control system at the Los Alamos Neutron Science Centre (LANSCE) and what we have learned about integrating CompactRIO into large experimental physics facilities. We will also discuss the implications of using Channel Access Server for LabVIEW which will enable more commercial hardware platforms to be used in upgrading existing facilities or in commissioning new ones.

  1. Hardware Implementation of Maximum Power Point Tracking for Thermoelectric Generators

    NASA Astrophysics Data System (ADS)

    Maganga, Othman; Phillip, Navneesh; Burnham, Keith J.; Montecucco, Andrea; Siviter, Jonathan; Knox, Andrew; Simpson, Kevin

    2014-06-01

    This work describes the practical implementation of two maximum power point tracking (MPPT) algorithms, namely those of perturb and observe, and extremum seeking control. The proprietary dSPACE system is used to perform hardware in the loop (HIL) simulation whereby the two control algorithms are implemented using the MATLAB/Simulink (Mathworks, Natick, MA) software environment in order to control a synchronous buck-boost converter connected to two commercial thermoelectric modules. The process of performing HIL simulation using dSPACE is discussed, and a comparison between experimental and simulated results is highlighted. The experimental results demonstrate the validity of the two MPPT algorithms, and in conclusion the benefits and limitations of real-time implementation of MPPT controllers using dSPACE are discussed.

  2. Hardware authentication using transmission spectra modified optical fiber.

    SciTech Connect

    Grubbs, Robert K.; Romero, Juan A.

    2010-09-01

    The ability to authenticate the source and integrity of data is critical to the monitoring and inspection of special nuclear materials, including hardware related to weapons production. Current methods rely on electronic encryption/authentication codes housed in monitoring devices. This always invites the question of implementation and protection of authentication information in an electronic component necessitating EMI shielding, possibly an on board power source to maintain the information in memory. By using atomic layer deposition techniques (ALD) on photonic band gap (PBG) optical fibers we will explore the potential to randomly manipulate the output spectrum and intensity of an input light source. This randomization could produce unique signatures authenticating devices with the potential to authenticate data. An external light source projected through the fiber with a spectrometer at the exit would 'read' the unique signature. No internal power or computational resources would be required.

  3. Modular implementation of a digital hardware design automation system

    NASA Astrophysics Data System (ADS)

    Masud, M.

    An automation system based on AHPL (A Hardware Programming Language) was developed. The project may be divided into three distinct phases: (1) Upgrading of AHPL to make it more universally applicable; (2) Implementation of a compiler for the language; and (3) illustration of how the compiler may be used to support several phases of design activities. Several new features were added to AHPL. These include: application-dependent parameters, mutliple clocks, asynchronous results, functional registers and primitive functions. The new language, called Universal AHPL, has been defined rigorously. The compiler design is modular. The parsing is done by an automatic parser generated from the SLR(1)BNF grammar of the language. The compiler produces two data bases from the AHPL description of a circuit. The first one is a tabular representation of the circuit, and the second one is a detailed interconnection linked list. The two data bases provide a means to interface the compiler to application-dependent CAD systems.

  4. Research on starlight hardware-in-the-loop simulator

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Gao, Yang; Qu, Huiyang; Liu, Dongfang; Du, Huijie; Lei, Jie

    2016-10-01

    The starlight navigation is considered to be one of the most important methods for spacecraft navigation. Starlight simulation system is a high-precision system with large fields of view, designed to test the starlight navigation sensor performance on the ground. A complete hardware-in-the-loop simulation of the system has been built. The starlight simulator is made up of light source, light source controller, light filter, LCD, collimator and control computer. LCD is the key display component of the system, and is installed at the focal point of the collimator. For the LCD cannot emit light itself, so light source and light source power controller is specially designed for the brightness demanded by the LCD. Light filter is designed for the dark background which is also needed in the simulation.

  5. Fault Tolerant Characteristics of Artificial Neural Network Electronic Hardware

    NASA Technical Reports Server (NTRS)

    Zee, Frank

    1995-01-01

    The fault tolerant characteristics of analog-VLSI artificial neural network (with 32 neurons and 532 synapses) chips are studied by exposing them to high energy electrons, high energy protons, and gamma ionizing radiations under biased and unbiased conditions. The biased chips became nonfunctional after receiving a cumulative dose of less than 20 krads, while the unbiased chips only started to show degradation with a cumulative dose of over 100 krads. As the total radiation dose increased, all the components demonstrated graceful degradation. The analog sigmoidal function of the neuron became steeper (increase in gain), current leakage from the synapses progressively shifted the sigmoidal curve, and the digital memory of the synapses and the memory addressing circuits began to gradually fail. From these radiation experiments, we can learn how to modify certain designs of the neural network electronic hardware without using radiation-hardening techniques to increase its reliability and fault tolerance.

  6. Tuple spaces in hardware for accelerated implicit routing

    SciTech Connect

    Baker, Zachary Kent; Tripp, Justin

    2010-12-01

    Organizing and optimizing data objects on networks with support for data migration and failing nodes is a complicated problem to handle as systems grow. The goal of this work is to demonstrate that high levels of speedup can be achieved by moving responsibility for finding, fetching, and staging data into an FPGA-based network card. We present a system for implicit routing of data via FPGA-based network cards. In this system, data structures are requested by name, and the network of FPGAs finds the data within the network and relays the structure to the requester. This is acheived through successive examination of hardware hash tables implemented in the FPGA. By avoiding software stacks between nodes, the data is quickly fetched entirely through FPGA-FPGA interaction. The performance of this system is orders of magnitude faster than software implementations due to the improved speed of the hash tables and lowered latency between the network nodes.

  7. Hierarchical Simulation to Assess Hardware and Software Dependability

    NASA Technical Reports Server (NTRS)

    Ries, Gregory Lawrence

    1997-01-01

    This thesis presents a method for conducting hierarchical simulations to assess system hardware and software dependability. The method is intended to model embedded microprocessor systems. A key contribution of the thesis is the idea of using fault dictionaries to propagate fault effects upward from the level of abstraction where a fault model is assumed to the system level where the ultimate impact of the fault is observed. A second important contribution is the analysis of the software behavior under faults as well as the hardware behavior. The simulation method is demonstrated and validated in four case studies analyzing Myrinet, a commercial, high-speed networking system. One key result from the case studies shows that the simulation method predicts the same fault impact 87.5% of the time as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. Of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulations was therefore reduced from 500 to 145. Finally, the case studies show how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injections into the real system.

  8. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry.

    PubMed

    Wang, Xin; Yang, James N; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-07

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm(2). The results showed that the rod increased the dose to water by ∼6% at the water-rod interface because of electron backscattering and decreased the dose by ∼7% in the shadow of the rod because of photon attenuation. The Pinnacle(3) treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm(-3) was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm(-3) (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm(-3) to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  9. Software and hardware infrastructure for research in electrophysiology

    PubMed Central

    Mouček, Roman; Ježek, Petr; Vařeka, Lukáš; Řondík, Tomáš; Brůha, Petr; Papež, Václav; Mautner, Pavel; Novotný, Jiří; Prokop, Tomáš; Štěbeták, Jan

    2014-01-01

    As in other areas of experimental science, operation of electrophysiological laboratory, design and performance of electrophysiological experiments, collection, storage and sharing of experimental data and metadata, analysis and interpretation of these data, and publication of results are time consuming activities. If these activities are well organized and supported by a suitable infrastructure, work efficiency of researchers increases significantly. This article deals with the main concepts, design, and development of software and hardware infrastructure for research in electrophysiology. The described infrastructure has been primarily developed for the needs of neuroinformatics laboratory at the University of West Bohemia, the Czech Republic. However, from the beginning it has been also designed and developed to be open and applicable in laboratories that do similar research. After introducing the laboratory and the whole architectural concept the individual parts of the infrastructure are described. The central element of the software infrastructure is a web-based portal that enables community researchers to store, share, download and search data and metadata from electrophysiological experiments. The data model, domain ontology and usage of semantic web languages and technologies are described. Current data publication policy used in the portal is briefly introduced. The registration of the portal within Neuroscience Information Framework is described. Then the methods used for processing of electrophysiological signals are presented. The specific modifications of these methods introduced by laboratory researches are summarized; the methods are organized into a laboratory workflow. Other parts of the software infrastructure include mobile and offline solutions for data/metadata storing and a hardware stimulator communicating with an EEG amplifier and recording software. PMID:24639646

  10. Cascade Error Projection: A Learning Algorithm for Hardware Implementation

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A.; Daud, Taher

    1996-01-01

    In this paper, we workout a detailed mathematical analysis for a new learning algorithm termed Cascade Error Projection (CEP) and a general learning frame work. This frame work can be used to obtain the cascade correlation learning algorithm by choosing a particular set of parameters. Furthermore, CEP learning algorithm is operated only on one layer, whereas the other set of weights can be calculated deterministically. In association with the dynamical stepsize change concept to convert the weight update from infinite space into a finite space, the relation between the current stepsize and the previous energy level is also given and the estimation procedure for optimal stepsize is used for validation of our proposed technique. The weight values of zero are used for starting the learning for every layer, and a single hidden unit is applied instead of using a pool of candidate hidden units similar to cascade correlation scheme. Therefore, simplicity in hardware implementation is also obtained. Furthermore, this analysis allows us to select from other methods (such as the conjugate gradient descent or the Newton's second order) one of which will be a good candidate for the learning technique. The choice of learning technique depends on the constraints of the problem (e.g., speed, performance, and hardware implementation); one technique may be more suitable than others. Moreover, for a discrete weight space, the theoretical analysis presents the capability of learning with limited weight quantization. Finally, 5- to 8-bit parity and chaotic time series prediction problems are investigated; the simulation results demonstrate that 4-bit or more weight quantization is sufficient for learning neural network using CEP. In addition, it is demonstrated that this technique is able to compensate for less bit weight resolution by incorporating additional hidden units. However, generation result may suffer somewhat with lower bit weight quantization.

  11. Loads and Structural Dynamics Requirements for Spaceflight Hardware

    NASA Technical Reports Server (NTRS)

    Schultz, Kenneth P.

    2011-01-01

    The purpose of this document is to establish requirements relating to the loads and structural dynamics technical discipline for NASA and commercial spaceflight launch vehicle and spacecraft hardware. Requirements are defined for the development of structural design loads and recommendations regarding methodologies and practices for the conduct of load analyses are provided. As such, this document represents an implementation of NASA STD-5002. Requirements are also defined for structural mathematical model development and verification to ensure sufficient accuracy of predicted responses. Finally, requirements for model/data delivery and exchange are specified to facilitate interactions between Launch Vehicle Providers (LVPs), Spacecraft Providers (SCPs), and the NASA Technical Authority (TA) providing insight/oversight and serving in the Independent Verification and Validation role. In addition to the analysis-related requirements described above, a set of requirements are established concerning coupling phenomena or other interaction between structural dynamics and aerodynamic environments or control or propulsion system elements. Such requirements may reasonably be considered structure or control system design criteria, since good engineering practice dictates consideration of and/or elimination of the identified conditions in the development of those subsystems. The requirements are included here, however, to ensure that such considerations are captured in the design space for launch vehicles (LV), spacecraft (SC) and the Launch Abort Vehicle (LAV). The requirements in this document are focused on analyses to be performed to develop data needed to support structural verification. As described in JSC 65828, Structural Design Requirements and Factors of Safety for Spaceflight Hardware, implementation of the structural verification requirements is expected to be described in a Structural Verification Plan (SVP), which should describe the verification of each

  12. A novel hardware-friendly algorithm for hyperspectral linear unmixing

    NASA Astrophysics Data System (ADS)

    Guerra, Raúl; Santos, Lucana; López, Sebastián.; Sarmiento, Roberto

    2015-10-01

    Linear unmixing of hyperspectral images has rapidly become one of the most widely utilized tools for analyzing the content of hyperspectral images captured by state-of-the-art remote hyperspectral sensors. The aforementioned unmixing process consists of the following three sequential steps: dimensionality estimation, endmember extraction and abundances computation. Within this procedure, the first two steps are by far the most demanding from a computational point of view, since they involve a large amount of matrix operations. Moreover, the complex nature of these operations seriously difficult the hardware implementation of these two unmixing steps, leading to non-optimized implementations which are not able to satisfy the strict delay requirements imposed by those applications under real-time or near real-time requirements. This paper uncovers a new algorithm which is capable of estimating the number of endmembers and extracting them from a given hyperspectral image with at least the same accuracy than state-of-the-art approaches while demanding a much lower computational effort, with independence of the characteristics of the image under analysis. In particular, the proposed algorithm is based on the concept of orthogonal projections and allows performing the estimation of the number of end- members and their extraction simultaneously, using simple operations, which can be also easily parallelized. In this sense, it is worth to mention that our algorithm does not perform complex matrix operations, such as the inverse of a matrix or the extraction of eigenvalues and eigenvectors, which makes easier its ulterior hardware. The experimental results obtained with synthetic and real hyperspectral images demonstrate that the accuracy obtained with the proposed algorithm when estimating the number of endmembers and extracting them is similar or better than the one provided by well-known state-of-the-art algorithms, while the complexity of the overall process is

  13. Hardware reconfiguration for fault-tolerant processor arrays

    SciTech Connect

    Chean, M.

    1989-01-01

    In large VLSI/WSI arrays, improved reliability and yield can be obtained through reconfiguration techniques. In fault tolerance design, redundancy is used to offset faults when they occur in the arrays. Since redundant components are themselves susceptible to faults, their number must be a minimum. This also implies that an efficient reconfiguration scheme is preferred, i.e., one that can use as many spare components as possible so that unnecessary waste of spares is reduced. In this thesis, hardware reconfiguration for fault-tolerant processor arrays is discussed. First, a taxonomy for reconfiguration techniques is introduced, and several schemes are surveyed and classified. This taxonomy can be used to introduce, explain, compare, study, and classify new reconfiguration schemes. Next, an extension to reconfiguration technique is presented. Two special cases of the scheme are simulated and their results compared and studied. Finally, a new approach to hardware reconfiguration, called FUSS (Full Use of Suitable Spares), is proposed for VLSI/WSI fault-tolerant processor arrays. FUSS uses an indicator vector, the surplus vector, to guide the replacement of faulty processors within an array. Analytical study of the general FUSS algorithm shows that a linear relationship between the array size and the area of interconnect is required for the reconfiguration to be 100% successful. In an instance of FUSS, called simple FUSS, reconfiguration is done by simply shifting up or down faulty processors along their corresponding columns according to the surplus vector's entries. The surplus vector is progressively updated after each column is reconfigured. The reconfiguration is successful when the surplus vector becomes the null vector. Simulations show that when the number of faulty processors is equal to that of spare processors, simple FUSS can achieve a probability of survival as high as 99%

  14. 2D to 3D conversion implemented in different hardware

    NASA Astrophysics Data System (ADS)

    Ramos-Diaz, Eduardo; Gonzalez-Huitron, Victor; Ponomaryov, Volodymyr I.; Hernandez-Fragoso, Araceli

    2015-02-01

    Conversion of available 2D data for release in 3D content is a hot topic for providers and for success of the 3D applications, in general. It naturally completely relies on virtual view synthesis of a second view given by original 2D video. Disparity map (DM) estimation is a central task in 3D generation but still follows a very difficult problem for rendering novel images precisely. There exist different approaches in DM reconstruction, among them manually and semiautomatic methods that can produce high quality DMs but they demonstrate hard time consuming and are computationally expensive. In this paper, several hardware implementations of designed frameworks for an automatic 3D color video generation based on 2D real video sequence are proposed. The novel framework includes simultaneous processing of stereo pairs using the following blocks: CIE L*a*b* color space conversions, stereo matching via pyramidal scheme, color segmentation by k-means on an a*b* color plane, and adaptive post-filtering, DM estimation using stereo matching between left and right images (or neighboring frames in a video), adaptive post-filtering, and finally, the anaglyph 3D scene generation. Novel technique has been implemented on DSP TMS320DM648, Matlab's Simulink module over a PC with Windows 7, and using graphic card (NVIDIA Quadro K2000) demonstrating that the proposed approach can be applied in real-time processing mode. The time values needed, mean Similarity Structural Index Measure (SSIM) and Bad Matching Pixels (B) values for different hardware implementations (GPU, Single CPU, and DSP) are exposed in this paper.

  15. Establishing a Novel Modeling Tool: A Python-Based Interface for a Neuromorphic Hardware System

    PubMed Central

    Brüderle, Daniel; Müller, Eric; Davison, Andrew; Muller, Eilif; Schemmel, Johannes; Meier, Karlheinz

    2008-01-01

    Neuromorphic hardware systems provide new possibilities for the neuroscience modeling community. Due to the intrinsic parallelism of the micro-electronic emulation of neural computation, such models are highly scalable without a loss of speed. However, the communities of software simulator users and neuromorphic engineering in neuroscience are rather disjoint. We present a software concept that provides the possibility to establish such hardware devices as valuable modeling tools. It is based on the integration of the hardware interface into a simulator-independent language which allows for unified experiment descriptions that can be run on various simulation platforms without modification, implying experiment portability and a huge simplification of the quantitative comparison of hardware and simulator results. We introduce an accelerated neuromorphic hardware device and describe the implementation of the proposed concept for this system. An example setup and results acquired by utilizing both the hardware system and a software simulator are demonstrated. PMID:19562085

  16. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    SciTech Connect

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  17. Efficient BinDCT hardware architecture exploration and implementation on FPGA.

    PubMed

    Ben Abdelali, Abdessalem; Chatti, Ichraf; Hannachi, Marwa; Mtibaa, Abdellatif

    2016-11-01

    This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances.

  18. A Computer Scientist’s Evaluation of Publically Available Hardware Trojan Benchmarks

    DTIC Science & Technology

    2015-09-01

    application-specific integrated circuit COTS commercial off-the-shelf DEF design exchange file DSP digital signal processor FPGA field-programmable gate...is a deliberate alteration to a piece of electronic hardware that causes that device, under certain conditions, to display undocumented...functionality. Hardware Trojans may be added to varying items of hardware, including application-specific integrated circuits (ASICs), digital signal

  19. Hardware based redundant multi-threading inside a GPU for improved reliability

    DOEpatents

    Sridharan, Vilas; Gurumurthi, Sudhanva

    2015-05-05

    A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.

  20. Space biology initiative program definition review. Trade study 3: Hardware miniaturization versus cost

    NASA Technical Reports Server (NTRS)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Herbert, Frank J.; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The optimum hardware miniaturization level with the lowest cost impact for space biology hardware was determined. Space biology hardware and/or components/subassemblies/assemblies which are the most likely candidates for application of miniaturization are to be defined and relative cost impacts of such miniaturization are to be analyzed. A mathematical or statistical analysis method with the capability to support development of parametric cost analysis impacts for levels of production design miniaturization are provided.

  1. 15 MW HArdware-in-the-loop Grid Simulation Project

    SciTech Connect

    Rigas, Nikolaos; Fox, John Curtiss; Collins, Randy; Tuten, James; Salem, Thomas; McKinney, Mark; Hadidi, Ramtin; Gislason, Benjamin; Boessneck, Eric; Leonard, Jesse

    2014-10-31

    The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA

  2. Life sciences flight hardware development for the International Space Station

    NASA Astrophysics Data System (ADS)

    Kern, V. D.; Bhattacharya, S.; Bowman, R. N.; Donovan, F. M.; Elland, C.; Fahlen, T. F.; Girten, B.; Kirven-Brooks, M.; Lagel, K.; Meeker, G. B.; Santos, O.

    During the construction phase of the International Space Station (ISS), early flight opportunities have been identified (including designated Utilization Flights, UF) on which early science experiments may be performed. The focus of NASA's and other agencies' biological studies on the early flight opportunities is cell and molecular biology; with UF-1 scheduled to fly in fall 2001, followed by flights 8A and UF-3. Specific hardware is being developed to verify design concepts, e.g., the Avian Development Facility for incubation of small eggs and the Biomass Production System for plant cultivation. Other hardware concepts will utilize those early research opportunities onboard the ISS, e.g., an Incubator for sample cultivation, the European Modular Cultivation System for research with small plant systems, an Insect Habitat for support of insect species. Following the first Utilization Flights, additional equipment will be transported to the ISS to expand research opportunities and capabilities, e.g., a Cell Culture Unit, the Advanced Animal Habitat for rodents, an Aquatic Facility to support small fish and aquatic specimens, a Plant Research Unit for plant cultivation, and a specialized Egg Incubator for developmental biology studies. Host systems (Figure 1A, B), e.g., a 2.5 m Centrifuge Rotor (g-levels from 0.01-g to 2-g) for direct comparisons between μg and selectable g levels, the Life Sciences Glove☐ for contained manipulations, and Habitat Holding Racks (Figure 1B) will provide electrical power, communication links, and cooling to the habitats. Habitats will provide food, water, light, air and waste management as well as humidity and temperature control for a variety of research organisms. Operators on Earth and the crew on the ISS will be able to send commands to the laboratory equipment to monitor and control the environmental and experimental parameters inside specific habitats. Common laboratory equipment such as microscopes, cryo freezers, radiation

  3. New Approaches in Force-Limited Vibration Testing of Flight Hardware

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Kern, Dennis L.

    2012-01-01

    To qualify flight hardware for random vibration environments the following methods are used to limit the loads in the aerospace industry: (1) Response limiting and notching (2) Simple TDOF model (3) Semi-empirical force limits (4) Apparent mass, etc. and (5) Impedance method. In all these methods attempts are made to remove conservatism due to the mismatch in impedances between the test and the flight configurations of the hardware that are being qualified. Assumption is the hardware interfaces have correlated responses. A new method that takes into account the un-correlated hardware interface responses are described in this presentation.

  4. Hardware and Software Integration to Support Real-Time Space-Link Emulation

    NASA Technical Reports Server (NTRS)

    Murawski, Robert; Bhasin, Kul; Bittner, David

    2012-01-01

    Prior to operational use, communications hardware and software must be thoroughly tested and verified. In space-link communications, field testing equipment can be prohibitively expensive and cannot test to non-ideal situations. In this paper, we show how software and hardware emulation tools can be used to accurately model the characteristics of a satellite communication channel in a lab environment. We describe some of the challenges associated with developing an emulation lab and present results to demonstrate the channel modeling. We then show how network emulation software can be used to extend a hardware emulation model without requiring additional network and channel simulation hardware.

  5. Analyzing the scaling of connectivity in neuromorphic hardware and in models of neural networks.

    PubMed

    Partzsch, Johannes; Schüffny, René

    2011-06-01

    In recent years, neuromorphic hardware systems have significantly grown in size. With more and more neurons and synapses integrated in such systems, the neural connectivity and its configurability have become crucial design constraints. To tackle this problem, we introduce a generic extended graph description of connection topologies that allows a systematical analysis of connectivity in both neuromorphic hardware and neural network models. The unifying nature of our approach enables a close exchange between hardware and models. For an existing hardware system, the optimally matched network model can be extracted. Inversely, a hardware architecture may be fitted to a particular model network topology with our description method. As a further strength, the extended graph can be used to quantify the amount of configurability for a certain network topology. This is a hardware design variable that has widely been neglected, mainly because of a missing analysis method. To condense our analysis results, we develop a classification for the scaling complexity of network models and neuromorphic hardware, based on the total number of connections and the configurability. We find a gap between several models and existing hardware, making these hardware systems either impossible or inefficient to use for scaled-up network models. In this respect, our analysis results suggest models with locality in their connections as promising approach for tackling this scaling gap.

  6. Speed challenge: a case for hardware implementation in soft-computing

    NASA Technical Reports Server (NTRS)

    Daud, T.; Stoica, A.; Duong, T.; Keymeulen, D.; Zebulum, R.; Thomas, T.; Thakoor, A.

    2000-01-01

    For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

  7. Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

    2000-01-01

    The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

  8. W-026 acceptance test plan plant control system hardware (submittal {number_sign} 216)

    SciTech Connect

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP 1 Plant Control System Hardware will be conducted throughout the construction of WRAP I with the final testing on the Process Area hardware being completed in November 1996. The hardware tests will be broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DNS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document will contain completed copies of each of the hardware tests along with the applicable test logs and completed test exception reports.

  9. Communications, Navigation, and Network Reconfigurable Test-bed Flight Hardware Compatibility Test S

    NASA Technical Reports Server (NTRS)

    2010-01-01

    Communications, Navigation, and Network Reconfigurable Test-bed Flight Hardware Compatibility Test Sets and Networks Integration Management Office Testing for the Tracking and Data Relay Satellite System

  10. Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

    PubMed Central

    Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

    2014-01-01

    In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration. PMID:24672292

  11. Essential SpaceWire Hardware Capabilities for a Robust Network

    NASA Technical Reports Server (NTRS)

    Birmingham, Michael; Krimchansky, Alexander; Anderson, William; Lombardi, Matthew

    2016-01-01

    The Geostationary Operational Environmental Satellite R-Series Program (GOES-R) mission is a joint program between National Oceanic & Atmospheric Administration (NOAA) and National Aeronautics & Space Administration (NASA) Goddard Space Flight Center (GSFC). GOES-R project selected SpaceWire as the best solution to satisfy the desire for simple and flexible instrument to spacecraft command and telemetry communications. GOES-R development and integration is complete and the observatory is scheduled for launch October 2016. The spacecraft design was required to support redundant SpaceWire links for each instrument side, as well as to route the fewest number of connections through a Slip Ring Assembly necessary to support Solar pointing instruments. The final design utilized two different router designs. The SpaceWire standard alone does not ensure the most practical or reliable network. On GOES-R a few key hardware capabilities were identified that merit serious consideration for future designs. Primarily these capabilities address persistent port stalls and the prevention of receive buffer overflows. Workarounds were necessary to overcome shortcomings that could be avoided in future designs if they utilize the capabilities, discussed in this paper, above and beyond the requirements of the SpaceWire standard.

  12. Space station common module network topology and hardware development

    NASA Technical Reports Server (NTRS)

    Anderson, P.; Braunagel, L.; Chwirka, S.; Fishman, M.; Freeman, K.; Eason, D.; Landis, D.; Lech, L.; Martin, J.; Mccorkle, J.

    1990-01-01

    Conceptual space station common module power management and distribution (SSM/PMAD) network layouts and detailed network evaluations were developed. Individual pieces of hardware to be developed for the SSM/PMAD test bed were identified. A technology assessment was developed to identify pieces of equipment requiring development effort. Equipment lists were developed from the previously selected network schematics. Additionally, functional requirements for the network equipment as well as other requirements which affected the suitability of specific items for use on the Space Station Program were identified. Assembly requirements were derived based on the SSM/PMAD developed requirements and on the selected SSM/PMAD network concepts. Basic requirements and simplified design block diagrams are included. DC remote power controllers were successfully integrated into the DC Marshall Space Flight Center breadboard. Two DC remote power controller (RPC) boards experienced mechanical failure of UES 706 stud-mounted diodes during mechanical installation of the boards into the system. These broken diodes caused input to output shorting of the RPC's. The UES 706 diodes were replaced on these RPC's which eliminated the problem. The DC RPC's as existing in the present breadboard configuration do not provide ground fault protection because the RPC was designed to only switch the hot side current. If ground fault protection were to be implemented, it would be necessary to design the system so the RPC switched both the hot and the return sides of power.

  13. UniBoard: generic hardware for radio astronomy signal processing

    NASA Astrophysics Data System (ADS)

    Hargreaves, J. E.

    2012-09-01

    UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

  14. A hardware implementation of multiresolution filtering for broadband instrumentation

    SciTech Connect

    Kercel, S.W.; Dress, W.B.

    1995-12-01

    The authors have constructed a wavelet processing board that implements a 14-level wavelet transform. The board uses a high-speed, analog-to-digital (A/D) converter, a hardware queue, and five fixed-point digital signal processing (DSP) chips in a parallel pipeline architecture. All five processors are independently programmable. The board is designed as a general purpose engine for instrumentation applications requiring near real-time wavelet processing or multiscale filtering. The present application is the processing engine of a magnetic field monitor that covers 305 Hz through 5 MHz. The monitor is used for the detection of peak values of magnetic fields in nuclear power plants. This paper describes the design, development, simulation, and testing of the system. Specific issues include the conditioning of real-world signals for wavelet processing, practical trade-offs between queue length and filter length, selection of filter coefficients, simulation of a 14-octave filter bank, and limitations imposed by a fixed-point processor. Test results from the completed wavelet board are included.

  15. What Scientific Applications can Benefit from Hardware Transactional Memory?

    SciTech Connect

    Schindewolf, M; Bihari, B; Gyllenhaal, J; Schulz, M; Wang, A; Karl, W

    2012-06-04

    Achieving efficient and correct synchronization of multiple threads is a difficult and error-prone task at small scale and, as we march towards extreme scale computing, will be even more challenging when the resulting application is supposed to utilize millions of cores efficiently. Transactional Memory (TM) is a promising technique to ease the burden on the programmer, but only recently has become available on commercial hardware in the new Blue Gene/Q system and hence the real benefit for realistic applications has not been studied, yet. This paper presents the first performance results of TM embedded into OpenMP on a prototype system of BG/Q and characterizes code properties that will likely lead to benefits when augmented with TM primitives. We first, study the influence of thread count, environment variables and memory layout on TM performance and identify code properties that will yield performance gains with TM. Second, we evaluate the combination of OpenMP with multiple synchronization primitives on top of MPI to determine suitable task to thread ratios per node. Finally, we condense our findings into a set of best practices. These are applied to a Monte Carlo Benchmark and a Smoothed Particle Hydrodynamics method. In both cases an optimized TM version, executed with 64 threads on one node, outperforms a simple TM implementation. MCB with optimized TM yields a speedup of 27.45 over baseline.

  16. RF control hardware design for CYCIAE-100 cyclotron

    NASA Astrophysics Data System (ADS)

    Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-01

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  17. Automated Eddy Current Inspection on Space Shuttle Hardware

    NASA Technical Reports Server (NTRS)

    Hartmann, John; Felker, Jeremy

    2007-01-01

    Over the life time of the Space Shuttle program, metal parts used for the Reusable Solid Rocket Motors (RSRMs) have been nondestructively inspected for cracks and surface breaking discontinuities using magnetic particle (steel) and penetrant methods. Although these inspections adequately screened for critical sized cracks in most regions of the hardware, it became apparent after detection of several sub-critical flaws that the processes were very dependent on operator attentiveness and training. Throughout the 1990's, eddy current inspections were added to areas that had either limited visual access or were more fracture critical. In the late 1990's. a project was initiated to upgrade NDE inspections with the overall objective of improving inspection reliability and control. An automated eddy current inspection system was installed in 2001. A figure shows one of the inspection bays with the robotic axis of the system highlighted. The system was programmed to inspect the various case, nozzle, and igniter metal components that make up an RSRM. both steel and aluminum. For the past few years, the automated inspection system has been a part of the baseline inspection process for steel components. Although the majority of the RSRM metal part inventory ts free of detectable surface flaws, a few small, sub-critical manufacturing defects have been detected with the automated system. This paper will summarize the benefits that have been realized with the current automated eddy current system, as well as the flaws that have been detected.

  18. Surveys of ISS Returned Hardware for MMOD Impacts

    NASA Technical Reports Server (NTRS)

    Hyde, James; Christiansen, E.; Lear, D.; Nagy, K.

    2017-01-01

    Since February 2001, the Hypervelocity Impact Technology (HVIT) group at the Johnson Space Center in Houston has performed 26 post-flight inspections on space exposed hardware that have been returned from the International Space Station. Data on 1,024 observations of MMOD damage have been collected from these inspections. Survey documentation typically includes impact feature location and size measurements as well as microscopic photography (25-200x). Sampling of impacts sites for projectile residue was performed for the largest features. Results of Scanning Electron Microscopy (SEM) analysis to discern impactor source is included in the database. This paper will summarize the post-flight MMOD inspections, and focus on two inspections in particular: (1) Pressurized Mating Adapter-2 (PMA-2) cover returned in 2015 after 1.6 years exposure with 26 observed damages, and (2) Airlock shield panels returned in 2010 after 8.7 years exposure with 58 MMOD damages. Feature sizes from the observed data are compared to predictions using the Bumper risk assessment code.

  19. Astronaut Prepares for Mission With Virtual Reality Hardware

    NASA Technical Reports Server (NTRS)

    2001-01-01

    Astronaut John M. Grunsfeld, STS-109 payload commander, uses virtual reality hardware at Johnson Space Center to rehearse some of his duties prior to the STS-109 mission. The most familiar form of virtual reality technology is some form of headpiece, which fits over your eyes and displays a three dimensional computerized image of another place. Turn your head left and right, and you see what would be to your sides; turn around, and you see what might be sneaking up on you. An important part of the technology is some type of data glove that you use to propel yourself through the virtual world. This technology allows NASA astronauts to practice International Space Station work missions in advance. Currently, the medical community is using the new technologies in four major ways: To see parts of the body more accurately, for study, to make better diagnosis of disease and to plan surgery in more detail; to obtain a more accurate picture of a procedure during surgery; to perform more types of surgery with the most noninvasive, accurate methods possible; and to model interactions among molecules at a molecular level.

  20. Astronauts Prepare for Mission With Virtual Reality Hardware

    NASA Technical Reports Server (NTRS)

    2001-01-01

    Astronauts John M. Grunsfeld (left), STS-109 payload commander, and Nancy J. Currie, mission specialist, use the virtual reality lab at Johnson Space Center to train for upcoming duties aboard the Space Shuttle Columbia. This type of computer interface paired with virtual reality training hardware and software helps to prepare the entire team to perform its duties for the fourth Hubble Space Telescope Servicing mission. The most familiar form of virtual reality technology is some form of headpiece, which fits over your eyes and displays a three dimensional computerized image of another place. Turn your head left and right, and you see what would be to your sides; turn around, and you see what might be sneaking up on you. An important part of the technology is some type of data glove that you use to propel yourself through the virtual world. Currently, the medical community is using the new technologies in four major ways: To see parts of the body more accurately, for study, to make better diagnosis of disease and to plan surgery in more detail; to obtain a more accurate picture of a procedure during surgery; to perform more types of surgery with the most noninvasive, accurate methods possible; and to model interactions among molecules at a molecular level.

  1. Hardware implementation of multiresolution filtering for broadband instrumentation

    NASA Astrophysics Data System (ADS)

    Kercel, Stephen W.; Dress, William B.

    1995-04-01

    The authors have constructed a wavelet processing board that implements a 14-level wavelet transform. The board uses a high-speed analog-to-digital (A/D) converter, a hardware queue, and five fixed-point digital signal processing (DSP) chips in a parallel pipeline architecture. All five processors are independently programmable. The board is designed as a general purpose engine for instrumentation applications requiring near real-time wavelet processing or multiscale filtering. The present application is the processing engine of a magnetic field monitor that covers 305 Hz through 5 MHz. The monitor is used for the detection of peak values of magnetic fields in nuclear power plants. This paper describes the design, development, simulation, and testing of the system. Specific issues include the conditioning of real-world signals for wavelet processing, practical trade-offs between queue length and filter length, selection of filter coefficients, simulation of a 14-octave filter bank, and limitations imposed by a fixed-point processor. Test results from the completed wavelet board are included.

  2. Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

    NASA Technical Reports Server (NTRS)

    Hereford, James; Gwaltney, David

    2004-01-01

    In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

  3. The Fluid Processing Apparatus: from Flight Hardware to Electron Micrographs

    NASA Technical Reports Server (NTRS)

    Hilaire, Emmanuel; Brown, Christopher S.; Guikema, James A.

    1995-01-01

    Since the early years of space biology, a major drawback in spaceflight plant experiments has been the inability to fix specimens in microgravity, relying instead on fixation after return to Earth. As there, it is of a growing interest to look at the effect of microgravity on the structure and the developmental polarity of root graviperceptive cells, or columella cells, and so, it is important to use flight hardware which allows specimen fixation in space therefore avoiding the confounding effects of rapid readaptation to gravity after landing. As part of the Bioserve Space Technologies, a Center for the Commercial Development of Space (CCDS), we now have experiment flight opportunities through the Commercial Generic Bioprocessing Apparatus (CGBA) payload. In this study the Fluid Processing Apparatus (FPA) was used to grow seedlings for a limited period of time prior to fixation of the tissue in a microgravity environment. Upon return to Earth, the samples were processed for electron microscopy. This report describes the microscopic data obtained from the two space flights (STS-54 and STS-60). In both cases, the electron micrographs of the columella cells revealed well preserved cell structure, well defined microtubules, and the presence of calcium precipitates formed by a antimonate precipitation method.

  4. Secure management of biomedical data with cryptographic hardware.

    PubMed

    Canim, Mustafa; Kantarcioglu, Murat; Malin, Bradley

    2012-01-01

    The biomedical community is increasingly migrating toward research endeavors that are dependent on large quantities of genomic and clinical data. At the same time, various regulations require that such data be shared beyond the initial collecting organization (e.g., an academic medical center). It is of critical importance to ensure that when such data are shared, as well as managed, it is done so in a manner that upholds the privacy of the corresponding individuals and the overall security of the system. In general, organizations have attempted to achieve these goals through deidentification methods that remove explicitly, and potentially, identifying features (e.g., names, dates, and geocodes). However, a growing number of studies demonstrate that deidentified data can be reidentified to named individuals using simple automated methods. As an alternative, it was shown that biomedical data could be shared, managed, and analyzed through practical cryptographic protocols without revealing the contents of any particular record. Yet, such protocols required the inclusion of multiple third parties, which may not always be feasible in the context of trust or bandwidth constraints. Thus, in this paper, we introduce a framework that removes the need for multiple third parties by collocating services to store and to process sensitive biomedical data through the integration of cryptographic hardware. Within this framework, we define a secure protocol to process genomic data and perform a series of experiments to demonstrate that such an approach can be run in an efficient manner for typical biomedical investigations.

  5. Development of hardware for a drag-free control system

    NASA Astrophysics Data System (ADS)

    Leach, Rachel

    2003-03-01

    Space-borne gravitational wave missions like LISA require Drag-Free Contorl (DFC) systems to control the motion of a constellation of spaceraft to high positional accuracy so that Michelson interferometers of vast scales can be implemented and used to detect gravitational waves. The spacecraft will continually experience forces and torques due to external disturbances, resulting in positional perturbations. Therefore the development of a DFC system is essential to stabilize the spacecraft to a specified tolerance. Prior to such space-borne gravitational wave missions, a technology demonstrator mission, such as the proposed ODIE, ELITE or SMART-2, is needed to test the feasibility of drag-free spacecraft technology. This paper discusses the requirements of the hardware needed to implement a DFC system. Contorl-loop models ahve been develoepd to model the DFC system's dynamic behavior, which enabled quantification of its performance. Results show that if an accelerometer noise level of 1×10-12 m Hz-0.5 and thruster noise level of 1×10-8 N Hz-0.5 can be realized then the ODIE acceleration budget can easily be met.

  6. Secure Management of Biomedical Data With Cryptographic Hardware

    PubMed Central

    Canim, Mustafa; Kantarcioglu, Murat; Malin, Bradley

    2014-01-01

    The biomedical community is increasingly migrating toward research endeavors that are dependent on large quantities of genomic and clinical data. At the same time, various regulations require that such data be shared beyond the initial collecting organization (e.g., an academic medical center). It is of critical importance to ensure that when such data are shared, as well as managed, it is done so in a manner that upholds the privacy of the corresponding individuals and the overall security of the system. In general, organizations have attempted to achieve these goals through deidentification methods that remove explicitly, and potentially, identifying features (e.g., names, dates, and geocodes). However, a growing number of studies demonstrate that deidentified data can be reidentified to named individuals using simple automated methods. As an alternative, it was shown that biomedical data could be shared, managed, and analyzed through practical cryptographic protocols without revealing the contents of any particular record. Yet, such protocols required the inclusion of multiple third parties, which may not always be feasible in the context of trust or bandwidth constraints. Thus, in this paper, we introduce a framework that removes the need for multiple third parties by collocating services to store and to process sensitive biomedical data through the integration of cryptographic hardware. Within this framework, we define a secure protocol to process genomic data and perform a series of experiments to demonstrate that such an approach can be run in an efficient manner for typical biomedical investigations. PMID:22010157

  7. Physics of Colloids in Space: Flight Hardware Operations on ISS

    NASA Technical Reports Server (NTRS)

    Doherty, Michael P.; Bailey, Arthur E.; Jankovsky, Amy L.; Lorik, Tibor

    2002-01-01

    The Physics of Colloids in Space (PCS) experiment was launched on Space Shuttle STS-100 in April 2001 and integrated into EXpedite the PRocess of Experiments to Space Station Rack 2 on the International Space Station (ISS). This microgravity fluid physics investigation is being conducted in the ISS U.S. Lab 'Destiny' Module over a period of approximately thirteen months during the ISS assembly period from flight 6A through flight 9A. PCS is gathering data on the basic physical properties of simple colloidal suspensions by studying the structures that form. A colloid is a micron or submicron particle, be it solid, liquid, or gas. A colloidal suspension consists of these fine particles suspended in another medium. Common colloidal suspensions include paints, milk, salad dressings, cosmetics, and aerosols. Though these products are routinely produced and used, we still have much to learn about their behavior as well as the underlying properties of colloids in general. The long-term goal of the PCS investigation is to learn how to steer the growth of colloidal structures to create new materials. This experiment is the first part of a two-stage investigation conceived by Professor David Weitz of Harvard University (the Principal Investigator) along with Professor Peter Pusey of the University of Edinburgh (the Co-Investigator). This paper describes the flight hardware, experiment operations, and initial science findings of the first fluid physics payload to be conducted on ISS: The Physics of Colloids in Space.

  8. Physics of Colloids in Space (PCS) Flight Hardware Developed

    NASA Technical Reports Server (NTRS)

    Koudelka, John M.

    2001-01-01

    investigation that will be located in an Expedite the Process of Experiments to Space Station (EXPRESS) Rack. The investigation will be conducted in the International Space Station U.S. laboratory, Destiny, over a period of approximately 10 months during the station assembly period from flight 6A through flight UF-2. This experiment will gather data on the basic physical properties of colloids by studying three different colloid systems with the objective of understanding how they grow and what structures they form. A colloidal suspension consists of fine particles (micrometer to submicrometer) suspended in a fluid for example, paints, milk, salad dressings, and aerosols. The long-term goal of this investigation is to learn how to steer the growth of colloidal suspensions to create new materials and new structures. This experiment is part of a two-stage investigation conceived by Professor David Weitz of Harvard University along with Professor Peter Pusey of the University of Edinburgh. The experiment hardware was developed by the NASA Glenn Research Center through contracts with Dynacs, Inc., and ZIN Technologies.

  9. Real-time 3D video conference on generic hardware

    NASA Astrophysics Data System (ADS)

    Desurmont, X.; Bruyelle, J. L.; Ruiz, D.; Meessen, J.; Macq, B.

    2007-02-01

    Nowadays, video-conference tends to be more and more advantageous because of the economical and ecological cost of transport. Several platforms exist. The goal of the TIFANIS immersive platform is to let users interact as if they were physically together. Unlike previous teleimmersion systems, TIFANIS uses generic hardware to achieve an economically realistic implementation. The basic functions of the system are to capture the scene, transmit it through digital networks to other partners, and then render it according to each partner's viewing characteristics. The image processing part should run in real-time. We propose to analyze the whole system. it can be split into different services like central processing unit (CPU), graphical rendering, direct memory access (DMA), and communications trough the network. Most of the processing is done by CPU resource. It is composed of the 3D reconstruction and the detection and tracking of faces from the video stream. However, the processing needs to be parallelized in several threads that have as little dependencies as possible. In this paper, we present these issues, and the way we deal with them.

  10. Design of coupling resistor networks for neural network hardware

    NASA Astrophysics Data System (ADS)

    Barkan, Ozdal; Smith, W. R.; Persky, George

    1990-06-01

    The specification of an artificial neural network includes (1) the transformation relating each neuron's output voltage to its input voltage, and (2) a set of coupling weight factors expressing the input voltage of any neuron as a linear combination of the output voltages of other neurons. In analog VLSI chips for direct hardware implementation of these networks, neurons are often represented by amplifier elements (e.g. operational amplifiers or opamps), and resistors or active transconductances are used to couple signals from the outputs of certain neurons to the inputs of other neurons. Each coupling conductance is proportional to a single, corresponding coupling weight only under the following 'ideal' conditions: (1) each opamp has negligible output impedance, and (2) the input voltage of each opamp is developed across a low-resistance sampling resistor that is not loaded by the opamp itself. By contrast, the output impedance of a practical opamp may not be negligible in comparison to that of the high-fan network that it drives, and the sampling resistances on the opamp inputs cannot be arbitrarily low lest the input voltages be corrupted by unavoidable opamp input voltage offsets.

  11. Cartilage formation in the CELLS 'double bubble' hardware

    NASA Technical Reports Server (NTRS)

    Duke, P. J.; Arizpe, Jorge; Montufar-Solis, Dina

    1991-01-01

    The CELLS experiment scheduled to be flown on the first International Microgravity Laboratory is designed to study the effect of microgravity on the cartilage formation, by measuring parameters of growth in a differentiating cartilage cell culture. This paper investigates the conditions for this experiment by studying cartilage differentiation in the 'bubble exchange' hardware with the 'double bubble' design in which the bubbles are joined by a flange which also overlays the gasket. Four types of double bubbles (or double gas permeable membranes) were tested: injection-molded bubbles 0.01- and 0.005-in. thick, and compression molded bubbles 0.015- and 0.01-in. thick. It was found that double bubble membranes of 0.005- and 0.010-in. thickness supported cartilage differentiation, while the 0.015-in. bubbles did not. It was also found that nodule count, used in this study as a parameter, is not the best measure of the amount of cartilage differentiation.

  12. Solid-Liquid Interface Characterization Hardware: Advanced Technology Development (ATD)

    NASA Technical Reports Server (NTRS)

    Peters, Palmer N.; Sisk, R. C.; Sen, S.; Kaukler, W. F.; Curreri, Peter A.; Wang, F. C.; Rose, M. Franklin (Technical Monitor)

    2000-01-01

    This ATD has the goal of enabling the integration of three separate measurement techniques to characterize the solid-liquid interface of directionally solidified materials in real-time. Arrays of film-based metal thermocouple elements are under development along with compact Seebeck furnaces suitable for interfacing with separately developed X-ray Transmission Microscopes. Results of applying film arrays to furnace profiling are shown, demonstrating their ability to identify a previously undetected hardware flaw in the development of a second-generation compact furnace. Results of real-time furnace profiling also confirmed that the compact furnace design effectively isolates the temperature profiles in two halves of the furnace, a necessary feature. This isolation had only been inferred previously from the characteristics of Seebeck data reported. Results from a 24-thermocouple array successfully monitoring heating and isothermal cooling of a tin sample are shown. The importance of non-intrusion by the arrays, as well as furnace design, on the profiling of temperature gradients is illustrated with example measurements. Further developments underway for effectively combining all three measurements are assessed in terms of improved x-ray transmission, increased magnification, integral arrays with minimum intrusion, integral scales for velocity measurements and other features being incorporated into the third generation Seebeck furnace under construction.

  13. Measuring FLOPS Using Hardware Performance Counter Technologies on LC systems

    SciTech Connect

    Ahn, D H

    2008-09-05

    FLOPS (FLoating-point Operations Per Second) is a commonly used performance metric for scientific programs that rely heavily on floating-point (FP) calculations. The metric is based on the number of FP operations rather than instructions, thereby facilitating a fair comparison between different machines. A well-known use of this metric is the LINPACK benchmark that is used to generate the Top500 list. It measures how fast a computer solves a dense N by N system of linear equations Ax=b, which requires a known number of FP operations, and reports the result in millions of FP operations per second (MFLOPS). While running a benchmark with known FP workloads can provide insightful information about the efficiency of a machine's FP pipelines in relation to other machines, measuring FLOPS of an arbitrary scientific application in a platform-independent manner is nontrivial. The goal of this paper is twofold. First, we explore the FP microarchitectures of key processors that are underpinning the LC machines. Second, we present the hardware performance monitoring counter-based measurement techniques that a user can use to get the native FLOPS of his or her program, which are practical solutions readily available on LC platforms. By nature, however, these native FLOPS metrics are not directly comparable across different machines mainly because FP operations are not consistent across microarchitectures. Thus, the first goal of this paper represents the base reference by which a user can interpret the measured FLOPS more judiciously.

  14. Use of brain MRI after deep brain stimulation hardware implantation.

    PubMed

    Nazzaro, Jules M; Lyons, Kelly E; Wetzel, Louis H; Pahwa, Rajesh

    2010-03-01

    The objective of this study was to examine the experience with and safety of brain 1.5 Tesla (T) magnetic resonance imaging (MRI) in deep brain stimulation (DBS) patients. This was a retrospective review of brain MRI scanning performed on DBS patients at the University of Kansas Medical Center between January 1995 and December 2007. A total of 249 DBS patients underwent 445 brain 1.5 T MRI scan sessions encompassing 1,092 individual scans using a transmit-receive head coil, representing the cumulative scanning of 1,649 DBS leads. Patients with complete implanted DBS systems as well as those with externalized leads underwent brain imaging. For the majority of scans, specific absorption rates localized to the head (SAR(H)) were estimated and in all cases SAR(H) were higher than that specified in the present product labeling. There were no clinical or hardware related adverse events secondary to brain MRI scanning. Our data should not be extrapolated to encourage MRI scanning beyond the present labeling. Rather, our data may contribute to further defining safe MRI scanning parameters that might ultimately be adopted in future product labeling as more centers report in detail their experiences.

  15. Structuring Formal Control Systems Specifications for Reuse: Surviving Hardware Changes

    NASA Technical Reports Server (NTRS)

    Thompson, Jeffrey M.; Heimdahl, Mats P. E.; Erickson, Debra M.

    2000-01-01

    Formal capture and analysis of the required behavior of control systems have many advantages. For instance, it encourages rigorous requirements analysis, the required behavior is unambiguously defined, and we can assure that various safety properties are satisfied. Formal modeling is, however, a costly and time consuming process and if one could reuse the formal models over a family of products, significant cost savings would be realized. In an ongoing project we are investigating how to structure state-based models to achieve a high level of reusability within product families. In this paper we discuss a high-level structure of requirements models that achieves reusability of the desired control behavior across varying hardware platforms in a product family. The structuring approach is demonstrated through a case study in the mobile robotics domain where the desired robot behavior is reused on two diverse platforms-one commercial mobile platform and one build in-house. We use our language RSML (-e) to capture the control behavior for reuse and our tool NIMBUS to demonstrate how the formal specification can be validated and used as a prototype on the two platforms.

  16. Various hardware in the SSPF undergoes or waits for testing.

    NASA Technical Reports Server (NTRS)

    2000-01-01

    The floor of the Space Station Processing Facility is filled with racks and hardware for testing the various components of the International Space Station (ISS). The large module in the center of the floor (top) is the U.S. Lab, Destiny. The U.S. Laboratory module continues a long tradition of microgravity materials research, first conducted by Skylab and later Shuttle and Spacelab missions. Destiny is expected to be a major feature in future research, providing facilities for biotechnology, fluid physics, combustion, and life sciences research. It is scheduled to be launched on mission STS-98 (no date determined yet for launch). At top left are the Multi-Purpose Logistics Modules Raffaello and Leonardo and the Pressurized Mating Adapter-3 (PMA- 3). Italy's major contributions to the ISS program, Raffaello and Leonardo are reusable logistics carriers to resupply and return Station cargo requiring a pressurized environment. They are slated as payloads on missions STS-102 and STS-100, respectively. Dates have not yet been determined for the two missions. The PMA- 3, once launched, will be mated to Node 1, a connecting passageway to the living and working areas of the Space Station. The primary purpose of PMA-3 is to serve as a Shuttle docking port through which crew members and equipment will transfer to the Space Station during later assembly missions. PMA-3 is scheduled as payload on mission STS-92, whose date for launch is not yet determined.

  17. Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development

    DTIC Science & Technology

    2016-09-01

    ARL-TN-0779 ● SEP 2016 US Army Research Laboratory Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and... Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development by Neal Tesny Sensors and Electron Devices Directorate...TITLE AND SUBTITLE Electronic Warfare Closed Loop Laboratory (EWCLL) Antenna Motor Software and Hardware Development 5a. CONTRACT NUMBER 5b

  18. Round Girls in Square Computers: Feminist Perspectives on the Aesthetics of Computer Hardware.

    ERIC Educational Resources Information Center

    Carr-Chellman, Alison A.; Marra, Rose M.; Roberts, Shari L.

    2002-01-01

    Considers issues related to computer hardware, aesthetics, and gender. Explores how gender has influenced the design of computer hardware and how these gender-driven aesthetics may have worked to maintain, extend, or alter gender distinctions, roles, and stereotypes; discusses masculine media representations; and presents an alternative model.…

  19. An Analysis of Hardware Requirements for Airborne Tactical Mesh Networking Nodes

    DTIC Science & Technology

    2005-03-01

    Global PAGES Information Grid, MANET, Wireless, OLSR, Sensor Networks, Tactical 53 Network Topology, Single Board Computer , PC/104, Tern UAV 16. PRICE...21 A . HARDWARE .......................................... 21 1. Single Board Computer ........................ 21 2. Compact Flash...logical choice was to base an improved design on the PC/104 standard for embedded PC architecture. A. HARDWARE 1. Single Board Computer Embedded

  20. Use of CCSDS Packets Over SpaceWire to Control Hardware

    NASA Technical Reports Server (NTRS)

    Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

    2012-01-01

    For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

  1. Functional design specification for Stowage List And Hardware Tracking System (SLAHTS). [space shuttles

    NASA Technical Reports Server (NTRS)

    Keltner, D. J.

    1975-01-01

    This functional design specification defines the total systems approach to meeting the requirements stated in the Detailed Requirements Document for Stowage List and Hardware Tracking System for the space shuttle program. The stowage list and hardware tracking system is identified at the system and subsystem level with each subsystem defined as a function of the total system.

  2. A Hardware Platform for Characterizing and Validating 1-Dimensional Optical Systems

    DTIC Science & Technology

    2014-09-01

    and microcontroller , are presented in detail along with ancillary subsystems that support and enhance the functionality of this apparatus. Specifics...3 2.3 Microcontroller ...7 3. Major Hardware Component Integration 7 4. Ancillary Hardware Components 10 4.1 Microcontroller In

  3. Application of innovative rendering techniques for the hardware-in-the-loop (HIL) scene generation

    NASA Astrophysics Data System (ADS)

    Bergin, Thomas P.

    2003-09-01

    A revolution is underway within commercial PC video graphics, driven mainly by the 3-D gaming community and its demands for customizable lighting effects and realistic, visually appealing, 3-D rendering. This revolution is bringing about a configurable transformation and lighting (T&L) engine within modern PC video graphics hardware. The results of these technological advancements will profoundly impact the way computer-based rendering is done. Although PC graphics hardware continues to change rapidly, it has evolved to the point where it can be made to address most of the Hardware-In-the-Loop (HWIL) scene generation demands which historically could be accomplished only on costly graphics workstations. With the ability to control how operations are performed within the hardware rendering process, it is possible to implement customized per-pixel spatial and lighting effects. To illustrate how these capabilities can be applied to solve certain HWIL scene generation problems. A graphics hardware approach will be implemented to demonstrate a method of achieving increased monochrome intensity resolution and a user-defined spatial distortion. There is great potential in modern graphics hardware. The limits are becoming less a function of the hardware capabilities and more a function of the ability of engineers and scientists to exploit the functionality of this rapidly advancing hardware rendering technology.

  4. Alternative, Green Processes for the Precision Cleaning of Aerospace Hardware

    NASA Technical Reports Server (NTRS)

    Maloney, Phillip R.; Grandelli, Heather Eilenfield; Devor, Robert; Hintze, Paul E.; Loftin, Kathleen B.; Tomlin, Douglas J.

    2014-01-01

    Precision cleaning is necessary to ensure the proper functioning of aerospace hardware, particularly those systems that come in contact with liquid oxygen or hypergolic fuels. Components that have not been cleaned to the appropriate levels may experience problems ranging from impaired performance to catastrophic failure. Traditionally, this has been achieved using various halogenated solvents. However, as information on the toxicological and/or environmental impacts of each came to light, they were subsequently regulated out of use. The solvent currently used in Kennedy Space Center (KSC) precision cleaning operations is Vertrel MCA. Environmental sampling at KSC indicates that continued use of this or similar solvents may lead to high remediation costs that must be borne by the Program for years to come. In response to this problem, the Green Solvents Project seeks to develop state-of-the-art, green technologies designed to meet KSCs precision cleaning needs.Initially, 23 solvents were identified as potential replacements for the current Vertrel MCA-based process. Highly halogenated solvents were deliberately omitted since historical precedents indicate that as the long-term consequences of these solvents become known, they will eventually be regulated out of practical use, often with significant financial burdens for the user. Three solvent-less cleaning processes (plasma, supercritical carbon dioxide, and carbon dioxide snow) were also chosen since they produce essentially no waste stream. Next, experimental and analytical procedures were developed to compare the relative effectiveness of these solvents and technologies to the current KSC standard of Vertrel MCA. Individually numbered Swagelok fittings were used to represent the hardware in the cleaning process. First, the fittings were cleaned using Vertrel MCA in order to determine their true cleaned mass. Next, the fittings were dipped into stock solutions of five commonly encountered contaminants and were

  5. Magnetic particle imaging: introduction to imaging and hardware realization.

    PubMed

    Buzug, Thorsten M; Bringout, Gael; Erbe, Marlitt; Gräfe, Ksenija; Graeser, Matthias; Grüttner, Mandy; Halkola, Aleksi; Sattel, Timo F; Tenner, Wiebke; Wojtczyk, Hanne; Haegele, Julian; Vogt, Florian M; Barkhausen, Jörg; Lüdtke-Buzug, Kerstin

    2012-12-01

    Magnetic Particle Imaging (MPI) is a recently invented tomographic imaging method that quantitatively measures the spatial distribution of a tracer based on magnetic nanoparticles. The new modality promises a high sensitivity and high spatial as well as temporal resolution. There is a high potential of MPI to improve interventional and image-guided surgical procedures because, today, established medical imaging modalities typically excel in only one or two of these important imaging properties. MPI makes use of the non-linear magnetization characteristics of the magnetic nanoparticles. For this purpose, two magnetic fields are created and superimposed, a static selection field and an oscillatory drive field. If superparamagnetic iron-oxide nanoparticles (SPIOs) are subjected to the oscillatory magnetic field, the particles will react with a non-linear magnetization response, which can be measured with an appropriate pick-up coil arrangement. Due to the non-linearity of the particle magnetization, the received signal consists of the fundamental excitation frequency as well as of harmonics. After separation of the fundamental signal, the nanoparticle concentration can be reconstructed quantitatively based on the harmonics. The spatial coding is realized with the static selection field that produces a field-free point, which is moved through the field of view by the drive fields. This article focuses on the frequency-based image reconstruction approach and the corresponding imaging devices while alternative concepts like x-space MPI and field-free line imaging are described as well. The status quo in hardware realization is summarized in an overview of MPI scanners.

  6. Implementing the lattice Boltzmann model on commodity graphics hardware

    NASA Astrophysics Data System (ADS)

    Kaufman, Arie; Fan, Zhe; Petkov, Kaloian

    2009-06-01

    Modern graphics processing units (GPUs) can perform general-purpose computations in addition to the native specialized graphics operations. Due to the highly parallel nature of graphics processing, the GPU has evolved into a many-core coprocessor that supports high data parallelism. Its performance has been growing at a rate of squared Moore's law, and its peak floating point performance exceeds that of the CPU by an order of magnitude. Therefore, it is a viable platform for time-sensitive and computationally intensive applications. The lattice Boltzmann model (LBM) computations are carried out via linear operations at discrete lattice sites, which can be implemented efficiently using a GPU-based architecture. Our simulations produce results comparable to the CPU version while improving performance by an order of magnitude. We have demonstrated that the GPU is well suited for interactive simulations in many applications, including simulating fire, smoke, lightweight objects in wind, jellyfish swimming in water, and heat shimmering and mirage (using the hybrid thermal LBM). We further advocate the use of a GPU cluster for large scale LBM simulations and for high performance computing. The Stony Brook Visual Computing Cluster has been the platform for several applications, including simulations of real-time plume dispersion in complex urban environments and thermal fluid dynamics in a pressurized water reactor. Major GPU vendors have been targeting the high performance computing market with GPU hardware implementations. Software toolkits such as NVIDIA CUDA provide a convenient development platform that abstracts the GPU and allows access to its underlying stream computing architecture. However, software programming for a GPU cluster remains a challenging task. We have therefore developed the Zippy framework to simplify GPU cluster programming. Zippy is based on global arrays combined with the stream programming model and it hides the low-level details of the

  7. RESEARCH PROGRESS AND HARDWARE SYSTEMS AT DIII-D

    SciTech Connect

    PETERSEN,P.I; THE DIII-D TEAM

    2003-10-01

    OAK-B135 During the last two years significant progress has been made in the scientific understanding of DIII-D plasmas. Much of this progress has been enabled by the addition of new hardware systems. The electron cyclotron (EC) system has been upgraded from 3 MW to 6 MW, by adding three 1 MW gyrotrons with diamond windows and three steerable launchers (PPPL). The new gyrotrons have been tested to 1.0 MW for 5 s. The system has been used to control the 3/2 and 2/1 neoclassical tearing modes and to locally heat the plasma and thereby indirectly control the current density. Electron cyclotron current drive ECCD has been used to directly affect the current density. A Li-beam diagnostic has been brought on-line for measuring the edge current density using Zeeman splitting. A set of 12 coils (1-coils), consisting of six picture frame coils each above and below the midplane, with a capability of 7 kA for 10 s has been installed inside the DIII-D vessel. These coils, along with the existing six C-coils, are used to apply non-axisymmetric fields to the plasma for both exciting and controlling plasma instabilities. The DIII-D digital plasma control system is now used to not just control the shape and location of the plasma but also the electron temperature, density, the NTMs, RWMs, plasma beta and disruption mitigation. Plasma disruption experiments are extended to mitigation of real time detected disruptions on DIII-D.

  8. FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine

    NASA Astrophysics Data System (ADS)

    Zaitsu, Kazuya; Yamamoto, Koji; Kuroda, Yasuto; Inoue, Kazunari; Ata, Shingo; Oka, Ikuo

    Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

  9. A hardware implementation of artificial neural networks using field programmable gate arrays

    NASA Astrophysics Data System (ADS)

    Won, E.

    2007-11-01

    An artificial neural network algorithm is implemented using a low-cost field programmable gate array hardware. One hidden layer is used in the feed-forward neural network structure in order to discriminate one class of patterns from the other class in real time. In this work, the training of the network is performed in the off-line computing environment and the results of the training are configured to the hardware in order to minimize the latency of the neural computation. With five 8-bit input patterns, six hidden nodes, and one 8-bit output, the implemented hardware neural network makes decisions on a set of input patterns in 11 clock cycles, or less than 200 ns with a 60 MHz clock. The result from the hardware neural computation is well predictable based on the off-line computation. This implementation may be used in level 1 hardware triggers in high energy physics experiments.

  10. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    NASA Astrophysics Data System (ADS)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  11. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 1, Activation measurements and comparison with calculations for spent fuel assembly hardware

    SciTech Connect

    Luksic, A.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1. 5 refs., 4 figs., 21 tabs.

  12. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 3, Calculated activity profiles of spent nuclear fuel assembly hardware for boiling water reactors

    SciTech Connect

    Short, S.M.; Luksic, A.T.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly that is also radioactive and required disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volume 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  13. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 2, Calculated activity profiles of spent nuclear fuel assembly hardware for pressurized water reactors

    SciTech Connect

    Short, S.M.; Luksic, A.T.; Lotz, T.L.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report present a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from Laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  14. Design of Test Support Hardware for Advanced Space Suits

    NASA Technical Reports Server (NTRS)

    Watters, Jeffrey A.; Rhodes, Richard

    2013-01-01

    As a member of the Space Suit Assembly Development Engineering Team, I designed and built test equipment systems to support the development of the next generation of advanced space suits. During space suit testing it is critical to supply the subject with two functions: (1) cooling to remove metabolic heat, and (2) breathing air to pressurize the space suit. The objective of my first project was to design, build, and certify an improved Space Suit Cooling System for manned testing in a 1-G environment. This design had to be portable and supply a minimum cooling rate of 2500 BTU/hr. The Space Suit Cooling System is a robust, portable system that supports very high metabolic rates. It has a highly adjustable cool rate and is equipped with digital instrumentation to monitor the flowrate and critical temperatures. It can supply a variable water temperature down to 34 deg., and it can generate a maximum water flowrate of 2.5 LPM. My next project was to design and build a Breathing Air System that was capable of supply facility air to subjects wearing the Z-2 space suit. The system intakes 150 PSIG breathing air and regulates it to two operating pressures: 4.3 and 8.3 PSIG. It can also provide structural capabilities at 1.5x operating pressure: 6.6 and 13.2 PSIG, respectively. It has instrumentation to monitor flowrate, as well as inlet and outlet pressures. The system has a series of relief valves to fully protect itself in case of regulator failure. Both projects followed a similar design methodology. The first task was to perform research on existing concepts to develop a sufficient background knowledge. Then mathematical models were developed to size components and simulate system performance. Next, mechanical and electrical schematics were generated and presented at Design Reviews. After the systems were approved by the suit team, all the hardware components were specified and procured. The systems were then packaged, fabricated, and thoroughly tested. The next step

  15. A hardware error estimate for floating-point computations

    NASA Astrophysics Data System (ADS)

    Lang, Tomás; Bruguera, Javier D.

    2008-08-01

    We propose a hardware-computed estimate of the roundoff error in floating-point computations. The estimate is computed concurrently with the execution of the program and gives an estimation of the accuracy of the result. The intention is to have a qualitative indication when the accuracy of the result is low. We aim for a simple implementation and a negligible effect on the execution of the program. Large errors due to roundoff occur in some computations, producing inaccurate results. However, usually these large errors occur only for some values of the data, so that the result is accurate in most executions. As a consequence, the computation of an estimate of the error during execution would allow the use of algorithms that produce accurate results most of the time. In contrast, if an error estimate is not available, the solution is to perform an error analysis. However, this analysis is complex or impossible in some cases, and it produces a worst-case error bound. The proposed approach is to keep with each value an estimate of its error, which is computed when the value is produced. This error is the sum of a propagated error, due to the errors of the operands, plus the generated error due to roundoff during the operation. Since roundoff errors are signed values (when rounding to nearest is used), the computation of the error allows for compensation when errors are of different sign. However, since the error estimate is of finite precision, it suffers from similar accuracy problems as any floating-point computation. Moreover, it is not an error bound. Ideally, the estimate should be large when the error is large and small when the error is small. Since this cannot be achieved always with an inexact estimate, we aim at assuring the first property always, and the second most of the time. As a minimum, we aim to produce a qualitative indication of the error. To indicate the accuracy of the value, the most appropriate type of error is the relative error. However

  16. A Common Approach for the Certifying of International Space Station (ISS) Basic Hardware for Ground Safety

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, Paul D.; Trinchero, Jean-Pierre

    2005-01-01

    In order to support the International Space Station, as well as any future long term human missions, vast amounts of logistical-type hardware is required to be processed through the various launch sites. This category consists of such hardware as spare parts, replacement items, and upgraded hardware. The category also includes samples for experiments and consumables. One attribute that all these items have is they are generally non-hazardous, at least to ground personnel. Even though the items are non-hazardous, launch site ground safety has a responsibility for the protection of personnel, the flight hardware, and launch site resources. In order to fulfill this responsibility, the safety organization must have knowledge of the hardware and its operations. Conversely, the hardware providers are entitled to a process that is commensurate with the hazard. Additionally, a common system should be in place that is flexible enough to account for the requirements at all launch sites, so that, the hardware provider need only complete one process for ground safety regardless of the launch site.

  17. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    NASA Astrophysics Data System (ADS)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  18. The Application of Acoustic Measurements and Audio Recordings for Diagnosis of In-Flight Hardware Anomalies

    NASA Technical Reports Server (NTRS)

    Welsh, David; Denham, Samuel; Allen, Christopher

    2011-01-01

    In many cases, an initial symptom of hardware malfunction is unusual or unexpected acoustic noise. Many industries such as automotive, heating and air conditioning, and petro-chemical processing use noise and vibration data along with rotating machinery analysis techniques to identify noise sources and correct hardware defects. The NASA/Johnson Space Center Acoustics Office monitors the acoustic environment of the International Space Station (ISS) through periodic sound level measurement surveys. Trending of the sound level measurement survey results can identify in-flight hardware anomalies. The crew of the ISS also serves as a "detection tool" in identifying unusual hardware noises; in these cases the spectral analysis of audio recordings made on orbit can be used to identify hardware defects that are related to rotating components such as fans, pumps, and compressors. In this paper, three examples of the use of sound level measurements and audio recordings for the diagnosis of in-flight hardware anomalies are discussed: identification of blocked inter-module ventilation (IMV) ducts, diagnosis of abnormal ISS Crew Quarters rack exhaust fan noise, and the identification and replacement of a defective flywheel assembly in the Treadmill with Vibration Isolation (TVIS) hardware. In each of these examples, crew time was saved by identifying the off nominal component or condition that existed and in directing in-flight maintenance activities to address and correct each of these problems.

  19. Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

    NASA Astrophysics Data System (ADS)

    Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

    2016-11-01

    The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

  20. Preparing the hardware of the CMS Electromagnetic Calorimeter control and safety systems for LHC Run 2

    NASA Astrophysics Data System (ADS)

    Holme, O.; Adzic, P.; Di Calafiori, D.; Cirkovic, P.; Dissertori, G.; Djambazov, L.; Jovanovic, D.; Lustermann, W.; Zelepoukine, S.

    2016-01-01

    The Detector Control System of the CMS Electromagnetic Calorimeter has undergone significant improvements during the first LHC Long Shutdown. Based on the experience acquired during the first period of physics data taking of the LHC, several hardware projects were carried out to improve data accuracy, to minimise the impact of failures and to extend remote control possibilities in order to accelerate recovery from problematic situations. This paper outlines the hardware of the detector control and safety systems and explains in detail the requirements, design and commissioning of the new hardware projects.

  1. Power Hardware-in-the-Loop (PHIL) Testing Facility for Distributed Energy Storage (Poster)

    SciTech Connect

    Neubauer.J.; Lundstrom, B.; Simpson, M.; Pratt, A.

    2014-06-01

    The growing deployment of distributed, variable generation and evolving end-user load profiles presents a unique set of challenges to grid operators responsible for providing reliable and high quality electrical service. Mass deployment of distributed energy storage systems (DESS) has the potential to solve many of the associated integration issues while offering reliability and energy security benefits other solutions cannot. However, tools to develop, optimize, and validate DESS control strategies and hardware are in short supply. To fill this gap, NREL has constructed a power hardware-in-the-loop (PHIL) test facility that connects DESS, grid simulator, and load bank hardware to a distribution feeder simulation.

  2. Management of a CFD organization in support of space hardware development

    NASA Technical Reports Server (NTRS)

    Schutzenhofer, L. A.; Mcconnaughey, P. K.; Mcconnaughey, H. V.; Wang, T. S.

    1991-01-01

    The management strategy of NASA-Marshall's CFD branch in support of space hardware development and code validation implements various elements of total quality management. The strategy encompasses (1) a teaming strategy which focuses on the most pertinent problem, (2) quick-turnaround analysis, (3) the evaluation of retrofittable design options through sensitivity analysis, and (4) coordination between the chief engineer and the hardware contractors. Advanced-technology concepts are being addressed via the definition of technology-development projects whose products are transferable to hardware programs and the integration of research activities with industry, government agencies, and universities, on the basis of the 'consortium' concept.

  3. State-of-the-art in CT hardware and scan modes for cardiovascular CT

    PubMed Central

    Halliburton, Sandra; Arbab-Zadeh, Armin; Dey, Damini; Einstein, Andrew J.; Gentry, Ralph; George, Richard T.; Gerber, Thomas; Mahesh, Mahadevappa; Weigold, Wm. Guy

    2013-01-01

    Multidetector row computed tomography (CT) allows noninvasive anatomic and functional imaging of the heart, great vessels, and the coronary arteries. In recent years, there have been several advances in CT hardware, which have expanded the clinical utility of CT for cardiovascular imaging; such advances are ongoing. This review article from the Society of Cardiovascular Computed Tomography (SCCT) Basic and Emerging Sciences and Technology (BEST) Working Group summarizes the technical aspects of current state-of-the-art CT hardware and describes the scan modes this hardware supports for cardiovascular CT imaging. PMID:22551595

  4. State-of-the-art in CT hardware and scan modes for cardiovascular CT.

    PubMed

    Halliburton, Sandra; Arbab-Zadeh, Armin; Dey, Damini; Einstein, Andrew J; Gentry, Ralph; George, Richard T; Gerber, Thomas; Mahesh, Mahadevappa; Weigold, Wm Guy

    2012-01-01

    Multidetector row computed tomography (CT) allows noninvasive anatomic and functional imaging of the heart, great vessels, and coronary arteries. In recent years, there have been several advances in CT hardware, which have expanded the clinical utility of CT for cardiovascular imaging; such advances are ongoing. This review article from the Society of Cardiovascular Computed Tomography Basic and Emerging Sciences and Technology Working Group summarizes the technical aspects of current state-of-the-art CT hardware and describes the scan modes this hardware supports for cardiovascular CT imaging.

  5. FPGA based implementation of hardware diagnostic layer for local trigger of BAC calorimeter for ZEUS detector

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.

    2004-07-01

    The paper describes design and construction of hardware diagnostics layer dedicated to the local trigger of the Backing Calorimeter (BAC). The BAC is a part of the ZEUS experiment in DESY, Hamburg. A general characteristic of the hardware of BAC trigger was presented. The design of hardware diagnostic and calibration sub-systems for BAC trigger bases on the continuous monitoring of consecutive electronic and photonic blocks. The monitoring process is performed via the specialized tests. The standardized diagnostic components were realized in the algorithmic and parameterized description in AHDL. There were presented the implementation results in ALTERA ACEX chips.

  6. Reconfigurable hardware applications on NetFPGA for network monitoring in large area sensor networks

    NASA Astrophysics Data System (ADS)

    Belias, A.; Koutsoumpos, V.; Manolopoulos, K.; Kachris, C.

    2013-10-01

    A valuable functionality for sensor networks, distributed in large volumes is the capability to characterize and analyze the data traffic at wire speed and monitor the data prior to committing to permanent storage. As a demonstrator we use a reconfigurable hardware router for real-time monitoring of data before their transmission to further processing and storage. The reconfigurable hardware router is based on the NetFPGA platform. In this study we report on the hardware implementation to monitor web-based network applications and compare our results with a software based network analyzer.

  7. Implementation of COTs Hardware in Non-Critical Space Applications: A Brief Tutorial

    NASA Technical Reports Server (NTRS)

    Yoder, Geoffrey L.

    2004-01-01

    Approaches used for manned applications include limited items such as CD-players evaluated for safety to high criticality applications where the COTs hardware is evaluated on a case-by-case basis for the application and commensurate screening and qualification testing. COTS hardware is successfully implemented in both the International Space Station and Space Shuttle but requires evaluation and modifications for the application. Screening and qualification of COTs hardware used in critical applications may need to be more extensive and stringent than traditional military screening. Evaluation for: a) Suitability for the application; b) Safety; c) Reliability and maintainability; and d) Workmanship.

  8. Hardware and Software Developments for the Accurate Time-Linked Data Acquisition System

    SciTech Connect

    BERG,DALE E.; RUMSEY,MARK A.; ZAYAS,JOSE R.

    1999-11-09

    Wind-energy researchers at Sandia National Laboratories have developed a new, light-weight, modular data acquisition system capable of acquiring long-term, continuous, multi-channel time-series data from operating wind-turbines. New hardware features have been added to this system to make it more flexible and permit programming via telemetry. User-friendly Windows-based software has been developed for programming the hardware and acquiring, storing, analyzing, and archiving the data. This paper briefly reviews the major components of the system, summarizes the recent hardware enhancements and operating experiences, and discusses the features and capabilities of the software programs that have been developed.

  9. SHI(EL)DS: A Novel Hardware-Based Security Backplane to Enhance Security with Minimal Impact to System Operation

    DTIC Science & Technology

    2008-03-01

    52 PCI Peripheral Component Interface . . . . . . . . . . . . . . . 55 APHID Anomaly Processor in Hardware for...Hardware. 4.3.2.1 APHID . Hart presents an Anomaly Processor in Hardware for Intrusion Detection ( APHID ) which uses co-processing ID to offload the security...Samuel. APHID : Anomoly Processor in Hardware for Intrusion Detection. Master’s thesis, Air Force Institute of Technology, March 2007. 27. Howorth, Roger

  10. Lessons Learned during Thermal Hardware Integration on the Global Precipitation Measurement Satellite

    NASA Technical Reports Server (NTRS)

    Cottingham, Christine; Dwivedi, Vivek H.; Peters, Carlton; Powers, Daniel; Yang, Kan

    2012-01-01

    The Global Precipitation Measurement mission is a joint NASA/JAXA mission scheduled for launch in late 2013. The integration of thermal hardware onto the satellite began in the Fall of 2010 and will continue through the Summer of 2012. The thermal hardware on the mission included several constant conductance heat pipes, heaters, thermostats, thermocouples radiator coatings and blankets. During integration several problems arose and insights were gained that would help future satellite integrations. Also lessons learned from previous missions were implemented with varying degrees of success. These insights can be arranged into three categories. 1) the specification of flight hardware using analysis results and the available mechanical resources. 2) The integration of thermal flight hardware onto the spacecraft, 3) The preparation and implementation of testing the thermal flight via touch tests, resistance measurements and thermal vacuum testing.

  11. Pyroshock Simulation Systems: Are We Correctly Qualifying Flight Hardware for Pyroshock Environments?

    NASA Technical Reports Server (NTRS)

    Kolaini, Ali R.; Nayeri, Reza; Kern, Dennis L.

    2009-01-01

    There are several methods of shock testing that are commonly used by the aerospace industry to qualify flight hardware to pyroshock environments. In some cases the shock results and in particular the shock response spectra computed from these tests were interpreted in such a way as to satisfy the testing requirements and were often considered successful for flight hardware qualification. However, close scrutiny of these acquired shock data suggest gross violation of the pyroshock qualification requirements. There are several issues, both in terms of the shock generation mechanisms and the shock signature acquisition and analysis that have led to improper qualification of flight hardware. In this paper some factors contributing to the misinterpretation of the shock data are reviewed. First, issues with the hardware fixturing and instrumentation that may lead to incorrect shock testing are discussed. Second, issues facing the shock simulation systems and pyrotechnic testing are reviewed. Finally, issues pertaining to the data acquisition and analysis are briefly discussed.

  12. Postflight hardware evaluation 360T025 (RSRM-25, STS-46). Appendix A: Insulation PFORs

    NASA Technical Reports Server (NTRS)

    1993-01-01

    The final Postflight Hardware Evaluation Report 360T025, Appendix A is presented. Insulation Postflight Observation Records (PFOR's) are provided. Postfire insulation, nozzle insert throat diameter measurements, segment internal insulation condition, and segment liner pattern are addressed.

  13. A Pulse-Type Hardware CPG Model for Generation and Transition of Quadruped Locomotion Pattern

    NASA Astrophysics Data System (ADS)

    Hata, Keiko; Sekine, Yoshifumi; Nakabora, Yoshifumi; Saeki, Katsutoshi

    The purpose of our research is to clarify information processing functions of living organisms by neural networks using pulse-type hardware neuron models and applying pulse-type hardware neural networks to engineered models. It is known that locomotion such as walking by a living organism is generated and transited by CPG (Central Pattern Generator) in the central nervous system. We investigate a pulse-type hardware CPG model using coupled oscillator composed of pulse-type hardware neuron models. A CPG model is need to generate and control quadruped locomotion. In this paper, we describe generation and transition of oscillation patterns, corresponding to quadruped locomotion patterns. As a result, it is shown that generation and transition of oscillation patterns are possible by giving external inputs of one pulse to the CPG model.

  14. Open source hardware and software platform for robotics and artificial intelligence applications

    NASA Astrophysics Data System (ADS)

    Liang, S. Ng; Tan, K. O.; Lai Clement, T. H.; Ng, S. K.; Mohammed, A. H. Ali; Mailah, Musa; Azhar Yussof, Wan; Hamedon, Zamzuri; Yussof, Zulkifli

    2016-02-01

    Recent developments in open source hardware and software platforms (Android, Arduino, Linux, OpenCV etc.) have enabled rapid development of previously expensive and sophisticated system within a lower budget and flatter learning curves for developers. Using these platform, we designed and developed a Java-based 3D robotic simulation system, with graph database, which is integrated in online and offline modes with an Android-Arduino based rubbish picking remote control car. The combination of the open source hardware and software system created a flexible and expandable platform for further developments in the future, both in the software and hardware areas, in particular in combination with graph database for artificial intelligence, as well as more sophisticated hardware, such as legged or humanoid robots.

  15. A configurable-hardware document-similarity classifier to detect web attacks.

    SciTech Connect

    Ulmer, Craig D.; Gokhale, Maya

    2010-04-01

    This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to reconfigurable hardware. The TFIDF classifier is used to detect web attacks in HTTP data. In our reconfigurable hardware approach, we design a streaming, real-time classifier by simplifying an existing sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. We have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires two orders of magnitude less memory than the original algorithm. At 166MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.

  16. Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

    NASA Technical Reports Server (NTRS)

    Gwaltney, David A.; Ferguson, Michael I.

    2003-01-01

    Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

  17. EHWPACK: An evolvable hardware environment using the SPICE simulator and the Field Programmable Transistor Array

    NASA Technical Reports Server (NTRS)

    Keymeulen, D.; Klimeck, G.; Zebulum, R.; Stoica, A.; Jin, Y.; Lazaro, C.

    2000-01-01

    This paper describes the EHW development system, a tool that performs the evolutionary synthesis of electronic circuits, using the SPICE simulator and the Field Programmable Transistor Array hardware (FPTA) developed at JPL.

  18. Simulation verification techniques study: Simulation self test hardware design and techniques report

    NASA Technical Reports Server (NTRS)

    1974-01-01

    The final results are presented of the hardware verification task. The basic objectives of the various subtasks are reviewed along with the ground rules under which the overall task was conducted and which impacted the approach taken in deriving techniques for hardware self test. The results of the first subtask and the definition of simulation hardware are presented. The hardware definition is based primarily on a brief review of the simulator configurations anticipated for the shuttle training program. The results of the survey of current self test techniques are presented. The data sources that were considered in the search for current techniques are reviewed, and results of the survey are presented in terms of the specific types of tests that are of interest for training simulator applications. Specifically, these types of tests are readiness tests, fault isolation tests and incipient fault detection techniques. The most applicable techniques were structured into software flows that are then referenced in discussions of techniques for specific subsystems.

  19. 78 FR 18366 - Baldwin Hardware Corporation, a Subsidiary of Spectrum Brands, Formerly Known as a Subsidiary of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-26

    ... Employment and Training Administration Baldwin Hardware Corporation, a Subsidiary of Spectrum Brands... on December 17, 2012, Spectrum Brands purchased Baldwin Hardware, and that the subject firm is now known as Baldwin Hardware Corporation, a Subsidiary of Spectrum Brands, formerly known as a...

  20. 76 FR 11511 - In the Matter of Certain Set-Top Boxes, and Hardware and Software Components Thereof; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-03-02

    ... COMMISSION In the Matter of Certain Set-Top Boxes, and Hardware and Software Components Thereof; Notice of... States after importation of certain set-top boxes, and hardware and software components thereof by reason... importation of certain set-top boxes, and hardware and software components thereof that infringe one or...

  1. 48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title...

  2. 48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title...

  3. 48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title...

  4. CHeCS (Crew Health Care Systems): International Space Station (ISS) Medical Hardware Catalog. Version 10.0

    NASA Technical Reports Server (NTRS)

    2011-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  5. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2015-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  6. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2014-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink(R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  7. Orbiter subsystem hardware/software interaction analysis. Volume 8: Forward reaction control system

    NASA Technical Reports Server (NTRS)

    Becker, D. D.

    1980-01-01

    The results of the orbiter hardware/software interaction analysis for the AFT reaction control system are presented. The interaction between hardware failure modes and software are examined in order to identify associated issues and risks. All orbiter subsystems and interfacing program elements which interact with the orbiter computer flight software are analyzed. The failure modes identified in the subsystem/element failure mode and effects analysis are discussed.

  8. A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

    NASA Technical Reports Server (NTRS)

    Childress-Thompson, Rhonda; Thomas, Dale; Farrington, Phillip

    2016-01-01

    Within the space flight community, reusability has taken center stage as the new buzzword. In order for reusable hardware to be competitive with its expendable counterpart, two major elements must be closely scrutinized. First, recovery and refurbishment costs must be lower than the development and acquisition costs. Additionally, the reliability for reused hardware must remain the same (or nearly the same) as "first use" hardware. Therefore, it is imperative that a systematic approach be established to enhance the development of reusable systems. However, before the decision can be made on whether it is more beneficial to reuse hardware or to replace it, the parameters that are needed to deem hardware worthy of reuse must be identified. For reusable hardware to be successful, the factors that must be considered are reliability (integrity, life, number of uses), operability (maintenance, accessibility), and cost (procurement, retrieval, refurbishment). These three factors are essential to the successful implementation of reusability while enabling the ability to meet performance goals. Past and present strategies and attempts at reuse within the space industry will be examined to identify important attributes of reusability that can be used to evaluate hardware when contemplating reusable versus expendable options. This paper will examine why reuse must be stated as an initial requirement rather than included as an afterthought in the final design. Late in the process, changes in the overall objective/purpose of components typically have adverse effects that potentially negate the benefits. A methodology for assessing the viability of reusing hardware will be presented by using the Space Shuttle Main Engine (SSME) to validate the approach. Because reliability, operability, and costs are key drivers in making this critical decision, they will be used to assess requirements for reuse as applied to components of the SSME.

  9. Transfer molding using soft-flow epoxy in multiwire cable EMR hardware

    NASA Astrophysics Data System (ADS)

    Friebe, M. C.; Wetherill, W. R.

    1981-12-01

    A technique using a soft-flow molding epoxy and a transfer press to fill EMR hardware was found to reduce manufacturing time and scrap yield for shielded multiwire cables. Samples representative of production cables were subjected to mechanical and temperature shock, humidity, and vibration. The results indicated that this epoxy could prevent or reduce EMR hardware collapse from molding pressures during fabrication, thereby reducing scrap and increasing cable production yield.

  10. PNNL OS3300 Alpha/Beta Monitoring System Software and Hardware Operations Manual, Revision 0

    SciTech Connect

    Barnett, J. Matthew; Duchsherer, Cheryl J.; Sisk, Daniel R.; Carter, Gregory L.; Douglas, David D.; Carrell, Dorothy M.

    2006-01-25

    This Pacific Northwest National Laboratory (PNNL) OS3300 Alpha/Beta Monitoring System Software and Hardware Operations Manual describes how to install and operate the software and hardware on a personal computer in conjunction with the EG&G Berthold LB150D continuous air monitor. Included are operational details for the software functions, how to read and use the drop-down menus, how to understand readings and calculations, and how to access the database tables.

  11. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    NASA Technical Reports Server (NTRS)

    Zinnecker, Alicia Mae; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2014-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (40,000 pound force thrust) (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a Simulink (R) library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL

  12. Analysis of systems hardware flown on LDEF. Results of the systems special investigation group

    NASA Technical Reports Server (NTRS)

    Dursch, Harry W.; Spear, W. Steve; Miller, Emmett A.; Bohnhoff-Hlavacek, Gail L.; Edelman, Joel

    1992-01-01

    The Long Duration Exposure Facility (LDEF) was retrieved after spending 69 months in low Earth orbit (LEO). LDEF carried a remarkable variety of mechanical, electrical, thermal, and optical systems, subsystems, and components. The Systems Special Investigation Group (Systems SIG) was formed to investigate the effects of the long duration exposure to LEO on systems related hardware and to coordinate and collate all systems analysis of LDEF hardware. Discussed here is the status of the LDEF Systems SIG investigation through the end of 1991.

  13. Formal detection method for hardware vulnerabilities and Trojan of embedded devices

    NASA Astrophysics Data System (ADS)

    Xie, Xiaodong; Li, Qingbao; Niu, Xiaopeng

    2013-03-01

    As become more widely used, embedded systems security has increasingly gained attention. From the hardware point of view, this paper describes the background of approach to the vulnerabilities and hardware Trojan detection of embedded system, basic ideas and objectives; established the model- ESM (Embedded Systems Model) used to describe embedded systems, provides the encoding method of the ESM system state. Based on this model, this article describes how to use model checking methods to detect vulnerabilities and Trojan existence of an embedded system.

  14. PARAMETERIZED K-MEANS CLUSTERING FOR RAPID HARDWARE DEVELOPMENT TO ACCELERATE ANALYSIS OF SATELLITE DATA

    SciTech Connect

    Leeser, M. ,; Belanov, P.; Estlick, M.; Gokhale, M.; Szymanski, J. J.; Theiler, J. P.

    2001-01-01

    Reconfigurable hardware has successfully been used to obtain speed-up in the implementation of image processing algorithms over purely software based implementations. At HPEC 2000 111, we described research we have done in applying reconfigurable hardware to satellite image data for remote sensing applications. We presented an FPGA implementation of K-means clustering that exhibited two orders of magnitude speedup over a software implementation.

  15. The hardware control system for WEAVE at the William Herschel telescope

    NASA Astrophysics Data System (ADS)

    Delgado Hernandez, Jose M.; Rodríguez-Ramos, Luis F.; Cano Infantes, Diego; Martin, Carlos; Bevil, Craige; Picó, Sergio; Dee, Kevin M.; Abrams, Don Carlos; Lewis, Ian J.; Pragt, Johan; Stuik, Remko; Tromp, Niels; Dalton, Gavin; L. Aguerri, J. Alfonso; Bonifacio, Piercarlo; Middleton, Kevin F.; Trager, Scott C.

    2014-07-01

    This work describes the hardware control system of the Prime Focus Corrector (PFC) and the Spectrograph, two of the main parts of WEAVE, a multi-object fiber spectrograph for the WHT Telescope. The PFC and Spectrograph control system hardware is based on the Allen Bradley's Programmable Automation Controller and its modules. Mechanisms, sensors and actuators of both systems are summarized and their functionality described, showing how they meet the instrument requirements.

  16. Evaluation of accelerated iterative x-ray CT image reconstruction using floating point graphics hardware

    NASA Astrophysics Data System (ADS)

    Kole, J. S.; Beekman, F. J.

    2006-02-01

    Statistical reconstruction methods offer possibilities to improve image quality as compared with analytical methods, but current reconstruction times prohibit routine application in clinical and micro-CT. In particular, for cone-beam x-ray CT, the use of graphics hardware has been proposed to accelerate the forward and back-projection operations, in order to reduce reconstruction times. In the past, wide application of this texture hardware mapping approach was hampered owing to limited intrinsic accuracy. Recently, however, floating point precision has become available in the latest generation commodity graphics cards. In this paper, we utilize this feature to construct a graphics hardware accelerated version of the ordered subset convex reconstruction algorithm. The aims of this paper are (i) to study the impact of using graphics hardware acceleration for statistical reconstruction on the reconstructed image accuracy and (ii) to measure the speed increase one can obtain by using graphics hardware acceleration. We compare the unaccelerated algorithm with the graphics hardware accelerated version, and for the latter we consider two different interpolation techniques. A simulation study of a micro-CT scanner with a mathematical phantom shows that at almost preserved reconstructed image accuracy, speed-ups of a factor 40 to 222 can be achieved, compared with the unaccelerated algorithm, and depending on the phantom and detector sizes. Reconstruction from physical phantom data reconfirms the usability of the accelerated algorithm for practical cases.

  17. Evaluation of accelerated iterative x-ray CT image reconstruction using floating point graphics hardware.

    PubMed

    Kole, J S; Beekman, F J

    2006-02-21

    Statistical reconstruction methods offer possibilities to improve image quality as compared with analytical methods, but current reconstruction times prohibit routine application in clinical and micro-CT. In particular, for cone-beam x-ray CT, the use of graphics hardware has been proposed to accelerate the forward and back-projection operations, in order to reduce reconstruction times. In the past, wide application of this texture hardware mapping approach was hampered owing to limited intrinsic accuracy. Recently, however, floating point precision has become available in the latest generation commodity graphics cards. In this paper, we utilize this feature to construct a graphics hardware accelerated version of the ordered subset convex reconstruction algorithm. The aims of this paper are (i) to study the impact of using graphics hardware acceleration for statistical reconstruction on the reconstructed image accuracy and (ii) to measure the speed increase one can obtain by using graphics hardware acceleration. We compare the unaccelerated algorithm with the graphics hardware accelerated version, and for the latter we consider two different interpolation techniques. A simulation study of a micro-CT scanner with a mathematical phantom shows that at almost preserved reconstructed image accuracy, speed-ups of a factor 40 to 222 can be achieved, compared with the unaccelerated algorithm, and depending on the phantom and detector sizes. Reconstruction from physical phantom data reconfirms the usability of the accelerated algorithm for practical cases.

  18. Benchmarking Model Variants in Development of a Hardware-in-the-Loop Simulation System

    NASA Technical Reports Server (NTRS)

    Aretskin-Hariton, Eliot D.; Zinnecker, Alicia M.; Kratz, Jonathan L.; Culley, Dennis E.; Thomas, George L.

    2016-01-01

    Distributed engine control architecture presents a significant increase in complexity over traditional implementations when viewed from the perspective of system simulation and hardware design and test. Even if the overall function of the control scheme remains the same, the hardware implementation can have a significant effect on the overall system performance due to differences in the creation and flow of data between control elements. A Hardware-in-the-Loop (HIL) simulation system is under development at NASA Glenn Research Center that enables the exploration of these hardware dependent issues. The system is based on, but not limited to, the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k). This paper describes the step-by-step conversion from the self-contained baseline model to the hardware in the loop model, and the validation of each step. As the control model hardware fidelity was improved during HIL system development, benchmarking simulations were performed to verify that engine system performance characteristics remained the same. The results demonstrate the goal of the effort; the new HIL configurations have similar functionality and performance compared to the baseline C-MAPSS40k system.

  19. Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

    NASA Technical Reports Server (NTRS)

    Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

    2014-01-01

    Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-watt radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center (GRC). While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA GRC. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

  20. Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

    NASA Technical Reports Server (NTRS)

    Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

    2015-01-01

    Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

  1. Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

    PubMed

    Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

    2012-06-01

    Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

  2. Cyber-Physical Test Platform for Microgrids: Combining Hardware, Hardware-in-the-Loop, and Network-Simulator-in-the-Loop

    SciTech Connect

    Nelson, Austin; Chakraborty, Sudipta; Wang, Dexin; Singh, Pawan; Cui, Qiang; Yang, Liuqing; Suryanarayanan, Siddharth

    2016-11-14

    This paper presents a cyber-physical testbed, developed to investigate the complex interactions between emerging microgrid technologies such as grid-interactive power sources, control systems, and a wide variety of communication platforms and bandwidths. The cyber-physical testbed consists of three major components for testing and validation: real time models of a distribution feeder model with microgrid assets that are integrated into the National Renewable Energy Laboratory's (NREL) power hardware-in-the-loop (PHIL) platform; real-time capable network-simulator-in-the-loop (NSIL) models; and physical hardware including inverters and a simple system controller. Several load profiles and microgrid configurations were tested to examine the effect on system performance with increasing channel delays and router processing delays in the network simulator. Testing demonstrated that the controller's ability to maintain a target grid import power band was severely diminished with increasing network delays and laid the foundation for future testing of more complex cyber-physical systems.

  3. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    NASA Astrophysics Data System (ADS)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  4. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    NASA Astrophysics Data System (ADS)

    Yeh, Chi-Tsai; Wang, Chun-Hao; Huang, Ing-Jer; Wong, Weng-Fai

    2011-12-01

    Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  5. Determining Temperature Differential to Prevent Hardware Cross-Contamination in a Vacuum Chamber

    NASA Technical Reports Server (NTRS)

    Hughes, David

    2013-01-01

    When contamination-sensitive hardware must be tested in a thermal vacuum chamber, cross-contamination from other hardware present in the chamber, or residue from previous tests, becomes a concern. Typical mitigation strategies involve maintaining the temperature of the critical item above that of other hardware elements at the end of the test. A formula for relating the pumping speed of a chamber, the surface area of contamination sources, and the temperatures of the chamber, source, and contamination-sensitive items has been developed. The formula allows the determination of a temperature threshold about which contamination will not condense on the sensitive items. It defines a parameter alpha that is the fraction given by (contaminant source area)/[chamber pumping speed (time under vacuum) 0.5]. If this parameter is less than 10(exp -6), cross-contamination from common spacecraft material will not occur when the sensitive hardware is at the same temperature as the source of contamination (The chamber is isothermal within 5 C.). Knowing when it becomes safe to have the hardware isothermal permits faster and easier thermal transitions when compared with maintaining an arbitrary temperature differential between parts. Furthermore, the standard temperature differential may not be adequate under some conditions (alpha>10(exp -4)).

  6. Event management for large scale event-driven digital hardware spiking neural networks.

    PubMed

    Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

    2013-09-01

    The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms.

  7. Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

    NASA Technical Reports Server (NTRS)

    Moore, J. Strother

    1992-01-01

    Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

  8. A historical survey of algorithms and hardware architectures for neural-inspired and neuromorphic computing applications

    DOE PAGES

    James, Conrad D.; Aimone, James B.; Miner, Nadine E.; ...

    2017-01-04

    In this study, biological neural networks continue to inspire new developments in algorithms and microelectronic hardware to solve challenging data processing and classification problems. Here in this research, we survey the history of neural-inspired and neuromorphic computing in order to examine the complex and intertwined trajectories of the mathematical theory and hardware developed in this field. Early research focused on adapting existing hardware to emulate the pattern recognition capabilities of living organisms. Contributions from psychologists, mathematicians, engineers, neuroscientists, and other professions were crucial to maturing the field from narrowly-tailored demonstrations to more generalizable systems capable of addressing difficult problem classesmore » such as object detection and speech recognition. Algorithms that leverage fundamental principles found in neuroscience such as hierarchical structure, temporal integration, and robustness to error have been developed, and some of these approaches are achieving world-leading performance on particular data classification tasks. Additionally, novel microelectronic hardware is being developed to perform logic and to serve as memory in neuromorphic computing systems with optimized system integration and improved energy efficiency. Key to such advancements was the incorporation of new discoveries in neuroscience research, the transition away from strict structural replication and towards the functional replication of neural systems, and the use of mathematical theory frameworks to guide algorithm and hardware developments.« less

  9. A historical survey of algorithms and hardware architectures for neural-inspired and neuromorphic computing applications

    SciTech Connect

    James, Conrad D.; Aimone, James B.; Miner, Nadine E.; Vineyard, Craig M.; Rothganger, Fredrick H.; Carlson, Kristofor D.; Mulder, Samuel A.; Draelos, Timothy J.; Faust, Aleksandra; Marinella, Matthew J.; Naegle, John H.; Plimpton, Steven J.

    2017-01-01

    Biological neural networks continue to inspire new developments in algorithms and microelectronic hardware to solve challenging data processing and classification problems. Here in this research, we survey the history of neural-inspired and neuromorphic computing in order to examine the complex and intertwined trajectories of the mathematical theory and hardware developed in this field. Early research focused on adapting existing hardware to emulate the pattern recognition capabilities of living organisms. Contributions from psychologists, mathematicians, engineers, neuroscientists, and other professions were crucial to maturing the field from narrowly-tailored demonstrations to more generalizable systems capable of addressing difficult problem classes such as object detection and speech recognition. Algorithms that leverage fundamental principles found in neuroscience such as hierarchical structure, temporal integration, and robustness to error have been developed, and some of these approaches are achieving world-leading performance on particular data classification tasks. Additionally, novel microelectronic hardware is being developed to perform logic and to serve as memory in neuromorphic computing systems with optimized system integration and improved energy efficiency. Key to such advancements was the incorporation of new discoveries in neuroscience research, the transition away from strict structural replication and towards the functional replication of neural systems, and the use of mathematical theory frameworks to guide algorithm and hardware developments.

  10. Current trends in hardware and software for brain-computer interfaces (BCIs).

    PubMed

    Brunner, P; Bianchi, L; Guger, C; Cincotti, F; Schalk, G

    2011-04-01

    A brain-computer interface (BCI) provides a non-muscular communication channel to people with and without disabilities. BCI devices consist of hardware and software. BCI hardware records signals from the brain, either invasively or non-invasively, using a series of device components. BCI software then translates these signals into device output commands and provides feedback. One may categorize different types of BCI applications into the following four categories: basic research, clinical/translational research, consumer products, and emerging applications. These four categories use BCI hardware and software, but have different sets of requirements. For example, while basic research needs to explore a wide range of system configurations, and thus requires a wide range of hardware and software capabilities, applications in the other three categories may be designed for relatively narrow purposes and thus may only need a very limited subset of capabilities. This paper summarizes technical aspects for each of these four categories of BCI applications. The results indicate that BCI technology is in transition from isolated demonstrations to systematic research and commercial development. This process requires several multidisciplinary efforts, including the development of better integrated and more robust BCI hardware and software, the definition of standardized interfaces, and the development of certification, dissemination and reimbursement procedures.

  11. Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

    NASA Technical Reports Server (NTRS)

    1990-01-01

    This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

  12. Co-design of software and hardware to implement remote sensing algorithms

    SciTech Connect

    Theiler, J. P.; Frigo, J.; Gokhale, M.; Szymanski, J. J.

    2001-01-01

    Both for offline searches through large data archives and for onboard computation at the sensor head, there is a growing need for ever-more rapid processing of remote sensing data. For many algorithms of use in remote sensing, the bulk of the processing takes place in an 'inner loop' with a large number of simple operations. For these algorithms, dramatic speedups can often be obtained with specialized hardware. The difficulty and expense of digital design continues to limit applicability of this approach, but the development of new design tools is making this approach more feasible, and some notable successes have been reported. On the other hand, it is often the case that processing can also be accelerated by adopting a more sophisticated algorithm design. Unfortunately, a more sophisticated algorithm is much harder to implement in hardware, so these approaches are often at odds with each other. With careful planning, however, it is sometimes possible to combine software and hardware design in such a way that each complements the other, and the final implementation achieves speedup that would not have been possible with a hardware-only or a software-only solution. We will in particular discuss the co-design of software and hardware to achieve substantial speedup of algorithms for multispectral image segmentation and for endmember identification.

  13. Modulation of respiratory sinus arrhythmia in rats with central pattern generator hardware.

    PubMed

    Nogaret, Alain; Zhao, Le; Moraes, Davi J A; Paton, Julian F R

    2013-01-15

    We report on the modulation of respiratory sinus arrhythmia in rats with central pattern generator (CPG) hardware made of silicon neurons. The neurons are made to compete through mutually inhibitory synapses to provide timed electrical oscillations that stimulate the peripheral end of vagus nerve at specific points of the respiratory cycle: the inspiratory phase (φ(1)), the early expiratory phase (φ(2)) and the late expiratory phase (φ(3)). In this way the CPG hardware mimics the neuron populations in the brainstem which through connections with cardiac vagal motoneurones control respiratory sinus arrhythmia (RSA). Here, we time the output of the CPG hardware from the phrenic nerve activity recorded from rats while monitoring heart rate changes evoked by vagal nerve stimulation (derived from ECG) controlled by the CPG. This neuroelectric stimulation has the effect of reducing the heart rate and increasing the arterial pressure. The artificially induced RSA strongly depends on the timing of pulses within the breathing cycle. It is strongest when the vagus nerve is stimulated during the inspiratory phase (φ(1)) or the early expiratory phase (φ(2)) in which case the heart rate slows by 50% of the normal rate. Heart rate modulation is less when the same exact stimulus is applied during the late expiratory phase (φ(3)). These trials show that neurostimulation by CPG hardware can augment respiratory sinus arrhythmia. The CPG hardware technology opens a new line of therapeutic possibilities for prosthetic devices that restore RSA in patients where respiratory-cardiac coupling has been lost.

  14. Performance/price estimates for cortex-scale hardware: a design space exploration.

    PubMed

    Zaveri, Mazad S; Hammerstrom, Dan

    2011-04-01

    In this paper, we revisit the concept of virtualization. Virtualization is useful for understanding and investigating the performance/price and other trade-offs related to the hardware design space. Moreover, it is perhaps the most important aspect of a hardware design space exploration. Such a design space exploration is a necessary part of the study of hardware architectures for large-scale computational models for intelligent computing, including AI, Bayesian, bio-inspired and neural models. A methodical exploration is needed to identify potentially interesting regions in the design space, and to assess the relative performance/price points of these implementations. As an example, in this paper we investigate the performance/price of (digital and mixed-signal) CMOS and hypothetical CMOL (nanogrid) technology based hardware implementations of human cortex-scale spiking neural systems. Through this analysis, and the resulting performance/price points, we demonstrate, in general, the importance of virtualization, and of doing these kinds of design space explorations. The specific results suggest that hybrid nanotechnology such as CMOL is a promising candidate to implement very large-scale spiking neural systems, providing a more efficient utilization of the density and storage benefits of emerging nano-scale technologies. In general, we believe that the study of such hypothetical designs/architectures will guide the neuromorphic hardware community towards building large-scale systems, and help guide research trends in intelligent computing, and computer engineering.

  15. PC-based PCM (Pulse Code Modulation) telemetry data reduction system hardware

    SciTech Connect

    Simms, D.A.; Butterfield, C.P.

    1990-02-01

    The Solar Energy Research Institute's (SERI) Wind Research Program is using pulse code modulation (PCM) telemetry systems to study horizontal-axis wind turbines. SERI has developed a low-cost PC-based PCM data acquisition system to facilitate quick PCM data analysis in the field. The SERI PC-PCM system consists of AT-compatible hardware boards for decoding and combining PCM data streams and DOS software for control and management of data acquisition. Up to four boards can be installed in a single PC, providing the capability to combine data from four PCM streams direct to disk or memory. This paper describes the SERI PC-PCM system hardware, focusing on the practicality of PC-based PCM data reduction. A related paper highlights our comprehensive PCM data management software program which can be used in conjunction with this hardware to provide full quick-look'' data processing and display. The PC-PCM hardware boards support a subset of the Inter-Range Instrumentation Group (IRIG) PCM standard, designed to synchronize and decommutate NRZ or Bi-Phase L PCM streams in the range of 1 to 800 Kbits/sec at 8 to 12 bits per word and 2 to 64 words per frame. Multiple PCM streams (at various rates) can be combined and interleaved into a contiguous digital time series. Maximum data throughput depends on characteristics of the PC hardware, such as CPU rate and disk access speed. 7 refs., 6 figs., 4 tabs.

  16. Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

    NASA Technical Reports Server (NTRS)

    Tobbe, Patrick; Matras, Alex; Walker, David; Wilson, Heath; Fulton, Chris; Alday, Nathan; Betts, Kevin; Hughes, Ryan; Turbe, Michael

    2009-01-01

    The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented.

  17. Real-time IP-hologram conversion hardware based on floating point DSPs

    NASA Astrophysics Data System (ADS)

    Oi, Ryutaro; Mishina, Tomoyuki; Yamamoto, Kenji; Okui, Makoto

    2009-02-01

    Holography is a 3-D display method that fully satisfies the visual characteristics of the human eye. However, the hologram must be developed in a darkroom under laser illumination. We attempted hologram generation under white light by adopting an integral photography (IP) technique as the input. In this research, we developed a hardware converter to convert IP input (with 120×66 elemental images) to a hologram with high definition television (HDTV) resolution (approximately 2 million pixels). This conversion could be carried out in real time. In this conversion method, each elemental image can be independently extracted and processed. Our hardware contains twenty 300-MHz floating-point digital signal processors (DSPs) operating in parallel. We verified real-time conversion operations by the implemented hardware.

  18. Data Applicability of Heritage and New Hardware for Launch Vehicle System Reliability Models

    NASA Technical Reports Server (NTRS)

    Al Hassan Mohammad; Novack, Steven

    2015-01-01

    Many launch vehicle systems are designed and developed using heritage and new hardware. In most cases, the heritage hardware undergoes modifications to fit new functional system requirements, impacting the failure rates and, ultimately, the reliability data. New hardware, which lacks historical data, is often compared to like systems when estimating failure rates. Some qualification of applicability for the data source to the current system should be made. Accurately characterizing the reliability data applicability and quality under these circumstances is crucial to developing model estimations that support confident decisions on design changes and trade studies. This presentation will demonstrate a data-source classification method that ranks reliability data according to applicability and quality criteria to a new launch vehicle. This method accounts for similarities/dissimilarities in source and applicability, as well as operating environments like vibrations, acoustic regime, and shock. This classification approach will be followed by uncertainty-importance routines to assess the need for additional data to reduce uncertainty.

  19. High-performance image reconstruction in fluorescence tomography on desktop computers and graphics hardware.

    PubMed

    Freiberger, Manuel; Egger, Herbert; Liebmann, Manfred; Scharfetter, Hermann

    2011-11-01

    Image reconstruction in fluorescence optical tomography is a three-dimensional nonlinear ill-posed problem governed by a system of partial differential equations. In this paper we demonstrate that a combination of state of the art numerical algorithms and a careful hardware optimized implementation allows to solve this large-scale inverse problem in a few seconds on standard desktop PCs with modern graphics hardware. In particular, we present methods to solve not only the forward but also the non-linear inverse problem by massively parallel programming on graphics processors. A comparison of optimized CPU and GPU implementations shows that the reconstruction can be accelerated by factors of about 15 through the use of the graphics hardware without compromising the accuracy in the reconstructed images.

  20. Hardware Design and Implementation of IP-over-1394 Protocol Stack and Its Evaluation

    NASA Astrophysics Data System (ADS)

    Abe, Kôki; Hassan, Mohd Yusairi Bin Abu

    This paper describes the hardware design of core functions of the Internet protocol IP over IEEE1394 interface (IP over 1394) and its implementation on an FPGA. The design was evaluated by counting the number of FPGA logic elements required for the implementation. Using a system clock of 49.152MHz, we verified that packets sent from an application on top of the protocol stack were correctly received by the other protocol stack via the IEEE1394 port at a transfer rate of 400 Mbps. We also verified the communication behaviors of the design with an isochronous resource manager to reserve a channel prior to data transmissions. The hardware cost of the core IP layer was less than that of the link layer. The evaluation results will help the IP-over-1394 designers explore quantitatively various spectrum of the software/hardware design alternatives.