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Sample records for high speed cmos

  1. CMOS Image Sensors for High Speed Applications.

    PubMed

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  2. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  3. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  4. High speed CMOS/SOS standard cell notebook

    NASA Technical Reports Server (NTRS)

    1978-01-01

    The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

  5. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  6. High-speed CMOS optical communication using silicon light emitters

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Nell, Ilse J.; Bogalecki, Alfons W.; Rademeyer, Pieter

    2011-01-01

    The idea of moving CMOS into the mainstream optical domain remains an attractive one. In this paper we discuss our recent advances towards a complete silicon optical communication solution. We prove that transmission of baseband data at multiples of megabits per second rates are possible using improved silicon light sources in a completely native standard CMOS process with no post processing. The CMOS die is aligned to a fiber end and the light sources are directly modulated. An optical signal is generated and transmitted to a silicon Avalanche Photodiode (APD) module, received and recovered. Signal detectability is proven through eye diagram measurements. The results show an improvement of more than tenfold over our previous results, also demonstrating the fastest optical communication from standard CMOS light sources. This paper presents an all silicon optical data link capable of 2 Mb/s at a bit error rate of 10-10, or alternatively 1 Mb/s at a bit error rate of 10-14. As the devices are not operating at their intrinsic switching speed limit, we believe that even higher transmission rates are possible with complete integration of all components in CMOS.

  7. High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Choi, Pyung; Shin, Jang-Kyoo

    2015-03-01

    In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

  8. High-speed bipolar phototransistors in a 180 nm CMOS process.

    PubMed

    Kostov, P; Gaberl, W; Zimmermann, H

    2013-03-01

    Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm(2) and 100×100 μm(2). Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p(+) wafer with a p(-) epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

  9. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  10. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  11. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    NASA Astrophysics Data System (ADS)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  12. High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

    NASA Astrophysics Data System (ADS)

    Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

    2017-02-01

    Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

  13. A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixels Using Pinned Diodes

    NASA Astrophysics Data System (ADS)

    Yasutomi, Keita; Tamura, Toshihiro; Furuta, Masanori; Itoh, Shinya; Kawahito, Shoji

    This paper describes a high-speed CMOS image sensor with a new type of global electronic shutter pixel. A global electronic shutter is necessary for imaging fast-moving objects without motion blur or distortion. The proposed pixel has two potential wells with pinned diode structure for two-stage charge transfer that enables a global electronic shuttering and reset noise canceling. A prototype high-speed image sensor fabricated in 0.18μm standard CMOS image sensor process consists of the proposed pixel array, 12-bit column-parallel cyclic ADC arrays and 192-channel digital outputs. The sensor achieves a good linearity at low-light intensity, demonstrating the perfect charge transfer between two pinned diodes. The input referred noise of the proposed pixel is measured to be 6.3 e-.

  14. High-speed camera based on a CMOS active pixel sensor

    NASA Astrophysics Data System (ADS)

    Bloss, Hans S.; Ernst, Juergen D.; Firla, Heidrun; Schmoelz, Sybille C.; Gick, Stephan K.; Lauxtermann, Stefan C.

    2000-02-01

    Standard CMOS technologies offer great flexibility in the design of image sensors, which is a big advantage especially for high framerate system. For this application we have integrated an active pixel sensor with 256 X 256 pixel using a standard 0.5 micrometers CMOS technologies. With 16 analog outputs and a clockrate of 25-30 MHz per output, a continuous framerate of more than 50000 Hz is achieved. A global synchronous shutter is provided, but it required a more complex pixel circuit of five transistors and a special pixel layout to get a good optical fill factor. The active area of the photodiode is 9 X 9 micrometers . These square diodes are arranged in a chess pattern, while the remaining space is used for the electronic circuit. FIll factor is nearly 50 percent. The sensor is embedded in a high-speed camera system with 16 ADCs, 256Mbyte dynamic RAM, FPGAs for high-speed real time image processing, and a PC for user interface, data archive and network operation. Fixed pattern noise, which is always a problem of CMOS sensor, and the mismatching of the 16 analog channels is removed by a pixelwise gain-offset correction. After this, the chess pattern requires a reconstruction of all the 'missing' pixels, which can be done by a special edge sensitive algorithm. So a high quality 512 X 256 image with low remaining noise can be displayed. Sensor, architecture and processing are also suitable for color imaging.

  15. Speed optimized linear-mode high-voltage CMOS avalanche photodiodes with high responsivity.

    PubMed

    Enne, R; Steindl, B; Zimmermann, H

    2015-10-01

    Two different speed optimized avalanche photodiodes (APDs) fabricated in a 0.35 μm standard high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) process with a high unamplified responsivity (avalanche gain M=1) of 0.41 A/W at 670 nm are presented. These APDs differ regarding the effective doping of the deep p well (90% and 75%), using lateral well modulation doping. Compared to the -3  dB bandwidth of the unmodulated APD with 100% doping (850 MHz), this optimization leads to an improved bandwidth of 1.02 and 1.25 GHz for the 75% APD and 90% APD, respectively, both at a gain of M=50.

  16. A high-speed lateral PIN polysilicon photodiode on standard bulk CMOS process

    NASA Astrophysics Data System (ADS)

    Zou, Wanghui; Xia, Yu; Chen, Diping; Zeng, Yun

    2017-03-01

    This paper reports a lateral PIN polysilicon photodiode on standard bulk complementary metal-oxidesemiconductor (CMOS) process for monolithically integrated high-speed optoelectronic integrated circuits (OEIC). A nominal undoped polysilicon as the photodetection area is intentionally created without introducing any process modification. With the device area of 50 × 50 μm2, a measured responsivity of 46 mA/W and a quantum efficiency of 11% were observed under the reverse voltage of 10 V and the wavelength of 520 nm. A compact equivalent circuit model for the proposed lateral photodiode is built to analyze the frequency response, and a bandwidth of over 20 GHz was obtained from the measured data, which is to the best of our knowledge the largest bandwidth ever reported based on standard bulk CMOS process.

  17. A 2.2M CMOS image sensor for high-speed machine vision applications

    NASA Astrophysics Data System (ADS)

    Wang, Xinyang; Bogaerts, Jan; Vanhorebeek, Guido; Ruythoren, Koen; Ceulemans, Bart; Lepage, Gérald; Willems, Pieter; Meynants, Guy

    2010-01-01

    This paper describes a 2.2 Megapixel CMOS image sensor made in 0.18 μm CMOS process for high-speed machine vision applications. The sensor runs at 340 fps with digital output using 16 LVDS channels at 480MHz. The pixel array counts 2048x1088 pixels with a 5.5um pitch. The unique pixel architecture supports a true correlated double sampling, thus yields a noise level as low as 13 e- and a pixel parasitic light sensitivity (PLS) of 1/60 000. The sensitivity of the sensor is measured to be 4.64 Vlux.s and the pixel full well charge is 18k e-.

  18. A high speed, low power consumption LVDS interface for CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Shi, Zhan; Tang, Zhenan; Tian, Yong; Pham, Hung; Valin, Isabelle; Jaaskelainen, Kimmo

    2015-01-01

    The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-μm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW.

  19. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    PubMed

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  20. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

    PubMed Central

    Jeong, Gyu-Seob

    2017-01-01

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies. PMID:28841154

  1. Characterization of a fast CMOS imaging sensor for high-speed laser detection

    NASA Astrophysics Data System (ADS)

    Casadei, Bruno; Le Normand, J. P.; Hu, Y.; Cunin, Bernard

    2003-07-01

    CMOS active pixel sensors (APS) have performances competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost and miniaturization. In this paper, we present characterization of a fast CMOS APS used in an imager for high-speed laser detections, which can replace the streak cameras. It produces the intensity information in function of one spatial dimension and time [I = f(x,t)] from one frame in two spatial dimensions. The time information is obtained for the first prototype camera to delay successively the integration phase in each pixel of the same row. The different noise sources of the APS sensors such as shot noise due to the photo sensor, the thermal noise and flicker noise due to the readout transistors and the photon shot noise are presented to determine the fundamental limits on image sensor. The first prototype FAMOSI (FAst MOS Imager) is composed of 64 x 64 active pixels. The simulation and experimental results show that a conversion gain of 6.73 +/- 0.25 μV/e- has been obtained with a noise level of 87 +/- 3e- rms. The power consumption of the chip is 25 mW at 50 images/sec.

  2. Design and characterization of high-speed CMOS pseudo-LVDS transceivers

    NASA Astrophysics Data System (ADS)

    Kondratenko, S. V.

    2016-02-01

    High-speed transceiver for on-board systems of data collection and processing need to meet additional requirements, such as low power consumption and increased radiation hardness. It is therefore necessary to compare and search for alternative variants of transceivers on the physical layer, where high transfer speed is not achieved at the cost of a significant increase in power consumption or a limitation of transmission distance by the size of a printed circuit board. For on-board applications, it is also necessary to solve the problem of increasing the radiation hardness without going to expensive types of technology. In this paper, we studied some variants of implementation of pseudo-LVDS transceivers and analyzed their achievable quantitative characteristics. According to the results of calculations and analysis of the literature, specialized transceivers of this type, intended for the manufacture or manufactured according to the bulk CMOS technology processes in the range of 250-80 nm, can provide data speeds up to 6 Gbps at a specific power consumption of less than 4 mW/Gbps.

  3. High-speed laser Doppler perfusion imaging using an integrating CMOS image sensor.

    PubMed

    Serov, Alexandre; Lasser, Theo

    2005-08-22

    This paper describes the design and the performance of a new high-speed laser Doppler imaging system for monitoring blood flow over an area of tissue. The new imager delivers high-resolution flow images (256x256 pixels) every 2 to 10 seconds, depending on the number of points in the acquired time-domain signal (32-512 points). This new imaging modality utilizes a digital integrating CMOS image sensor to detect Doppler signals in a plurality of points over the area illuminated by a divergent laser beam of a uniform intensity profile. The integrating property of the detector improves the signal-to-noise ratio of the measurements, which results in high-quality flow images. We made a series of measurements in vitro to test the performance of the system in terms of bandwidth, SNR, etc. Subsequently we give some examples of flow-related images measured on human skin, thus demonstrating the performance of the imager in vivo. The perspectives for future implementations of the imager for clinical and physiological applications are discussed.

  4. A high sensitivity 20Mfps CMOS image sensor with readout speed of 1Tpixel/sec for visualization of ultra-high speed phenomena

    NASA Astrophysics Data System (ADS)

    Kuroda, R.; Sugawa, S.

    2017-02-01

    Ultra-high speed (UHS) CMOS image sensors with on-chop analog memories placed on the periphery of pixel array for the visualization of UHS phenomena are overviewed in this paper. The developed UHS CMOS image sensors consist of 400H×256V pixels and 128 memories/pixel, and the readout speed of 1Tpixel/sec is obtained, leading to 10 Mfps full resolution video capturing with consecutive 128 frames, and 20 Mfps half resolution video capturing with consecutive 256 frames. The first development model has been employed in the high speed video camera and put in practical use in 2012. By the development of dedicated process technologies, photosensitivity improvement and power consumption reduction were simultaneously achieved, and the performance improved version has been utilized in the commercialized high-speed video camera since 2015 that offers 10 Mfps with ISO16,000 photosensitivity. Due to the improved photosensitivity, clear images can be captured and analyzed even under low light condition, such as under a microscope as well as capturing of UHS light emission phenomena.

  5. Pixel-based characterisation of CMOS high-speed camera systems

    NASA Astrophysics Data System (ADS)

    Weber, V.; Brübach, J.; Gordon, R. L.; Dreizler, A.

    2011-05-01

    Quantifying high-repetition rate laser diagnostic techniques for measuring scalars in turbulent combustion relies on a complete description of the relationship between detected photons and the signal produced by the detector. CMOS-chip based cameras are becoming an accepted tool for capturing high frame rate cinematographic sequences for laser-based techniques such as Particle Image Velocimetry (PIV) and Planar Laser Induced Fluorescence (PLIF) and can be used with thermographic phosphors to determine surface temperatures. At low repetition rates, imaging techniques have benefitted from significant developments in the quality of CCD-based camera systems, particularly with the uniformity of pixel response and minimal non-linearities in the photon-to-signal conversion. The state of the art in CMOS technology displays a significant number of technical aspects that must be accounted for before these detectors can be used for quantitative diagnostics. This paper addresses these issues.

  6. High-speed charge transfer pinned-photodiode for a CMOS time-of-flight range image sensor

    NASA Astrophysics Data System (ADS)

    Takeshita, Hiroaki; Sawada, Tomonari; Iida, Tetsuya; Yasutomi, Keita; Kawahito, Shoji

    2010-01-01

    This paper presents a structure and method of range calculation for CMOS time-of-flight(TOF) range image sensors using pinned photodiodes. In the proposed method, a LED light with short pulse width and small duty ratio irradiates the objects and a back-reflected light is received by the CMOS TOF range imager.Each pixel has a pinned photodiode optimized for high speed charge transfer and unwanted charge draining. In TOF range image sensors, high speed charge transfer from the light receiving part to a charge accumulator is essential.It was found that the fastest charge transfer can be realized when the lateral electric field along the axis of charge transfer is constant and this conditon is met when the shape of the diode exactly follows the relationship between the fully-depleted potential and width. A TOF range imager prototype is designed and implemented with 0.18um CMOS image sensor technology with pinned photodiode 4transistor(T) pixels. The measurement results show that the charge transfer time is a few ns from the pinned photodiode to a charge accumulator.

  7. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

    PubMed

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-11-06

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  8. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    PubMed Central

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  9. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    NASA Technical Reports Server (NTRS)

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  10. LGSD/NGSD: high speed visible CMOS imagers for E-ELT adaptive optics

    NASA Astrophysics Data System (ADS)

    Downing, Mark; Kolb, Johann; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Fryer, Martin; Gach, Jean-Luc; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Pike, Andrew; Reyes, Javier; Stadler, Eric; Swift, Nick

    2016-08-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the European Extremely Large Telescope (E-ELT) has been identified as the Large Visible Laser/Natural Guide Star AO Wavefront Sensing (WFS) detector. The combination of large format, 1600x1600 pixels to finely sample the wavefront and the spot elongation of laser guide stars (LGS), fast frame rate of 700 frames per second (fps), low read noise (< 3e-), and high QE (> 90%) makes the development of this device extremely challenging. Results of design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most suitable technology. Two generations of the CMOS Imager are planned: a) a smaller `pioneering' device of > 800x800 pixels capable of meeting first light needs of the E-ELT. The NGSD, the topic of this paper, is the first iteration of this device; b) the larger full sized device called LGSD. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). Results of comprehensive tests performed both at e2v and ESO are presented that validate the choice of CMOS Imager as the correct technology for the E-ELT Large Visible WFS Detector. These results along with plans for a second iteration to improve two issues of hot pixels and cross-talk are presented.

  11. LGSD/NGSD: high speed optical CMOS imagers for E-ELT adaptive optics

    NASA Astrophysics Data System (ADS)

    Downing, Mark; Kolb, Johann; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Payne, Andrew; Pike, Andrew; Reyes, Javier; Simpson, Robert; Stadler, Eric; Stent, Jeremy; Swift, Nick

    2014-07-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the optical Laser/Natural Guide Star WFS detector. The combination of large format, 1760×1680 pixels to finely sample the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 frames per second (fps), low read noise (< 3e-), and high QE (> 90%) makes the development of this device extremely challenging. Design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most likely technology to succeed. Two generations of the CMOS Imager are being developed: a) the already designed and manufactured NGSD (Natural Guide Star Detector), a quarter-sized pioneering device of 880×840 pixels capable of meeting first light needs of the E-ELT; b) the LGSD (Laser Guide Star Detector), the larger full size device. The detailed design is presented including the approach of using massive parallelism (70,400 ADCs) to achieve the low read noise at high pixel rates of ~3 Gpixel/s and the 88 channel LVDS 220Mbps serial interface to get the data off-chip. To enable read noise closer to the goal of 1e- to be achieved, a split wafer run has allowed the NGSD to be manufactured in the more speculative, but much lower read noise, Ultra Low Threshold Transistors in the unit cell. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). First results of tests performed both at e2v and ESO are presented.

  12. A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

    NASA Technical Reports Server (NTRS)

    Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

    2004-01-01

    A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

  13. A Comparative Study of Heavy Ion and Proton Induced Bit Error Sensitivity and Complex Burst Error Modes in Commercially Available High Speed SiGe BiCMOS

    NASA Technical Reports Server (NTRS)

    Marshall, Paul; Carts, Marty; Campbell, Art; Reed, Robert; Ladbury, Ray; Seidleck, Christina; Currie, Steve; Riggs, Pam; Fritz, Karl; Randall, Barb

    2004-01-01

    A viewgraph presentation that reviews recent SiGe bit error test data for different commercially available high speed SiGe BiCMOS chips that were subjected to various levels of heavy ion and proton radiation. Results for the tested chips at different operating speeds are displayed in line graphs.

  14. High speed wide field CMOS camera for Transneptunian Automatic Occultation Survey

    NASA Astrophysics Data System (ADS)

    Wang, Shiang-Yu; Geary, John C.; Amato, Stephen M.; Hu, Yen-Sang; Ling, Hung-Hsu; Huang, Pin-Jie; Furesz, Gabor; Chen, Hsin-Yo; Chang, Yin-Chang; Szentgyorgyi, Andrew; Lehner, Matthew; Norton, Timothy

    2014-08-01

    The Transneptunian Automated Occultation Survey (TAOS II) is a three robotic telescope project to detect the stellar occultation events generated by Trans Neptunian Objects (TNOs). TAOS II project aims to monitor about 10000 stars simultaneously at 20Hz to enable statistically significant event rate. The TAOS II camera is designed to cover the 1.7 degree diameter field of view (FoV) of the 1.3m telescope with 10 mosaic 4.5kx2k CMOS sensors. The new CMOS sensor has a back illumination thinned structure and high sensitivity to provide similar performance to that of the backillumination thinned CCDs. The sensor provides two parallel and eight serial decoders so the region of interests can be addressed and read out separately through different output channels efficiently. The pixel scale is about 0.6"/pix with the 16μm pixels. The sensors, mounted on a single Invar plate, are cooled to the operation temperature of about 200K by a cryogenic cooler. The Invar plate is connected to the dewar body through a supporting ring with three G10 bipods. The deformation of the cold plate is less than 10μm to ensure the sensor surface is always within ±40μm of focus range. The control electronics consists of analog part and a Xilinx FPGA based digital circuit. For each field star, 8×8 pixels box will be readout. The pixel rate for each channel is about 1Mpix/s and the total pixel rate for each camera is about 80Mpix/s. The FPGA module will calculate the total flux and also the centroid coordinates for every field star in each exposure.

  15. Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

    NASA Astrophysics Data System (ADS)

    Liu, Hui-Min; Zhang, Xiao-Xing; Dai, Yu-Jie; Lv, Ying-Jie

    2011-09-01

    Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.

  16. High Speed, Radiation Hard CMOS Pixel Sensors for Transmission Electron Microscopy

    NASA Astrophysics Data System (ADS)

    Contarato, Devis; Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad

    CMOS monolithic active pixel sensors are currently being established as the technology of choice for new generation digital imaging systems in Transmission Electron Microscopy (TEM). A careful sensor design that couples μm-level pixel pitches with high frame rate readout and radiation hardness to very high electron doses enables the fabrication of direct electron detectors that are quickly revolutionizing high-resolution TEM imaging in material science and molecular biology. This paper will review the principal characteristics of this novel technology and its advantages over conventional, optically-coupled cameras, and retrace the sensor development driven by the Transmission Electron Aberration corrected Microscope (TEAM) project at the LBNL National Center for Electron Microscopy (NCEM), illustrating in particular the imaging capabilities enabled by single electron detection at high frame rate. Further, the presentation will report on the translation of the TEAM technology to a finer feature size process, resulting in a sensor with higher spatial resolution and superior radiation tolerance currently serving as the baseline for a commercial camera system.

  17. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier

    PubMed Central

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-01-01

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed. PMID:27089339

  18. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

    PubMed

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-04-13

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  19. Lateral drift-field photodiode for low noise, high-speed, large photoactive-area CMOS imaging applications

    NASA Astrophysics Data System (ADS)

    Durini, Daniel; Spickermann, Andreas; Mahdi, Rana; Brockherde, Werner; Vogt, Holger; Grabmaier, Anton; Hosticka, Bedrich J.

    2010-12-01

    In this work a theoretical concept and simulations are presented for a novel lateral drift-field photodetector pixel to be fabricated in a 0.35 μm CMOS process. The proposed pixel consists of a specially designed n-well with a non-uniform lateral doping profile that follows a square-root spatial dependence. "Buried" MOS capacitor-based collection-gate, a transfer-gate, and an n-type MOSFET source/drain n + floating-diffusion serve to realize a non-destructive readout. The pixel readout is performed using an in-pixel source-follower pixel buffer configuration followed by an output amplifier featuring correlated double-sampling. The concentration gradient formed in the n-well employs a single extra implantation step in the 0.35 μm CMOS process mentioned and requires only a single extra mask. It generates an electrostatic potential gradient, i.e. a lateral drift-field, in the photoactive area of the pixel which enables high charge transfer speed and low image-lag. According to the simulation results presented, charge transfer times of less than 3 ns are to be expected.

  20. Single-event transient imaging with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor.

    PubMed

    Mochizuki, Futa; Kagawa, Keiichiro; Okihara, Shin-ichiro; Seo, Min-Woong; Zhang, Bo; Takasawa, Taishi; Yasutomi, Keita; Kawahito, Shoji

    2016-02-22

    In the work described in this paper, an image reproduction scheme with an ultra-high-speed temporally compressive multi-aperture CMOS image sensor was demonstrated. The sensor captures an object by compressing a sequence of images with focal-plane temporally random-coded shutters, followed by reconstruction of time-resolved images. Because signals are modulated pixel-by-pixel during capturing, the maximum frame rate is defined only by the charge transfer speed and can thus be higher than those of conventional ultra-high-speed cameras. The frame rate and optical efficiency of the multi-aperture scheme are discussed. To demonstrate the proposed imaging method, a 5×3 multi-aperture image sensor was fabricated. The average rising and falling times of the shutters were 1.53 ns and 1.69 ns, respectively. The maximum skew among the shutters was 3 ns. The sensor observed plasma emission by compressing it to 15 frames, and a series of 32 images at 200 Mfps was reconstructed. In the experiment, by correcting disparities and considering temporal pixel responses, artifacts in the reconstructed images were reduced. An improvement in PSNR from 25.8 dB to 30.8 dB was confirmed in simulations.

  1. A high speed CMOS image sensor with a novel digital correlated double sampling and a differential difference amplifier.

    PubMed

    Kim, Daehyeok; Bae, Jaeyoung; Song, Minkyu

    2015-03-02

    In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

  2. High-speed modulator with interleaved junctions in zero-change CMOS photonics

    SciTech Connect

    Alloatti, L. Cheian, D.; Ram, R. J.

    2016-03-28

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  3. High-speed modulator with interleaved junctions in zero-change CMOS photonics

    NASA Astrophysics Data System (ADS)

    Alloatti, L.; Cheian, D.; Ram, R. J.

    2016-03-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  4. Optimal high speed CMOS inverter design using craziness based Particle Swarm Optimization Algorithm

    NASA Astrophysics Data System (ADS)

    De, Bishnu P.; Kar, Rajib; Mandal, Durbadal; Ghoshal, Sakti P.

    2015-07-01

    The inverter is the most fundamental logic gate that performs a Boolean operation on a single input variable. In this paper, an optimal design of CMOS inverter using an improved version of particle swarm optimization technique called Craziness based Particle Swarm Optimization (CRPSO) is proposed. CRPSO is very simple in concept, easy to implement and computationally efficient algorithm with two main advantages: it has fast, nearglobal convergence, and it uses nearly robust control parameters. The performance of PSO depends on its control parameters and may be influenced by premature convergence and stagnation problems. To overcome these problems the PSO algorithm has been modiffed to CRPSO in this paper and is used for CMOS inverter design. In birds' flocking or ffsh schooling, a bird or a ffsh often changes direction suddenly. In the proposed technique, the sudden change of velocity is modelled by a direction reversal factor associated with the previous velocity and a "craziness" velocity factor associated with another direction reversal factor. The second condition is introduced depending on a predeffned craziness probability to maintain the diversity of particles. The performance of CRPSO is compared with real code.gnetic algorithm (RGA), and conventional PSO reported in the recent literature. CRPSO based design results are also compared with the PSPICE based results. The simulation results show that the CRPSO is superior to the other algorithms for the examples considered and can be efficiently used for the CMOS inverter design.

  5. PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

    PubMed

    Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

    2012-08-01

    This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm(2) and 100 × 100 μm(2). Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

  6. PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process

    PubMed Central

    Kostov, P.; Gaberl, W.; Hofbauer, M.; Zimmermann, H.

    2012-01-01

    This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high −3 dB bandwidth at low collector–emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm2 and 100 × 100 μm2. Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done. PMID:23482349

  7. High speed CMOS imager with motion artifact supression and anti-blooming

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Wrigley, Chris (Inventor); Yang, Guang (Inventor); Yadid-Pecht, Orly (Inventor)

    2001-01-01

    An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.

  8. A high-speed 0.35μm CMOS optical communication link

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Bogalecki, Alfons W.; Alberts, Antonie C.; Rademeyer, Pieter

    2012-01-01

    The idea of integrating a light emitter and detector in the cost effective and mature technology which is CMOS remains an attractive one. Silicon light emitters, used in avalanche breakdown, are demonstrated to switch at frequencies above 1 GHz whilst still being electrically detected, a three-fold increase on previous reported results. Utilizing novel BEOLstack reflectors and increased array sizes have resulted in an increased power efficiency allowing multi-Mb/s data rates. In this paper we present an all-silicon optical communication link with data rates exceeding 10 Mb/s at a bit error rate of less than 10-12, representing a ten-fold increase over the previous fastest demonstrated silicon data link. Data rates exceeding 40 Mb/s are also presented and evaluated. The quality of the optical link is established using both eye diagram measurements as well as a digital communication system setup. The digital communication system setup comprises the generation of 232-1 random data, 8B/10B encoding and decoding, data recovery and the subsequent bit error counting.

  9. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    PubMed

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-11-17

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  10. High-speed low-voltage CMOS line driver for SerDes applications

    NASA Astrophysics Data System (ADS)

    Rogers, M.; Hayatleh, K.; Lidgey, F. J.; Joy, A.

    2013-04-01

    The challenge facing SerDes (Serialiser De-Serialiser) designers is common with all current communications technologies. Industry advances show a trend to increase speed, reduce power and improve efficiency. In this article a novel line driver that can operate at speeds of up to 40 Gbps with a power supply of 1 V and a power consumption of 4.54 mW/Gb/s is presented. Pre-distortion on the front-end is used to maintain signal integrity.

  11. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  12. Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

    PubMed Central

    Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

    2014-01-01

    The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

  13. Turn up the lights: Deep-sea in situ application of a high-speed, high-resolution sCMOS camera to observe marine bioluminescence

    NASA Astrophysics Data System (ADS)

    Phillips, B. T.; Gruber, D. F.; Sparks, J. S.; Vasan, G.; Roman, C.; Pieribone, V. A.

    2016-02-01

    Observing and measuring marine bioluminescence presents unique challenges in situ. Technology is the greatest limiting factor in this endeavor, with sensitivity, speed and resolution constraining the imaging tools available to researchers. State-of-the-art microscopy cameras offer to bridge this gap. An ultra-low-light, scientific complimentary-metal-oxide-semiconductor (sCMOS) camera was outfitted for in-situ imaging of marine bioluminescence. This system was deployed on multiple deep-sea platforms (manned submersible, remotely operated vehicle, and towed body) in three oceanic regions (Western Tropical Pacific, Eastern Equatorial Pacific, and Northwestern Atlantic) to depths up to 2500m. Using light stimulation, bioluminescent responses were recorded at high frame rates and in high resolution, offering unprecedented low-light imagery of deep-sea bioluminescence in situ. The kinematics and physiology of light production in several zooplankton groups is presented, and luminescent responses at different depths are quantified as intensity vs. time.

  14. Transistor sizing in the design of high-speed CMOS (complementary-symmetry metal-oxide-semiconductor) super buffers. Master's thesis

    SciTech Connect

    Steele, G.R.

    1988-03-01

    An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated-circuit logic design using silicon-gate enhancement-mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm is applied to the mask-level hardware design of a three-micron-minimum feature-size p-well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated (VLSI) circuits.

  15. Bulk CMOS VLSI Technology Studies. Part 5. The Design and Implementation of a High Speed Integrated Circuit Functional Tester.

    DTIC Science & Technology

    2014-09-26

    SPEED INTEGRATED CIRCUIT FUNCTIONAL TESTER It Principal Investi-s tar J. Donald Trotter Associate Investigator Boyle Dwayne Robbins Mississippi State...3H * 7H . .......................................... ’ " "" : ’ " " 176 S REFERENCES 177 References Atlas, Joseph & Nielsen, Robert High-Speed Digital

  16. A high speed and high gain CMOS receiver chip for a pulsed time-of-flight laser rangefinder

    NASA Astrophysics Data System (ADS)

    Yu, Jin-jin; Deng, Ruo-han; Yuan, Hong-hui; Chen, Yong-ping

    2011-06-01

    An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed. Pulsed TOF laser range finding devices using a laser diode transmitter can achieve millimeter-level distance measurement accuracy in a measurement range of several tens of meters to non-cooperative targets. The amplifier exploits the regulated cascade (RGC) configuration as the input-stage, thus achieving as large effective input trans-conductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. To enlarge the bandwidth, inductive peaking technology has been adopted. An active inductor (MOS-L) is used instead of spiral inductor in CMOS process. An R-2R resistor ladder is inserting between per-amplifier and post-amplifier as the variable attenuator for digital gain control purpose. The gain-bandwidth of a basic differential pair with resistive load is not large enough for broad band operation. A circuit solution to improve both gain and bandwidth of an amplifying stage is proposed. Traditional and modified Cherry-Hooper amplifiers are discussed and the cascading of several stages to constitute the post-amplifier is designed. The fully integrated one-chip solution is designed with Cadence IC design platform. The simulation result shows the bandwidth of the trans-impedance amplifier is 215MHz with the presence of a 2pF input capacitor and 5pF load capacitor. And the maximum trans-impedance gain is 136dB. The walk error is less than 1ns in 1:1000 dynamic range. The responsive time is less than 2.2ns.

  17. High speed sCMOS-based oblique plane microscopy applied to the study of calcium dynamics in cardiac myocytes.

    PubMed

    Sikkel, Markus B; Kumar, Sunil; Maioli, Vincent; Rowlands, Christina; Gordon, Fabiana; Harding, Sian E; Lyon, Alexander R; MacLeod, Kenneth T; Dunsby, Chris

    2016-03-01

    Oblique plane microscopy (OPM) is a form of light sheet microscopy that uses a single high numerical aperture microscope objective for both fluorescence excitation and collection. In this paper, measurements of the relative collection efficiency of OPM are presented. An OPM system incorporating two sCMOS cameras is then introduced that enables single isolated cardiac myocytes to be studied continuously for 22 seconds in two dimensions at 667 frames per second with 960 × 200 pixels and for 30 seconds with 960 × 200 × 20 voxels at 25 volumes per second. In both cases OPM is able to record in two spectral channels, enabling intracellular calcium to be studied via the probe Fluo-4 AM simultaneously with the sarcolemma and transverse tubule network via the membrane dye Cellmask Orange. The OPM system was then applied to determine the spatial origin of spontaneous calcium waves for the first time and to measure the cell transverse tubule structure at their point of origin. Further results are presented to demonstrate that the OPM system can also be used to study calcium spark parameters depending on their relationship to the transverse tubule structure.

  18. High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier.

    PubMed

    Pan, Huapu; Assefa, Solomon; Green, William M J; Kuchta, Daniel M; Schow, Clint L; Rylyakov, Alexander V; Lee, Benjamin G; Baks, Christian W; Shank, Steven M; Vlasov, Yurii A

    2012-07-30

    The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

  19. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Quanliang, Li; Liyuan, Liu; Ye, Han; Zhongxiang, Cao; Nanjian, Wu

    2014-10-01

    This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

  20. A high-speed two-frame, 1-2 ns gated X-ray CMOS imager used as a hohlraum diagnostic on the National Ignition Facility (invited).

    PubMed

    Chen, Hui; Palmer, N; Dayton, M; Carpenter, A; Schneider, M B; Bell, P M; Bradley, D K; Claus, L D; Fang, L; Hilsabeck, T; Hohenberger, M; Jones, O S; Kilkenny, J D; Kimmel, M W; Robertson, G; Rochau, G; Sanchez, M O; Stahoviak, J W; Trotter, D C; Porter, J L

    2016-11-01

    A novel x-ray imager, which takes time-resolved gated images along a single line-of-sight, has been successfully implemented at the National Ignition Facility (NIF). This Gated Laser Entrance Hole diagnostic, G-LEH, incorporates a high-speed multi-frame CMOS x-ray imager developed by Sandia National Laboratories to upgrade the existing Static X-ray Imager diagnostic at NIF. The new diagnostic is capable of capturing two laser-entrance-hole images per shot on its 1024 × 448 pixels photo-detector array, with integration times as short as 1.6 ns per frame. Since its implementation on NIF, the G-LEH diagnostic has successfully acquired images from various experimental campaigns, providing critical new information for understanding the hohlraum performance in inertial confinement fusion (ICF) experiments, such as the size of the laser entrance hole vs. time, the growth of the laser-heated gold plasma bubble, the change in brightness of inner beam spots due to time-varying cross beam energy transfer, and plasma instability growth near the hohlraum wall.

  1. A high-speed two-frame, 1-2 ns gated X-ray CMOS imager used as a hohlraum diagnostic on the National Ignition Facility (invited)

    NASA Astrophysics Data System (ADS)

    Chen, Hui; Palmer, N.; Dayton, M.; Carpenter, A.; Schneider, M. B.; Bell, P. M.; Bradley, D. K.; Claus, L. D.; Fang, L.; Hilsabeck, T.; Hohenberger, M.; Jones, O. S.; Kilkenny, J. D.; Kimmel, M. W.; Robertson, G.; Rochau, G.; Sanchez, M. O.; Stahoviak, J. W.; Trotter, D. C.; Porter, J. L.

    2016-11-01

    A novel x-ray imager, which takes time-resolved gated images along a single line-of-sight, has been successfully implemented at the National Ignition Facility (NIF). This Gated Laser Entrance Hole diagnostic, G-LEH, incorporates a high-speed multi-frame CMOS x-ray imager developed by Sandia National Laboratories to upgrade the existing Static X-ray Imager diagnostic at NIF. The new diagnostic is capable of capturing two laser-entrance-hole images per shot on its 1024 × 448 pixels photo-detector array, with integration times as short as 1.6 ns per frame. Since its implementation on NIF, the G-LEH diagnostic has successfully acquired images from various experimental campaigns, providing critical new information for understanding the hohlraum performance in inertial confinement fusion (ICF) experiments, such as the size of the laser entrance hole vs. time, the growth of the laser-heated gold plasma bubble, the change in brightness of inner beam spots due to time-varying cross beam energy transfer, and plasma instability growth near the hohlraum wall.

  2. Observations of in situ deep-sea marine bioluminescence with a high-speed, high-resolution sCMOS camera

    NASA Astrophysics Data System (ADS)

    Phillips, Brennan T.; Gruber, David F.; Vasan, Ganesh; Roman, Christopher N.; Pieribone, Vincent A.; Sparks, John S.

    2016-05-01

    Observing and measuring marine bioluminescence in situ presents unique challenges, characterized by the difficult task of approaching and imaging weakly illuminated bodies in a three-dimensional environment. To address this problem, a scientific complementary-metal-oxide-semiconductor (sCMOS) microscopy camera was outfitted for deep-sea imaging of marine bioluminescence. This system was deployed on multiple platforms (manned submersible, remotely operated vehicle, and towed body) in three oceanic regions (Western Tropical Pacific, Eastern Equatorial Pacific, and Northwestern Atlantic) to depths up to 2500 m. Using light stimulation, bioluminescent responses were recorded at high frame rates and in high resolution, offering unprecedented low-light imagery of deep-sea bioluminescence in situ. The kinematics of light production in several zooplankton groups was observed, and luminescent responses at different depths were quantified as intensity vs. time. These initial results signify a clear advancement in the bioluminescent imaging methods available for observation and experimentation in the deep-sea.

  3. Developments and Applications of High-Performance CCD and CMOS Imaging Arrays

    NASA Astrophysics Data System (ADS)

    Janesick, James; Putnam, Gloria

    2003-12-01

    For over 20 years, charge-coupled devices (CCDs) have dominated most digital imaging applications and markets. Today, complementary metal oxide semiconductor (CMOS) arrays are displacing CCDs in some applications, and this trend is expected to continue. Low cost, low power, on-chip system integration, and high-speed operation are unique features that have generated interest in CMOS arrays. This paper reviews current CCD and CMOS sensor developments and related applications. We compare fundamental performance parameters common to these technologies and describe why the CCD is considered a mature technology, whereas CMOS arrays have significant room for growth. The paper presents custom CMOS pixel designs and related fabrication processes that address performance deficiencies of the CCD in high-performance applications. We discuss areas of development for future CCD and CMOS imagers. The paper also briefly reviews hybrid imaging arrays that combine the advantages of CCD and CMOS, producing better sensors than either technology alone can provide.

  4. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.

    PubMed

    Abdulrazzaq, Bilal I; Ibrahim, Omar J; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md; Lee, Lini; Halin, Izhal Abdul

    2016-09-28

    A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture's circuit is 0.1 mW when the DLL is operated at 2 GHz.

  5. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

    PubMed Central

    Abdulrazzaq, Bilal I.; Ibrahim, Omar J.; Kawahito, Shoji; Sidek, Roslina M.; Shafie, Suhaidi; Yunus, Nurul Amziah Md.; Lee, Lini; Halin, Izhal Abdul

    2016-01-01

    A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz. PMID:27690040

  6. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  7. Video-rate fluorescence lifetime imaging camera with CMOS single-photon avalanche diode arrays and high-speed imaging algorithm.

    PubMed

    Li, David D-U; Arlt, Jochen; Tyndall, David; Walker, Richard; Richardson, Justin; Stoppa, David; Charbon, Edoardo; Henderson, Robert K

    2011-09-01

    A high-speed and hardware-only algorithm using a center of mass method has been proposed for single-detector fluorescence lifetime sensing applications. This algorithm is now implemented on a field programmable gate array to provide fast lifetime estimates from a 32 × 32 low dark count 0.13 μm complementary metal-oxide-semiconductor single-photon avalanche diode (SPAD) plus time-to-digital converter array. A simple look-up table is included to enhance the lifetime resolvability range and photon economics, making it comparable to the commonly used least-square method and maximum-likelihood estimation based software. To demonstrate its performance, a widefield microscope was adapted to accommodate the SPAD array and image different test samples. Fluorescence lifetime imaging microscopy on fluorescent beads in Rhodamine 6G at a frame rate of 50 fps is also shown.

  8. A custom CMOS imager for multi-beam laser scanning microscopy and an improvement of scanning speed

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2013-02-01

    Multi-beam laser scanning confocal microscopy with a 256 × 256-pixel custom CMOS imager performing focal-plane pinhole effect, in which any rotating disk is not required, is demonstrated. A specimen is illuminated by 32 × 32 diffraction limited light spots whose wavelength and pitch are 532nm and 8.4 μm, respectively. The spot array is generated by a microlens array, which is scanned by two-dimensional piezo actuator according to the scanning of the image sensor. The frame rate of the prototype is 0.17 Hz, which is limited by the actuator. The confocal effect has been confirmed by comparing the axial resolution in the confocal imaging mode with that of the normal imaging mode. The axial resolution in the confocal mode measured by the full width at half maximum (FWHM) for a planar mirror was 8.9 μm, which is showed that the confocality has been achieved with the proposed CMOS image sensor. The focal-plane pinhole effect in the confocal microscopy with the proposed CMOS imager has been demonstrated at low frame rate. An improvement of the scanning speed and a CMOS imager with photo-sensitivity modulation pixels suitable for high-speed scanning are also discussed.

  9. High speed technology development and evaluation

    NASA Astrophysics Data System (ADS)

    Parker, D. R.; Brown, E. R.; Dickson, J. F.

    1986-10-01

    Semiconductor technology suited to high on-board data handling rates was investigated. Very high speed discrete logic and high speed gate arrays; single chip digital signal processors and single chip floating point processing peripherals; and analog CCD technologies and custom designed CCD chips for synthetic aperture radar applications were assessed. The 2 micron CMOS technology is highly reliable, supporting semicustom design techniques. Process JGC, the CCD technology, is highly reliable except for tolerance to ionizing radiation. Reliability of the ECL 16-bit serial-parallel parallel-serial converter junction isolated bipolar process, process WZA, is compromised by a design error and oxide contamination contributing to high leakage levels. The bipolar circuit is tolerant to an ionizing radiation of 20kRad. Step stress environmental testing to 200 C produces no failures in CMOS and CCD technologies, but accelerates the degradation of the oxide contaminated bipolar process. All technologies are susceptible to single event upsets.

  10. Theoretical performance analysis for CMOS based high resolution detectors.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-06

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

  11. High speed handpieces

    PubMed Central

    Bhandary, Nayan; Desai, Asavari; Shetty, Y Bharath

    2014-01-01

    High speed instruments are versatile instruments used by clinicians of all specialties of dentistry. It is important for clinicians to understand the types of high speed handpieces available and the mechanism of working. The centers for disease control and prevention have issued guidelines time and again for disinfection and sterilization of high speed handpieces. This article presents the recent developments in the design of the high speed handpieces. With a view to prevent hospital associated infections significant importance has been given to disinfection, sterilization & maintenance of high speed handpieces. How to cite the article: Bhandary N, Desai A, Shetty YB. High speed handpieces. J Int Oral Health 2014;6(1):130-2. PMID:24653618

  12. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  13. Delta Doping High Purity CCDs and CMOS for LSST

    NASA Technical Reports Server (NTRS)

    Blacksberg, Jordana; Nikzad, Shouleh; Hoenk, Michael; Elliott, S. Tom; Bebek, Chris; Holland, Steve; Kolbe, Bill

    2006-01-01

    A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

  14. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  15. High Speed Research Program

    NASA Technical Reports Server (NTRS)

    Anderson, Robert E.; Corsiglia, Victor R.; Schmitz, Frederic H. (Technical Monitor)

    1994-01-01

    An overview of the NASA High Speed Research Program will be presented from a NASA Headquarters perspective. The presentation will include the objectives of the program and an outline of major programmatic issues.

  16. High-Speed Photography

    SciTech Connect

    Paisley, D.L.; Schelev, M.Y.

    1998-08-01

    The applications of high-speed photography to a diverse set of subjects including inertial confinement fusion, laser surgical procedures, communications, automotive airbags, lightning etc. are briefly discussed. (AIP) {copyright} {ital 1998 Society of Photo-Optical Instrumentation Engineers.}

  17. A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

    NASA Astrophysics Data System (ADS)

    Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

    2016-01-01

    This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

  18. Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Fu, M.; Zhang, Y.; Yan, W.; Wang, M.

    2017-01-01

    The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

  19. High speed flywheel

    SciTech Connect

    McGrath, S.V.

    1990-01-01

    This invention relates generally to flywheels and relates more particularly to the construction of a high speed, low-mass flywheel. Flywheels with which this invention is to be compared include those constructed of circumferentially wound filaments or fibers held together by a matrix or bonding material. Flywheels of such construction are known to possess a relatively high hoop strength but a relatively low radial strength. Hoop-wound flywheels are, therefore, particularly susceptible to circumferential cracks, and the radial stress limitations of such a flywheel substantially limit its speed capabilities. It is an object of the present invention to provide a new and improved flywheel which experiences reduced radial stress at high operating speeds. Another object of the present invention is to provide flywheel whose construction allows for radial growth as flywheel speed increases while providing the necessary stiffness for transferring and maintaining kinetic energy within the flywheel. Still another object of the present invention is to provide a flywheel having concentrically-disposed component parts wherein rotation induced radial stresses at the interfaces of such component parts approach zero. Yet another object of the present invention is to provide a flywheel which is particularly well-suited for high speed applications. 5 figs.

  20. High Speed Ice Friction

    NASA Astrophysics Data System (ADS)

    Seymour-Pierce, Alexandra; Sammonds, Peter; Lishman, Ben

    2014-05-01

    Many different tribological experiments have been run to determine the frictional behaviour of ice at high speeds, ostensibly with the intention of applying results to everyday fields such as winter tyres and sports. However, experiments have only been conducted up to linear speeds of several metres a second, with few additional subject specific studies reaching speeds comparable to these applications. Experiments were conducted in the cold rooms of the Rock and Ice Physics Laboratory, UCL, on a custom built rotational tribometer based on previous literature designs. Preliminary results from experiments run at 2m/s for ice temperatures of 271 and 263K indicate that colder ice has a higher coefficient of friction, in accordance with the literature. These results will be presented, along with data from further experiments conducted at temperatures between 259-273K (in order to cover a wide range of the temperature dependent behaviour of ice) and speeds of 2-15m/s to produce a temperature-velocity-friction map for ice. The effect of temperature, speed and slider geometry on the deformation of ice will also be investigated. These speeds are approaching those exhibited by sports such as the luge (where athletes slide downhill on an icy track), placing the tribological work in context.

  1. High speed door assembly

    DOEpatents

    Shapiro, Carolyn

    1993-01-01

    A high speed door assembly, comprising an actuator cylinder and piston rods, a pressure supply cylinder and fittings, an electrically detonated explosive bolt, a honeycomb structured door, a honeycomb structured decelerator, and a structural steel frame encasing the assembly to close over a 3 foot diameter opening within 50 milliseconds of actuation, to contain hazardous materials and vapors within a test fixture.

  2. High speed door assembly

    DOEpatents

    Shapiro, C.

    1993-04-27

    A high speed door assembly is described, comprising an actuator cylinder and piston rods, a pressure supply cylinder and fittings, an electrically detonated explosive bolt, a honeycomb structured door, a honeycomb structured decelerator, and a structural steel frame encasing the assembly to close over a 3 foot diameter opening within 50 milliseconds of actuation, to contain hazardous materials and vapors within a test fixture.

  3. High Speed Vortex Flows

    NASA Technical Reports Server (NTRS)

    Wood, Richard M.; Wilcox, Floyd J., Jr.; Bauer, Steven X. S.; Allen, Jerry M.

    2000-01-01

    A review of the research conducted at the National Aeronautics and Space Administration (NASA), Langley Research Center (LaRC) into high-speed vortex flows during the 1970s, 1980s, and 1990s is presented. The data reviewed is for flat plates, cavities, bodies, missiles, wings, and aircraft. These data are presented and discussed relative to the design of future vehicles. Also presented is a brief historical review of the extensive body of high-speed vortex flow research from the 1940s to the present in order to provide perspective of the NASA LaRC's high-speed research results. Data are presented which show the types of vortex structures which occur at supersonic speeds and the impact of these flow structures to vehicle performance and control is discussed. The data presented shows the presence of both small- and large scale vortex structures for a variety of vehicles, from missiles to transports. For cavities, the data show very complex multiple vortex structures exist at all combinations of cavity depth to length ratios and Mach number. The data for missiles show the existence of very strong interference effects between body and/or fin vortices and the downstream fins. It was shown that these vortex flow interference effects could be both positive and negative. Data are shown which highlights the effect that leading-edge sweep, leading-edge bluntness, wing thickness, location of maximum thickness, and camber has on the aerodynamics of and flow over delta wings. The observed flow fields for delta wings (i.e. separation bubble, classical vortex, vortex with shock, etc.) are discussed in the context of' aircraft design. And data have been shown that indicate that aerodynamic performance improvements are available by considering vortex flows as a primary design feature. Finally a discussing of a design approach for wings which utilize vortex flows for improved aerodynamic performance at supersonic speed is presented.

  4. High Speed Video Insertion

    NASA Astrophysics Data System (ADS)

    Janess, Don C.

    1984-11-01

    This paper describes a means of inserting alphanumeric characters and graphics into a high speed video signal and locking that signal to an IRIG B time code. A model V-91 IRIG processor, developed by Instrumentation Technology Systems under contract to Instrumentation Marketing Corporation has been designed to operate in conjunction with the NAC model FHS-200 High Speed Video Camera which operates at 200 fields per second. The system provides for synchronizing the vertical and horizontal drive signals such that the vertical sync precisely coincides with five millisecond transitions in the IRIG time code. Additionally, the unit allows for the insertion of an IRIG time message as well as other data and symbols.

  5. Mechanically Flexible and High-Performance CMOS Logic Circuits.

    PubMed

    Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

    2015-10-13

    Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

  6. High speed multiphoton imaging

    NASA Astrophysics Data System (ADS)

    Li, Yongxiao; Brustle, Anne; Gautam, Vini; Cockburn, Ian; Gillespie, Cathy; Gaus, Katharina; Lee, Woei Ming

    2016-12-01

    Intravital multiphoton microscopy has emerged as a powerful technique to visualize cellular processes in-vivo. Real time processes revealed through live imaging provided many opportunities to capture cellular activities in living animals. The typical parameters that determine the performance of multiphoton microscopy are speed, field of view, 3D imaging and imaging depth; many of these are important to achieving data from in-vivo. Here, we provide a full exposition of the flexible polygon mirror based high speed laser scanning multiphoton imaging system, PCI-6110 card (National Instruments) and high speed analog frame grabber card (Matrox Solios eA/XA), which allows for rapid adjustments between frame rates i.e. 5 Hz to 50 Hz with 512 × 512 pixels. Furthermore, a motion correction algorithm is also used to mitigate motion artifacts. A customized control software called Pscan 1.0 is developed for the system. This is then followed by calibration of the imaging performance of the system and a series of quantitative in-vitro and in-vivo imaging in neuronal tissues and mice.

  7. High speed civil transport

    NASA Technical Reports Server (NTRS)

    Bogardus, Scott; Loper, Brent; Nauman, Chris; Page, Jeff; Parris, Rusty; Steinbach, Greg

    1990-01-01

    The design process of the High Speed Civil Transport (HSCT) combines existing technology with the expectation of future technology to create a Mach 3.0 transport. The HSCT was designed to have a range in excess of 6000 nautical miles and carry up to 300 passengers. This range will allow the HSCT to service the economically expanding Pacific Basin region. Effort was made in the design to enable the aircraft to use conventional airports with standard 12,000 foot runways. With a takeoff thrust of 250,000 pounds, the four supersonic through-flow engines will accelerate the HSCT to a cruise speed of Mach 3.0. The 679,000 pound (at takeoff) HSCT is designed to cruise at an altitude of 70,000 feet, flying above most atmospheric disturbances.

  8. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  9. Micromachined high-performance RF passives in CMOS substrate

    NASA Astrophysics Data System (ADS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  10. High speed flywheel

    DOEpatents

    McGrath, Stephen V.

    1991-01-01

    A flywheel for operation at high speeds utilizes two or more ringlike coments arranged in a spaced concentric relationship for rotation about an axis and an expansion device interposed between the components for accommodating radial growth of the components resulting from flywheel operation. The expansion device engages both of the ringlike components, and the structure of the expansion device ensures that it maintains its engagement with the components. In addition to its expansion-accommodating capacity, the expansion device also maintains flywheel stiffness during flywheel operation.

  11. High speed flywheel

    SciTech Connect

    McGrath, S.V.

    1991-05-07

    This patent describes a flywheel for operation at high speed which utilizes two or more ringlike components arranged in a spaced concentric relationship for rotation about an axis and an expansion device interposed between the components for accommodating radial growth of the components resulting from flywheel operation. The expansion device engages both of the ringlike components, and the structure of the expansion device ensures that it maintains its engagement with the components. In addition to its expansion-accommodating capacity, the expansion device also maintains flywheel stiffness during flywheel operation.

  12. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    NASA Technical Reports Server (NTRS)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  13. High speed transient sampler

    DOEpatents

    McEwan, Thomas E.

    1995-01-01

    A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator. The sample holding capacitor is implemented using a smaller capacitor and a larger capacitor isolated from the smaller capacitor by resistance. The high speed sampler of the present invention is also characterized by other optimizations, including transmission line tap compensation, stepped impedance strobe line, a multi-layer physical layout, and unique strobe generator design. A plurality of banks of such samplers are controlled for concatenated or interleaved sample intervals to achieve long sample lengths or short sample spacing.

  14. High speed transient sampler

    DOEpatents

    McEwan, T.E.

    1995-11-28

    A high speed sampler comprises a meandered sample transmission line for transmitting an input signal, a straight strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates along the transmission lines. The sampling gates comprise a four terminal diode bridge having a first strobe resistor connected from a first terminal of the bridge to the positive strobe line, a second strobe resistor coupled from the third terminal of the bridge to the negative strobe line, a tap connected to the second terminal of the bridge and to the sample transmission line, and a sample holding capacitor connected to the fourth terminal of the bridge. The resistance of the first and second strobe resistors is much higher than the signal transmission line impedance in the preferred system. This results in a sampling gate which applies a very small load on the sample transmission line and on the strobe generator. The sample holding capacitor is implemented using a smaller capacitor and a larger capacitor isolated from the smaller capacitor by resistance. The high speed sampler of the present invention is also characterized by other optimizations, including transmission line tap compensation, stepped impedance strobe line, a multi-layer physical layout, and unique strobe generator design. A plurality of banks of such samplers are controlled for concatenated or interleaved sample intervals to achieve long sample lengths or short sample spacing. 17 figs.

  15. Monolithic CMOS-MEMS integration for high-g accelerometers

    NASA Astrophysics Data System (ADS)

    Narasimhan, Vinayak; Li, Holden; Tan, Chuan Seng

    2014-10-01

    This paper highlights work-in-progress towards the conceptualization, simulation, fabrication and initial testing of a silicon-germanium (SiGe) integrated CMOS-MEMS high-g accelerometer for military, munition, fuze and shock measurement applications. Developed on IMEC's SiGe MEMS platform, the MEMS offers a dynamic range of 5,000 g and a bandwidth of 12 kHz. The low noise readout circuit adopts a chopper-stabilization technique implementing the CMOS through the TSMC 0.18 µm process. The device structure employs a fully differential split comb-drive set up with two sets of stators and a rotor all driven separately. Dummy structures acting as protective over-range stops were designed to protect the active components when under impacts well above the designed dynamic range.

  16. HIGH SPEED CAMERA

    DOEpatents

    Rogers, B.T. Jr.; Davis, W.C.

    1957-12-17

    This patent relates to high speed cameras having resolution times of less than one-tenth microseconds suitable for filming distinct sequences of a very fast event such as an explosion. This camera consists of a rotating mirror with reflecting surfaces on both sides, a narrow mirror acting as a slit in a focal plane shutter, various other mirror and lens systems as well as an innage recording surface. The combination of the rotating mirrors and the slit mirror causes discrete, narrow, separate pictures to fall upon the film plane, thereby forming a moving image increment of the photographed event. Placing a reflecting surface on each side of the rotating mirror cancels the image velocity that one side of the rotating mirror would impart, so as a camera having this short a resolution time is thereby possible.

  17. High speed nozzles task

    NASA Technical Reports Server (NTRS)

    Hamed, Awatef

    1995-01-01

    Supersonic cruise exhaust nozzles for advanced applications are optimized for a high nozzle pressure ratio (NPR) at design supersonic cruise Mach number and altitude. The performance of these nozzles with large expansion ratios are severely degraded for operations at subsonic speeds near sea level for NPR significantly less than the design values. The prediction of over-expanded 2DCD nozzles performance is critical to evaluating the internal losses and to the optimization of the integrated vehicle and propulsion system performance. The reported research work was aimed at validating and assessing existing computational methods and turbulence models for predicting the flow characteristics and nozzle performance at over-expanded conditions. Flow simulations in 2DCD nozzles were performed using five different turbulence models. The results are compared with the experimental data for the wall pressure distribution and thrust and flow coefficients at over-expanded static conditions.

  18. High speed packet switching

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This document constitutes the final report prepared by Proteon, Inc. of Westborough, Massachusetts under contract NAS 5-30629 entitled High-Speed Packet Switching (SBIR 87-1, Phase 2) prepared for NASA-Greenbelt, Maryland. The primary goal of this research project is to use the results of the SBIR Phase 1 effort to develop a sound, expandable hardware and software router architecture capable of forwarding 25,000 packets per second through the router and passing 300 megabits per second on the router's internal busses. The work being delivered under this contract received its funding from three different sources: the SNIPE/RIG contract (Contract Number F30602-89-C-0014, CDRL Sequence Number A002), the SBIR contract, and Proteon. The SNIPE/RIG and SBIR contracts had many overlapping requirements, which allowed the research done under SNIPE/RIG to be applied to SBIR. Proteon funded all of the work to develop new router interfaces other than FDDI, in addition to funding the productization of the router itself. The router being delivered under SBIR will be a fully product-quality machine. The work done during this contract produced many significant findings and results, summarized here and explained in detail in later sections of this report. The SNIPE/RIG contract was completed. That contract had many overlapping requirements with the SBIR contract, and resulted in the successful demonstration and delivery of a high speed router. The development that took place during the SNIPE/RIG contract produced findings that included the choice of processor and an understanding of the issues surrounding inter processor communications in a multiprocessor environment. Many significant speed enhancements to the router software were made during that time. Under the SBIR contract (and with help from Proteon-funded work), it was found that a single processor router achieved a throughput significantly higher than originally anticipated. For this reason, a single processor router was

  19. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    NASA Astrophysics Data System (ADS)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  20. High resolution, high bandwidth global shutter CMOS area scan sensors

    NASA Astrophysics Data System (ADS)

    Faramarzpour, Naser; Sonder, Matthias; Li, Binqiao

    2013-10-01

    Global shuttering, sometimes also known as electronic shuttering, enables the use of CMOS sensors in a vast range of applications. Teledyne DALSA Global shutter sensors are able to integrate light synchronously across millions of pixels with microsecond accuracy. Teledyne DALSA offers 5 transistor global shutter pixels in variety of resolutions, pitches and noise and full-well combinations. One of the recent generations of these pixels is implemented in 12 mega pixel area scan device at 6 um pitch and that images up to 70 frames per second with 58 dB dynamic range. These square pixels include microlens and optional color filters. These sensors also offer exposure control, anti-blooming and high dynamic range operation by introduction of a drain and a PPD reset gate to the pixel. The state of the art sense node design of Teledyne DALSA's 5T pixel offers exceptional shutter rejection ratio. The architecture is consistent with the requirements to use stitching to achieve very large area scan devices. Parallel or serial digital output is provided on these sensors using on-chip, column-wise analog to digital converters. Flexible ADC bit depth combined with windowing (adjustable region of interest, ROI) allows these sensors to run with variety of resolution/bandwidth combinations. The low power, state of the art LVDS I/O technology allows for overall power consumptions of less than 2W at full performance conditions.

  1. High-Voltage CMOS Controller for Microfluidics.

    PubMed

    Khorasani, M; Behnam, M; van den Berg, L; Backhouse, C J; Elliott, D G

    2009-04-01

    A high-voltage microfluidic controller designed using DALSA semiconductor's 0.8-mum low-voltage/high-voltage complementary metal-oxide semiconductor/double diffused metal-oxide semiconductor process is presented. The chip's four high-voltage output drivers can switch 300 V, and the dc-dc boost converter can generate up to 68 V using external passive components. This integrated circuit represents an advancement in microfluidic technology when used in conjunction with a charge coupling device (CCD)-based optical system and a glass microfluidic channel, enabling a portable and cost-efficient platform for genetic analysis.

  2. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    NASA Astrophysics Data System (ADS)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  3. High speed civil transport

    NASA Technical Reports Server (NTRS)

    1991-01-01

    This report discusses the design and marketability of a next generation supersonic transport. Apogee Aeronautics Corporation has designated its High Speed Civil Transport (HSCT): Supercruiser HS-8. Since the beginning of the Concorde era, the general consensus has been that the proper time for the introduction of a next generation Supersonic Transport (SST) would depend upon the technical advances made in the areas of propulsion (reduction in emissions) and material composites (stronger, lighter materials). It is believed by many in the aerospace industry that these beforementioned technical advances lie on the horizon. With this being the case, this is the proper time to begin the design phase for the next generation HSCT. The design objective for a HSCT was to develop an aircraft that would be capable of transporting at least 250 passengers with baggage at a distance of 5500 nmi. The supersonic Mach number is currently unspecified. In addition, the design had to be marketable, cost effective, and certifiable. To achieve this goal, technical advances in the current SST's must be made, especially in the areas of aerodynamics and propulsion. As a result of these required aerodynamic advances, several different supersonic design concepts were reviewed.

  4. High speed nanotechnology-based photodetector

    NASA Astrophysics Data System (ADS)

    Kurtz, Russell M.; Pradhan, Ranjit D.; Parfenov, Alexander V.; Holmstedt, Jason; Esterkin, Vladimir; Menon, Naresh; Aye, Tin M.; Chua, Kang-Bin; Schindler, Axel; Balandin, Alexander A.; Nichter, James E.

    2005-08-01

    An inexpensive, easily integrated, 40 Gbps photoreceiver operating in the communications band would revolutionize the telecommunications industry. While generation of 40 Gbps data is not difficult, its reception and decoding require specific technologies. We present a 40 Gbps photoreceiver that exceeds the capabilities of current devices. This photoreceiver is based on a technology we call "nanodust." This new technology enables nanoscale photodetectors to be embedded in matrices made from a different semiconductor, or directly integrated into a CMOS amplification circuit. Photoreceivers based on quantum dust technology can be designed to operate in any spectral region, including the telecommunications bands near 1.31 and 1.55 micrometers. This technology also lends itself to normal-incidence detection, enabling a large detector size with its associated increase in sensitivity, even at high speeds and reception wavelengths beyond the capability of silicon.

  5. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  6. High speed transition prediction

    NASA Technical Reports Server (NTRS)

    Gasperas, Gediminis

    1992-01-01

    The main objective of this work period was to develop, acquire and apply state-of-the-art tools for the prediction of transition at high speeds at NASA Ames. Although various stability codes as well as basic state codes were acquired, the development of a new Parabolized Stability Equation (PSE) code was minimal. The time that was initially allocated for development was used on other tasks, in particular for the Leading Edge Suction problem, in acquiring proficiency in various graphics tools, and in applying these tools to evaluate various Navier-Stokes and Euler solutions. The second objective of this work period was to attend the Transition and Turbulence Workshop at NASA Langley in July and August, 1991. A report on the Workshop follows. From July 8, 1991 to August 2, 1991, the author participated in the Transition and Turbulence Workshop at NASA Langley. For purposes of interest here, analysis can be said to consist of solving simplified governing equations by various analytical methods, such as asymptotic methods, or by use of very meager computer resources. From the composition of the various groups at the Workshop, it can be seen that analytical methods are generally more popular in Great Britain than they are in the U.S., possibly due to historical factors and the lack of computer resources. Experimenters at the Workshop were mostly concerned with subsonic flows, and a number of demonstrations were provided, among which were a hot-wire experiment to probe the boundary layer on a rotating disc, a hot-wire rake to map a free shear layer behind a cylinder, and the use of heating strips on a flat plate to control instability waves and consequent transition. A highpoint of the demonstrations was the opportunity to observe the rather noisy 'quiet' supersonic pilot tunnel in operation.

  7. High Speed Metal Removal

    DTIC Science & Technology

    1982-10-01

    values showed an unusual wear pattern, so the cutting speed was lowered to 440 feet per minute. When the results of these tests were plotted, this curve...again showed unusual wear. From this chart. Figure 6, Page 16, values of 3100 square inches of machined area, at a surface speed of 440 feet per...G RA DE _ 5P0 / f— r- s FM _ 4 00 F r. /M IN / O F RF D _ ,0 22 i N. / RPV / UJ 3 0 0 0- t // / Q. / / — LU O < t / / LL / / W 2 0 0

  8. High speed metal removal

    NASA Astrophysics Data System (ADS)

    Pugh, R. F.; Pohl, R. F.

    1982-10-01

    Four types of steel (AISI 1340, 4140, 4340, and HF-1) which are commonly used in large caliber projectile manufacture were machined at different hardness ranges representing the as-forged and the heat treated condition with various ceramic tools using ceramic coated tungsten carbide as a reference. Results show that machining speeds can be increased significantly using present available tooling.

  9. An integrated CMOS high data rate transceiver for video applications

    NASA Astrophysics Data System (ADS)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  10. High-performance imagers for space applications: The strong benefits of CMOS image sensors processes

    NASA Astrophysics Data System (ADS)

    Saint-Pé, O.; Magnan, P.; Bréart de Boisanger, M.; Tulet, M.; Davancens, R.; Martin Gonthier, P.; Corbière, F.; Huger, N.

    2009-10-01

    Space community has quickly understood the benefits that CMOS technology can procure for the design and manufacture of image sensors, with respect to CCDs which have been the detector of choice for most optical applications during the last 25 years. On the other hand, a majority of space applications is requesting high electro-optics performances to avoid payload oversizing. This was not reachable by CMOS monolithic devices built with standard mixed signal processes. Since the end of the 90s, foundries have developed outstanding CMOS processes optimised for Image Sensors. Combined with the intrinsic advantages of CMOS, they allow developing powerful imagers for space missions. After explaining specificity of CIS processes, the development of a first generation of CMOS Image Sensors for optical instrument will be detailed. Continuation of this route, thanks to the use of advanced CMOS processes, will then be presented.

  11. Focused Mission High Speed Combatant

    DTIC Science & Technology

    2003-05-09

    hull types to determine which hull type best meets the requirements for the Focused Mission High Speed Combatant. The first step in the analysis...MAPC, uses parametric models and scaling to create high level designs of various hull types. The inputs are desired speed , range, payload, sea state...reached 10 SWATH vessels exhibit superior seakeeping at near zero speed compared to other hull forms 5 Assumes 2 equal-sized GE Gas Turbines 11

  12. CMOS array design automation techniques

    NASA Technical Reports Server (NTRS)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  13. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  14. Broadband terahertz imaging with highly sensitive silicon CMOS detectors.

    PubMed

    Schuster, Franz; Coquillat, Dominique; Videlier, Hadley; Sakowicz, Maciej; Teppe, Frédéric; Dussopt, Laurent; Giffard, Benoît; Skotnicki, Thomas; Knap, Wojciech

    2011-04-11

    This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric window around 300 GHz and at room temperature. We demonstrate furthermore that the same detectors are efficient for imaging in a very wide frequency range from ~0.27 THz up to 1.05 THz. These results pave the way towards high sensitivity focal plane arrays in silicon for terahertz imaging.

  15. Cryogenic CMOS cameras for high voltage monitoring in liquid argon

    NASA Astrophysics Data System (ADS)

    McConkey, N.; Spooner, N.; Thiesse, M.; Wallbank, M.; Warburton, T. K.

    2017-03-01

    The prevalent use of large volume liquid argon detectors strongly motivates the development of novel readout and monitoring technology which functions at cryogenic temperatures. This paper presents the development of a cryogenic CMOS camera system suitable for use inside a large volume liquid argon detector for online monitoring purposes. The characterisation of the system is described in detail. The reliability of such a camera system has been demonstrated over several months, and recent data from operation within the liquid argon region of the DUNE 35 t cryostat is presented. The cameras were used to monitor for high voltage breakdown inside the cryostat, with capability to observe breakdown of a liquid argon time projection chamber in situ. They were also used for detector monitoring, especially of components during cooldown.

  16. High-Speed Electrochemical Imaging.

    PubMed

    Momotenko, Dmitry; Byers, Joshua C; McKelvey, Kim; Kang, Minkyung; Unwin, Patrick R

    2015-09-22

    The design, development, and application of high-speed scanning electrochemical probe microscopy is reported. The approach allows the acquisition of a series of high-resolution images (typically 1000 pixels μm(-2)) at rates approaching 4 seconds per frame, while collecting up to 8000 image pixels per second, about 1000 times faster than typical imaging speeds used up to now. The focus is on scanning electrochemical cell microscopy (SECCM), but the principles and practicalities are applicable to many electrochemical imaging methods. The versatility of the high-speed scan concept is demonstrated at a variety of substrates, including imaging the electroactivity of a patterned self-assembled monolayer on gold, visualization of chemical reactions occurring at single wall carbon nanotubes, and probing nanoscale electrocatalysts for water splitting. These studies provide movies of spatial variations of electrochemical fluxes as a function of potential and a platform for the further development of high speed scanning with other electrochemical imaging techniques.

  17. SEAL FOR HIGH SPEED CENTRIFUGE

    DOEpatents

    Skarstrom, C.W.

    1957-12-17

    A seal is described for a high speed centrifuge wherein the centrifugal force of rotation acts on the gasket to form a tight seal. The cylindrical rotating bowl of the centrifuge contains a closure member resting on a shoulder in the bowl wall having a lower surface containing bands of gasket material, parallel and adjacent to the cylinder wall. As the centrifuge speed increases, centrifugal force acts on the bands of gasket material forcing them in to a sealing contact against the cylinder wall. This arrangememt forms a simple and effective seal for high speed centrifuges, replacing more costly methods such as welding a closure in place.

  18. Gated high speed optical detector

    NASA Technical Reports Server (NTRS)

    Green, S. I.; Carson, L. M.; Neal, G. W.

    1973-01-01

    The design, fabrication, and test of two gated, high speed optical detectors for use in high speed digital laser communication links are discussed. The optical detectors used a dynamic crossed field photomultiplier and electronics including dc bias and RF drive circuits, automatic remote synchronization circuits, automatic gain control circuits, and threshold detection circuits. The equipment is used to detect binary encoded signals from a mode locked neodynium laser.

  19. High speed optical networks

    NASA Astrophysics Data System (ADS)

    Frankel, Michael Y.; Livas, Jeff

    2005-02-01

    This overview will discuss core network technology and cost trade-offs inherent in choosing between "analog" architectures with high optical transparency, and ones heavily dependent on frequent "digital" signal regeneration. The exact balance will be related to the specific technology choices in each area outlined above, as well as the network needs such as node geographic spread, physical connectivity patterns, and demand loading. Over the course of a decade, optical networks have evolved from simple single-channel SONET regenerator-based links to multi-span multi-channel optically amplified ultra-long haul systems, fueled by high demand for bandwidth at reduced cost. In general, the cost of a well-designed high capacity system is dominated by the number of optical to electrical (OE) and electrical to optical (EO) conversions required. As the reach and channel capacity of the transport systems continued to increase, it became necessary to improve the granularity of the demand connections by introducing (optical add/drop multiplexers) OADMs. Thus, if a node requires only small demand connectivity, most of the optical channels are expressed through without regeneration (OEO). The network costs are correspondingly reduced, partially balanced by the increased cost of the OADM nodes. Lately, the industry has been aggressively pursuing a natural extension of this philosophy towards all-optical "analog" core networks, with each demand touching electrical digital circuitry only at the in/egress nodes. This is expected to produce a substantial elimination of OEO costs, increase in network capacity, and a notionally simpler operation and service turn-up. At the same time, such optical "analog" network requires a large amount of complicated hardware and software for monitoring and manipulating high bit rate optical signals. New and more complex modulation formats that provide resiliency to both optical noise and nonlinear propagation effects are important for extended

  20. Flexible high speed CODEC

    NASA Technical Reports Server (NTRS)

    Wernlund, James V.

    1993-01-01

    HARRIS, under contract with NASA Lewis, has developed a hard decision BCH (Bose-Chaudhuri-Hocquenghem) triple error correcting block CODEC ASIC, that can be used in either a bursted or continuous mode. the ASIC contains both encoder and decoder functions, programmable lock thresholds, and PSK related functions. The CODEC provides up to 4 dB of coding gain for data rates up to 300 Mbps. The overhead is selectable from 7/8 to 15/16 resulting in minimal band spreading, for a given BER. Many of the internal calculations are brought out enabling the CODEC to be incorporated in more complex designs. The ASIC has been tested in BPSK, QPSK and 16-ary PSK link simulators and found to perform to within 0.1 dB of theory for BER's of 10(exp -2) to 10(exp -9). The ASIC itself, being a hard decision CODEC, is not limited to PSK modulation formats. Unlike most hard decision CODEC's, the HARRIS CODEC doesn't upgrade BER performance significantly at high BER's but rather becomes transparent.

  1. Multi-aperture ultra-high-speed imaging with lateral electric field charge modulators

    NASA Astrophysics Data System (ADS)

    Kagawa, K.; Mochizuki, F.; Seo, M.-W.; Yasutomi, K.; Kawahito, S.

    2016-03-01

    The time resolution of charge modulation in CMOS image sensors has entered the sub-nano second regime and is still reducing toward tens of pico-second. The lateral electric field modulators (LEFM) invented at Shizuoka University has significantly contributed to the recent progress in the solid-state time-resolved imaging field. Based on the LEFM technology, we are developing ultra-high-speed CMOS image sensors whose frame rate or time resolution is determined only by the charge modulation speed. In this presentation, the concept, architecture, example of implementation, and demonstration of 200Mfps single-shot video capturing based on our scheme are shown.

  2. CMOS monolithic active pixel sensors for high energy physics

    NASA Astrophysics Data System (ADS)

    Snoeys, W.

    2014-11-01

    Monolithic pixel detectors integrating sensor matrix and readout in one piece of silicon are only now starting to make their way into high energy physics. Two major requirements are radiation tolerance and low power consumption. For the most extreme radiation levels, signal charge has to be collected by drift from a depletion layer onto a designated collection electrode without losing the signal charge elsewhere in the in-pixel circuit. Low power consumption requires an optimization of Q/C, the ratio of the collected signal charge over the input capacitance [1]. Some solutions to combine sufficient Q/C and collection by drift require exotic fabrication steps. More conventional solutions up to now require a simple in-pixel readout circuit. Both high voltage CMOS technologies and Monolithic Active Pixel Sensors (MAPS) technologies with high resistivity epitaxial layers offer high voltage diodes. The choice between the two is not fundamental but more a question of how much depletion can be reached and also of availability and cost. This paper tries to give an overview.

  3. Correct CMOS IC defect models for quality testing

    NASA Technical Reports Server (NTRS)

    Soden, Jerry M.; Hawkins, Charles F.

    1993-01-01

    Leading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.

  4. High-frequency BiCMOS transconductance integrators

    NASA Astrophysics Data System (ADS)

    Beards, R. Douglas

    1990-10-01

    The capabilities of a fine-line bipolar complementary metal oxide semiconductor (BiCMOS) process in the design of wideband transconductance integrators for precision monolithic continuous time filtering are explored. The design considerations of such an integrator are examined in detail, with an emphasis on tunability and phase compensation as a means for realizing a precision wideband design. The concept of open-loop transconductance filtering is described and possible circuit topologies are investigated. Detailed small-signal and large-signal analysis of one proposed circuit which has both tunable bandwidth and tunable phase compensation is presented. Application of such an integrator to open-loop transconductance filtering in the 10-50 MHz frequency range is studied. Simulation results show specific performance expectations of the proposed circuit. The tunable compensation circuit was seen to restrict the amplitude of signals which the integrator can pass without severe distortion or even instability occurring. A potential solution to this problem is deemed to be unsuitable for high frequency applications. The general design philosophy of applying low-frequency techniques to realize a high frequency circuit was seen to result in several fundamental problems.

  5. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    PubMed

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging.

  6. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  7. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    NASA Astrophysics Data System (ADS)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  8. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    PubMed

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-06

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  9. High speed multiwire photon camera

    NASA Technical Reports Server (NTRS)

    Lacy, Jeffrey L. (Inventor)

    1991-01-01

    An improved multiwire proportional counter camera having particular utility in the field of clinical nuclear medicine imaging. The detector utilizes direct coupled, low impedance, high speed delay lines, the segments of which are capacitor-inductor networks. A pile-up rejection test is provided to reject confused events otherwise caused by multiple ionization events occuring during the readout window.

  10. High speed multiwire photon camera

    NASA Technical Reports Server (NTRS)

    Lacy, Jeffrey L. (Inventor)

    1989-01-01

    An improved multiwire proportional counter camera having particular utility in the field of clinical nuclear medicine imaging. The detector utilizes direct coupled, low impedance, high speed delay lines, the segments of which are capacitor-inductor networks. A pile-up rejection test is provided to reject confused events otherwise caused by multiple ionization events occurring during the readout window.

  11. Hardware-based image processing for high-speed inspection of grains

    USDA-ARS?s Scientific Manuscript database

    A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

  12. High-speed sorting of grains by color and surface texture

    USDA-ARS?s Scientific Manuscript database

    A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

  13. A CMOS floating point multiplier

    NASA Astrophysics Data System (ADS)

    Uya, M.; Kaneko, K.; Yasui, J.

    1984-10-01

    This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

  14. Experiments on high speed ejectors

    NASA Technical Reports Server (NTRS)

    Wu, J. J.

    1986-01-01

    Experimental studies were conducted to investigate the flow and the performance of thrust augmenting ejectors for flight Mach numbers in the range of 0.5 to 0.8, primary air stagnation pressures up to 107 psig (738 kPa), and primary air stagnation temperatures up to 1250 F (677 C). The experiment verified the existence of the second solution ejector flow, where the flow after complete mixing is supersonic. Thrust augmentation in excess of 1.2 was demonstrated for both hot and cold primary jets. The experimental ejector performed better than the corresponding theoretical optimal first solution ejector, where the mixed flow is subsonic. Further studies are required to realize the full potential of the second solution ejector. The research program was started by the Flight Dynamics Research Corporation (FDRC) to investigate the characteristic of a high speed ejector which augments thrust of a jet at high flight speeds.

  15. Small Scale High Speed Turbomachinery

    NASA Technical Reports Server (NTRS)

    London, Adam P. (Inventor); Droppers, Lloyd J. (Inventor); Lehman, Matthew K. (Inventor); Mehra, Amitav (Inventor)

    2015-01-01

    A small scale, high speed turbomachine is described, as well as a process for manufacturing the turbomachine. The turbomachine is manufactured by diffusion bonding stacked sheets of metal foil, each of which has been pre-formed to correspond to a cross section of the turbomachine structure. The turbomachines include rotating elements as well as static structures. Using this process, turbomachines may be manufactured with rotating elements that have outer diameters of less than four inches in size, and/or blading heights of less than 0.1 inches. The rotating elements of the turbomachines are capable of rotating at speeds in excess of 150 feet per second. In addition, cooling features may be added internally to blading to facilitate cooling in high temperature operations.

  16. High Speed Photometry for BUSCA

    NASA Astrophysics Data System (ADS)

    Cordes, O.; Reif, K.

    The camera BUSCA (Bonn University Simultaneous CAmera) is a standard instrument at the 2.2m telescope at Calar Alto Observatory (Spain) since 2001. At the moment some modifications of BUSCA are planned and partially realised. One major goal is the replacement of the old thick CCDs in the blue, yellow-green, and near-infrared channels. The newer CCDs have better cosmetics and performance in sensitivity. The other goal is to replace the old "Heidelberg"-style controller with a newly designed controller with the main focus on high-speed readout and on an advanced windowing mechanism. We present a theoretical analysis of the new controller design and its advantage in high speed photometry of rapidly pulsating stars. As an example PG1605+072 was chosen which was observed with BUSCA before in 2001 and 2002.

  17. High-speed rotorcraft propulsion

    NASA Technical Reports Server (NTRS)

    Rutherford, John W.; Fitzpatrick, Robert E.

    1991-01-01

    Recently completed high-speed rotorcraft design studies for NASA provide the basis to assess technology needs for the development of these aircraft. Preliminary analysis of several concepts possessing helicopter-like hover characteristics and cruise capabilities in the 450 knot regime, led to the selection of two concepts for further study. The concepts selected included the Rotor/Wing and the Tilt Wing. The two unique concepts use turbofan and turboshaft engines respectively. Designs, based on current technology for each, established a baseline configuration from which technology trade studies could be conducted. Propulsion technology goals from the IHPTET program established the advanced technolgy year. Due to high-speed requirements, each concept possesses its own unique propulsion challenges. Trade studies indicate that achieving th IHPTET Phase III goals significantly improves the effectiveness of both concepts. Increased engine efficiency is particularly important to VTOL aircraft by reducing gross weight.

  18. High-speed code validation

    NASA Technical Reports Server (NTRS)

    Barnwell, Richard W.; Rogers, R. Clayton; Pittman, James L.; Dwoyer, Douglas L.

    1987-01-01

    The topics are presented in viewgraph form and include the following: NFL body experiment; high-speed validation problems; 3-D Euler/Navier-Stokes inlet code; two-strut inlet configuration; pressure contours in two longitudinal planes; sidewall pressure distribution; pressure distribution on strut inner surface; inlet/forebody tests in 60 inch helium tunnel; pressure distributions on elliptical missile; code validations; small scale test apparatus; CARS nonintrusive measurements; optimized cone-derived waverider study; etc.

  19. High Speed Holographic Movie Camera

    NASA Astrophysics Data System (ADS)

    Hentschel, W.; Lauterborn, W.

    1985-08-01

    A high speed holographic movie camera system has been developed to investigate the dynamic behavior of cavitation bubbles in liquids. As a light source for holography, a high power multiply cavity-dumped argonion laser is used to record very long hologram series with framing rates up to 300 kHz. For separating successively recorded holograms, two spatial multiplexing techniques are applied simultaneously: rotation of the holographic plate or film and acousto-optic beam deflection. With the combination of these two techniques we achieve up to 4000 single holograms in one series.

  20. High Speed Holographic Movie Camera

    NASA Astrophysics Data System (ADS)

    Hentschel, W.; Lauterborn, W.

    1985-02-01

    A high speed holographic movie camera system has been developed in our laboratories at the Third Physical Institute of the University of Gdttingen. As a light source for holography a high power multiply cavity-dumped argonion laser is used to record very long hologram series with framing rates up to 300 kHz. For separating successively recorded holograms two spatial multiplexing techniques are applied simultaneously: rotating of the holographic plate or film and acousto-optic beam deflection. With the combination of these two techniques we achieve up to 4000 single holograms in one series.

  1. High-Speed TCP Testing

    NASA Technical Reports Server (NTRS)

    Brooks, David E.; Gassman, Holly; Beering, Dave R.; Welch, Arun; Hoder, Douglas J.; Ivancic, William D.

    1999-01-01

    Transmission Control Protocol (TCP) is the underlying protocol used within the Internet for reliable information transfer. As such, there is great interest to have all implementations of TCP efficiently interoperate. This is particularly important for links exhibiting long bandwidth-delay products. The tools exist to perform TCP analysis at low rates and low delays. However, for extremely high-rate and lone-delay links such as 622 Mbps over geosynchronous satellites, new tools and testing techniques are required. This paper describes the tools and techniques used to analyze and debug various TCP implementations over high-speed, long-delay links.

  2. Quiet High-Speed Fan

    NASA Technical Reports Server (NTRS)

    Lieber, Lysbeth; Repp, Russ; Weir, Donald S.

    1996-01-01

    A calibration of the acoustic and aerodynamic prediction methods was performed and a baseline fan definition was established and evaluated to support the quiet high speed fan program. A computational fluid dynamic analysis of the NASA QF-12 Fan rotor, using the DAWES flow simulation program was performed to demonstrate and verify the causes of the relatively poor aerodynamic performance observed during the fan test. In addition, the rotor flowfield characteristics were qualitatively compared to the acoustic measurements to identify the key acoustic characteristics of the flow. The V072 turbofan source noise prediction code was used to generate noise predictions for the TFE731-60 fan at three operating conditions and compared to experimental data. V072 results were also used in the Acoustic Radiation Code to generate far field noise for the TFE731-60 nacelle at three speed points for the blade passage tone. A full 3-D viscous flow simulation of the current production TFE731-60 fan rotor was performed with the DAWES flow analysis program. The DAWES analysis was used to estimate the onset of multiple pure tone noise, based on predictions of inlet shock position as a function of the rotor tip speed. Finally, the TFE731-60 fan rotor wake structure predicted by the DAWES program was used to define a redesigned stator with the leading edge configured to minimize the acoustic effects of rotor wake / stator interaction, without appreciably degrading performance.

  3. High-speed phosphor thermometry.

    PubMed

    Fuhrmann, N; Baum, E; Brübach, J; Dreizler, A

    2011-10-01

    Phosphor thermometry is a semi-invasive surface temperature measurement technique utilising the luminescence properties of doped ceramic materials. Typically, these phosphor materials are coated onto the object of interest and are excited by a short UV laser pulse. Up to now, primarily Q-switched laser systems with repetition rates of 10 Hz were employed for excitation. Accordingly, this diagnostic tool was not applicable to resolve correlated temperature transients at time scales shorter than 100 ms. This contribution reports on the first realisation of a high-speed phosphor thermometry system employing a highly repetitive laser in the kHz regime and a fast decaying phosphor. A suitable material was characterised regarding its temperature lifetime characteristic and its measurement precision. Additionally, the influence of laser power on the phosphor coating was investigated in terms of heating effects. A demonstration of this high-speed technique has been conducted inside the thermally highly transient system of an optically accessible internal combustion engine. Temperatures have been measured with a repetition rate of 6 kHz corresponding to one sample per crank angle degree at 1000 rpm.

  4. High-speed phosphor thermometry

    NASA Astrophysics Data System (ADS)

    Fuhrmann, N.; Baum, E.; Brübach, J.; Dreizler, A.

    2011-10-01

    Phosphor thermometry is a semi-invasive surface temperature measurement technique utilising the luminescence properties of doped ceramic materials. Typically, these phosphor materials are coated onto the object of interest and are excited by a short UV laser pulse. Up to now, primarily Q-switched laser systems with repetition rates of 10 Hz were employed for excitation. Accordingly, this diagnostic tool was not applicable to resolve correlated temperature transients at time scales shorter than 100 ms. This contribution reports on the first realisation of a high-speed phosphor thermometry system employing a highly repetitive laser in the kHz regime and a fast decaying phosphor. A suitable material was characterised regarding its temperature lifetime characteristic and its measurement precision. Additionally, the influence of laser power on the phosphor coating was investigated in terms of heating effects. A demonstration of this high-speed technique has been conducted inside the thermally highly transient system of an optically accessible internal combustion engine. Temperatures have been measured with a repetition rate of 6 kHz corresponding to one sample per crank angle degree at 1000 rpm.

  5. Development of High Speed Digital Camera: EXILIM EX-F1

    NASA Astrophysics Data System (ADS)

    Nojima, Osamu

    The EX-F1 is a high speed digital camera featuring a revolutionary improvement in burst shooting speed that is expected to create entirely new markets. This model incorporates a high speed CMOS sensor and a high speed LSI processor. With this model, CASIO has achieved an ultra-high speed 60 frames per second (fps) burst rate for still images, together with 1,200 fps high speed movie that captures movements which cannot even be seen by human eyes. Moreover, this model can record movies at full High-Definition. After launching it into the market, it was able to get a lot of high appraisals as an innovation camera. We will introduce the concept, features and technologies about the EX-F1.

  6. High aspect ratio sharp nanotip for nanocantilever integration at CMOS compatible temperature

    NASA Astrophysics Data System (ADS)

    Wang, P.; Michael, A.; Kwok, CY

    2017-08-01

    In this paper, we demonstrate a novel low temperature nanofabrication approach that enables the formation of ultra-sharp high aspect ratio (HAR) and high density nanotip structures and their integration onto nanoscale cantilever beams. The nanotip structure consists of a nanoscale thermally evaporated Cr Spindt tip on top of an amorphous silicon rod. An apex radius of the tip, as small as 2.5 nm, has been achieved, and is significantly smaller than any other Spindt tips reported so far. 100 nm wide tips with aspect ratio of more than 50 and tip density of more than 5 × 109 tips cm-2 have been fabricated. The HAR tips have been integrated onto an array of 460 nm wide cantilever beams with high precision and yield. In comparison with other approaches, this approach allows the integration of HAR sharp nanotips with nano-mechanical structures in a parallel and CMOS compatible fashion for the first time to our knowledge. Potential applications include on-chip high-speed atomic force microscopy and field emission devices.

  7. High aspect ratio sharp nanotip for nanocantilever integration at CMOS compatible temperature.

    PubMed

    Wang, P; Michael, A; Kwok, C Y

    2017-08-11

    In this paper, we demonstrate a novel low temperature nanofabrication approach that enables the formation of ultra-sharp high aspect ratio (HAR) and high density nanotip structures and their integration onto nanoscale cantilever beams. The nanotip structure consists of a nanoscale thermally evaporated Cr Spindt tip on top of an amorphous silicon rod. An apex radius of the tip, as small as 2.5 nm, has been achieved, and is significantly smaller than any other Spindt tips reported so far. 100 nm wide tips with aspect ratio of more than 50 and tip density of more than 5 × 10(9) tips cm(-2) have been fabricated. The HAR tips have been integrated onto an array of 460 nm wide cantilever beams with high precision and yield. In comparison with other approaches, this approach allows the integration of HAR sharp nanotips with nano-mechanical structures in a parallel and CMOS compatible fashion for the first time to our knowledge. Potential applications include on-chip high-speed atomic force microscopy and field emission devices.

  8. High speed quantitative digital microscopy

    NASA Technical Reports Server (NTRS)

    Castleman, K. R.; Price, K. H.; Eskenazi, R.; Ovadya, M. M.; Navon, M. A.

    1984-01-01

    Modern digital image processing hardware makes possible quantitative analysis of microscope images at high speed. This paper describes an application to automatic screening for cervical cancer. The system uses twelve MC6809 microprocessors arranged in a pipeline multiprocessor configuration. Each processor executes one part of the algorithm on each cell image as it passes through the pipeline. Each processor communicates with its upstream and downstream neighbors via shared two-port memory. Thus no time is devoted to input-output operations as such. This configuration is expected to be at least ten times faster than previous systems.

  9. A high speed sequential decoder

    NASA Technical Reports Server (NTRS)

    Lum, H., Jr.

    1972-01-01

    The performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.

  10. High speed holographic digital recorder.

    PubMed

    Roberts, H N; Watkins, J W; Johnson, R H

    1974-04-01

    Concepts, feasibility experiments, and key component developments are described for a holographic digital record/reproduce system with the potential for 1.0 Gbit/sec rates and higher. Record rates of 500 Mbits/sec have been demonstrated with a ten-channel acoustooptic modulator array and a mode-locked, cavity-dumped argon-ion laser. Acoustooptic device technology has been advanced notably during the development of mode lockers, cavity dumpers, beam deflectors, and multichannel modulator arrays. The development of high speed multichannel photodetector arrays for the readout subsystem requires special attention. The feasibility of 1.0 Gbits/sec record rates has been demonstrated.

  11. Flexible high-speed CODEC

    NASA Technical Reports Server (NTRS)

    Segallis, Greg P.; Wernlund, Jim V.; Corry, Glen

    1993-01-01

    This report is prepared by Harris Government Communication Systems Division for NASA Lewis Research Center under contract NAS3-25087. It is written in accordance with SOW section 4.0 (d) as detailed in section 2.6. The purpose of this document is to provide a summary of the program, performance results and analysis, and a technical assessment. The purpose of this program was to develop a flexible, high-speed CODEC that provides substantial coding gain while maintaining bandwidth efficiency for use in both continuous and bursted data environments for a variety of applications.

  12. High speed quantitative digital microscopy

    NASA Technical Reports Server (NTRS)

    Castleman, K. R.; Price, K. H.; Eskenazi, R.; Ovadya, M. M.; Navon, M. A.

    1984-01-01

    Modern digital image processing hardware makes possible quantitative analysis of microscope images at high speed. This paper describes an application to automatic screening for cervical cancer. The system uses twelve MC6809 microprocessors arranged in a pipeline multiprocessor configuration. Each processor executes one part of the algorithm on each cell image as it passes through the pipeline. Each processor communicates with its upstream and downstream neighbors via shared two-port memory. Thus no time is devoted to input-output operations as such. This configuration is expected to be at least ten times faster than previous systems.

  13. Characterisation of novel prototypes of monolithic HV-CMOS pixel detectors for high energy physics experiments

    NASA Astrophysics Data System (ADS)

    Terzo, S.; Cavallaro, E.; Casanova, R.; Di Bello, F.; Förster, F.; Grinstein, S.; Períc, I.; Puigdengoles, C.; Ristić, B.; Barrero Pinto, M. Vicente; Vilella, E.

    2017-06-01

    An upgrade of the ATLAS experiment for the High Luminosity phase of LHC is planned for 2024 and foresees the replacement of the present Inner Detector (ID) with a new Inner Tracker (ITk) completely made of silicon devices. Depleted active pixel sensors built with the High Voltage CMOS (HV-CMOS) technology are investigated as an option to cover large areas in the outermost layers of the pixel detector and are especially interesting for the development of monolithic devices which will reduce the production costs and the material budget with respect to the present hybrid assemblies. For this purpose the H35DEMO, a large area HV-CMOS demonstrator chip, was designed by KIT, IFAE and University of Liverpool, and produced in AMS 350 nm CMOS technology. It consists of four pixel matrices and additional test structures. Two of the matrices include amplifiers and discriminator stages and are thus designed to be operated as monolithic detectors. In these devices the signal is mainly produced by charge drift in a small depleted volume obtained by applying a bias voltage of the order of 100V. Moreover, to enhance the radiation hardness of the chip, this technology allows to enclose the electronics in the same deep N-WELLs which are also used as collecting electrodes. In this contribution the characterisation of H35DEMO chips and results of the very first beam test measurements of the monolithic CMOS matrices with high energetic pions at CERN SPS will be presented.

  14. A Synchronization Algorithm and Implementation for High-Speed Block Codes Applications. Part 4

    NASA Technical Reports Server (NTRS)

    Lin, Shu; Zhang, Yu; Nakamura, Eric B.; Uehara, Gregory T.

    1998-01-01

    Block codes have trellis structures and decoders amenable to high speed CMOS VLSI implementation. For a given CMOS technology, these structures enable operating speeds higher than those achievable using convolutional codes for only modest reductions in coding gain. As a result, block codes have tremendous potential for satellite trunk and other future high-speed communication applications. This paper describes a new approach for implementation of the synchronization function for block codes. The approach utilizes the output of the Viterbi decoder and therefore employs the strength of the decoder. Its operation requires no knowledge of the signal-to-noise ratio of the received signal, has a simple implementation, adds no overhead to the transmitted data, and has been shown to be effective in simulation for received SNR greater than 2 dB.

  15. CMOS compatible high-Q photonic crystal nanocavity fabricated with photolithography on silicon photonic platform.

    PubMed

    Ooka, Yuta; Tetsumoto, Tomohiro; Fushimi, Akihiro; Yoshiki, Wataru; Tanabe, Takasumi

    2015-06-18

    Progress on the fabrication of ultrahigh-Q photonic-crystal nanocavities (PhC-NCs) has revealed the prospect for new applications including silicon Raman lasers that require a strong confinement of light. Among various PhC-NCs, the highest Q has been recorded with silicon. On the other hand, microcavity is one of the basic building blocks in silicon photonics. However, the fusion between PhC-NCs and silicon photonics has yet to be exploited, since PhC-NCs are usually fabricated with electron-beam lithography and require an air-bridge structure. Here we show that a 2D-PhC-NC fabricated with deep-UV photolithography on a silica-clad silicon-on-insulator (SOI) structure will exhibit a high-Q of 2.2 × 10(5) with a mode-volume of ~ 1.7(λ/n)(3). This is the highest Q demonstrated with photolithography. We also show that this device exhibits an efficient thermal diffusion and enables high-speed switching. The demonstration of the photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices.

  16. CMOS compatible high-Q photonic crystal nanocavity fabricated with photolithography on silicon photonic platform

    PubMed Central

    Ooka, Yuta; Tetsumoto, Tomohiro; Fushimi, Akihiro; Yoshiki, Wataru; Tanabe, Takasumi

    2015-01-01

    Progress on the fabrication of ultrahigh-Q photonic-crystal nanocavities (PhC-NCs) has revealed the prospect for new applications including silicon Raman lasers that require a strong confinement of light. Among various PhC-NCs, the highest Q has been recorded with silicon. On the other hand, microcavity is one of the basic building blocks in silicon photonics. However, the fusion between PhC-NCs and silicon photonics has yet to be exploited, since PhC-NCs are usually fabricated with electron-beam lithography and require an air-bridge structure. Here we show that a 2D-PhC-NC fabricated with deep-UV photolithography on a silica-clad silicon-on-insulator (SOI) structure will exhibit a high-Q of 2.2 × 105 with a mode-volume of ~1.7(λ/n)3. This is the highest Q demonstrated with photolithography. We also show that this device exhibits an efficient thermal diffusion and enables high-speed switching. The demonstration of the photolithographic fabrication of high-Q silica-clad PhC-NCs will open possibility for mass-manufacturing and boost the fusion between silicon photonics and CMOS devices. PMID:26086849

  17. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    SciTech Connect

    Benoit, M.; de Mendizabal, J. Bilbao; Casse, G.; Chen, H.; Chen, K.; Bello, F. A. Di; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Pinto, M. Vicente Barrero; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-21

    We investigated the active pixel sensors based on the High-Voltage CMOS technology as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. Our paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. These results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  18. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  19. Remote Transmission at High Speed

    NASA Technical Reports Server (NTRS)

    2003-01-01

    Omni and NASA Test Operations at Stennis entered a Dual-Use Agreement to develop the FOTR-125, a 125 megabit-per-second fiber-optic transceiver that allows accurate digital recordings over a great distance. The transceiver s fiber-optic link can be as long as 25 kilometers. This makes it much longer than the standard coaxial link, which can be no longer than 50 meters.The FOTR-125 utilizes laser diode transmitter modules and integrated receivers for the optical interface. Two transmitters and two receivers are employed at each end of the link with automatic or manual switchover to maximize the reliability of the communications link. NASA uses the transceiver in Stennis High-Speed Data Acquisition System (HSDAS). The HSDAS consists of several identical systems installed on the Center s test stands to process all high-speed data related to its propulsion test programs. These transceivers allow the recorder and HSDAS controls to be located in the Test Control Center in a remote location while the digitizer is located on the test stand.

  20. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    PubMed

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics.

  1. Design of optoelectronic imaging system with high resolution and large field-of-view based on dual CMOS

    NASA Astrophysics Data System (ADS)

    Cheng, Hanglin; Hao, Qun; Hu, Yao; Cao, Jie; Wang, Shaopu; Li, Lin

    2016-10-01

    With the advantages of high resolution, large field of view and compacted size, optoelectronic imaging sensors are widely used in many fields, such as robot's navigation, industrial measurement and remote sensing. Many researchers pay more attention to improve the comprehensive performances of imaging sensors, including large field of view (FOV), high resolution, compact size and high imaging efficiency, etc. One challenge is the tradeoff between high resolution and large field of view simultaneously considering compacted size. In this paper, we propose an optoelectronic imaging system combining the lenses of short focal length and long focal length based on dual CMOS to simulate the characters of human eyes which observe object within large FOV in high resolution. We design and optimize the two lens, the lens of short focal length is used to search object in a wide field and the long one is responsible for high resolution imaging of the target area. Based on a micro-CMOS imaging sensor with low voltage differential transmission technology-MIPI (Mobile Industry Processor Interface), we design the corresponding circuits to realize collecting optical information with high speed. The advantage of the interface is to help decreasing power consumption, improving transmission efficiency and achieving compacted size of imaging sensor. Meanwhile, we carried out simulations and experiments to testify the optoelectronic imaging system. The results show that the proposed method is helpful to improve the comprehensive performances of optoelectronic imaging sensors.

  2. Use of CMOS imagers to measure high fluxes of charged particles

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Tucceri, P.

    2016-03-01

    The measurement of high flux charged particle beams, specifically at medical accelerators and with small fields, poses several challenges. In this work we propose a single particle counting method based on CMOS imagers optimized for visible light collection, exploiting their very high spatial segmentation (> 3 106 pixels/cm2) and almost full efficiency detection capability. An algorithm to measure the charged particle flux with a precision of ~ 1% for fluxes up to 40 MHz/cm2 has been developed, using a non-linear calibration algorithm, and several CMOS imagers with different characteristics have been compared to find their limits on flux measurement.

  3. High-stage analog accumulator for TDI CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  4. High-Speed Schlieren Movies of Decelerators at Supersonic Speeds

    NASA Technical Reports Server (NTRS)

    1960-01-01

    High-Speed Schlieren Movies of Decelerators at Supersonic Speeds. Tests were conducted on several types of porous parachutes, a paraglider, and a simulated retrorocket. Mach numbers ranged from 1.8-3.0, porosity from 20-80 percent, and camera speeds from 1680-3000 feet per second (fps) in trials with porous parachutes. Trials of reefed parachutes were conducted at Mach number 2.0 and reefing of 12-33 percent at camera speeds of 600 fps. A flexible parachute with an inflatable ring in the periphery of the canopy was tested at Reynolds number 750,000 per foot, Mach number 2.85, porosity of 28 percent, and camera speed of 36oo fps. A vortex-ring parachute was tested at Mach number 2.2 and camera speed of 3000 fps. The paraglider, with a sweepback of 45 degrees at an angle of attack of 45 degrees was tested at Mach number 2.65, drag coefficient of 0.200, and lift coefficient of 0.278 at a camera speed of 600 fps. A cold air jet exhausting upstream from the center of a bluff body was used to simulate a retrorocket. The free-stream Mach number was 2.0, free-stream dynamic pressure was 620 lb/sq ft, jet-exit static pressure ratio was 10.9, and camera speed was 600 fps. [Entire movie available on DVD from CASI as Doc ID 20070030973. Contact help@sti.nasa.gov

  5. High-speed data search

    NASA Technical Reports Server (NTRS)

    Driscoll, James N.

    1994-01-01

    The high-speed data search system developed for KSC incorporates existing and emerging information retrieval technology to help a user intelligently and rapidly locate information found in large textual databases. This technology includes: natural language input; statistical ranking of retrieved information; an artificial intelligence concept called semantics, where 'surface level' knowledge found in text is used to improve the ranking of retrieved information; and relevance feedback, where user judgements about viewed information are used to automatically modify the search for further information. Semantics and relevance feedback are features of the system which are not available commercially. The system further demonstrates focus on paragraphs of information to decide relevance; and it can be used (without modification) to intelligently search all kinds of document collections, such as collections of legal documents medical documents, news stories, patents, and so forth. The purpose of this paper is to demonstrate the usefulness of statistical ranking, our semantic improvement, and relevance feedback.

  6. Flexible High Speed Codec (FHSC)

    NASA Technical Reports Server (NTRS)

    Segallis, G. P.; Wernlund, J. V.

    1991-01-01

    The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

  7. Preliminary study of high-speed machining

    SciTech Connect

    Jordan, R.E.

    1980-07-01

    The feasibility of a high speed machining process has been established for application to Bendix aluminum products, based upon information gained through visits to existing high speed machining facilities and by the completion of a representative Bendix part using this process. The need for an experimental high speed machining capability at Bendix for further process evaluation is established.

  8. High speed sampler and demultiplexer

    DOEpatents

    McEwan, T.E.

    1995-12-26

    A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length. Second tier demultiplexing circuitry is coupled to each of the samplers in the plurality of banks. The second tier demultiplexing circuitry senses the sample taken by the corresponding sampler each time the bank in which the sampler is found is strobed. A plurality of such samples can be stored by the second tier demultiplexing circuitry for later processing. Repetitive sampling with the high speed transient sampler induces an effect known as ``strobe kickout``. The sample transmission lines include structures which reduce strobe kickout to acceptable levels, generally 60 dB below the signal, by absorbing the kickout pulses before the next sampling repetition. 16 figs.

  9. High speed sampler and demultiplexer

    DOEpatents

    McEwan, Thomas E.

    1995-01-01

    A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length. Second tier demultiplexing circuitry is coupled to each of the samplers in the plurality of banks. The second tier demultiplexing circuitry senses the sample taken by the corresponding sampler each time the bank in which the sampler is found is strobed. A plurality of such samples can be stored by the second tier demultiplexing circuitry for later processing. Repetitive sampling with the high speed transient sampler induces an effect known as "strobe kickout". The sample transmission lines include structures which reduce strobe kickout to acceptable levels, generally 60 dB below the signal, by absorbing the kickout pulses before the next sampling repetition.

  10. Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

    NASA Astrophysics Data System (ADS)

    Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

    2017-06-01

    Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

  11. High Precision Bright-Star Astrometry with the USNO Astrometric CMOS Hybrid Camera System

    NASA Astrophysics Data System (ADS)

    Secrest, Nathan; Dudik, Rachel; Berghea, Ciprian T.; Hennessy, Greg; Dorland, Bryan

    2015-05-01

    While GAIA will provide excellent positional measurements of hundreds of millions of stars between 5 < mag < 20, an ongoing challenge in the field of high-precision differential astrometry is the positional accuracy of very bright stars (mag < 5), due to the enormous dynamic range between bright stars of interest, such as those in the Hipparcos catalog, and their background field stars, which are especially important for differential astrometry. Over the past few years, we have been testing the USNO Astrometric CMOS Hybrid Camera System (UAHC), which utilizes an H4RG-10 detector in windowing mode, as a possible solution to the NOFS USNO Bright Star Astrometric Database (UBAD). In this work, we discuss the results of an astrometric analysis of single-epoch Hipparcos data taken with the UAHC from the 1.55m Kaj Strand Astrometric Reflector at NOFS from June 27-30, 2014. We discuss the calibration of this data, as well as an astrometric analysis pipeline we developed that will enable multi-epoch differential and absolute astrometry with the UAHC. We find that while the overall differential astrometric stability of data taken with the UAHC is good (5-10 mas single-measurement precision) and comparable to other ground-based astrometric camera systems, bright stars in the detector window suffer from several systematic effects, such as insufficient window geometry and centroiding failures due to read-out artifacts - both of which can be significantly improved with modifications to the electronics, read-out speed and microcode.

  12. CMOS capacitive biosensors for highly sensitive biosensing applications.

    PubMed

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  13. ADVANCED HIGH SPEED PROGRAMMABLE PREFORMING

    SciTech Connect

    Norris Jr, Robert E; Lomax, Ronny D; Xiong, Fue; Dahl, Jeffrey S; Blanchard, Patrick J

    2010-01-01

    Polymer-matrix composites offer greater stiffness and strength per unit weight than conventional materials resulting in new opportunities for lightweighting of automotive and heavy vehicles. Other benefits include design flexibility, less corrosion susceptibility, and the ability to tailor properties to specific load requirements. However, widespread implementation of structural composites requires lower-cost manufacturing processes than those that are currently available. Advanced, directed-fiber preforming processes have demonstrated exceptional value for rapid preforming of large, glass-reinforced, automotive composite structures. This is due to process flexibility and inherently low material scrap rate. Hence directed fiber performing processes offer a low cost manufacturing methodology for producing preforms for a variety of structural automotive components. This paper describes work conducted at the Oak Ridge National Laboratory (ORNL), focused on the development and demonstration of a high speed chopper gun to enhance throughput capabilities. ORNL and the Automotive Composites Consortium (ACC) revised the design of a standard chopper gun to expand the operational envelope, enabling delivery of up to 20kg/min. A prototype unit was fabricated and used to demonstrate continuous chopping of multiple roving at high output over extended periods. In addition fiber handling system modifications were completed to sustain the high output the modified chopper affords. These hardware upgrades are documented along with results of process characterization and capabilities assessment.

  14. Butterflies' wings deformations using high speed digital holographic interferometry

    NASA Astrophysics Data System (ADS)

    Mendoza Santoyo, Fernando; Aguayo, Daniel D.; de La Torre-Ibarra, Manuel H.; Salas-Araiza, Manuel D.

    2011-08-01

    A variety of efforts in different scientific disciplines have tried to mimic the insect's in-flight complex system. The gained knowledge has been applied to improve the performance of different flying artifacts. In this research report it is presented a displacement measurement on butterflies' wings using the optical noninvasive Digital Holographic Interferometry technique with out of plane sensitivity, using a high power cw laser and a high speed CMOS camera to record the unrepeatable displacement movements on these organic tissues. A series of digital holographic interferograms were recorded and the experimental results for several butterflies during flapping events. The relative unwrapped phase maps micro-displacements over the whole wing surface are shown in a wire-mesh representation. The difference between flying modes is remarkably depicted among them.

  15. Hypereutectoid high-speed steels

    SciTech Connect

    Kremnev, L.S.

    1986-01-01

    Half of the tungsten and molybdenum contained in R6M5 and R18 steels is concentrated in the undissolved eutectic carbides hindering austenitic grain gowth in hardening and providing the necessary strength and impact strength. This article describes the tungsten-free low-alloy high-speed steel 11M5F with a chemical composition of 1.03-1.10% C, 5.2-5.7% Mo, 3.8-4.2% Cr, 1.3-1.7% V, 0.3-0.6% Si, and 0.3% Ce. The properties of 11M5F and R6M5 steels are examined and compared. The results of production and laboratory tests of the cutting properties of tools of the steels developed showed their high effectiveness, especially of 11M5F steel with 1% A1. The life of tools of the tungsten-free steels is two or three times greater than the life of tools of R6M5 steel.

  16. High speed imager test station

    DOEpatents

    Yates, G.J.; Albright, K.L.; Turko, B.T.

    1995-11-14

    A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment. 12 figs.

  17. High speed imager test station

    DOEpatents

    Yates, George J.; Albright, Kevin L.; Turko, Bojan T.

    1995-01-01

    A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.

  18. High speed holographic cine-recorder

    NASA Astrophysics Data System (ADS)

    Snyder, Donald; Watts, David; Gordon, Joseph; Lysogorski, Charles; Powers, Aaron; Perry, John; Chenette, Eugene; Hudson, Roger; Young, Raymond

    2005-08-01

    Air Force Research Laboratory and North Dancer Labs researchers have completed the initial development and transition to operational use of a high-speed holographic movie system. This paper documents the first fully operational use of a novel and unique experimental capability for high-speed holographic movies and high-speed cinema interferometry. In this paper we document the initial experiments that were performed with the High Speed Holographic Recorder (HSHR) at the Munitions Directorate, Air Force Research Laboratory Site at Eglin, AFB, Florida. These experiments were performed to assess the possibilities for high-speed cine-laser holography combined with high-speed videography to document the formation and propagation of plumes of materials created by impact of high-speed projectiles. This paper details the development of the experimental procedures and initial results of this new tool. After successful integration and testing the system was delivered to Arnold Engineering Development Center.

  19. Advanced MOSFET technologies for high-speed circuits and EPROM

    SciTech Connect

    Wu, A.T.T.

    1987-01-01

    In the first part of the thesis, two novel source-side injection EPROM (SI-EPROM) devices capable of 5-volt only, high-speed programming are studied. Both devices are asymmetrical n-channel stacked-gate MOSFETs, each with a short weak gate-control channel region introduced close to the source. Under high gate bias, a strong-channel electric field for hot-electron generation is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region is highly favorable for hot-electron injection into the floating-gate. As a results, a programming speed of 10..mu..s at a drain voltage of 5 volts was demonstrated with one of the SI-EPROM devices fabricated. In the second part of the thesis, technology design considerations accompanying MOSFET scaling are studied for high-speed analog circuits and densely packed digital circuits. It is shown that for sub-micron technologies, especially those for CMOS, the drain/source junction capacitances dominate device parasitic capacitances in digital applications. A novel MOS device structure that employs the COO and DOO schemes is described.

  20. A very high speed lossless compression/decompression chip set

    NASA Technical Reports Server (NTRS)

    Venbrux, Jack; Liu, Norley; Liu, Kathy; Vincent, Peter; Merrell, Randy

    1991-01-01

    A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.

  1. A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell

    NASA Astrophysics Data System (ADS)

    Hsiao, Woan Yun; Mei, Chin Yu; Chao Shen, Wen; Der Chih, Yue; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This work presents a high density high-k metal gate (HKMG) one-time programmable (OTP) cell. Without additional processes and steps, this OTP cell is fully compatible to 28 nm HKMG CMOS process. The OTP cell adopts high-k dielectric breakdown as programming mechanism to obtain more than 105 times of on/off read window. Moreover, it features low power and fast program speed by 4.5 V program voltage in 100 µs. In addition to the ultrasmall cell area of 0.0425 µm2, the superior performance of disturb immunities and data retention further support the new logic OTP cell to be a very promising solution in advanced logic non-volatile memory (NVM) applications.

  2. 8-Foot High Speed Tunnel

    NASA Technical Reports Server (NTRS)

    1936-01-01

    Control panel below the test section of the 8-Foot High Speed Tunnel (8-Foot HST). Authorized July 17, 1933, construction of the 8-Foot HST was paid for with funds from the Federal Public Works Administration. Manly Hood and Russell Robinson designed the unusual facility which could produce a 500 mph wind stream across an 8-Foot test section. The concrete shell was not part of the original design. Like most projects funded through New Deal programs, the PWA restricted the amount of money which could be spent on materials. The majority of funds were supposed to be expended on labor. Though originally, Hood and Robinson had planned a welded steel pressure vessel around the test section, PWA officials proposed the idea of concrete. This picture shows the test section inside the igloo-like structure with walls of 1-foot thick reinforced concrete. The thick walls were needed 'because of the Bernoulli effect, [which meant that] the text chamber had to withstand powerful, inwardly directed pressure. Operating personnel located inside the igloo were subjected to pressures equivalent to 10,000-foot altitude and had to wear oxygen masks and enter through airlocks. A heat exchanger removed the large quantities of heat generated by the big fan.'

  3. Experimental high-speed network

    NASA Astrophysics Data System (ADS)

    McNeill, Kevin M.; Klein, William P.; Vercillo, Richard; Alsafadi, Yasser H.; Parra, Miguel V.; Dallas, William J.

    1993-09-01

    Many existing local area networking protocols currently applied in medical imaging were originally designed for relatively low-speed, low-volume networking. These protocols utilize small packet sizes appropriate for text based communication. Local area networks of this type typically provide raw bandwidth under 125 MHz. These older network technologies are not optimized for the low delay, high data traffic environment of a totally digital radiology department. Some current implementations use point-to-point links when greater bandwidth is required. However, the use of point-to-point communications for a total digital radiology department network presents many disadvantages. This paper describes work on an experimental multi-access local area network called XFT. The work includes the protocol specification, and the design and implementation of network interface hardware and software. The protocol specifies the Physical and Data Link layers (OSI layers 1 & 2) for a fiber-optic based token ring providing a raw bandwidth of 500 MHz. The protocol design and implementation of the XFT interface hardware includes many features to optimize image transfer and provide flexibility for additional future enhancements which include: a modular hardware design supporting easy portability to a variety of host system buses, a versatile message buffer design providing 16 MB of memory, and the capability to extend the raw bandwidth of the network to 3.0 GHz.

  4. High speed all optical networks

    NASA Technical Reports Server (NTRS)

    Chlamtac, Imrich; Ganz, Aura

    1990-01-01

    An inherent problem of conventional point-to-point wide area network (WAN) architectures is that they cannot translate optical transmission bandwidth into comparable user available throughput due to the limiting electronic processing speed of the switching nodes. The first solution to wavelength division multiplexing (WDM) based WAN networks that overcomes this limitation is presented. The proposed Lightnet architecture takes into account the idiosyncrasies of WDM switching/transmission leading to an efficient and pragmatic solution. The Lightnet architecture trades the ample WDM bandwidth for a reduction in the number of processing stages and a simplification of each switching stage, leading to drastically increased effective network throughputs. The principle of the Lightnet architecture is the construction and use of virtual topology networks, embedded in the original network in the wavelength domain. For this construction Lightnets utilize the new concept of lightpaths which constitute the links of the virtual topology. Lightpaths are all-optical, multihop, paths in the network that allow data to be switched through intermediate nodes using high throughput passive optical switches. The use of the virtual topologies and the associated switching design introduce a number of new ideas, which are discussed in detail.

  5. High-speed pressure clamp.

    PubMed

    Besch, Stephen R; Suchyna, Thomas; Sachs, Frederick

    2002-10-01

    We built a high-speed, pneumatic pressure clamp to stimulate patch-clamped membranes mechanically. The key control element is a newly designed differential valve that uses a single, nickel-plated piezoelectric bending element to control both pressure and vacuum. To minimize response time, the valve body was designed with minimum dead volume. The result is improved response time and stability with a threefold decrease in actuation latency. Tight valve clearances minimize the steady-state air flow, permitting us to use small resonant-piston pumps to supply pressure and vacuum. To protect the valve from water contamination in the event of a broken pipette, an optical sensor detects water entering the valve and increases pressure rapidly to clear the system. The open-loop time constant for pressure is 2.5 ms for a 100-mmHg step, and the closed-loop settling time is 500-600 micros. Valve actuation latency is 120 micros. The system performance is illustrated for mechanically induced changes in patch capacitance.

  6. High-speed Wind Tunnels

    NASA Technical Reports Server (NTRS)

    Ackeret, J

    1936-01-01

    Wind tunnel construction and design is discussed especially in relation to subsonic and supersonic speeds. Reynolds Numbers and the theory of compressible flows are also taken into consideration in designing new tunnels.

  7. Synchronous high speed multi-point velocity profile measurement by heterodyne interferometry

    NASA Astrophysics Data System (ADS)

    Hou, Xueqin; Xiao, Wen; Chen, Zonghui; Qin, Xiaodong; Pan, Feng

    2017-02-01

    This paper presents a synchronous multipoint velocity profile measurement system, which acquires the vibration velocities as well as images of vibrating objects by combining optical heterodyne interferometry and a high-speed CMOS-DVR camera. The high-speed CMOS-DVR camera records a sequence of images of the vibrating object. Then, by extracting and processing multiple pixels at the same time, a digital demodulation technique is implemented to simultaneously acquire the vibrating velocity of the target from the recorded sequences of images. This method is validated with an experiment. A piezoelectric ceramic plate with standard vibration characteristics is used as the vibrating target, which is driven by a standard sinusoidal signal.

  8. A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

    PubMed Central

    Lee, Hyung-Min; Ghovanloo, Maysam

    2014-01-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm2 of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages. PMID:23853321

  9. A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission.

    PubMed

    Lee, Hyung-Min; Ghovanloo, Maysam

    2013-06-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.

  10. Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

    NASA Astrophysics Data System (ADS)

    Kim, M. S.; Kim, G.; Cho, G.; Kim, D.

    2016-11-01

    A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ~ 50 μm pitch and ~ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

  11. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    PubMed Central

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  12. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    PubMed

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

  13. High-speed detection of DNA translocation in nanopipettes

    NASA Astrophysics Data System (ADS)

    Fraccari, Raquel L.; Ciccarella, Pietro; Bahrami, Azadeh; Carminati, Marco; Ferrari, Giorgio; Albrecht, Tim

    2016-03-01

    We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface.We present a high-speed electrical detection scheme based on a custom-designed CMOS amplifier which allows the analysis of DNA translocation in glass nanopipettes on a microsecond timescale. Translocation of different DNA lengths in KCl electrolyte provides a scaling factor of the DNA translocation time equal to p = 1.22, which is different from values observed previously with nanopipettes in LiCl electrolyte or with nanopores. Based on a theoretical model involving electrophoresis, hydrodynamics and surface friction, we show that the experimentally observed range of p-values may be the result of, or at least be affected by DNA adsorption and friction between the DNA and the substrate surface. Electronic supplementary information (ESI) available: Gel electrophoresis confirming lengths and purity of DNA samples, comparison between Axopatch 200B and custom-built setup, comprehensive low-noise amplifier characterization, representative I-V curves of nanopipettes used, typical scatter plots of τ vs. peak amplitude for the four LDNA's used, table of most probable τ values, a comparison between different fitting models for the DNA translocation time distribution, further details on the stochastic numerical simulation of the scaling statistics and the derivation of the extended

  14. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  15. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    PubMed

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  16. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 μm 1 Poly 4 Metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  17. A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.

    PubMed

    Huang, Xiwei; Yu, Hao; Liu, Xu; Jiang, Yu; Yan, Mei; Wu, Dongping

    2015-09-01

    The existing ISFET-based DNA sequencing detects hydrogen ions released during the polymerization of DNA strands on microbeads, which are scattered into microwell array above the ISFET sensor with unknown distribution. However, false pH detection happens at empty microwells due to crosstalk from neighboring microbeads. In this paper, a dual-mode CMOS ISFET sensor is proposed to have accurate pH detection toward DNA sequencing. Dual-mode sensing, optical and chemical modes, is realized by integrating a CMOS image sensor (CIS) with ISFET pH sensor, and is fabricated in a standard 0.18-μm CIS process. With accurate determination of microbead physical locations with CIS pixel by contact imaging, the dual-mode sensor can correlate local pH for one DNA slice at one location-determined microbead, which can result in improved pH detection accuracy. Moreover, toward a high-throughput DNA sequencing, a correlated-double-sampling readout that supports large array for both modes is deployed to reduce pixel-to-pixel nonuniformity such as threshold voltage mismatch. The proposed CMOS dual-mode sensor is experimentally examined to show a well correlated pH map and optical image for microbeads with a pH sensitivity of 26.2 mV/pH, a fixed pattern noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/s. A dual-mode CMOS ISFET sensor with suppressed FPN for accurate large-arrayed pH sensing is proposed and demonstrated with state-of-the-art measured results toward accurate and high-throughput DNA sequencing. The developed dual-mode CMOS ISFET sensor has great potential for future personal genome diagnostics with high accuracy and low cost.

  18. High speed imaging - An important industrial tool

    NASA Technical Reports Server (NTRS)

    Moore, Alton; Pinelli, Thomas E.

    1986-01-01

    High-speed photography, which is a rapid sequence of photographs that allow an event to be analyzed through the stoppage of motion or the production of slow-motion effects, is examined. In high-speed photography 16, 35, and 70 mm film and framing rates between 64-12,000 frames per second are utilized to measure such factors as angles, velocities, failure points, and deflections. The use of dual timing lamps in high-speed photography and the difficulties encountered with exposure and programming the camera and event are discussed. The application of video cameras to the recording of high-speed events is described.

  19. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    PubMed Central

    Jain, A; Takemoto, H; Silver, M D; Nagesh, S V S; Ionita, C N; Bednarek, D R; Rudin, S

    2015-01-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm × 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested. PMID:26877577

  20. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector.

    PubMed

    Jain, A; Takemoto, H; Silver, M D; Nagesh, S V S; Ionita, C N; Bednarek, D R; Rudin, S

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm × 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  1. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  2. Design methodology and application of high speed gate arrays

    NASA Astrophysics Data System (ADS)

    Decker, R.

    A system to provide real-time signal averaging of waveforms from a 50 MHz analog to digital converter has been fabricated to operate over a wide temperature range. This system evolved from conception, through an initial simulated design for emitter coupled logic (ECL), to a pair of CMOS gate array designs. Changing the implementation technology to CMOS gate arrays resulted in savings in cost, size, weight, and power. Design rules employed to obtain working silicon on the first cycle, at double state-of-the-art gate array speeds, are discussed. Also discussed are built-in, run-time, self-test features.

  3. High-Speed Ring Bus

    NASA Technical Reports Server (NTRS)

    Wysocky, Terry; Kopf, Edward, Jr.; Katanyoutananti, Sunant; Steiner, Carl; Balian, Harry

    2010-01-01

    The high-speed ring bus at the Jet Propulsion Laboratory (JPL) allows for future growth trends in spacecraft seen with future scientific missions. This innovation constitutes an enhancement of the 1393 bus as documented in the Institute of Electrical and Electronics Engineers (IEEE) 1393-1999 standard for a spaceborne fiber-optic data bus. It allows for high-bandwidth and time synchronization of all nodes on the ring. The JPL ring bus allows for interconnection of active units with autonomous operation and increased fault handling at high bandwidths. It minimizes the flight software interface with an intelligent physical layer design that has few states to manage as well as simplified testability. The design will soon be documented in the AS-1393 standard (Serial Hi-Rel Ring Network for Aerospace Applications). The framework is designed for "Class A" spacecraft operation and provides redundant data paths. It is based on "fault containment regions" and "redundant functional regions (RFR)" and has a method for allocating cables that completely supports the redundancy in spacecraft design, allowing for a complete RFR to fail. This design reduces the mass of the bus by incorporating both the Control Unit and the Data Unit in the same hardware. The standard uses ATM (asynchronous transfer mode) packets, standardized by ITU-T, ANSI, ETSI, and the ATM Forum. The IEEE-1393 standard uses the UNI form of the packet and provides no protection for the data portion of the cell. The JPL design adds optional formatting to this data portion. This design extends fault protection beyond that of the interconnect. This includes adding protection to the data portion that is contained within the Bus Interface Units (BIUs) and by adding to the signal interface between the Data Host and the JPL 1393 Ring Bus. Data transfer on the ring bus does not involve a master or initiator. Following bus protocol, any BIU may transmit data on the ring whenever it has data received from its host. There

  4. Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

    NASA Astrophysics Data System (ADS)

    Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

    2016-10-01

    The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

  5. BiCMOS circuit technology for a 704 MHz ATM switch LSI

    NASA Astrophysics Data System (ADS)

    Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

    1994-05-01

    This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

  6. A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

    PubMed

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

  7. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    PubMed Central

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C. PMID:22438758

  8. High speed nano-metrology

    SciTech Connect

    Humphris, Andrew D. L.; Zhao Bin; Catto, David; Kohli, Priyanka; Howard-Knight, Jeremy P.; Hobbs, Jamie K.

    2011-04-15

    For manufacturing at the nanometre scale a method for rapid and accurate measurement of the resultant functional devices is required. Although atomic force microscopy (AFM) has the requisite spatial resolution, it is severely limited in scan speed, the resolution and repeatability of vertical and lateral measurements being degraded when speed is increased. Here we present a new approach to AFM that makes a direct and feedback-independent measurement of surface height using a laser interferometer focused onto the back of the AFM tip. Combining this direct height measurement with a passive, feedback-free method for maintaining tip-sample contact removes the constraint on scan speed that comes from the bandwidth of the z-feedback loop. Conventional laser reflection detection is used for feedback control, which now plays the role of minimising tip-sample forces, rather than producing the sample topography. Using the system in conjunction with a rapid scanner, true height images are obtained with areas up to (36 x 36) {mu}m{sup 2} at 1 image/second, suitable for in-line applications.

  9. High Precision Bright-Star Astrometry with the USNO Astrometric CMOS Hybrid Camera System

    NASA Astrophysics Data System (ADS)

    Secrest, Nathan; Dudik, Rachel; Berghea, Ciprian; Hennessy, Greg; Dorland, Bryan

    2015-08-01

    While GAIA will provide excellent positional measurements of hundreds of millions of stars between 5 < mag < 20, an ongoing challenge in the field of high-precision differential astrometry is the positional accuracy of very bright stars (mag < 5), due to the enormous dynamic range between bright stars of interest, such as those in the Hipparcos catalog, and their background field stars, which are especially important for differential astrometry. Over the past few years, we have been testing the USNO Astrometric CMOS Hybrid Camera System (UAHC), which utilizes an H4RG-10 detector in windowing mode, as a possible solution to the NOFS USNO Bright Star Astrometric Database (UBAD). In this work, we discuss the results of an astrometric analysis of single-epoch Hipparcos data taken with the UAHC from the 1.55m Kaj Strand Astrometric Reflector at NOFS from June 27-30, 2014. We discuss the calibration of this data, as well as an astrometric analysis pipeline we developed that will enable multi-epoch differential and absolute astrometry with the UAHC. We find that while the overall differential astrometric stability of data taken with the UAHC is good (5-10 mas single-measurement precision) and comparable to other ground-based astrometric camera systems, bright stars in the detector window suffer from several systematic effects, such as insufficient window geometry and centroiding failures due to read-out artifacts—both of which can be significantly improved with modifications to the electronics, read-out speed and microcode.

  10. Full-frame, high-speed 3D shape and deformation measurements using stereo-digital image correlation and a single color high-speed camera

    NASA Astrophysics Data System (ADS)

    Yu, Liping; Pan, Bing

    2017-08-01

    Full-frame, high-speed 3D shape and deformation measurement using stereo-digital image correlation (stereo-DIC) technique and a single high-speed color camera is proposed. With the aid of a skillfully designed pseudo stereo-imaging apparatus, color images of a test object surface, composed of blue and red channel images from two different optical paths, are recorded by a high-speed color CMOS camera. The recorded color images can be separated into red and blue channel sub-images using a simple but effective color crosstalk correction method. These separated blue and red channel sub-images are processed by regular stereo-DIC method to retrieve full-field 3D shape and deformation on the test object surface. Compared with existing two-camera high-speed stereo-DIC or four-mirror-adapter-assisted singe-camera high-speed stereo-DIC, the proposed single-camera high-speed stereo-DIC technique offers prominent advantages of full-frame measurements using a single high-speed camera but without sacrificing its spatial resolution. Two real experiments, including shape measurement of a curved surface and vibration measurement of a Chinese double-side drum, demonstrated the effectiveness and accuracy of the proposed technique.

  11. High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

    2012-07-01

    In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

  12. Lightweight, high speed bearing balls: A concept

    NASA Technical Reports Server (NTRS)

    Parker, R. J.

    1974-01-01

    Low mass bearing balls with hardened iron-plated surfaces can eliminate problems of low fatigue strength and flexure fatigue, and lead to increased life and reliability of high speed ball bearings. Low mass balls exert lower centrifugal forces on outer race of bearing thus eliminating detrimental effect of high speed operation.

  13. High Speed Video for Airborne Instrumentation Application

    NASA Technical Reports Server (NTRS)

    Tseng, Ting; Reaves, Matthew; Mauldin, Kendall

    2006-01-01

    A flight-worthy high speed color video system has been developed. Extensive system development and ground and environmental. testing hes yielded a flight qualified High Speed Video System (HSVS), This HSVS was initially used on the F-15B #836 for the Lifting Insulating Foam Trajectory (LIFT) project.

  14. Reducing Heating In High-Speed Cinematography

    NASA Technical Reports Server (NTRS)

    Slater, Howard A.

    1989-01-01

    Infrared-absorbing and infrared-reflecting glass filters simple and effective means for reducing rise in temperature during high-speed motion-picture photography. "Hot-mirror" and "cold-mirror" configurations, employed in projection of images, helps prevent excessive heating of scenes by powerful lamps used in high-speed photography.

  15. High-Speed Photography with Computer Control.

    ERIC Educational Resources Information Center

    Winters, Loren M.

    1991-01-01

    Describes the use of a microcomputer as an intervalometer for the control and timing of several flash units to photograph high-speed events. Applies this technology to study the oscillations of a stretched rubber band, the deceleration of high-speed projectiles in water, the splashes of milk drops, and the bursts of popcorn kernels. (MDH)

  16. High-Speed Photography with Computer Control.

    ERIC Educational Resources Information Center

    Winters, Loren M.

    1991-01-01

    Describes the use of a microcomputer as an intervalometer for the control and timing of several flash units to photograph high-speed events. Applies this technology to study the oscillations of a stretched rubber band, the deceleration of high-speed projectiles in water, the splashes of milk drops, and the bursts of popcorn kernels. (MDH)

  17. Fundamental performance differences of CMOS and CCD imagers: part V

    NASA Astrophysics Data System (ADS)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  18. High speed flow past wings

    NASA Technical Reports Server (NTRS)

    Norstrud, H.

    1973-01-01

    The analytical solution to the transonic small perturbation equation which describes steady compressible flow past finite wings at subsonic speeds can be expressed as a nonlinear integral equation with the perturbation velocity potential as the unknown function. This known formulation is substituted by a system of nonlinear algebraic equations to which various methods are applicable for its solution. Due to the presence of mathematical discontinuities in the flow solutions, however, a main computational difficulty was to ensure uniqueness of the solutions when local velocities on the wing exceeded the speed of sound. For continuous solutions this was achieved by embedding the algebraic system in an one-parameter operator homotopy in order to apply the method of parametric differentiation. The solution to the initial system of equations appears then as a solution to a Cauchy problem where the initial condition is related to the accompanying incompressible flow solution. In using this technique, however, a continuous dependence of the solution development on the initial data is lost when the solution reaches the minimum bifurcation point. A steepest descent iteration technique was therefore, added to the computational scheme for the calculation of discontinuous flow solutions. Results for purely subsonic flows and supersonic flows with and without compression shocks are given and compared with other available theoretical solutions.

  19. Active control system for high speed windmills

    DOEpatents

    Avery, Don E.

    1988-01-01

    A pump stroke is matched to the operating speed of a high speed windmill. The windmill drives a hydraulic pump for a control. Changes in speed of a wind driven shaft open supply and exhaust valves to opposite ends of a hydraulic actuator to lengthen and shorten an oscillating arm thereby lengthening and shortening the stroke of an output pump. Diminishing wind to a stall speed causes the valves to operate the hydraulic cylinder to shorten the oscillating arm to zero. A pressure accumulator in the hydraulic system provides the force necessary to supply the hydraulic fluid under pressure to drive the actuator into and out of the zero position in response to the windmill shaft speed approaching and exceeding windmill stall speed.

  20. Active control system for high speed windmills

    DOEpatents

    Avery, D.E.

    1988-01-12

    A pump stroke is matched to the operating speed of a high speed windmill. The windmill drives a hydraulic pump for a control. Changes in speed of a wind driven shaft open supply and exhaust valves to opposite ends of a hydraulic actuator to lengthen and shorten an oscillating arm thereby lengthening and shortening the stroke of an output pump. Diminishing wind to a stall speed causes the valves to operate the hydraulic cylinder to shorten the oscillating arm to zero. A pressure accumulator in the hydraulic system provides the force necessary to supply the hydraulic fluid under pressure to drive the actuator into and out of the zero position in response to the windmill shaft speed approaching and exceeding windmill stall speed. 4 figs.

  1. A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

    NASA Astrophysics Data System (ADS)

    Huang, Zhangcai; Jiang, Minglu; Inoue, Yasuaki

    Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for ±2.5V power supply voltages, respectively.

  2. A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

    NASA Astrophysics Data System (ADS)

    Lauxtermann, Stefan; Fisher, John; McDougal, Michael

    2014-06-01

    In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

  3. Design of high speed LVDS transceiver ICs

    NASA Astrophysics Data System (ADS)

    Jian, Xu; Zhigong, Wang; Xiaokang, Niu

    2010-07-01

    The design of low-power LVDS (low voltage differential signaling) transceiver ICs is presented. The LVDS transmitter integrates a common-mode feedback control on chip, while a specially designed pre-charge circuit is proposed to improve the speed of the circuit, making the highest data rate up to 622 Mb/s. For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers. In addition, the LVDS receiver also supports the failsafe function. The transceiver chips were verified with the CSMC 0.5-μm CMOS process. The measured results showed that, for the LVDS transmitter with the pre-charge technique proposed, the maximum data rate is higher than 622 Mb/s. The power consumption is 6 mA with a 5-V power supply. The LVDS receiver can work properly with a larger input common mode voltage (0.1-2.4 V) but a differential input voltage as low as 100 mV. The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s. The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.

  4. The VK-8L High - Speed Camera

    NASA Astrophysics Data System (ADS)

    Venatovsky, I. V.; Tsukanov, A. A.; Kirillov, V. A.

    1985-02-01

    To enhance the time resolution of high-speed cine equipment during the investigation of rapidly flowing processes, a light source to illumi late an object under test is represented b7 solid-state laser exposure devices operating in the mode of Q-factor flodulation. With a high-speed eine cafiera being run in the continuous scanning mode, these devices will permit a sequence of fra Mlles to be obtained within a short exposure time of 150 ns to 200 nanoseconds. At scanning speeds of up to 250 m/s this will ensure satisfactory image quality from the slear viewpoint. In the case of faster continuous scanuin speeds and of shorter exposure times, it becomes necessary to run the high-speed cauera in the fl ode of frame-by-frame cinematography.

  5. ERROR CORRECTION IN HIGH SPEED ARITHMETIC,

    DTIC Science & Technology

    The errors due to a faulty high speed multiplier are shown to be iterative in nature. These errors are analyzed in various aspects. The arithmetic coding technique is suggested for the improvement of high speed multiplier reliability. Through a number theoretic investigation, a large class of arithmetic codes for single iterative error correction are developed. The codes are shown to have near-optimal rates and to render a simple decoding method. The implementation of these codes seems highly practical. (Author)

  6. Lubrication and cooling for high speed gears

    NASA Technical Reports Server (NTRS)

    Townsend, D. P.

    1985-01-01

    The problems and failures occurring with the operation of high speed gears are discussed. The gearing losses associated with high speed gearing such as tooth mesh friction, bearing friction, churning, and windage are discussed with various ways shown to help reduce these losses and thereby improve efficiency. Several different methods of oil jet lubrication for high speed gearing are given such as into mesh, out of mesh, and radial jet lubrication. The experiments and analytical results for the various methods of oil jet lubrication are shown with the strengths and weaknesses of each method discussed. The analytical and experimental results of gear lubrication and cooling at various test conditions are presented. These results show the very definite need of improved methods of gear cooling at high speed and high load conditions.

  7. Speed control with end cushion for high speed air cylinder

    DOEpatents

    Stevens, Wayne W.; Solbrig, Charles W.

    1991-01-01

    A high speed air cylinder in which the longitudinal movement of the piston within the air cylinder tube is controlled by pressurizing the air cylinder tube on the accelerating side of the piston and releasing pressure at a controlled rate on the decelerating side of the piston. The invention also includes a method for determining the pressure required on both the accelerating and decelerating sides of the piston to move the piston with a given load through a predetermined distance at the desired velocity, bringing the piston to rest safely without piston bounce at the end of its complete stroke.

  8. Optical waveguide taps on silicon CMOS circuits

    NASA Astrophysics Data System (ADS)

    Stenger, Vincent E.; Beyette, Fred R., Jr.

    2000-11-01

    As silicon CMOS circuit technology is scaled beyond the GHz range, both chipmakers and board makers face increasingly difficult challenges in implementing high speed metal interconnects. Metal traces are limited in density-speed performance due to the skin effect, electrical conductivity, and cross talk. Optical based interconnects have higher available bandwidth by virtue of the extremely high carrier frequencies of optical signals (> 100 THz). For this work, an effort has been made to determine an optimal optical tap receiver design for integration with commercial CMOS processes. Candidate waveguide tap technologies were considered in terms of optical loss, bandwidth, economy, and CMOS process compatibility. A new device, which is based on a variation of the multimode interference effect, has been found to be especially promising. BeamProp simulation results show nearly zero excess optical loss for the design, and up to 70% coupling into a 25 micrometer traveling wave CMOS photodetector device. Single-mode waveguides make the design readily compatible with wavelength multiplexing/demultiplexing elements. Polymer waveguide materials are targeted for fabrication due to planarization properties, low cost, broad index control, and poling abilities for modulation/tuning functions. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer chip and board level interconnects, as well as metro fiber-to-the- home/desk telecommunications applications.

  9. Key Technologies for Ultra High Dose CMOS Applications

    SciTech Connect

    Jeon, Y.; Koo, I.; Singh, V.; Oh, J.; Jin, S.; Lee, J.; Rouh, K.; Ju, M.; Jeon, S.; Ku, J.; Lee, S. B.; Lee, S. W.; Ok, M. T.; Butterbaugh, J.; Lee, A.; Kim, K.; Lee, S. W.; Ju, K. J.; Park, J. W.

    2008-11-03

    The trend towards shrinking advanced microelectronic Logic and DRAM devices will require ultra high dose implantation. One ultra high dose application in DRAM, being rapidly adopted in production is Dual Poly Gate (DPG). Three main challenges existed for the adoption of this high dose dual poly gate (DPG) doping applications: monitoring of high dose implantation, photoresist stripping and maintaining high throughput. In this paper we present how these challenges have been addressed. VSEA's plasma doping (PLAD) tool offers several unique advantages for DPG applications. When compared to conventional or molecular beam line implanters or other immersion techniques, PLAD delivers 3 to 7 times higher throughput (compared to traditional ion implanter) without dopant penetration through the thin doped polysilicon layer into the gate oxide. It also improves P{sup +} poly silicon DPG device properties at superior throughput. In this work we demonstrate how hot spray photoresist strip processing eliminates the need for multiple-tools required for wet+ash+wet process. In addition to PLAD's patented in-situ dose control metrology we also demonstrate an ex-situ high dose implantation metrology using spectroscopic ellipsometer (SE) and spectroscopic reflectometer (SR). The technique shows good correlation (R{sup 2}{approx}0.99) between implant dose and damaged layer thickness.

  10. Agile Electromagnetics Exploiting High Speed Logic (AEEHSL).

    DTIC Science & Technology

    2014-09-26

    examination and alteration of codes and filter weights 3. READ Mode - This mode enables the reading or replaying of the data from the digital tape recorder...available in this subsystems are used to initialize the * radar, clock the code from the high-speed code storage memory to drive the code modulator, delay...correlation process. There is storage space within the high speed memory for 32 codes of length 64 bits or less. The radiated code can be changed by a

  11. High-speed mirror-scanning tracker

    NASA Astrophysics Data System (ADS)

    Tong, HengWei

    1999-06-01

    This paper introduces a high speed single-mirror scanner developed by us as a versatile tracker. It can be connected with a high speed camera, a TV tracker (or color video recorder) /measurer/recorder. It can be guided by a computer, a joystick (automatic or manual) or TV tracker. In this paper, we also present the advantages of our scanner contrasted with the limitations of fixed camera system. In addition, several usable projects of mirror scanner are discussed.

  12. Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

    NASA Astrophysics Data System (ADS)

    Ellinger, Frank; Fritsche, David; Tretter, Gregor; Leufker, Jan Dirk; Yodprasit, Uroschanit; Carta, C.

    2017-01-01

    In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

  13. High-speed high-resolution optical coherence tomography at 800 and 1060 nm

    NASA Astrophysics Data System (ADS)

    Považay, B.; Hofer, B.; Hermann, B.; Torti, C.; Kajic, V.; Unterhuber, A.; Drexler, W.

    2008-09-01

    Two high speed systems for spectrometer based frequency domain optical coherence tomography are presented. A device operating at 800 nm, based on the Basler Sprint CMOS camera with linerates of up to 312,000 lps and a device based on the Goodrich SUI LHD 1024 px camera at 1060 nm with 47,000 lps are applied in a clinical environment to normal subjects. The feasibility of clinical high and ultra high-resolution optical coherence tomography (OCT) devices for retinal imaging at different wavelengths, capable of isotropic sampling with 70 to 600 frames per second at 512 depth scans/frame for widefield imaging and high density sampling at 1 Gvoxel are demostrated.

  14. Compact, high-speed and power-efficient electrooptic plasmonic modulators.

    PubMed

    Cai, Wenshan; White, Justin S; Brongersma, Mark L

    2009-12-01

    CMOS compatible electrooptic plasmonic modulators are slated to be key components in chip-scale photonic circuits. In this work, we investigate detailed design and optimization protocols for electrooptic plasmonic modulators that are suitable for free-space coupling and on-chip integration. The metallic structures in the proposed devices offer simultaneous electric and optical functions. The resonance-enhanced nonlinear interaction and submicrometer-footprint of these devices meet the stringent requirements for future CMOS modulators, allowing for high-speed operation (>100 GHz) with a decent modulation depth (>3 dB) and moderate insertion loss (<3 dB) at a very low swing voltage ( approximately 1 V) and power dissipation ( approximately 1 fJ/bit). The realization of the proposed structures appears feasible with current materials and lithographic techniques.

  15. A High Vacuum High Speed Ion Pump

    DOE R&D Accomplishments Database

    Foster, J. S. Jr.; Lawrence, E. O.; Lofgren, E. J.

    1952-08-27

    A vacuum pump based on the properties of a magnetically collimated electric discharge is described. It has a speed in the range 3000 to 7000 liters a second and a base pressure in the order of 10{sup -6} mm. (auth)

  16. High energy ion implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology

    NASA Astrophysics Data System (ADS)

    Jacobson, D. C.; Kamgar, A.; Eaglesham, D. J.; Lloyd, E. J.; Hillenius, S. J.; Poate, J. M.

    1995-03-01

    High energy ion implantation has been utilized to fabricate profiled tubs and to create gettering sites in deep submicron CMOS devices in bulk and epitaxial Si. The isolation and latch-up characteristics have been measured and found to be superior to those of devices in tubs fabricated by the conventional thermal drive-in method. High energy implants into bulk Si produce inferior gettering as deduced from diode leakage measurements. Iron gettering to the MeV boron implanted region has been investigated.

  17. High Speed Prototype Car Test

    NASA Image and Video Library

    2014-01-10

    CAPE CANAVERAL, Fla. - A Hennessey Venom GT stands on the 3.5-mile long runway between test runs at the Shuttle Landing Facility at NASA's Kennedy Space Center in Florida. The flat concrete runway is one of the few places in the world where high performance automobiles can be tested for aerodynamic and safety designs. Hennessey Performance of Sealy, Texas, worked with Performance Power Racing in West Palm Beach to arrange use of the NASA facility. Performance Power Racing has conducted numerous engineering tests on the runway with a variety of vehicles. Photo credit: NASA/Kim Shiflett

  18. High Speed Prototype Car Test

    NASA Image and Video Library

    2014-01-10

    CAPE CANAVERAL, Fla. - An engineer readies a Hennessey Venom GT for test runs on the 3.5-mile long runway at the Shuttle Landing Facility at NASA's Kennedy Space Center in Florida. The flat concrete runway is one of the few places in the world where high performance automobiles can be tested for aerodynamic and safety designs. Hennessey Performance of Sealy, Texas, worked with Performance Power Racing in West Palm Beach to arrange use of the NASA facility. Performance Power Racing has conducted numerous engineering tests on the runway with a variety of vehicles. Photo credit: NASA/Kim Shiflett

  19. High Speed Prototype Car Test

    NASA Image and Video Library

    2014-01-10

    CAPE CANAVERAL, Fla. - Mechanics and engineers ready a Hennessey Venom GT for test runs on the 3.5-mile long runway at the Shuttle Landing Facility at NASA's Kennedy Space Center in Florida. The flat concrete runway is one of the few places in the world where high performance automobiles can be tested for aerodynamic and safety designs. Hennessey Performance of Sealy, Texas, worked with Performance Power Racing in West Palm Beach to arrange use of the NASA facility. Performance Power Racing has conducted numerous engineering tests on the runway with a variety of vehicles. Photo credit: NASA/Kim Shiflett

  20. High Speed Prototype Car Test

    NASA Image and Video Library

    2014-01-10

    CAPE CANAVERAL, Fla. - Mechanics, engineers and Driver Brian Smith, in jumpsuit, ready a Hennessey Venom GT for test runs on the 3.5-mile long runway at the Shuttle Landing Facility at NASA's Kennedy Space Center in Florida. The flat concrete runway is one of the few places in the world where high performance automobiles can be tested for aerodynamic and safety designs. Hennessey Performance of Sealy, Texas, worked with Performance Power Racing in West Palm Beach to arrange use of the NASA facility. Performance Power Racing has conducted numerous engineering tests on the runway with a variety of vehicles. Photo credit: NASA/Kim Shiflett

  1. High Speed Prototype Car Test

    NASA Image and Video Library

    2014-01-10

    CAPE CANAVERAL, Fla. - The Performance Power Racing and Hennessey Performance teams pose with a Hennessey Venom GT at the 3.5-mile long runway at the Shuttle Landing Facility at NASA's Kennedy Space Center in Florida. The teams are, from left, Hennessey's John Heinricy, John Hennessey, Brian Smith, Performance Power Racing's Johnny Bohmer, Matt Lundy and Jeff McEachran. The flat concrete runway is one of the few places in the world where high performance automobiles can be tested for aerodynamic and safety designs. Hennessey Performance of Sealy, Texas, worked with Performance Power Racing in West Palm Beach to arrange use of the NASA facility. Performance Power Racing has conducted numerous engineering tests on the runway with a variety of vehicles.

  2. Small high-speed dynamic target at close range laser active imaging system

    NASA Astrophysics Data System (ADS)

    Yao, Jun; Wang, Du-yue; Zhang, Zheng; Zhang, Yue; Dai, Qin

    2016-11-01

    In the shooting range measuring, all-weather, high speed, unattended, the new concepts such as the remote control is gradually applied. In this paper, a new type of low cost range measurement system, using FPGA + MCU as electronic control system of laser active illumination and high-speed CMOS camera, data to the rear zone by using optical fiber communications, transmission and realizes the remote control of unmanned, due to the low cost of front-end equipment, can be used as consumables replacement at any time, combined with distributed layout principle, can maximum limit close to the measured with mutilate ability goal, thus to achieve the goal of small high-speed dynamic imaging from close range.

  3. Speckle noise reduction in high speed polarization sensitive spectral domain optical coherence tomography

    PubMed Central

    Götzinger, Erich; Pircher, Michael; Baumann, Bernhard; Schmoll, Tilman; Sattmann, Harald; Leitgeb, Rainer A.; Hitzenberger, Christoph K.

    2015-01-01

    We present a high speed polarization sensitive spectral domain optical coherence tomography system based on polarization maintaining fibers and two high speed CMOS line scan cameras capable of retinal imaging with up to 128 k A-lines/s. This high imaging speed strongly reduces motion artifacts and therefore averaging of several B-scans is possible, which strongly reduces speckle noise and improves image quality. We present several methods for averaging retardation and optic axis orientation, the best one providing a 5 fold noise reduction. Furthermore, a novel scheme of calculating images of degree of polarization uniformity is presented. We quantitatively compare the noise reduction depending on the number of averaged frames and discuss the limits of frame numbers that can usefully be averaged. PMID:21934820

  4. A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

    NASA Astrophysics Data System (ADS)

    Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

    2017-02-01

    This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

  5. Machine Vision Techniques For High Speed Videography

    NASA Astrophysics Data System (ADS)

    Hunter, David B.

    1984-11-01

    The priority associated with U.S. efforts to increase productivity has led to, among other things, the development of Machine Vision systems for use in manufacturing automation requirements. Many such systems combine solid state television cameras and data processing equipment to facilitate high speed, on-line inspection and real time dimensional measurement of parts and assemblies. These parts are often randomly oriented and spaced on a conveyor belt under continuous motion. Television imagery of high speed events has historically been achieved by use of pulsed (strobe) illumination or high speed shutter techniques synchronized with a camera's vertical blanking to separate write and read cycle operation. Lack of synchronization between part position and camera scanning in most on-line applications precludes use of this vertical interval illumination technique. Alternatively, many Machine Vision cameras incorporate special techniques for asynchronous, stop-motion imaging. Such cameras are capable of imaging parts asynchronously at rates approaching 60 hertz while remaining compatible with standard video recording units. Techniques for asynchronous, stop-motion imaging have not been incorporated in cameras used for High Speed Videography. Imaging of these events has alternatively been obtained through the utilization of special, high frame rate cameras to minimize motion during the frame interval. High frame rate cameras must undoubtedly be utilized for recording of high speed events occurring at high repetition rates. However, such cameras require very specialized, and often expensive, video recording equipment. It seems, therefore, that Machine Vision cameras with capability for asynchronous, stop-motion imaging represent a viable approach for cost effective video recording of high speed events occurring at repetition rates up to 60 hertz.

  6. High speed flight effects on noise propagation

    NASA Astrophysics Data System (ADS)

    Burrin, R. H.; Ahuja, K. K.; Salikuddin, M.

    1987-01-01

    An experimental study to investigate the effects of source motion on sound propagation at high Mach numbers was devised to determine, in particular, if the large amplifications in the forward arc to high speeds, predicted by the 'convective amplification' factors normally used for low speeds, are realistic. An acoustic point source and a microphone, both immersed in flows up to a Mach number of 0.8, were used to obtain the convective amplification factors for comparison with predictions. The results confirmed the existence of high levels of noise propagating ahead of an aircraft flying at high speed. The commonly adopted prediction formula, namely (1 - M sub 0 cos theta sub E) exp -4, was categorically confirmed by the data for frequencies up to 5 kHz and Mach numbers of 0.2 to 0.8. At higher frequencies, the predictions are followed up to emission angles of 120 deg, but then deviate downward towards the direction of flight.

  7. Scientific Visualization in High Speed Network Environments

    NASA Technical Reports Server (NTRS)

    Vaziri, Arsi; Kutler, Paul (Technical Monitor)

    1997-01-01

    In several cases, new visualization techniques have vastly increased the researcher's ability to analyze and comprehend data. Similarly, the role of networks in providing an efficient supercomputing environment have become more critical and continue to grow at a faster rate than the increase in the processing capabilities of supercomputers. A close relationship between scientific visualization and high-speed networks in providing an important link to support efficient supercomputing is identified. The two technologies are driven by the increasing complexities and volume of supercomputer data. The interaction of scientific visualization and high-speed networks in a Computational Fluid Dynamics simulation/visualization environment are given. Current capabilities supported by high speed networks, supercomputers, and high-performance graphics workstations at the Numerical Aerodynamic Simulation Facility (NAS) at NASA Ames Research Center are described. Applied research in providing a supercomputer visualization environment to support future computational requirements are summarized.

  8. High speed fluorescence imaging with compressed ultrafast photography

    NASA Astrophysics Data System (ADS)

    Thompson, J. V.; Mason, J. D.; Beier, H. T.; Bixler, J. N.

    2017-02-01

    Fluorescent lifetime imaging is an optical technique that facilitates imaging molecular interactions and cellular functions. Because the excited lifetime of a fluorophore is sensitive to its local microenvironment,1, 2 measurement of fluorescent lifetimes can be used to accurately detect regional changes in temperature, pH, and ion concentration. However, typical state of the art fluorescent lifetime methods are severely limited when it comes to acquisition time (on the order of seconds to minutes) and video rate imaging. Here we show that compressed ultrafast photography (CUP) can be used in conjunction with fluorescent lifetime imaging to overcome these acquisition rate limitations. Frame rates up to one hundred billion frames per second have been demonstrated with compressed ultrafast photography using a streak camera.3 These rates are achieved by encoding time in the spatial direction with a pseudo-random binary pattern. The time domain information is then reconstructed using a compressed sensing algorithm, resulting in a cube of data (x,y,t) for each readout image. Thus, application of compressed ultrafast photography will allow us to acquire an entire fluorescent lifetime image with a single laser pulse. Using a streak camera with a high-speed CMOS camera, acquisition rates of 100 frames per second can be achieved, which will significantly enhance our ability to quantitatively measure complex biological events with high spatial and temporal resolution. In particular, we will demonstrate the ability of this technique to do single-shot fluorescent lifetime imaging of cells and microspheres.

  9. Post-CMOS compatible high-throughput fabrication of AlN-based piezoelectric microcantilevers

    NASA Astrophysics Data System (ADS)

    Pérez-Campos, A.; Iriarte, G. F.; Hernando-Garcia, J.; Calle, F.

    2015-02-01

    A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3-Cl2-Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

  10. A clock generator for a high-speed high-resolution pipelined A/D converter

    NASA Astrophysics Data System (ADS)

    Lei, Zhao; Yintang, Yang; Zhangming, Zhu; Lianxi, Liu

    2013-02-01

    A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 μm 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.

  11. High speed hydrogen/graphite interaction

    NASA Technical Reports Server (NTRS)

    Kelly, A. J.; Hamman, R.; Sharma, O. P.; Harrje, D. T.

    1974-01-01

    Various aspects of a research program on high speed hydrogen/graphite interaction are presented. Major areas discussed are: (1) theoretical predictions of hydrogen/graphite erosion rates; (2) high temperature, nonequilibrium hydrogen flow in a nozzle; and (3) molecular beam studies of hydrogen/graphite erosion.

  12. High Speed Digital Camera Technology Review

    NASA Technical Reports Server (NTRS)

    Clements, Sandra D.

    2009-01-01

    A High Speed Digital Camera Technology Review (HSD Review) is being conducted to evaluate the state-of-the-shelf in this rapidly progressing industry. Five HSD cameras supplied by four camera manufacturers participated in a Field Test during the Space Shuttle Discovery STS-128 launch. Each camera was also subjected to Bench Tests in the ASRC Imaging Development Laboratory. Evaluation of the data from the Field and Bench Tests is underway. Representatives from the imaging communities at NASA / KSC and the Optical Systems Group are participating as reviewers. A High Speed Digital Video Camera Draft Specification was updated to address Shuttle engineering imagery requirements based on findings from this HSD Review. This draft specification will serve as the template for a High Speed Digital Video Camera Specification to be developed for the wider OSG imaging community under OSG Task OS-33.

  13. High-speed optical packet processing technologies based on novel optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Takenouchi, Hirokazu; Takahashi, Ryo; Takahata, Kiyoto; Nakahara, Tatsushi; Suzuki, Hiroyuki

    2004-10-01

    To cope with the explosive growth of IP traffic, we must increase both the link capacity between nodes and the node throughput. These requirements have stimulated research on photonic networks that use optical technologies. Optical packet switching (OPS) is an attractive solution because it maximizes the use of the network bandwidth. The key functions in achieving such networks include synchronization, label processing, compression/decompression, regeneration, and buffering for high-speed asynchronous optical packets. However, it is impractical to implement such functions by using all-optical approaches. We have proposed a new optoelectronic system composed of a packet-by-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The OCG provides a single optical pulse synchronized with the incoming packet, and the SPC carries out a parallel conversion of the incoming packet. The parallel converted data are processed in the smart CMOS circuit, and reconstructed into an optical packet by the photonic PSC. Our system makes it possible to carry out various functions for high-speed asynchronous optical packets. This paper reviews our recent work on high-speed optical packet processing technologies such as buffering, packet compression/decompression, and label swapping, which are key technologies for constructing future OPS networks.

  14. CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

    PubMed

    Li, Haitao; Boling, C Sam; Mason, Andrew J

    2016-08-01

    Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

  15. CMOS Amperometric ADC with High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring

    PubMed Central

    Li, Haitao; Boling, Sam; Mason, Andrew J.

    2016-01-01

    Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental ΣΔ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 μm CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 μW and 0.157mm2 active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit’s real-time response to a wide range of analyte concentrations. PMID:27352395

  16. A programmable vision chip with high speed image processing

    NASA Astrophysics Data System (ADS)

    Dubois, Jérôme; Paindavoine, Michel; Ginhac, Dominique

    2008-11-01

    A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 64×64 pixel retina is used to extract the magnitude and direction of spatial gradients from images. So, the sensor implements some lowlevel image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel filter or Laplacian are described and implemented on the circuit. The retina implements in a massively parallel way, at pixel level, some various treatments based on a four-quadrants multipliers architecture. Each pixel includes a photodiode, an amplifier, two storage capacitors and an analog arithmetic unit. A maximal output frame rate of about 10 000 frames per second with only image acquisition and 2000 to 5000 frames per second with image processing is achieved in a 0.35 μm standard CMOS process. The retina provides address-event coded output on three asynchronous buses, one output is dedicated to the gradient and both other to the pixel values. A prototype based on this principle, has been designed. Simulation results from Mentor GraphicsTMsoftware and AustriaMicrosystem Design kit are presented.

  17. Pushing the material limit and physics novelty in high κ's/high carrier mobility semiconductors for post Si CMOS

    NASA Astrophysics Data System (ADS)

    Hong, Minghwei

    2012-02-01

    The semiconductor industry is now facing unprecedented materials/physics challenges due to the scaling-limitation of Si CMOS transistor arising from non-scaling of matters, namely gate dielectrics and channel mobility. The new technology using high-κ plus metal gate on high carrier mobility semiconductors of InGaAs and Ge will lead to faster speed at lower power. The tasks for realizing the new devices equivalent oxide thickness (EOT) < 1 nm, interfacial density of state (Dit) <= 10^11 eV-1cm-2, self-aligned process, low parasitic, and integration with Si, have been solved or are being feverishly studied. The key of achieving the above goals is to understand/tailor interfaces of the high κ's/InGaAs (Ge). Tremendous progress has been made using molecular beam epitaxy (MBE) and atomic layer deposition (ALD) high κ's of Ga2O3(Gd2O3), Al2O3, and HfO2, and the novel ALD/MBE dual dielectrics in attaining an EOT of 0.5 nm, Dit of low 10^11 eV-1cm-2 (with a flat Dit distribution versus energy), and thermal stability at high temperatures higher than 800 C of the MOS structures. Electronic/electrical characteristics of the hetero-structures have been studied using in-situ synchrotron radiation photo-emission, cross-sectional scanning tunneling spectroscopy, capacitance (conductance)-voltage under various temperatures, and charge pumping methods. Device performance in world-record drain currents, transconductances, sub-threshold swings, etc. in self-aligned inversion-channel high κ's/InGaAs and /Ge MOSFET's will also be presented. This work has been supported by Nano National Program (NSC 100-2120-M-007-010) of the NSC of Taiwan, and the AOARD of the US Air Force. [4pt] In collaboration with J. Kwo, W. C. Lee, M. L. Huang, T. D. Lin, Y. C. Chang, Y. H. Chang, C. A. Lin, Y. M. Chang (NTHU and NTU in Taiwan), T. W. Pi, C. H. Hsu (NSRRC in Taiwan), Y. P. Chiu (NSYSU in Taiwan), C. Merckling (IMEC in Belgium), J. I. Chyi (NCU, Taiwan), and G. J. Brown (AFRL, USA).

  18. DAC 22 High Speed Civil Transport Model

    NASA Technical Reports Server (NTRS)

    1992-01-01

    Between tests, NASA research engineer Dave Hahne inspects a tenth-scale model of a supersonic transport model in the 30- by 60-Foot Tunnel at NASA Langley Research Center, Hampton, Virginia. The model is being used in support of NASA's High-Speed Research (HSR) program. Langley researchers are applying advance aerodynamic design methods to develop a wing leading-edge flap system which significantly improves low-speed fuel efficiency and reduces noise generated during takeoff operation. Langley is NASA's lead center for the agency's HSR program, aimed at developing technology to help U.S. industry compete in the rapidly expanding trans-oceanic transport market. A U.S. high-speed civil transport is expected to fly in about the year 2010. As envisioned, it would fly 300 passengers across the Pacific in about four hours at Mach 2.4 (approximately 1,600 mph/1950 kph) for a modest increase over business class fares.

  19. High Speed and Slow Motion: The Technology of Modern High Speed Cameras

    ERIC Educational Resources Information Center

    Vollmer, Michael; Mollmann, Klaus-Peter

    2011-01-01

    The enormous progress in the fields of microsystem technology, microelectronics and computer science has led to the development of powerful high speed cameras. Recently a number of such cameras became available as low cost consumer products which can also be used for the teaching of physics. The technology of high speed cameras is discussed,…

  20. High Speed and Slow Motion: The Technology of Modern High Speed Cameras

    ERIC Educational Resources Information Center

    Vollmer, Michael; Mollmann, Klaus-Peter

    2011-01-01

    The enormous progress in the fields of microsystem technology, microelectronics and computer science has led to the development of powerful high speed cameras. Recently a number of such cameras became available as low cost consumer products which can also be used for the teaching of physics. The technology of high speed cameras is discussed,…

  1. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  2. Experiments with synchronized sCMOS cameras

    NASA Astrophysics Data System (ADS)

    Steele, Iain A.; Jermak, Helen; Copperwheat, Chris M.; Smith, Robert J.; Poshyachinda, Saran; Soonthorntham, Boonrucksar

    2016-07-01

    Scientific-CMOS (sCMOS) cameras can combine low noise with high readout speeds and do not suffer the charge multiplication noise that effectively reduces the quantum efficiency of electron multiplying CCDs by a factor 2. As such they have strong potential in fast photometry and polarimetry instrumentation. In this paper we describe the results of laboratory experiments using a pair of commercial off the shelf sCMOS cameras based around a 4 transistor per pixel architecture. In particular using a both stable and a pulsed light sources we evaluate the timing precision that may be obtained when the cameras readouts are synchronized either in software or electronically. We find that software synchronization can introduce an error of 200-msec. With electronic synchronization any error is below the limit ( 50-msec) of our simple measurement technique.

  3. High-speed video-based tracking of optically trapped colloids

    NASA Astrophysics Data System (ADS)

    Otto, O.; Gornall, J. L.; Stober, G.; Czerwinski, F.; Seidel, R.; Keyser, U. F.

    2011-04-01

    We have developed an optical tweezer setup, with high-speed and real-time position tracking, based on a CMOS camera technology. Our software encoded algorithm is cross-correlation based and implemented on a standard computer. By measuring the fluctuations of a confined colloid at 6000 frames s - 1, continuously for an hour, we show our technique is a viable alternative to quadrant photodiodes. The optical trap is calibrated by using power spectrum analysis and the Stokes method. The trap stiffness is independent of the camera frame rate and scales linearly with the applied laser power. The analysis of our data by Allan variance demonstrates single nanometer accuracy in position detection.

  4. A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

    NASA Astrophysics Data System (ADS)

    Kaçar, Fırat; Metin, Bilgin; Kuntman, Hakan; Cicekoglu, Oguzhan

    2010-05-01

    In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z-, good linearity and excellent output-input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.

  5. High speed optical tomography for flow visualization

    NASA Technical Reports Server (NTRS)

    Snyder, Ray; Hesselink, Lambertus

    1987-01-01

    A novel optical architecture (based on holographic optical elements) for making high speed tomographic measurements is presented. The system is designed for making density or species concentration measurements in a nonsteady fluid or combustion flow. Performance evaluations of the optical system are discussed, and a test phase object was successfully reconstructed using this optical arrangement.

  6. Maneuverability Estimation of High-Speed Craft

    DTIC Science & Technology

    2015-06-01

    derived based on equations by Lewandowski and Denny- Hubble in order to find the fundamental maneuvering characteristics. The model is developed in...characteristic of high- speed craft. A mathematical model is derived based on equations by Lewandowski and Denny- Hubble in order to find the fundamental...33 C. EQUATIONS BY DENNY AND HUBBLE ................................................43 D. NOMOTO

  7. High-Speed Sealift Technology. Volume 1

    DTIC Science & Technology

    1998-09-01

    Engineering Directorate Technology Projection Report HIGH-SPEED SEALIFT TECHNOLOGY Volume 1 BY OWEN K. RITTER MICHAEL T. TEMPLEMAN...7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Naval Surface Warfare Center,Carderock Division,Total Ship Systems Engineering Directorate...11 3.4.3.2 Diesel Engines

  8. Laser Trigger For High Speed Camera

    NASA Astrophysics Data System (ADS)

    Chang, Rong-Seng; Lin, Chin-Wu; Cheng, Tung

    1987-09-01

    High speed camera coorperated with laser trigger to catch high speed unpredictable events has many applications: such as scoring system for the end game of missile interception, war head explosive study etc. When the event happening in a very short duration, the repetition rate of the laser ranging must be as high as 5K herze and the pulse duration should be less than 10 nsec. In some environment, like inside the aircraft, the abailable space for high speed camera to set up is limited, large film capacity camera could not be used. In order to use the small capacity film, the exact trigger time for the camera are especially important. The target velocity, camera acceleration characteristics, speed regulation, camera size, weight and the ruggedness are all be considered before the laser trigger be designed. Electric temporal gate is used to measure the time of flight ranging datum. The triangular distance measurement principle are also used to get the ranging when the base line i.e. the distance between the laser transmitter and receiver are large enough.

  9. Italian High-speed Airplane Engines

    NASA Technical Reports Server (NTRS)

    Bona, C F

    1940-01-01

    This paper presents an account of Italian high-speed engine designs. The tests were performed on the Fiat AS6 engine, and all components of that engine are discussed from cylinders to superchargers as well as the test set-up. The results of the bench tests are given along with the performance of the engines in various races.

  10. Impedance Matching for High Speed Optical Communication

    DTIC Science & Technology

    1988-06-01

    OPTICAL COMMUNICATION 16, PERaPNAL AUATHOR(S)ur. Kenry Zmuda IfTYJE OF REPORT 13b TIMý COVA5ED 14. DATE OF REPORT (Year, Month. Day) I5 PAGE COUNT EnaJ...294. 5. D. J. Nicholson and H. Zmuda, "Matching Structures for High Speed Optical Communication ", To be published in the Proceedings of Society of

  11. High-speed data word monitor

    NASA Technical Reports Server (NTRS)

    Wirth, M. N.

    1975-01-01

    Small, portable, self-contained device provides high-speed display of bit pattern or any selected portion of transmission, can suppress filler patterns so that display is not updated, and can freeze display so that specific event may be observed in detail.

  12. High-Speed Photometry of Catalina Sources

    NASA Astrophysics Data System (ADS)

    Warner, Brian; Woudt, Patrick A.

    2010-12-01

    High-speed photometry of cataclysmic variables selected from the Catalina Real-Time Transient (CRTS) survey results in orbital periods for 12 objects (10 dwarf novae and 2 polars). The period distribution for all CRTS sources has a pronounced peak near 80 minutes, confirming previous results from the Sloan Digital Sky Survey cataclysmic variables.

  13. High-Speed Schlieren Movies of Decelerators at Supersonic Speeds

    NASA Technical Reports Server (NTRS)

    1960-01-01

    Tests were conducted on several types of porous parachutes, a paraglider, and a simulated retrorocket. Mach numbers ranged from 1.8-3.0, porosity from 20-80 percent, and camera speeds from 1680-3000 feet per second (fps) in trials with porous parachutes. Trials of reefed parachutes were conducted at Mach number 2.0 and reefing of 12-33 percent at camera speeds of 600 fps. A flexible parachute with an inflatable ring in the periphery of the canopy was tested at Reynolds number 750,000 per foot, Mach number 2.85, porosity of 28 percent, and camera speed of 36oo fps. A vortex-ring parachute was tested at Mach number 2.2 and camera speed of 3000 fps. The paraglider, with a sweepback of 45 degrees at an angle of attack of 45 degrees was tested at Mach number 2.65, drag coefficient of 0.200, and lift coefficient of 0.278 at a camera speed of 600 fps. A cold air jet exhausting upstream from the center of a bluff body was used to simulate a retrorocket. The free-stream Mach number was 2.0, free-stream dynamic pressure was 620 lb/sq ft, jet-exit static pressure ratio was 10.9, and camera speed was 600 fps.

  14. High-Speed Schlieren Movies of Decelerators at Supersonic Speeds

    NASA Technical Reports Server (NTRS)

    1960-01-01

    Tests were conducted on several types of porous parachutes, a paraglider, and a simulated retrorocket. Mach numbers ranged from 1.8-3.0, porosity from 20-80 percent, and camera speeds from 1680-3000 feet per second (fps) in trials with porous parachutes. Trials of reefed parachutes were conducted at Mach number 2.0 and reefing of 12-33 percent at camera speeds of 600 fps. A flexible parachute with an inflatable ring in the periphery of the canopy was tested at Reynolds number 750,000 per foot, Mach number 2.85, porosity of 28 percent, and camera speed of 36oo fps. A vortex-ring parachute was tested at Mach number 2.2 and camera speed of 3000 fps. The paraglider, with a sweepback of 45 degrees at an angle of attack of 45 degrees was tested at Mach number 2.65, drag coefficient of 0.200, and lift coefficient of 0.278 at a camera speed of 600 fps. A cold air jet exhausting upstream from the center of a bluff body was used to simulate a retrorocket. The free-stream Mach number was 2.0, free-stream dynamic pressure was 620 lb/sq ft, jet-exit static pressure ratio was 10.9, and camera speed was 600 fps.

  15. Pulsed laser triggered high speed microfluidic switch

    NASA Astrophysics Data System (ADS)

    Wu, Ting-Hsiang; Gao, Lanyu; Chen, Yue; Wei, Kenneth; Chiou, Pei-Yu

    2008-10-01

    We report a high-speed microfluidic switch capable of achieving a switching time of 10 μs. The switching mechanism is realized by exciting dynamic vapor bubbles with focused laser pulses in a microfluidic polydimethylsiloxane (PDMS) channel. The bubble expansion deforms the elastic PDMS channel wall and squeezes the adjacent sample channel to control its fluid and particle flows as captured by the time-resolved imaging system. A switching of polystyrene microspheres in a Y-shaped channel has also been demonstrated. This ultrafast laser triggered switching mechanism has the potential to advance the sorting speed of state-of-the-art microscale fluorescence activated cell sorting devices.

  16. Some problems of high speed travel

    PubMed Central

    Reader, D. C.

    1975-01-01

    Some aspects of high speed flight are examined to investigate whether increase in speed implies any lowering of safety standards. The problem of circadian dysrhythmia is discussed and methods of attenuating its effects are explained and some new hypnotic drugs are mentioned. The risk of decompression has been quantified and predictions have been made for risks in commercial service. Cosmic radiation in supersonic aircraft is unlikely to limit commercial operation or significantly increase risks to passengers and crew. The supersonic boom is likely to limit the terrain over which supersonic aircraft can operate and regulations covering engine noise on the ground could restrict some flights. PMID:1208294

  17. High Speed SPM of Functional Materials

    SciTech Connect

    Huey, Bryan D.

    2015-08-14

    The development and optimization of applications comprising functional materials necessitates a thorough understanding of their static and dynamic properties and performance at the nanoscale. Leveraging High Speed SPM and concepts enabled by it, efficient measurements and maps with nanoscale and nanosecond temporal resolution are uniquely feasible. This includes recent enhancements for topographic, conductivity, ferroelectric, and piezoelectric properties as originally proposed, as well as newly developed methods or improvements to AFM-based mechanical, friction, thermal, and photoconductivity measurements. The results of this work reveal fundamental mechanisms of operation, and suggest new approaches for improving the ultimate speed and/or efficiency, of data storage systems, magnetic-electric sensors, and solar cells.

  18. High-speed spectroradiometer for remote sensing.

    PubMed

    Miyazaki, T; Shimizu, H; Yasuoka, Y

    1987-11-15

    A high-speed spectroradiometer designed for spectral reflectance measurement in remote sensing is described. This instrument uses a monochromatic grating and a photomultiplier system for light detection and sweeps over the 400-850-nm wavelength spectral range with the spectral resolution of 2 nm within 1 s. The instrument has the inherent advantage of portability and speed of operation which make it particularly suitable for field work in the area of fast moving surfaces, e.g., water with wave motion. Some applications of its use in laboratory and field experiments also have been presented. The instrument would seem to be an appropriate instrument for ground data collection in remote sensing.

  19. Sensor study for high speed autonomous operations

    NASA Astrophysics Data System (ADS)

    Schneider, Anne; La Celle, Zachary; Lacaze, Alberto; Murphy, Karl; Del Giorno, Mark; Close, Ryan

    2015-06-01

    As robotic ground systems advance in capabilities and begin to fulfill new roles in both civilian and military life, the limitation of slow operational speed has become a hindrance to the wide-spread adoption of these systems. For example, military convoys are reluctant to employ autonomous vehicles when these systems slow their movement from 60 miles per hour down to 40. However, these autonomous systems must operate at these lower speeds due to the limitations of the sensors they employ. Robotic Research, with its extensive experience in ground autonomy and associated problems therein, in conjunction with CERDEC/Night Vision and Electronic Sensors Directorate (NVESD), has performed a study to specify system and detection requirements; determined how current autonomy sensors perform in various scenarios; and analyzed how sensors should be employed to increase operational speeds of ground vehicles. The sensors evaluated in this study include the state of the art in LADAR/LIDAR, Radar, Electro-Optical, and Infrared sensors, and have been analyzed at high speeds to study their effectiveness in detecting and accounting for obstacles and other perception challenges. By creating a common set of testing benchmarks, and by testing in a wide range of real-world conditions, Robotic Research has evaluated where sensors can be successfully employed today; where sensors fall short; and which technologies should be examined and developed further. This study is the first step to achieve the overarching goal of doubling ground vehicle speeds on any given terrain.

  20. Technology needs for high speed rotorcraft (2)

    NASA Technical Reports Server (NTRS)

    Scott, Mark W.

    1991-01-01

    An analytical study was conducted to identify rotorcraft concepts best capable of combining a cruise speed of 350 to 450 knots with helicopter-like low speed attributes, and to define the technology advancements needed to make them viable by the year 2000. A systematic approach was used to compare the relative attributes and mission gross weights for a wide range of concepts, resulting in a downselect to the most promising concept/mission pairs. For transport missions, tilt-wing and variable diameter tilt-rotor (VDTR) concepts were found to be superior. For a military scout/attack role, the VDTR was best, although a shrouded rotor concept could provide a highly agile, low observable alternative if its weight empty fraction could be reduced. A design speed of 375 to 425 knots was found to be the maximum desirable for transport missions, with higher speed producing rapidly diminishing benefits in productivity. The key technologies that require advancement to make the tilt-wing and VDTR concepts viable are in the areas of wing and proprotor aerodynamics, efficient structural design, flight controls, refinement of the geared flap pitch control system, expansion of the speed/descent envelope, and the structural and aerodynamic tradeoffs of wing thickness and forward sweep. For the shrouded rotor, weight reduction is essential, particularly with respect to the mechanism for covering the rotor in cruise.

  1. Novel digital logic gate for high-performance CMOS imaging system

    NASA Astrophysics Data System (ADS)

    Chung, Hoon H.; Joo, Youngjoong

    2004-06-01

    In these days, the CMOS image sensors are commonly used in many low resolution applications because the CMOS imaging system has several advantages against the conventional CCD imaging system. However, there are still several problems for the realization of the single-chip CMOS imaging system. One main problem is the substrate coupling noise, which is caused by the digital switching noise. Because the CMOS image sensors share the same substrate with surrounding digital circuit, it is difficult for the CMOS image sensor to get a good performance. In order to investigate the substrate coupling noise effect of the CMOS image sensor, the conventional CMOS logic, C-CBL (Complementary-Current balanced logic) and proposed low switching noise logic are simulated and compared. Consequently, the proposed logic compensates not only the large digital switching noise of conventional CMOS logic ,but also the huge power consumption of the C-CBL. Both the total instantaneous current behaviors on the power supply and the peak-to-peak voltages of the substrate voltage variation (di/dt noise) are investigated. The simulation is performed by AMI 0.5μm CMOS technology.

  2. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    PubMed

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  3. High speed printing with polygon scan heads

    NASA Astrophysics Data System (ADS)

    Stutz, Glenn

    2016-03-01

    To reduce and in many cases eliminate the costs associated with high volume printing of consumer and industrial products, this paper investigates and validates the use of the new generation of high speed pulse on demand (POD) lasers in concert with high speed (HS) polygon scan heads (PSH). Associated costs include consumables such as printing ink and nozzles, provisioning labor, maintenance and repair expense as well as reduction of printing lines due to high through put. Targets that are applicable and investigated include direct printing on plastics, printing on paper/cardboard as well as printing on labels. Market segments would include consumer products (CPG), medical and pharmaceutical products, universal ID (UID), and industrial products. In regards to the POD lasers employed, the wavelengths include UV(355nm), Green (532nm) and IR (1064nm) operating within the repetition range of 180 to 250 KHz.

  4. Safety issues in high speed machining

    NASA Astrophysics Data System (ADS)

    1994-05-01

    There are several risks related to High-Speed Milling, but they have not been systematically determined or studied so far. Increased loads by high centrifugal forces may result in dramatic hazards. Flying tools or fragments from a tool with high kinetic energy may damage surrounding people, machines and devices. In the project, mechanical risks were evaluated, theoretic values for kinetic energies of rotating tools were calculated, possible damages of the flying objects were determined and terms to eliminate the risks were considered. The noise levels of the High-Speed Machining center owned by the Helsinki University of Technology (HUT) and the Technical Research Center of Finland (VTT) in practical machining situation were measured and the results were compared to those after basic preventive measures were taken.

  5. High speed, high current pulsed driver circuit

    DOEpatents

    Carlen, Christopher R.

    2017-03-21

    Various technologies presented herein relate to driving a LED such that the LED emits short duration pulses of light. This is accomplished by driving the LED with short duration, high amplitude current pulses. When the LED is driven by short duration, high amplitude current pulses, the LED emits light at a greater amplitude compared to when the LED is driven by continuous wave current.

  6. Data Capture Technique for High Speed Signaling

    DOEpatents

    Barrett, Wayne Melvin; Chen, Dong; Coteus, Paul William; Gara, Alan Gene; Jackson, Rory; Kopcsay, Gerard Vincent; Nathanson, Ben Jesse; Vranas, Paylos Michael; Takken, Todd E.

    2008-08-26

    A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.

  7. High Speed Blood and Fluid Transfusion Equipment

    DTIC Science & Technology

    2010-06-01

    it stores energy for heating fluid when not attached to an external power source, (2) that it provides for high heating and infusion rates, up to...8217 % High Speed Blood and Fluid Transfusion Equipment Final Report Prepared by: Rocky Research 1598 Foothill Drive Boulder City, NV 89005...University of Nevada School of Medicine Trauma Institute Department of Surgery 2040 W. Charleston Blvd #302 Las Vegas, NV 89102 Principal

  8. High dynamic range CMOS-based mammography detector for FFDM and DBT

    NASA Astrophysics Data System (ADS)

    Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

    2016-03-01

    Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

  9. High-speed civil transport study

    NASA Technical Reports Server (NTRS)

    1989-01-01

    A system study of the potential for a high-speed commercial transport has addressed technological, economic, and environmental constraints. Market projections indicate a need for fleets of transports with supersonic or greater cruise speeds by the year 2000 to 2005. The associated design requirements called for a vehicle to carry 250 to 300 passengers over a range of 5,000 to 6,000 nautical miles. The study was initially unconstrained in terms of vehicle characteristic, such as cruise speed, propulsion systems, fuels, or structural materials. Analyses led to a focus on the most promising vehicle concepts. These were concepts that used a kerosene-type fuel and cruised at Mach numbers between 2.0 to 3.2. Further systems study identified the impact of environmental constraints (for community noise, sonic boom, and engine emissions) on economic attractiveness and technological needs. Results showed that current technology cannot produce a viable high-speed civil transport; significant advances are required to reduce takeoff gross weight and allow for both economic attractiveness and environmental accepatability. Specific technological requirements were identified to meet these needs.

  10. High-speed civil transport study. Summary

    NASA Technical Reports Server (NTRS)

    1989-01-01

    A system of study of the potential for a high speed commercial transport aircraft addressed technology, economic, and environmental constraints. Market projections indicated a need for fleets of transport with supersonic or greater cruise speeds by the years 2000 to 2005. The associated design requirements called for a vehicle to carry 250 to 300 passengers over a range of 5000 to 6000 nautical miles. The study was initially unconstrained in terms of vehicle characteristics, such as cruise speed, propulsion systems, fuels, or structural materials. Analyses led to a focus on the most promising vehicle concepts. These were concepts that used a kerosene type fuel and cruised at Mach numbers between 2.0 to 3.2. Further systems study identified the impact of environmental constraints (for community noise, sonic boom, and engine emissions) on economic attractiveness and technological needs. Results showed that current technology cannot produce a viable high speed civil transport. Significant advances are needed to take off gross weight and allow for both economic attractiveness and environment acceptability. Specific technological requirements were identified to meet these needs.

  11. An ASIC memory buffer controller for a high speed disk system

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.; Campbell, Steve

    1993-01-01

    The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

  12. An ASIC memory buffer controller for a high speed disk system

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.; Campbell, Steve

    1993-01-01

    The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

  13. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 μm process with a high resistivity epitaxial layer

    NASA Astrophysics Data System (ADS)

    Senyukov, S.; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz 0.18 μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 1013neq /cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz 0.18 μm CMOS process for the ALICE ITS upgrade.

  14. High Speed Research Program Sonic Fatigue

    NASA Technical Reports Server (NTRS)

    Rizzi, Stephen A. (Technical Monitor); Beier, Theodor H.; Heaton, Paul

    2005-01-01

    The objective of this sonic fatigue summary is to provide major findings and technical results of studies, initiated in 1994, to assess sonic fatigue behavior of structure that is being considered for the High Speed Civil Transport (HSCT). High Speed Research (HSR) program objectives in the area of sonic fatigue were to predict inlet, exhaust and boundary layer acoustic loads; measure high cycle fatigue data for materials developed during the HSR program; develop advanced sonic fatigue calculation methods to reduce required conservatism in airframe designs; develop damping techniques for sonic fatigue reduction where weight effective; develop wing and fuselage sonic fatigue design requirements; and perform sonic fatigue analyses on HSCT structural concepts to provide guidance to design teams. All goals were partially achieved, but none were completed due to the premature conclusion of the HSR program. A summary of major program findings and recommendations for continued effort are included in the report.

  15. Development of a Revolutionary High Speed Spindle

    NASA Technical Reports Server (NTRS)

    Agba, Emmanuel I.

    1999-01-01

    This report presents the development of a hydraulic motor driven spindle system to be employed for high speed machining of composite materials and metals. The spindle system is conceived to be easily retrofitted into conventional milling machines. The need for the hydraulic spindle arises because of the limitations placed on conventional electric motor driven spindles by the low cutting power and the presence of vibrational phenomena associated with voltage frequency at high rotational speeds. Also, the electric motors are usually large and expensive when power requirements are moderately high. In contrast, hydraulic motor driven spindles promise a distinct increase in spindle life over the conventional electric motor driven spindles. In this report, existing technologies applicable to spindle holder for severe operating conditions were reviewed, conceptual designs of spindle holder system were developed and evaluated, and a detailed design of an acceptable concept was conducted. Finally, a rapid prototype of the design was produced for design evaluation.

  16. CMOS highly linear direct-conversion transmitter for WCDMA with fine gain accuracy

    NASA Astrophysics Data System (ADS)

    Xin, Li; Jian, Fu; Yumei, Huang; Zhiliang, Hong

    2011-08-01

    A highly linear, high output power, 0.13 μm CMOS direct conversion transmitter for wideband code division multiple access (WCDMA) is described. The transmitter delivers 6.8 dBm output power with 38 mA current consumption. With careful design on the resistor bank in the IQ-modulator, the gain step accuracy is within 0.1 dB, hence the image rejection ratio can be kept below -47 dBc for the entire output range. The adjacent channel leakage ratio and the LO leakage at 6.8 dBm output power are -44 dBc @ 5 MHz and -37 dBc, respectively, and the corresponding EVM is 3.6%. The overall gain can be programmed in 6 dB steps in a 66-dB range.

  17. An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

    PubMed Central

    Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

    2014-01-01

    In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. PMID:25517692

  18. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

    NASA Astrophysics Data System (ADS)

    Tao, Yang; Yu, Jiang; Shengyou, Liu; Guiliang, Guo; Yuepeng, Yan

    2015-06-01

    This paper presents a low power, high sensitivity Gaussian frequency shift keying (GFSK) demodulator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The receiver uses a low-IF (1.5 MHz) architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with ± 180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate (BER), and consumes no more than 0.26 mA from a 1.8 V power supply. Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

  19. A High Performance CMOS Current Mirror Circuit with Neuron MOSFETs and a Transimpedance Amplifier

    NASA Astrophysics Data System (ADS)

    Shimizu, Akio; Ishikawa, Yohei; Fukai, Sumio; Aikawa, Masayoshi

    In this paper, we propose a high accuracy current mirror circuit suitable for a low-voltage operation. The proposed circuit has a novel negative feedback that is composed of neuron MOSFETs and a transimpedance amplifier. As a result, the proposed circuit achieves a high accuracy current mirror circuit. At the same time, the proposed circuit monitors an error current by a low voltage because the negative feedback operates in a current-mode. The performance of the proposed circuit is evaluated using HSPICE simulation with On-Semiconductor 1.48μm CMOS device parameters. Simulation results show that the output resistance of the proposed circuit is 5.79[GΩ] and minimum operating range is 0.3[V].

  20. An analog gamma correction scheme for high dynamic range CMOS logarithmic image sensors.

    PubMed

    Cao, Yuan; Pan, Xiaofang; Zhao, Xiaojin; Wu, Huisi

    2014-12-15

    In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process.

  1. Architectures and applications of high-speed vision

    NASA Astrophysics Data System (ADS)

    Watanabe, Yoshihiro; Oku, Hiromasa; Ishikawa, Masatoshi

    2014-11-01

    With the progress made in high-speed imaging technology, image processing systems that can process images at high frame rates, as well as their applications, are expected. In this article, we examine architectures for high-speed vision systems, and also dynamic image control, which can realize high-speed active optical systems. In addition, we also give an overview of some applications in which high-speed vision is used, including man-machine interfaces, image sensing, interactive displays, high-speed three-dimensional sensing, high-speed digital archiving, microvisual feedback, and high-speed intelligent robots.

  2. Abbreviated annealing of high-speed steel

    SciTech Connect

    Zablotskii, V.K.; Bartel, G.P.

    1987-07-01

    The authors investigate the structural and phase transformations during the heating, holding, and cooling of high-speed steels of two basic groups: tungsten (R18, R12, R12F3, and R12F4K5) and tungsten-molybdenum (R6M5, 10R6M5, R6M5K5, R8M3, 10R8M3, and R8M3K6S) steels in the forged state. They propose a cooling regime with complete alpha-gamma recrystallization whose implementation at a Soviet steel plant has made it possible to reduce the duration of heat treatment and increase productivity by 20% in cutting the annealed high-speed steels.

  3. High-speed massively parallel scanning

    DOEpatents

    Decker, Derek E.

    2010-07-06

    A new technique for recording a series of images of a high-speed event (such as, but not limited to: ballistics, explosives, laser induced changes in materials, etc.) is presented. Such technique(s) makes use of a lenslet array to take image picture elements (pixels) and concentrate light from each pixel into a spot that is much smaller than the pixel. This array of spots illuminates a detector region (e.g., film, as one embodiment) which is scanned transverse to the light, creating tracks of exposed regions. Each track is a time history of the light intensity for a single pixel. By appropriately configuring the array of concentrated spots with respect to the scanning direction of the detection material, different tracks fit between pixels and sufficient lengths are possible which can be of interest in several high-speed imaging applications.

  4. Pulse Detonation Engines for High Speed Flight

    NASA Technical Reports Server (NTRS)

    Povinelli, Louis A.

    2002-01-01

    Revolutionary concepts in propulsion are required in order to achieve high-speed cruise capability in the atmosphere and for low cost reliable systems for earth to orbit missions. One of the advanced concepts under study is the air-breathing pulse detonation engine. Additional work remains in order to establish the role and performance of a PDE in flight applications, either as a stand-alone device or as part of a combined cycle system. In this paper, we shall offer a few remarks on some of these remaining issues, i.e., combined cycle systems, nozzles and exhaust systems and thrust per unit frontal area limitations. Currently, an intensive experimental and numerical effort is underway in order to quantify the propulsion performance characteristics of this device. In this paper, we shall highlight our recent efforts to elucidate the propulsion potential of pulse detonation engines and their possible application to high-speed or hypersonic systems.

  5. High-speed tensile test instrument.

    PubMed

    Mott, P H; Twigg, J N; Roland, D F; Schrader, H S; Pathak, J A; Roland, C M

    2007-04-01

    A novel high-speed tensile test instrument is described, capable of measuring the mechanical response of elastomers at strain rates ranging from 10 to 1600 s(-1) for strains through failure. The device employs a drop weight that engages levers to stretch a sample on a horizontal track. To improve dynamic equilibrium, a common problem in high speed testing, equal and opposite loading was applied to each end of the sample. Demonstrative results are reported for two elastomers at strain rates to 588 s(-1) with maximum strains of 4.3. At the higher strain rates, there is a substantial inertial contribution to the measured force, an effect unaccounted for in prior works using the drop weight technique. The strain rates were essentially constant over most of the strain range and fill a three-decade gap in the data from existing methods.

  6. High speed receiver for capsule endoscope.

    PubMed

    Woo, S H; Yoon, K W; Moon, Y K; Lee, J H; Park, H J; Kim, T W; Choi, H C; Won, C H; Cho, J H

    2010-10-01

    In this study, a high-speed receiver for a capsule endoscope was proposed and implemented. The proposed receiver could receive 20 Mbps data that was sufficient to receive images with a higher resolution than conventional receivers. The receiver used a 1.2 GHz band to receive radio frequency (RF) signal, and demodulated the signal to an intermediate frequency (IF) stage (150 MHz). The demodulated signal was amplified, filtered, and under-sampled by a high-speed analog-to-digital converter (ADC). In order to decode the under-sampled data in real time, a simple frequency detection algorithm was selected and was implemented by using a FPGA. The implemented system could receive 20 Mbps data.

  7. The NASA high-speed turboprop program

    NASA Technical Reports Server (NTRS)

    Dugan, J. F.; Miller, B. A.; Graber, E. J.; Sagerser, D. A.

    1980-01-01

    Technology readiness for Mach 0.7 to 0.8 turboprop powered aircraft with the potential for fuel savings and DOC reductions of up to 30 and 15 percent respectively relative to current in-service aircraft is addressed. The areas of propeller aeroacoustics, propeller structures, turboprop installed performance, aircraft cabin environment, and turboprop engine and aircraft studies are emphasized. Large scale propeller characteristics and high speed propeller flight research tests using a modified testbed aircraft are also considered.

  8. The high-speed camera ULTRACAM

    NASA Astrophysics Data System (ADS)

    Marsh, T. R.; Dhillon, V. S.

    2006-08-01

    ULTRACAM is a high-speed, tri-band CCD camera designed for observations of time variable celestial objects. Commissioned on the 4.2m WHT in La Palma, it has now been used for observations of many types of phenomena and objects including stellar occultations, accreting black-holes, neutron stars and white dwarfs, pulsars, eclipsing binaries and pulsating stars. In this paper we describe the salient features of ULTRACAM and discuss some of the results of its use.

  9. High-speed Digital Color Imaging Pyrometry

    DTIC Science & Technology

    2011-08-01

    and environment of the events. To overcome these challenges, we have characterized and calibrated a digital high-speed color camera that may be...correction) to determine their effect on the calculated temperature. Using this technique with a Phantom color camera , we measured the temperature of...constant value of approximately 1980~K. 15. SUBJECT TERMS Pyrometry, color camera 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT

  10. High-resolution extremity cone-beam CT with a CMOS detector: task-based optimization of scintillator thickness

    NASA Astrophysics Data System (ADS)

    Cao, Q.; Brehler, M.; Sisniega, A.; Stayman, J. W.; Yorkston, J.; Siewerdsen, J. H.; Zbijewski, W.

    2017-03-01

    Purpose: CMOS x-ray detectors offer small pixel sizes and low electronic noise that may support the development of novel high-resolution imaging applications of cone-beam CT (CBCT). We investigate the effects of CsI scintillator thickness on the performance of CMOS detectors in high resolution imaging tasks, in particular in quantitative imaging of bone microstructure in extremity CBCT. Methods: A scintillator thickness-dependent cascaded systems model of CMOS x-ray detectors was developed. Detectability in low-, high- and ultra-high resolution imaging tasks (Gaussian with FWHM of 250 μm, 80 μm and 40 μm, respectively) was studied as a function of scintillator thickness using the theoretical model. Experimental studies were performed on a CBCT test bench equipped with DALSA Xineos3030 CMOS detectors (99 μm pixels) with CsI scintillator thicknesses of 400 μm and 700 μm, and a 0.3 FS compact rotating anode x-ray source. The evaluation involved a radiographic resolution gauge (0.6-5.0 lp/mm), a 127 μm tungsten wire for assessment of 3D resolution, a contrast phantom with tissue-mimicking inserts, and an excised fragment of human tibia for visual assessment of fine trabecular detail. Results: Experimental studies show 35% improvement in the frequency of 50% MTF modulation when using the 400 μm scintillator compared to the standard nominal CsI thickness of 700 μm. Even though the high-frequency DQE of the two detectors is comparable, theoretical studies show a 14% to 28% increase in detectability index (d'2) of high- and ultra- high resolution tasks, respectively, for the detector with 400 μm CsI compared to 700 μm CsI. Experiments confirm the theoretical findings, showing improvements with the adoption of 400 μm panel in the visibility of the radiographic pattern (2x improvement in peak-to-through distance at 4.6 lp/mm) and a 12.5% decrease in the FWHM of the tungsten wire. Reconstructions of the tibial plateau reveal enhanced visibility of trabecular

  11. An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors

    NASA Astrophysics Data System (ADS)

    Gao, Zhiqiang; Luan, Bo; Zhao, Jincai; Liu, Xiaowei

    2017-03-01

    In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz1/2 at 2 Hz, the equivalent input noise spectral density 17 nV/Hz1/2(@2Hz) is achieved. The chip-scale package of the TMR sensor and the instrumentation amplifier is only about 5 mm × 5 mm × 1 mm, while the whole DC current dissipates only 2 mA.

  12. Fibre-optic coupling to high-resolution CCD and CMOS image sensors

    NASA Astrophysics Data System (ADS)

    van Silfhout, R. G.; Kachatkou, A. S.

    2008-12-01

    We describe a simple method of gluing fibre-optic faceplates to complementary metal oxide semiconductor (CMOS) active pixel and charge coupled device (CCD) image sensors and report on their performance. Cross-sectional cuts reveal that the bonding layer has a thickness close to the diameter of the individual fibres and is uniform over the whole sensor area. Our method requires no special tools or alignment equipment and gives reproducible and high-quality results. The method maintains a uniform bond layer thickness even if sensor dies are mounted at slight angles with their package. These fibre-coupled sensors are of particular interest to X-ray imaging applications but also provide a solution for compact optical imaging systems.

  13. A high linearity X-band SOI CMOS digitally-controlled phase shifter

    NASA Astrophysics Data System (ADS)

    Liang, Chen; Xinyu, Chen; Youtao, Zhang; Zhiqun, Li; Lei, Yang

    2015-06-01

    This paper proposed an X-band 6-bit passive phase shifter (PS) designed in 0.18 μm silicon-on-insulator (SOI) CMOS technology, which solves the key problem of high integration degree, low power, and a small size T/R module. The switched-topology is employed to achieve broadband and flat phase shift. The ESD circuit and driver are also integrated in the PS. It covers the frequency band from 7.5 to 10.5 GHz with an EMS phase error less than 7.5°. The input and output VSWRs are less than 2 and the insertion loss (IL) is between 8-14 dB across the 7.5 to 10.5 GHz, with a maximum IL difference of 4 dB. The input 1 dB compression point (IP1dB) is 20 dBm.

  14. Technology needs for high speed rotorcraft (3)

    NASA Technical Reports Server (NTRS)

    Detore, Jack; Conway, Scott

    1991-01-01

    The spectrum of vertical takeoff and landing (VTOL) type aircraft is examined to determine which aircraft are most likely to achieve high subsonic cruise speeds and have hover qualities similar to a helicopter. Two civil mission profiles are considered: a 600-n.mi. mission for a 15- and a 30-passenger payload. Applying current technology, only the 15- and 30-passenger tiltfold aircraft are capable of attaining the 450-knot design goal. The two tiltfold aircraft at 450 knots and a 30-passenger tiltrotor at 375 knots were further developed for the Task II technology analysis. A program called High-Speed Total Envelope Proprotor (HI-STEP) is recommended to meet several of these issues based on the tiltrotor concept. A program called Tiltfold System (TFS) is recommended based on the tiltrotor concept. A task is identified to resolve the best design speed from productivity and demand considerations based on the technology that emerges from the recommended programs. HI-STEP's goals are to investigate propulsive efficiency, maneuver loads, and aeroelastic stability. Programs currently in progress that may meet the other technology needs include the Integrated High Performance Turbine Engine Technology (IHPTET) (NASA Lewis) and the Advanced Structural Concepts Program funded through NASA Langley.

  15. MM-122: High speed civil transport

    NASA Technical Reports Server (NTRS)

    Demarest, Bill; Anders, Kurt; Manchec, John; Yang, Eric; Overgaard, Dan; Kalkwarf, Mike

    1992-01-01

    The rapidly expanding Pacific Rim market along with other growing markets indicates that the future market potential for a high speed civil transport is great indeed. The MM-122 is the answer to the international market desire for a state of the art, long range, high speed civil transport. It will carry 250 passengers a distance of 5200 nm at over twice the speed of sound. The MM-122 is designed to incorporate the latest technologies in the areas of control systems, propulsions, aerodynamics, and materials. The MM-122 will accomplish these goals using the following design parameters. First, a double delta wing planform with highly swept canards and an appropriately area ruled fuselage will be incorporated to accomplish desired aerodynamic characteristics. Propulsion will be provided by four low bypass variable cycle turbofan engines. A quad-redundant fly-by-wire flight control system will be incorporated to provide appropriate static stability and level 1 handling qualities. Finally, the latest in conventional metallic and modern composite materials will be used to provide desired weight and performance characteristics. The MM-122 incorporates the latest in technology and cost minimization techniques to provide a viable solution to this future market potential.

  16. 14 CFR 25.253 - High-speed characteristics.

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... 14 Aeronautics and Space 1 2014-01-01 2014-01-01 false High-speed characteristics. 25.253 Section...-speed characteristics. (a) Speed increase and recovery characteristics. The following speed increase and... inadvertent speed increases (including upsets in pitch and roll) must be simulated with the airplane trimmed...

  17. 14 CFR 25.253 - High-speed characteristics.

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... 14 Aeronautics and Space 1 2013-01-01 2013-01-01 false High-speed characteristics. 25.253 Section...-speed characteristics. (a) Speed increase and recovery characteristics. The following speed increase and... inadvertent speed increases (including upsets in pitch and roll) must be simulated with the airplane trimmed...

  18. Experimental and theoretical performance analysis for a CMOS-based high resolution image detector

    PubMed Central

    Jain, Amit; Bednarek, Daniel R.; Rudin, Stephen

    2014-01-01

    Increasing complexity of endovascular interventional procedures requires superior x-ray imaging quality. Present state-of-the-art x-ray imaging detectors may not be adequate due to their inherent noise and resolution limitations. With recent developments, CMOS based detectors are presenting an option to fulfill the need for better image quality. For this work, a new CMOS detector has been analyzed experimentally and theoretically in terms of sensitivity, MTF and DQE. The detector (Dexela Model 1207, Perkin-Elmer Co., London, UK) features 14-bit image acquisition, a CsI phosphor, 75 µm pixels and an active area of 12 cm × 7 cm with over 30 fps frame rate. This detector has two modes of operations with two different full-well capacities: high and low sensitivity. The sensitivity and instrumentation noise equivalent exposure (INEE) were calculated for both modes. The detector modulation-transfer function (MTF), noise-power spectra (NPS) and detective quantum efficiency (DQE) were measured using an RQA5 spectrum. For the theoretical performance evaluation, a linear cascade model with an added aliasing stage was used. The detector showed excellent linearity in both modes. The sensitivity and the INEE of the detector were found to be 31.55 DN/µR and 0.55 µR in high sensitivity mode, while they were 9.87 DN/µR and 2.77 µR in low sensitivity mode. The theoretical and experimental values for the MTF and DQE showed close agreement with good DQE even at fluoroscopic exposure levels. In summary, the Dexela detector's imaging performance in terms of sensitivity, linear system metrics, and INEE demonstrates that it can overcome the noise and resolution limitations of present state-of-the-art x-ray detectors. PMID:25300571

  19. Experimental and theoretical performance analysis for a CMOS-based high resolution image detector

    NASA Astrophysics Data System (ADS)

    Jain, Amit; Bednarek, Daniel R.; Rudin, Stephen

    2014-03-01

    Increasing complexity of endovascular interventional procedures requires superior x-ray imaging quality. Present stateof- the-art x-ray imaging detectors may not be adequate due to their inherent noise and resolution limitations. With recent developments, CMOS based detectors are presenting an option to fulfill the need for better image quality. For this work, a new CMOS detector has been analyzed experimentally and theoretically in terms of sensitivity, MTF and DQE. The detector (Dexela Model 1207, Perkin-Elmer Co., London, UK) features 14-bit image acquisition, a CsI phosphor, 75 μm pixels and an active area of 12 cm x 7 cm with over 30 fps frame rate. This detector has two modes of operations with two different full-well capacities: high and low sensitivity. The sensitivity and instrumentation noise equivalent exposure (INEE) were calculated for both modes. The detector modulation-transfer function (MTF), noise-power spectra (NPS) and detective quantum efficiency (DQE) were measured using an RQA5 spectrum. For the theoretical performance evaluation, a linear cascade model with an added aliasing stage was used. The detector showed excellent linearity in both modes. The sensitivity and the INEE of the detector were found to be 31.55 DN/μR and 0.55 μR in high sensitivity mode, while they were 9.87 DN/μR and 2.77 μR in low sensitivity mode. The theoretical and experimental values for the MTF and DQE showed close agreement with good DQE even at fluoroscopic exposure levels. In summary, the Dexela detector's imaging performance in terms of sensitivity, linear system metrics, and INEE demonstrates that it can overcome the noise and resolution limitations of present state-of-the-art x-ray detectors.

  20. Experimental and theoretical performance analysis for a CMOS-based high resolution image detector.

    PubMed

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2014-03-19

    Increasing complexity of endovascular interventional procedures requires superior x-ray imaging quality. Present state-of-the-art x-ray imaging detectors may not be adequate due to their inherent noise and resolution limitations. With recent developments, CMOS based detectors are presenting an option to fulfill the need for better image quality. For this work, a new CMOS detector has been analyzed experimentally and theoretically in terms of sensitivity, MTF and DQE. The detector (Dexela Model 1207, Perkin-Elmer Co., London, UK) features 14-bit image acquisition, a CsI phosphor, 75 µm pixels and an active area of 12 cm × 7 cm with over 30 fps frame rate. This detector has two modes of operations with two different full-well capacities: high and low sensitivity. The sensitivity and instrumentation noise equivalent exposure (INEE) were calculated for both modes. The detector modulation-transfer function (MTF), noise-power spectra (NPS) and detective quantum efficiency (DQE) were measured using an RQA5 spectrum. For the theoretical performance evaluation, a linear cascade model with an added aliasing stage was used. The detector showed excellent linearity in both modes. The sensitivity and the INEE of the detector were found to be 31.55 DN/µR and 0.55 µR in high sensitivity mode, while they were 9.87 DN/µR and 2.77 µR in low sensitivity mode. The theoretical and experimental values for the MTF and DQE showed close agreement with good DQE even at fluoroscopic exposure levels. In summary, the Dexela detector's imaging performance in terms of sensitivity, linear system metrics, and INEE demonstrates that it can overcome the noise and resolution limitations of present state-of-the-art x-ray detectors.

  1. High speed GaN micro-light-emitting diode arrays for data communications

    NASA Astrophysics Data System (ADS)

    Watson, Scott; McKendry, Jonathan J. D.; Zhang, Shuailong; Massoubre, David; Rae, Bruce R.; Green, Richard P.; Gu, Erdan; Henderson, Robert K.; Kelly, A. E.; Dawson, Martin D.

    2012-10-01

    Micro light-emitting diode (micro-LED) arrays based on an AlInGaN structure have attracted much interest recently as light sources for data communications. Visible light communication (VLC), over free space or plastic optical fibre (POF), has become a very important technique in the role of data transmission. The micro-LEDs which are reported here contain pixels ranging in diameter from 14 to 84μm and can be driven directly using a high speed probe or via complementary metal-oxide semiconductor (CMOS) technology. The CMOS arrays allow for easy, computer control of individual pixels within arrays containing up to 16×16 elements. The micro-LEDs best suited for data transmission have peak emissions of 450nm or 520nm, however various other wavelengths across the visible spectrum can also be used. Optical modulation bandwidths of over 400MHz have been achieved as well as error-free (defined as an error rate of <1x10-10) data transmission using on-off keying (OOK) non-return-to-zero (NRZ) modulation at data rates of over 500Mbit/s over free space. Also, as a step towards a more practical multi-emitter data transmitter, the frequency response of a micro-LED integrated with CMOS circuitry was measured and found to be up to 185MHz. Despite the reduction in bandwidth compared to the bare measurements using a high speed probe, a good compromise is achieved from the additional control available to select each pixel. It has been shown that modulating more than one pixel simultaneously can increase the data rate. As work continues in this area, the aim will be to further increase the data transmission rate by modulating more pixels on a single device to transmit multiple parallel data channels simultaneously.

  2. High-Speed, High-Resolution Time-to-Digital Conversion

    NASA Technical Reports Server (NTRS)

    Katz, Richard; Kleyner, Igor; Garcia, Rafael

    2013-01-01

    This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

  3. Cryogenic, high speed, turbopump bearing cooling requirements

    NASA Technical Reports Server (NTRS)

    Dolan, Fred J.; Gibson, Howard G.; Cannon, James L.; Cody, Joe C.

    1988-01-01

    Although the Space Shuttle Main Engine (SSME) has repeatedly demonstrated the capability to perform during launch, the High Pressure Oxidizer Turbopump (HPOTP) main shaft bearings have not met their 7.5 hour life requirement. A tester is being employed to provide the capability of subjecting full scale bearings and seals to speeds, loads, propellants, temperatures, and pressures which simulate engine operating conditions. The tester design permits much more elaborate instrumentation and diagnostics than could be accommodated in an SSME turbopump. Tests were made to demonstrate the facilities; and the devices' capabilities, to verify the instruments in its operating environment and to establish a performance baseline for the flight type SSME HPOTP Turbine Bearing design. Bearing performance data from tests are being utilized to generate: (1) a high speed, cryogenic turbopump bearing computer mechanical model, and (2) a much improved, very detailed thermal model to better understand bearing internal operating conditions. Parametric tests were also made to determine the effects of speed, axial loads, coolant flow rate, and surface finish degradation on bearing performance.

  4. Pressure Distribution Over Airfoils at High Speeds

    NASA Technical Reports Server (NTRS)

    Briggs, L J; Dryden, H L

    1927-01-01

    This report deals with the pressure distribution over airfoils at high speeds, and describes an extension of an investigation of the aerodynamic characteristics of certain airfoils which was presented in NACA Technical Report no. 207. The results presented in report no. 207 have been confirmed and extended to higher speeds through a more extensive and systematic series of tests. Observations were also made of the air flow near the surface of the airfoils, and the large changes in lift coefficients were shown to be associated with a sudden breaking away of the flow from the upper surface. The tests were made on models of 1-inch chord and comparison with the earlier measurements on models of 3-inch chord shows that the sudden change in the lift coefficient is due to compressibility and not to a change in the Reynolds number. The Reynolds number still has a large effect, however, on the drag coefficient. The pressure distribution observations furnish the propeller designer with data on the load distribution at high speeds, and also give a better picture of the air-flow changes.

  5. High-speed multichannel optical switching

    SciTech Connect

    Mikaelian, A.L.; Salakhutdinov, V.K.

    1994-12-31

    The programmable interconnection between N input and N output channels based on a matrix of microholograms is considered. Such a system can be used for optical switching having high speed, about gigabits-per-second. An example of such a system using bacteriorhodopsin film is investigated both theoretically and experimentally. The thickness of bacteriorhodopsin was 50 {micro}m and the cell size 3cmx2cm. To maintain interconnects each microhologram was regenerated by means of a routing system composed of a He-Ne laser, deflectors and optical elements. Experimentally, 20 channels were used. The diameter of the microhologram was 1 mm, and the diffraction efficiency was about 2%. The tests and calculations show the possibility of arranging 10{sup 4} switching channels with speed about 1 gigabit per second.

  6. Thermomechanical phenomena in high speed rubbing

    NASA Technical Reports Server (NTRS)

    Kennedy, F. E.

    1980-01-01

    An analytical approach is presented for the modeling of the thermomechanical interactions which occur in high speed sliding situations. These sliding contact problems which are characterized by active and interrelated thermal and mechanical phenomena could be called 'rub energetics' problems. Analytical models were developed to simulate two different rub situations: high energy braking of disk brakes and high speed rubs of gas path seals in turbine engines. The models proved to be particularly useful in predicting the severe temperatures and deformations near hot contact patches on the rubbing surfaces. The size of the hot patches is generally determined by normal load and the properties of the contacting materials. Temperatures at the contact patches can approach the melting point of the materials, especially at high sliding velocities. These high temperatures can lead to large amounts of near-surface deformation and high wear rates. Decreased contact temperatures can result from using materials with increased thermal conductivity and increased heat capacity or choosing mechanical properties (decreased stiffness, yield stress or coefficient of thermal expansion) which give larger hot spot size.

  7. High-Speed Propeller for Aircraft

    NASA Technical Reports Server (NTRS)

    Sagerser, D. A.; Gatzen, B. S.

    1986-01-01

    Engine efficiency increased. Propeller blades required to be quite thin and highly swept to minimize compressibility losses and propeller noise during high-speed cruise. Use of 8 or 10 blades with highpropeller-power loading allows overall propeller diameter to be kept relatively small. Area-ruled spinner and integrated nacelle shape reduce compressibility losses in propeller hub region. Finally, large modern turboshaft engine and gearbox provide power to advanced propeller. Fuel savings of 30 to 50 percent over present systems anticipated. Propfan system adaptable to number of applications, such as highspeed (subsonic) business and general-aviation aircraft, and military aircraft including V/STOL.

  8. An SAE high speed ring bus overview

    NASA Astrophysics Data System (ADS)

    Kroeger, Brian W.; Shih, Hubert

    An overview of the protocols and important features of the SAE high-speed ring bus (HSRB) standard is presented here, along with the functional design of a typical ring interface unit architecture. The counterrotating ring topology, with both loopback and bypass mechanisms, provides the high degree of fault tolerance desirable in many military and avionic systems. The error-detection, fault-detection, and recovery mechanisms are briefly described to illustrate the robustness of the HSRB system. The reserved-priority token-passing protocol is shown to provide efficient and deterministic performance, uselful in real-time applications where messages must be transmitted predictably, quickly, and reliably.

  9. Conclusions from high-speed rotorcraft studies

    NASA Technical Reports Server (NTRS)

    Conway, Scott

    1991-01-01

    Under the tutelage of NASA-Ames, evaluations have been made of the technology required for high-speed rotorcraft flight with a view to the performance potential and development risks of several candidate configurations. Configurational performance limitations were associated with rotor performance at high Mach numbers and advance ratios, nacelle interference effects on rotor flow, and wing/rotor aeroelastic stability requirements. Attention is given to tiltwing, tilt-for-VTOL/fold-for-cruise rotor, and conventional tiltrotor configurations capable of carrying 30 passengers for the intercity commuter market.

  10. Anti-scatter grid artifact elimination for high resolution x-ray imaging CMOS detectors

    PubMed Central

    Rana, R.; Singh, V.; Jain, A.; Bednarek, D.R.; Rudin, S.

    2015-01-01

    Higher resolution in dynamic radiological imaging such as angiography is increasingly being demanded by clinicians; however, when standard anti-scatter grids are used with such new high resolution detectors, grid-line artifacts become more apparent resulting in increased structured noise that may overcome the contrast signal improvement benefits of the scatter-reducing grid. Although grid-lines may in theory be eliminated by dividing the image of a patient taken with the grid by a flat-field image taken with the grid obtained prior to the clinical image, unless the remaining additive scatter contribution is subtracted in real-time from the dynamic clinical image sequence before the division by the reference image, severe grid-line artifacts may remain. To investigate grid-line elimination, a stationary Smit Röntgen X-ray grid (line density: 70 lines/cm, grid ratio 13:1) was used with both a 75 micron-pixel CMOS detector and a standard 194 micron-pixel flat panel detector (FPD) to image an artery block insert placed in a modified uniform frontal head phantom for a 20 × 20cm FOV (approximately). Contrast and contrast-to-noise ratio (CNR) were measured with and without scatter subtraction prior to grid-line correction. The fixed pattern noise caused by the grid was substantially higher for the CMOS detector compared to the FPD and caused a severe reduction of CNR. However, when the scatter subtraction corrective method was used, the removal of the fixed pattern noise (grid artifacts) became evident resulting in images with improved CNR. PMID:26877578

  11. Anti-scatter grid artifact elimination for high resolution x-ray imaging CMOS detectors.

    PubMed

    Rana, R; Singh, V; Jain, A; Bednarek, D R; Rudin, S

    Higher resolution in dynamic radiological imaging such as angiography is increasingly being demanded by clinicians; however, when standard anti-scatter grids are used with such new high resolution detectors, grid-line artifacts become more apparent resulting in increased structured noise that may overcome the contrast signal improvement benefits of the scatter-reducing grid. Although grid-lines may in theory be eliminated by dividing the image of a patient taken with the grid by a flat-field image taken with the grid obtained prior to the clinical image, unless the remaining additive scatter contribution is subtracted in real-time from the dynamic clinical image sequence before the division by the reference image, severe grid-line artifacts may remain. To investigate grid-line elimination, a stationary Smit Röntgen X-ray grid (line density: 70 lines/cm, grid ratio 13:1) was used with both a 75 micron-pixel CMOS detector and a standard 194 micron-pixel flat panel detector (FPD) to image an artery block insert placed in a modified uniform frontal head phantom for a 20 × 20cm FOV (approximately). Contrast and contrast-to-noise ratio (CNR) were measured with and without scatter subtraction prior to grid-line correction. The fixed pattern noise caused by the grid was substantially higher for the CMOS detector compared to the FPD and caused a severe reduction of CNR. However, when the scatter subtraction corrective method was used, the removal of the fixed pattern noise (grid artifacts) became evident resulting in images with improved CNR.

  12. Anti-scatter grid artifact elimination for high resolution x-ray imaging CMOS detectors

    NASA Astrophysics Data System (ADS)

    Rana, R.; Singh, V.; Jain, A.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Higher resolution in dynamic radiological imaging such as angiography is increasingly being demanded by clinicians; however, when standard anti-scatter grids are used with such new high resolution detectors, grid-line artifacts become more apparent resulting in increased structured noise that may overcome the contrast signal improvement benefits of the scatter-reducing grid. Although grid-lines may in theory be eliminated by dividing the image of a patient taken with the grid by a flat-field image taken with the grid obtained prior to the clinical image, unless the remaining additive scatter contribution is subtracted in real-time from the dynamic clinical image sequence before the division by the reference image, severe grid-line artifacts may remain. To investigate grid-line elimination, a stationary Smit Röntgen X-ray grid (line density: 70 lines/cm, grid ratio 13:1) was used with both a 75 micron-pixel CMOS detector and a standard 194 micron-pixel flat panel detector (FPD) to image an artery block insert placed in a modified uniform frontal head phantom for a 20 x 20cm FOV (approximately). Contrast and contrast-to-noise ratio (CNR) were measured with and without scatter subtraction prior to grid-line correction. The fixed pattern noise caused by the grid was substantially higher for the CMOS detector compared to the FPD and caused a severe reduction of CNR. However, when the scatter subtraction corrective method was used, the removal of the fixed pattern noise (grid artifacts) became evident resulting in images with improved CNR.

  13. Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

    NASA Astrophysics Data System (ADS)

    Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2012-04-01

    In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

  14. High-Speed, high-power, switching transistor

    NASA Technical Reports Server (NTRS)

    Carnahan, D.; Ohu, C. K.; Hower, P. L.

    1979-01-01

    Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

  15. High-speed high-efficiency photodetectors based on heterostructures

    NASA Astrophysics Data System (ADS)

    Korolkov, V. I.

    Recent advances in the development of high-speed high-efficiency heterostructure photodetectors (HPs) are reviewed. It is noted that the performance of semiconductor photodetectors has been improved by forbidden bandwidth control. Various types of HPs are examined, including modifications of heterophotodiodes and detectors with internal amplification; avalanche photodiodes; bipolar phototransistors; and planar photoresistance devices and field-effect phototransistors. These devices are compared in terms of speed and efficiency.

  16. High-Speed, high-power, switching transistor

    NASA Technical Reports Server (NTRS)

    Carnahan, D.; Ohu, C. K.; Hower, P. L.

    1979-01-01

    Silicon transistor rate for 200 angstroms at 400 to 600 volts combines switching speed of transistors with ruggedness, power capacity of thyristor. Transistor introduces unique combination of increased power-handling capability, unusally low saturation and switching losses, and submicrosecond switching speeds. Potential applications include high power switching regulators, linear amplifiers, chopper controls for high frequency electrical vehicle drives, VLF transmitters, RF induction heaters, kitchen cooking ranges, and electronic scalpels for medical surgery.

  17. Three-Dimensional Image Cytometer Based on Widefield Structured Light Microscopy and High-Speed Remote Depth Scanning

    PubMed Central

    Choi, Heejin; Wadduwage, Dushan N.; Tu, Ting Yuan; Matsudaira, Paul; So, Peter T. C.

    2014-01-01

    A high throughput 3D image cytometer have been developed that improves imaging speed by an order of magnitude over current technologies. This imaging speed improvement was realized by combining several key components. First, a depth-resolved image can be rapidly generated using a structured light reconstruction algorithm that requires only two wide field images, one with uniform illumination and the other with structured illumination. Second, depth scanning is implemented using the high speed remote depth scanning. Finally, the large field of view, high NA objective lens and the high pixelation, high frame rate sCMOS camera enable high resolution, high sensitivity imaging of a large cell population. This system can image at 800 cell/sec in 3D at submicron resolution corresponding to imaging 1 million cells in 20 min. The statistical accuracy of this instrument is verified by quantitatively measuring rare cell populations with ratio ranging from 1:1 to 1:105. PMID:25352187

  18. Exhaust emissions from high speed passenger ferries

    NASA Astrophysics Data System (ADS)

    Cooper, D. A.

    Exhaust emission measurements have been carried out on-board three high-speed passenger ferries (A, B and C) during normal service routes. Ship A was powered by conventional, medium-speed, marine diesel engines, Ship B by gas turbine engines and Ship C conventional, medium-speed, marine diesel engines equipped with selective catalytic reduction (SCR) systems for NO x abatement. All ships had similar auxiliary engines (marine diesels) for generating electric power on-board. Real-world emission factors of NOx, SO2, CO, CO 2, NMVOC, CH4, N2O, NH3, PM and PAH at steady-state engine loads and for complete voyages were determined together with an estimate of annual emissions. In general, Ship B using gas turbines showed favourable NO x, PM and PAH emissions but at the expense of higher fuel consumption and CO 2 emissions. Ship C with the SCR had the lowest NO x emissions but highest NH 3 emissions especially during harbour approaches and stops. The greatest PM and PAH specific emissions were measured from auxiliary engines operating at low engine loads during harbour stops. Since all ships used a low-sulphur gas oil, SO 2 emissions were relatively low in all cases.

  19. High-speed Civil Transport Aircraft Emissions

    NASA Technical Reports Server (NTRS)

    Miake-Lye, Richard C.; Matulaitis, J. A.; Krause, F. H.; Dodds, Willard J.; Albers, Martin; Hourmouziadis, J.; Hasel, K. L.; Lohmann, R. P.; Stander, C.; Gerstle, John H.

    1992-01-01

    Estimates are given for the emissions from a proposed high speed civil transport (HSCT). This advanced technology supersonic aircraft would fly in the lower stratosphere at a speed of roughly Mach 1.6 to 3.2 (470 to 950 m/sec or 920 to 1850 knots). Because it would fly in the stratosphere at an altitude in the range of 15 to 23 km commensurate with its design speed, its exhaust effluents could perturb the chemical balance in the upper atmosphere. The first step in determining the nature and magnitude of any chemical changes in the atmosphere resulting from these proposed aircraft is to identify and quantify the chemically important species they emit. Relevant earlier work is summarized, dating back to the Climatic Impact Assessment Program of the early 1970s and current propulsion research efforts. Estimates are provided of the chemical composition of an HSCT's exhaust, and these emission indices are presented. Other aircraft emissions that are not due to combustion processes are also summarized; these emissions are found to be much smaller than the exhaust emissions. Future advances in propulsion technology, in experimental measurement techniques, and in understanding upper atmospheric chemistry may affect these estimates of the amounts of trace exhaust species or their relative importance.

  20. High photon detection efficiency single photon avalanche diode in 0.18 μm standard CMOS process

    NASA Astrophysics Data System (ADS)

    Wang, Wei; Bao, Xiaoyuan; Chen, Li; Chen, Ting; Wang, Guanyu; Yuan, Jun

    2017-06-01

    This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 μm standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.

  1. 14 CFR 23.253 - High speed characteristics.

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... 14 Aeronautics and Space 1 2011-01-01 2011-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

  2. 14 CFR 23.253 - High speed characteristics.

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... 14 Aeronautics and Space 1 2014-01-01 2014-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

  3. 14 CFR 23.253 - High speed characteristics.

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... 14 Aeronautics and Space 1 2012-01-01 2012-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. Link to an amendment published at 76 FR 75755, December 2, 2011. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed...

  4. 14 CFR 23.253 - High speed characteristics.

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... 14 Aeronautics and Space 1 2013-01-01 2013-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

  5. Flow imaging by high speed transmission tomography.

    PubMed

    Johansen, Geir Anton; Hampel, Uwe; Hjertaker, Bjørn Tore

    2010-01-01

    Fourth generation medical X-ray scanners using a gantry with a rotating X-ray source and a fixed circular detector array as sensor head, are too slow for imaging of the process dynamics for instance in multiphase flows. To avoid inconsistent measurements and motion blurring, all measurements need to be carried out in a short time compared to the time constants of the process dynamics. Two different high speed tomographic imaging systems are presented here demonstrating that image rates of several thousand images per second is possible. Copyright 2009 Elsevier Ltd. All rights reserved.

  6. Characterization and Compensation of High Speed Digitizers

    SciTech Connect

    Fong, P; Teruya, A; Lowry, M

    2005-04-04

    Increasingly, ADC technology is being pressed into service for single single-shot instrumentation applications that were formerly served by vacuum-tube based oscilloscopes and streak cameras. ADC technology, while convenient, suffers significant performance impairments. Thus, in these demanding applications, a quantitative and accurate representation of these impairments is critical to an understanding of measurement accuracy. We have developed a phase-plane behavioral model, implemented it in SIMULINK and applied it to interleaved, high-speed ADCs (up to 4 gigasamples/sec). We have also developed and demonstrated techniques to effectively compensate for these impairments based upon the model.

  7. High Speed Solid State Circuit Breaker

    NASA Technical Reports Server (NTRS)

    Podlesak, Thomas F.

    1993-01-01

    The U.S. Army Research Laboratory, Fort Monmouth, NJ, has developed and is installing two 3.3 MW high speed solid state circuit breakers at the Army's Pulse Power Center. These circuit breakers will interrupt 4160V three phase power mains in no more than 300 microseconds, two orders of magnitude faster than conventional mechanical contact type circuit breakers. These circuit breakers utilize Gate Turnoff Thyristors (GTO's) and are currently utility type devices using air cooling in an air conditioned enclosure. Future refinements include liquid cooling, either water or two phase organic coolant, and more advanced semiconductors. Each of these refinements promises a more compact, more reliable unit.

  8. The Hubble Space Telescope high speed photometer

    NASA Technical Reports Server (NTRS)

    Vancitters, G. W., Jr.; Bless, R. C.; Dolan, J. F.; Elliot, J. L.; Robinson, E. L.; White, R. L.

    1988-01-01

    The Hubble Space Telescope will provide the opportunity to perform precise astronomical photometry above the disturbing effects of the atmosphere. The High Speed Photometer is designed to provide the observatory with a stable, precise photometer with wide dynamic range, broad wavelenth coverage, time resolution in the microsecond region, and polarimetric capability. Here, the scientific requirements for the instrument are examined, the unique design features of the photometer are explored, and the improvements to be expected over the performance of ground-based instruments are projected.

  9. Finite element methods for high speed flows

    NASA Technical Reports Server (NTRS)

    Loehner, R.; Morgan, K.; Peraire, J.; Zienkiewicz, O. C.

    1985-01-01

    An explicit finite element based solution procedure for solving the equations of compressible viscous high speed flow is presented. The method uses domain splitting to advance the solution with different timesteps on different portions of the mesh. For steady inviscid flows, adaptive mesh refinement procedures are successfully employed to enhance the definition of discontinuities. Preliminary ideas on the application of adaptive mesh refinement to the solution of problems involving steady viscous flow are presented. Sample timings are given for the performance of the finite element code on modern supercomputers.

  10. Continuous QKD and high speed data encryption

    NASA Astrophysics Data System (ADS)

    Zbinden, Hugo; Walenta, Nino; Guinnard, Olivier; Houlmann, Raphael; Wen, Charles Lim Ci; Korzh, Boris; Lunghi, Tommaso; Gisin, Nicolas; Burg, Andreas; Constantin, Jeremy; Legré, Matthieu; Trinkler, Patrick; Caselunghe, Dario; Kulesza, Natalia; Trolliet, Gregory; Vannel, Fabien; Junod, Pascal; Auberson, Olivier; Graf, Yoan; Curchod, Gilles; Habegger, Gilles; Messerli, Etienne; Portmann, Christopher; Henzen, Luca; Keller, Christoph; Pendl, Christian; Mühlberghuber, Michael; Roth, Christoph; Felber, Norbert; Gürkaynak, Frank; Schöni, Daniel; Muheim, Beat

    2013-10-01

    We present the results of a Swiss project dedicated to the development of high speed quantum key distribution and data encryption. The QKD engine features fully automated key exchange, hardware key distillation based on finite key security analysis, efficient authentication and wavelength division multiplexing of the quantum and the classical channel and one-time pas encryption. The encryption device allows authenticated symmetric key encryption (e.g AES) at rates of up to 100 Gb/s. A new quantum key can uploaded up to 1000 times second from the QKD engine.

  11. High-speed multispectral confocal biomedical imaging

    PubMed Central

    Carver, Gary E.; Locknar, Sarah A.; Morrison, William A.; Krishnan Ramanujan, V.; Farkas, Daniel L.

    2014-01-01

    Abstract. A new approach for generating high-speed multispectral confocal images has been developed. The central concept is that spectra can be acquired for each pixel in a confocal spatial scan by using a fast spectrometer based on optical fiber delay lines. This approach merges fast spectroscopy with standard spatial scanning to create datacubes in real time. The spectrometer is based on a serial array of reflecting spectral elements, delay lines between these elements, and a single element detector. The spatial, spectral, and temporal resolution of the instrument is described and illustrated by multispectral images of laser-induced autofluorescence in biological tissues. PMID:24658777

  12. Study of high-speed civil transports

    NASA Technical Reports Server (NTRS)

    1989-01-01

    A systems study to identify the economic potential for a high-speed commercial transport (HSCT) has considered technology, market characteristics, airport infrastructure, and environmental issues. Market forecasts indicate a need for HSCT service in the 2000/2010 time frame conditioned on economic viability and environmental acceptability. Design requirements focused on a 300 passenger, 3 class service, and 6500 nautical mile range based on the accelerated growth of the Pacific region. Compatibility with existing airports was an assumed requirement. Mach numbers between 2 and 25 were examined in conjunction with the appropriate propulsion systems, fuels, structural materials, and thermal management systems. Aircraft productivity was a key parameter with aircraft worth, in comparison to aircraft price, being the airline-oriented figure of merit. Aircraft screening led to determination that Mach 3.2 (TSJF) would have superior characteristics to Mach 5.0 (LNG) and the recommendation that the next generation high-speed commercial transport aircraft use a kerosene fuel. The sensitivity of aircraft performance and economics to environmental constraints (e.g., sonic boom, engine emissions, and airport/community noise) was identified together with key technologies. In all, current technology is not adequate to produce viable HSCTs for the world marketplace. Technology advancements must be accomplished to meet environmental requirements (these requirements are as yet undetermined for sonic boom and engine emissions). High priority is assigned to aircraft gross weight reduction which benefits both economics and environmental aspects. Specific technology requirements are identified and national economic benefits are projected.

  13. Applications for high-speed infrared imaging

    NASA Astrophysics Data System (ADS)

    Richards, Austin A.

    2005-03-01

    The phrase high-speed imaging is generally associated with short exposure times, fast frame rates or both. Supersonic projectiles, for example, are often impossible to see with the unaided eye, and require strobe photography to stop their apparent motion. It is often necessary to image high-speed objects in the infrared region of the spectrum, either to detect them or to measure their surface temperature. Conventional infrared cameras have time constants similar to the human eye, so they too, are often at a loss when it comes to photographing fast-moving hot targets. Other types of targets or scenes such as explosions change very rapidly with time. Visualizing those changes requires an extremely high frame rate combined with short exposure times in order to slow down a dynamic event so that it can be studied and quantified. Recent advances in infrared sensor technology and computing power have pushed the envelope of what is possible to achieve with commercial IR camera systems.

  14. TOPICAL REVIEW: Plasmas in high speed aerodynamics

    NASA Astrophysics Data System (ADS)

    Bletzinger, P.; Ganguly, B. N.; Van Wie, D.; Garscadden, A.

    2005-02-01

    A review is presented of the studies in the former Soviet Union and in the USA of the mutual interactions of plasmas and high speed flows and shocks. There are reports from as early as the 1980s of large changes in the standoff distance ahead of a blunt body in ballistic tunnels, significantly reduced drag and modifications of travelling shocks in bounded weakly ionized gases. Energy addition to the flow results in an increase in the local sound speed that leads to expected modifications of the flow and changes to the pressure distribution around a vehicle due to the decrease in local Mach number. The critical question was, did a plasma provide a significant energy multiplier for the system? There have been a large number of experimental studies on the influence of a weakly ionized plasma on relatively low Mach number shocks and inherently also on the influence of the shock on the plasma. This literature is reviewed and illustrated with representative examples. The convergence through more controlled experiments and improved modelling to a physics understanding of the effects being essentially due to heating is outlined. It is demonstrated that the heating in many cases is global; however, tailored experiments with positive columns, dielectric barrier discharges and focused microwave plasmas can produce very localized heating. The latter appears more attractive for energy efficiency in flow control. Tailored localized ionization and thermal effects are also of interest for high speed inlet shock control and for producing reliable ignition for short residence time combustors, and work in these areas is also reviewed.

  15. Nanopatterned Quantum Dot Lasers for High Speed, High Efficiency, Operation

    DTIC Science & Technology

    2015-04-27

    SECURITY CLASSIFICATION OF: Quantum dot (QD) active regions hold potential for realizing extremely high performance semiconductor diode lasers...2009 31-Dec-2014 Approved for Public Release; Distribution Unlimited Final Report: Nanopatterned Quantum Dot Lasers for High Speed, High Efficiency...Research Office P.O. Box 12211 Research Triangle Park, NC 27709-2211 quantum dots , nanopatterning, MOCVD, laser REPORT DOCUMENTATION PAGE 11

  16. Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Kawahito, Shoji; Itoh, Shinya

    2008-02-01

    A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.

  17. A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Yasutomi, Keita; Kagawa, Keiichiro; Kawahito, Shoji

    2014-03-01

    We have developed and evaluated the high responsivity and low dark leakage CMOS image sensor with the ring-gate shared-pixel design. A ring-gate shared-pixel design with a high fill factor makes it possible to achieve the low-light imaging. As eliminating the shallow trench isolation in the proposed pixel, the dark leakage current is significantly decreased because one of major dark leakage sources is removed. By sharing the in-pixel transistors such as a reset transistor, a select transistor, and a source follower amplifier, each pixel has a high fill-factor of 43 % and high sensitivity of 144.6 ke-/lx·sec. In addition, the effective number of transistors per pixel is 1.75. The proposed imager achieved the relatively low dark leakage current of about 104.5 e-/s (median at 60°C), corresponding to a dark current density Jdark_proposed of about 30 pA/cm2. In contrast, the conventional type test pixel has a large dark leakage current of 2450 e-/s (median at 60°C), corresponding to Jdark_conventional of about 700 pA/cm2. Both pixels have a same pixel size of 7.5×7.5 μm2 and are fabricated in same process.

  18. ACTS High-Speed VSAT Demonstrated

    NASA Technical Reports Server (NTRS)

    Tran, Quang K.

    1999-01-01

    The Advanced Communication Technology Satellite (ACTS) developed by NASA has demonstrated the breakthrough technologies of Ka-band transmission, spot-beam antennas, and onboard processing. These technologies have enabled the development of very small and ultrasmall aperture terminals (VSAT s and USAT's), which have capabilities greater than have been possible with conventional satellite technologies. The ACTS High Speed VSAT (HS VSAT) is an effort at the NASA Glenn Research Center at Lewis Field to experimentally demonstrate the maximum user throughput data rate that can be achieved using the technologies developed and implemented on ACTS. This was done by operating the system uplinks as frequency division multiple access (FDMA), essentially assigning all available time division multiple access (TDMA) time slots to a single user on each of two uplink frequencies. Preliminary results show that, using a 1.2-m antenna in this mode, the High Speed VSAT can achieve between 22 and 24 Mbps of the 27.5 Mbps burst rate, for a throughput efficiency of 80 to 88 percent.

  19. High-speed optogenetic circuit mapping

    NASA Astrophysics Data System (ADS)

    Augustine, George J.; Chen, Susu; Gill, Harin; Katarya, Malvika; Kim, Jinsook; Kudolo, John; Lee, Li M.; Lee, Hyunjeong; Lo, Shun Qiang; Nakajima, Ryuichi; Park, Min-Yoon; Tan, Gregory; Tang, Yanxia; Teo, Peggy; Tsuda, Sachiko; Wen, Lei; Yoon, Su-In

    2013-03-01

    Scanning small spots of laser light allows mapping of synaptic circuits in brain slices from transgenic mice expressing channelrhodopsin-2 (ChR2). These light spots photostimulate presynaptic neurons expressing ChR2, while postsynaptic responses can be monitored in neurons that do not express ChR2. Correlating the location of the light spot with the amplitude of the postsynaptic response elicited at that location yields maps of the spatial organization of the synaptic circuits. This approach yields maps within minutes, which is several orders of magnitude faster than can be achieved with conventional paired electrophysiological methods. We have applied this high-speed technique to map local circuits in many brain regions. In cerebral cortex, we observed that maps of excitatory inputs to pyramidal cells were qualitatively different from those measured for interneurons within the same layers of the cortex. In cerebellum, we have used this approach to quantify the convergence of molecular layer interneurons on to Purkinje cells. The number of converging interneurons is reduced by treatment with gap junction blockers, indicating that electrical synapses between interneurons contribute substantially to the spatial convergence. Remarkably, gap junction blockers affect convergence in sagittal cerebellar slices but not in coronal slices, indicating sagittal polarization of electrical coupling between interneurons. By measuring limb movement or other forms of behavioral output, this approach also can be used in vivo to map brain circuits non-invasively. In summary, ChR2-mediated high-speed mapping promises to revolutionize our understanding of brain circuitry.

  20. Driver speed selection on high-speed two-lane highways: Comparing speed profiles between uniform and differential speed limits.

    PubMed

    Russo, Brendan J; Savolainen, Peter T; Gates, Timothy J; Kay, Jonathan J; Frazier, Sterling

    2017-07-04

    Although a considerable amount of prior research has investigated the impacts of speed limits on traffic safety and operations, much of this research, and nearly all of the research related to differential speed limits, has been specific to limited access freeways. The unique safety and operational issues on highways without access control create difficulty relating the conclusions from prior freeway-related speed limit research to 2-lane highways, particularly research on differential limits due to passing limitations and subsequent queuing. Therefore, the objective of this study was to assess differences in driver speed selection with respect to the posted speed limit on rural 2-lane highways, with a particular emphasis on the differences between uniform and differential speed limits. Data were collected from nearly 59,000 vehicles across 320 sites in Montana and 4 neighboring states. Differences in mean speeds, 85th percentile speeds, and the standard deviation in speeds for free-flowing vehicles were examined across these sites using ordinary least squares regression models. Ultimately, the results of the analysis show that the mean speed, 85th percentile speed, and variability in travel speeds for free-flowing vehicles on 2-lane highways are generally lower at locations with uniform 65 mph speed limits, compared to locations with differential limits of 70 mph for cars and 60 mph for trucks. In addition to posted speed limits, several site characteristics were shown to influence speed selection including shoulder widths, frequency of horizontal curves, percentage of the segment that included no passing zones, and hourly volumes. Differences in vehicle speed characteristics were also observed between states, indicating that speed selection may also be influenced by local factors, such as driver population or enforcement.

  1. High mobility CMOS technologies using III-V/Ge channels on Si platform

    NASA Astrophysics Data System (ADS)

    Takagi, S.; Kim, S.-H.; Yokoyama, M.; Zhang, R.; Taoka, N.; Urabe, Y.; Yasuda, T.; Yamada, H.; Ichikawa, O.; Fukuhara, N.; Hata, M.; Takenaka, M.

    2013-10-01

    MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to Ge and III-V channels. In this paper, possible solutions for realizing III-V/Ge MOSFETs on the Si platform are presented. The high quality III-V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation is constructed on a basis of atomic layer deposition (ALD) Al2O3 gate insulators for both InGaAs and Ge MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

  2. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    PubMed Central

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-01-01

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

  3. High-speed spatial scanning pyrometer

    NASA Technical Reports Server (NTRS)

    Cezairliyan, A.; Chang, R. F.; Foley, G. M.; Miller, A. P.

    1993-01-01

    A high-speed spatial scanning pyrometer has been designed and developed to measure spectral radiance temperatures at multiple target points along the length of a rapidly heating/cooling specimen in dynamic thermophysical experiments at high temperatures (above about 1800 K). The design, which is based on a self-scanning linear silicon array containing 1024 elements, enables the pyrometer to measure spectral radiance temperatures (nominally at 650 nm) at 1024 equally spaced points along a 25-mm target length. The elements of the array are sampled consecutively every 1 microsec, thereby permitting one cycle of measurements to be completed in approximately 1 msec. Procedures for calibration and temperature measurement as well as the characteristics and performance of the pyrometer are described. The details of sources and estimated magnitudes of possible errors are given. An example of measurements of radiance temperatures along the length of a tungsten rod, during its cooling following rapid resistive pulse heating, is presented.

  4. Very high-speed digital holography

    NASA Astrophysics Data System (ADS)

    Pérez López, Carlos; Mendoza Santoyo, Fernando; Rodríguez Vera, Ramón; Moreno, David; Barrientos, Bernardino

    2006-08-01

    It is reported for the first time the use of a high speed camera in digital holography with an out of plane sensitivity. The camera takes the image plane holograms of a cw laser illuminated rectangular framed polyester material at a rate of 5000 per second, that is a spacing of 200 microseconds between holograms, and 512 by 500 pixels at 10 bit resolution. The freely standing object has a random movement due to non controlled environmental air currents. As is usual with this technique each digital hologram is Fourier processed in order to obtain upon comparison with a consecutive digital hologram the phase map of the displacement. High quality results showing the amplitude and direction of the random movement are presented.

  5. Interpolation circuit with high resolution and high response speed

    NASA Astrophysics Data System (ADS)

    Piao, Weiying; Yuan, Yibao; Xu, Lianhu; Zhang, Hao

    2009-05-01

    An interpolation circuit based upon the looking-up table by hardware is presented. Output data of two A/D convertors are connected to ROM's address bus. The memory space of ROM is divided. When the address bus is activated by A/D conversion's output data, the ROM's output data is interpolation data. This circuit has high response speed, and it is easy to obtain high interpolation multiple. The same kind of hardware circuit can achieve different interpolation multiple by modifying ROM's data. It is very convenient and flexible. The principle of direction judgment and counting is analyzed; the implementation speed and maximal interpolation multiple are discussed in this paper. Finally through experiment, make sure this circuit not only has the characteristic of high response speed and high interpolation multiple, but also avoids the counting error of micro-computer interpolation.

  6. Visualization of high speed phenomena using high-speed infrared camera

    NASA Astrophysics Data System (ADS)

    Yaoita, T.; Marcotte, F.

    2017-02-01

    The standard infrared camera has taken certain integration time with the photography per once, it was unsuitable for high-speed photography. By the infrared camera which can buffer photography data efficiently continually, high-speed photography of 2,000fps is enabled in 320X240 pixels and 11,000fps in128X100 pixels by windowing mode. The heat generation of specimen phenomenon is used for the monitoring of the start point of the destruction and the thermometry of combustion gases.

  7. A method for electrophysiological characterization of hamster retinal ganglion cells using a high-density CMOS microelectrode array

    PubMed Central

    Jones, Ian L.; Russell, Thomas L.; Farrow, Karl; Fiscella, Michele; Franke, Felix; Müller, Jan; Jäckel, David; Hierlemann, Andreas

    2015-01-01

    Knowledge of neuronal cell types in the mammalian retina is important for the understanding of human retinal disease and the advancement of sight-restoring technology, such as retinal prosthetic devices. A somewhat less utilized animal model for retinal research is the hamster, which has a visual system that is characterized by an area centralis and a wide visual field with a broad binocular component. The hamster retina is optimally suited for recording on the microelectrode array (MEA), because it intrinsically lies flat on the MEA surface and yields robust, large-amplitude signals. However, information in the literature about hamster retinal ganglion cell functional types is scarce. The goal of our work is to develop a method featuring a high-density (HD) complementary metal-oxide-semiconductor (CMOS) MEA technology along with a sequence of standardized visual stimuli in order to categorize ganglion cells in isolated Syrian Hamster (Mesocricetus auratus) retina. Since the HD-MEA is capable of recording at a higher spatial resolution than most MEA systems (17.5 μm electrode pitch), we were able to record from a large proportion of RGCs within a selected region. Secondly, we chose our stimuli so that they could be run during the experiment without intervention or computation steps. The visual stimulus set was designed to activate the receptive fields of most ganglion cells in parallel and to incorporate various visual features to which different cell types respond uniquely. Based on the ganglion cell responses, basic cell properties were determined: direction selectivity, speed tuning, width tuning, transience, and latency. These properties were clustered to identify ganglion cell types in the hamster retina. Ultimately, we recorded up to a cell density of 2780 cells/mm2 at 2 mm (42°) from the optic nerve head. Using five parameters extracted from the responses to visual stimuli, we obtained seven ganglion cell types. PMID:26528115

  8. High-speed ACR/NEMA interface

    NASA Astrophysics Data System (ADS)

    Reijns, Gerard L.; Santilli, D.; Schellingerhout, G.; Jochem, A. J.; Ottes, Fenno P.; van Aken, I. W.

    1990-08-01

    The design and implementation of a standard high speed ACR-NEMA communications interface is described. The upper layers e.g. the Presentation layer, Session layer and part of the Transport/Network layer have been implemented in software. In order to reach the speed requirement of 8M byte/sec. the lower layers e.g. part of the Transport/Network layer and Data Link layer have been implemented in hardware. We have developed and built an interface for an IBM personal computer P5/2 model 50, working under the operating system OS/2. The PS/2, model 50 has been equipped with a fast micro-channel bus, which enables a large throughput. The operating systern OS/2 has a multitasking capability, which enables concurrent programming. In order to minimize the delays, we used this multitasking facility to create a number of parallel operating "threads". The Transport/Network layer functions have been implemented using a receive thread, two send threads and a device driver with three hardware registers. The time to transfer a packet by DMA, to initiate the DMA logic and to execute the required Kernal functions have each been measured and figures are shown. The Data Link layer provides for storage of two packets in two separate random access memories (RAM's). These two RAM's enable a pipelined operation, which minimizes the delay in the Data Link layer.

  9. High Speed Fibre Optic Backbone LAN

    NASA Astrophysics Data System (ADS)

    Tanimoto, Masaaki; Hara, Shingo; Kajita, Yuji; Kashu, Fumitoshi; Ikeuchi, Masaru; Hagihara, Satoshi; Tsuzuki, Shinji

    1987-09-01

    Our firm has developed the SUMINET-4100 series, a fibre optic local area network (LAN), to serve the communications system trunk line needs for facilities, such as steel refineries, automobile plants and university campuses, that require large transmission capacity, and for the backbone networks used in intelligent building systems. The SUMINET-4100 series is already in service in various fields of application. Of the networks available in this series, the SUMINET-4150 has a trunk line speed of 128 Mbps and the multiplexer used for time division multiplexing (TDM) was enabled by designing an ECL-TTL gate array (3000 gates) based custom LSI. The synchronous, full-duplex V.24 and V.3.5 interfaces (SUMINET-2100) are provided for use with general purpose lines. And the IBM token ring network, the SUMINET-3200, designed for heterogeneous PCs and the Ethernet can all be connected to sub loops. Further, the IBM 3270 TCA and 5080 CADAM can be connected in the local mode. Interfaces are also provided for the NTT high-speed digital service, the digital PBX systems, and the Video CODEC system. The built-in loop monitor (LM) and network supervisory processor (NSP) provide management of loop utilization and send loop status signals to the host CPU's network configuration and control facility (NCCF). These built-in functions allow both the computer system and LAN to be managed from a single source at the host. This paper outlines features of the SUMINET-4150 and provides an example of its installation.

  10. High-speed cameras at Los Alamos

    NASA Astrophysics Data System (ADS)

    Brixner, Berlyn

    1997-05-01

    In 1943, there was no camera with the microsecond resolution needed for research in Atomic Bomb development. We had the Mitchell camera (100 fps), the Fastax (10 000), the Marley (100 000), the drum streak (moving slit image) 10-5 s resolution, and electro-optical shutters for 10-6 s. Julian Mack invented a rotating-mirror camera for 10-7 s, which was in use by 1944. Small rotating mirror changes secured a resolution of 10-8 s. Photography of oscilloscope traces soon recorded 10-6 resolution, which was later improved to 10-8 s. Mack also invented two time resolving spectrographs for studying the radiation of the first atomic explosion. Much later, he made a large aperture spectrograph for shock wave spectra. An image dissecting drum camera running at 107 frames per second (fps) was used for studying high velocity jets. Brixner invented a simple streak camera which gave 10-8 s resolution. Using a moving film camera, an interferometer pressure gauge was developed for measuring shock-front pressures up to 100 000 psi. An existing Bowen 76-lens frame camera was speeded up by our turbine driven mirror to make 1 500 000 fps. Several streak cameras were made with writing arms from 4 1/2 to 40 in. and apertures from f/2.5 to f/20. We made framing cameras with top speeds of 50 000, 1 000 000, 3 500 000, and 14 000 000 fps.

  11. High-Speed RaPToRS

    NASA Astrophysics Data System (ADS)

    Henchen, Robert; Esham, Benjamin; Becker, William; Pogozelski, Edward; Padalino, Stephen; Sangster, Thomas; Glebov, Vladimir

    2008-11-01

    The High-Speed Rapid Pneumatic Transport of Radioactive Samples (HS-RaPToRS) system, designed to quickly and safely move radioactive materials, was assembled and tested at the Mercury facility of the Naval Research Laboratory (NRL) in Washington D.C. A sample, which is placed inside a four-inch-diameter carrier, is activated before being transported through a PVC tube via airflow. The carrier travels from the reaction chamber to the end station where it pneumatically brakes prior to the gate. A magnetic latch releases the gate when the carrier arrives and comes to rest. The airflow, optical carrier-monitoring devices, and end gate are controlled manually or automatically with LabView software. The installation and testing of the RaPToRS system at NRL was successfully completed with transport times of less than 3 seconds. The speed of the carrier averaged 16 m/s. Prospective facilities for similar systems include the Laboratory for Laser Energetics and the National Ignition Facility.

  12. Using a High-Speed Camera to Measure the Speed of Sound

    ERIC Educational Resources Information Center

    Hack, William Nathan; Baird, William H.

    2012-01-01

    The speed of sound is a physical property that can be measured easily in the lab. However, finding an inexpensive and intuitive way for students to determine this speed has been more involved. The introduction of affordable consumer-grade high-speed cameras (such as the Exilim EX-FC100) makes conceptually simple experiments feasible. Since the…

  13. Using a High-Speed Camera to Measure the Speed of Sound

    ERIC Educational Resources Information Center

    Hack, William Nathan; Baird, William H.

    2012-01-01

    The speed of sound is a physical property that can be measured easily in the lab. However, finding an inexpensive and intuitive way for students to determine this speed has been more involved. The introduction of affordable consumer-grade high-speed cameras (such as the Exilim EX-FC100) makes conceptually simple experiments feasible. Since the…

  14. High speed operation of permanent magnet machines

    NASA Astrophysics Data System (ADS)

    El-Refaie, Ayman M.

    This work proposes methods to extend the high-speed operating capabilities of both the interior PM (IPM) and surface PM (SPM) machines. For interior PM machines, this research has developed and presented the first thorough analysis of how a new bi-state magnetic material can be usefully applied to the design of IPM machines. Key elements of this contribution include identifying how the unique properties of the bi-state magnetic material can be applied most effectively in the rotor design of an IPM machine by "unmagnetizing" the magnet cavity center posts rather than the outer bridges. The importance of elevated rotor speed in making the best use of the bi-state magnetic material while recognizing its limitations has been identified. For surface PM machines, this research has provided, for the first time, a clear explanation of how fractional-slot concentrated windings can be applied to SPM machines in order to achieve the necessary conditions for optimal flux weakening. A closed-form analytical procedure for analyzing SPM machines designed with concentrated windings has been developed. Guidelines for designing SPM machines using concentrated windings in order to achieve optimum flux weakening are provided. Analytical and numerical finite element analysis (FEA) results have provided promising evidence of the scalability of the concentrated winding technique with respect to the number of poles, machine aspect ratio, and output power rating. Useful comparisons between the predicted performance characteristics of SPM machines equipped with concentrated windings and both SPM and IPM machines designed with distributed windings are included. Analytical techniques have been used to evaluate the impact of the high pole number on various converter performance metrics. Both analytical techniques and FEA have been used for evaluating the eddy-current losses in the surface magnets due to the stator winding subharmonics. Techniques for reducing these losses have been

  15. Trapping of hydrogen in hafnium-based high kappa dielectric thin films for advanced CMOS applications

    NASA Astrophysics Data System (ADS)

    Ukirde, Vaishali

    In recent years, advanced high kappa gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high kappa dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.

  16. A CMOS high resolution, process/temperature variation tolerant RSSI for WIA-PA transceiver

    NASA Astrophysics Data System (ADS)

    Tao, Yang; Yu, Jiang; Jie, Li; Jiangfei, Guo; Hua, Chen; Jingyu, Han; Guiliang, Guo; Yuepeng, Yan

    2015-08-01

    This paper presents a high resolution, process/temperature variation tolerant received signal strength indicator (RSSI) for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The active area of the RSSI is 0.24 mm2. Measurement results show that the proposed RSSI has a dynamic range more than 70 dB and the linearity error is within ±0.5 dB for an input power from -70 to 0 dBm (dBm to 50 Ω), the corresponding output voltage is from 0.81 to 1.657 V and the RSSI slope is 12.1 mV/dB while consuming all of 2 mA from a 1.8 V power supply. Furthermore, by the help of the integrated compensation circuit, the proposed RSSI shows the temperature error within ±1.5 dB from -40 to 85 °C, and process variation error within ±0.25 dB, which exhibits good temperature-independence and excellent robustness against process variation characteristics. Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

  17. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    PubMed Central

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  18. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-07-22

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

  19. Ultra-fast MTF Test for High-Volume production of CMOS Imaging Cameras

    NASA Astrophysics Data System (ADS)

    Dahl, Michael; Heinisch, Josef; Krey, Stefan; Bäumer, Stefan M.; Lurquin, Johan; Chen, Linghua

    2004-01-01

    During the last years compact CMOS imaging cameras have grown into high volume applications such as mobile phones, PDAs, etc. In order to insure a constant quality of the lenses of the cameras, MTF is used as a figure of merit. MTF is a polychromatic, objective test for imaging lens quality including diffraction effects, system aberrations and surface defects as well. The draw back of MTF testing is that the proper measurement of the lens MTF is quite cumbersome and time consuming. In the current investigation we designed, produced and tested a new semi-automated MTF set up that is able to measure the polychromatic lens system MTF at 6 or more field points at best focus in less than 6 seconds. The computed MTF is a real diffraction MTF derived from a line spread function (not merely a contrast measurement). This enables lens manufacturers to perform 100% MTF testing even in high volume applications. Using statistic tools to analyze the data also gives possibility to find even small systematic errors in the production like shift or tilt of lenses and lens elements. Using this as feedback the quality of the product can be increased. The system is very compact and can be put easily in an assembly line. Besides design and test of the MTF set up correlation experiments between several testers have been carried out. A correlation of better than 6% points for all tested systems at all fields has been achieved.

  20. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    NASA Astrophysics Data System (ADS)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  1. A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

    PubMed

    Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

    2007-06-01

    A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode

  2. High-speed VLSI concentrators for terabit intelligent optical backplanes

    NASA Astrophysics Data System (ADS)

    Supmonchai, Boonchuay; Szymanski, Ted H.

    1998-05-01

    Self-routing `concentrators' are fundamental building blocks of optical switching systems. An N-to-M concentrator can process and extract data packets from N optical channels and forward the packets to M electrical channels, where typically N M. Terabit Optical Backplanes which exploit free-space optical data links, with bandwidths approaching 1 - 10 Terabits per second will require extremely fast self- routing concentrators which can make routing decisions within a few nanoseconds. In this paper, a VLSI analysis of a new circuit called the `Daisy Chain' concentrator is presented. This concentrator has a regular topology suitable for very efficient VLSI layout, which leads to very high clock rates. The analyses are performed using 0.8 micrometers standard cell CMOS technology with the Synopsys CAD tool. The results shows that the proposed concentrator uses substantially less VLSI area from 20 - 50% less in the control logic and up to 150% less on the switching logic than the previous best known concentrator circuit. It also performs significantly faster, ranging from 20 - 40% faster in the control logic and 150 - 300% faster in the switching logic. Using 0.8 micrometers CMOS technology, the proposed concentrator can be used in smart pixel arrays for optical backplanes with clock rates in the range of 500 Mhz. Using faster CMOS or ECL logic, the concentrator can support clock rates in the several Gigahertz range.

  3. Neutron and high speed photogrammetric arcjet diagnosis

    NASA Technical Reports Server (NTRS)

    Stewart, P. A. E.; Rogers, J. D.; Fowler, P. H.; Deininger, W. D.; Taylor, A. D.

    1989-01-01

    Two methods for real time internal diagnostics of arcjet engines are described. One method uses cold, thermal, or epithermal neutrons. Cold neutrons are used to detect the presence and location of hydrogenous propellants. Thermal neutrons are used to delineate the edge contours of anode and cathode surfaces and to measure stress/strain. Epithermal neutrons are used to measure temperatures on arcjet surfaces, bulk material temperatures, and point temperatures in bulk materials. It is found that this method, with an exposure time of 10 min, produces at temperature accuracy for W or Re of + or - 2.5 C. The other method uses visible-light high-speed photogrammetry to obtain images of the transient behavior of the arc during start-up and to relate this behavior to electrial supply characteristics such as voltage, current, and ripple.

  4. High Speed Photography In The United Kingdom

    NASA Astrophysics Data System (ADS)

    Lunn, George H.

    1989-06-01

    At the 13th Congress in Tokyo, I presented a paper with this title in which some early history was mentioned followed by a more detailed study of the activities of the main research groups in Britain from the period between 1950 and 1978. On this occasion, some early topics will be mentioned. The period since 1978 has seen quite a few changes in that research is now more in the hands of commercial groups as opposed to the previous governmental laboratories. It is true that the pricipal camera systems have reached towards their physical limits. However other new techniques are still expanding, for example, Lasers, Holography and Videography. The new systems are principally in the hands of major or specialist companies with the offical and industrial research groups using their products. The Association for High Speed Photography continues to encourage both researchers and users by providing oportunities for users, suppliers and manufacturers to meet and discuss.

  5. Merging of high speed argon plasma jets

    SciTech Connect

    Case, A.; Messer, S.; Brockington, S.; Wu, L.; Witherspoon, F. D.; Elton, R.

    2013-01-15

    Formation of an imploding plasma liner for the plasma liner experiment (PLX) requires individual plasma jets to merge into a quasi-spherical shell of plasma converging on the origin. Understanding dynamics of the merging process requires knowledge of the plasma phenomena involved. We present results from the study of the merging of three plasma jets in three dimensional geometry. The experiments were performed using HyperV Technologies Corp. 1 cm Minirailguns with a preionized argon plasma armature. The vacuum chamber partially reproduces the port geometry of the PLX chamber. Diagnostics include fast imaging, spectroscopy, interferometry, fast pressure probes, B-dot probes, and high speed spatially resolved photodiodes, permitting measurements of plasma density, temperature, velocity, stagnation pressure, magnetic field, and density gradients. These experimental results are compared with simulation results from the LSP 3D hybrid PIC code.

  6. Design of a high speed business transport

    NASA Technical Reports Server (NTRS)

    1990-01-01

    The design of a High Speed Business Transport (HSBT) was considered by the Aeronautical Design Class during the academic year 1989 to 1990. The project was chosen to offer an opportunity to develop user friendliness for some computer codes such as WAVE DRAG, supplied by NASA/Langley, and to experiment with several design lessons developed by Dr. John McMasters and his colleages at Boeing. Central to these design lessons was an appeal to marketing and feasibility considerations. There was an emphasis upon simplified analytical techniques to study trades and to stimulate creative thinking before committing to extensive analytical activity. Two designs stood out among all the rest because of the depth of thought and consideration of alternatives. One design, the Aurora, used a fixed wing design to satisfy the design mission: the Viero used a swept wing configuration to overcome problems related to supersonic flight. A summary of each of these two designs is given.

  7. High speed civil transport aerodynamic optimization

    NASA Technical Reports Server (NTRS)

    Ryan, James S.

    1994-01-01

    This is a report of work in support of the Computational Aerosciences (CAS) element of the Federal HPCC program. Specifically, CFD and aerodynamic optimization are being performed on parallel computers. The long-range goal of this work is to facilitate teraflops-rate multidisciplinary optimization of aerospace vehicles. This year's work is targeted for application to the High Speed Civil Transport (HSCT), one of four CAS grand challenges identified in the HPCC FY 1995 Blue Book. This vehicle is to be a passenger aircraft, with the promise of cutting overseas flight time by more than half. To meet fuel economy, operational costs, environmental impact, noise production, and range requirements, improved design tools are required, and these tools must eventually integrate optimization, external aerodynamics, propulsion, structures, heat transfer, controls, and perhaps other disciplines. The fundamental goal of this project is to contribute to improved design tools for U.S. industry, and thus to the nation's economic competitiveness.

  8. Technology needs for high-speed rotorcraft

    NASA Technical Reports Server (NTRS)

    Rutherford, John; Orourke, Matthew; Martin, Christopher; Lovenguth, Marc; Mitchell, Clark

    1991-01-01

    A study to determine the technology development required for high-speed rotorcraft development was conducted. The study begins with an initial assessment of six concepts capable of flight at, or greater than 450 knots with helicopter-like hover efficiency (disk loading less than 50 pfs). These concepts were sized and evaluated based on measures of effectiveness and operational considerations. Additionally, an initial assessment of the impact of technology advances on the vehicles attributes was made. From these initial concepts a tilt wing and rotor/wing concepts were selected for further evaluation. A more detailed examination of conversion and technology trade studies were conducted on these two vehicles, each sized for a different mission.

  9. High-speed electrical motor evaluation

    SciTech Connect

    Not Available

    1989-02-03

    Under this task, MTI conducted a general review of state-of-the-art high-speed motors. The purpose of this review was to assess the operating parameters, limitations and performance of existing motor designs, and to establish commercial sources for a motor compatible with the requirements of the Brayton-cycle system. After the motor requirements were established, a list of motor types, manufacturers and designs capable of achieving the requisite performance was compiled. This list was based on an in-house evaluation of designs. Following the establishment of these options, a technical evaluation of the designs selected was conducted. In parallel with their evaluations, MTI focused on the establishment of commercial sources.

  10. HIGH SPEED KERR CELL FRAMING CAMERA

    DOEpatents

    Goss, W.C.; Gilley, L.F.

    1964-01-01

    The present invention relates to a high speed camera utilizing a Kerr cell shutter and a novel optical delay system having no moving parts. The camera can selectively photograph at least 6 frames within 9 x 10/sup -8/ seconds during any such time interval of an occurring event. The invention utilizes particularly an optical system which views and transmits 6 images of an event to a multi-channeled optical delay relay system. The delay relay system has optical paths of successively increased length in whole multiples of the first channel optical path length, into which optical paths the 6 images are transmitted. The successively delayed images are accepted from the exit of the delay relay system by an optical image focusing means, which in turn directs the images into a Kerr cell shutter disposed to intercept the image paths. A camera is disposed to simultaneously view and record the 6 images during a single exposure of the Kerr cell shutter. (AEC)

  11. High-speed digital wireless battlefield network

    NASA Astrophysics Data System (ADS)

    Dao, Son K.; Zhang, Yongguang; Shek, Eddie C.; van Buer, Darrel

    1999-07-01

    In the past two years, the Digital Wireless Battlefield Network consortium that consists of HRL Laboratories, Hughes Network Systems, Raytheon, and Stanford University has participated in the DARPA TRP program to leverage the efforts in the development of commercial digital wireless products for use in the 21st century battlefield. The consortium has developed an infrastructure and application testbed to support the digitized battlefield. The consortium has implemented and demonstrated this network system. Each member is currently utilizing many of the technology developed in this program in commercial products and offerings. These new communication hardware/software and the demonstrated networking features will benefit military systems and will be applicable to the commercial communication marketplace for high speed voice/data multimedia distribution services.

  12. Very high speed cw digital holographic interferometry

    NASA Astrophysics Data System (ADS)

    Pérez-López, Carlos; de La Torre-Ibarra, Manuel H.; Mendoza Santoyo, Fernando

    2006-10-01

    It is reported for the first time the use of a very high speed camera in digital holographic interferometry with an out of plane sensitivity setup. The image plane holograms of a spherical latex balloon illuminated by a cw laser were acquired at a rate of 4000 frames per second, representing a time spacing between holograms of 250 microseconds, for 512 × 512 pixels at 8 bits resolution. Two types of tests were accomplished for a proof of principle of the technique, one with no constrains on the object which meant random movements due to non controlled environmental air currents, and the other with specific controlled conditions on the object. Results presented correspond to a random sample of sequential digital holograms, chosen from a 1 second exposure, individually Fourier processed in order to perform the usual comparison by subtraction between consecutive pairs thus obtaining the phase map of the object out of plane displacement, shown as a movie.

  13. Photodetector having high speed and sensitivity

    DOEpatents

    Morse, Jeffrey D.; Mariella, Jr., Raymond P.

    1991-01-01

    The present invention provides a photodetector having an advantageous combination of sensitivity and speed; it has a high sensitivity while retaining high speed. In a preferred embodiment, visible light is detected, but in some embodiments, x-rays can be detected, and in other embodiments infrared can be detected. The present invention comprises a photodetector having an active layer, and a recombination layer. The active layer has a surface exposed to light to be detected, and comprises a semiconductor, having a bandgap graded so that carriers formed due to interaction of the active layer with the incident radiation tend to be swept away from the exposed surface. The graded semiconductor material in the active layer preferably comprises Al.sub.1-x Ga.sub.x As. An additional sub-layer of graded In.sub.1-y Ga.sub.y As may be included between the Al.sub.1-x Ga.sub.x As layer and the recombination layer. The recombination layer comprises a semiconductor material having a short recombination time such as a defective GaAs layer grown in a low temperature process. The recombination layer is positioned adjacent to the active layer so that carriers from the active layer tend to be swept into the recombination layer. In an embodiment, the photodetector may comprise one or more additional layers stacked below the active and recombination layers. These additional layers may include another active layer and another recombination layer to absorb radiation not absorbed while passing through the first layers. A photodetector having a stacked configuration may have enhanced sensitivity and responsiveness at selected wavelengths such as infrared.

  14. Computation of high-speed reacting flows

    NASA Astrophysics Data System (ADS)

    Clutter, James Keith

    A computational study has been conducted for high-speed reacting flows relevant to munition problems, including shock-induced combustion and gun muzzle blast. The theoretical model considers inviscid and viscous flows, multi-species, finite rate chemical reaction schemes, and turbulence. Both the physical and numerical aspects are investigated to determine their impact on simulation accuracy. A range of hydrogen and oxygen reaction mechanisms are evaluated for the shock-induced combustion flow scenario. Characteristics of the mechanisms such as the induction time, heat release rate, and second explosion limit are found to impact the accuracy of the computation. On the numerical side, reaction source term treatments, including logarithmic weighting and scaling modifications, are investigated to determine their effectiveness in addressing numerical errors caused by disparate length scales between chemical reactions and fluid dynamics. It is demonstrated that these techniques can enhance solution accuracy. Computations of shock-induced combustion have also been performed using a κ-ɛ model to account for the turbulent transport of species and heat. An algebraic model of the temperature fluctuations has been used to estimate the impact of the turbulent effect on the chemical reaction source terms. The turbulence effects when represented with the current models are found to be minimal in the shock-induced combustion flow investigated in the present work. For the gun system simulations, computations for both a large caliber howitzer and small caliber firearms are carried out. A reduced kinetic scheme and an algebraic turbulence model are employed. The present approach, which accounts for the chemical reaction aspects of the gun muzzle blast problem, is found to improve the prediction of peak overpressures and can capture the effects produced by small caliber firearm sound suppressors. The present study has established the numerical and physical requirements for

  15. Photogrammetric Techniques Using High-Speed Cineradiography

    NASA Astrophysics Data System (ADS)

    Nusholtz, Guy S.; Bender, Max; Suggitt, Bryan R.; Kaiker, Patricia S.; Muscott, Gail J.

    1986-01-01

    A high-speed 16-mm cineradiographic system previously developed at the University of Michigan Transportation Research Institute for use in biomechanics research has been undergoing a continuous upgrading in capability. In addition to changes in the structural aspect of the cineradiography, improvements have been made in the procedures used to obtain better image quality as well as methods for interpretation of the digitized results. The current improvements in the system include: 1) filtering the X-ray source before penetration of the subject to increase image contrast as well as to protect the image tube; 2) pre-processing of the film to increase its effective speed; 3) development of a neutral density radio-contrast media for outlining anatomical structure without using the vascular system; and 4) development of procedures for obtaining analytical information about motion of non-rigid anatomical structures from digitized film. This system now consists of either a 35-mm Photosonics 4B, a 16-mm Photosonics 1B, or a 16-mm Milliken which views a 50-mm (2-inch) diameter output of a P-11 phosphor of a high gain, four-stage magnetically focused image intensifier tube, gated on and off synchronously with the motion picture camera shutter. A lens optically couples the input photocathode of the image tube to an X-ray fluorescent (rare earth) screen image produced by a smoothed DC X-ray generator of a conventional type. The system is capable of looking at a large spectrum of anatomical structures under a wide range of dynamic loading conditions.

  16. High-speed shutter for mirror cameras

    NASA Astrophysics Data System (ADS)

    Trofimenko, Vladimir V.; Klimashin, V. P.; Drozhbin, Yu. A.

    1999-06-01

    High-speed mirror cameras are mainly used for investigations of quick processes in a wide spectral range of radiation including ultraviolet and infrared regions (from 0.2 to 11 micrometer). High-speed shutters for these cameras must be non-selective and when opened must transmit the whole radiation without refraction, absorption and scattering. Electromechanical, electrodynamic and induction-dynamic shutters possess such properties because their optical channels contain no medium. Electromechanical shutters are devices where the displacement of the working blind which opens or closes an aperture is produced by a spring. Such shutters are relatively slow and are capable of closing an aperture of 50 mm in diameter in 10 - 15 ms. Electrodynamic and induction-dynamic shutters are devices where displacement of a blind is produced by the electromagnetic interaction between circuits with electric currents. In induction-dynamic shutter the secondary circuit is current-conducting blind itself in which a short-circuited loop forms. The latter is more quick because of the lower mass of its moveable secondary circuit. For this reason induction-dynamic shutters with a flat primary circuit coil and a tightly fitted to it load- bearing aluminum plate have been investigated. The blind which opens or closes an aperture was attached to this plate. The dependencies of cut-off time on the form, size and the number of turns of the primary circuit coil, on size, type of material, thickness and weight of the load-bearing plate and the blind, as well as on capacitance in the discharge circuit and the capacitor voltage have been investigated. The influence of the environmental atmosphere on the cut-off time was also studied. For this purpose the shutter was placed into the chamber where vacuum up to 10- atm could be produced. As a result the values of the above mentioned parameters have been optimized and the designs of the shutters which are shown have been developed.

  17. High Speed/ Low Effluent Process for Ethanol

    SciTech Connect

    M. Clark Dale

    2006-10-30

    n this project, BPI demonstrated a new ethanol fermentation technology, termed the High Speed/ Low Effluent (HS/LE) process on both lab and large pilot scale as it would apply to wet mill and/or dry mill corn ethanol production. The HS/LE process allows very rapid fermentations, with 18 to 22% sugar syrups converted to 9 to 11% ethanol ‘beers’ in 6 to 12 hours using either a ‘consecutive batch’ or ‘continuous cascade’ implementation. This represents a 5 to 8X increase in fermentation speeds over conventional 72 hour batch fermentations which are the norm in the fuel ethanol industry today. The ‘consecutive batch’ technology was demonstrated on a large pilot scale (4,800 L) in a dry mill corn ethanol plant near Cedar Rapids, IA (Xethanol Biofuels). The pilot demonstrated that 12 hour fermentations can be accomplished on an industrial scale in a non-sterile industrial environment. Other objectives met in this project included development of a Low Energy (LE) Distillation process which reduces the energy requirements for distillation from about 14,000 BTU/gal steam ($0.126/gal with natural gas @ $9.00 MCF) to as low as 0.40 KW/gal electrical requirements ($0.022/gal with electricity @ $0.055/KWH). BPI also worked on the development of processes that would allow application of the HS/LE fermentation process to dry mill ethanol plants. A High-Value Corn ethanol plant concept was developed to produce 1) corn germ/oil, 2) corn bran, 3) ethanol, 4) zein protein, and 5) nutritional protein, giving multiple higher value products from the incoming corn stream.

  18. High-sensitivity chemiluminescence detection of cytokines using an antibody-immobilized CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Hong, Dong-Gu; Joung, Hyou-Arm; Kim, Sang-Hyo; Kim, Min-Gon

    2013-05-01

    In this study, we used a Complementary Metal Oxide Semiconductor (CMOS) image sensor with immobilizing antibodies on its surface to detect human cytokines, which are activators that mediate intercellular communication including expression and control of immune responses. The CMOS image sensor has many advantages over the Charge Couple Device, including lower power consumption, operation voltage, and cost. The photodiode, a unit pixel component in the CMOS image sensor, receives light from the detection area and generates digital image data. About a million pixels are embedded, and size of each pixel is 3 x 3 μm. The chemiluminescence reaction produces light from the chemical reaction of luminol and hydrogen peroxide. To detect cytokines, antibodies were immobilized on the surface of the CMOS image sensor, and a sandwich immunoassay using an HRP-labeled antibody was performed. An HRP-catalyzed chemiluminescence reaction was measured by each pixel of the CMOS image sensor. Pixels with stronger signals indicated higher cytokine concentrations; thus, we were able to measure human interleukin-5 (IL-5) at femtomolar concentrations.

  19. ESD evaluation of radiation-hardened, high-reliability CMOS and MNOS ICs

    SciTech Connect

    Soden, J.M.; Stewart, H.D.; Pastorek, R.A.

    1983-01-01

    Standard human-body-equivalent circuit electrostatic discharge (ESD) tests were performed on the inputs of high-reliability, radiation-hardened integrated circuits (ICs) designed with seven different technologies. Metal and silicon gate complementary MOS (CMOS) and metal-nitride-oxide-semiconductor (MNOS) ICs with design rules ranging from 10 microns down to 2 microns were evaluated. The ESD hardness of these ICs ranged from 1 kV to greater than 9 kV. The low-range ESD hardness ICs were fabricated with a masking polysilicon ring that defined the input protection diodes. Tests on commercial equivalent ICs demonstrated that the ESD hardness of the radiation-hardened ICs was not significantly less than the ESD hardness of the commercial equivalent ICs. The failure modes and mechanisms of the ICs were evaluated. Most of the ICs that did not have the masking polysilicon ring failed because of input to V/sub DD/ or V/sub SS/ shorts due to degraded protection diodes. ESD tests with the pulse applied between the package metal lid and the package pins were also performed. These lid tests produced permanent input damage, the same as occurred during tests with the pulse applied to the package input, but the damage occurred at lower voltages. ESD pulses with peak voltages as low as 250 volts produced arcs from the lid to the input bond wires, resulting in degraded inputs.

  20. ESD evaluation of radiation-hardened, high reliability CMOS and MNOS ICs

    SciTech Connect

    Soden, J.M.; Pastorek, R.A.; Stewart, H.D.

    1984-02-01

    Standard human body equivalent circuit electrostatic discharge (ESD) tests were performed on the inputs of high-reliability, radiation-hardened integrated circuits (ICs) designed with seven different technologies. Metal and silicon gate complementary MOS (CMOS) and metal-nitrideoxide-semiconductor (MNOS) ICs with design rules ranging from 10 microns down to 2 microns were evaluated. The ESD hardness of these ICs ranged from 1 kV to greater than 9 kV. The low range ESD hardness ICs were fabricated with a masking polysilicon ring that defined the input protection diodes. Tests on commercial equivalent ICs demonstrated that the ESD hardness of the radiation-hardened ICs was not significantly less than the ESD hardness of the commercial equivalent ICs. The failure modes and mechanisms of the ICs were evaluated. Most of the ICs that did not have the masking polysilicon ring failed because of input to V/sub DD/ or V/sub SS/ shorts due to degraded protection diodes. ESD tests with the pulse applied between the package metal lid and the package pins were also performed. These lid tests produced permanent input damage, the same as occurred during tests with the pulse applied to the package input, but the damage occurred at lower voltages. ESD pulses with peak voltages as low as 250 volts produced arcs from the lid to the input bond wires, resulting in degraded inputs.

  1. ESD evaluation of radiation-hardened, high-reliability CMOS and MNOS ICs

    NASA Astrophysics Data System (ADS)

    Soden, J. M.; Stewart, H. D.; Pastorek, R. A.

    Standard human-body-equivalent circuit electrostatic discharge (ESD) tests were performed on the inputs of high-reliability, radiation-hardened integrated circuits (ICs) designed with seven different technologies. Metal and silicon gate complementary metal oxide semiconductors (CMOS) and metal-nitride-oxide-semiconductor (MNOS) ICs with design rules ranging from 10 microns down to 2 microns were evaluated. The ESD hardness of these ICs ranged from 1 kV to greater than 9 kV. The low-range ESD hardness ICs were fabricated with a masking polysilicon ring that defined the input protection diodes. Tests on commercial equivalent ICs demonstrated that the ESD hardness of the radiation-hardened ICs was not significantly less than the ESD hardness of the commercial equivalent ICs. The failure modes and mechanisms of the ICs were evaluated. Most of the ICs that did not have the making polysilicon ring failed because of input to V sub DD or V sub SS shorts due to degraded protection diodes. ESD tests with the pulse applied between the package metal lid and the package pins were also performed. These lid tests produced permanent input damage, the same as occurred during tests with the pulse applied to the package input, but the damage occurred at lower voltages. ESD pulses with peak voltages as low as 250 volts produced arcs from the lid to the input bond wires, resulting in degraded inputs.

  2. High-resolution CMOS MEA platform to study neurons at subcellular, cellular, and network levels.

    PubMed

    Müller, Jan; Ballini, Marco; Livi, Paolo; Chen, Yihui; Radivojevic, Milos; Shadmani, Amir; Viswam, Vijay; Jones, Ian L; Fiscella, Michele; Diggelmann, Roland; Stettler, Alexander; Frey, Urs; Bakkum, Douglas J; Hierlemann, Andreas

    2015-07-07

    Studies on information processing and learning properties of neuronal networks would benefit from simultaneous and parallel access to the activity of a large fraction of all neurons in such networks. Here, we present a CMOS-based device, capable of simultaneously recording the electrical activity of over a thousand cells in in vitro neuronal networks. The device provides sufficiently high spatiotemporal resolution to enable, at the same time, access to neuronal preparations on subcellular, cellular, and network level. The key feature is a rapidly reconfigurable array of 26 400 microelectrodes arranged at low pitch (17.5 μm) within a large overall sensing area (3.85 × 2.10 mm(2)). An arbitrary subset of the electrodes can be simultaneously connected to 1024 low-noise readout channels as well as 32 stimulation units. Each electrode or electrode subset can be used to electrically stimulate or record the signals of virtually any neuron on the array. We demonstrate the applicability and potential of this device for various different experimental paradigms: large-scale recordings from whole networks of neurons as well as investigations of axonal properties of individual neurons.

  3. High-dynamic-range 4-Mpixel CMOS image sensor for scientific applications

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Bartkovjak, Peter; Do, Hung; Li, Wang; Appelbaum, Jeff; Lopez, Angel

    2012-03-01

    As bio-technology transitions from research and development to high volume production, dramatic improvements in image sensor performance will be required to support the throughput and cost requirements of this market. This includes higher resolution, higher frame rates, higher quantum efficiencies, increased system integration, lower read-noise, and lower device costs. We present the performance of a recently developed low noise 2048(H) x 2048(V) CMOS image sensor optimized for scientific applications such as life science imaging, microscopy, as well as industrial inspection applications. The sensor architecture consists of two identical halves which can be operated independently and the imaging array consists of 4T pixels with pinned photodiodes on a 6.5μm pitch with integrated micro-lens. The operation of the sensor is programmable through a SPI interface. The measured peak quantum efficiency of the sensor is 73% at 600nm, and the read noise is about 1.1e- RMS at 100 fps data rate. The sensor features dual gain column parallel ouput amplifiers with 11-bit single slope ADCs. The full well capacity is greater than 36ke-, the dark current is less than 7pA/cm2 at 20°C. The sensor achieves an intra-scene linear dynamic range of greater than 91dB (36000:1) at room temperature.

  4. A high performance multi-tap CMOS lock-in pixel image sensor for biomedical applications

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Shirakawa, Yuya; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2017-02-01

    We have developed and evaluated the large full well capacity (FWC) for wide signal detection range and low temporal noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two storage-diodes (SDs). In addition, for fast charge transfer from photodiode (PD) to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large FWC of approximately 7000e-, low temporal random noise of 1.17e-rms at 45fps with true correlated double sampling (CDS) operation, and fast intrinsic response less than 500ps at 635nm. The proposed imager has an effective pixel array of 128(H)×256(V) and a pixel size of 11.2×11.2μm2. The sensor chip is fabricated by a Dongbu HiTek 1P4M 0.11μm CIS process.

  5. Characterization of high resolution CMOS monolithic active pixel detector in SOI technology

    NASA Astrophysics Data System (ADS)

    Ahmed, M. I.; Arai, Y.; Glab, S.; Idzik, M.; Kapusta, P.; Miyoshi, T.; Takeda, A.; Turala, M.

    2015-05-01

    Novel CMOS monolithic pixel detectors designed at KEK and fabricated at Lapis Semiconductor in 0.2 μm Silicon-on-Insulator (SOI) technology are presented. A thin layer of silicon oxide separates high and low resistivity silicon layers, allowing for optimization of design of detector and readout parts. Shallow wells buried under the oxide in the detector part screen the entire pixel electronics from electrical field applied to the detector. Several integration type SOI pixel detectors have been developed with pixel sizes 8-20 μm. The general features of 14 × 14 μm2 detectors designed on different wafers (CZ-n, FZ-n and FZ-p) were measured and compared. The detector performance was studied under irradiation with visible and infra-red laser, and also X-ray ionizing source. Using X-rays from an Am-241 source the noise of readout electronics was measured at different working conditions, showing the ENC in the range of 88-120 e-. The pixel current was calculated from average DC pedestal shift while varying the pixel integration time. The operation of the detector was studied under partial and full depletion conditions. The effects of temperature and detector bias voltage on noise and leakage current were studied. Characteristics of an ADC integrated in the front-end chip are also presented.

  6. Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging

    PubMed Central

    Resetar, Tomislav; De Munck, Koen; Haspeslagh, Luc; Rosmeulen, Maarten; Süss, Andreas; Puers, Robert; Van Hoof, Chris

    2016-01-01

    This work explores the benefits of linear-mode avalanche photodiodes (APDs) in high-speed CMOS imaging as compared to different approaches present in literature. Analysis of APDs biased below their breakdown voltage employed in single-photon counting mode is also discussed, showing a potentially interesting alternative to existing Geiger-mode APDs. An overview of the recently presented gated pinned avalanche photodiode pixel concept is provided, as well as the first experimental results on a 8 × 16 pixel test array. Full feasibility of the proposed pixel concept is not demonstrated; however, informative data is obtained from the sensor operating under −32 V substrate bias and clearly exhibiting wavelength-dependent gain in frontside illumination. The readout of the chip designed in standard 130 nm CMOS technology shows no dependence on the high-voltage bias. Readout noise level of 15 e- rms, full well capacity of 8000e-, and the conversion gain of 75 µV/e- are extracted from the photon-transfer measurements. The gain characteristics of the avalanche junction are characterized on separate test diodes showing a multiplication factor of 1.6 for red light in frontside illumination. PMID:27537882

  7. Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging.

    PubMed

    Resetar, Tomislav; De Munck, Koen; Haspeslagh, Luc; Rosmeulen, Maarten; Süss, Andreas; Puers, Robert; Van Hoof, Chris

    2016-08-15

    This work explores the benefits of linear-mode avalanche photodiodes (APDs) in high-speed CMOS imaging as compared to different approaches present in literature. Analysis of APDs biased below their breakdown voltage employed in single-photon counting mode is also discussed, showing a potentially interesting alternative to existing Geiger-mode APDs. An overview of the recently presented gated pinned avalanche photodiode pixel concept is provided, as well as the first experimental results on a 8 × 16 pixel test array. Full feasibility of the proposed pixel concept is not demonstrated; however, informative data is obtained from the sensor operating under -32 V substrate bias and clearly exhibiting wavelength-dependent gain in frontside illumination. The readout of the chip designed in standard 130 nm CMOS technology shows no dependence on the high-voltage bias. Readout noise level of 15 e - rms, full well capacity of 8000 e - , and the conversion gain of 75 µV / e - are extracted from the photon-transfer measurements. The gain characteristics of the avalanche junction are characterized on separate test diodes showing a multiplication factor of 1.6 for red light in frontside illumination.

  8. 8-Foot High Speed Tunnel (HST

    NASA Technical Reports Server (NTRS)

    1957-01-01

    Interior view of the slotted throat test section installed in the 8-Foot High Speed Tunnel (HST) in 1950. The slotted region is about 160 inches in length. In this photograph, the sting-type model support is seen straight on. In a NASA report, the test section is described as follows: 'The test section of the Langley 8-foot transonic tunnel is dodecagonal in cross section and has a cross-sectional area of about 43 square feet. Longitudinal slots are located between each of the 12 wall panels to allow continuous operation through the transonic speed range. The slots contain about 11 percent of the total periphery of the test section. Six of the twelve panels have windows in them to allow for schlieren observations. The entire test section is enclosed in a hemispherical shaped chamber.' John Becker noted that the tunnel's 'final achievement was the development and use in routine operations of the first transonic slotted throat. The investigations of wing-body shapes in this tunnel led to Whitcomb's discovery of the transonic area rule.' James Hansen described the origins of the the slotted throat as follows: 'In 1946 Langley physicist Ray H. Wright conceived a way to do transonic research effectively in a wind tunnel by placing slots in the throat of the test section. The concept for what became known as the slotted-throat or slotted-wall tunnel came to Wright not as a solution to the chronic transonic problem, but as a way to get rid of wall interference (i.e., the mutual effect of two or more meeting waves or vibrations of any kind caused by solid boundaries) at subsonic speeds. For most of the year before Wright came up with this idea, he had been trying to develop a theoretical understanding of wall interference in the 8-Foot HST, which was then being repowered for Mach 1 capability.' When Wright presented these ideas to John Stack, the response was enthusiastic but neither Wright nor Stack thought of slotted-throats as a solution to the transonic problem, only

  9. High speed image correlation for vibration analysis

    NASA Astrophysics Data System (ADS)

    Siebert, T.; Wood, R.; Splitthof, K.

    2009-08-01

    Digital speckle correlation techniques have already been successfully proven to be an accurate displacement analysis tool for a wide range of applications. With the use of two cameras, three dimensional measurements of contours and displacements can be carried out. With a simple setup it opens a wide range of applications. Rapid new developments in the field of digital imaging and computer technology opens further applications for these measurement methods to high speed deformation and strain analysis, e.g. in the fields of material testing, fracture mechanics, advanced materials and component testing. The high resolution of the deformation measurements in space and time opens a wide range of applications for vibration analysis of objects. Since the system determines the absolute position and displacements of the object in space, it is capable of measuring high amplitudes and even objects with rigid body movements. The absolute resolution depends on the field of view and is scalable. Calibration of the optical setup is a crucial point which will be discussed in detail. Examples of the analysis of harmonic vibration and transient events from material research and industrial applications are presented. The results show typical features of the system.

  10. Multiple-samples-method enabling high dynamic range imaging for high frame rate CMOS image sensor by FPGA and co-processor

    NASA Astrophysics Data System (ADS)

    Jacquot, Blake C.; Johnson-Williams, Nathan

    2014-09-01

    We present results from a prototype CMOS camera system implementing a multiple sampled pixel level algorithm ("Last Sample Before Saturation") to create High-Dynamic Range (HDR) images that approach the dynamic range of CCDs. The system is built around a commercial 1280 × 1024 CMOS image sensor with 10-bits per pixel and up to 500 Hz full frame rate with higher frame rates available through windowing. We analyze imagery data collected at room temperature for SNR versus photocurrent, among other figures of merit. Results conform to expectations of a model that uses only dark current, read noise, and photocurrent as input parameters.

  11. A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments

    NASA Astrophysics Data System (ADS)

    Wei, Xiaomin; Gao, Deyuan; Doziere, Guy; Hu, Yann

    2013-02-01

    CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35 μm standard CMOS process. The prototype chips are adapted to work with frequencies up to 80 MHz, power supply voltages from 2.9 V to 3.3 V and temperatures from 0 °C to 60 °C. The single event latchup (SEL) tolerance is improved from 5.2 MeV cm2/mg to above 56 MeV cm2/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.

  12. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    NASA Astrophysics Data System (ADS)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  13. High-sensitivity 2.5-μm pixel CMOS image sensor realized using Cu interconnect layers

    NASA Astrophysics Data System (ADS)

    Tatani, Keiji; Enomoto, Yoshiyuki; Yamamoto, Atsuhiko; Goto, Takayuki; Abe, Hideshi; Hirayama, Teruo

    2006-02-01

    We have adapted Cu interconnect layers to realize a high sensitivity in a small-pixel CMOS image sensor with a pixel size of 2.5 × 2.5 μm. We used the 1P3M CMOS process, and applied Back End of Line (BEOL) with a design rule equivalent to the 90-nm process. The Cu process features a fill factor that is about 15% greater and an interconnect layer height about 40% less than those of the Al process. As a result, the sensitivity at F5.6 is about 5% greater, while that at F1.2 is about 30% greater. One of problems with the Cu process is the stopper film of the Cu that interferes with the light. Furthermore, this stopper film interacts with the SiO II layers to form a multilayer, which leads to a discontinuity in the reflection characteristics at some wavelengths (ripple). Our method involves removing the stopper films together with all the layers. We have also adopted the use of an inner lens. Using these methods, we were able to eliminate the problem of discontinuity in the reflection at some wavelengths. Another problem is the deterioration in the shading characteristics of the optical black area where the black standard is assumed, due to the fact that the Cu interconnect layer is much thinner than the Al interconnect layer. We confirmed that the optical black shading characteristic could be satisfied by using a color filter with the Cu interconnect layer. To realize a 2.5μm pixel CMOS image sensor, we developed the Cu interconnect process. As a result, we created a high-sensitivity CMOS image sensor. This technology should enable the further reduction of the pixel size to less than 2.5 μm.

  14. Interferometric comparison of the performance of a CMOS and sCMOS detector

    NASA Astrophysics Data System (ADS)

    Flores-Moreno, J. M.; De la Torre I., Manuel H.; Hernández-Montes, M. S.; Pérez-López, Carlos; Mendoza S., Fernando

    2015-08-01

    We present an analysis of the imaging performance of two state-of-the-art sensors widely used in the nondestructive- testing area (NDT). The analysis is based on the quantification of the signal-to-noise (SNR) ratio from an optical phase image. The calculation of the SNR is based on the relation of the median (average) and standard deviation measurements over specific areas of interest in the phase images of both sensors. This retrieved phase is coming from the vibrational behavior of a large object by means of an out-of-plane holographic interferometer. The SNR is used as a figure-of-merit to evaluate and compare the performance of the CMOS and scientific CMOS (sCMOS) camera as part of the experimental set-up. One of the cameras has a high speed CMOS sensor while the other has a high resolution sCMOS sensor. The object under study is a metallically framed table with a Formica cover with an observable area of 1.1 m2. The vibration induced to the sample is performed by a linear step motor with an attached tip in the motion stage. Each camera is used once at the time to record the deformation keeping the same experimental conditions for each case. These measurements may complement the conventional procedures or technical information commonly used to evaluate a camerás performance such as: quantum efficiency, spatial resolution and others. Results present post processed images from both cameras, but showing a smoother and easy to unwrap optical phase coming from those recorded with the sCMOS camera.

  15. High-End CMOS Active Pixel Sensors For Space-Borne Imaging Instruments

    DTIC Science & Technology

    2005-07-13

    sur la technologie CCD, alors que les capteurs CMOS à pixel actifs (APS) ont des nombreux avantages pour des applications embarquées. Cette...Les capteurs optiques intégrés sont utilisés dans le domaine spatial dans un large éventail d’applications. Beaucoup d’entres elles reposent toujours...publication présente des capteurs CMOS hautes performances d’aujourd’hui et met en lumière leurs avantages par rapport à leur équivalent CCD. Ces capteurs

  16. 14 CFR 23.253 - High speed characteristics.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High speed characteristics. 23.253 Section 23.253 Aeronautics and Space FEDERAL AVIATION ADMINISTRATION, DEPARTMENT OF TRANSPORTATION AIRCRAFT... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established...

  17. SPADAS: a high-speed 3D single-photon camera for advanced driver assistance systems

    NASA Astrophysics Data System (ADS)

    Bronzi, D.; Zou, Y.; Bellisai, S.; Villa, F.; Tisa, S.; Tosi, A.; Zappa, F.

    2015-02-01

    Advanced Driver Assistance Systems (ADAS) are the most advanced technologies to fight road accidents. Within ADAS, an important role is played by radar- and lidar-based sensors, which are mostly employed for collision avoidance and adaptive cruise control. Nonetheless, they have a narrow field-of-view and a limited ability to detect and differentiate objects. Standard camera-based technologies (e.g. stereovision) could balance these weaknesses, but they are currently not able to fulfill all automotive requirements (distance range, accuracy, acquisition speed, and frame-rate). To this purpose, we developed an automotive-oriented CMOS single-photon camera for optical 3D ranging based on indirect time-of-flight (iTOF) measurements. Imagers based on Single-photon avalanche diode (SPAD) arrays offer higher sensitivity with respect to CCD/CMOS rangefinders, have inherent better time resolution, higher accuracy and better linearity. Moreover, iTOF requires neither high bandwidth electronics nor short-pulsed lasers, hence allowing the development of cost-effective systems. The CMOS SPAD sensor is based on 64 × 32 pixels, each able to process both 2D intensity-data and 3D depth-ranging information, with background suppression. Pixel-level memories allow fully parallel imaging and prevents motion artefacts (skew, wobble, motion blur) and partial exposure effects, which otherwise would hinder the detection of fast moving objects. The camera is housed in an aluminum case supporting a 12 mm F/1.4 C-mount imaging lens, with a 40°×20° field-of-view. The whole system is very rugged and compact and a perfect solution for vehicle's cockpit, with dimensions of 80 mm × 45 mm × 70 mm, and less that 1 W consumption. To provide the required optical power (1.5 W, eye safe) and to allow fast (up to 25 MHz) modulation of the active illumination, we developed a modular laser source, based on five laser driver cards, with three 808 nm lasers each. We present the full characterization of

  18. High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

    NASA Astrophysics Data System (ADS)

    Sridhar, Ranjana; Pandey, Neeta; Bhattacharyya, Asok; Bhatia, Veepsa

    2016-06-01

    This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, -0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

  19. High speed exhaust gas recirculation valve

    SciTech Connect

    Fensom, Rod; Kidder, David J.

    2005-01-18

    In order to minimize pollutants such as Nox, internal combustion engines typically include an exhaust gas recirculation (EGR) valve that can be used to redirect a portion of exhaust gases to an intake conduit, such as an intake manifold, so that the redirected exhaust gases will be recycled. It is desirable to have an EGR valve with fast-acting capabilities, and it is also desirable to have the EGR valve take up as little space as possible. An exhaust gas recirculation valve is provided that includes an exhaust passage tube, a valve element pivotally mounted within the exhaust passage tube, a linear actuator; and a gear train. The gear train includes a rack gear operatively connected to the linear actuator, and at least one rotatable gear meshing with the rack gear and operatively connected to the valve element to cause rotation of the valve element upon actuation of the linear actuator. The apparatus provides a highly compact package having a high-speed valve actuation capability.

  20. Material constraints on high-speed design

    NASA Astrophysics Data System (ADS)

    Bucur, Diana; Militaru, Nicolae

    2015-02-01

    Current high-speed circuit designs with signal rates up to 100Gbps and above are implying constraints for dielectric and conductive materials and their dependence of frequency, for component elements and for production processes. The purpose of this paper is to highlight through various simulation results the frequency dependence of specific parameters like insertion and return loss, eye diagrams, group delay that are part of signal integrity analyses type. In low-power environment designs become more complex as the operation frequency increases. The need for new materials with spatial uniformity for dielectric constant is a need for higher data rates circuits. The fiber weave effect (FWE) will be analyzed through the eye diagram results for various dielectric materials in a differential signaling scheme given the fact that the FWE is a phenomenon that affects randomly the performance of the circuit on balanced/differential transmission lines which are typically characterized through the above mentioned approaches. Crosstalk between traces is also of concern due to propagated signals that have tight rise and fall times or due to high density of the boards. Criteria should be considered to achieve maximum performance of the designed system requiring critical electronic properties.

  1. High-Speed Data Recorder for Space, Geodesy, and Other High-Speed Recording Applications

    NASA Technical Reports Server (NTRS)

    Taveniku, Mikael

    2013-01-01

    A high-speed data recorder and replay equipment has been developed for reliable high-data-rate recording to disk media. It solves problems with slow or faulty disks, multiple disk insertions, high-altitude operation, reliable performance using COTS hardware, and long-term maintenance and upgrade path challenges. The current generation data recor - ders used within the VLBI community are aging, special-purpose machines that are both slow (do not meet today's requirements) and are very expensive to maintain and operate. Furthermore, they are not easily upgraded to take advantage of commercial technology development, and are not scalable to multiple 10s of Gbit/s data rates required by new applications. The innovation provides a softwaredefined, high-speed data recorder that is scalable with technology advances in the commercial space. It maximally utilizes current technologies without being locked to a particular hardware platform. The innovation also provides a cost-effective way of streaming large amounts of data from sensors to disk, enabling many applications to store raw sensor data and perform post and signal processing offline. This recording system will be applicable to many applications needing realworld, high-speed data collection, including electronic warfare, softwaredefined radar, signal history storage of multispectral sensors, development of autonomous vehicles, and more.

  2. Modifications in CMOS Dynamic Logic Style: A Review Paper

    NASA Astrophysics Data System (ADS)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  3. Control circuitry for high speed VLSI (Very Large Scale Integration) winograd fourier transform processors

    NASA Astrophysics Data System (ADS)

    Rossbach, P. C.

    1985-12-01

    The calculation of the Discrete Fourier Transform has long been a significant bottleneck in many Digital Signal Processing applications. With the arrival of Very Large Scale Integration and new DFT algorithms, system architectures that significantly reduce the DFT bottleneck are possible. This thesis addresses the design, simulation, implementation, and testing of the control circuitry for a high speed, VLSI Winograd Fourier Transform (WFT) processor. Three WFT processors are combined into a pipelined architecture that is capable of computing a 4080-point DFT on complex input data approximately every 120 microseconds when operating with 70 MHz clock signals. The chip control architecture features a special Programmable Logic Array (PLA) to control the on-chip arithmetic circuitry, and a dense, 54K ROM to generate data addresses for the external RAM. The PLA controller was fabricated in 3 micron CMOS and functioned properly for clock rates of over 60 MHz. The address generator ROM was designed and submitted for fabrication in 3 micron CMOS, and SPICE simulations predict an access time of 60 nanoseconds. Software that automatically generates a ROM layout description from a data file was developed to ensure the correctness of the final design. The transistor minimization procedure i s based on a graph partitioning heuristic, and the drain removal procedure is based on an algorithm that near-optimally solves the Traveling Salesman Problem.

  4. High speed imaging technology: yesterday, today, and tomorrow

    NASA Astrophysics Data System (ADS)

    Pendley, Gil J.

    2003-07-01

    The purpose of this discussion is to familiarize readers with an overview of high-speed imaging technology as a means of analyzing objects in motion that occur too fast for the eye to see or conventional photography or video to capture. This information is intended to provide a brief historical narrative from the inception of high-speed imaging in the USA and the acceptance of digital video technology to augment or replace high-speed motion picture cameras. It is not intended a definitive work on the subject. For those interested in greater detail, such as application techniques, formulae, very high-speed and ultra speed technology etc. I recommend the latest text on the subject: High Speed Photography and Photonics first published in 1997 by Focal Press in the UK and copyrighted by the Association for High Speed Photography in the United Kingdom.

  5. Analysis of coupling between high-speed railway and common speed railway system in transportation corridor

    NASA Astrophysics Data System (ADS)

    Zhou, Hongchang; Li, Haijun; Chen, Xiaohong; Zhu, Changfeng

    2017-04-01

    The high-speed railway and common speed railway subsystems as important components of the railway transportation system, can make railway traffic organization more orderly, when there are a rational division and balance development between them. In order to quantitatively evaluate the coordinate relations between high-speed railway subsystem and common speed railway subsystem, this paper takes the railway transportation corridor from Baoji to Lanzhou as an example. Firstly, using Logit model and grey forecasting model predict the passenger volume, passenger turnover and time value of high-speed railway and common speed railway in the Baoji-Lanzhou corridor. And then, the coupling forecast model of these two subsystems is established. Lastly, the coupling and coupling coordination of these two subsystems using are predicted and analyzed at theatrically level.

  6. The unstable behavior of low and high-speed compressors

    SciTech Connect

    Day, I.J. . Whittle Lab.); Freeman, C. )

    1994-04-01

    By far the greater part of the understanding about stall and surge in axial compressors comes from work on low-speed laboratory machines. As a general rule, these machines do not model the compressibility effects present in high-speed compressors and therefore doubt has always existed about the application of low-speed results to high-speed machines. In recent years interest in active control has led to a number of studies of compressor stability in engine-type compressors. The instrumentation used in these experiments has been sufficiently detailed that, for the first time, adequate data are available to make direct comparisons between high-speed and low-speed compressors. This paper presents new data from an eight-stage fixed geometry engine compressor and compares then with low-speed laboratory data. The results show remarkable similarities in both the stalling and surging behavior of the two machines, particularly when the engine compressor is run at intermediate speeds. The engine results also show that, as in the laboratory tests, surge is precipitated by the onset of rotating stall. This is true even at very high speeds where it had previously been thought that surge might be the result of a blast wave moving through the compressor. This paper therefore contains new information about high-speed compressors and confirms that low-speed testing is an effective means of obtaining insight into the behavior of high-speed machines.

  7. Large monolithic particle pixel-detector in high-voltage CMOS technology

    NASA Astrophysics Data System (ADS)

    Perić, I.; Takacs, C.

    2010-12-01

    A large monolithic particle pixel-detector implemented as system on a chip in a high-voltage 0.35 μm CMOS technology will be presented. The detector uses high-voltage n-well/p-substrate diodes as pixel-sensors. The diodes can be reversely biased with more than 60 V. In this way, depleted zones of about 10 μm thickness are formed, where the signal charges can be collected by drift. Due to fast charge collection in the strong electric-field zones, a higher radiation tolerance of the sensor is expected than in the case of the standard MAPS detectors. Simple pixel-readout electronics are implemented inside the n-wells. The readout is based on a source follower with one select- and two reset-transistors. Due to embedding of the pixel-readout electronics inside the collecting electrodes (n-wells) there are no insensitive zones within the pixel matrix. The detector chip contains a 128×128 matrix consisting of pixels of 21×21 μm2 -size. The diode voltages of one selected pixel-row are received at the bottom of the matrix by 128 eight-bit single-slope ADCs. All ADCs operate in parallel. The ADC codes are read out using eight LVDS 500 MBit/s output links. The readout electronics are designed to allow the readout of the whole pixel matrix in less than 50 μs. The total DC power consumption of the chip is 50 mW. All analog parts of the chip are implemented using radiation-hard layout techniques. Experimental results will be presented.

  8. A high linearity current mode second IF CMOS mixer for a DRM/DAB receiver

    NASA Astrophysics Data System (ADS)

    Jian, Xu; Zheng, Zhou; Yiqiang, Wu; Zhigong, Wang; Jianping, Chen

    2015-05-01

    A passive current switch mixer was designed for the second IF down-conversion in a DRM/DAB receiver. The circuit consists of an input transconductance stage, a passive current switching stage, and a current amplifier stage. The input transconductance stage employs a self-biasing current reusing technique, with a resistor shunt feedback to increase the gain and output impedance. A dynamic bias technique is used in the switching stage to ensure the stability of the overdrive voltage versus the PVT variations. A current shunt feedback is introduced to the conventional low-voltage second-generation fully balanced multi-output current converter (FBMOCCII), which provides very low input impedance and high output impedance. With the circuit working in current mode, the linearity is effectively improved with low supply voltages. Especially, the transimpedance stage can be removed, which simplifies the design considerably. The design is verified with a SMIC 0.18 μm RF CMOS process. The measurement results show that the voltage conversation gain is 1.407 dB, the NF is 16.22 dB, and the IIP3 is 4.5 dBm, respectively. The current consumption is 9.30 mA with a supply voltage of 1.8 V. This exhibits a good compromise among the gain, noise, and linearity for the second IF mixer in DRM/DAB receivers. Project supported by the National Natural Science Foundation of China (No. 61306069), and the National High Technology Research and Development Program of China (No. 2011AA010301).

  9. The high speed civil transport and NASA's High Speed Research (HSR) program

    NASA Technical Reports Server (NTRS)

    Shaw, Robert J.

    1994-01-01

    Ongoing studies being conducted not only in this country but in Europe and Asia suggest that a second generation supersonic transport, or High-Speed Civil Transport (HSCT), could become an important part of the 21st century international air transportation system. However, major environmental compatibility and economic viability issues must be resolved if the HSCT is to become a reality. This talk will overview the NASA High-Speed Research (HSR) program which is aimed at providing the U.S. industry with a technology base to allow them to consider launching an HSCT program early in the next century. The talk will also discuss some of the comparable activities going on within Europe and Japan.

  10. How to Combine Engines to Achieve High Speed, Hypersonic Speed, Speed of Light and Even Higher-Applications

    NASA Astrophysics Data System (ADS)

    Mwizerwa, Celestin; Nishimwe, Celestine

    2014-03-01

    When Einstein left us, he left us a really big problem to solve, does anything can travel faster than the speed of light? There hasn't been any way to try this in the past, because there were any technology which could accelerate objects at this speed. What researchers tried to do, was to accelerate particles. But there must be a way to play with speeds so that, as we do math, we may practically multiply the speed by any number we want, we also may practically divide the speed by any number we want. In this paper I will try to show how. Also, In our real life, there might be a need of such high speeds, so that a lot of problems may be solved, as for example the airplane technology, electric power, space travel, car transmission, industrial high temperature and so on ...I do not say for sure that, the object will move faster than the speed of light, but, people who have ability may try to accelerate it at this speed and even faster to see what will happen as now it is very easy to realize. There are two ways; you go to space to do it or, you create a vacuum and move it inside.

  11. High speed point derivative microseismic detector

    DOEpatents

    Uhl, James Eugene; Warpinski, Norman Raymond; Whetten, Ernest Blayne

    1998-01-01

    A high speed microseismic event detector constructed in accordance with the present invention uses a point derivative comb to quickly and accurately detect microseismic events. Compressional and shear waves impinging upon microseismic receiver stations disposed to collect waves are converted into digital data and analyzed using a point derivative comb including assurance of quiet periods prior to declaration of microseismic events. If a sufficient number of quiet periods have passed, the square of a two point derivative of the incoming digital signal is compared to a trip level threshold exceeding the determined noise level to declare a valid trial event. The squaring of the derivative emphasizes the differences between noise and signal, and the valid event is preferably declared when the trip threshold has been exceeded over a temporal comb width to realize a comb over a given time period. Once a trial event has been declared, the event is verified through a spatial comb, which applies the temporal event comb to additional stations. The detector according to the present invention quickly and accurately detects initial compressional waves indicative of a microseismic event which typically exceed the ambient cultural noise level by a small amount, and distinguishes the waves from subsequent larger amplitude shear waves.

  12. High speed point derivative microseismic detector

    DOEpatents

    Uhl, J.E.; Warpinski, N.R.; Whetten, E.B.

    1998-06-30

    A high speed microseismic event detector constructed in accordance with the present invention uses a point derivative comb to quickly and accurately detect microseismic events. Compressional and shear waves impinging upon microseismic receiver stations disposed to collect waves are converted into digital data and analyzed using a point derivative comb including assurance of quiet periods prior to declaration of microseismic events. If a sufficient number of quiet periods have passed, the square of a two point derivative of the incoming digital signal is compared to a trip level threshold exceeding the determined noise level to declare a valid trial event. The squaring of the derivative emphasizes the differences between noise and signal, and the valid event is preferably declared when the trip threshold has been exceeded over a temporal comb width to realize a comb over a given time period. Once a trial event has been declared, the event is verified through a spatial comb, which applies the temporal event comb to additional stations. The detector according to the present invention quickly and accurately detects initial compressional waves indicative of a microseismic event which typically exceed the ambient cultural noise level by a small amount, and distinguishes the waves from subsequent larger amplitude shear waves. 9 figs.

  13. Computation of High Speed Jet Noise

    NASA Technical Reports Server (NTRS)

    Freund, Jonathan B.

    2002-01-01

    The objective of this work was to use direct numerical simulation (DNS) techniques to study the physics of noise generation by a high-speed turbulent jet. A Mach 0.9, Reynolds number 3,600 jet was selected because of available experimental data. New numerical methods for generating disturbances at the nozzle and computing far-field sound were developed and reported in the course of this work. Over 25 million mesh points were used in the simulations which ran for over 50,000 timesteps and required over 50,000 processor hours on state-of-the-art parallel computer systems to complete. Figures show a visualization of the jet and sound field, a comparison of the mean flow development with the experiment, a directivity comparison with the experiment, and time spectrum comparison with the experiment. Agreement is seen to be excellent. These are fully document in the attached references. Full details of the work, detailed achievements and conclusions are discussed in appendices, which are copies of publications that resulted from this work. We have studied noise mechanisms in supersonic jets, the refraction of sound by turbulence in subsonic jets, and noise sources in conjunction with a DNS of a Mach 0.9 jet.

  14. 8-Foot High Speed Tunnel (HST)

    NASA Technical Reports Server (NTRS)

    1953-01-01

    Semi-automatic readout equipment installed in the 1950s used for data recording and reduction in the 8-Foot High Speed Tunnel (HST). A 1957 NACA report on wind tunnel facilities at Langley included these comments on the data recording and reduction equipment for the 8-foot HST: 'The data recording and reduction equipment used for handling steady force and pressure information at the Langley 8-foot transonic tunnel is similar to that described for the Langley 16-foot transonic tunnel. Very little dynamic data recording equipment, however, is available.' The description of the 16-foot transonic tunnel equipment is as follows: 'A semiautomatic force data readout system provides tabulated raw data and punch card storage of raw data concurrent with the operation of the wind tunnel. Provision is made for 12 automatic channels of strain gage-data output, and eight channels of four-digit manually operated inputs are available for tabulating and punching constants, configuration codes, and other information necessary for data reduction and identification. The data are then processed on electronic computing machines to obtain the desired coefficients. These coefficients and their proper identification are then machine tabulated to provide a printed record of the results. The punched cards may also be fed into an automatic plotting device for the preparation of plots necessary for data analysis.'

  15. High-transonic-speed transport aircraft study

    NASA Technical Reports Server (NTRS)

    Kulfan, R. M.

    1974-01-01

    An initial design study of high-transonic-speed transport aircraft has been completed. Five different design concepts were developed. These included fixed swept wing, variable-sweep wing, delta wing, double-fuselage yawed-wing, and single-fuselage yawed-wing aircraft. The boomless supersonic design objectives of range = 5560 km (3000 nmi), payload = 18,143 kg (40,000 lb), Mach = 1.2, and FAR Part 36 aircraft noise levels were achieved by the single-fuselage yawed-wing configuration with a gross weight of 211,828 kg (467,000 lb). A noise level of 15 EPNdB below FAR Part 36 requirements was obtained with a gross weight increase to 226,796 kg (500,000 lb). The off-design subsonic range capability for this configuration exceeded the Mach 1.2 design range by more than 20%. Although wing aeroelastic divergence was a primary design consideration for the yawed-wing concepts, the graphite-epoxy wings of this study were designed by critical gust and maneuver loads rather than by divergence requirements. The transonic nacelle drag is shown to be very sensitive to the nacelle installation. A six-degree-of-freedom dynamic stability analysis indicated that the control coordination and stability augmentation system would require more development than for a symmetrical airplane but is entirely feasible. A three-plane development plan is recommended to establish the full potential of the yawed-wing concept.

  16. High speed imaging in icing windtunnel tests

    NASA Astrophysics Data System (ADS)

    de Pauw, Dennis; Graham, Percival; Dolatabadi, Ali

    2012-11-01

    The detailed visualization and behavior of a spray impinging on a hydrophilic, and superhydrophobic aerodynamic shape in isothermal room and icing conditions can provide deep understanding of in-flight icing. A superhydrophobic coating has a very low surface energy so it can be used to counteract the ice accumulation. It also reduces the adhesion strength of ice to the surface which ensures easier removal of the ice during flight. The focus of the experiments primarily lies on the fundamental study of multiple droplet, i.e. spray, impact on a NACA 0012 airfoil in room and icing conditions. Under such conditions, important icing features such as rivulets and runback flow are observed. This provides us with the basics of ice formation on an aerodynamic surface. The study also focuses on the comparison between aluminum and superhydrophobic surfaces for ice accumulation in conditions which approach flight conditions. All the experiments are carried out in a small scale icing windtunnel using high speed photography with frame rates ranging from five thousand to fifty thousand frames per second.

  17. Flickering aurora studies using high speed cameras

    NASA Astrophysics Data System (ADS)

    McHarg, M. G.; Stenbaek-Nielsen, H. C.; Samara, M.; Michell, R.; Hampton, D. L.; Haaland, R. K.

    2009-12-01

    We report on observations of flickering aurora using two different digital camera systems. The first, a high speed Phantom 7 camera with a Video Scope HS 1845 HS image intensifier coupled with an 50mm lens provides fast frame rates with data recorded at 200 and 400 frames per second with a 512x384 pixel, 11.8x8.8 degree FOV. The second system is an Andor Electron-Multiplying Charge Couple Device (EMCCD) running at 33 frames per second using a 256 by 256 format covering 16x16 degrees field of view. Both systems made observations of flickering aurora in the magnetic zenith, using optical filters transmitting the prompt blue and red emissions of nitrogen. The Andor system was deployed at the Poker Flat rocket range near Fairbanks AK, while the Phantom system was deployed approximately 400 miles north of Poker Flat at Toolik Lake observatory. We find both narrow band low frequency (~5-10 Hz) and wider band, higher frequency (50- 70 Hz) oscillations in the optical intensity of flickering aurora. Direct comparison of the optical data and the dispersion relation for ion cyclotron waves thought to be responsible for the modulation of electrons causing the intensity fluctuations seen in flickering aurora are presented.

  18. High speed ground transportation study. Executive summary

    SciTech Connect

    Not Available

    1992-10-01

    In 1991, the Washington State Legislature enacted Chapter 231, Laws of 1991 (SHB 1452), which directed that a comprehensive assessment be made of the feasibility of developing a high speed ground transportation (HSGT) system in the State of Washington. The legislation came about because there was a growing recognition that major transportation corridors were reaching unacceptable levels of congestion, and that even though most large metropolitan areas were developing specific plans to ease that congestion within their urban boundaries, intercity travel between those areas was becoming increasingly difficult. The study area included the State of Washington plus the Portland, OR urban area and the lower mainland of British Columbia. Two major corridors were identified and analyzed. The study was not meant to focus on the technologies but rather on the economic, environmental, institutional and financial feasibility of implementing HSGT in this state. The study was not meant to be a siting study. Alignments and station locations were assumed only to test feasibility, and to evaluate corridors and service areas. Specific location decisions will require more detailed engineering and operations studies.

  19. Enhanced high-speed coherent diffraction imaging

    NASA Astrophysics Data System (ADS)

    Potier, Jonathan; Fricker, Sebastien; Idir, Mourad

    2011-03-01

    Due to recent advances in X-ray microscopy, we are now able to image objects with nanometer resolution thanks to Synchrotron beam lines or Free Electron Lasers (FEL). The PCI (Phase Contrast Imaging) is a robust technique that can recover the wavefront from measurements of only few intensity pictures in the Fresnel diffraction region. With our fast straightforward calculus methods, we manage to provide the phase induced by a microscopic specimen in few seconds. We can therefore obtain high contrasted images from transparent materials at very small scales. To reach atomic resolution imaging and thus make a transition from the near to the far field, the Coherent Diffraction Imaging (CDI) technique finds its roots in the analysis of diffraction patterns to obtain the phase of the altered complex wave. Theoretical results about existence and uniqueness of this retrieved piece of information by both iterative and direct algorithms have already been released. However, performances of algorithms remain limited by the coherence of the X-ray beam, presence of random noise and the saturation threshold of the detector. We will present reconstructions of samples using an enhanced version of HIO algorithm improving the speed of convergence and its repeatability. As a first step toward a practical X-Ray CDI system, initial images for reconstructions are acquired with the laser-based CDI system working in the visible spectrum.

  20. High speed curved position sensitive detector

    DOEpatents

    Hendricks, Robert W.; Wilson, Jack W.

    1989-01-01

    A high speed curved position sensitive porportional counter detector for use in x-ray diffraction, the detection of 5-20 keV photons and the like. The detector employs a planar anode assembly of a plurality of parallel metallic wires. This anode assembly is supported between two cathode planes, with at least one of these cathode planes having a serpentine resistive path in the form of a meander having legs generally perpendicular to the anode wires. This meander is produced by special microelectronic fabrication techniques whereby the meander "wire" fans outwardly at the cathode ends to produce the curved aspect of the detector, and the legs of the meander are small in cross-section and very closely spaced whereby a spatial resolution of about 50 .mu.m can be achieved. All of the other performance characteristics are about as good or better than conventional position sensitive proportional counter type detectors. Count rates of up to 40,000 counts per second with 0.5 .mu.s shaping time constants are achieved.

  1. 8-Foot High Speed Tunnel (HST)

    NASA Image and Video Library

    1957-03-19

    Interior view of the slotted throat test section installed in the 8-Foot High Speed Tunnel (HST) in 1950. The slotted region is about 160 inches in length. In this photograph, the sting-type model support is seen straight on. In a NASA report, the test section is described as follows: The test section of the Langley 8-foot transonic tunnel is dodecagonal in cross section and has a cross-sectional area of about 43 square feet. Longitudinal slots are located between each of the 12 wall panels to allow continuous operation through the transonic speed range. The slots contain about 11 percent of the total periphery of the test section. Six of the twelve panels have windows in them to allow for schlieren observations. The entire test section is enclosed in a hemispherical shaped chamber. John Becker noted that the tunnel s final achievement was the development and use in routine operations of the first transonic slotted throat. The investigations of wing-body shapes in this tunnel led to Whitcomb s discovery of the transonic area rule. James Hansen described the origins of the the slotted throat as follows: In 1946 Langley physicist Ray H. Wright conceived a way to do transonic research effectively in a wind tunnel by placing slots in the throat of the test section. The concept for what became known as the slotted-throat or slotted-wall tunnel came to Wright not as a solution to the chronic transonic problem, but as a way to get rid of wall interference (i.e., the mutual effect of two or more meeting waves or vibrations of any kind caused by solid boundaries) at subsonic speeds. For most of the year before Wright came up with this idea, he had been trying to develop a theoretical understanding of wall interference in the 8-Foot HST, which was then being repowered for Mach 1 capability. When Wright presented these ideas to John Stack, the response was enthusiastic but neither Wright nor Stack thought of slotted-throats as a solution to the transonic problem, only the

  2. Silicon high speed modulator for advanced modulation: device structures and exemplary modulator performance

    NASA Astrophysics Data System (ADS)

    Milivojevic, Biljana; Wiese, Stefan; Whiteaway, James; Raabe, Christian; Shastri, Anujit; Webster, Mark; Metz, Peter; Sunder, Sanjay; Chattin, Bill; Anderson, Sean P.; Dama, Bipin; Shastri, Kal

    2014-03-01

    Fiber optics is well established today due to the high capacity and speed, unrivaled flexibility and quality of service. However, state of the art optical elements and components are hardly scalable in terms of cost and size required to achieve competitive port density and cost per bit. Next-generation high-speed coherent optical communication systems targeting a data rate of 100-Gb/s and beyond goes along with innovations in component and subsystem areas. Consequently, by leveraging the advanced silicon micro and nano-fabrication technologies, significant progress in developing CMOS platform-based silicon photonic devices has been made all over the world. These achievements include the demonstration of high-speed IQ modulators, which are important building blocks in coherent optical communication systems. In this paper, we demonstrate silicon photonic QPSK modulator based on a metal-oxide-semiconductor (MOS) capacitor structure, address different modulator configuration structures and report our progress and research associated with highspeed advanced optical modulation in silicon photonics

  3. High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

    NASA Astrophysics Data System (ADS)

    Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

    2016-04-01

    In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

  4. Chromotomosynthesis for high speed hyperspectral imagery

    NASA Astrophysics Data System (ADS)

    Bostick, Randall L.; Perram, Glen P.

    2012-09-01

    A rotating direct vision prism, chromotomosynthetic imaging (CTI) system operating in the visible creates hyperspectral imagery by collecting a set of 2D images with each spectrally projected at a different rotation angle of the prism. Mathematical reconstruction techniques that have been well tested in the field of medical physics are used to reconstruct the data to produce the 3D hyperspectral image. The instrument operates with a 100 mm focusing lens in the spectral range of 400-900 nm with a field of view of 71.6 mrad and angular resolution of 0.8-1.6 μrad. The spectral resolution is 0.6 nm at the shortest wavelengths, degrading to over 10 nm at the longest wavelengths. Measurements using a pointlike target show that performance is limited by chromatic aberration. The accuracy and utility of the instrument is assessed by comparing the CTI results to spatial data collected by a wideband image and hyperspectral data collected using a liquid crystal tunable filter (LCTF). The wide-band spatial content of the scene reconstructed from the CTI data is of same or better quality as a single frame collected by the undispersed imaging system with projections taken at every 1°. Performance is dependent on the number of projections used, with projections at 5° producing adequate results in terms of target characterization. The data collected by the CTI system can provide spatial information of equal quality as a comparable imaging system, provide high-frame rate slitless 1-D spectra, and generate 3-D hyperspectral imagery which can be exploited to provide the same results as a traditional multi-band spectral imaging system. While this prototype does not operate at high speeds, components exist which will allow for CTI systems to generate hyperspectral video imagery at rates greater than 100 Hz. The instrument has considerable potential for characterizing bomb detonations, muzzle flashes, and other battlefield combustion events.

  5. High Speed Dynamics in Brittle Materials

    NASA Astrophysics Data System (ADS)

    Hiermaier, Stefan

    2015-06-01

    Brittle Materials under High Speed and Shock loading provide a continuous challenge in experimental physics, analysis and numerical modelling, and consequently for engineering design. The dependence of damage and fracture processes on material-inherent length and time scales, the influence of defects, rate-dependent material properties and inertia effects on different scales make their understanding a true multi-scale problem. In addition, it is not uncommon that materials show a transition from ductile to brittle behavior when the loading rate is increased. A particular case is spallation, a brittle tensile failure induced by the interaction of stress waves leading to a sudden change from compressive to tensile loading states that can be invoked in various materials. This contribution highlights typical phenomena occurring when brittle materials are exposed to high loading rates in applications such as blast and impact on protective structures, or meteorite impact on geological materials. A short review on experimental methods that are used for dynamic characterization of brittle materials will be given. A close interaction of experimental analysis and numerical simulation has turned out to be very helpful in analyzing experimental results. For this purpose, adequate numerical methods are required. Cohesive zone models are one possible method for the analysis of brittle failure as long as some degree of tension is present. Their recent successful application for meso-mechanical simulations of concrete in Hopkinson-type spallation tests provides new insight into the dynamic failure process. Failure under compressive loading is a particular challenge for numerical simulations as it involves crushing of material which in turn influences stress states in other parts of a structure. On a continuum scale, it can be modeled using more or less complex plasticity models combined with failure surfaces, as will be demonstrated for ceramics. Models which take microstructural

  6. Calibration of GPS based high accuracy speed meter for vehicles

    NASA Astrophysics Data System (ADS)

    Bai, Yin; Sun, Qiao; Du, Lei; Yu, Mei; Bai, Jie

    2015-02-01

    GPS based high accuracy speed meter for vehicles is a special type of GPS speed meter which uses Doppler Demodulation of GPS signals to calculate the speed of a moving target. It is increasingly used as reference equipment in the field of traffic speed measurement, but acknowledged standard calibration methods are still lacking. To solve this problem, this paper presents the set-ups of simulated calibration, field test signal replay calibration, and in-field test comparison with an optical sensor based non-contact speed meter. All the experiments were carried out on particular speed values in the range of (40-180) km/h with the same GPS speed meter. The speed measurement errors of simulated calibration fall in the range of +/-0.1 km/h or +/-0.1%, with uncertainties smaller than 0.02% (k=2). The errors of replay calibration fall in the range of +/-0.1% with uncertainties smaller than 0.10% (k=2). The calibration results justify the effectiveness of the two methods. The relative deviations of the GPS speed meter from the optical sensor based noncontact speed meter fall in the range of +/-0.3%, which validates the use of GPS speed meter as reference instruments. The results of this research can provide technical basis for the establishment of internationally standard calibration methods of GPS speed meters, and thus ensures the legal status of GPS speed meters as reference equipment in the field of traffic speed metrology.

  7. High Speed Balancing Applied to the T700 Engine

    NASA Technical Reports Server (NTRS)

    Walton, J.; Lee, C.; Martin, M.

    1989-01-01

    The work performed under Contracts NAS3-23929 and NAS3-24633 is presented. MTI evaluated the feasibility of high-speed balancing for both the T700 power turbine rotor and the compressor rotor. Modifications were designed for the existing Corpus Christi Army Depot (CCAD) T53/T55 high-speed balancing system for balancing T700 power turbine rotors. Tests conducted under these contracts included a high-speed balancing evaluation for T700 power turbines in the Army/NASA drivetrain facility at MTI. The high-speed balancing tests demonstrated the reduction of vibration amplitudes at operating speed for both low-speed balanced and non-low-speed balanced T700 power turbines. In addition, vibration data from acceptance tests of T53, T55, and T700 engines were analyzed and a vibration diagnostic procedure developed.

  8. High Speed Link Radiated Emission Reduction

    NASA Astrophysics Data System (ADS)

    Bisognin, P.; Pelissou, P.; Cissou, R.; Giniaux, M.; Vargas, O.

    2016-05-01

    To control the radiated emission of high-speed link and associated unit, the current approach is to implement overall harness shielding on cables bundles. This method is very efficient in the HF/ VHF (high frequency/ very high frequency) and UHF (ultra-high frequency) ranges when the overall harness shielding is properly bonded on EMC back-shell. Unfortunately, with the increasing frequency, the associated half wavelength matches with the size of Sub-D connector that is the case for the L band. Therefore, the unit connectors become the main source of interference emission. For the L-band and S-band, the current technology of EMC back-shell leaves thin aperture matched with the L band half wavelength and therefore, the shielding effectiveness is drastically reduced. In addition, overall harness shielding means significant increases of the harness mass.Airbus D&S Toulouse and Elancourt investigated a new solution to avoid the need of overall harness shielding. The objective is to procure EM (Electro-Magnetic) clean unit connected to cables bundles free of any overall harness shielding. The proposed solution is to implement EMC common mode filtering on signal interfaces directly on unit PCB as close as possible the unit connector.Airbus D&S Elancourt designed and manufactured eight mock-ups of LVDS (Low Voltage Differential Signaling) interface PCBs' with different solutions of filtering. After verification of the signal integrity, three mock-ups were retained (RC filter and two common mode choke coil) in addition to the reference one (without EMC filter).Airbus D&S Toulouse manufactured associated LVDS cable bundles and integrated the RX (Receiver) and TX (Transmitter) LVDS boards in shielded boxes.Then Airbus D&S performed radiated emission measurement of the LVDS links subassemblies (e.g. RX and TX boxes linked by LVDS cables) according to the standard test method. This paper presents the different tested solutions and main conclusions on the feasibility of such

  9. High Speed, High Accuracy Stage for Advanced Lithography. Phase I

    DTIC Science & Technology

    2007-11-02

    noise and 5nm LSB of our laser interferometer. Zerodur Mounting bar Base expended in this direction Sensor heads Interferometer mirror ...state of the art. Their CORE machine claims an accuracy of 80nm over a 6- inch square field. This machine uses high-speed mirrors to scan multiple...variety of optical paths. If the laboratory is not quiet (e.g. if the interferometer mirror is moving, or if people are talking in the laboratory

  10. High speed flow cytometric separation of viable cells

    DOEpatents

    Sasaki, Dennis T.; Van den Engh, Gerrit J.; Buckie, Anne-Marie

    1995-01-01

    Hematopoietic cell populations are separated to provide cell sets and subsets as viable cells with high purity and high yields, based on the number of original cells present in the mixture. High-speed flow cytometry is employed using light characteristics of the cells to separate the cells, where high flow speeds are used to reduce the sorting time.

  11. High speed flow cytometric separation of viable cells

    DOEpatents

    Sasaki, D.T.; Van den Engh, G.J.; Buckie, A.M.

    1995-11-14

    Hematopoietic cell populations are separated to provide cell sets and subsets as viable cells with high purity and high yields, based on the number of original cells present in the mixture. High-speed flow cytometry is employed using light characteristics of the cells to separate the cells, where high flow speeds are used to reduce the sorting time.

  12. Measurements of speed of response of high-speed visible and IR optical detectors

    NASA Technical Reports Server (NTRS)

    Rowe, H. E.; Osmundson, J. S.

    1972-01-01

    A technique for measuring speed of response of high speed visible and IR optical detectors to mode-locked Nd:YAG laser pulses is described. Results of measurements of response times of four detectors are presented. Three detectors that can be used as receivers in a 500-MHz optical communication system are tested.

  13. Chicago-St. Louis high speed rail plan

    SciTech Connect

    Stead, M.E.

    1994-12-31

    The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team`s analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor.

  14. Water Containment Systems for Testing High-Speed Flywheels

    NASA Technical Reports Server (NTRS)

    Trase, Larry; Thompson, Dennis

    2006-01-01

    Water-filled containers are used as building blocks in a new generation of containment systems for testing high-speed flywheels. Such containment systems are needed to ensure safety by trapping high-speed debris in the event of centrifugal breakup or bearing failure. Traditional containment systems for testing flywheels consist mainly of thick steel rings. The effectiveness of this approach to shielding against high-speed debris was demonstrated in a series of tests.

  15. 33 CFR 84.24 - High-speed craft.

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... 33 Navigation and Navigable Waters 1 2013-07-01 2013-07-01 false High-speed craft. 84.24 Section... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at a...

  16. 33 CFR 84.24 - High-speed craft.

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... 33 Navigation and Navigable Waters 1 2014-07-01 2014-07-01 false High-speed craft. 84.24 Section... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at a...

  17. 33 CFR 84.24 - High-speed craft.

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... 33 Navigation and Navigable Waters 1 2012-07-01 2012-07-01 false High-speed craft. 84.24 Section... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at a...

  18. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    NASA Astrophysics Data System (ADS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  19. High-Speed General Purpose Genetic Algorithm Processor.

    PubMed

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  20. Silicon CMOS-based vertical multimode interference optical taps

    NASA Astrophysics Data System (ADS)

    Stenger, Vincent E.; Beyette, Fred R., Jr.

    2001-12-01

    A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. A recently introduced multimode interference effect based device has the potential for very high speed performance in a compact geometry and in a CMOS compatible process. For this work, 2-D and 3-D device simulations confirm a low excess optical loss on order of 0.1 dB, and a nominal 40% (2.2 dB) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated devices are on the order of 25micrometers in length and as narrow as 1 um. High temperature, hybrid polymer materials used for commercial CMOS inter-metal dielectric layers are targeted for tap fabrication and are incorporated into the models. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer multi-chip module and board level interconnects, as well as for metro fiber to the home and desk telecommunications applications.

  1. Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters

    NASA Astrophysics Data System (ADS)

    Gevaert, D.

    2007-05-01

    The design and testing of a 12-bit Analog-to-Digital (A/D) converter, in current mode, arranged in an 8-bit LSB and a 4- bit MSB architecture together with the integration of specialized test building blocks on chip allows the set up of a design automation technique for current folding and interpolation CMOS A/D converter architectures. The presented design methodology focuses on the automation for CMOS A/D building blocks in a flexible target current folding and interpolating architecture for a downscaling technology and for different quality specifications. The comprehensive understanding of all sources of mismatching in the crucial building blocks and the use of physical based mismatch modeling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of the A/D converter. In this design the folding degree is 16, the number of folders is 64 and the interpolation level is 4. The number of folders is reduced by creating intermediate folding signals with a 4-level interpolator based on current division techniques. Current comparators detect the zero-crossing between the differential folder output currents. The outputs of the comparators deliver a cyclic thermometer code. The digital synthesis part for decoding and error correction building blocks is a standardized digital standard cell design. The basic building blocks in the target architecture were designed in 0.35μ CMOS technology; they are suitable for topological reuse and are in an automated way downscaled into a 0.18μ CMOS technology.

  2. A time-of-flight range image sensor using high-speed 4-tap lock-in pixels

    NASA Astrophysics Data System (ADS)

    Komazawa, A.; Trang, H.; Takasawa, T.; Aoyama, S.; Yasutomi, K.; Kagawa, K.; Kawahito, S.

    2017-02-01

    This paper presents a CMOS Time-of-Flight (TOF) range imager using pinned-photodiode based high-speed 4-tap lock-in pixels with lateral-electric-field charge modulators (LEFM) in a 0.11 um CIS process. The proposed lock-in pixel structure using lateral electric field control is suitable for implementing a multiple-tap charge modulator while achieving high-speed charge transfer for high time resolution. The TOF imager with the multiple-tap charge modulators is expected to have background light cancelling capability in one frame and to improve range resolution with the 4 time windows for a range-shifted light pulse. Measurement results of the implemented TOF imager with 160×240 pixels are reported.

  3. High-speed dual Langmuir probe.

    PubMed

    Lobbia, Robert B; Gallimore, Alec D

    2010-07-01

    In an effort to temporally resolve the electron density, electron temperature, and plasma potential for turbulent plasma discharges, a unique high-speed dual Langmuir probe (HDLP) has been developed. A traditional single Langmuir probe of cylindrical geometry (exposed to the plasma) is swept simultaneously with a nearby capacitance and noise compensating null probe (fully insulated from the plasma) to enable bias sweep rates on a microsecond timescale. Traditional thin-sheath Langmuir probe theory is applied for interpretation of the collected probe data. Data at a sweep rate of 100 kHz are presented; however the developed system is capable of running at 1 MHz-near the upper limit of the applied electrostatic Langmuir probe theory for the investigated plasma conditions. Large sets (100,000 sweeps at each of 352 spatial locations) of contiguous turbulent plasma properties are collected using simple electronics for probe bias driving and current measurement attaining 80 dB signal-to-noise measurements with dc to 1 MHz bandwidth. Near- and far-field plume measurements with the HDLP system are performed downstream from a modern Hall effect thruster where the time-averaged plasma properties exhibit the approximate ranges: electron density n(e) from (1x10(15))-(5x10(16)) m(-3), electron temperature T(e) from 1 to 3.5 eV, and plasma potential V(p) from 5 to 15 V. The thruster discharge of 200 V (constant anode potential) and 2 A (average discharge current) displays strong, 2.2 A peak-to-peak, current oscillations at 19 kHz, characteristic of the thruster "breathing mode" ionization instability. Large amplitude discharge current fluctuations are typical for most Hall thrusters, yet the HDLP system reveals the presence of the same 19 kHz fluctuations in n(e)(t), T(e)(t), and V(p)(t) throughout the entire plume with peak-to-peak divided by mean plasma properties that average 94%. The propagation delays between the discharge current fluctuations and the corresponding plasma

  4. High-speed architecture for the decoding of trellis-coded modulation

    NASA Technical Reports Server (NTRS)

    Osborne, William P.

    1992-01-01

    Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

  5. High speed data transmission for the SSC solenoidal detector

    NASA Astrophysics Data System (ADS)

    Leskovar, B.

    1991-04-01

    High speed data transmission using fiber optics for the Superconducting Super Collider solenoidal detector has been studied. The solenoidal detector system will consist of nine subsystems involving more than a total 10(exp 7) channels of readout electronics. Consequently, a new high performance data acquisition system, incorporating high-speed optical fiber networks, will be required to process this large quantity of data.

  6. Holistic design in high-speed optical interconnects

    NASA Astrophysics Data System (ADS)

    Saeedi, Saman

    Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

  7. High-speed on-chip windowed centroiding using photodiode-based CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

    2003-01-01

    A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

  8. High-speed on-chip windowed centroiding using photodiode-based CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce (Inventor)

    2004-01-01

    A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

  9. Active High Power Conversion Efficiency Rectifier With Built-In Dual-Mode Back Telemetry in Standard CMOS Technology.

    PubMed

    Bawa, G; Ghovanloo, M

    2008-09-01

    In this paper, we present an active rectifier with high power conversion efficiency (PCE) implemented in a 0.5- mum 5 V standard CMOS technology with two modes of built-in back telemetry; short- and open-circuit. As a rectifier, it ensures a PCE > 80%, taking advantage of active synchronous rectification technique in the frequency range of 0.125-1 MHz. The built-in complementary back telemetry feature can be utilized in implantable microelectronic devices (IMD), wireless sensors, and radio frequency identification (RFID) applications to reduce the silicon area, increase the data rate, and improve the reading range and robustness in load shift keying (LSK).

  10. Time optimal paths for high speed maneuvering

    SciTech Connect

    Reister, D.B.; Lenhart, S.M.

    1993-01-01

    Recent theoretical results have completely solved the problem of determining the minimum length path for a vehicle with a minimum turning radius moving from an initial configuration to a final configuration. Time optimal paths for a constant speed vehicle are a subset of the minimum length paths. This paper uses the Pontryagin maximum principle to find time optimal paths for a constant speed vehicle. The time optimal paths consist of sequences of axes of circles and straight lines. The maximum principle introduces concepts (dual variables, bang-bang solutions, singular solutions, and transversality conditions) that provide important insight into the nature of the time optimal paths. We explore the properties of the optimal paths and present some experimental results for a mobile robot following an optimal path.

  11. High-speed optical 3D sensing and its applications

    NASA Astrophysics Data System (ADS)

    Watanabe, Yoshihiro

    2016-12-01

    This paper reviews high-speed optical 3D sensing technologies for obtaining the 3D shape of a target using a camera. The focusing speed is from 100 to 1000 fps, exceeding normal camera frame rates, which are typically 30 fps. In particular, contactless, active, and real-time systems are introduced. Also, three example applications of this type of sensing technology are introduced, including surface reconstruction from time-sequential depth images, high-speed 3D user interaction, and high-speed digital archiving.

  12. High-speed ground transportation: some current and future alternatives

    SciTech Connect

    Morita, T.

    1984-01-01

    High-speed ground transportation (HSGT), the value of time, and the social and technological considerations of inter-city transportation are discussed in this article. A particularly promising mode of high-speed ground transportation (MAGLEV) is discussed in some detail. An average speed for HSGT service, 400 kilometers per hour, seems to be attainable. In conclusion, the proposal for a hypersonic subway will be analyzed. 2 figures, 1 table.

  13. Full-field high-speed laser Doppler imaging system for blood-flow measurements

    NASA Astrophysics Data System (ADS)

    Serov, Alexandre; Lasser, Theo

    2006-02-01

    We describe the design and performance of a new full-field high-speed laser Doppler imaging system developed for mapping and monitoring of blood flow in biological tissue. The total imaging time for 256x256 pixels region of interest is 1.2 seconds. An integrating CMOS image sensor is utilized to detect Doppler signal in a plurality of points simultaneously on the sample illuminated by a divergent laser beam of a uniform intensity profile. The integrating property of the detector improves the signal-to-noise ratio of the measurement, which results in high-quality flow-images provided by the system. The new technique is real-time, non-invasive and the instrument is easy to use. The wide range of applications is one of the major challenges for a future application of the imager. High-resolution high-speed laser Doppler perfusion imaging is a promising optical technique for diagnostic and assessing the treatment effect of the diseases such as e.g. atherosclerosis, psoriasis, diabetes, skin cancer, allergies, peripheral vascular diseases, skin irritancy and wound healing. We present some biological applications of the new imager and discuss the perspectives for the future implementations of the imager for clinical and physiological applications.

  14. Multi-point, high-speed passive ion velocity distribution diagnostic on the Pegasus Toroidal Experiment.

    PubMed

    Burke, M G; Fonck, R J; Bongard, M W; Schlossberg, D J; Winz, G R

    2012-10-01

    A passive ion temperature polychromator has been deployed on Pegasus to study power balance and non-thermal ion distributions that arise during point source helicity injection. Spectra are recorded from a 1 m F/8.6 Czerny-Turner polychromator whose output is recorded by an intensified high-speed camera. The use of high orders allows for a dispersion of 0.02 Å/mm in 4th order and a bandpass of 0.14 Å (~13 km/s) at 3131 Å in 4th order with 100 μm entrance slit. The instrument temperature of the spectrometer is 15 eV. Light from the output of an image intensifier in the spectrometer focal plane is coupled to a high-speed CMOS camera. The system can accommodate up to 20 spatial points recorded at 0.5 ms time resolution. During helicity injection, stochastic magnetic fields keep T(e) low (100 eV) and thus low ionization impurities penetrate to the core. Under these conditions, high core ion temperatures are measured (T(i) ≈ 1.2 keV, T(e) ≈ 0.1 keV) using spectral lines from carbon III, nitrogen III, and boron IV.

  15. Multi-point, high-speed passive ion velocity distribution diagnostic on the Pegasus Toroidal Experiment

    SciTech Connect

    Burke, M. G.; Fonck, R. J.; Bongard, M. W.; Schlossberg, D. J.; Winz, G. R.

    2012-10-15

    A passive ion temperature polychromator has been deployed on Pegasus to study power balance and non-thermal ion distributions that arise during point source helicity injection. Spectra are recorded from a 1 m F/8.6 Czerny-Turner polychromator whose output is recorded by an intensified high-speed camera. The use of high orders allows for a dispersion of 0.02 A/mm in 4th order and a bandpass of 0.14 A ({approx}13 km/s) at 3131 A in 4th order with 100 {mu}m entrance slit. The instrument temperature of the spectrometer is 15 eV. Light from the output of an image intensifier in the spectrometer focal plane is coupled to a high-speed CMOS camera. The system can accommodate up to 20 spatial points recorded at 0.5 ms time resolution. During helicity injection, stochastic magnetic fields keep T{sub e} low ({approx}100 eV) and thus low ionization impurities penetrate to the core. Under these conditions, high core ion temperatures are measured (T{sub i} Almost-Equal-To 1.2 keV, T{sub e} Almost-Equal-To 0.1 keV) using spectral lines from carbon III, nitrogen III, and boron IV.

  16. Kevlar Properties Investigation High Speed Abrasion Resistance

    DTIC Science & Technology

    1980-02-01

    leading edge of the warp knuckle . These fibers were obviously flattened and smeared at the tips due to abrasion. The lack of severe cracking and...Parallel Configuration at a Speed of 160 fps Using a Contact Force of 15 Lb and a Contact Time of 30 Seconds 68 Photographs of Scorched Knuckle and...of filaments were protruding from the yarn knuckles giving the yarn an open appearance. Figure 4B shows photographs of the piled and unpiled surfaces

  17. High Speed Cascadable Signal Processing Circuits

    DTIC Science & Technology

    1988-04-29

    Mexico 88002 / "’ . Otavio J. Morales . Assistant Principal Investigator ~, . - .-" " The views, opinions, and/or findings contained in this report...T Fort Collins, Colorado 80525 U.S.Army White Sands Missile Ranpe New Mexico 88002-91h3 go. NAME OF FUNDING i SPONSOXINd 9b. OFFICE SYMBOL 9...general purpos; data processor. The Vector Processing Hardware ( VPH ) is a speed-optimized architecture capable of processing vectors of complex data. The

  18. High loading, low speed fan study, 5

    NASA Technical Reports Server (NTRS)

    Keenan, M. J.; Burdsall, E. A.

    1973-01-01

    A low speed, low noise, single stage fan was designed and tested. Design pressure ratio was 1.5 at a rotor tip speed of 1000 ft/sec. No inlet guide vane was used, the rotor stator was spaced and the number of rotor and stator airfoils was selected for low noise. Tests were conducted with uniform and distorted inlet flows. Stall margin of the initial design was too low for practical application. Airfoil slots and boundary layer and endwall devices did not improve stall margin sufficiently. A redesigned stator with reduced loadings increased stall margin, giving a fan efficiency of 0.883, 15% stall margin, and a 1.474 pressure radio at a specific flow of 41.7 lb/sec sq ft. Casing treatment over rotor tips improved stall margin with distorted inlet flow; vortex generators did not. Blade passing frequency noise increased with rotor relative Mach number. No supersonic fan noise was measured below 105% of design speed. Slotting airfoils, casing treatments, and a reduction of the ratio (number-stators/number-rotors) from (2n + 16) to (2n + 2) had no significant effects on noise.

  19. High-speed optical correlator with coaxial holographic system

    NASA Astrophysics Data System (ADS)

    Ikeda, Kanami; Watanabe, Eriko

    2015-09-01

    A high-speed volume holographic optical correlator is developed, which takes advantage of a coaxial holographic system. We have realized this high-speed correlator using an optimal design of the signal pattern, which improves the shift multiplex recording shift pitch. The speed of this correlator was further improved by increasing the number of pixels in the spatial light modulator and using a high speed rotating actuator. This correlation system successfully achieved an equal error rate of 0% by performing optical correlation over 900 times. It also achieved optical correlation experiment, at a shift pitch of 2.45 µm and a disk rotation speed of 900 rpm. In terms of optical correlation calculation speed, it yielded a peak interval of 542 ns, which corresponds to 1.846 × 106 frames per second.

  20. Structural vulnerability and intervention of high speed railway networks

    NASA Astrophysics Data System (ADS)

    Zhang, Jianhua; Hu, Funian; Wang, Shuliang; Dai, Yang; Wang, Yixing

    2016-11-01

    This paper employs complex network theory to assess the structural vulnerability of high speed railway networks subjected to two different malicious attacks. Chinese, US and Japanese high speed railway networks are used to discuss the vulnerable characteristics of systems. We find that high speed railway networks are very fragile when suffering serious disturbances and two attack rules can cause analogous damages to one high speed railway network, which illustrates that the station with large degree possesses high betweenness, vice versa. Meanwhile, we discover that Japanese high speed railway network has the best global connectivity, but Chinese high speed railway network has the best local connectivity and possesses the largest transport capacity. Moreover, we find that there exist several redundant paths in Chinese high speed railway network and discover the critical stations of three HSRNs. Furthermore, the nearest-link method is adopted to implement topological interventions and to improve the connectivity and reliability of high speed railway networks. In addition, the feasibility and effectiveness of topological interventions are shown by simulations.

  1. High-speed wireless optical LANs

    NASA Astrophysics Data System (ADS)

    Oe, Kunishige; Sato, Syuichi; Okayama, Motoyuki; Kubota, Toshihiro

    2001-11-01

    Study on high speed indoor wireless optical LAN system enabling 100Mbps signal transmission with low bit error rate (10-9) is presented. To realize the optical LAN system handling 100 Mbps signal, a directed line of sight (LOS) system is adopted as the optical receiver sensitivity for a bit error rate of 10-9 for 100 Mbps signals is fairly large. In the system, new approaches are introduced: WDM technology which enables bi-directional transmission in full duplex manner is applied using a 1.3 micrometers laser diode for down-link and 0.65 micrometers red laser diode for up-link light sources. As the wavelengths of the two lasers are quite separated from each other, this WDM technology brings an advantage that two kind of semiconductor materials can be used for detectors; GaInAs is used for down-link while Si is applied for up-link. GaInAs PD cannot detect the up-link laser light of 0.65 micrometers and Si PD or APD cannot detect the down-link laser light of 1.3micrometers . Therefore full duplex transmission can be achieved in this configuration. In the indoor wireless optical LAN system, one of the critical points is the transmitter configuration for down- link which enables to deliver optical power enough for 100 Mbps transmission to user areas as wide as possible with inexpensive prices. To realize the point, a special 1.3micrometers laser diode, a spot-size converter integrated laser (SS-LD), is introduced in company with convex lens and an object lens to deliver optical power to areas as wide as possible. As the far-field patterns of the SS-LD are fairly narrow, most of the output power of the LD could be collected to and spread wide by the object lens of 40 magnifications. Using the device, 3m diameter circle area in the plane 2m apart from the 1.3micrometers SS-LD emitting 20 mW optical power, could receive optical power above the receiver sensitivity for a bit error rate of 10-9 for 100 Mbps signals. The visible red light is convenient for not only position

  2. High-resolution high-speed panoramic cardiac imaging system

    PubMed Central

    Evertson (In Memoriam), Dale W.; Holcomb, Mark R.; Eames, Matthew D.C.; Bray, Mark-Anthony P.; Sidorov, Veniamin Y.; Xu, Junkai; Wingard, Holley; Dobrovolny, Hana M.; Woods, Marcella C.; Gauthier, Daniel J.; Wikswo, John P.

    2008-01-01

    A panoramic cardiac imaging system consisting of three high-speed CCD cameras has been developed to image the surface electrophysiology of a rabbit heart via fluorescence imaging using a voltage-sensitive fluorescent dye. A robust, unique mechanical system was designed to accommodate the three cameras and to adapt to the requirements of future experiments. A unified computer interface was created for this application – a single workstation controls all three CCD cameras, illumination, and stimulation, and the stepping motor rotates the heart. The geometric reconstruction algorithms were adapted from a previous cardiac imaging system. We demonstrate the system by imaging a polymorphic cardiac tachycardia. PMID:18334422

  3. The Advantages of ISDN for High-Speed Remote Access.

    ERIC Educational Resources Information Center

    Galvin, Mark; Hauf, Al

    1997-01-01

    Explains why ISDN (integrated services digital network) is the most practical solution for high-speed remote access, including reliability, cost, flexibility, scaleability, standards, and manageability. Other data transmission options are discussed, including asymmetric digital subscriber lines (ADSL), high-speed digital subscriber lines (HDSL),…

  4. HIGH-SPEED GC/MS FOR AIR ANALYSIS

    EPA Science Inventory

    High speed or fast gas chromatography (FGC) consists of narrow bandwidth injection into a high-speed carrier gas stream passing through a short column leading to a fast detector. Many attempts have been made to demonstrate FGC, but until recently no practical method for routin...

  5. Seakeeping Analysis of Small Displacement High-Speed Vessels

    DTIC Science & Technology

    2003-03-01

    72 73 74 75 76 77 78 79 80 81 82 83 VI. LIST OF REFERENCES [1] Kennell, Colen. Design ... trends in High-Speed Transport. Marine Technology, Vol. 35, No. 3, July 1998, pp.127-134. [2] Ritter, Owen K., Templeman, Michael T. High-Speed

  6. HIGH-SPEED GC/MS FOR AIR ANALYSIS

    EPA Science Inventory

    High speed or fast gas chromatography (FGC) consists of narrow bandwidth injection into a high-speed carrier gas stream passing through a short column leading to a fast detector. Many attempts have been made to demonstrate FGC, but until recently no practical method for routin...

  7. High-Speed Video Analysis of Damped Harmonic Motion

    ERIC Educational Resources Information Center

    Poonyawatpornkul, J.; Wattanakasiwich, P.

    2013-01-01

    In this paper, we acquire and analyse high-speed videos of a spring-mass system oscillating in glycerin at different temperatures. Three cases of damped harmonic oscillation are investigated and analysed by using high-speed video at a rate of 120 frames s[superscript -1] and Tracker Video Analysis (Tracker) software. We present empirical data for…

  8. 33 CFR 84.24 - High-speed craft.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... of the isosceles triangle formed by the side lights and masthead light when seen in end elevation is... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at...

  9. 33 CFR 84.24 - High-speed craft.

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... of the isosceles triangle formed by the side lights and masthead light when seen in end elevation is... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at...

  10. High-Speed Video Analysis of Damped Harmonic Motion

    ERIC Educational Resources Information Center

    Poonyawatpornkul, J.; Wattanakasiwich, P.

    2013-01-01

    In this paper, we acquire and analyse high-speed videos of a spring-mass system oscillating in glycerin at different temperatures. Three cases of damped harmonic oscillation are investigated and analysed by using high-speed video at a rate of 120 frames s[superscript -1] and Tracker Video Analysis (Tracker) software. We present empirical data for…

  11. High-speed tomography using pink beam at GeoSoilEnviroCARS

    NASA Astrophysics Data System (ADS)

    Rivers, Mark L.

    2016-10-01

    Synchrotron microtomography typically uses monochromatic beams, because these avoid beam-hardening artifacts and allow imaging above and below the absorption edges of specific elements. However, the monochromator greatly reduces the flux on the sample, and thus increases the data collection time. An alternative is to eliminate the monochromator, instead using absorbers to remove low-energy x-rays and reflection from a mirror to remove high-energy x-rays. This produces a pink beam with a large energy bandwidth and more than 1000 times greater flux. This is useful for dynamic studies, where an entire 3-D dataset can be collected in just a few seconds. We have implemented pink beam tomography at the 13-BM-D beamline at the GeoSoilEnviroCARS sector 13 at the Advanced Photon Source. A key component of such a system is a high-speed detector that can collect over 100 frames/s with excellent signal/noise. We are using a new generation of inexpensive CMOS detectors with very low read noise, large full-well capacity, and high speed. The system performs well, and first experiments in studying fluid imbibition and drainage are presented.

  12. Experimental Investigation of Micro Counter-Current Flow Using High-Speed Micro PIV

    NASA Astrophysics Data System (ADS)

    Shinohara, Kyosuke; Sugii, Yasuhiko; Aota, Arata; Hibara, Akihide; Kitamori, Takehiko; Okamoto, Koji

    2004-11-01

    Microfluidic devices have been developed for chemical analysis as micro total analysis systems (u-TAS). To utilize scale merits, continuous-flow chemical processing and micro unit operations had been proposed as microfluidic device including mixing, phase confluence, solvent extraction, and so on. Recently, as one of these integrated chemical processes, micro counter-current flow system had been developed for highly efficient solvent extraction. The system consisted of oil flow and water flow in inverse direction. Using the system, more efficient extraction of Co (II) complex than theoretical prediction was confirmed. In this paper, in order to investigate the fundamental characteristics of the micro counter-current flow, velocity fields of the micro counter-current flow were measured using high-speed micro PIV system. The system consisted of a high-speed CMOS camera with an image intensifier, an epi-fluorescent microscope with an objective lens and a color filter, and a CW laser. The velocity fields of water were visualized for a time resolution of 500 us and a spatial resolution of 2.2 x 2.2 um. Transient micro vortices at the water-butyl acetate interface were captured clearly.

  13. High-speed detector for time-resolved diffraction studies

    PubMed Central

    Singh, Bipin; Miller, Stuart R.; Bhandari, Harish B.; Graceffa, Rita; Irving, Thomas C.; Nagarkar, Vivek V.

    2013-01-01

    There are a growing number of high brightness synchrotron sources that require high-frame-rate detectors to provide the time-scales required for performing time-resolved diffraction experiments. We report on the development of a very high frame rate CMOS X-ray detector for time-resolved muscle diffraction and time-resolved solution scattering experiments. The detector is based on a low-afterglow scintillator, provides a megapixel resolution with frame rates of up to 120,000 frames per second, an effective pixel size of 64 µm, and can be adapted for various X-ray energies. The paper describes the detector design and initial results of time-resolved diffraction experiments on a synchrotron beamline. PMID:24489595

  14. High Speed Sonar Array Depressor Program

    DTIC Science & Technology

    1981-11-30

    were conducted in the Exuma Sound In August 1981. 33 Report 12482 1000 4000 z 3000 2000 - 500 1000 0 1I 0 0 5 10 15 20 25 30 SPEED-KNOTS 700 1:11 IS z...the ONR Sea Trial 1A6 on the R/V ATHENA. The depressor was deployed during that portion of the trials occuring on 5, 6, 7 and 8 August 1981 in Exuma ...Before the Exuma Sound runs the bolt holes in tVe depressor were permanently plugged and faired. From then on no relation was seen between the sign

  15. Spontaneous sidebanding in high speed rotordynamics

    NASA Astrophysics Data System (ADS)

    Ehrich, F. F.

    1992-10-01

    It is noted that the spontaneous sideband spacing frequency seems to be a whole number fraction (1/J) of the operating speed which indicates that the wave form is periodic and completes a full cycle every J rotations of the rotor. Employing a numerical model of a rotor that simulates local contact with a stator in close proximity as a bilinear spring, studies have been conducted to explore the circumstances for this spontaneous sidebanding. Two general classes of this type of response are determined in a system that is effectively single-degree-of-freedom.

  16. High speed all-optical networks

    NASA Technical Reports Server (NTRS)

    Chlamtac, Imrich

    1993-01-01

    An inherent problem of conventional point-to-point WAN architectures is that they cannot translate optical transmission bandwidth into comparable user available throughput due to the limiting electronic processing speed of the switching nodes. This report presents the first solution to WDM based WAN networks that overcomes this limitation. The proposed Lightnet architecture takes into account the idiosyncrasies of WDM switching/transmission leading to an efficient and pragmatic solution. The Lightnet architecture trades the ample WDM bandwidth for a reduction in the number of processing stages and a simplification of each switching stage, leading to drastically increased effective network throughputs.

  17. Final Report and Documentation for the Optical Backplane/Interconnect for High Speed Communication LDRD

    SciTech Connect

    ROBERTSON, PERRY J.; CHEN, HELEN Y.; BRANDT, JAMES M.; SULLIVAN, CHARLES T.; PIERSON, LYNDON G.; WITZKE, EDWARD L.; GASS, KARL

    2001-03-01

    Current copper backplane technology has reached the technical limits of clock speed and width for systems requiring multiple boards. Currently, bus technology such as VME and PCI (types of buses) will face severe limitations are the bus speed approaches 100 MHz. At this speed, the physical length limit of an unterminated bus is barely three inches. Terminating the bus enables much higher clock rates but at drastically higher power cost. Sandia has developed high bandwidth parallel optical interconnects that can provide over 40 Gbps throughput between circuit boards in a system. Based on Sandia's unique VCSEL (Vertical Cavity Surface Emitting Laser) technology, these devices are compatible with CMOS (Complementary Metal Oxide Semiconductor) chips and have single channel bandwidth in excess of 20 GHz. In this project, we are researching the use of this interconnect scheme as the physical layer of a greater ATM (Asynchronous Transfer Mode) based backplane. There are several advantages to this technology including small board space, lower power and non-contact communication. This technology is also easily expandable to meet future bandwidth requirements in excess of 160 Gbps sometimes referred to as UTOPIA 6. ATM over optical backplane will enable automatic switching of wide high-speed circuits between boards in a system. In the first year we developed integrated VCSELs and receivers, identified fiber ribbon based interconnect scheme and a high level architecture. In the second year, we implemented the physical layer in the form of a PCI computer peripheral card. A description of future work including super computer networking deployment and protocol processing is included.

  18. Nonparametric analysis of high wind speed data

    NASA Astrophysics Data System (ADS)

    Francisco-Fernández, Mario; Quintela-del-Río, Alejandro

    2013-01-01

    In this paper, nonparametric curve estimation methods are applied to analyze time series of wind speeds, focusing on the extreme events exceeding a chosen threshold. Classical parametric statistical approaches in this context consist in fitting a generalized Pareto distribution (GPD) to the tail of the empirical cumulative distribution, using maximum likelihood or the method of the moments to estimate the parameters of this distribution. Additionally, confidence intervals are usually computed to assess the uncertainty of the estimates. Nonparametric methods to estimate directly some quantities of interest, such as the probability of exceedance, the quantiles or return levels, or the return periods, are proposed. Moreover, bootstrap techniques are used to develop pointwise and simultaneous confidence intervals for these functions. The proposed models are applied to wind speed data in the Gulf Coast of US, comparing the results with those using the GPD approach, by means of a split-sample test. Results show that nonparametric methods are competitive with respect to the standard GPD approximations. The study is completed generating synthetic data sets and comparing the behavior of the parametric and the nonparametric estimates in this framework.

  19. High-Speed Tests of Radial-Engine Cowlings

    NASA Technical Reports Server (NTRS)

    Robinson, Russell G.; Becker, John V.

    1939-01-01

    The drag characteristics of eight radial-engine cowlings have been determined over a wide speed range in the N.A.C.A. 8-foot high-speed wind tunnel. The pressure distribution over all cowlings was measured, to and above the speed of the compressibility burble, as an aid in interpreting the force tests. One-fifth-scale models of radial-engine cowlings on a wing-nacelle combination mere used in the tests.

  20. High-speed OCT light sources and systems [Invited

    PubMed Central

    Klein, Thomas; Huber, Robert

    2017-01-01

    Imaging speed is one of the most important parameters that define the performance of optical coherence tomography (OCT) systems. During the last two decades, OCT speed has increased by over three orders of magnitude. New developments in wavelength-swept lasers have repeatedly been crucial for this development. In this review, we discuss the historical evolution and current state of the art of high-speed OCT systems, with focus on wavelength swept light sources and swept source OCT systems. PMID:28270988