high-performance microprocessor design: Topics by Science.gov

Sample records for high-performance microprocessor design

Small Microprocessor for ASIC or FPGA Implementation

NASA Technical Reports Server (NTRS)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.
Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

DTIC Science & Technology

2015-03-10

for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...P.O. Box 12211 Research Triangle Park, NC 27709-2211 Superconductor technology, RSFQ, RQL, processor design, arithmetic units, high-performance...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation
High-speed microprocessor characterization. Final report/project accomplishments summary, CRADA Number KCP-94-1004

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brown, L.W.

The objective of the project was to characterize and document the critical operating parameters of an 0.8-micron, 350-MHz, 32-bit microprocessor prototype. The roles of FM and T and the participant company were: FM and T -- evaluation performance of the prototype 32-bit microprocessor using the IDS5000 and Tektronix S3260 Integrated Circuit Test System; Corda -- design and build the prototype microprocessor. This project was terminated with nearly all of the planned activities unaddressed.
Innovative architectures for dense multi-microprocessor computers

NASA Technical Reports Server (NTRS)

Larson, Robert E.

1989-01-01

The purpose is to summarize a Phase 1 SBIR project performed for the NASA/Langley Computational Structural Mechanics Group. The project was performed from February to August 1987. The main objectives of the project were to: (1) expand upon previous research into the application of chordal ring architectures to the general problem of designing multi-microcomputer architectures, (2) attempt to identify a family of chordal rings such that each chordal ring can be simply expanded to produce the next member of the family, (3) perform a preliminary, high-level design of an expandable multi-microprocessor computer based upon chordal rings, (4) analyze the potential use of chordal ring based multi-microprocessors for sparse matrix problems and other applications arising in computational structural mechanics.
Importance of balanced architectures in the design of high-performance imaging systems

NASA Astrophysics Data System (ADS)

Sgro, Joseph A.; Stanton, Paul C.

1999-03-01

Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.
Gallium-arsenide process evaluation based on a RISC microprocessor example

NASA Astrophysics Data System (ADS)

Brown, Richard B.; Upton, Michael; Chandna, Ajay; Huff, Thomas R.; Mudge, Trevor N.; Oettel, Richard E.

1993-10-01

This work evaluates the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivity of the microprocessor and other large circuit blocks to different process parameters is analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance.
A microprocessor based high speed packet switch for satellite communications

NASA Technical Reports Server (NTRS)

Arozullah, M.; Crist, S. C.

1980-01-01

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.
Real-time fetal ECG system design using embedded microprocessors

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.
Using benchmarks for radiation testing of microprocessors and FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Robinson, William H.; Rech, Paolo

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less
Using benchmarks for radiation testing of microprocessors and FPGAs

DOE PAGES

Quinn, Heather; Robinson, William H.; Rech, Paolo; ...

2015-12-17

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less
A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.
Temperature and leakage aware techniques to improve cache reliability

NASA Astrophysics Data System (ADS)

Akaaboune, Adil

Decreasing power consumption in small devices such as handhelds, cell phones and high-performance processors is now one of the most critical design concerns. On-chip cache memories dominate the chip area in microprocessors and thus arises the need for power efficient cache memories. Cache is the simplest cost effective method to attain high speed memory hierarchy and, its performance is extremely critical for high speed computers. Cache is used by the microprocessor for channeling the performance gap between processor and main memory (RAM) hence the memory bandwidth is frequently a bottleneck which can affect the peak throughput significantly. In the design of any cache system, the tradeoffs of area/cost, performance, power consumption, and thermal management must be taken into consideration. Previous work has mainly concentrated on performance and area/cost constraints. More recent works have focused on low power design especially for portable devices and media-processing systems, however fewer research has been done on the relationship between heat management, Leakage power and cost per die. Lately, the focus of power dissipation in the new generations of microprocessors has shifted from dynamic power to idle power, a previously underestimated form of power loss that causes battery charge to drain and shutdown too early due the waste of energy. The problem has been aggravated by the aggressive scaling of process; device level method used originally by designers to enhance performance, conserve dissipation and reduces the sizes of digital circuits that are increasingly condensed. This dissertation studies the impact of hotspots, in the cache memory, on leakage consumption and microprocessor reliability and durability. The work will first prove that by eliminating hotspots in the cache memory, leakage power will be reduced and therefore, the reliability will be improved. The second technique studied is data quality management that improves the quality of the data stored in the cache to reduce power consumption. The initial work done on this subject focuses on the type of data that increases leakage consumption and ways to manage without impacting the performance of the microprocessor. The second phase of the project focuses on managing the data storage in different blocks of the cache to smooth the leakage power as well as dynamic power consumption. The last technique is a voltage controlled cache to reduce the leakage consumption of the cache while in execution and even in idle state. Two blocks of the 4-way set associative cache go through a voltage regulator before getting to the voltage well, and the other two are directly connected to the voltage well. The idea behind this technique is to use the replacement algorithm information to increase or decrease voltage of the two blocks depending on the need of the information stored on them.
Designs and performance of three new microprocessor-controlled knee joints.

PubMed

Thiele, Julius; Schöllig, Christina; Bellmann, Malte; Kraft, Marc

2018-02-09

A crossover design study with a small group of subjects was used to evaluate the performance of three microprocessor-controlled exoprosthetic knee joints (MPKs): C-Leg 4, Plié 3 and Rheo Knee 3. Given that the mechanical designs and control algorithms of the joints determine the user outcome, the influence of these inherent differences on the functional characteristics was investigated in this study. The knee joints were evaluated during level-ground walking at different velocities in a motion analysis laboratory. Additionally, technical analyses using patents, technical documentations and X-ray computed tomography (CT) for each knee joint were performed. The technical analyses showed that only C-Leg 4 and Rheo Knee 3 allow microprocessor-controlled adaptation of the joint resistances for different gait velocities. Furthermore, Plié 3 is not able to provide stance extension damping. The biomechanical results showed that only if a knee joint adapts flexion and extension resistances by the microprocessor all known advantages of MPKs can become apparent. But not all users may benefit from the examined functions: e.g. a good accommodation to fast walking speeds or comfortable stance phase flexion. Hence, a detailed comparison of user demands and performance of the designated knee joint is mandatory to ensure a maximum in user outcome.
Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.
A microprocessor based on a two-dimensional semiconductor.

PubMed

Wachter, Stefan; Polyushkin, Dmitry K; Bethge, Ole; Mueller, Thomas

2017-04-11

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.
A microprocessor based on a two-dimensional semiconductor

NASA Astrophysics Data System (ADS)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.
Enhancement of a prosthetic knee with a microprocessor-controlled gait phase switch reduces falls and improves balance confidence and gait speed in community ambulators with unilateral transfemoral amputation.

PubMed

Fuenzalida Squella, Sara Agueda; Kannenberg, Andreas; Brandão Benetti, Ângelo

2018-04-01

Despite the evidence for improved safety and function of microprocessor stance and swing-controlled prosthetic knees, non-microprocessor-controlled prosthetic knees are still standard of care for persons with transfemoral amputations in most countries. Limited feature microprocessor-control enhancement of such knees could stand to significantly improve patient outcomes. To evaluate gait speed, balance, and fall reduction benefits of the new 3E80 default stance hydraulic knee compared to standard non-microprocessor-controlled prosthetic knees. Comparative within-subject clinical study. A total of 13 young, high-functioning community ambulators with a transfemoral amputation underwent assessment of performance-based (e.g. 2-min walk test, timed ramp/stair tests) and self-reported (e.g. falls, Activities-Specific Balance Confidence scale, Prosthesis Evaluation Questionnaire question #1, Satisfaction with the Prosthesis) outcome measures for their non-microprocessor-controlled prosthetic knees and again after 8 weeks of accommodation to the 3E80 microprocessor-enhanced knee. Self-reported falls significantly declined 77% ( p = .04), Activities-Specific Balance Confidence scores improved 12 points ( p = .005), 2-min walk test walking distance increased 20 m on level ( p = .01) and uneven ( p = .045) terrain, and patient satisfaction significantly improved ( p < .01) when using the 3E80 knee. Slope and stair ambulation performance did not differ between knee conditions. The 3E80 knee reduced self-reported fall incidents and improved balance confidence. Walking performance on both level and uneven terrains also improved compared to non-microprocessor-controlled prosthetic knees. Subjects' satisfaction was significantly higher than with their previous non-microprocessor-controlled prosthetic knees. The 3E80 may be considered a prosthetic option for improving gait performance, balance confidence, and safety in highly active amputees. Clinical relevance This study compared performance-based and self-reported outcome measures when using non-microprocessor and a new microprocessor-enhanced, default stance rotary hydraulic knee. The results inform rehabilitation professionals about the functional benefits of a limited-feature, microprocessor-enhanced hydraulic prosthetic knee over standard non-microprocessor-controlled prosthetic knees.
Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.
Functional added value of microprocessor-controlled knee joints in daily life performance of Medicare Functional Classification Level-2 amputees.

PubMed

Theeven, Patrick; Hemmen, Bea; Rings, Frans; Meys, Guido; Brink, Peter; Smeets, Rob; Seelen, Henk

2011-10-01

To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. Randomised cross-over trial. Forty-one persons with unilateral above-knee or knee disarticulation limb loss, classified as Medicare Functional Classification Level-2 (MFCL-2). Participants were measured in 3 conditions, i.e. using a mechanically controlled knee joint and two types of microprocessor-controlled prosthetic knee joints. Functional performance level was assessed using a test in which participants performed 17 simulated activities of daily living (Assessment of Daily Activity Performance in Transfemoral amputees test). Performance time was measured and self-perceived level of difficulty was scored on a visual analogue scale for each activity. High levels of within-group variability in functional performance obscured detection of any effects of using a microprocessor-controlled prosthetic knee joint. Data analysis after stratification of the participants into 3 subgroups, i.e. participants with a "low", "intermediate" and "high" functional mobility level, showed that the two higher functional subgroups performed significantly faster using microprocessor-controlled prosthetic knee joints. MFCL-2 amputees constitute a heterogeneous patient group with large variation in functional performance levels. A substantial part of this group seems to benefit from using a microprocessor-controlled prosthetic knee joint when performing activities of daily living.
Fiber optic, Fabry-Perot high temperature sensor

NASA Technical Reports Server (NTRS)

James, K.; Quick, B.

1984-01-01

A digital, fiber optic temperature sensor using a variable Fabry-Perot cavity as the sensor element was analyzed, designed, fabricated, and tested. The fiber transmitted cavity reflection spectra is dispersed then converted from an optical signal to electrical information by a charged coupled device (CCD). A microprocessor-based color demodulation system converts the wavelength information to temperature. This general sensor concept not only utilizes an all-optical means of parameter sensing and transmitting, but also exploits microprocessor technology for automated control, calibration, and enhanced performance. The complete temperature sensor system was evaluated in the laboratory. Results show that the Fabry-Perot temperature sensor has good resolution (0.5% of full seale), high accuracy, and potential high temperature ( 1000 C) applications.

Scaling theory for information networks.

PubMed

Moses, Melanie E; Forrest, Stephanie; Davis, Alan L; Lodder, Mike A; Brown, James H

2008-12-06

Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.
Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luo, Y.; Cameron, K.W.

1998-11-24

Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators,more » which have substantial constraints especially on large-scale scientific computing applications. This paper presents a new technique of characterizing applications at the instruction level using hardware performance counters. It has the advantage of collecting instruction-level characteristics in a few runs virtually without overhead or slowdown. A variety of instruction counts can be utilized to calculate some average abstract workload parameters corresponding to microprocessor pipelines or functional units. Based on the microprocessor architectural constraints and these calculated abstract parameters, the architectural performance bottleneck for a specific application can be estimated. In particular, the analysis results can provide some insight to the problem that only a small percentage of processor peak performance can be achieved even for many very cache-friendly codes. Meanwhile, the bottleneck estimation can provide suggestions about viable architectural/functional improvement for certain workloads. Eventually, these abstract parameters can lead to the creation of an analytical microprocessor pipeline model and memory hierarchy model.« less
A microprocessor based on a two-dimensional semiconductor

PubMed Central

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-01-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III–V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor—molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material. PMID:28398336
JPRS Report, Science & Technology, China, High-Performance Computer Systems

DTIC Science & Technology

1992-10-28

microprocessor array The microprocessor array in the AP85 system is com- posed of 16 completely identical array element micro - processors . Each array element...microprocessors and capable of host machine reading and writing. The memory capacity of the array element micro - processors as a whole can be expanded...transmission functions to carry out data transmission from array element micro - processor to array element microprocessor, from array element
Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.
Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.
Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

NASA Technical Reports Server (NTRS)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.
OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.
Evaluation of function, performance, and preference as transfemoral amputees transition from mechanical to microprocessor control of the prosthetic knee.

PubMed

Hafner, Brian J; Willingham, Laura L; Buell, Noelle C; Allyn, Katheryn J; Smith, Douglas G

2007-02-01

To evaluate differences in function, performance, and preference between mechanical and microprocessor prosthetic knee control technologies. A-B-A-B reversal design. Home, community, and laboratory environments. Twenty-one unilateral, transfemoral amputees. Mechanical control prosthetic knee versus microprocessor control prosthetic knee (Otto Bock C-Leg). Stair rating, hill rating and time, obstacle course time, divided attention task accuracy and time, Amputee Mobility Predictor score, step activity, Prosthesis Evaluation Questionnaire score, Medical Outcomes Study 36-Item Short-Form Health Survey score, self-reported frequency of stumbles and falls, and self-reported concentration required for ambulation. Stair descent score, hill descent time, and hill sound-side step length showed significant (P<.01) improvement with the C-Leg. Users reported a significant (P<.05) decrease in frequency of stumbles and falls, frustration with falling, and difficulty in multitasking while using the microprocessor knee. Subject satisfaction with the C-Leg was significantly (P<.001) greater than the mechanical control prosthesis. The study population showed improved performance when negotiating stairs and hills, reduced frequency of stumbling and falling, and a preference for the microprocessor control C-Leg as compared with the mechanical control prosthetic knee.
A Report of Bethune-Cookman College NASA JOVE Projects

NASA Technical Reports Server (NTRS)

Agba, Lawrence C.; David, Sunil K.; Rao, Narsing G.; Rahmani, Munir A.

1997-01-01

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.
Achieving High Performance on the i860 Microprocessor

NASA Technical Reports Server (NTRS)

Lee, King; Kutler, Paul (Technical Monitor)

1998-01-01

The i860 is a high performance microprocessor used in the Intel Touchstone project. This paper proposes a paradigm for programming the i860 that is modelled on the vector instructions of the Cray computers. Fortran callable assembler subroutines were written that mimic the concurrent vector instructions of the Cray. Cache takes the place of vector registers. Using this paradigm we have achieved twice the performance of compiled code on a traditional solve.
Special purpose parallel computer architecture for real-time control and simulation in robotic applications

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1993-01-01

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.
A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.
A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.
A microprocessor-based position control system for a telescope secondary mirror

NASA Technical Reports Server (NTRS)

Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

1983-01-01

The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.
Microprocessor design for GaAs technology

NASA Astrophysics Data System (ADS)

Milutinovic, Veljko M.

Recent advances in the design of GaAs microprocessor chips are examined in chapters contributed by leading experts; the work is intended as reading material for a graduate engineering course or as a practical R&D reference. Topics addressed include the methodology used for the architecture, organization, and design of GaAs processors; GaAs device physics and circuit design; design concepts for microprocessor-based GaAs systems; a 32-bit GaAs microprocessor; a 32-bit processor implemented in GaAs JFET; and a direct coupled-FET-logic E/D-MESFET experimental RISC machine. Drawings, micrographs, and extensive circuit diagrams are provided.
Gait and balance of transfemoral amputees using passive mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, K R; Levine, J A; Brey, R H; Iverson, B K; McCrady, S K; Padgett, D J; Joyner, M J

2007-10-01

Microprocessor-controlled knee joints appeared on the market a decade ago. These joints are more sophisticated and more expensive than mechanical ones. The literature is contradictory regarding changes in gait and balance when using these sophisticated devices. This study employed a crossover design to assess the comparative performance of a passive mechanical knee prosthesis compared to a microprocessor-controlled knee joint in 15 subjects with an above-knee amputation. Objective measurements of gait and balance were obtained. Subjects demonstrated significantly improved gait characteristics after receiving the microprocessor-controlled prosthetic knee joint (p<0.01). Improvements in gait were a transition from a hyperextended knee to a flexed knee during loading response which resulted in a change from an internal knee flexor moment to a knee extensor moment. The participants' balance also improved (p<0.01). All conditions of the Sensory Organization Test (SOT) demonstrated improvements in equilibrium score. The composite score also increased. Transfemoral amputees using a microprocessor-controlled knee have significant improvements in gait and balance.
Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

ERIC Educational Resources Information Center

Pittsburgh Univ., PA. Dept. of Electrical Engineering.

Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…
Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.

1977-01-01

The feasibility of performing the same task in real time using microprocessor technology was determined. The least square algorithm was implemented on an Intel 8080 microprocessor. Results indicated that a microprocessor could easily match the IBM implementation in accuracy and be performed inside the time limitations set.
Formal Verification of the AAMP-FV Microcode

NASA Technical Reports Server (NTRS)

Miller, Steven P.; Greve, David A.; Wilding, Matthew M.; Srivas, Mandayam

1999-01-01

This report describes the experiences of Collins Avionics & Communications and SRI International in formally specifying and verifying the microcode in a Rockwell proprietary microprocessor, the AAMP-FV, using the PVS verification system. This project built extensively on earlier experiences using PVS to verify the microcode in the AAMP5, a complex, pipelined microprocessor designed for use in avionics displays and global positioning systems. While the AAMP5 experiment demonstrated the technical feasibility of formal verification of microcode, the steep learning curve encountered left unanswered the question of whether it could be performed at reasonable cost. The AAMP-FV project was conducted to determine whether the experience gained on the AAMP5 project could be used to make formal verification of microcode cost effective for safety-critical and high volume devices.

Microprocessor tester for the treat upgrade reactor trip system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lenkszus, F.R.; Bucher, R.G.

1984-01-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety systemmore » is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations.« less
Cellular functions of the microprocessor.

PubMed

Macias, Sara; Cordiner, Ross A; Cáceres, Javier F

2013-08-01

The microprocessor is a complex comprising the RNase III enzyme Drosha and the double-stranded RNA-binding protein DGCR8 (DiGeorge syndrome critical region 8 gene) that catalyses the nuclear step of miRNA (microRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as an endonuclease. Recent global analyses of microprocessor and Dicer proteins have suggested novel functions for these components independent of their role in miRNA biogenesis. A HITS-CLIP (high-throughput sequencing of RNA isolated by cross-linking immunoprecipitation) experiment designed to identify novel substrates of the microprocessor revealed that this complex binds and regulates a large variety of cellular RNAs. The microprocessor-mediated cleavage of several classes of RNAs not only regulates transcript levels, but also modulates alternative splicing events, independently of miRNA function. Importantly, DGCR8 can also associate with other nucleases, suggesting the existence of alternative DGCR8 complexes that may regulate the fate of a subset of cellular RNAs. The aim of the present review is to provide an overview of the diverse functional roles of the microprocessor.
High Performance Parallel Computational Nanotechnology

NASA Technical Reports Server (NTRS)

Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.
Robust Duplication with Comparison Methods in Microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less
Robust Duplication with Comparison Methods in Microcontrollers

DOE PAGES

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.; ...

2016-01-01

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less
Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

NASA Technical Reports Server (NTRS)

Darcy, Eric; Davies, Frank

2009-01-01

Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.
A microprocessor application to a strapdown laser gyro navigator

NASA Technical Reports Server (NTRS)

Giardina, C.; Luxford, E.

1980-01-01

The replacement of analog circuit control loops for laser gyros (path length control, cross axis temperature compensation loops, dither servo and current regulators) with digital filters residing in microcomputers is addressed. In addition to the control loops, a discussion is given on applying the microprocessor hardware to compensation for coning and skulling motion where simple algorithms are processed at high speeds to compensate component output data (digital pulses) for linear and angular vibration motions. Highlights are given on the methodology and system approaches used in replacing differential equations describing the analog system in terms of the mechanized difference equations of the microprocessor. Standard one for one frequency domain techniques are employed in replacing analog transfer functions by their transform counterparts. Direct digital design techniques are also discussed along with their associated benefits. Time and memory loading analyses are also summarized, as well as signal and microprocessor architecture. Trade offs in algorithm, mechanization, time/memory loading, accuracy, and microprocessor architecture are also given.
Feasibility study of a microprocessor based oculometer system

NASA Technical Reports Server (NTRS)

Varanasi, M. R.

1981-01-01

The elimination of redundancy in data to maximize processing speed and minimize storage requirements were objectives in a feasibility study of a microprocessor based oculometer system that would be portable in size and flexible in use. The appropriate architectural design of the signal processor, improved optics, and the reduction of size, weight, and power to the system were investigated. A flow chart is presented showing the strategy of the design. The simulation for developing microroutines for the high speed algorithmic processor subsystem is discussed as well as the Karhunen-Loeve transform technique for data compression.
Development of a fault-tolerant microprocessor based computer system for space flight

NASA Technical Reports Server (NTRS)

Montgomery, V. T.

1981-01-01

A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.
Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.
Microprocessor realizations of range rate filters

NASA Technical Reports Server (NTRS)

1979-01-01

The performance of five digital range rate filters is evaluated. A range rate filter receives an input of range data from a radar unit and produces an output of smoothed range data and its estimated derivative range rate. The filters are compared through simulation on an IBM 370. Two of the filter designs are implemented on a 6800 microprocessor-based system. Comparisons are made on the bases of noise variance reduction ratios and convergence times of the filters in response to simulated range signals.
The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

DTIC Science & Technology

2017-09-01

parallel, randomized, controlled clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power, will...Department of the Army position, policy or decision unless so designated by other documentation. CONTRACTING ORGANIZATION: University of Tennessee
The design of a microprocessor-based data logger

USGS Publications Warehouse

Leap, K.J.; Dedini, L.A.

1982-01-01

The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.
Deepthi Vaidhynathan | NREL

Science.gov Websites

Complex Systems Simulation and Optimization Group on performance analysis and benchmarking latest . Research Interests High Performance Computing|Embedded System |Microprocessors & Microcontrollers
A survey of the state of the art and focused research in range systems, task 2

NASA Technical Reports Server (NTRS)

Yao, K.

1986-01-01

Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems.
Microprocessor-based control systems application in nuclear power plant critical systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shah, M.R.; Nowak, J.B.

Microprocessor-based control systems have been used in fossil power plants and are receiving greater acceptance for application in nuclear plants. This technology is not new but it does require unique considerations when applied to nuclear power plants. Sargent and Lundy (S and L) has used a microprocessor-based component logic control system (interposing Logic System) for safety- and non-safety-related components in nuclear power plants under construction overseas. Currently, S and L is in the design stage to replace an existing analog control system with a microprocessor-based control system in the U.S. The trend in the industry is to replace systems inmore » existing plants or design new power plants with microprocessor-based control systems.« less
Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730
On the Floating Point Performance of the i860 Microprocessor

NASA Technical Reports Server (NTRS)

Lee, King; Kutler, Paul (Technical Monitor)

1997-01-01

The i860 microprocessor is a pipelined processor that can deliver two double precision floating point results every clock. It is being used in the Touchstone project to develop a teraflop computer by the year 2000. With such high computational capabilities it was expected that memory bandwidth would limit performance on many kernels. Measured performance of three kernels showed performance is less than what memory bandwidth limitations would predict. This paper develops a model that explains the discrepancy in terms of memory latencies and points to some problems involved in moving data from memory to the arithmetic pipelines.
Human supervision and microprocessor control of an optical tracking system

NASA Technical Reports Server (NTRS)

Bigley, W. J.; Vandenberg, J. D.

1981-01-01

Gunners using small calibre anti-aircraft systems have not been able to track high-speed air targets effectively. Substantial improvement in the accuracy of surface fire against attacking aircraft has been realized through the design of a director-type weapon control system. This system concept frees the gunner to exercise a supervisory/monitoring role while the computer takes over continuous target tracking. This change capitalizes on a key consideration of human factors engineering while increasing system accuracy. The advanced system design, which uses distributed microprocessor control, is discussed at the block diagram level and is contrasted with the previous implementation.
A methodology based on reduced complexity algorithm for system applications using microprocessors

NASA Technical Reports Server (NTRS)

Yan, T. Y.; Yao, K.

1988-01-01

The paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.
High performance flight computer developed for deep space applications

NASA Technical Reports Server (NTRS)

Bunker, Robert L.

1993-01-01

The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.
Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.
Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

NASA Technical Reports Server (NTRS)

Bickford, Mark; Srivas, Mandayam

1991-01-01

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.
PDSparc: A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-09-24

Kate Thurmer MIT Lincoln Laboratory, Lexington, MA, USA Distribution A: Public Release ABSTRACT Microprocessors are the...enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors usually start...out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small
Performance tuning of N-body codes on modern microprocessors: I. Direct integration with a hermite scheme on x86_64 architecture

NASA Astrophysics Data System (ADS)

Nitadori, Keigo; Makino, Junichiro; Hut, Piet

2006-12-01

The main performance bottleneck of gravitational N-body codes is the force calculation between two particles. We have succeeded in speeding up this pair-wise force calculation by factors between 2 and 10, depending on the code and the processor on which the code is run. These speed-ups were obtained by writing highly fine-tuned code for x86_64 microprocessors. Any existing N-body code, running on these chips, can easily incorporate our assembly code programs. In the current paper, we present an outline of our overall approach, which we illustrate with one specific example: the use of a Hermite scheme for a direct N2 type integration on a single 2.0 GHz Athlon 64 processor, for which we obtain an effective performance of 4.05 Gflops, for double-precision accuracy. In subsequent papers, we will discuss other variations, including the combinations of N log N codes, single-precision implementations, and performance on other microprocessors.
A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

NASA Technical Reports Server (NTRS)

Braswell, F. M.

1981-01-01

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.
Designs and performance of microprocessor-controlled knee joints.

PubMed

Thiele, Julius; Westebbe, Bettina; Bellmann, Malte; Kraft, Marc

2014-02-01

In this comparative study, three transfemoral amputee subjects were fitted with four different microprocessor-controlled exoprosthetic knee joints (MPK): C-Leg, Orion, Plié2.0, and Rel-K. In a motion analysis laboratory, objective gait measures were acquired during level walking at different velocities. Subsequent technical analyses, which involved X-ray computed tomography, identified the functional mechanisms of each device and enabled corroboration of the performance in the gait laboratory by the engineering design of the MPK. Gait measures showed that the mean increase of the maximum knee flexion angle at different walking velocities was closest in value to the unaffected contralateral knee (6.2°/m/s) with C-Leg (3.5°/m/s; Rel-K 17.0°/m/s, Orion 18.3°/m/s, and Plié2.0 28.1°/m/s). Technical analyses corroborated that only with Plié2.0 the flexion resistances were not regulated by microprocessor control at different walking velocities. The muscular effort for the initiation of the swing phase, measured by the minimum hip moment, was found to be lowest with C-Leg (-82.1±14.1 Nm; Rel-K -83.59±17.8 Nm, Orion -88.0±16.3 Nm, and Plié2.0 -91.6±16.5 Nm). Reaching the extension stop at the end of swing phase was reliably executed with both Plié2.0 and C-Leg. Abrupt terminal stance phase extension observed with Plié2.0 and Rel-K could be attributed to the absence of microprocessor control of extension resistance.
A car theft deterrent system research based on ARM9

NASA Astrophysics Data System (ADS)

Zhang, Kaisheng; Liu, Jinhao; Fan, Lijun

2009-07-01

The traditional automotive burglarproof systems commonly only rely on the simple remote control to security which measures are not perfect and functions are too single. With the development of society, people tend to concern on the fingerprint recognition technology, GSM /GPRS wireless transmission technology, the idea of ARM9-based design of automobile burglarproof system is dependent on both of them. The S3C2410 microprocessor embedded system is used in this system, which is illuminated the idea of the control system design through the hardware and software. The spot use indicates that the high control precision, steady performance and the humanistic rational design of automotive burglarproof system.
G-cueing microcontroller (a microprocessor application in simulators)

NASA Technical Reports Server (NTRS)

Horattas, C. G.

1980-01-01

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.
Energy and time determine scaling in biological and computer designs

PubMed Central

Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

2016-01-01

Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy–time minimization principle may govern the design of many complex systems that process energy, materials and information. This article is part of the themed issue ‘The major synthetic evolutionary transitions’. PMID:27431524
Energy and time determine scaling in biological and computer designs.

PubMed

Moses, Melanie; Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

2016-08-19

Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy-time minimization principle may govern the design of many complex systems that process energy, materials and information.This article is part of the themed issue 'The major synthetic evolutionary transitions'. © 2016 The Author(s).
Formal verification of an avionics microprocessor

NASA Technical Reports Server (NTRS)

Srivas, Mandayam, K.; Miller, Steven P.

1995-01-01

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.
Anti-Hassle Chip

NASA Technical Reports Server (NTRS)

1998-01-01

With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.
PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-08-18

Written Using Synopsys Processor Designer1 David Whelihan, Ph.D. and Kate Thurmer MIT Lincoln Laboratory, Lexington, MA, USA ABSTRACT Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its
Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.
A 32-bit NMOS microprocessor with a large register file

NASA Astrophysics Data System (ADS)

Sherburne, R. W., Jr.; Katevenis, M. G. H.; Patterson, D. A.; Sequin, C. H.

1984-10-01

Two scaled versions of a 32-bit NMOS reduced instruction set computer CPU, called RISC II, have been implemented on two different processing lines using the simple Mead and Conway layout rules with lambda values of 2 and 1.5 microns (corresponding to drawn gate lengths of 4 and 3 microns), respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.
Microprocessor control of a wind turbine generator

NASA Technical Reports Server (NTRS)

Gnecco, A. J.; Whitehead, G. T.

1978-01-01

A microprocessor based system was used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.
A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

1997-01-01

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.
Design Method of Digital Optimal Control Scheme and Multiple Paralleled Bridge Type Current Amplifier for Generating Gradient Magnetic Fields in MRI Systems

NASA Astrophysics Data System (ADS)

Watanabe, Shuji; Takano, Hiroshi; Fukuda, Hiroya; Hiraki, Eiji; Nakaoka, Mutsuo

This paper deals with a digital control scheme of multiple paralleled high frequency switching current amplifier with four-quadrant chopper for generating gradient magnetic fields in MRI (Magnetic Resonance Imaging) systems. In order to track high precise current pattern in Gradient Coils (GC), the proposal current amplifier cancels the switching current ripples in GC with each other and designed optimum switching gate pulse patterns without influences of the large filter current ripple amplitude. The optimal control implementation and the linear control theory in GC current amplifiers have affinity to each other with excellent characteristics. The digital control system can be realized easily through the digital control implementation, DSPs or microprocessors. Multiple-parallel operational microprocessors realize two or higher paralleled GC current pattern tracking amplifier with optimal control design and excellent results are given for improving the image quality of MRI systems.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Bristol Ridge: A 28-nm $$\\times$$ 86 Performance-Enhanced Microprocessor Through System Power Management

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sundaram, Sriram; Grenat, Aaron; Naffziger, Samuel

Power management techniques can be effective at extracting more performance and energy efficiency out of mature systems on chip (SoCs). For instance, the peak performance of microprocessors is often limited by worst case technology (Vmax), infrastructure (thermal/electrical), and microprocessor usage assumptions. Performance/watt of microprocessors also typically suffers from guard bands associated with the test and binning processes as well as worst case aging/lifetime degradation. Similarly, on multicore processors, shared voltage rails tend to limit the peak performance achievable in low thread count workloads. In this paper, we describe five power management techniques that maximize the per-part performance under the before-mentionedmore » constraints. Using these techniques, we demonstrate a net performance increase of up to 15% depending on the application and TDP of the SoC, implemented on 'Bristol Ridge,' a 28-nm CMOS, dual-core x 86 accelerated processing unit.« less
High Accuracy Investigation of Microwave Absorption in Polymer Electrical Components on Motherboard of Computers

NASA Astrophysics Data System (ADS)

Dašić, P.; Hutanu, C.; Jevremović, V.; Dobra, R.; Risteiu, M.; Ileana, I.

2017-06-01

Electronic operating at high frequencies can have problems with emission of high frequency noise. Once put inside an enclosure, the energy will add in phase at certain frequencies to cause resonances which will hinder the performance of the device. These absorbers are based upon open celled foam impregnated with a carbon coating. It is quite possible that in the near future, microprocessors would be to work on a frequency located in 5 to 10 GHz. In these circumstances it is useful to know how and how much of the electromagnetic field emitted by a microprocessor, it is absorbed by the circuit elements in the immediate vicinity of the microprocessor. The aim of this contribution is to demonstrate throughout high-level experimental analysis how the main electric parameters of polymer materials, which build the printed circuits and the one of electric capacitors and resistors, depend on the frequencies on which they work from the microwave range.
An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.
Rad-hard computer elements for space applications

NASA Technical Reports Server (NTRS)

Krishnan, G. S.; Longerot, Carl D.; Treece, R. Keith

1993-01-01

Space Hardened CMOS computer elements emulating a commercial microcontroller and microprocessor family have been designed, fabricated, qualified, and delivered for a variety of space programs including NASA's multiple launch International Solar-Terrestrial Physics (ISTP) program, Mars Observer, and government and commercial communication satellites. Design techniques and radiation performance of the 1.25 micron feature size products are described.
Performance, Resources, and Complexity: A Systematic Approach to Microarchitectural Design

DTIC Science & Technology

1989-05-01

Approved: ********************************** Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...Approved for public release; distribution unlimited 13. SUPPLEMENTARY NOTES 14. ABSTRACT VLSI design in general -- microprocessor design in particular...has been treated more like an art than a science in the past. The goal of this thesis is to explain the science of VLSI design to someone who wants
Microprocessor Seminar, phase 2

NASA Technical Reports Server (NTRS)

Scott, W. R.

1977-01-01

Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.
High-speed, automatic controller design considerations for integrating array processor, multi-microprocessor, and host computer system architectures

NASA Technical Reports Server (NTRS)

Jacklin, S. A.; Leyland, J. A.; Warmbrodt, W.

1985-01-01

Modern control systems must typically perform real-time identification and control, as well as coordinate a host of other activities related to user interaction, online graphics, and file management. This paper discusses five global design considerations which are useful to integrate array processor, multimicroprocessor, and host computer system architectures into versatile, high-speed controllers. Such controllers are capable of very high control throughput, and can maintain constant interaction with the nonreal-time or user environment. As an application example, the architecture of a high-speed, closed-loop controller used to actively control helicopter vibration is briefly discussed. Although this system has been designed for use as the controller for real-time rotorcraft dynamics and control studies in a wind tunnel environment, the controller architecture can generally be applied to a wide range of automatic control applications.
A rocket-borne data-manipulation experiment using a microprocessor

NASA Technical Reports Server (NTRS)

Davis, L. L.; Smith, L. G.; Voss, H. D.

1979-01-01

The development of a data-manipulation experiment using a Z-80 microprocessor is described. The instrumentation is included in the payloads of two Nike Apache sounding rockets used in an investigation of energetic particle fluxes. The data from an array of solid-state detectors and an electrostatic analyzer is processed to give the energy spectrum as a function of pitch angle. The experiment performed well in its first flight test: Nike Apache 14.543 was launched from Wallops Island at 2315 EST on 19 June 1978. The system was designed to be easily adaptable to other data-manipulation requirements and some suggestions for further development are included.
Smart motor technology

NASA Technical Reports Server (NTRS)

Packard, D.; Schmitt, D.

1984-01-01

Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.
Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Leventhal, Lance A.

Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…
Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…
Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.
Analysis of EDP performance

NASA Technical Reports Server (NTRS)

1994-01-01

The objective of this contract was the investigation of the potential performance gains that would result from an upgrade of the Space Station Freedom (SSF) Data Management System (DMS) Embedded Data Processor (EDP) '386' design with the Intel Pentium (registered trade-mark of Intel Corp.) '586' microprocessor. The Pentium ('586') is the latest member of the industry standard Intel X86 family of CISC (Complex Instruction Set Computer) microprocessors. This contract was scheduled to run in parallel with an internal IBM Federal Systems Company (FSC) Internal Research and Development (IR&D) task that had the goal to generate a baseline flight design for an upgraded EDP using the Pentium. This final report summarizes the activities performed in support of Contract NAS2-13758. Our plan was to baseline performance analyses and measurements on the latest state-of-the-art commercially available Pentium processor, representative of the proposed space station design, and then phase to an IBM capital funded breadboard version of the flight design (if available from IR&D and Space Station work) for additional evaluation of results. Unfortunately, the phase-over to the flight design breadboard did not take place, since the IBM Data Management System (DMS) for the Space Station Freedom was terminated by NASA before the referenced capital funded EDP breadboard could be completed. The baseline performance analyses and measurements, however, were successfully completed, as planned, on the commercial Pentium hardware. The results of those analyses, evaluations, and measurements are presented in this final report.
Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.
VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.
Programmable data collection platform study

NASA Technical Reports Server (NTRS)

1976-01-01

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.
Virtual Instrument Simulator for CERES

NASA Technical Reports Server (NTRS)

Chapman, John J.

1997-01-01

A benchtop virtual instrument simulator for CERES (Clouds and the Earth's Radiant Energy System) has been built at NASA, Langley Research Center in Hampton, VA. The CERES instruments will fly on several earth orbiting platforms notably NASDA's Tropical Rainfall Measurement Mission (TRMM) and NASA's Earth Observing System (EOS) satellites. CERES measures top of the atmosphere radiative fluxes using microprocessor controlled scanning radiometers. The CERES Virtual Instrument Simulator consists of electronic circuitry identical to the flight unit's twin microprocessors and telemetry interface to the supporting spacecraft electronics and two personal computers (PC) connected to the I/O ports that control azimuth and elevation gimbals. Software consists of the unmodified TRW developed Flight Code and Ground Support Software which serves as the instrument monitor and NASA/TRW developed engineering models of the scanners. The CERES Instrument Simulator will serve as a testbed for testing of custom instrument commands intended to solve in-flight anomalies of the instruments which could arise during the CERES mission. One of the supporting computers supports the telemetry display which monitors the simulator microprocessors during the development and testing of custom instrument commands. The CERES engineering development software models have been modified to provide a virtual instrument running on a second supporting computer linked in real time to the instrument flight microprocessor control ports. The CERES Instrument Simulator will be used to verify memory uploads by the CERES Flight Operations TEAM at NASA. Plots of the virtual scanner models match the actual instrument scan plots. A high speed logic analyzer has been used to track the performance of the flight microprocessor. The concept of using an identical but non-flight qualified microprocessor and electronics ensemble linked to a virtual instrument with identical system software affords a relatively inexpensive simulation system capable of high fidelity.
A functional language approach in high-speed digital simulation

NASA Technical Reports Server (NTRS)

Ercegovac, M. D.; Lu, S.-L.

1983-01-01

A functional programming approach for a multi-microprocessor architecture is presented. The language, based on Backus FP, its intermediate form and the translation process are discussed and illustrated with an example. The approach allows performance analysis to be performed at a high level as an aid in program partitioning.

Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

PubMed

Nimigan, André S; Gan, Bing Siang

2011-01-01

Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P < .0001). Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.
Multilevel Summation of Electrostatic Potentials Using Graphics Processing Units*

PubMed Central

Hardy, David J.; Stone, John E.; Schulten, Klaus

2009-01-01

Physical and engineering practicalities involved in microprocessor design have resulted in flat performance growth for traditional single-core microprocessors. The urgent need for continuing increases in the performance of scientific applications requires the use of many-core processors and accelerators such as graphics processing units (GPUs). This paper discusses GPU acceleration of the multilevel summation method for computing electrostatic potentials and forces for a system of charged atoms, which is a problem of paramount importance in biomolecular modeling applications. We present and test a new GPU algorithm for the long-range part of the potentials that computes a cutoff pair potential between lattice points, essentially convolving a fixed 3-D lattice of “weights” over all sub-cubes of a much larger lattice. The implementation exploits the different memory subsystems provided on the GPU to stream optimally sized data sets through the multiprocessors. We demonstrate for the full multilevel summation calculation speedups of up to 26 using a single GPU and 46 using multiple GPUs, enabling the computation of a high-resolution map of the electrostatic potential for a system of 1.5 million atoms in under 12 seconds. PMID:20161132
Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen
Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.
The performance of NASA research hydrogen masers

NASA Technical Reports Server (NTRS)

Reinhardt, V. S.; Rueger, L. J.

1980-01-01

Field operable hydrogen masers based on prior maser designs are presented. These units incorporate improvements in magnetic shielding, lower noise electronics, better thermal control, and have a microprocessor for operation, monitoring, and diagnostic functions. They are ruggedly built for transportability and ease of service anywhere in the world.
Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.
Microprocessor Simulation: A Training Technique.

ERIC Educational Resources Information Center

Oscarson, David J.

1982-01-01

Describes the design and application of a microprocessor simulation using BASIC for formal training of technicians and managers and as a management tool. Illustrates the utility of the modular approach for the instruction and practice of decision-making techniques. (SK)
Microeconomics of advanced process window control for 50-nm gates

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.; Chen, Xuemei; Falessi, Georges; Garvin, Craig; Hankinson, Matt; Lev, Amir; Levy, Ady; Slessor, Michael D.

2002-07-01

Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.
Automated mixed traffic transit vehicle microprocessor controller

NASA Technical Reports Server (NTRS)

Marks, R. A.; Cassell, P.; Johnston, A. R.

1981-01-01

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.
Synchronous clock stopper for microprocessor

NASA Technical Reports Server (NTRS)

Kitchin, David A. (Inventor)

1985-01-01

A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.
All-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors

NASA Astrophysics Data System (ADS)

Dunning, Jim; Garcia, Gerald; Lundberg, Jim; Nuckolls, Ed

1995-04-01

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 micron CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4x the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs.
Preliminary design and development of a reflectance spectrometer instrument

NASA Technical Reports Server (NTRS)

Mccord, T. B.

1979-01-01

An improved design for the reflectance spectrometer is described to be used on various terrestrial body missions. These improvements were made on the original Lunar Polar Orbiter design. These include a larger entrance mirror, rectangular aperture, multiple optical beams, spatial resolution, and a bandwidth extension to 5 microns. In addition, detailed electronic designs were produced for a charge amplifier and an amplifier/demodulator/integrator. Design of a microprocessor driven test system was begun. Laboratory tests were performed on a tuning fork chopper.
[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.
Development history of the Hybrid Test Vehicle

NASA Technical Reports Server (NTRS)

Trummel, M. C.; Burke, A. F.

1983-01-01

Phase I of a joint Department of Energy/Jet Propulsion Laboratory Program undertook the development of the Hybrid Test Vehicle (HTV), which has subsequently progressed through design, fabrication, and testing and evaluation phases. Attention is presently given to the design and test experience gained during the HTV development program, and a discussion is presented of the design features and performance capabilities of the various 'mule' vehicles, devoted to the separate development of engine microprocessor control, vehicle structure, and mechanical components, whose elements were incorporated into the final HTV design. Computer projections of the HTV's performance are given.
Integrally regulated solar array demonstration using an Intel 8080 microprocessor

NASA Technical Reports Server (NTRS)

Petrik, E. J.

1977-01-01

A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.
Efficient system interrupt concept design at the microprogramming level

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakharzadeh, M.M.

1989-01-01

Over the past decade the demand for high speed super microcomputers has been tremendously increased. To satisfy this demand many high speed 32-bit microcomputers have been designed. However, the currently available 32-bit systems do not provide an adequate solution to many highly demanding problems such as in multitasking, and in interrupt driven applications, which both require context switching. Systems for these purposes usually incorporate sophisticated software. In order to be efficient, a high end microprocessor based system must satisfy stringent software demands. Although these microprocessors use the latest technology in the fabrication design and run at a very high speed,more » they still suffer from insufficient hardware support for such applications. All too often, this lack also is the premier cause of execution inefficiency. In this dissertation a micro-programmable control unit and operation unit is considered in an advanced design. An automaton controller is designed for high speed micro-level interrupt handling. Different stack models are designed for the single task and multitasking environment. The stacks are used for storage of various components of the processor during the interrupt calls, procedure calls, and task switching. A universal (as an example seven port) register file is designed for high speed parameter passing, and intertask communication in the multitasking environment. In addition, the register file provides a direct path between ALU and the peripheral data which is important in real-time control applications. The overall system is a highly parallel architecture, with no pipeline and internal cache memory, which allows the designer to be able to predict the processor's behavior during the critical times.« less
Energy Expenditure and Activity of Transfemoral Amputees Using Mechanical and Microprocessor-Controlled Prosthetic Knees

PubMed Central

Kaufman, Kenton R.; Levine, James A.; Brey, Robert H.; McCrady, Shelly K.; Padgett, Denny J.; Joyner, Michael J.

2009-01-01

Objective To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Design Repeated-measures design to evaluate comparative functional outcomes. Setting Exercise physiology laboratory and community free-living environment. Participants Subjects (N=15; 12 men, 3 women; age, 42±9y; range, 26 –57y) with transfemoral amputation. Intervention Research participants were long-term users of a mechanical prosthesis (20±10y as an amputee; range, 3–36y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18±8wk) before being retested. Main Outcome Measures Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Results Subjects demonstrated significantly increased physical activity–related energy expenditure levels in the participant’s free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). Conclusions People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life. PMID:18586142
Improved Training Program for Fall Prevention of Warfighters with Lower Extremity Trauma

DTIC Science & Technology

2016-10-01

productive, active civilian life. The training program utilizes a microprocessor -controlled treadmill designed to deliver task- specific training...National Military Medical Center (WRNMMC), and Mayo. The fall prevention training program utilizes a microprocessor -controlled treadmill to deliver
A low cost surface plasmon resonance biosensor using a laser line generator

NASA Astrophysics Data System (ADS)

Chen, Ruipeng; Wang, Manping; Wang, Shun; Liang, Hao; Hu, Xinran; Sun, Xiaohui; Zhu, Juanhua; Ma, Liuzheng; Jiang, Min; Hu, Jiandong; Li, Jianwei

2015-08-01

Due to the instrument designed by using a common surface plasmon resonance biosensor is extremely expensive, we established a portable and cost-effective surface plasmon resonance biosensing system. It is mainly composed of laser line generator, P-polarizer, customized prism, microfluidic cell, and line Charge Coupled Device (CCD) array. Microprocessor PIC24FJ128GA006 with embedded A/D converter, communication interface circuit and photoelectric signal amplifier circuit are used to obtain the weak signals from the biosensing system. Moreover, the line CCD module is checked and optimized on the number of pixels, pixels dimension, output amplifier and the timing diagram. The micro-flow cell is made of stainless steel with a high thermal conductivity, and the microprocessor based Proportional-Integral-Derivative (PID) temperature-controlled algorithm was designed to keep the constant temperature (25 °C) of the sample solutions. Correspondingly, the data algorithms designed especially to this biosensing system including amplitude-limiting filtering algorithm, data normalization and curve plotting were programmed efficiently. To validate the performance of the biosensor, ethanol solution samples at the concentrations of 5%, 7.5%, 10%, 12.5% and 15% in volumetric fractions were used, respectively. The fitting equation ΔRU = - 752987.265 + 570237.348 × RI with the R-Square of 0.97344 was established by delta response units (ΔRUs) to refractive indexes (RI). The maximum relative standard deviation (RSD) of 4.8% was obtained.
Neutron beam irradiation study of workload dependence of SER in a microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Michalak, Sarah E; Graves, Todd L; Hong, Ted

It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

Dense and Sparse Matrix Operations on the Cell Processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Williams, Samuel W.; Shalf, John; Oliker, Leonid

2005-05-01

The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. Therefore, the high performance computing community is examining alternative architectures that address the limitations of modern superscalar designs. In this work, we examine STI's forthcoming Cell processor: a novel, low-power architecture that combines a PowerPC core with eight independent SIMD processing units coupled with a software-controlled memory to offer high FLOP/s/Watt. Since neither Cell hardware nor cycle-accurate simulators are currently publicly available, we develop an analytic framework to predict Cell performance on dense and sparse matrix operations, usingmore » a variety of algorithmic approaches. Results demonstrate Cell's potential to deliver more than an order of magnitude better GFLOP/s per watt performance, when compared with the Intel Itanium2 and Cray X1 processors.« less
Experience with custom processors in space flight applications

NASA Technical Reports Server (NTRS)

Fraeman, M. E.; Hayes, J. R.; Lohr, D. A.; Ballard, B. W.; Williams, R. L.; Henshaw, R. M.

1991-01-01

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.
Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.; Bashkow, T.

1978-01-01

The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.
Variable-thermoinsulation garments with a microprocessor temperature controller.

PubMed

Kurczewska, Agnieszka; Leánikowski, Jacek

2008-01-01

This paper presents the concept of active variable thermoinsulation clothing for users working in low temperatures. Those garments contain heating inserts regulated by a microprocessor temperature controller. This paper also presents the results of tests carried out on the newly designed garments.
Orbit determination software development for microprocessor based systems: Evaluation and recommendations

NASA Technical Reports Server (NTRS)

Shenitz, C. M.; Mcgarry, F. E.; Tasaki, K. K.

1980-01-01

A guide is presented for National Aeronautics and Space Administration management personnel who stand to benefit from the lessons learned in developing microprocessor-based flight dynamics software systems. The essential functional characteristics of microprocessors are presented. The relevant areas of system support software are examined, as are the distinguishing characteristics of flight dynamics software. Design examples are provided to illustrate the major points presented, and actual development experience obtained in this area is provided as evidence to support the conclusions reached.
Safety and function of a prototype microprocessor-controlled knee prosthesis for low active transfemoral amputees switching from a mechanic knee prosthesis: a pilot study.

PubMed

Hasenoehrl, Timothy; Schmalz, Thomas; Windhager, Reinhard; Domayer, Stephan; Dana, Sara; Ambrozy, Clemens; Palma, Stefano; Crevenna, Richard

2018-02-01

Aim of this pilot study was to assess safety and functioning of a microprocessor-controlled knee prosthesis (MPK) after a short familiarization time and no structured physical therapy. Five elderly, low-active transfemoral amputees who were fitted with a standard non-microprocessor controlled knee prosthesis (NMPK) performed a baseline measurement consisting of a 3 D gait analysis, functional tests and questionnaires. The first follow-up consisted of the same test procedure and was performed with the MPK after 4 to 6 weeks of familiarization. After being refitted to their standard NMPK again, the subjects undertook the second follow-up which consisted of solely questionnaires 4 weeks later. Questionnaires and functional tests showed an increase in the perception of safety. Moreover, gait analysis revealed more physiologic knee and hip extension/flexion patterns when using the MPK. Our results showed that although the Genium with Cenior-Leg ruleset-MPK (GCL-MPK) might help to improve several safety-related outcomes as well as gait biomechanics the functional potential of the GCL-MPK may have been limited without specific training and a sufficient acclimation period. Implications for Rehabilitation Elderly transfemoral amputees are often limited in their activity by safety issues as well as insufficient functioning regarding the non microprocessor-controlled knee prostheses (NMPK), thing that could be eliminated with the use of suitable microprocessor-controlled prostheses (MPK). The safety and functioning of a prototype MPK (GCL-MPK) specifically designed for the needs of older and low-active transfemoral amputees was assessed in this pilot study. The GCL-MPK showed indicators of increased safety and more natural walking patterns in older and low-active transfemoral amputees in comparison to the standard NMPK already after a short acclimatisation time and no structured physical therapy. Regarding functional performance it seems as if providing older and low-active transfemoral amputees with the GCL-MPK alone without prescribing structured prosthesis training might be insufficient to achieve improvements over the standard NMPKs.
Development of single cell protectors for sealed silver-zinc cells, phase 1

NASA Technical Reports Server (NTRS)

Imamura, M. S.; Donovan, R. L.; Lear, J. W.; Murray, B.

1976-01-01

A single cell protector (SCP) assembly capable of protecting a single silver-zinc (Ag Zn) battery cell was designed, fabricated, and tested. The SCP provides cell-level protection against overcharge and overdischarge by a bypass circuit. The bypass circuit consists of a magnetic-latching relay that is controlled by the high and low-voltage limit comparators. Although designed specifically for secondary Ag-Zn cells, the SCP is flexible enough to be adapted to other rechargeable cells. Eighteen SCPs were used in life testing of an 18-cell battery. The cells were sealed Ag-Zn system with inorganic separators. For comparison, another 18-cell battery was subjected to identical life test conditions, but with battery-level protection rather than cell-level. An alternative approach to the SCP design in the form of a microprocessor-based system was conceptually designed. The comparison of SCP and microprocessor approaches is also presented and a preferred approach for Ag-Zn battery protection is discussed.
APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.
Operation of commercial R3000 processors in the low earth orbit (LEO) space environment

NASA Astrophysics Data System (ADS)

Kaschmitter, J. L.; Shaeffer, D. L.; Colella, N. J.; McKnett, C. L.; Coakley, P. G.

1991-12-01

Spacecraft processors must operate with minimal degradation of performance in the LEO radiation environment, which includes the effects of total accumulated ionizing dose and single event phenomena (SEP) caused by protons and cosmic rays. Commercially available microprocessors can offer a number of advantages relative to radiation-hardened devices but are not normally designed to tolerate effects induced by the LEO environment. Extensive testing of the MIPS R3000 Reduced Instruction Set Computer (RISC) microprocessor family for operation in LEO environments is reported. The authors have characterized total dose and SEP effects for altitudes and inclinations of interest to systems operating in LEO, and they postulate techniques for detection and alleviation of SEP effects based on experimental results.
Research in the design of high-performance reconfigurable systems

NASA Technical Reports Server (NTRS)

Mcewan, S. D.; Spry, A. J.

1985-01-01

Computer aided design and computer aided manufacturing have the potential for greatly reducing the cost and lead time in the development of VLSI components. This potential paves the way for the design and fabrication of a wide variety of economically feasible high level functional units. It was observed that current computer systems have only a limited capacity to absorb new VLSI component types other than memory, microprocessors, and a relatively small number of other parts. The first purpose is to explore a system design which is capable of effectively incorporating a considerable number of VLSI part types and will both increase the speed of computation and reduce the attendant programming effort. A second purpose is to explore design techniques for VLSI parts which when incorporated by such a system will result in speeds and costs which are optimal. The proposed work may lay the groundwork for future efforts in the extensive simulation and measurements of the system's cost effectiveness and lead to prototype development.
Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

NASA Astrophysics Data System (ADS)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.
Simplified microprocessor design for VLSI control applications

NASA Technical Reports Server (NTRS)

Cameron, K.

1991-01-01

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.
Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

NASA Technical Reports Server (NTRS)

Hankins, J. D.

1979-01-01

Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use.
The digital implementation of control compensators: The coefficient wordlength issue

NASA Technical Reports Server (NTRS)

Moroney, P.; Willsky, A. S.; Houpt, P. K.

1979-01-01

There exists a number of mathematical procedures for designing discrete-time compensators. However, the digital implementation of these designs, with a microprocessor for example, has not received nearly as thorough an investigation. The finite-precision nature of the digital hardware makes it necessary to choose an algorithm (computational structure) that will perform 'well-enough' with regard to the initial objectives of the design. This paper describes a procedure for estimating the required fixed-point coefficient wordlength for any given computational structure for the implementation of a single-input single-output LOG design. The results are compared to the actual number of bits necessary to achieve a specified performance index.
A micrometeoroid deceleration and capture experiment: Conceptual experiment design description

NASA Technical Reports Server (NTRS)

Wolfe, J. H.; Ballard, R. W.; Carle, G. C.; Bunch, T. E.

1986-01-01

The preliminary conceptual design for a cosmic dust collector is described. For the case of low Earth orbit (LEO), dust particles enter the collector through the collimator at a few volts negative potential due to charging in the ionosphere, at a velocity of 1 to 50 km/sec. The particles then pass through an electron stream and are charged to about 1 KV negative (regardless of incoming polarity). The 1 KV negatively charged particle then passes through three sensing grids coupled to charge sensitive preamps (CSP). The comparison of the two pulses provided by S(1) and S(2) are utilized by the microprocessor to determine the charge, q, on the particle (pulse amplitude) and its velocity, v (by time of flight). The third sensing grid, S(3), is kept at about 20 KV negative so that the dust particle will now be decelerated in passing from S(2) (zero potential) to S(3). S(3) is capacitively coupled to its CSP and the pulse from S(3) is utilized by the microprocessor to determine the particle's energy, E, and therefore its mass, m (again by time of flight) by comparison with the pulses from S(1) and S(2). The microprocessor can now precisely program the high-voltage switching network for the proper timing in the grounding of the successive deceleration grids. As determined by the microprocessor, each successive deceleration grid is grounded just after the dust particle passes, thus reducing the particle's energy by the amount q*100 KV at each stage. The microprocessor also determines at which stage the particle will fall below a certain critical energy where all remaining grids remain unswitched so that the particle will drift to the collector. The collector is kept at about 100V positive and is covered with gold foil to eliminate contamination and is removable for subsequent return to earth for detailed analysis.
An Interdisciplinary Microprocessor Project.

ERIC Educational Resources Information Center

Wilcox, Alan D.; And Others

1985-01-01

Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)
The formal verification of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.
Advanced microprocessor based power protection system using artificial neural network techniques

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Z.; Kalam, A.; Zayegh, A.

This paper describes an intelligent embedded microprocessor based system for fault classification in power system protection system using advanced 32-bit microprocessor technology. The paper demonstrates the development of protective relay to provide overcurrent protection schemes for fault detection. It also describes a method for power fault classification in three-phase system based on the use of neural network technology. The proposed design is implemented and tested on a single line three phase power system in power laboratory. Both the hardware and software development are described in detail.
Technological trends in automobiles.

PubMed

Horton, E J; Compton, W D

1984-08-10

Current technological trends in the automotive industry reflect many diverse disciplines. Electronics and microprocessors, new engine transmission concepts, composite and ceramic materials, and computer-aided design and manufacture will combine to make possible the creation of advanced automobiles offering outstanding quality, fuel economy, and performance. A projected "average" vehicle of the 1990's is described to illustrate the application of these new concepts.
High-performance computing for airborne applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Manuzzato, Andrea; Fairbanks, Tom

2010-06-28

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even thoughmore » the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.« less

The microprocessor-based synthesizer controller

NASA Technical Reports Server (NTRS)

Wick, M. R.

1980-01-01

Implementation and performance of the microprocessor-based controllers and Dana Digiphase Synthesizer (DCO) installed in the Deep Space Network exciter in the 64-meter and 34-meter subnets to support uplink tuning required for the Voyager-Saturn Encounter is discussed. Test data in tests conducted during the production of the controllers verified the design objective for phase control accuracy of 10 to the - 12 power cycles in eight hours during ramping. Tests conducted require a phase error between a theoretical calculated value and the actual phase of no greater than + or - 1 cycle. Tests included (1) a ramp over a period of eight hours using a ramp rate which covers the synthesizer tuning range (40-51 MHz) and (2) a ramp sequence using the maximum rate (+ or kHz/s) over the tuning range.
MicroShell Minimalist Shell for Xilinx Microprocessors

NASA Technical Reports Server (NTRS)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.
Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.
Feasibility of a special-purpose computer to solve the Navier-Stokes equations

NASA Technical Reports Server (NTRS)

Gritton, E. C.; King, W. S.; Sutherland, I.; Gaines, R. S.; Gazley, C., Jr.; Grosch, C.; Juncosa, M.; Petersen, H.

1978-01-01

Orders-of-magnitude improvements in computer performance can be realized with a parallel array of thousands of fast microprocessors. In this architecture, wiring congestion is minimized by limiting processor communication to nearest neighbors. When certain standard algorithms are applied to a viscous flow problem and existing LSI technology is used, performance estimates of this conceptual design show a dramatic decrease in computational time when compared to the CDC 7600.
An Ill-Structured PBL-Based Microprocessor Course without Formal Laboratory

ERIC Educational Resources Information Center

Kim, Jungkuk

2012-01-01

This paper introduces a problem-based learning (PBL) microprocessor application course designed according to the following strategies: 1) hands-on training without having a formal laboratory, and 2) intense student-centered cooperative learning through an ill-structured problem. PBL was adopted as the core educational technique of the course to…
DSS 13 microprocessor antenna controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1988-01-01

A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.
An FPGA computing demo core for space charge simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Jinyuan; Huang, Yifei; /Fermilab

2009-01-01

In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computedmore » using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.« less
Human operator tracking performance with a vibrotactile display

NASA Technical Reports Server (NTRS)

Inbar, Gideon F.

1991-01-01

Vibrotactile displays have been designed and used as a sensory aid for the blind. In the present work the same 6 x 24 'Optacon' type vibrotactile display (VTD) was used to characterize human operator (HO) tracking performance in pursuit and compensatory tasks. The VTD was connected via a microprocessor to a one-dimensional joy stick manipulator. Various display schemes were tested on the VDT, and were also compared to visual tracking performance using a specially constructed photo diode matrix display comparable to the VTD.
Extended performance electric propulsion power processor design study. Volume 2: Technical summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.
Briefing: Microprocessors.

ERIC Educational Resources Information Center

Standing, Roy A.

1982-01-01

Reviews the basic concepts and technology behind the functions computers perform, describes the miniaturization of computer components, discusses the development of the microprocessor and the microcomputer, and makes projections concerning the future of the microcomputer market. Information is provided on the features, costs, and manufacturers of…
Low-power circuits design for the wireless force measurement system of the total knee arthroplasty.

PubMed

Chen, Hong; Liu, Ming; Wan, Weiyi; Jia, Chen; Zhang, Chun; Wang, Zihua

2010-01-01

This paper proposes a novel wireless force measurement system for the Total Knee Arthroplasty (TKA) to improve the ligament balancing procedure during TKA. The force measurement system is comprised of a Wireless Force Measurement Spacer (WFMS) and the display part. They communicate with each other by the Radio Frequency (RF) signal. The WFMS is designed to measure the force between the WFMS and the femoral component of the artificial implants and to transmit the force data wirelessly by a low power transceiver. The display part demonstrates the force data in 3D images in real time. The WFMS composes of a sensors array, a Universal Transducer Interfaces (UTIs) array, a low-power sub-threshold microprocessor and a transceiver. The sub-threshold 8-bit microprocessor is taped out with 0.18 microm CMOS technology. The testing results of the microprocessor show that the leakage power of 46nW and the dynamic power of 385nW@165kHz are achieved with the operating voltage of 350 mV. The test results of the system are given and the errors of the system are analyzed. The results verified the reliability of the system. The future work is to design the microprocessor and a lower power transceiver within a single chip.
A Multi-Media CAI Terminal Based upon a Microprocessor with Applications for the Handicapped.

ERIC Educational Resources Information Center

Brebner, Ann; Hallworth, H. J.

The design of the CAI interface described is based on the microprocessor in order to meet three basic requirements for providing appropriate instruction to the developmentally handicapped: (1) portability, so that CAI can be taken into the customary learning environment; (2) reliability; and (3) flexibility, to permit use of new input and output…
The Minerva Multi-Microprocessor.

DTIC Science & Technology

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.
A real time microcomputer implementation of sensor failure detection for turbofan engines

NASA Technical Reports Server (NTRS)

Delaat, John C.; Merrill, Walter C.

1989-01-01

An algorithm was developed which detects, isolates, and accommodates sensor failures using analytical redundancy. The performance of this algorithm was demonstrated on a full-scale F100 turbofan engine. The algorithm was implemented in real-time on a microprocessor-based controls computer which includes parallel processing and high order language programming. Parallel processing was used to achieve the required computational power for the real-time implementation. High order language programming was used in order to reduce the programming and maintenance costs of the algorithm implementation software. The sensor failure algorithm was combined with an existing multivariable control algorithm to give a complete control implementation with sensor analytical redundancy. The real-time microprocessor implementation of the algorithm which resulted in the successful completion of the algorithm engine demonstration, is described.
DOE Office of Scientific and Technical Information (OSTI.GOV)

Gebis, Joseph; Oliker, Leonid; Shalf, John

The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changesmore » to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.« less
DOE Office of Scientific and Technical Information (OSTI.GOV)

Budden, B. S.; Stonehill, L. C.; Warniment, A.

In this study, a new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurablemore » to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.« less
Stand-alone development system using a KIM-1 microcomputer module

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1978-01-01

A small microprocessor-based system designed to: contain all or most of the interface hardware, designed to be easy to access and modify the hardware, to be capable of being strapped to the seat of a small general aviation aircraft, and to be independent of the aircraft power system is described. The system is used to develop a low cost Loran C sensor processor, but is designed such that the Loran interface boards may be removed and other hardware interfaces inserted into the same connectors. This flexibility is achieved through memory-mapping techniques into the microprocessor.
ADA and multi-microprocessor real-time simulation

NASA Technical Reports Server (NTRS)

Feyock, S.; Collins, W. R.

1983-01-01

The selection of a high-order programming language for a real-time distributed network simulation is described. The additional problem of implementing a language on a possibly changing network is addressed. The recently designed language ADA (trademarked by DoD) was chosen since it provides the best model of the underlying application to be simulated.
Energy expenditure and activity of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Levine, James A; Brey, Robert H; McCrady, Shelly K; Padgett, Denny J; Joyner, Michael J

2008-07-01

To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Repeated-measures design to evaluate comparative functional outcomes. Exercise physiology laboratory and community free-living environment. Subjects (N=15; 12 men, 3 women; age, 42+/-9 y; range, 26-57 y) with transfemoral amputation. Research participants were long-term users of a mechanical prosthesis (20+/-10 y as an amputee; range, 3-36 y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18+/-8 wk) before being retested. Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Subjects demonstrated significantly increased physical activity-related energy expenditure levels in the participant's free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life.
High Accuracy Fuel Flowmeter, Phase 1

NASA Technical Reports Server (NTRS)

Mayer, C.; Rose, L.; Chan, A.; Chin, B.; Gregory, W.

1983-01-01

Technology related to aircraft fuel mass - flowmeters was reviewed to determine what flowmeter types could provide 0.25%-of-point accuracy over a 50 to one range in flowrates. Three types were selected and were further analyzed to determine what problem areas prevented them from meeting the high accuracy requirement, and what the further development needs were for each. A dual-turbine volumetric flowmeter with densi-viscometer and microprocessor compensation was selected for its relative simplicity and fast response time. An angular momentum type with a motor-driven, spring-restrained turbine and viscosity shroud was selected for its direct mass-flow output. This concept also employed a turbine for fast response and a microcomputer for accurate viscosity compensation. The third concept employed a vortex precession volumetric flowmeter and was selected for its unobtrusive design. Like the turbine flowmeter, it uses a densi-viscometer and microprocessor for density correction and accurate viscosity compensation.

Intelligent redundant actuation system requirements and preliminary system design

NASA Technical Reports Server (NTRS)

Defeo, P.; Geiger, L. J.; Harris, J.

1985-01-01

Several redundant actuation system configurations were designed and demonstrated to satisfy the stringent operational requirements of advanced flight control systems. However, this has been accomplished largely through brute force hardware redundancy, resulting in significantly increased computational requirements on the flight control computers which perform the failure analysis and reconfiguration management. Modern technology now provides powerful, low-cost microprocessors which are effective in performing failure isolation and configuration management at the local actuator level. One such concept, called an Intelligent Redundant Actuation System (IRAS), significantly reduces the flight control computer requirements and performs the local tasks more comprehensively than previously feasible. The requirements and preliminary design of an experimental laboratory system capable of demonstrating the concept and sufficiently flexible to explore a variety of configurations are discussed.
Input/output models for general aviation piston-prop aircraft fuel economy

NASA Technical Reports Server (NTRS)

Sweet, L. M.

1982-01-01

A fuel efficient cruise performance model for general aviation piston engine airplane was tested. The following equations were made: (1) for the standard atmosphere; (2) airframe-propeller-atmosphere cruise performance; and (3) naturally aspirated engine cruise performance. Adjustments are made to the compact cruise performance model as follows: corrected quantities, corrected performance plots, algebraic equations, maximize R with or without constraints, and appears suitable for airborne microprocessor implementation. The following hardwares are recommended: ignition timing regulator, fuel-air mass ration controller, microprocessor, sensors and displays.
Electromechanical actuation for thrust vector control applications

NASA Technical Reports Server (NTRS)

Roth, Mary Ellen

1990-01-01

The advanced launch system (ALS), is a launch vehicle that is designed to be cost-effective, highly reliable, and operationally efficient with a goal of reducing the cost per pound to orbit. An electromechanical actuation (EMA) system is being developed as an attractive alternative to the hydraulic systems. The controller will integrate 20 kHz resonant link power management and distribution (PMAD) technology and pulse population modulation (PPM) techniques to implement field-oriented vector control (FOVC) of a new advanced induction motor. The driver and the FOVC will be microprocessor controlled. For increased system reliability, a built-in test (BITE) capability will be included. This involves introducing testability into the design of a system such that testing is calibrated and exercised during the design, manufacturing, maintenance, and prelaunch activities. An actuator will be integrated with the motor controller for performance testing of the EMA thrust vector control (TVC) system. The EMA system and work proposed for the future are discussed.
DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D; Ulmer, Craig D.; Thompson, David

Field programmable gate arrays (FPGAs) have been used as alternative computational de-vices for over a decade; however, they have not been used for traditional scientific com-puting due to their perceived lack of floating-point performance. In recent years, there hasbeen a surge of interest in alternatives to traditional microprocessors for high performancecomputing. Sandia National Labs began two projects to determine whether FPGAs wouldbe a suitable alternative to microprocessors for high performance scientific computing and,if so, how they should be integrated into the system. We present results that indicate thatFPGAs could have a significant impact on future systems. FPGAs have thepotentialtohave ordermore » of magnitude levels of performance wins on several key algorithms; however,there are serious questions as to whether the system integration challenge can be met. Fur-thermore, there remain challenges in FPGA programming and system level reliability whenusing FPGA devices.4 AcknowledgmentArun Rodrigues provided valuable support and assistance in the use of the Structural Sim-ulation Toolkit within an FPGA context. Curtis Janssen and Steve Plimpton provided valu-able insights into the workings of two Sandia applications (MPQC and LAMMPS, respec-tively).5« less
Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

NASA Technical Reports Server (NTRS)

Rubaai, Ahmed; Kankam, David (Technical Monitor)

2003-01-01

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.
Evaluation of the performance of microprocessor-based colorimeter

PubMed Central

Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments. PMID:18924952
Evaluation of the performance of microprocessor-based colorimeter.

PubMed

Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.
Satisfying STEM Education Using the Arduino Microprocessor in C Programming

NASA Astrophysics Data System (ADS)

Hoffer, Brandyn M.

There exists a need to promote better Science Technology Engineering and Math (STEM) education at the high school level. To satisfy this need a series of hands-on laboratory assignments were created to be accompanied by 2 educational trainers that contain various electronic components. This project provides an interdisciplinary, hands-on approach to teaching C programming that meets several standards defined by the Tennessee Board of Education. Together the trainers and lab assignments also introduce key concepts in math and science while allowing students hands-on experience with various electronic components. This will allow students to mimic real world applications of using the C programming language while exposing them to technology not currently introduced in many high school classrooms. The developed project is targeted at high school students performing at or above the junior level and uses the Arduino Mega open-source Microprocessor and software as the primary control unit.
A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

PubMed

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.
Impact of a stance phase microprocessor-controlled knee prosthesis on level walking in lower functioning individuals with a transfemoral amputation.

PubMed

Eberly, Valerie J; Mulroy, Sara J; Gronley, JoAnne K; Perry, Jacquelin; Yule, William J; Burnfield, Judith M

2014-12-01

For individuals with transfemoral amputation, walking with a prosthesis presents challenges to stability and increases the demand on the hip of the prosthetic limb. Increasing age or comorbidities magnify these challenges. Computerized prosthetic knee joints improve stability and efficiency of gait, but are seldom prescribed for less physically capable walkers who may benefit from them. To compare level walking function while wearing a microprocessor-controlled knee (C-Leg Compact) prosthesis to a traditionally prescribed non-microprocessor-controlled knee prosthesis for Medicare Functional Classification Level K-2 walkers. Crossover. Stride characteristics, kinematics, kinetics, and electromyographic activity were recorded in 10 participants while walking with non-microprocessor-controlled knee and Compact prostheses. Walking with the Compact produced significant increase in velocity, cadence, stride length, single-limb support, and heel-rise timing compared to walking with the non-microprocessor-controlled knee prosthesis. Hip and thigh extension during late stance improved bilaterally. Ankle dorsiflexion, knee extension, and hip flexion moments of the prosthetic limb were significantly improved. Improvements in walking function and stability on the prosthetic limb were demonstrated by the K-2 level walkers when using the C-Leg Compact prosthesis. Understanding the impact of new prosthetic designs on gait mechanics is essential to improve prescription guidelines for deconditioned or older persons with transfemoral amputation. Prosthetic designs that improve stability for safety and walking function have the potential to improve community participation and quality of life. © The International Society for Prosthetics and Orthotics 2013.
System design and installation for RS600 programmable control system for solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Procedures for installing, operating, and maintaining a programmable control system which utilizes a F8 microprocessor to perform all timing, control, and calculation functions in order to customize system performance to meet individual requirements for solar heating, combined heating and cooling, and/or hot water systems are described. The manual discusses user configuration and options, displays, theory of operation, trouble-shooting procedures, and warranty and assistance. Wiring lists, parts lists, drawings, and diagrams are included.
Advanced Electricity. Microprocessors and Robotics. Curriculum Development. Bulletin 1803.

ERIC Educational Resources Information Center

Southeastern Louisiana Univ., Hammond.

This model instructional unit was developed to aid industrial arts/technology education teachers in Louisiana to teach a course on microprocessors and robotics in grades 11 and 12. It provides guidance on model performance objectives, current technology content, sources, and supplemental materials. Following a course description, rationale, and…
Multitasking in a data acquisition system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Larsen, J.E.

1980-01-01

Microprocessors and microcomputers have been employed widely in data acquisition applications due to low cost and the ease of adapting the microcomputer to changing or altered requirements. Multitasking offers ways of getting more performance from a microcomputer and also a means of designing a system which by its nature is easily changed to meet new requirements. The term multitasking is used to include definitions of multitasking and multiprogramming: multitasking-performing various related functions of the same job, e.g. data acquisition and data logging (recording); multiprogramming-performing possibly unrelated jobs concurrently.
A class of optimum digital phase locked loops

NASA Technical Reports Server (NTRS)

Kumar, R.; Hurd, W. J.

1986-01-01

This paper presents a class of optimum digital filters for digital phase locked loops, for the important case in which the maximum update rate of the loop filter and numerically controlled oscillator (NCO) is limited. This case is typical when the loop filter is implemented in a microprocessor. In these situations, pure delay is encountered in the loop transfer function and thus the stability and gain margin of the loop are of crucial interest. The optimum filters designed for such situations are evaluated in terms of their gain margin for stability, dynamic error, and steady-state error performance. For situations involving considerably high phase dynamics an adaptive and programmable implementation is also proposed to obtain an overall optimum strategy.
"Smart" Sensor Module

NASA Technical Reports Server (NTRS)

Mahajan, Ajay

2007-01-01

An assembly that contains a sensor, sensor-signal-conditioning circuitry, a sensor-readout analog-to-digital converter (ADC), data-storage circuitry, and a microprocessor that runs special-purpose software and communicates with one or more external computer(s) has been developed as a prototype of "smart" sensor modules for monitoring the integrity and functionality (the "health") of engineering systems. Although these modules are now being designed specifically for use on rocket-engine test stands, it is anticipated that they could also readily be designed to be incorporated into health-monitoring subsystems of such diverse engineering systems as spacecraft, aircraft, land vehicles, bridges, buildings, power plants, oilrigs, and defense installations. The figure is a simplified block diagram of the "smart" sensor module. The analog sensor readout signal is processed by the ADC, the digital output of which is fed to the microprocessor. By means of a standard RS-232 cable, the microprocessor is connected to a local personal computer (PC), from which software is downloaded into a randomaccess memory in the microprocessor. The local PC is also used to debug the software. Once the software is running, the local PC is disconnected and the module is controlled by, and all output data from the module are collected by, a remote PC via an Ethernet bus. Several smart sensor modules like this one could be connected to the same Ethernet bus and controlled by the single remote PC. The software running in the microprocessor includes driver programs for operation of the sensor, programs that implement self-assessment algorithms, programs that implement protocols for communication with the external computer( s), and programs that implement evolutionary methodologies to enable the module to improve its performance over time. The design of the module and of the health-monitoring system of which it is a part reflects the understanding that the main purpose of a health-monitoring system is to detect damage and, therefore, the health-monitoring system must be able to function effectively in the presence of damage and should be capable of distinguishing between damage to itself and damage to the system being monitored. A major benefit afforded by the self-assessment algorithms is that in the output of the module, the sensor data indicative of the health of the engineering system being monitored are coupled with a confidence factor that quantifies the degree of reliability of the data. Hence, the output includes information on the health of the sensor module itself in addition to information on the health of the engineering system being monitored.
Design of a Distributed Microprocessor Sensor System

DTIC Science & Technology

1990-04-01

implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion
Design of verification platform for wireless vision sensor networks

NASA Astrophysics Data System (ADS)

Ye, Juanjuan; Shang, Fei; Yu, Chuang

2017-08-01

At present, the majority of research for wireless vision sensor networks (WVSNs) still remains in the software simulation stage, and the verification platforms of WVSNs that available for use are very few. This situation seriously restricts the transformation from theory research of WVSNs to practical application. Therefore, it is necessary to study the construction of verification platform of WVSNs. This paper combines wireless transceiver module, visual information acquisition module and power acquisition module, designs a high-performance wireless vision sensor node whose core is ARM11 microprocessor and selects AODV as the routing protocol to set up a verification platform called AdvanWorks for WVSNs. Experiments show that the AdvanWorks can successfully achieve functions of image acquisition, coding, wireless transmission, and obtain the effective distance parameters between nodes, which lays a good foundation for the follow-up application of WVSNs.
A HW-SW Co-Designed System for the Lunar Lander Hazard Detection and Avoidance Breadboarding

NASA Astrophysics Data System (ADS)

Palomo, Pedro; Latorre, Antonio; Valle, Carlos; Gomez de Aguero, Sergio; Hagenfeldt, Miguel; Parreira, Baltazar; Lindoso, Almudena; Portela, Marta; Garcia, Mario; San Millan, Enrique; Zharikov, Yuri; Entrena, Luis

2014-08-01

This paper presents the HW-SW co-design approach followed to tackle the design of the Hazard Detection and Avoidance (HDA) system breadboarding for the Lunar Lander ESA mission, undertaken given the fact that novel GNC technologies used to promote autonomous systems demand processing capabilities that current (and forthcoming) space processors are not able to satisfy. The paper shows how the current system design has been performed in a process in which the original HDA functionally validated design has been partitioned between SW (deemed for execution in a microprocessor) and HW algorithms (to be executed in an FPGA), considering the performance requirements and resorting to a deep analysis of the algorithms in view of their adequacy to HW or SW implementation.
The development of an airborne information management system for flight test

NASA Technical Reports Server (NTRS)

Bever, Glenn A.

1992-01-01

An airborne information management system is being developed at the NASA Dryden Flight Research Facility. This system will improve the state of the art in management data acquisition on-board research aircraft. The design centers around highly distributable, high-speed microprocessors that allow data compression, digital filtering, and real-time analysis. This paper describes the areas of applicability, approach to developing the system, potential for trouble areas, and reasons for this development activity. System architecture (including the salient points of what makes it unique), design philosophy, and tradeoff issues are also discussed.
Design considerations for a LORAN-C timing receiver in a hostile signal to noise environment

NASA Technical Reports Server (NTRS)

Porter, J. W.; Bowell, J. R.; Price, G. E.

1981-01-01

The environment in which a LORAN-C Timing Receiver may function effectively depends to a large extent on the techniques utilized to insure that interfering signals within the pass band of the unit are neutralized. The baseline performance manually operated timing receivers is discussed and the basic design considerations and necessary parameters for an automatic unit utilizing today's technology are established. Actual performance data is presented comparing the results obtained from a present generation timing receiver against a new generation microprocessor controlled automatic acquisition receiver. The achievements possible in a wide range of signal to noise situations are demonstrated.

Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

DOE PAGES

Budden, B. S.; Stonehill, L. C.; Warniment, A.; ...

2015-06-10

In this study, a new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurablemore » to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.« less
Handheld readout electronics to fully exploit the particle discrimination capabilities of elpasolite scintillators

NASA Astrophysics Data System (ADS)

Budden, B. S.; Stonehill, L. C.; Warniment, A.; Michel, J.; Storms, S.; Dallmann, N.; Coupland, D. D. S.; Stein, P.; Weller, S.; Borges, L.; Proicou, M.; Duran, G.; Kamto, J.

2015-09-01

A new class of elpasolite scintillators has garnered recent attention due to the ability to perform as simultaneous gamma spectrometers and thermal neutron detectors. Such a dual-mode capability is made possible by pulse-shape discrimination (PSD), whereby the emission waveform profiles of gamma and neutron events are fundamentally unique. To take full advantage of these materials, we have developed the Compact Advanced Readout Electronics for Elpasolites (CAREE). This handheld instrument employs a multi-channel PSD-capable ASIC, custom micro-processor board, front-end electronics, power supplies, and a 2 in. photomultiplier tube for readout of the scintillator. The unit is highly configurable to allow for performance optimization amongst a wide sample of elpasolites which provide PSD in fundamentally different ways. We herein provide an introduction to elpasolites, then describe the motivation for the work, mechanical and electronic design, and preliminary performance results.
Loran-C digital word generator for use with a KIM-1 microprocessor system

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1977-01-01

The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.
Hyperswitch communication network

NASA Technical Reports Server (NTRS)

Peterson, J.; Pniel, M.; Upchurch, E.

1991-01-01

The Hyperswitch Communication Network (HCN) is a large scale parallel computer prototype being developed at JPL. Commercial versions of the HCN computer are planned. The HCN computer being designed is a message passing multiple instruction multiple data (MIMD) computer, and offers many advantages in price-performance ratio, reliability and availability, and manufacturing over traditional uniprocessors and bus based multiprocessors. The design of the HCN operating system is a uniquely flexible environment that combines both parallel processing and distributed processing. This programming paradigm can achieve a balance among the following competing factors: performance in processing and communications, user friendliness, and fault tolerance. The prototype is being designed to accommodate a maximum of 64 state of the art microprocessors. The HCN is classified as a distributed supercomputer. The HCN system is described, and the performance/cost analysis and other competing factors within the system design are reviewed.
Design and implementation of scalable tape archiver

NASA Technical Reports Server (NTRS)

Nemoto, Toshihiro; Kitsuregawa, Masaru; Takagi, Mikio

1996-01-01

In order to reduce costs, computer manufacturers try to use commodity parts as much as possible. Mainframes using proprietary processors are being replaced by high performance RISC microprocessor-based workstations, which are further being replaced by the commodity microprocessor used in personal computers. Highly reliable disks for mainframes are also being replaced by disk arrays, which are complexes of disk drives. In this paper we try to clarify the feasibility of a large scale tertiary storage system composed of 8-mm tape archivers utilizing robotics. In the near future, the 8-mm tape archiver will be widely used and become a commodity part, since recent rapid growth of multimedia applications requires much larger storage than disk drives can provide. We designed a scalable tape archiver which connects as many 8-mm tape archivers (element archivers) as possible. In the scalable archiver, robotics can exchange a cassette tape between two adjacent element archivers mechanically. Thus, we can build a large scalable archiver inexpensively. In addition, a sophisticated migration mechanism distributes frequently accessed tapes (hot tapes) evenly among all of the element archivers, which improves the throughput considerably. Even with the failures of some tape drives, the system dynamically redistributes hot tapes to the other element archivers which have live tape drives. Several kinds of specially tailored huge archivers are on the market, however, the 8-mm tape scalable archiver could replace them. To maintain high performance in spite of high access locality when a large number of archivers are attached to the scalable archiver, it is necessary to scatter frequently accessed cassettes among the element archivers and to use the tape drives efficiently. For this purpose, we introduce two cassette migration algorithms, foreground migration and background migration. Background migration transfers cassettes between element archivers to redistribute frequently accessed cassettes, thus balancing the load of each archiver. Background migration occurs the robotics are idle. Both migration algorithms are based on access frequency and space utility of each element archiver. To normalize these parameters according to the number of drives in each element archiver, it is possible to maintain high performance even if some tape drives fail. We found that the foreground migration is efficient at reducing access response time. Beside the foreground migration, the background migration makes it possible to track the transition of spatial access locality quickly.
Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

PubMed

Shenoy, Archana; Blelloch, Robert

2009-09-11

The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript. To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES) cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8. We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.
Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Architectures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava

Faced with physical and energy density limitations on clock speed, contemporary microprocessor designers have increasingly turned to on-chip parallelism for performance gains. Examples include the Intel Xeon Phi, GPGPUs, and similar technologies. Algorithms should accordingly be designed with ample amounts of fine-grained parallelism if they are to realize the full performance of the hardware. This requirement can be challenging for algorithms that are naturally expressed as a sequence of small-matrix operations, such as the Kalman filter methods widely in use in high-energy physics experiments. In the High-Luminosity Large Hadron Collider (HL-LHC), for example, one of the dominant computational problems ismore » expected to be finding and fitting charged-particle tracks during event reconstruction; today, the most common track-finding methods are those based on the Kalman filter. Experience at the LHC, both in the trigger and offline, has shown that these methods are robust and provide high physics performance. Previously we reported the significant parallel speedups that resulted from our efforts to adapt Kalman-filter-based tracking to many-core architectures such as Intel Xeon Phi. Here we report on how effectively those techniques can be applied to more realistic detector configurations and event complexity.« less
Programmable calculator as a data system controller

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, A.W.; Strasburg, A.C.

Digital data techniques are in common use for analysis of analog information obtained in various tests, and systems have been developed which use a minicomputer as the central controller and data processor. Now, microprocessors allow new design approaches at considerably less cost. This report outlines an approach to system design based on the use of a programmable calculator as the data system controller. A block diagram of the calculator-controlled data system is shown. It was found that the programmable calculator provides a viable alternative to minicomputers or microprocessors for the development laboratory requiring digital data processing. 3 figures. (RWR)
Multi-sensor Array for High Altitude Balloon Missions to the Stratosphere

NASA Astrophysics Data System (ADS)

Davis, Tim; McClurg, Bryce; Sohl, John

2008-10-01

We have designed and built a microprocessor controlled and expandable multi-sensor array for data collection on near space missions. Weber State University has started a high altitude research balloon program called HARBOR. This array has been designed to data log a base set of measurements for every flight and has room for six guest instruments. The base measurements are absolute pressure, on-board temperature, 3-axis accelerometer for attitude measurement, and 2-axis compensated magnetic compass. The system also contains a real time clock and circuitry for logging data directly to a USB memory stick. In typical operation the measurements will be cycled through in sequence and saved to the memory stick along with the clock's time stamp. The microprocessor can be reprogrammed to adapt to guest experiments with either analog or digital interfacing. This system will fly with every mission and will provide backup data collection for other instrumentation for which the primary task is measuring atmospheric pressure and temperature. The attitude data will be used to determine the orientation of the onboard camera systems to aid in identifying features in the images. This will make these images easier to use for any future GIS (geographic information system) remote sensing missions.
Transient Performance Improvement Circuit (TPIC)s for DC-DC converter applications

NASA Astrophysics Data System (ADS)

Lim, Sungkeun

Gordon Moore famously predicted the exponential increase in transistor integration and computing power that has been witnessed in recent decades [1]. In the near future, it is expected that more than one billion transistors will be integrated per chip, and advanced microprocessors will require clock speeds in excess of several GHz. The increasing number of transistors and high clock speeds will necessitate the consumption of more power. By 2014, it is expected that the maximum power consumption of the microprocessor will reach approximately 150W, and the maximum load current will be around 150A. Today's trend in power and thermal management is to reduce supply voltage as low as possible to reduce delivered power. It is anticipated that the Intel cores will operate on 0.8V of supply voltage by 2014 [2]. A significant challenge in Voltage Regulator Module (VRM) development for next generation microprocessors is to regulate the supply voltage within a certain tolerance band during high slew rate load transitions, since the required supply voltage tolerance band will be much narrower than the current requirement. If VR output impedance is maintained at a constant value from DC to high frequency, large output voltage spikes can be avoided during load cur- rent transients. Based on this, the Adaptive Voltage Position (AVP) concept was developed to achieve constant VR output impedance to improve transient response performance [3]. However, the VR output impedance can not be made constant over the entire frequency range with AVP design, because the AVP design makes the VR output impedance constant only at low frequencies. To make the output impedance constant at high frequencies, many bulk capacitors and ceramic capacitors are required. The tight supply voltage tolerance for the next generation of microprocessors during high slew rate load transitions requires fast transient response power supplies. A VRM can not follow the high slew rate load current transients, because of the slow inductor current slew rate which is determined by the input voltage, output voltage, and the inductance. The remaining inductor current in the power delivery path will charge the output capacitors and develop a voltage across the ESR. As a result, large output voltage spikes occur during load current transients. Due to their limited control bandwidth, traditional VRs can not sufficiently respond rapidly to certain load transients. As a result, a large output voltage spike can occur during load transients, hence requiring a large amount of bulk capacitance to decouple the VR from the load [2]. If the remaining inductor current is removed from the power stage or the inductor current slew rate is changed, the output voltage spikes can be clamped, allowing the output capacitance to be reduced. A new design methodology for a Transient Performance Improvement Circuit(TPIC) based on controlling the output impedance of a regulator is presented. The TPIC works in parallel with a voltage regulator (VR)'s ceramic capacitors to achieve faster voltage regulation without the need for a large bulk capacitance, and can serve as a replacement for bulk capacitors. The specific function of the TPIC is to mimic the behavior of the bulk capacitance in a traditional VRM by sinking and sourcing large currents during transients, allowing the VR to respond quickly to current transients without the need for a large bulk capacitance. This will allow fast transient response without the need for a large bulk capacitor. The main challenge in applying the TPIC is creating a design which will not interfere with VR operation. A TPIC for a 4 Switch Buck-Boost (4SBB) converter is presented which functions by con- trolling the inductor current slew rate during load current transients. By increasing the inductor current slew rate, the remaining inductor current can be removed from the 4SBB power delivery path and the output voltage spike can be clamped. A second TPIC is presented which is designed to improve the performance of an LDO regulator during output current transients. A TPIC for a LDO regulator is proposed to reduce the over voltage spike settling time. During a load current step down transient, the only current discharging path is a light load current. However, it takes a long time to discharge the current charged in the output capacitors with the light load current. The proposed TPIC will make an additional current discharging path to reduce the long settling time. By reducing the settling time, the load current transient frequency of the LDO regulator can be increased. A Ripple Cancellation Circuit (RCC) is proposed to reduce the output voltage ripple. The RCC has a very similar concept with the TPIC which is sinking or injecting additional current to the power stage to compensate the inductor ripple current. The proposed TPICs and RCC have been implemented with a 0.6m CMOS process. A single-phase VR, a 4SBB converter, and a LDO regulator have been utilized with the proposed TPIC to evaluate its performance. The theoretical analysis will be confirmed by Cadence simulation results and experimental results.
Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis

PubMed Central

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2016-01-01

Background: There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. Objectives: The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Study design: Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Methods: Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. Results: The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation (p = .001), paretic limb health (p = .04), sounds (p = .02), and well-being (p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. Conclusion: The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety. PMID:27151648
USC orthogonal multiprocessor for image processing with neural networks

NASA Astrophysics Data System (ADS)

Hwang, Kai; Panda, Dhabaleswar K.; Haddadi, Navid

1990-07-01

This paper presents the architectural features and imaging applications of the Orthogonal MultiProcessor (OMP) system, which is under construction at the University of Southern California with research funding from NSF and assistance from several industrial partners. The prototype OMP is being built with 16 Intel i860 RISC microprocessors and 256 parallel memory modules using custom-designed spanning buses, which are 2-D interleaved and orthogonally accessed without conflicts. The 16-processor OMP prototype is targeted to achieve 430 MIPS and 600 Mflops, which have been verified by simulation experiments based on the design parameters used. The prototype OMP machine will be initially applied for image processing, computer vision, and neural network simulation applications. We summarize important vision and imaging algorithms that can be restructured with neural network models. These algorithms can efficiently run on the OMP hardware with linear speedup. The ultimate goal is to develop a high-performance Visual Computer (Viscom) for integrated low- and high-level image processing and vision tasks.
Design and Development of a Multiprogramming Operating System for Sixteen Bit Microprocessors.

DTIC Science & Technology

1981-12-01

with the technical details of how services are programmed or produced, except perhaps when they fail to meet user requirements. Users are interested in...locations and loading decks. As the expense *and speed of computers increased, executive programs were created to allow several users to sequence...single user operating system as a companion to the 8080 microprocessor. CP/M (Control Program for Microcomputers) was a single user operating system that
Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

NASA Astrophysics Data System (ADS)

Liebmann, Lars W.; Graur, Ioana C.; Leipold, William C.; Oberschmidt, James M.; O'Grady, David S.; Regaill, Denis

1999-07-01

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.
Embedded algorithms within an FPGA-based system to process nonlinear time series data

NASA Astrophysics Data System (ADS)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better computational and power efficiency.
Development of a preprototype sabatier CO2 reduction subsystem

NASA Technical Reports Server (NTRS)

Kleiner, G. N.; Birbara, P.

1980-01-01

A preoprototype Sabatier CO2 Reduction Subsystem was successfully designed, fabricated and tested. The lightweight, quick starting reactor utilizes a highly active and physically durable methanation catalyst composed of ruthenium on alumina. The use of this improved catalyst permits a single straight through plug flow design with an average lean component H2/CO2 conversion efficiency of over 99% over a range of H2/CO2 molar ratios of 1.8 to 5 while operating with flows equivalent to a crew size of one person steadystate to 3 persons cyclical (equivalent to 5 persons steady state). The reactor requires no heater operation after start-up even during simulated 55 minute lightside/39 minute darkside orbital operation over the above range of molar ratios and crew loadings. The subsystem's operation and performance is controlled by a microprocessor and displayed on a nineteen inch multi-colored cathode ray tube.
Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi

Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have notmore » responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.« less
RS-600 programmable controller: Solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Three identical microprocessor control subsystems were developed which can be used in heating, heating and cooling, and/or hot water systems for single family, multifamily, or commercial applications. The controller incorporates a low cost, highly reliable (all solid state) microprocessor which can be easily reprogrammed.
The use of real-time, hardware-in-the-loop simulation in the design and development of the new Hughes HS601 spacecraft attitude control system

NASA Technical Reports Server (NTRS)

Slafer, Loren I.

1989-01-01

Realtime simulation and hardware-in-the-loop testing is being used extensively in all phases of the design, development, and testing of the attitude control system (ACS) for the new Hughes HS601 satellite bus. Realtime, hardware-in-the-loop simulation, integrated with traditional analysis and pure simulation activities is shown to provide a highly efficient and productive overall development program. Implementation of high fidelity simulations of the satellite dynamics and control system algorithms, capable of real-time execution (using applied Dynamics International's System 100), provides a tool which is capable of being integrated with the critical flight microprocessor to create a mixed simulation test (MST). The MST creates a highly accurate, detailed simulated on-orbit test environment, capable of open and closed loop ACS testing, in which the ACS design can be validated. The MST is shown to provide a valuable extension of traditional test methods. A description of the MST configuration is presented, including the spacecraft dynamics simulation model, sensor and actuator emulators, and the test support system. Overall system performance parameters are presented. MST applications are discussed; supporting ACS design, developing on-orbit system performance predictions, flight software development and qualification testing (augmenting the traditional software-based testing), mission planning, and a cost-effective subsystem-level acceptance test. The MST is shown to provide an ideal tool in which the ACS designer can fly the spacecraft on the ground.
Variable frequency microprocessor clock generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Branson, C.N.

A microprocessor-based system is described comprising: a digital central microprocessor provided with a clock input and having a rate of operation determined by the frequency of a clock signal input thereto; memory means operably coupled to the central microprocessor for storing programs respectively including a plurality of instructions and addressable by the central microprocessor; peripheral device operably connected to the central microprocessor, the first peripheral device being addressable by the central microprocessor for control thereby; a system clock generator for generating a digital reference clock signal having a reference frequency rate; and frequency rate reduction circuit means connected between themore » clock generator and the clock input of the central microprocessor for selectively dividing the reference clock signal to generate a microprocessor clock signal as an input to the central microprocessor for clocking the central microprocessor.« less

Performance, operational limits, of an Electronic Switching Spherical Array (ESSA) antenna

NASA Technical Reports Server (NTRS)

Stockton, R.

1979-01-01

The development of a microprocessor controller which provides multimode operational capability for the Electronic Switching Spherical Array (ESSA) Antenna is described. The best set of operating conditions were determined and the performance of an ESSA antenna was demonstrated in the following modes: (1) omni; (2) acquisition/track; (3) directive; and (4) multibeam. The control algorithms, software flow diagrams, and electronic circuitry were developed. The microprocessor and control electronics were built and interfaced with the antenna to carry out performance testing. The acquisition/track mode for users in the Tracking and Data Relay Satellite System is emphasized.
DSS 13 Microprocessor Antenna Controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1984-01-01

A microprocessor based antenna controller system developed as part of the unattended station project for DSS 13 is described. Both the hardware and software top level designs are presented and the major problems encounted are discussed. Developments useful to related projects include a JPL standard 15 line interface using a single board computer, a general purpose parser, a fast floating point to ASCII conversion technique, and experience gained in using off board floating point processors with the 8080 CPU.
Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port.
Recent Developments: PKI Square Dish for the Soleras Project

NASA Technical Reports Server (NTRS)

Rogers, W. E.

1984-01-01

The Square Dish solar collectors are subjected to rigorous design attention regarding corrosion at the site, and certification of the collector structure. The microprocessor controls and tracking mechanisms are improved in the areas of fail safe operations, durability, and low parasitic power requirements. Prototype testing demonstrates performance efficiency of approximately 72% at 730 F outlet temperature. Studies are conducted that include developing formal engineering design studies, developing formal engineering design drawing and fabrication details, establishing subcontracts for fabrication of major components, and developing a rigorous quality control system. The improved design is more cost effective to product and the extensive manuals developed for assembly and operation/maintenance result in faster field assembly and ease of operation.
Recent developments: PKI square dish for the Soleras Project

NASA Astrophysics Data System (ADS)

Rogers, W. E.

1984-03-01

The Square Dish solar collectors are subjected to rigorous design attention regarding corrosion at the site, and certification of the collector structure. The microprocessor controls and tracking mechanisms are improved in the areas of fail safe operations, durability, and low parasitic power requirements. Prototype testing demonstrates performance efficiency of approximately 72% at 730 F outlet temperature. Studies are conducted that include developing formal engineering design studies, developing formal engineering design drawing and fabrication details, establishing subcontracts for fabrication of major components, and developing a rigorous quality control system. The improved design is more cost effective to product and the extensive manuals developed for assembly and operation/maintenance result in faster field assembly and ease of operation.
FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.
Self-Checking Pairs Of Microprocessors

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1995-01-01

Method of imparting fault tolerance to computer system provides for immediate detection of faults at microprocessor level. Shadow microprocessor provides nominal duplicate outputs to verify functioning of main microprocessor. When output signal on any pin of one microprocessor differs from that on corresponding pin of other microprocessor, comparator puts out alarm signal.
Validation of a wireless modular monitoring system for structures

NASA Astrophysics Data System (ADS)

Lynch, Jerome P.; Law, Kincho H.; Kiremidjian, Anne S.; Carryer, John E.; Kenny, Thomas W.; Partridge, Aaron; Sundararajan, Arvind

2002-06-01

A wireless sensing unit for use in a Wireless Modular Monitoring System (WiMMS) has been designed and constructed. Drawing upon advanced technological developments in the areas of wireless communications, low-power microprocessors and micro-electro mechanical system (MEMS) sensing transducers, the wireless sensing unit represents a high-performance yet low-cost solution to monitoring the short-term and long-term performance of structures. A sophisticated reduced instruction set computer (RISC) microcontroller is placed at the core of the unit to accommodate on-board computations, measurement filtering and data interrogation algorithms. The functionality of the wireless sensing unit is validated through various experiments involving multiple sensing transducers interfaced to the sensing unit. In particular, MEMS-based accelerometers are used as the primary sensing transducer in this study's validation experiments. A five degree of freedom scaled test structure mounted upon a shaking table is employed for system validation.
Development of a preprototype Sabatier CO2 reduction subsystem

NASA Technical Reports Server (NTRS)

Kleiner, G. N.; Birbara, P.

1981-01-01

A lightweight, quick starting reactor utilizes a highly active and physically durable methanation catalyst composed of ruthenium on alumina. The use of this improved catalyst permits a single straight through plug flow design with an average lean component H2/CO2 conversion efficiency of over 99% over a range of H2/CO2 molar ratios of 1.8 to 5 while operating with flows equivalent to a crew size of one person steadystate to 3 persons cyclical. The reactor requires no heater operation after start-up even during simulated 55 minute lightside/39 minute darkside orbital operation over the above range of molar ratios and crew loadings. Subsystem performance was proven by parametric testing and endurance testing over a wide range of crew sizes and metabolic loadings. The subsystem's operation and performance is controlled by a microprocessor and displayed on a nineteen inch multi-colored cathode ray tube.
Supercritical water oxidation of products of human metabolism

NASA Technical Reports Server (NTRS)

Tester, Jefferson W.; Orge A. achelling, Richard K. ADTHOMASSON; Orge A. achelling, Richard K. ADTHOMASSON

1986-01-01

Although the efficient destruction of organic material was demonstrated in the supercritical water oxidation process, the reaction kinetics and mechanisms are unknown. The kinetics and mechanisms of carbon monoxide and ammonia oxidation in and reaction with supercritical water were studied experimentally. Experimental oxidation of urine and feces in a microprocessor controlled system was performed. A minaturized supercritical water oxidation process for space applications was design, including preliminary mass and energy balances, power, space and weight requirements.
A real time, FEM based optimal control algorithm and its implementation using parallel processing hardware (transistors) in a microprocessor environment

NASA Technical Reports Server (NTRS)

Patten, William Neff

1989-01-01

There is an evident need to discover a means of establishing reliable, implementable controls for systems that are plagued by nonlinear and, or uncertain, model dynamics. The development of a generic controller design tool for tough-to-control systems is reported. The method utilizes a moving grid, time infinite element based solution of the necessary conditions that describe an optimal controller for a system. The technique produces a discrete feedback controller. Real time laboratory experiments are now being conducted to demonstrate the viability of the method. The algorithm that results is being implemented in a microprocessor environment. Critical computational tasks are accomplished using a low cost, on-board, multiprocessor (INMOS T800 Transputers) and parallel processing. Progress to date validates the methodology presented. Applications of the technique to the control of highly flexible robotic appendages are suggested.
Teacher Training for High Technology. Final Report.

ERIC Educational Resources Information Center

Goettmann, Thomas L.

The objective of this project was to develop computer literacy and a working knowledge of microprocessor applications and digital circuits for teachers in selected vocational subject areas. Twenty-four vocational trade and industry teachers completed 16 hours of training in microprocessor skills for computerized instruction and curriculum update.…
High Stability Metal-Protein Interactions Evaluated by Microcalorimetry

DTIC Science & Technology

2016-04-29

microprocessor -controlled internal vacuum pump runs for a 90 second period, then it evaluates the vacuum pressure attained, and if that value meets spec...and the other with the software. There is a place in the wash module program where the ITC’s microprocessor - controlled internal vacuum pump runs for
An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

NASA Astrophysics Data System (ADS)

Chandaliya, Mudit; Chaturvedi, Nitin; Gurunarayanan, S.

2018-03-01

The current microprocessors has shown a remarkable performance and memory capacity improvement since its innovation. However, due to power and thermal limitations, only a fraction of cores can operate at full frequency at any instant of time irrespective of the advantages of new technology generation. This phenomenon of under-utilization of microprocessor is called as dark silicon which leads to distraction in innovative computing. To overcome the limitation of utilization wall, IBM technologies explored and invented neurosynaptic system chips. It has opened a wide scope of research in the field of innovative computing, technology, material sciences, machine learning etc. In this paper, we first reviewed the diverse stages of research that have been influential in the innovation of neurosynaptic architectures. These, architectures focuses on the development of brain-like framework which is efficient enough to execute a broad set of computations in real time while maintaining ultra-low power consumption as well as area considerations in mind. We also reveal the inadvertent challenges and the opportunities of designing neuromorphic systems as presented by the existing technologies in the dark silicon era, which constitute the utmost area of research in future.
Report to Congress on the Activities of the DoD Office of Technology Transition

DTIC Science & Technology

2006-08-01

a 4:1 return- on -investment (ROI) to DoD from licensing revenues, CRADAs, and other partnerships. In addition, the ...nutritional high energy bar for the troops. The result was the “HooAH!” bar. Based on an invention at Natick and through a CRADA with MGM Mars, inc...production capacities for high performance RH microprocessors with a progression from radiation tolerant to radiation
Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

PubMed

Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.
Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

NASA Astrophysics Data System (ADS)

Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.
RISC Processors and High Performance Computing

NASA Technical Reports Server (NTRS)

Saini, Subhash; Bailey, David H.; Lasinski, T. A. (Technical Monitor)

1995-01-01

In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.
Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.
Microprocessor Control Design for a Low-Head Crossflow Turbine.

DTIC Science & Technology

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

NASA Technical Reports Server (NTRS)

Srivas, Mandayam; Bickford, Mark

1991-01-01

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.
Report on phase 1 of the Microprocessor Seminar. [and associated large scale integration

NASA Technical Reports Server (NTRS)

1977-01-01

Proceedings of a seminar on microprocessors and associated large scale integrated (LSI) circuits are presented. The potential for commonality of device requirements, candidate processes and mechanisms for qualifying candidate LSI technologies for high reliability applications, and specifications for testing and testability were among the topics discussed. Various programs and tentative plans of the participating organizations in the development of high reliability LSI circuits are given.
Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad H.

2004-01-01

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.
Design of the Bus Interface Unit for the Distributed Processor/Memory System.

DTIC Science & Technology

1976-12-01

microroutine flowchart developed. Once this had been done , a high-speed, flexible microprocessor that would be adapt- able to a hardware...routine) was translated Into microcode and provide the mnemonic code and flowchart , Chapter V summarizes and discusses actual system construction...Fig. 11. This diagram shows that the BIU is driven by Interrupt stimuli which select the beginn ing address of the appropriate microroutine rather
A programmable transformer coupled converter for high-power space applications

NASA Technical Reports Server (NTRS)

Kapustka, R. E.; Bush, J. R., Jr.; Graves, J. R.; Lanier, J. R., Jr.

1986-01-01

A programmable transformer coupled converter (PTCC) is being developed by NASA/Marshall Space Flight Center for application in future large space power systems. The PTCC uses an internal microprocessor to control the output characteristics of its three Cuk integrated magnetics type power stages which have a combined capability of 5.4 kW (30 V at 180 A). Details of design trade-offs and test results are presented.
Communications Satellite Systems Conference, 9th, San Diego, CA, March 7-11, 1982, Collection of Technical Papers

NASA Astrophysics Data System (ADS)

The Shuttle-to-Geostationary Orbital Transfer by mid-level thrust is considered along with multibeam antenna concepts for global communications, the antenna pointing systems for large communication satellites, the connection phase of multidestination protocols for broadcast satellites, and an experiment in high-speed international packet switching. Attention is given to a dynamic switch matrix for the TDMA satellite switching system, the characterization of 16 bit microprocessors for space use, in-orbit operation and test of Intelsat V satellites, the first operational communications system via satellite in Europe, the Arab satellite communications systems, second generation business satellite systems for Europe, and a high performance Ku-band satellite for the 1980's. Other topics investigated are related to Ku-band terminal design tradeoffs, progress in the definition of the Italian satellite for domestic telecommunications, future global satellite systems for Intelsat, and satellite refuelling in orbit.
A microprocessor tester for the treat upgrade reactor trip system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lenkszus, F.R.; Bucher, R.G.

1985-02-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. To improve the analytical extrapolation of test results to full-size assembly bundles, the facility upgrade will increase the maximum size of the test bundle from 7 to 37 fuel pins. By creating a core convertor zone around the test location, the neutron spectrum incident on the test assembly will be hardened and the maximum energy deposited in the sample will be increased. In addition, a programmable Automated Reactor Control System (ARCS) willmore » permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations. A quantitative reliability analysis of the RTS shows that the unreliability, that is, the probability of failure, is acceptable for a 10 hour mission time or risk interval.« less
The Roots of Beowulf

NASA Technical Reports Server (NTRS)

Fischer, James R.

2014-01-01

The first Beowulf Linux commodity cluster was constructed at NASA's Goddard Space Flight Center in 1994 and its origins are a part of the folklore of high-end computing. In fact, the conditions within Goddard that brought the idea into being were shaped by rich historical roots, strategic pressures brought on by the ramp up of the Federal High-Performance Computing and Communications Program, growth of the open software movement, microprocessor performance trends, and the vision of key technologists. This multifaceted story is told here for the first time from the point of view of NASA project management.
FEDS - An experiment with a microprocessor-based orbit determination system using TDRS data

NASA Technical Reports Server (NTRS)

Shank, D.; Pajerski, R.

1986-01-01

An experiment in microprocessor-based onboard orbit determination has been conducted at NASA's Goddard Space Flight Center. The experiment collected forward-link observation data in real time from a prototype transponder and performed orbit estimation on a typical low-earth scientific satellite. This paper discusses the hardware and organizational configurations of the experiment, the structure of the onboard software, the mathematical models, and the experiment results.
Industry Study, Electronics Industry, Spring 2009

DTIC Science & Technology

2009-01-01

Toshiba, Samsung , and NEC.7 The microprocessor is a central processing unit containing hundreds of millions of transistors and logic to perform...business with an 11.7% market share followed closely by Samsung with a 10.3% market share.40 Intel is the leader in the production of microprocessors...while Samsung is the leading memory chip producer. Other US chip manufacturers include Texas Instruments (TI), Advanced Micro Devices (AMD), Micron
Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Choi, G.; Iyer, R. K.

1990-01-01

A simulation study is described which predicts the susceptibility of an advanced control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor and it incorporates fault-tolerant techniques. The system under test and the method to perform the transient injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection.
Specifications Physiological Monitoring System

NASA Technical Reports Server (NTRS)

1985-01-01

The operation of a physiological monitoring system (PMS) is described. Specifications were established for performance, design, interface, and test requirements. The PMS is a compact, microprocessor-based system, which can be worn in a pack on the body or may be mounted on a Spacelab rack or other appropriate structure. It consists of two modules, the Data Control Unit (DCU) and the Remote Control/Display Unit (RCDU). Its purpose is to collect and distribute data from physiological experiments in the Spacelab and in the Orbiter.
Towards a DNA Nanoprocessor: Reusable Tile-Integrated DNA Circuits.

PubMed

Gerasimova, Yulia V; Kolpashchikov, Dmitry M

2016-08-22

Modern electronic microprocessors use semiconductor logic gates organized on a silicon chip to enable efficient inter-gate communication. Here, arrays of communicating DNA logic gates integrated on a single DNA tile were designed and used to process nucleic acid inputs in a reusable format. Our results lay the foundation for the development of a DNA nanoprocessor, a small and biocompatible device capable of performing complex analyses of DNA and RNA inputs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
An optimal controller for an electric ventricular-assist device: theory, implementation, and testing.

PubMed

Klute, G K; Tasch, U; Geselowitz, D B

1992-04-01

This paper addresses the development and testing of an optimal position feedback controller for the Penn State electric ventricular-assist device (EVAD). The control law is designed to minimize the expected value of the EVAD's power consumption for a targeted patient population. The closed-loop control law is implemented on an Intel 8096 microprocessor and in vitro test runs show that this controller improves the EVAD's efficiency by 15-21%, when compared with the performance of the currently used feedforward control scheme.
Will Moores law be sufficient?

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik P.

2004-07-01

It seems well understood that supercomputer simulation is an enabler for scientific discoveries, weapons, and other activities of value to society. It also seems widely believed that Moore's Law will make progressively more powerful supercomputers over time and thus enable more of these contributions. This paper seeks to add detail to these arguments, revealing them to be generally correct but not a smooth and effortless progression. This paper will review some key problems that can be solved with supercomputer simulation, showing that more powerful supercomputers will be useful up to a very high yet finite limit of around 1021 FLOPSmore » (1 Zettaflops) . The review will also show the basic nature of these extreme problems. This paper will review work by others showing that the theoretical maximum supercomputer power is very high indeed, but will explain how a straightforward extrapolation of Moore's Law will lead to technological maturity in a few decades. The power of a supercomputer at the maturity of Moore's Law will be very high by today's standards at 1016-1019 FLOPS (100 Petaflops to 10 Exaflops), depending on architecture, but distinctly below the level required for the most ambitious applications. Having established that Moore's Law will not be that last word in supercomputing, this paper will explore the nearer term issue of what a supercomputer will look like at maturity of Moore's Law. Our approach will quantify the maximum performance as permitted by the laws of physics for extension of current technology and then find a design that approaches this limit closely. We study a 'multi-architecture' for supercomputers that combines a microprocessor with other 'advanced' concepts and find it can reach the limits as well. This approach should be quite viable in the future because the microprocessor would provide compatibility with existing codes and programming styles while the 'advanced' features would provide a boost to the limits of performance.« less
Network Structures for Distributed Situation Assessment

DTIC Science & Technology

1980-08-01

name a few-can contribute to the study of DAI. Presumably, DAI will advance these fields as well by providing a modeling technology suitable for precise...moreover, current SA sys- tems are highly centralized and vulnerable. Technological advances in cheap sen- sors, microprocessors, packet radio...communications, and artificial intelligence offer promising alternatives for performing military surveillance in many situations. A new approach now being
VASP-4096: a very high performance programmable device for digital media processing applications

NASA Astrophysics Data System (ADS)

Krikelis, Argy

2001-03-01

Over the past few years, technology drivers for microprocessors have changed significantly. Media data delivery and processing--such as telecommunications, networking, video processing, speech recognition and 3D graphics--is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper presents the architecture of the VASP-4096 processor. VASP-4096 provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the VASP-4096 is the integration of thousands of processing units in a single chip that are capable of support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, VASP-4096 integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 Kbytes of Data Memory, and I/O interfaces. The SIMD processing in VASP-4096 implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate), and a 64- bit 66 MHz PCI interface. VASP-4096, compared with other processors architectures that support media processing, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re- used in future chip generations.
Could a neuroscientist understand a microprocessor?

DOE PAGES

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

2017-01-12

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less
Could a Neuroscientist Understand a Microprocessor?

PubMed Central

Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods. PMID:28081141
Could a Neuroscientist Understand a Microprocessor?

PubMed

Jonas, Eric; Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

Could a neuroscientist understand a microprocessor?

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less
Multi-bit operations in vertical spintronic shift registers

NASA Astrophysics Data System (ADS)

Lavrijsen, Reinoud; Petit, Dorothée C. M. C.; Fernández-Pacheco, Amalio; Lee, JiHyun; Mansell, Mansell; Cowburn, Russell P.

2014-03-01

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.
Multi-bit operations in vertical spintronic shift registers.

PubMed

Lavrijsen, Reinoud; Petit, Dorothée C M C; Fernández-Pacheco, Amalio; Lee, Jihyun; Mansell, Mansell; Cowburn, Russell P

2014-03-14

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.
The electronics system for the LBNL positron emission mammography (PEM) camera

NASA Astrophysics Data System (ADS)

Moses, W. W.; Young, J. W.; Baker, K.; Jones, W.; Lenox, M.; Ho, M. H.; Weng, M.

2001-06-01

Describes the electronics for a high-performance positron emission mammography (PEM) camera. It is based on the electronics for a human brain positron emission tomography (PET) camera (the Siemens/CTI HRRT), modified to use a detector module that incorporates a photodiode (PD) array. An application-specified integrated circuit (ASIC) services the photodetector (PD) array, amplifying its signal and identifying the crystal of interaction. Another ASIC services the photomultiplier tube (PMT), measuring its output and providing a timing signal. Field-programmable gate arrays (FPGAs) and lookup RAMs are used to apply crystal-by-crystal correction factors and measure the energy deposit and the interaction depth (based on the PD/PMT ratio). Additional FPGAs provide event multiplexing, derandomization, coincidence detection, and real-time rebinning. Embedded PC/104 microprocessors provide communication, real-time control, and configure the system. Extensive use of FPGAs make the overall design extremely flexible, allowing many different functions (or design modifications) to be realized without hardware changes. Incorporation of extensive onboard diagnostics, implemented in the FPGAs, is required by the very high level of integration and density achieved by this system.
Application of Fault-Tolerant Computing For Spacecraft Using Commercial-Off-The-Shelf Microprocessors

DTIC Science & Technology

2000-06-01

real - time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation-induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware
A 20 MHz CMOS reorder buffer for a superscalar microprocessor

NASA Technical Reports Server (NTRS)

Lenell, John; Wallace, Steve; Bagherzadeh, Nader

1992-01-01

Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.
A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.
Microprocessor-based multichannel flutter monitor using dynamic strain gage signals

NASA Technical Reports Server (NTRS)

Smalley, R. R.

1976-01-01

Two microprocessor-based multichannel monitors for monitoring strain gage signals during aerodynamic instability (flutter) testing in production type turbojet engines were described. One system monitors strain gage signals in the time domain and gives an output indication whenever the signal amplitude of any gage exceeds a pre-set alarm or abort level for that particular gage. The second system monitors the strain gage signals in the frequency domain and therefore is able to use both the amplitude and frequency information. Thus, an alarm signal is given whenever the spectral content of the strain gage signal exceeds, at any point, its corresponding amplitude vs. frequency limit profiles. Each system design is described with details on design trade-offs, hardware, software, and operating experience.
Test report for single event effects of the 80386DX microprocessor

NASA Technical Reports Server (NTRS)

Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

1993-01-01

The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.
A real-time implementation of an advanced sensor failure detection, isolation, and accommodation algorithm

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Merrill, W. C.

1983-01-01

A sensor failure detection, isolation, and accommodation algorithm was developed which incorporates analytic sensor redundancy through software. This algorithm was implemented in a high level language on a microprocessor based controls computer. Parallel processing and state-of-the-art 16-bit microprocessors are used along with efficient programming practices to achieve real-time operation.
Small Private Key PKS on an Embedded Microprocessor

PubMed Central

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722
Small private key MQPKS on an embedded microprocessor.

PubMed

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.
DOE Office of Scientific and Technical Information (OSTI.GOV)

Madduri, Kamesh; Im, Eun-Jin; Ibrahim, Khaled Z.

The next decade of high-performance computing (HPC) systems will see a rapid evolution and divergence of multi- and manycore architectures as power and cooling constraints limit increases in microprocessor clock speeds. Understanding efficient optimization methodologies on diverse multicore designs in the context of demanding numerical methods is one of the greatest challenges faced today by the HPC community. In this paper, we examine the efficient multicore optimization of GTC, a petascale gyrokinetic toroidal fusion code for studying plasma microturbulence in tokamak devices. For GTC’s key computational components (charge deposition and particle push), we explore efficient parallelization strategies across a broadmore » range of emerging multicore designs, including the recently-released Intel Nehalem-EX, the AMD Opteron Istanbul, and the highly multithreaded Sun UltraSparc T2+. We also present the first study on tuning gyrokinetic particle-in-cell (PIC) algorithms for graphics processors, using the NVIDIA C2050 (Fermi). Our work discusses several novel optimization approaches for gyrokinetic PIC, including mixed-precision computation, particle binning and decomposition strategies, grid replication, SIMDized atomic floating-point operations, and effective GPU texture memory utilization. Overall, we achieve significant performance improvements of 1.3–4.7× on these complex PIC kernels, despite the inherent challenges of data dependency and locality. Finally, our work also points to several architectural and programming features that could significantly enhance PIC performance and productivity on next-generation architectures.« less
A microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Donaldson, J. A.; Crosier, W. G.

1979-01-01

The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.
Design of a cardiac monitor in terms of parameters of QRS complex.

PubMed

Chen, Zhen-cheng; Ni, Li-li; Su, Ke-ping; Wang, Hong-yan; Jiang, Da-zong

2002-08-01

Objective. To design a portable cardiac monitor system based on the available ordinary ECG machine and works on the basis of QRS parameters. Method. The 80196 single chip microcomputer was used as the central microprocessor and real time electrocardiac signal was collected and analyzed [correction of analysized] in the system. Result. Apart from the performance of an ordinary monitor, this machine possesses also the following functions: arrhythmia analysis, HRV analysis, alarm, freeze, and record of automatic papering. Convenient in carrying, the system is powered by AC or DC sources. Stability, low power and low cost are emphasized in the hardware design; and modularization method is applied in software design. Conclusion. Popular in usage and low cost made the portable monitor system suitable for use under simple conditions.
Developing prescribing guidelines for microprocessor-controlled prosthetic knees in the South East England.

PubMed

Sedki, Imad; Fisher, Keren

2015-06-01

Microprocessor-controlled prosthetic knees have gained increasing popularity over the last decade. Research supports their provision to address specific problems or to achieve certain rehabilitation goals. However, there are yet no agreed protocols or prescribing criteria to assist clinicians in the identification and appropriate selection of suitable users. The aim is to reach professionals' agreement on specific prescribing guidelines for microprocessor-controlled prosthetic knees. The study involved multidisciplinary teams from the Inter Regional Prosthetic Audit Group, representing nine Prosthetic Rehabilitation Centres in the South East England region. We used the Delphi technique with a total of three rounds to reach professionals' agreement. The prescribing guidelines were agreed and will be reviewed and updated depending on new research evidence and technical advances. This project is highly useful for professionals in a clinic setting to aid in appropriate patient selection and to justify the cost of prescribing microprocessor-controlled prosthetic knees. © The International Society for Prosthetics and Orthotics 2014.
Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII.

PubMed

Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

2012-09-14

Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 3'-5' exoribonuclease, Rrp6, to initiate RNAPII pausing and premature termination at the HIV-1 promoter through cleavage of the stem-loop RNA, TAR. Rrp6 further processes the cleavage product, which generates a small RNA that is required to mediate potent transcriptional repression and chromatin remodeling at the HIV-1 promoter. Using chromatin immunoprecipitation coupled to high-throughput sequencing (ChIP-seq), we identified cellular gene targets whose transcription is modulated by microprocessor. Our study reveals RNAPII pausing and premature termination mediated by the co-operative activity of ribonucleases, Drosha/Dgcr8, Xrn2, and Rrp6, as a regulatory mechanism of RNAPII-dependent transcription elongation. Copyright © 2012 Elsevier Inc. All rights reserved.
2nd Generation QUATARA Flight Computer Project

NASA Technical Reports Server (NTRS)

Falker, Jay; Keys, Andrew; Fraticelli, Jose Molina; Capo-Iugo, Pedro; Peeples, Steven

2015-01-01

Single core flight computer boards have been designed, developed, and tested (DD&T) to be flown in small satellites for the last few years. In this project, a prototype flight computer will be designed as a distributed multi-core system containing four microprocessors running code in parallel. This flight computer will be capable of performing multiple computationally intensive tasks such as processing digital and/or analog data, controlling actuator systems, managing cameras, operating robotic manipulators and transmitting/receiving from/to a ground station. In addition, this flight computer will be designed to be fault tolerant by creating both a robust physical hardware connection and by using a software voting scheme to determine the processor's performance. This voting scheme will leverage on the work done for the Space Launch System (SLS) flight software. The prototype flight computer will be constructed with Commercial Off-The-Shelf (COTS) components which are estimated to survive for two years in a low-Earth orbit.
Development of a patch type embedded cardiac function monitoring system using dual microprocessor for arrhythmia detection in heart disease patient.

PubMed

Jang, Yongwon; Noh, Hyung Wook; Lee, I B; Jung, Ji-Wook; Song, Yoonseon; Lee, Sooyeul; Kim, Seunghwan

2012-01-01

A patch type embedded cardiac function monitoring system was developed to detect arrhythmias such as PVC (Premature Ventricular Contraction), pause, ventricular fibrillation, and tachy/bradycardia. The overall system is composed of a main module including a dual processor and a Bluetooth telecommunication module. The dual microprocessor strategy minimizes power consumption and size, and guarantees the resources of embedded software programs. The developed software was verified with standard DB, and showed good performance.
Concept for a power system controller for large space electrical power systems

NASA Technical Reports Server (NTRS)

Lollar, L. F.; Lanier, J. R., Jr.; Graves, J. R.

1981-01-01

The development of technology for a fail-operatonal power system controller (PSC) utilizing microprocessor technology for managing the distribution and power processor subsystems of a large multi-kW space electrical power system is discussed. The specific functions which must be performed by the PSC, the best microprocessor available to do the job, and the feasibility, cost savings, and applications of a PSC were determined. A limited function breadboard version of a PSC was developed to demonstrate the concept and potential cost savings.

Prototype microprocessor controller. [for STDN antennas

NASA Technical Reports Server (NTRS)

Zarur, J.; Kraeuter, R.

1980-01-01

A microcomputer controller for STDN antennas was developed. The microcomputer technology reduces the system's physical size by the implementation in firmware of functions. The reduction in the number of components increases system reliability and similar benefit is derived when a graphic video display is substituted for several control and indicator panels. A substantial reduction in the number of cables, connectors, and mechanical switches is achieved. The microcomputer based system is programmed to perform calibration and diagnostics, to update the satellite orbital vector, and to communicate with other network systems. The design is applicable to antennas and lasers.
FAME, a microprocessor based front-end analysis and modeling environment

NASA Technical Reports Server (NTRS)

Rosenbaum, J. D.; Kutin, E. B.

1980-01-01

Higher order software (HOS) is a methodology for the specification and verification of large scale, complex, real time systems. The HOS methodology was implemented as FAME (front end analysis and modeling environment), a microprocessor based system for interactively developing, analyzing, and displaying system models in a low cost user-friendly environment. The nature of the model is such that when completed it can be the basis for projection to a variety of forms such as structured design diagrams, Petri-nets, data flow diagrams, and PSL/PSA source code. The user's interface with the analyzer is easily recognized by any current user of a structured modeling approach; therefore extensive training is unnecessary. Furthermore, when all the system capabilities are used one can check on proper usage of data types, functions, and control structures thereby adding a new dimension to the design process that will lead to better and more easily verified software designs.
Cumulative Timers for Microprocessors

NASA Technical Reports Server (NTRS)

Battle, John O.

2007-01-01

It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.
Sequoia: A fault-tolerant tightly coupled multiprocessor for transaction processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernstein, P.A.

1988-02-01

The Sequoia computer is a tightly coupled multiprocessor, and thus attains the performance advantages of this style of architecture. It avoids most of the fault-tolerance disadvantages of tight coupling by using a new fault-tolerance design. The Sequoia architecture is similar to other multimicroprocessor architectures, such as those of Encore and Sequent, in that it gives dozens of microprocessors shared access to a large main memory. It resembles the Stratus architecture in its extensive use of hardware fault-detection techniques. It resembles Stratus and Auragen in its ability to quickly recover all processes after a single point failure, transparently to the user.more » However, Sequoia is unique in its combination of a large-scale tightly coupled architecture with a hardware approach to fault tolerance. This article gives an overview of how the hardware architecture and operating systems (OS) work together to provide a high degree of fault tolerance with good system performance.« less
An electric artificial heart for clinical use.

PubMed Central

Pierce, W S; Rosenberg, G; Snyder, A J; Pae, W E; Donachy, J H; Waldhausen, J A

1990-01-01

Advances in microelectronics, high-strength magnets, and control system design now make replacement of the heart using an implantable, electrically powered pump feasible. The device described herein is a compact, dual pusher plate unit with valved polyurethane sac-type ventricles positioned at either end. The power unit consists of a small, brushless direct current motor and a motion translator. A microprocessor control system is used to regulate heart beat rate and provide left-right output balance. Bench studies lasting for as long as 1 year have been performed. Heart replacement with the electric heart has been performed in 18 calves since 1984. The longest survivor lived for more than 7 months. Among the causes of termination were component failure, thromboembolic complications, and bleeding. No major problem has been identified that precludes prolonged use of the electric heart. In the future the patient with end-stage heart disease will have an electric artificial heart as one therapeutic option. Images Figs. 1A and 1B. Fig. 3. Fig. 5. PMID:2396885
Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.
Microprocessor-controlled laser tracker for atmospheric sensing

NASA Technical Reports Server (NTRS)

Johnson, R. A.; Webster, C. R.; Menzies, R. T.

1985-01-01

An optical tracking system comprising a visible HeNe laser, an imaging detector, and a microprocessor-controlled mirror, has been designed to track a moving retroreflector located up to 500 m away from an atmospheric instrument and simultaneously direct spectrally tunable infrared laser radiation to the retroreflector for double-ended, long-path absorption measurements of atmospheric species. The tracker has been tested during the recent flight of a balloon-borne tunable diode laser absorption spectrometer which monitors the concentrations of stratospheric species within a volume defined by a 0.14-m-diameter retroreflector lowered 500 m below the instrument gondola.
Multiprocessor switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

2014-03-11

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus
The role of nanomaterials in redox-based supercapacitors for next generation energy storage devices.

PubMed

Zhao, Xin; Sánchez, Beatriz Mendoza; Dobson, Peter J; Grant, Patrick S

2011-03-01

The development of more efficient electrical storage is a pressing requirement to meet future societal and environmental needs. This demand for more sustainable, efficient energy storage has provoked a renewed scientific and commercial interest in advanced capacitor designs in which the suite of experimental techniques and ideas that comprise nanotechnology are playing a critical role. Capacitors can be charged and discharged quickly and are one of the primary building blocks of many types of electrical circuit, from microprocessors to large-sale power supplies, but usually have relatively low energy storage capability when compared with batteries. The application of nanostructured materials with bespoke morphologies and properties to electrochemical supercapacitors is being intensively studied in order to provide enhanced energy density without comprising their inherent high power density and excellent cyclability. In particular, electrode materials that exploit physical adsorption or redox reactions of electrolyte ions are foreseen to bridge the performance disparity between batteries with high energy density and capacitors with high power density. In this review, we present some of the novel nanomaterial systems applied for electrochemical supercapacitors and show how material morphology, chemistry and physical properties are being tailored to provide enhanced electrochemical supercapacitor performance.
The role of nanomaterials in redox-based supercapacitors for next generation energy storage devices

NASA Astrophysics Data System (ADS)

Zhao, Xin; Sánchez, Beatriz Mendoza; Dobson, Peter J.; Grant, Patrick S.

2011-03-01

The development of more efficient electrical storage is a pressing requirement to meet future societal and environmental needs. This demand for more sustainable, efficient energy storage has provoked a renewed scientific and commercial interest in advanced capacitor designs in which the suite of experimental techniques and ideas that comprise nanotechnology are playing a critical role. Capacitors can be charged and discharged quickly and are one of the primary building blocks of many types of electrical circuit, from microprocessors to large-sale power supplies, but usually have relatively low energy storage capability when compared with batteries. The application of nanostructured materials with bespoke morphologies and properties to electrochemical supercapacitors is being intensively studied in order to provide enhanced energy density without comprising their inherent high power density and excellent cyclability. In particular, electrode materials that exploit physical adsorption or redox reactions of electrolyte ions are foreseen to bridge the performance disparity between batteries with high energy density and capacitors with high power density. In this review, we present some of the novel nanomaterial systems applied for electrochemical supercapacitors and show how material morphology, chemistry and physical properties are being tailored to provide enhanced electrochemical supercapacitor performance.
Benchmark tests on the digital equipment corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wasserman, H.J.

1996-02-01

The second generation of the Digital Equipment Corp. (DEC) DECchip Alpha AXP microprocessor is referred to as the 21164. From the viewpoint of numerically-intensive computing, the primary difference between it and its predecessor, the 21064, is that the 21164 has twice the multiply/add throughput per clock period (CP), a maximum of two floating point operations (FLOPS) per CP vs. one for 21064. The AlphaServer 8400 is a shared-memory multiprocessor server system that can accommodate up to 12 CPUs and up to 14 GB of memory. In this report we will compare single processor performance of the 8400 system with thatmore » of the International Business Machines Corp. (IBM) RISC System/6000 POWER-2 microprocessor running at 66 MHz, the Silicon Graphics, Inc. (SGI) MIPS R8000 microprocessor running at 75 MHz, and the Cray Research, Inc. CRAY J90. The performance comparison is based on a set of Fortran benchmark codes that represent a portion of the Los Alamos National Laboratory supercomputer workload. The advantage of using these codes, is that the codes also span a wide range of computational characteristics, such as vectorizability, problem size, and memory access pattern. The primary disadvantage of using them is that detailed, quantitative analysis of performance behavior of all codes on all machines is difficult. One important addition to the benchmark set appears for the first time in this report. Whereas the older version was written for a vector processor, the newer version is more optimized for microprocessor architectures. Therefore, we have for the first time, an opportunity to measure performance on a single application using implementations that expose the respective strengths of vector and superscalar architecture. All results in this report are from single processors. A subsequent article will explore shared-memory multiprocessing performance of the 8400 system.« less
Software and languages for microprocessors

NASA Astrophysics Data System (ADS)

Williams, David O.

1986-08-01

This paper forms the basis for lectures given at the 6th Summer School on Computing Techniques in Physics, organised by the Computational Physics group of the European Physics Society, and held at the Hotel Ski, Nové Město na Moravě, Czechoslovakia, on 17-26 September 1985. Various types of microprocessor applications are discussed and the main emphasis of the paper is devoted to 'embedded' systems, where the software development is not carried out on the target microprocessor. Some information is provided on the general characteristics of microprocessor hardware. Various types of microprocessor operating system are compared and contrasted. The selection of appropriate languages and software environments for use with microprocessors is discussed. Mechanisms for interworking between different languages, including reasonable error handling, are treated. The CERN developed cross-software suite for the Motorola 68000 family is described. Some remarks are made concerning program tools applicable to microprocessors. PILS, a Portable Interactive Language System, which can be interpreted or compiled for a range of microprocessors, is described in some detail, and the implementation techniques are discussed.
An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…
Optical reversible programmable Boolean logic unit.

PubMed

Chattopadhyay, Tanay

2012-07-20

Computing with reversibility is the only way to avoid dissipation of energy associated with bit erase. So, a reversible microprocessor is required for future computing. In this paper, a design of a simple all-optical reversible programmable processor is proposed using a polarizing beam splitter, liquid crystal-phase spatial light modulators, a half-wave plate, and plane mirrors. This circuit can perform 16 logical operations according to three programming inputs. Also, inputs can be easily recovered from the outputs. It is named the "reversible programmable Boolean logic unit (RPBLU)." The logic unit is the basic building block of many complex computational operations. Hence the design is important in sense. Two orthogonally polarized lights are defined here as two logical states, respectively.
Generalized fast feedback system in the SLC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hendrickson, L.; Allison, S.; Gromme, T.

A generalized fast feedback system has been developed to stabilize beams at various locations in the SLC. The system is designed to perform measurements and change actuator settings to control beam states such as position, angle and energy on a pulse to pulse basis. The software design is based on the state space formalism of digital control theory. The system is database-driven, facilitating the addition of new loops without requiring additional software. A communications system, KISNet, provides fast communications links between microprocessors for feedback loops which involve multiple micros. Feedback loops have been installed in seventeen locations throughout the SLCmore » and have proven to be invaluable in stabilizing the machine.« less
Study and Design of Flight Data Recording Systems for Military Aircraft

DTIC Science & Technology

1976-06-01

minicomputer (PDP-11/ 40 ) with 24K of core memory and a disk operating system. Peripherals include a CRT terminal, two 9-track magnetic tape drives, a 19 high...in question-answer mode. The NTSB plans to adapt an existing routine to the PDP 11/ 40 which will prepare a ground track of the aircraft from the...20 microseconds). Like PMOS memory, multiple power supplies were required. The next generation of microprocessors were implemented on a 40 pin package
Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

ERIC Educational Resources Information Center

Sloan, M. E.

Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…
76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-07

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-781] In the Matter of Certain Microprocessors... importation of certain microprocessors, components thereof, and products containing same by reason of... microprocessors, components thereof, and products containing same that infringe one or more of claims 11-16, 41...
Transient Heat Conduction Simulation around Microprocessor Die

NASA Astrophysics Data System (ADS)

Nishi, Koji

This paper explains about fundamental formula of calculating power consumption of CMOS (Complementary Metal-Oxide-Semiconductor) devices and its voltage and temperature dependency, then introduces equation for estimating power consumption of the microprocessor for notebook PC (Personal Computer). The equation is applied to heat conduction simulation with simplified thermal model and evaluates in sub-millisecond time step calculation. In addition, the microprocessor has two major heat conduction paths; one is from the top of the silicon die via thermal solution and the other is from package substrate and pins via PGA (Pin Grid Array) socket. Even though the dominant factor of heat conduction is the former path, the latter path - from package substrate and pins - plays an important role in transient heat conduction behavior. Therefore, this paper tries to focus the path from package substrate and pins, and to investigate more accurate method of estimating heat conduction paths of the microprocessor. Also, cooling performance expression of heatsink fan is one of key points to assure result with practical accuracy, while finer expression requires more computation resources which results in longer computation time. Then, this paper discusses the expression to minimize computation workload with a practical accuracy of the result.
Design, construction, operation and costs of a modern small-scale fuel-alcohol plant

NASA Astrophysics Data System (ADS)

Leeper, S. A.; Dawley, L. J.; Wolfram, J. H.; Berglund, G. R.; Richardson, J. G.; McAtee, R. E.

1982-01-01

The design used for the small-scale fuel alcohol plant (SSFAP) is discussed. By incorporating a microprocessor into the plant design, most plant operations were automated and labor requirements were reduced. Continuous processing made energy conservation possible, thus reducing energy requirements. A low-temperature, continuous plug-flow cooker design made high yields possible. Ethanol was consistently produced at the SSFAP from corn at a yield of 2.6 gallons (anhydrous) per bushel and an energy requirement of 30,000 to 35,000 Btu/gallon (190-proof). In addition, barley, grain dust, and potato waste were converted at the SSFAP. The capacity of the SSFAP is 180,000 gallons per year (300 days operation). Competitively priced ethanol is produced at this capacity.

Application of digital control to a magnetic model suspension and balance model

NASA Technical Reports Server (NTRS)

Luh, P. B.; Covert, E. E.; Whitaker, H. P.; Haldeman, C. W.

1978-01-01

The feasibility of using a digital computer for performing the automatic control functions for a magnetic suspension and balance system (MSBS) for use with wind tunnel models was investigated. Modeling was done using both a prototype MSBS and a one dimensional magnetic balance. A microcomputer using the Intel 8080 microprocessor is described and results are given using this microprocessor to control the one dimensional balance. Hybrid simulations for one degree of freedom of the MSBS were also performed and are reported. It is concluded that use of a digital computer to control the MSBS is eminently feasible and should extend both the accuracy and utility of the system.
A Low-Power Instruction Issue Queue for Microprocessors

NASA Astrophysics Data System (ADS)

Watanabe, Shingo; Chiyonobu, Akihiro; Sato, Toshinori

Instruction issue queue is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction queue size should be increased. However, it is difficult to increase the size, since instruction queue is implemented by a content addressable memory (CAM) whose power and delay are much large. This paper introduces a low power and scalable instruction queue that replaces the CAM with a RAM. In this queue, instructions are explicitly woken up. Evaluation results show that the proposed instruction queue decreases processor performance by only 1.9% on average. Furthermore, the total energy consumption is reduced by 54% on average.
Quo vadis: Hydrologic inverse analyses using high-performance computing and a D-Wave quantum annealer

NASA Astrophysics Data System (ADS)

O'Malley, D.; Vesselinov, V. V.

2017-12-01

Classical microprocessors have had a dramatic impact on hydrology for decades, due largely to the exponential growth in computing power predicted by Moore's law. However, this growth is not expected to continue indefinitely and has already begun to slow. Quantum computing is an emerging alternative to classical microprocessors. Here, we demonstrated cutting edge inverse model analyses utilizing some of the best available resources in both worlds: high-performance classical computing and a D-Wave quantum annealer. The classical high-performance computing resources are utilized to build an advanced numerical model that assimilates data from O(10^5) observations, including water levels, drawdowns, and contaminant concentrations. The developed model accurately reproduces the hydrologic conditions at a Los Alamos National Laboratory contamination site, and can be leveraged to inform decision-making about site remediation. We demonstrate the use of a D-Wave 2X quantum annealer to solve hydrologic inverse problems. This work can be seen as an early step in quantum-computational hydrology. We compare and contrast our results with an early inverse approach in classical-computational hydrology that is comparable to the approach we use with quantum annealing. Our results show that quantum annealing can be useful for identifying regions of high and low permeability within an aquifer. While the problems we consider are small-scale compared to the problems that can be solved with modern classical computers, they are large compared to the problems that could be solved with early classical CPUs. Further, the binary nature of the high/low permeability problem makes it well-suited to quantum annealing, but challenging for classical computers.
1988 IEEE Aerospace Applications Conference, Park City, UT, Feb. 7-12, 1988, Digest

NASA Astrophysics Data System (ADS)

The conference presents papers on microwave applications, data and signal processing applications, related aerospace applications, and advanced microelectronic products for the aerospace industry. Topics include a high-performance antenna measurement system, microwave power beaming from earth to space, the digital enhancement of microwave component performance, and a GaAs vector processor based on parallel RISC microprocessors. Consideration is also given to unique techniques for reliable SBNR architectures, a linear analysis subsystem for CSSL-IV, and a structured singular value approach to missile autopilot analysis.
Mongoose ASIC microcontroller programming guide

NASA Astrophysics Data System (ADS)

Smith, Brian S.

1993-09-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.
Mongoose ASIC microcontroller programming guide

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1993-01-01

The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.
Autoregulatory mechanisms controlling the Microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2010-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature 22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part ofa newly identified regulatory mechanism controlling Microprocessor activity.
SMARBot: a modular miniature mobile robot platform

NASA Astrophysics Data System (ADS)

Meng, Yan; Johnson, Kerry; Simms, Brian; Conforth, Matthew

2008-04-01

Miniature robots have many advantages over their larger counterparts, such as low cost, low power, and easy to build a large scale team for complex tasks. Heterogeneous multi miniature robots could provide powerful situation awareness capability due to different locomotion capabilities and sensor information. However, it would be expensive and time consuming to develop specific embedded system for different type of robots. In this paper, we propose a generic modular embedded system architecture called SMARbot (Stevens Modular Autonomous Robot), which consists of a set of hardware and software modules that can be configured to construct various types of robot systems. These modules include a high performance microprocessor, a reconfigurable hardware component, wireless communication, and diverse sensor and actuator interfaces. The design of all the modules in electrical subsystem, the selection criteria for module components, and the real-time operating system are described. Some proofs of concept experimental results are also presented.
High-Speed Integrated Circuits for Military Applications.

DTIC Science & Technology

1979-11-01

1.5 pm circuits at the present time. " Market economics do not justify these circuits in the time frame of the VHSI program." See also Ref. 9. 7 per...on microprocessors currently in production, but the huge commercial market that is thought to exist for these devices when they can at last be...Subsection I, below). The single-chip microprocessor dominates the commercial market and those military applications for which their through- put is
Microprocessor activity controls differential miRNA biogenesis In Vivo.

PubMed

Conrad, Thomas; Marsico, Annalisa; Gehre, Maja; Orom, Ulf Andersson

2014-10-23

In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression. Copyright © 2014 The Authors. Published by Elsevier Inc. All rights reserved.
Microprocessor depends on hemin to recognize the apical loop of primary microRNA

PubMed Central

Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-01-01

Abstract Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction. PMID:29750274
Microprocessor depends on hemin to recognize the apical loop of primary microRNA.

PubMed

Nguyen, Tuan Anh; Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-06-20

Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction.
GaAs Supercomputing: Architecture, Language, And Algorithms For Image Processing

NASA Astrophysics Data System (ADS)

Johl, John T.; Baker, Nick C.

1988-10-01

The application of high-speed GaAs processors in a parallel system matches the demanding computational requirements of image processing. The architecture of the McDonnell Douglas Astronautics Company (MDAC) vector processor is described along with the algorithms and language translator. Most image and signal processing algorithms can utilize parallel processing and show a significant performance improvement over sequential versions. The parallelization performed by this system is within each vector instruction. Since each vector has many elements, each requiring some computation, useful concurrent arithmetic operations can easily be performed. Balancing the memory bandwidth with the computation rate of the processors is an important design consideration for high efficiency and utilization. The architecture features a bus-based execution unit consisting of four to eight 32-bit GaAs RISC microprocessors running at a 200 MHz clock rate for a peak performance of 1.6 BOPS. The execution unit is connected to a vector memory with three buses capable of transferring two input words and one output word every 10 nsec. The address generators inside the vector memory perform different vector addressing modes and feed the data to the execution unit. The functions discussed in this paper include basic MATRIX OPERATIONS, 2-D SPATIAL CONVOLUTION, HISTOGRAM, and FFT. For each of these algorithms, assembly language programs were run on a behavioral model of the system to obtain performance figures.
Microprocessor Based Temperature Control of Liquid Delivery with Flow Disturbances.

ERIC Educational Resources Information Center

Kaya, Azmi

1982-01-01

Discusses analytical design and experimental verification of a PID control value for a temperature controlled liquid delivery system, demonstrating that the analytical design techniques can be experimentally verified by using digital controls as a tool. Digital control instrumentation and implementation are also demonstrated and documented for…
Microtube strip heat exchanger

NASA Astrophysics Data System (ADS)

Doty, F. D.

1992-07-01

The purpose of this contract has been to explore the limits of miniaturization of heat exchangers with the goals of (1) improving the theoretical understanding of laminar heat exchangers, (2) evaluating various manufacturing difficulties, and (3) identifying major applications for the technology. A low-cost, ultra-compact heat exchanger could have an enormous impact on industry in the areas of cryocoolers and energy conversion. Compact cryocoolers based on the reverse Brayton cycle (RBC) would become practical with the availability of compact heat exchangers. Many experts believe that hardware advances in personal computer technology will rapidly slow down in four to six years unless lowcost, portable cryocoolers suitable for the desktop supercomputer can be developed. Compact refrigeration systems would permit dramatic advances in high-performance computer work stations with 'conventional' microprocessors operating at 150 K, and especially with low-cost cryocoolers below 77 K. NASA has also expressed strong interest in our MTS exchanger for space-based RBC cryocoolers for sensor cooling. We have demonstrated feasibility of higher specific conductance by a factor of five than any other work in high-temperature gas-to-gas exchangers. These laminar-flow, microtube exchangers exhibit extremely low pressure drop compared to alternative compact designs under similar conditions because of their much shorter flow length and larger total flow area for lower flow velocities. The design appears to be amenable to mass production techniques, but considerable process development remains. The reduction in materials usage and the improved heat exchanger performance promise to be of enormous significance in advanced engine designs and in cryogenics.
Energy Storage Flywheels on Spacecraft

NASA Technical Reports Server (NTRS)

Bartlett, Robert O.; Brown, Gary; Levinthal, Joel; Brodeur, Stephen (Technical Monitor)

2002-01-01

With advances in carbon composite material, magnetic bearings, microprocessors, and high-speed power switching devices, work has begun on a space qualifiable Energy Momentum Wheel (EMW). An EMW is a device that can be used on a satellite to store energy, like a chemical battery, and manage angular momentum, like a reaction wheel. These combined functions are achieved by the simultaneous and balanced operation of two or more energy storage flywheels. An energy storage flywheel typically consists of a carbon composite rotor driven by a brushless DC motor/generator. Each rotor has a relatively large angular moment of inertia and is suspended on magnetic bearings to minimize energy loss. The use of flywheel batteries on spacecraft will increase system efficiencies (mass and power), while reducing design-production time and life-cycle cost. This paper will present a discussion of flywheel battery design considerations and a simulation of spacecraft system performance utilizing four flywheel batteries to combine energy storage and momentum management for a typical LEO satellite. A proposed set of control laws and an engineering animation will also be presented. Once flight qualified and demonstrated, space flywheel batteries may alter the architecture of most medium and high-powered spacecraft.
Bus-Programmable Slave Card

NASA Technical Reports Server (NTRS)

Hall, William A.

1990-01-01

Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.
75 FR 54219 - Notice of Application for Approval of Discontinuance or Modification of a Railroad Signal System...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-09-03

... microprocessor-based systems. NJT proposes to verify and test signal locking systems controlled by microprocessor... interlocking, controlled points and other locations are controlled by solid-state vital microprocessor-based... components for control of both vital and non-vital functions. The logic does not change once a microprocessor...
A microprocessor controlled pressure scanning system

NASA Technical Reports Server (NTRS)

Anderson, R. C.

1976-01-01

A microprocessor-based controller and data logger for pressure scanning systems is described. The microcomputer positions and manages data from as many as four 48-port electro-mechanical pressure scanners. The maximum scanning rate is 80 pressure measurements per second (20 ports per second on each of four scanners). The system features on-line calibration, position-directed data storage, and once-per-scan display in engineering units of data from a selected port. The system is designed to be interfaced to a facility computer through a shared memory. System hardware and software are described. Factors affecting measurement error in this type of system are also discussed.
Design of Water Temperature Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

A fuel-efficient cruise performance model for general aviation piston engine airplanes. Ph.D. Thesis. Final Report

NASA Technical Reports Server (NTRS)

Parkinson, R. C. H.

1983-01-01

A fuel-efficient cruise performance model which facilitates maximizing the specific range of General Aviation airplanes powered by spark-ignition piston engines and propellers is presented. Airplanes of fixed design only are considered. The uses and limitations of typical Pilot Operating Handbook cruise performance data, for constructing cruise performance models suitable for maximizing specific range, are first examined. These data are found to be inadequate for constructing such models. A new model of General Aviation piston-prop airplane cruise performance is then developed. This model consists of two subsystem models: the airframe-propeller-atmosphere subsystem model; and the engine-atmosphere subsystem model. The new model facilitates maximizing specific range; and by virtue of its implicity and low volume data storge requirements, appears suitable for airborne microprocessor implementation.
An Intelligent Terminal for Access to a Medical Database

PubMed Central

Womble, M. E.; Wilson, S. D.; Keiser, H. N.; Tworek, M. L.

1978-01-01

Very powerful data base management systems (DBMS) now exist which allow medical personnel access to patient record data bases. DBMS's make it easy to retrieve either complete or abbreviated records of patients with similar characteristics. In addition, statistics on data base records are immediately accessible. However, the price of this power is a large computer with the inherent problems of access, response time, and reliability. If a general purpose, time-shared computer is used to get this power, the response time to a request can be either rapid or slow, depending upon loading by other users. Furthermore, if the computer is accessed via dial-up telephone lines, there is competition with other users for telephone ports. If either the DBMS or the host machine is replaced, the medical users, who are typically not sophisticated in computer usage, are forced to learn the new system. Microcomputers, because of their low cost and adaptability, lend themselves to a solution of these problems. A microprocessor-based intelligent terminal has been designed and implemented at the USAF School of Aerospace Medicine to provide a transparent interface between the user and his data base. The intelligent terminal system includes multiple microprocessors, floppy disks, a CRT terminal, and a printer. Users interact with the system at the CRT terminal using menu selection (framing). The system translates the menu selection into the query language of the DBMS and handles all actual communication with the DBMS and its host computer, including telephone dialing and sign on procedures, as well as the actual data base query and response. Retrieved information is stored locally for CRT display, hard copy production, and/or permanent retention. Microprocessor-based communication units provide security for sensitive medical data through encryption/decryption algorithms and high reliability error detection transmission schemes. Highly modular software design permits adapation to a different DBMS and/or host computer with only minor localized software changes. Importantly, this portability is completely transparent to system users. Although the terminal system is independent of the host computer and its DBMS, it has been linked to a UNIVAC 1108 computer supporting MRI's SYSTEM 2000 DBMS.
Gyrokinetic particle-in-cell optimization on emerging multi- and manycore platforms

DOE PAGES

Madduri, Kamesh; Im, Eun-Jin; Ibrahim, Khaled Z.; ...

2011-03-02

The next decade of high-performance computing (HPC) systems will see a rapid evolution and divergence of multi- and manycore architectures as power and cooling constraints limit increases in microprocessor clock speeds. Understanding efficient optimization methodologies on diverse multicore designs in the context of demanding numerical methods is one of the greatest challenges faced today by the HPC community. In this paper, we examine the efficient multicore optimization of GTC, a petascale gyrokinetic toroidal fusion code for studying plasma microturbulence in tokamak devices. For GTC’s key computational components (charge deposition and particle push), we explore efficient parallelization strategies across a broadmore » range of emerging multicore designs, including the recently-released Intel Nehalem-EX, the AMD Opteron Istanbul, and the highly multithreaded Sun UltraSparc T2+. We also present the first study on tuning gyrokinetic particle-in-cell (PIC) algorithms for graphics processors, using the NVIDIA C2050 (Fermi). Our work discusses several novel optimization approaches for gyrokinetic PIC, including mixed-precision computation, particle binning and decomposition strategies, grid replication, SIMDized atomic floating-point operations, and effective GPU texture memory utilization. Overall, we achieve significant performance improvements of 1.3–4.7× on these complex PIC kernels, despite the inherent challenges of data dependency and locality. Finally, our work also points to several architectural and programming features that could significantly enhance PIC performance and productivity on next-generation architectures.« less
Autoregulatory mechanisms controlling the microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2011-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.
Post-transcriptional control of DGCR8 expression by the Microprocessor.

PubMed

Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

2009-06-01

The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.
Single-event upset in advanced PowerPC microprocessors

NASA Technical Reports Server (NTRS)

Irom, F.; Swift, G. M.; Farmanesh, F.; Millward, D. G.

2002-01-01

Proton and heavy-ion single-event upset susceptibility has been measured for the MotorolaPowerPC7400. The results show that this advanced device has low upset susceptibility, despite the scaling and design advances.
OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems.

PubMed

Stone, John E; Gohara, David; Shi, Guochun

2010-05-01

We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures.
Microprocessors in Schools?

ERIC Educational Resources Information Center

Cuthbert, L. G.

1981-01-01

Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)
The special radiation-hardened processors for new highly informative experiments in space

NASA Astrophysics Data System (ADS)

Serdin, O. V.; Antonov, A. A.; Dubrovsky, A. G.; Novogilov, E. A.; Zuev, A. L.

2017-01-01

The article provides a detailed description of the series of special radiation-hardened microprocessor developed by SRISA for use in space technology. The microprocessors have 32-bit and 64-bit KOMDIV architecture with embedded SpaceWire, RapidIO, Ethernet and MIL-STD-1553B interfaces. These devices are used in space telescope GAMMA-400 data acquisition system, and may also be applied to other experiments in space (such as observatory “Millimetron” etc.).
Measures and procedures utilized to determine the added value of microprocessor-controlled prosthetic knee joints: a systematic review

PubMed Central

2013-01-01

Background The effectiveness of microprocessor-controlled prosthetic knee joints (MPKs) has been assessed using a variety of outcome measures in a variety of health and health-related domains. However, if the patient is to receive a prosthetic knee joint that enables him to function optimally in daily life, it is vital that the clinician has adequate information about the effects of that particular component on all aspects of persons’ functioning. Especially information concerning activities and participation is of high importance, as this component of functioning closely describes the person’s ability to function with the prosthesis in daily life. The present study aimed to review the outcome measures that have been utilized to assess the effects of microprocessor-controlled prosthetic knee joints (MPK), in comparison with mechanically controlled prosthetic knee joints, and aimed to classify these measures according to the components and categories of functioning defined by the International Classification of Functioning, Disability and Health (ICF). Subsequently, the gaps in the scientific evidence regarding the effectiveness of MPKs were determined. Methods A systematic literature search in 6 databases (i.e. PubMed, CINAHL, Cochrane Library, Embase, Medline and PsychInfo) identified scientific studies that compared the effects of using MPKs with mechanically controlled prosthetic knee joints on persons’ functioning. The outcome measures that have been utilized in those studies were extracted and categorized according to the ICF framework. Also, a descriptive analysis regarding all studies has been performed. Results A total of 37 studies and 72 outcome measures have been identified. The majority (67%) of the outcome measures that described the effects of using an MPK on persons’ actual performance with the prosthesis covered the ICF body functions component. Only 31% of the measures on persons’ actual performance investigated how an MPK may affect performance in daily life. Research also typically focused on young, fit and active persons. Conclusions Scientifically valid evidence regarding the performance of persons with an MPK in everyday life is limited. Future research should specifically focus on activities and participation to increase the understanding of the possible functional added value of MPKs. PMID:24279314
Measures and procedures utilized to determine the added value of microprocessor-controlled prosthetic knee joints: a systematic review.

PubMed

Theeven, Patrick J R; Hemmen, Bea; Brink, Peter R G; Smeets, Rob J E M; Seelen, Henk A M

2013-11-27

The effectiveness of microprocessor-controlled prosthetic knee joints (MPKs) has been assessed using a variety of outcome measures in a variety of health and health-related domains. However, if the patient is to receive a prosthetic knee joint that enables him to function optimally in daily life, it is vital that the clinician has adequate information about the effects of that particular component on all aspects of persons' functioning. Especially information concerning activities and participation is of high importance, as this component of functioning closely describes the person's ability to function with the prosthesis in daily life. The present study aimed to review the outcome measures that have been utilized to assess the effects of microprocessor-controlled prosthetic knee joints (MPK), in comparison with mechanically controlled prosthetic knee joints, and aimed to classify these measures according to the components and categories of functioning defined by the International Classification of Functioning, Disability and Health (ICF). Subsequently, the gaps in the scientific evidence regarding the effectiveness of MPKs were determined. A systematic literature search in 6 databases (i.e. PubMed, CINAHL, Cochrane Library, Embase, Medline and PsychInfo) identified scientific studies that compared the effects of using MPKs with mechanically controlled prosthetic knee joints on persons' functioning. The outcome measures that have been utilized in those studies were extracted and categorized according to the ICF framework. Also, a descriptive analysis regarding all studies has been performed. A total of 37 studies and 72 outcome measures have been identified. The majority (67%) of the outcome measures that described the effects of using an MPK on persons' actual performance with the prosthesis covered the ICF body functions component. Only 31% of the measures on persons' actual performance investigated how an MPK may affect performance in daily life. Research also typically focused on young, fit and active persons. Scientifically valid evidence regarding the performance of persons with an MPK in everyday life is limited. Future research should specifically focus on activities and participation to increase the understanding of the possible functional added value of MPKs.
Imaging Electron Spectrometer (IES) Electron Preprocessor (EPP) Design

NASA Technical Reports Server (NTRS)

Fennell, J. F.; Osborn, J. V.; Christensen, John L. (Technical Monitor)

2001-01-01

The Aerospace Corporation developed the Electron PreProcessor (EPP) to support the Imaging Electron Spectrometer (IES) that is part of the RAPID experiment on the ESA/NASA CLUSTER mission. The purpose of the EPP is to collect raw data from the IES and perform processing and data compression on it before transferring it to the RAPID microprocessor system for formatting and transmission to the CLUSTER satellite data system. The report provides a short history of the RAPID and CLUSTER programs and describes the EPP design. Four EPP units were fabricated, tested, and delivered for the original CLUSTER program. These were destroyed during a launch failure. Four more EPP units were delivered for the CLUSTER II program. These were successfully launched and are operating nominally on orbit.
A Microprocessor Project for Non-Electrical Engineering Students.

ERIC Educational Resources Information Center

Swingler, D. N.

1981-01-01

Offers rationale for and a description of a microprocessor-based control system project for mechanical engineering students. Includes reasons for selecting a Texas Instruments TM990/189 microprocessor system. (SK)
Microprocessor prosthetic knees.

PubMed

Berry, Dale

2006-02-01

This article traces the development of microprocessor prosthetic knees from early research in the 1970s to the present. Read about how microprocessor knees work, functional options, patient selection, and the future of this prosthetic.
15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2013 CFR

2013-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...
15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2010 CFR

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...
15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for ‘military...

Code of Federal Regulations, 2014 CFR

2014-01-01

... reexports of general purpose microprocessors for âmilitary end usesâ and to âmilitary end usersâ. 744.17... microprocessors for ‘military end uses’ and to ‘military end users’. (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...
15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2012 CFR

2012-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...
15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2011 CFR

2011-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...
Stair ascent with an innovative microprocessor-controlled exoprosthetic knee joint.

PubMed

Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

2012-12-01

Climbing stairs can pose a major challenge for above-knee amputees as a result of compromised motor performance and limitations to prosthetic design. A new, innovative microprocessor-controlled prosthetic knee joint, the Genium, incorporates a function that allows an above-knee amputee to climb stairs step over step. To execute this function, a number of different sensors and complex switching algorithms were integrated into the prosthetic knee joint. The function is intuitive for the user. A biomechanical study was conducted to assess objective gait measurements and calculate joint kinematics and kinetics as subjects ascended stairs. Results demonstrated that climbing stairs step over step is more biomechanically efficient for an amputee using the Genium prosthetic knee than the previously possible conventional method where the extended prosthesis is trailed as the amputee executes one or two steps at a time. There is a natural amount of stress on the residual musculoskeletal system, and it has been shown that the healthy contralateral side supports the movements of the amputated side. The mechanical power that the healthy contralateral knee joint needs to generate during the extension phase is also reduced. Similarly, there is near normal loading of the hip joint on the amputated side.

[Development of a portable ambulatory ECG monitor based on embedded microprocessor unit].

PubMed

Wang, Da-xiong; Wang, Guo-jun

2005-06-01

To develop a new kind of portable ambulatory ECG monitor. The hardware and software were designed based on RCA-CDP1802. New methods of ECG data compression and feature extraction of QRS complexes were applied to software design. A model for automatic arrhythmia analysis was established for real-time ambulatory ECG Data analysis. Compact, low power consumption and low cost were emphasized in the hardware design. This compact and light-weight monitor with low power consumption and high intelligence was capable of real-time monitoring arrhythmia for more than 48 h. More than ten types of arrhythmia could be detected, only the compressed abnormal ECG data was recorded and could be transmitted to the host if required. The monitor meets the design requirements and can be used for ambulatory ECG monitoring.
Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.
Sensor Control And Film Annotation For Long Range, Standoff Reconnaissance

NASA Astrophysics Data System (ADS)

Schmidt, Thomas G.; Peters, Owen L.; Post, Lawrence H.

1984-12-01

This paper describes a Reconnaissance Data Annotation System that incorporates off-the-shelf technology and system designs providing a high degree of adaptability and interoperability to satisfy future reconnaissance data requirements. The history of data annotation for reconnaissance is reviewed in order to provide the base from which future developments can be assessed and technical risks minimized. The system described will accommodate new developments in recording head assemblies and the incorporation of advanced cameras of both the film and electro-optical type. Use of microprocessor control and digital bus inter-face form the central design philosophy. For long range, high altitude, standoff missions, the Data Annotation System computes the projected latitude and longitude of central target position from aircraft position and attitude. This complements the use of longer ranges and high altitudes for reconnaissance missions.
Perceived self-efficacy and specific self-reported outcomes in persons with lower-limb amputation using a non-microprocessor-controlled versus a microprocessor-controlled prosthetic knee.

PubMed

Möller, Saffran; Hagberg, Kerstin; Samulesson, Kersti; Ramstrand, Nerrolyn

2018-04-01

To measure self-efficacy in a group of individuals who have undergone a lower-limb amputation and investigate the relationship between self-efficacy and prosthetic-specific outcomes including prosthetic use, mobility, amputation-related problems and global health. A second purpose was to examine if differences exist in outcomes based upon the type of prosthetic knee unit being used. Cross-sectional study using the General Self-Efficacy (GSE) Scale and the Questionnaire for Persons with a Transfemoral Amputation (Q-TFA). Forty-two individuals participated in the study. Twenty-three used a non-microprocessor-controlled prosthetic knee joint (non-MPK) and 19 used a microprocessor-controlled prosthetic knee joint (MPK). The study sample had quite high GSE scores (32/40). GSE scores were significantly correlated to the Q-TFA prosthetic use, mobility and problem scores. High GSE scores were related to higher levels of prosthetic use, mobility, global scores and negatively related to problem score. No significant difference was observed between individuals using a non-MPK versus MPK joints. Individuals with high self-efficacy used their prosthesis to a higher degree and high self-efficacy was related to higher level of mobility, global scores and fewer problems related to the amputation in individuals who have undergone a lower-limb amputation and were using a non-MPK or MPK knee. Implications for rehabilitation Perceived self-efficacy has has been shown to be related to quality of life, prosthetic mobility and capability as well as social activities in daily life. Prosthetic rehabilitation is primary focusing on physical improvement rather than psychological interventions. More attention should be directed towards the relationship between self-efficacy and prosthetic related outcomes during prosthetic rehabilitation after a lower-limb amputation.
Generic interpreters and microprocessor verification

NASA Technical Reports Server (NTRS)

Windley, Phillip J.

1990-01-01

The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work.
OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems

PubMed Central

Stone, John E.; Gohara, David; Shi, Guochun

2010-01-01

We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures. PMID:21037981
External Verification of SCADA System Embedded Controller Firmware

DTIC Science & Technology

2012-03-01

microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors
Optimal design of leak-proof SRAM cell using MCDM method

NASA Astrophysics Data System (ADS)

Wang, Qi; Kang, Sung-Mo

2003-04-01

As deep-submicron CMOS technology advances, on-chip cache has become a bottleneck on microprocessor's performance. Meanwhile, it also occupies a big percentage of processor area and consumes large power. Speed, power and area of SRAM are mutually contradicting, and not easy to be met simultaneously. Many existent leakage suppression techniques have been proposed, but they limit the circuit's performance. We apply a Multi-Criteria Decision Making strategy to perform a minimum delay-power-area optimization on SRAM circuit under some certain constraints. Based on an integrated device and circuit-level approach, we search for a process that yields a targeted composite performance. In consideration of the huge amount of simulation workload involved in the optimal design-seeking process, most of this process is automated to facilitate our goal-pursuant. With varying emphasis put on delay, power or area, different optimal SRAM designs are derived and a gate-oxide thickness scaling limit is projected. The result seems to indicate that a better composite performance could be achieved under a thinner oxide thickness. Under the derived optimal oxide thickness, the static leakage power consumption contributes less than 1% in the total power dissipation.
Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; White, Mark; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.
Versatile, low-cost, computer-controlled, sample positioning system for vacuum applications

NASA Technical Reports Server (NTRS)

Vargas-Aburto, Carlos; Liff, Dale R.

1991-01-01

A versatile, low-cost, easy to implement, microprocessor-based motorized positioning system (MPS) suitable for accurate sample manipulation in a Second Ion Mass Spectrometry (SIMS) system, and for other ultra-high vacuum (UHV) applications was designed and built at NASA LeRC. The system can be operated manually or under computer control. In the latter case, local, as well as remote operation is possible via the IEEE-488 bus. The position of the sample can be controlled in three linear orthogonal and one angular coordinates.
Microprocessor-based interface for oceanography

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1979-01-01

Ocean floor imaging system incorporates five identical microprocessor-based interface units each assigned to specific sonar instrument to simplify system. Central control module based on same microprocessor eliminates need for custom tailoring hardware interfaces for each instrument.
Phoenix, a High-Performance UNIX with an Emphasis on Dynamic Modification, Real-Time Response and Survivability

DTIC Science & Technology

1988-12-02

Include Area Code) I22c. OFIICE 5YMBOL Dr. David W. Hislop I I DD FORM 1473,84 MAR d3 APR edition may oe used until exnausteo. SECURITY CLASSIFICATION OF...Emulator for Performance Evaluation, CommUicanions ofILheACM23, 2 (Feb. 1980 ), 71-80. (4) Wirth, N., Microprocessor Architectures: A Comparison Based on...byte-addressing and has a 16-bit word 1980 decimal size. 3764B octal (denoted by the trailing "B") OCADH hexadeci’nal (denoted by the mailing "H") 1.1
Lunar material transport vehicle

NASA Technical Reports Server (NTRS)

Fisher, Charles D.; Lyons, Douglas; Wilkins, W. Allen, Jr.; Whitehead, Harry C., Jr.

1988-01-01

The proposed vehicle, the Lunar Material Transport Vehicle (LMTV), has a mission objective of efficient lunar soil material transport. The LMTV was designed to meet a required set of performance specifications while operating under a given set of constraints. The LMTV is essentially an articulated steering, double-ended dump truck. The vehicle moves on four wheels and has two identical chassis halves. Each half consists of a chassis frame, a material bucket, two wheels with integral curvilinear synchronous motors, a fuel cell and battery arrangement, an electromechanically actuated dumping mechanism, and a powerful microprocessor. The vehicle, as designed, is capable of transporting up to 200 cu ft of material over a one mile round trip per hour. The LMTV is capable of being operated from a variety of sources. The vehicle has been designed as simply as possible with attention also given to secondary usage of components.
General, database-driven fast-feedback system for the Stanford Linear Collider

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rouse, F.; Allison, S.; Castillo, S.

A new feedback system has been developed for stabilizing the SLC beams at many locations. The feedback loops are designed to sample and correct at the 60 Hz repetition rate of the accelerator. Each loop can be distributed across several of the standard 80386 microprocessors which control the SLC hardware. A new communications system, KISNet, has been implemented to pass signals between the microprocessors at this rate. The software is written in a general fashion using the state space formalism of digital control theory. This allows a new loop to be implemented by just setting up the online database andmore » perhaps installing a communications link. 3 refs., 4 figs.« less
Effect of various features on the life cycle cost of the timing/synchronization subsystem of the DCS digital communications network

NASA Technical Reports Server (NTRS)

Kimsey, D. B.

1978-01-01

The effect on the life cycle cost of the timing subsystem was examined, when these optional features were included in various combinations. The features included mutual control, directed control, double-ended reference links, independence of clock error measurement and correction, phase reference combining, self-organization, smoothing for link and nodal dropouts, unequal reference weightings, and a master in a mutual control network. An overall design of a microprocessor-based timing subsystem was formulated. The microprocessor (8080) implements the digital filter portion of a digital phase locked loop, as well as other control functions such as organization of the network through communication with processors at neighboring nodes.
A microprocessor based anti-aliasing filter for a PCM system

NASA Technical Reports Server (NTRS)

Morrow, D. C.; Sandlin, D. R.

1984-01-01

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.
A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

PubMed Central

González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

2012-01-01

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system. PMID:23201989
High-Resolution Gas Metering and Nonintrusive Appliance Load Monitoring System

NASA Astrophysics Data System (ADS)

Tewolde, Mahder

This thesis deals with design and implementation of a high-resolution metering system for residential natural gas meters. Detailed experimental measurements are performed on the meter to characterize and understand its measurement properties. Results from these experiments are used to develop a simple, fast and accurate technique to non-intrusively monitor the gas consumption of individual appliances in homes by resolving small amounts of gas usage. The technique is applied on an existing meter retrofitted with a module that includes a high-resolution encoder to collect gas flow data and a microprocessor to analyze and identify appliance load profiles. This approach provides a number of appealing features including low cost, easy installation and integration with automated meter reading (AMR) systems. The application of this method to residential gas meters currently deployed is also given. This is done by performing a load simulation on realistic gas loads with the aim of identifying the necessary parameters that minimize the cost and complexity of the mechanical encoder module. The primary benefits of the system are efficiency analysis, appliance health monitoring and real-time customer feedback of gas usage. Additional benefits of include the ability to detect very small leaks and theft. This system has the potential for wide scale market adoption.
An evaluation of NASA's program in human factors research: Aircrew-vehicle system interaction

NASA Technical Reports Server (NTRS)

1982-01-01

Research in human factors in the aircraft cockpit and a proposed program augmentation were reviewed. The dramatic growth of microprocessor technology makes it entirely feasible to automate increasingly more functions in the aircraft cockpit; the promise of improved vehicle performance, efficiency, and safety through automation makes highly automated flight inevitable. An organized data base and validated methodology for predicting the effects of automation on human performance and thus on safety are lacking and without such a data base and validated methodology for analyzing human performance, increased automation may introduce new risks. Efforts should be concentrated on developing methods and techniques for analyzing man machine interactions, including human workload and prediction of performance.
Comparative biomechanical analysis of current microprocessor-controlled prosthetic knee joints.

PubMed

Bellmann, Malte; Schmalz, Thomas; Blumentritt, Siegmar

2010-04-01

To investigate and identify functional differences of 4 microprocessor-controlled prosthetic knee joints (C-Leg, Hybrid Knee [also called Energy Knee], Rheo Knee, Adaptive 2). Tested situations were walking on level ground, on stairs and ramps; additionally, the fall prevention potentials for each design were examined. The measuring technology used included an optoelectronic camera system combined with 2 forceplates as well as a mobile spiroergometric system. The study was conducted in a gait laboratory. Subjects with unilateral transfemoral amputations (N=9; mobility grade, 3-4; age, 22-49y) were tested. Participants were fitted and tested with 4 different microprocessor-controlled knee joints. Static prosthetic alignment, time distance parameters, kinematic and kinetic data and metabolic energy consumption. Compared with the Hybrid Knee and the Adaptive 2, the C-Leg offers clear advantages in the provision of adequate swing phase flexion resistances and terminal extension damping during level walking at various speeds, especially at higher walking speeds. The Rheo Knee provides sufficient terminal extension; however, swing phase flexion resistances seem to be too low. The values for metabolic energy consumption show only slight differences during level walking. The joint resistances generated for descending stairs and ramps relieve the contralateral side to varying degrees. When walking on stairs, safety-relevant technical differences between the investigated joint types can be observed. Designs with adequate internal resistances offer stability advantages when the foot is positioned on the step. Stumble recovery tests reveal that the different knee joint designs vary in their effectiveness in preventing the patient from falling. The patient benefits provided by the investigated electronic prosthetic knee joints differ considerably. The C-Leg appears to offer the amputee greater functional and safety-related advantages than the other tested knee joints. Reduced loading of the contralateral side has been demonstrated during ramp and stair descent. Metabolic energy consumption does not vary significantly between the tested knees. Hence, this parameter seems not to be a suitable criterion for assessing microprocessor-controlled knee components. Copyright 2010 American Congress of Rehabilitation Medicine. Published by Elsevier Inc. All rights reserved.

Microprocessor dynamics and interactions at endogenous imprinted C19MC microRNA genes.

PubMed

Bellemer, Clément; Bortolin-Cavaillé, Marie-Line; Schmidt, Ute; Jensen, Stig Mølgaard Rask; Kjems, Jørgen; Bertrand, Edouard; Cavaillé, Jérôme

2012-06-01

Nuclear primary microRNA (pri-miRNA) processing catalyzed by the DGCR8-Drosha (Microprocessor) complex is highly regulated. Little is known, however, about how microRNA biogenesis is spatially organized within the mammalian nucleus. Here, we image for the first time, in living cells and at the level of a single microRNA cluster, the intranuclear distribution of untagged, endogenously-expressed pri-miRNAs generated at the human imprinted chromosome 19 microRNA cluster (C19MC), from the environment of transcription sites to single molecules of fully released DGCR8-bound pri-miRNAs dispersed throughout the nucleoplasm. We report that a large fraction of Microprocessor concentrates onto unspliced C19MC pri-miRNA deposited in close proximity to their genes. Our live-cell imaging studies provide direct visual evidence that DGCR8 and Drosha are targeted post-transcriptionally to C19MC pri-miRNAs as a preformed complex but dissociate separately. These dynamics support the view that, upon pri-miRNA loading and most probably concomitantly with Drosha-mediated cleavages, Microprocessor undergoes conformational changes that trigger the release of Drosha while DGCR8 remains stably bound to pri-miRNA.
Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

NASA Technical Reports Server (NTRS)

Rickard, D. A.; Bodenheimer, R. E.

1976-01-01

Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.
Microprocessor Airborne Data Acquisition & Replay (MADAR) System,

DTIC Science & Technology

1984-03-01

Time Record 7. TAPE USAGE 28 7.1 Geseral2 7.2 Tape Time Remanfng lbdocator 28 7.3 Tape Record Capacity 30 . 8. MODULE CONSTRUCTION 30 8.1 Gemeral...general purpose quick-fit type, calibrated for use with a range of different aircraft. The concept was modified such that the microprocessor module was not...dedicated to boom usage but a versatile instrument for other applications. The microprocessor module (Fig. 1) became known as the Microprocessor
Model based design introduction: modeling game controllers to microprocessor architectures

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; Badawy, Abdel-Hameed

2017-04-01

We present an introduction to model based design. Model based design is a visual representation, generally a block diagram, to model and incrementally develop a complex system. Model based design is a commonly used design methodology for digital signal processing, control systems, and embedded systems. Model based design's philosophy is: to solve a problem - a step at a time. The approach can be compared to a series of steps to converge to a solution. A block diagram simulation tool allows a design to be simulated with real world measurement data. For example, if an analog control system is being upgraded to a digital control system, the analog sensor input signals can be recorded. The digital control algorithm can be simulated with the real world sensor data. The output from the simulated digital control system can then be compared to the old analog based control system. Model based design can compared to Agile software develop. The Agile software development goal is to develop working software in incremental steps. Progress is measured in completed and tested code units. Progress is measured in model based design by completed and tested blocks. We present a concept for a video game controller and then use model based design to iterate the design towards a working system. We will also describe a model based design effort to develop an OS Friendly Microprocessor Architecture based on the RISC-V.
Apparatus Reviews.

ERIC Educational Resources Information Center

School Science Review, 1981

1981-01-01

Reviews apparatus design and instructional uses for Fume Cupboard Monitor, Plant Tissue Culture Kit, various equipment for electronic systems course, Welwyn Microprocessor-Tutor, Sweep Function Generator SFG 606, and Harris manufacturers materials--Regulated Power Supply Units, Electronic Current and Voltage Meters, Gas Preparation Kit, and…
Transcription of the Workshop on General Aviation Advanced Avionics Systems

NASA Technical Reports Server (NTRS)

Tashker, M. (Editor)

1975-01-01

Papers are presented dealing with the design of reliable, low cost, advanced avionics systems applicable to general aviation in the 1980's and beyond. Sensors, displays, integrated circuits, microprocessors, and minicomputers are among the topics discussed.
The Apple IIc.

ERIC Educational Resources Information Center

Freiberger, Paul

1984-01-01

Description of the portable Apple IIc includes its flat panel display; a new microprocessor, the 65CO2; its new design language; layout; documentation, including interactive tutorials; software support; and cost. Apple IIc's competitors and its new printer, the Scribe, are also discussed. (MBR)
Solid State Audio/Speech Processor Analysis.

DTIC Science & Technology

1980-03-01

techniques. The techniques were demonstrated to be worthwhile in an efficient realtime AWR system. Finally, microprocessor architectures were designed to...do not include custom chip development, detailed hardware design , construction or testing. ITTDCD is very encouraged by the results obtained in this...California, Berkley, was responsible for furnishing the simulation data of OD speech analysis techniques and for the design and development of the hardware OD
Single event effect testing of the Intel 80386 family and the 80486 microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moran, A.; LaBel, K.; Gates, M.

The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.
Microprocessors and the Curriculum.

ERIC Educational Resources Information Center

Pasahow, Edward J.

1981-01-01

Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)
Computer Electromagnetics and Supercomputer Architecture

NASA Technical Reports Server (NTRS)

Cwik, Tom

1993-01-01

The dramatic increase in performance over the last decade for microporcessor computations is compared with that for the supercomputer computations. This performance, the projected performance, and a number of other issues such as cost and the inherent pysical limitations in curent supercomputer technology have naturally led to parallel supercomputers and ensemble of interconnected microprocessors.
Multi-crop area estimation and mapping on a microprocessor/mainframe network

NASA Technical Reports Server (NTRS)

Sheffner, E.

1985-01-01

The data processing system is outlined for a 1985 test aimed at determining the performance characteristics of area estimation and mapping procedures connected with the California Cooperative Remote Sensing Project. The project is a joint effort of the USDA Statistical Reporting Service-Remote Sensing Branch, the California Department of Water Resources, NASA-Ames Research Center, and the University of California Remote Sensing Research Program. One objective of the program was to study performance when data processing is done on a microprocessor/mainframe network under operational conditions. The 1985 test covered the hardware, software, and network specifications and the integration of these three components. Plans for the year - including planned completion of PEDITOR software, testing of software on MIDAS, and accomplishment of data processing on the MIDAS-VAX-CRAY network - are discussed briefly.
Software resilience and the effectiveness of software mitigation in microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Baker, Zachary; Fairbanks, Tom

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less
Software resilience and the effectiveness of software mitigation in microcontrollers

DOE PAGES

Quinn, Heather; Baker, Zachary; Fairbanks, Tom; ...

2015-12-01

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less
Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond

NASA Astrophysics Data System (ADS)

Liebmann, Lars; Pileggi, Larry; Hibbeler, Jason; Rovner, Vyacheslav; Jhaveri, Tejas; Northrop, Greg

2009-03-01

The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed. Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a 65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the integrated process-design co-optimization, is introduced.
Machine learning on-a-chip: a high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications.

PubMed

Sun, Yuwen; Cheng, Allen C

2012-07-01

Artificial neural networks (ANNs) are a promising machine learning technique in classifying non-linear electrocardiogram (ECG) signals and recognizing abnormal patterns suggesting risks of cardiovascular diseases (CVDs). In this paper, we propose a new reusable neuron architecture (RNA) enabling a performance-efficient and cost-effective silicon implementation for ANN. The RNA architecture consists of a single layer of physical RNA neurons, each of which is designed to use minimal hardware resource (e.g., a single 2-input multiplier-accumulator is used to compute the dot product of two vectors). By carefully applying the principal of time sharing, RNA can multiplexs this single layer of physical neurons to efficiently execute both feed-forward and back-propagation computations of an ANN while conserving the area and reducing the power dissipation of the silicon. A three-layer 51-30-12 ANN is implemented in RNA to perform the ECG classification for CVD detection. This RNA hardware also allows on-chip automatic training update. A quantitative design space exploration in area, power dissipation, and execution speed between RNA and three other implementations representative of different reusable hardware strategies is presented and discussed. Compared with an equivalent software implementation in C executed on an embedded microprocessor, the RNA ASIC achieves three orders of magnitude improvements in both the execution speed and the energy efficiency. Copyright © 2012 Elsevier Ltd. All rights reserved.
Microprocessors in Systems Engineering at the U.S. Naval Academy.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

1982-01-01

Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)
Low-level processing for real-time image analysis

NASA Technical Reports Server (NTRS)

Eskenazi, R.; Wilf, J. M.

1979-01-01

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.
Electronic Design Automation (EDA) Roadmap Taskforce Report, Design of Microprocessors

DTIC Science & Technology

1999-04-01

through on time. Hence, the study is not a crystal-ball- gazing exercise, but a rigorous, schedulable plan of action to attain the goal. NTRS97...formats so as not to impose too heavy a maintenance burden on their users Object Interfaces eliminate these problems: • A tool that binds the interface ...and User Interface - Design Tool Communication - EDA System Extension Language - EDA Standards- Based Software Development Environment - Design and
Spinoff 2011

NASA Technical Reports Server (NTRS)

2012-01-01

Topics include: Bioreactors Drive Advances in Tissue Engineering; Tooling Techniques Enhance Medical Imaging; Ventilator Technologies Sustain Critically Injured Patients; Protein Innovations Advance Drug Treatments, Skin Care; Mass Analyzers Facilitate Research on Addiction; Frameworks Coordinate Scientific Data Management; Cameras Improve Navigation for Pilots, Drivers; Integrated Design Tools Reduce Risk, Cost; Advisory Systems Save Time, Fuel for Airlines; Modeling Programs Increase Aircraft Design Safety; Fly-by-Wire Systems Enable Safer, More Efficient Flight; Modified Fittings Enhance Industrial Safety; Simulation Tools Model Icing for Aircraft Design; Information Systems Coordinate Emergency Management; Imaging Systems Provide Maps for U.S. Soldiers; High-Pressure Systems Suppress Fires in Seconds; Alloy-Enhanced Fans Maintain Fresh Air in Tunnels; Control Algorithms Charge Batteries Faster; Software Programs Derive Measurements from Photographs; Retrofits Convert Gas Vehicles into Hybrids; NASA Missions Inspire Online Video Games; Monitors Track Vital Signs for Fitness and Safety; Thermal Components Boost Performance of HVAC Systems; World Wind Tools Reveal Environmental Change; Analyzers Measure Greenhouse Gasses, Airborne Pollutants; Remediation Technologies Eliminate Contaminants; Receivers Gather Data for Climate, Weather Prediction; Coating Processes Boost Performance of Solar Cells; Analyzers Provide Water Security in Space and on Earth; Catalyst Substrates Remove Contaminants, Produce Fuel; Rocket Engine Innovations Advance Clean Energy; Technologies Render Views of Earth for Virtual Navigation; Content Platforms Meet Data Storage, Retrieval Needs; Tools Ensure Reliability of Critical Software; Electronic Handbooks Simplify Process Management; Software Innovations Speed Scientific Computing; Controller Chips Preserve Microprocessor Function; Nanotube Production Devices Expand Research Capabilities; Custom Machines Advance Composite Manufacturing; Polyimide Foams Offer Superior Insulation; Beam Steering Devices Reduce Payload Weight; Models Support Energy-Saving Microwave Technologies; Materials Advance Chemical Propulsion Technology; and High-Temperature Coatings Offer Energy Savings.

Quantum Theory and the Silicon Revolution. Resources in Technology.

ERIC Educational Resources Information Center

Deal, Walter F., III

1995-01-01

This learning activity describes silicon as one of the most plentiful materials on earth, demonstrating how it supplies the building blocks for electronic devices such as transistors, integrated circuits, and microprocessors. It includes a design brief on control technology. (JOW)
75 FR 2591 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-15

... on vital microprocessor-based systems. CSXT proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative procedures every 4 years after initial... vital microprocessor-based systems. These systems utilize programmed logic equations in lieu of relays...
Redundant Asynchronous Microprocessor System

NASA Technical Reports Server (NTRS)

Meyer, G.; Johnston, J. O.; Dunn, W. R.

1985-01-01

Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.
NASA Communications Division (NASCOM) Tracking and Data Relay Satellite System (TDRSS) shuttle multiplexer-demultiplexer data system (MDM) and supporting items

NASA Technical Reports Server (NTRS)

New, S. R.

1981-01-01

The multiplexer-demultiplexer (MDM) project included the design, documentation, manufacture, and testing of three MDM Data Systems. The equipment is contained in 59 racks, and includes more than 3,000 circuit boards and 600 microprocessors. Spares, circuit card testers, a master set of programmable integrated circuits, and a program development system were included as deliverables. All three MDM's were installed, and were operationally tested. The systems performed well with no major problems. The progress and problems analysis, addresses schedule conformance, new technology, items awaiting government approval, and project conclusions are summarized. All contract modifications are described.
NASA Communications Division (NASCOM) Tracking and Data Relay Satellite System (TDRSS) shuttle multiplexer-demultiplexer data system (MDM) and supporting items

NASA Astrophysics Data System (ADS)

New, S. R.

1981-06-01

The multiplexer-demultiplexer (MDM) project included the design, documentation, manufacture, and testing of three MDM Data Systems. The equipment is contained in 59 racks, and includes more than 3,000 circuit boards and 600 microprocessors. Spares, circuit card testers, a master set of programmable integrated circuits, and a program development system were included as deliverables. All three MDM's were installed, and were operationally tested. The systems performed well with no major problems. The progress and problems analysis, addresses schedule conformance, new technology, items awaiting government approval, and project conclusions are summarized. All contract modifications are described.
Digital system upset. The effects of simulated lightning-induced transients on a general-purpose microprocessor

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1983-01-01

Flight critical computer based control systems designed for advanced aircraft must exhibit ultrareliable performance in lightning charged environments. Digital system upset can occur as a result of lightning induced electrical transients, and a methodology was developed to test specific digital systems for upset susceptibility. Initial upset data indicates that there are several distinct upset modes and that the occurrence of upset is related to the relative synchronization of the transient input with the processing sate of the digital system. A large upset test data base will aid in the formulation and verification of analytical upset reliability modeling techniques which are being developed.
System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.
Optoelectronic-cache memory system architecture.

PubMed

Chiarulli, D M; Levitan, S P

1996-05-10

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.
76 FR 61476 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-04

... locking; and 236.109, Time releases, timing relays and timing devices; on vital microprocessor-based... microprocessor-based locking systems. These tests, at this interval, would replace the tests currently required... listed in Exhibit B. 2. All future purchases of microprocessor-controlled interlocking locations. 3...
Development of a microprocessor controller for stand-alone photovoltaic power systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.
Microprocessor implementation of an FFT for ionospheric VLF observations

NASA Technical Reports Server (NTRS)

Elvidge, J.; Kintner, P.; Holzworth, R.

1984-01-01

A fast Fourier transform algorithm is implemented on a CMOS microprocessor for application to very low-frequency electric fields (less than 10 kHz) sensed on high-altitude scientific balloons. Two FFT's are calculated simultaneously by associating them with conjugate symmetric and conjugate antisymmetric results. One goal of the system was to detect spectral signatures associated with fast time variations present in natural signals such as whistlers and chorus. Although a full evaluation of the system was not possible for operational reasons, a measure of the system's success has been defined and evaluated.
Development report: Automatic System Test and Calibration (ASTAC) equipment

NASA Technical Reports Server (NTRS)

Thoren, R. J.

1981-01-01

A microcomputer based automatic test system was developed for the daily performance monitoring of wind energy system time domain (WEST) analyzer. The test system consists of a microprocessor based controller and hybrid interface unit which are used for inputing prescribed test signals into all WEST subsystems and for monitoring WEST responses to these signals. Performance is compared to theoretically correct performance levels calculated off line on a large general purpose digital computer. Results are displayed on a cathode ray tube or are available from a line printer. Excessive drift and/or lack of repeatability of the high speed analog sections within WEST is easily detected and the malfunctioning hardware identified using this system.
Design of Plant Eco-physiology Monitoring System Based on Embedded Technology

NASA Astrophysics Data System (ADS)

Li, Yunbing; Wang, Cheng; Qiao, Xiaojun; Liu, Yanfei; Zhang, Xinlu

A real time system has been developed to collect plant's growth information comprehensively. Plant eco-physiological signals can be collected and analyzed effectively. The system adopted embedded technology: wireless sensors network collect the eco-physiological information. Touch screen and ARM microprocessor make the system work independently without PC. The system is versatile and all parameters can be set by the touch screen. Sensors' intelligent compensation can be realized in this system. Information can be displayed by either graphically or in table mode. The ARM microprocessor provides the interface to connect with the internet, so the system support remote monitoring and controlling. The system has advantages of friendly interface, flexible construction and extension. It's a good tool for plant's management.
A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.
The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

ERIC Educational Resources Information Center

Garrett, Larry Neal

1983-01-01

The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)
Microprocessors in the Curriculum and the Classroom.

ERIC Educational Resources Information Center

Summers, M. K.

1978-01-01

This article, directed at teachers concerned with computer science courses at sixth-form level with no prior knowledge of microprocessors, provides a basic introduction, and describes possible applications of a microprocessor development system as a teaching aid in computer sciences courses in UK secondary school. (Author/RAO)
78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-16

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-781] Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements on the Public Interest AGENCY: U.S... a limited exclusion order as to subject Intel microprocessors, but that implementation be delayed...
Microcomputers in Special Education: Some New Opportunities, Some Old Problems.

ERIC Educational Resources Information Center

Hannaford, Alonzo E.

1983-01-01

Discusses ways in which microprocessors are aiding the handicapped in three major areas: (1) compensation (sensory, communication, and compensation for control); (2) management (personal and educational); and (3) instructional delivery (uses, advantages, problems, educational compatibility, instructional design, technical adequacy). (EJS)
Operation of commercially-based microcomputer technology in a space radiation environment

NASA Astrophysics Data System (ADS)

Yelverton, J. N.

This paper focuses on detection and recovery techniques that should enable the reliable operation of commercially-based microprocessor technology in the harsh radiation environment of space and at high altitudes. This approach is especially significant in light of the current shift in emphasis (due to cost) from space hardened Class-S parts qualification to a more direct use of commercial parts. The method should offset some of the concern that the newer high density state-of-the-art RISC and CISC microprocessors can be used in future space applications. Also, commercial aviation, should benefit, since radiation induced transients are a new issue arising from the increased quantities of microcomputers used in aircraft avionics.
Design and Evaluation of a Microprocessor Course Combining Three Cooperative Methods: SDLA, PjBL and CnBL

ERIC Educational Resources Information Center

Alorda, B.; Suenaga, K.; Pons, P.

2011-01-01

This paper reports on the design, implementation and assessment of a new approach course structure based on the combination of three cooperative methodologies. The main goal is to reduce the percentage of non-passed students focusing the learning process on students by offering different alternatives and motivational activities based on working in…

Differences in knee flexion between the Genium and C-Leg microprocessor knees while walking on level ground and ramps.

PubMed

Lura, Derek J; Wernke, Matthew M; Carey, Stephanie L; Kahle, Jason T; Miro, Rebecca M; Highsmith, M Jason

2015-02-01

Microprocessor knees have improved the gait and functional abilities of persons with transfemoral amputation. The Genium prosthetic knee offers an advanced sensor and control system designed to decrease impairment by: allowing greater stance phase flexion, easing transitions between gait phases, and compensating for changes in terrain. The aim of this study was to determine differences between the knee flexion angle of persons using the Genium knee, the C-Leg knee, and non-amputee controls; and to evaluate the impact the prostheses on gait and level of impairment of the user. This study used a randomized experimental crossover of persons with transfemoral amputation using the Genium and C-Leg microprocessor knees (n=25), with an observational sample of non-amputee controls (n=5). Gait analysis by 3D motion tracking of subjects ambulating at different speeds on level ground and on 5° and 10° ramps was completed. Use of the Genium resulted in a significant increase in peak knee flexion for swing (5°, p<0.01, d=0.34) and stance (2°, p<0.01, d=0.19) phases relative to C-Leg use. There was a high degree of variability between subjects, and significant differences still remain between the Genium group and the control group's knee flexion angles for most speeds and slopes. The Genium knee generally increases flexion in swing and stance, potentially decreasing the level of impairment for persons with transfemoral amputation. This study demonstrates functional differences between the C-Leg and Genium knees to help prosthetists determine if the Genium will provide functional benefits to individual patients. Copyright © 2014 Elsevier Ltd. All rights reserved.
Information Technologies for the 1980's: Lasers and Microprocessors.

ERIC Educational Resources Information Center

Mathews, William D.

This discussion of the development and application of lasers and microprocessors to information processing stresses laser communication in relation to capacity, reliability, and cost and the advantages of this technology to real-time information access and information storage. The increased capabilities of microprocessors are reviewed, and a…
Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.
Design of control system based on SCM music fountain

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao; Jiang, Suping

2018-06-01

The design of the design of a microprocessor controlled by simple circuit, introduced this design applied to the components, and draw the main flow chart presentation. System is the use of an external music source, the intensity of the input audio signal lights will affect the light off, the fountain spray of water level will be based on changes in the lantern light off. This design uses a single-chip system is simple, powerful, good reliability and low cost.
Microprocessor-controlled, wide-range streak camera

DOE Office of Scientific and Technical Information (OSTI.GOV)

Amy E. Lewis, Craig Hollabaugh

Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storagemore » using flash-based storage media. The camera’s user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.« less
Microprocessor-controlled wide-range streak camera

NASA Astrophysics Data System (ADS)

Lewis, Amy E.; Hollabaugh, Craig

2006-08-01

Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.
Design and validation of a low cost surface plasmon resonance bioanalyzer using microprocessors and a touch-screen monitor.

PubMed

Hu, Jiandong; Hu, Jingfang; Luo, Fukun; Li, Wei; Jiang, Guoliang; Li, Zhengfeng; Zhang, Runna

2009-03-15

An economical and high-performance bioanalyzer, with no use of laptop computer, based on the use of TSPR1k23 biosensors was systematically designed, and validated experimentally for its high performance. The analyzer is composed of a micro-flow cell, a thermoelectric cooler (TEC), a clamp, a touch-screen monitor, and an electronic control unit (ECU) incorporated with photoelectric conversion device. The micro-flow cell is made of stainless steel with high thermal conductivity, and the micro-flow system is based on PID temperature-controlled algorithm to keep the constant temperature (25 degrees C) of the liquid sample via thermal exchange with the clamp. With a peristaltic pump implemented by an injection loop flow system, the bioanalyzer allows the core sensor to be completely exposed to samples. The touch-screen monitor displays the normalized response signal values updated every 0.25s, with a typical noise level less than 5RU (response unit) within 2h. The bioanalyzer was validated using hepatitis B surface antigen (HBsAg) as an example. Anti-HBsAg monoclonal antibody is adhered to the surface of the sensor chip by a bifunctional cross-linker with the technology of self-assembly. The duration of the HBsAg measurement only lasts 5min with a dilution factor ranging from 200 to 1200, optimized with a R-squared value 0.998. The results suggested that the bioanalyzer has higher selectivity, lower cost, expanded detection limit, and shorter measuring time as compared with the HBsAg ELISA kit, especially for low concentrations of analyte.
Personal Cabin Pressure Monitor and Warning System

NASA Technical Reports Server (NTRS)

Zysko, Jan A. (Inventor)

2002-01-01

A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.
Personal Cabin Pressure Monitor and Warning System

NASA Astrophysics Data System (ADS)

Zysko, Jan A.

2002-09-01

A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.
DESIGN, DEVELOPMENT, AND FIELD DEMONSTRATION OF A REMOTELY DEPLOYABLE WATER QUALITY MONITORING SYSTEM

EPA Science Inventory

A prototype water quality monitoring system is described which offers almost continuous in situ monitoring. The two-man portable system features: (1) a microprocessor controlled central processing unit which allows preprogrammed sampling schedules and reprogramming in situ; (2) a...
Microprocessor Control For Liquid-Cooled Garment

NASA Technical Reports Server (NTRS)

Weaver, Charles S.

1990-01-01

Automatic control system maintains temperature of water-cooled garment within comfort zone while wearer's level of physical activity varies. Uncomfortable overshoots and undershoots of temperature eliminated. Designed for use in space suit, adaptable to other protective garments and to enclosed environments operating according to similar principles.
Microprocessor control and networking for the amps breadboard

NASA Technical Reports Server (NTRS)

Floyd, Stephen A.

1987-01-01

Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.
A monitoring system for vegetable greenhouses based on a wireless sensor network.

PubMed

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring.
Microprocessors: An Understandable Guide for the Classroom Teacher.

ERIC Educational Resources Information Center

Okinaka, Russell T.

A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…
JPRS Report, Science & Technology, USSR: Electronics & Electrical Engineering.

DTIC Science & Technology

1988-02-23

calculations or design examples are cited in this purely theoretical treatment, it is noted that experimental data from an on-board microprocessor controlled ...The requirements placed on the design of the semiconductor devices used in such systems can be divided into two groups : 1) Assure the requisite...describes a computer-aided approach to the design of resonant arrays that results in equal losses in the on and off states of such control devices. An
Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava

2017-01-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particlemore » tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.« less
Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

NASA Astrophysics Data System (ADS)

Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava; Lantz, Steven; Lefebvre, Matthieu; Masciovecchio, Mario; McDermott, Kevin; Riley, Daniel; Tadel, Matevž; Wittich, Peter; Würthwein, Frank; Yagil, Avi

2017-08-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.
Development of a differentially balanced magnetic bearing and control system for use with a flywheel energy storage system

NASA Technical Reports Server (NTRS)

Higgins, Mark A.; Plant, David P.; Ries, Douglas M.; Kirk, James A.; Anand, Davinder K.

1992-01-01

The purpose of a magnetically suspended flywheel energy storage system for electric utility load leveling is to provide a means to store energy during times when energy is inexpensive to produce and then return it to the customer during times of peak power demand when generated energy is most expensive. The design of a 20 kWh flywheel energy storage system for electric utility load leveling applications involves the successful integration of a number of advanced technologies so as to minimize the size and cost of the system without affecting its efficiency and reliability. The flywheel energy storage system uses a carbon epoxy flywheel, two specially designed low loss magnetic bearings, a high efficiency motor generator, and a 60 cycle AC power converter all integrated through a microprocessor controller. The basic design is discussed of each of the components that is used in the energy storage design.
Microprocessor controlled movement of solid colonic content using sequential neural electrical stimulation

PubMed Central

Amaris, M A; Rashev, P Z; Mintchev, M P; Bowes, K L

2002-01-01

Background and aims: Invoked peristaltic contractions and movement of solid content have not been attempted in normal canine colon. The purpose of this study was to determine if movement of solid content through the colon could be produced by microprocessor controlled sequential stimulation. Methods: The study was performed on six anaesthetised dogs. At laparotomy, a 15 cm segment of descending colon was selected, the proximal end closed with a purse string suture, and the distal end opened into a collecting container. Four sets of subserosal stimulating electrodes were implanted at 3 cm intervals. The segment of bowel was filled with a mixture of dog food and 50 plastic pellets before each of 2–5 random sessions of non-stimulated or stimulated emptying. Propagated contractions were generated using microprocessor controlled bipolar trains of 50 Hz rectangular voltage having 20 V (peak to peak) amplitude, 18 second stimulus duration, and a nine second phase lag between stimulation trains in sequential electrode sets. Results: Electrical stimulation using the above mentioned parameters resulted in powerful phasic contractions that closed the lumen. By phase locking the stimulation voltage between adjacent sets of electrodes, propagated contractions could be produced in an aboral or orad direction. The number of evacuated pellets during the stimulation sessions was significantly higher than during the non-stimulated sessions (p<0.01). Conclusions: Microprocessor controlled electrical stimulation accelerated movement of colonic content suggesting the possibility of future implantable colonic stimulators. PMID:11889065
Arranging computer architectures to create higher-performance controllers

NASA Technical Reports Server (NTRS)

Jacklin, Stephen A.

1988-01-01

Techniques for integrating microprocessors, array processors, and other intelligent devices in control systems are reviewed, with an emphasis on the (re)arrangement of components to form distributed or parallel processing systems. Consideration is given to the selection of the host microprocessor, increasing the power and/or memory capacity of the host, multitasking software for the host, array processors to reduce computation time, the allocation of real-time and non-real-time events to different computer subsystems, intelligent devices to share the computational burden for real-time events, and intelligent interfaces to increase communication speeds. The case of a helicopter vibration-suppression and stabilization controller is analyzed as an example, and significant improvements in computation and throughput rates are demonstrated.

Design studies for a technology assessment receiver for global positioning system

NASA Technical Reports Server (NTRS)

Painter, J. H.

1981-01-01

The operational conditions of a radio receiver - microprocessor for the global positioning system are studied. Navigation fundamentals and orbit characterization are reviewed. The global positioning system is described with emphasis upon signal structure and satellite positioning. Ranging and receiver processing techniques are discussed.
A proposed microcomputer implementation of an Omega navigation processor

NASA Technical Reports Server (NTRS)

Abel, J. D.

1976-01-01

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.
Development of an Automated Emergency Response System (AERS) for Rail Transit Systems

DOT National Transportation Integrated Search

1984-10-01

As a result of a fire in 1979 at the Bay Area Rapid Transit District (BART), a microprocessor-based information retrieval system was developed to aid in the emergency decision-making process. This system was proposed, designed and programmed by a sup...
An electronic flow control system for a variable-rate tree sprayer

USDA-ARS?s Scientific Manuscript database

Precise modulation of nozzle flow rates is a critical measure to achieve variable-rate spray applications. An electronic flow rate control system accommodating with microprocessors and pulse width modulation (PWM) controlled solenoid valves was designed to manipulate the output of spray nozzles inde...
Microprocessor-Controlled Laser Balancing System

NASA Technical Reports Server (NTRS)

Demuth, R. S.

1985-01-01

Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.
SEU induced errors observed in microprocessor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asenek, V.; Underwood, C.; Oldfield, M.

In this paper, the authors present software tools for predicting the rate and nature of observable SEU induced errors in microprocessor systems. These tools are built around a commercial microprocessor simulator and are used to analyze real satellite application systems. Results obtained from simulating the nature of SEU induced errors are shown to correlate with ground-based radiation test data.
DGCR8 HITS-CLIP reveals novel functions for the Microprocessor

PubMed Central

Macias, Sara; Plass, Mireya; Stajuda, Agata; Michlewski, Gracjan; Eyras, Eduardo; Cáceres, Javier F.

2012-01-01

The Drosha-DGCR8 complex (Microprocessor) is required for microRNA (miRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as the endonuclease. High-throughput sequencing and crosslinking immunoprecipitation (HITS-CLIP) was used to identify RNA targets of DGCR8 in human cells. Unexpectedly, miRNAs were not the most abundant targets. DGCR8-bound RNAs also comprised several hundred mRNAs as well as snoRNAs and long non-coding RNAs. We found that the Microprocessor controls the abundance of several mRNAs as well as of MALAT-1. By contrast, DGCR8-mediated cleavage of snoRNAs is independent of Drosha, suggesting the involvement of DGCR8 in cellular complexes with other endonucleases. Interestingly, binding of DGCR8 to cassette exons, acts as a novel mechanism to regulate the relative abundance of alternatively spliced isoforms. Collectively, these data provide new insights in the complex role of DGCR8 in controlling the fate of several classes of RNAs. PMID:22796965
Advanced development of a programmable power processor

NASA Technical Reports Server (NTRS)

Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

1980-01-01

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.
Design Considerations For Imaging Charge-Coupled Device (ICCD) Star Sensors

NASA Astrophysics Data System (ADS)

McAloon, K. J.

1981-04-01

A development program is currently underway to produce a precision star sensor using imaging charge coupled device (ICCD) technology. The effort is the critical component development phase for the Air Force Multi-Mission Attitude Determination and Autonomous Navigation System (MADAN). A number of unique considerations have evolved in designing an arcsecond accuracy sensor around an ICCD detector. Three tiers of performance criteria are involved: at the spacecraft attitude determination system level, at the star sensor level, and at the detector level. Optimum attitude determination system performance involves a tradeoff between Kalman filter iteration time and sensor ICCD integration time. The ICCD star sensor lends itself to the use of a new approach in the functional interface between the attitude determination system and the sensor. At the sensor level image data processing tradeoffs are important for optimum sensor performance. These tradeoffs involve the sensor optic configuration, the optical point spread function (PSF) size and shape, the PSF position locator, and the microprocessor locator algorithm. Performance modelling of the sensor mandates the use of computer simulation programs. Five key performance parameters at the ICCD detector level are defined. ICCD error characteristics have also been isolated to five key parameters.
Design of measuring system for wire diameter based on sub-pixel edge detection algorithm

NASA Astrophysics Data System (ADS)

Chen, Yudong; Zhou, Wang

2016-09-01

Light projection method is often used in measuring system for wire diameter, which is relatively simpler structure and lower cost, and the measuring accuracy is limited by the pixel size of CCD. Using a CCD with small pixel size can improve the measuring accuracy, but will increase the cost and difficulty of making. In this paper, through the comparative analysis of a variety of sub-pixel edge detection algorithms, polynomial fitting method is applied for data processing in measuring system for wire diameter, to improve the measuring accuracy and enhance the ability of anti-noise. In the design of system structure, light projection method with orthogonal structure is used for the detection optical part, which can effectively reduce the error caused by line jitter in the measuring process. For the electrical part, ARM Cortex-M4 microprocessor is used as the core of the circuit module, which can not only drive double channel linear CCD but also complete the sampling, processing and storage of the CCD video signal. In addition, ARM microprocessor can complete the high speed operation of the whole measuring system for wire diameter in the case of no additional chip. The experimental results show that sub-pixel edge detection algorithm based on polynomial fitting can make up for the lack of single pixel size and improve the precision of measuring system for wire diameter significantly, without increasing hardware complexity of the entire system.
The Microprocessor controls the activity of mammalian retrotransposons

PubMed Central

Heras, Sara R.; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L.; Cáceres, Javier F.

2013-01-01

More than half of the human genome is made of Transposable Elements. Their ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human LINE-1 (Long INterspersed Element 1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons acting as a defender of human genome integrity. PMID:23995758
The Microprocessor controls the activity of mammalian retrotransposons.

PubMed

Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

2013-10-01

More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.
Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.
Control law synthesis and optimization software for large order aeroservoelastic systems

NASA Technical Reports Server (NTRS)

Mukhopadhyay, V.; Pototzky, A.; Noll, Thomas

1989-01-01

A flexible aircraft or space structure with active control is typically modeled by a large-order state space system of equations in order to accurately represent the rigid and flexible body modes, unsteady aerodynamic forces, actuator dynamics and gust spectra. The control law of this multi-input/multi-output (MIMO) system is expected to satisfy multiple design requirements on the dynamic loads, responses, actuator deflection and rate limitations, as well as maintain certain stability margins, yet should be simple enough to be implemented on an onboard digital microprocessor. A software package for performing an analog or digital control law synthesis for such a system, using optimal control theory and constrained optimization techniques is described.
A new electronic scanner of pressure designed for installation in wind-tunnel models

NASA Technical Reports Server (NTRS)

Coe, C. T.; Parra, G. T.; Kauffman, R. C.

1981-01-01

A new electronic scanner of pressure (ESOP) has been developed by NASA Ames Research Center for installation in wind-tunnel models. An ESOP system includes up to 20 pressure modules, each with 48 pressure transducers, an A/D converter, a microprocessor, a data controller, a monitor unit, and a heater controller. The system is sized so that the pressure modules and A/D converter module can be installed within an average-size model tested in the Ames Aerodynamics Division wind tunnels. This paper describes the ESOP system, emphasizing the main element of the system - the pressure module. The measured performance of the overall system is also presented.
Programmable data communications controller requirements

NASA Technical Reports Server (NTRS)

1977-01-01

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.
A polymorphic reconfigurable emulator for parallel simulation

NASA Technical Reports Server (NTRS)

Parrish, E. A., Jr.; Mcvey, E. S.; Cook, G.

1980-01-01

Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described.
MIDAS - A microcomputer-based image display and analysis system with full Landsat frame processing capabilities

NASA Technical Reports Server (NTRS)

Hofman, L. B.; Erickson, W. K.; Donovan, W. E.

1984-01-01

Image Display and Analysis Systems (MIDAS) developed at NASA/Ames for the analysis of Landsat MSS images is described. The MIDAS computer power and memory, graphics, resource-sharing, expansion and upgrade, environment and maintenance, and software/user-interface requirements are outlined; the implementation hardware (including 32-bit microprocessor, 512K error-correcting RAM, 70 or 140-Mbyte formatted disk drive, 512 x 512 x 24 color frame buffer, and local-area-network transceiver) and applications software (ELAS, CIE, and P-EDITOR) are characterized; and implementation problems, performance data, and costs are examined. Planned improvements in MIDAS hardware and design goals and areas of exploration for MIDAS software are discussed.
Real-time and high accuracy frequency measurements for intermediate frequency narrowband signals

NASA Astrophysics Data System (ADS)

Tian, Jing; Meng, Xiaofeng; Nie, Jing; Lin, Liwei

2018-01-01

Real-time and accurate measurements of intermediate frequency signals based on microprocessors are difficult due to the computational complexity and limited time constraints. In this paper, a fast and precise methodology based on the sigma-delta modulator is designed and implemented by first generating the twiddle factors using the designed recursive scheme. This scheme requires zero times of multiplications and only half amounts of addition operations by using the discrete Fourier transform (DFT) and the combination of the Rife algorithm and Fourier coefficient interpolation as compared with conventional methods such as DFT and Fast Fourier Transform. Experimentally, when the sampling frequency is 10 MHz, the real-time frequency measurements with intermediate frequency and narrowband signals have a measurement mean squared error of ±2.4 Hz. Furthermore, a single measurement of the whole system only requires approximately 0.3 s to achieve fast iteration, high precision, and less calculation time.
A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2004-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.

Mechanical Engineering Design Project report: Enabler control systems

NASA Technical Reports Server (NTRS)

Cullen, Christian; Delvecchio, Dave; Scarborough, Alan; Havics, Andrew A.

1992-01-01

The Controls Group was assigned the responsibility for designing the Enabler's control system. The requirement for the design was that the control system must provide a simple user interface to control the boom articulation joints, chassis articulation joints, and the wheel drive. The system required controlling hydraulic motors on the Enabler by implementing 8-bit microprocessor boards. In addition, feedback to evaluate positions and velocities must be interfaced to provide the operator with confirmation as well as control.
Reconfigurable Very Long Instruction Word (VLIW) Processor

NASA Technical Reports Server (NTRS)

Velev, Miroslav N.

2015-01-01

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.
COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

ERIC Educational Resources Information Center

Marcovitz, Alan B., Ed.

This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…
Microprocessor-based single particle calibration of scintillation counter

NASA Technical Reports Server (NTRS)

Mazumdar, G. K. D.; Pathak, K. M.

1985-01-01

A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.
COED Transactions, Vol. XI, No. 12, December 1979. Some Alternate Applications of Microprocessor Trainers in Support of Undergraduate Laboratories.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.

Ways are described for the use of a microprocessor trainer in undergraduate laboratories. Listed are microcomputer applications that have been used as demonstrations and which provide signals for other experiments which are not related to microprocessors. Information and figures are provided for methods to do the following: direct generation of…
Microprocessor Based Real-Time Monitoring of Multiple ECG Signals

PubMed Central

Nasipuri, M.; Basu, D.K.; Dattagupta, R.; Kundu, M.; Banerjee, S.

1987-01-01

A microprocessor based system capable of realtime monitoring of multiple ECG signals has been described. The system consists of a number of microprocessors connected in a hierarchical fashion and capable of working concurrently on ECG data collected from different channels. The system can monitor different arrhythmic abnormalities for at least 36 patients even for a heart rate of 500 beats/min.
Hypoxia, Monitoring, and Mitigation System

DTIC Science & Technology

2015-08-01

Oxygen Saturation Measured via Pulse - Oximeter SRS Software Requirements Specification SW Software TI Texas Instruments uPROC Micro-Processor USAARL...Financial) Table of Figures Figure 1: Pulse OX custom module...Tasks 3, 4 and 5 have not been exercised. Sensor definition testing continued on the custom pulse -ox design. Additional refinement on the pulse
Security of Personal Computer Systems: A Management Guide.

ERIC Educational Resources Information Center

Steinauer, Dennis D.

This report describes management and technical security considerations associated with the use of personal computer systems as well as other microprocessor-based systems designed for use in a general office environment. Its primary objective is to identify and discuss several areas of potential vulnerability and associated protective measures. The…
[Multimag-M magnetotherapy system of the new generation].

PubMed

Borisov, A G; Grigor'ev, E M; Gurzhin, S G; Zhulev, V I; Kriakov, V G; Proshin, E M

2007-01-01

The Multimag-M microprocessor chronomagne-totherapy system of the new generation is described. The system provides on-line diagnosis of the pulse parameters and the breathing rate during a biotechnical feedback session. The requirements to the system software, as well as its specific features and design principles, are considered.
Assessment of transfemoral amputees using a passive microprocessor-controlled knee versus an active powered microprocessor-controlled knee for level walking.

PubMed

Creylman, Veerle; Knippels, Ingrid; Janssen, Paul; Biesbrouck, Evelyne; Lechler, Knut; Peeraer, Louis

2016-12-19

In transfemoral (TF) amputees, the forward propulsion of the prosthetic leg in swing has to be mainly carried out by hip muscles. With hip strength being the strongest predictor to ambulation ability, an active powered knee joint could have a positive influence, lowering hip loading and contributing to ambulation mobility. To assess this, gait of four TF amputees was measured for level walking, first while using a passive microprocessor-controlled prosthetic knee (P-MPK), subsequently while using an active powered microprocessor-controlled prosthetic knee (A-MPK). Furthermore, to assess long-term effects of the use of an A-MPK, a 4-weeks follow-up case study was performed. The kinetics and kinematics of the gait of four TF amputees were assessed while walking with subsequently the P-MPK and the A-MPK. For one amputee, a follow-up study was performed: he used the A-MPK for 4 weeks, his gait was measured weekly. The range of motion of the knee was higher on both the prosthetic and the sound leg in the A-MPK compared to the P-MPK. Maximum hip torque (HT) during early stance increased for the prosthetic leg and decreased for the sound leg with the A-MPK compared to the P-MPK. During late stance, the maximum HT decreased for the prosthetic leg. The difference between prosthetic and sound leg for HT disappeared when using the A-MPK. Also, an increase in stance phase duration was observed. The follow-up study showed an increase in confidence with the A-MPK over time. Results suggested that, partially due to an induced knee flexion during stance, HT can be diminished when walking with the A-MPK compared to the P-MPK. The single case follow-up study showed positive trends indicating that an adaptation time is beneficial for the A-MPK.
369 TFlop/s molecular dynamics simulations on the Roadrunner general-purpose heterogeneous supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swaminarayan, Sriram; Germann, Timothy C; Kadau, Kai

2008-01-01

The authors present timing and performance numbers for a short-range parallel molecular dynamics (MD) code, SPaSM, that has been rewritten for the heterogeneous Roadrunner supercomputer. Each Roadrunner compute node consists of two AMD Opteron dual-core microprocessors and four PowerXCell 8i enhanced Cell microprocessors, so that there are four MPI ranks per node, each with one Opteron and one Cell. The interatomic forces are computed on the Cells (each with one PPU and eight SPU cores), while the Opterons are used to direct inter-rank communication and perform I/O-heavy periodic analysis, visualization, and checkpointing tasks. The performance measured for our initial implementationmore » of a standard Lennard-Jones pair potential benchmark reached a peak of 369 Tflop/s double-precision floating-point performance on the full Roadrunner system (27.7% of peak), corresponding to 124 MFlop/Watt/s at a price of approximately 3.69 MFlops/dollar. They demonstrate an initial target application, the jetting and ejection of material from a shocked surface.« less
RISC Processors and High Performance Computing

NASA Technical Reports Server (NTRS)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.
An Adaptable Power System with Software Control Algorithm

NASA Technical Reports Server (NTRS)

Castell, Karen; Bay, Mike; Hernandez-Pellerano, Amri; Ha, Kong

1998-01-01

A low cost, flexible and modular spacecraft power system design was developed in response to a call for an architecture that could accommodate multiple missions in the small to medium load range. Three upcoming satellites will use this design, with one launch date in 1999 and two in the year 2000. The design consists of modular hardware that can be scaled up or down, without additional cost, to suit missions in the 200 to 600 Watt orbital average load range. The design will be applied to satellite orbits that are circular, polar elliptical and a libration point orbit. Mission unique adaptations are accomplished in software and firmware. In designing this advanced, adaptable power system, the major goals were reduction in weight volume and cost. This power system design represents reductions in weight of 78 percent, volume of 86 percent and cost of 65 percent from previous comparable systems. The efforts to miniaturize the electronics without sacrificing performance has created streamlined power electronics with control functions residing in the system microprocessor. The power system design can handle any battery size up to 50 Amp-hour and any battery technology. The three current implementations will use both nickel cadmium and nickel hydrogen batteries ranging in size from 21 to 50 Amp-hours. Multiple batteries can be used by adding another battery module. Any solar cell technology can be used and various array layouts can be incorporated with no change in Power System Electronics (PSE) hardware. Other features of the design are the standardized interfaces between cards and subsystems and immunity to radiation effects up to 30 krad Total Ionizing Dose (TID) and 35 Mev/cm(exp 2)-kg for Single Event Effects (SEE). The control algorithm for the power system resides in a radiation-hardened microprocessor. A table driven software design allows for flexibility in mission specific requirements. By storing critical power system constants in memory, modifying the system code for other programs is simple. These constants can be altered also by ground command, or in response to an anomolous event. All critical power system functions have backup hardware functions to prevent a software or computer glitch from propagating. A number of battery charge control schemes can be implemented by selecting the proper control terms in the code. The architecture allows the design engineer to tune the system response to various system components and anticipated load profiles without costly alterations. A design trade was made with the size, weight and power dissipation of the electronics versus the performance of the power bus to load variations. Linear, fine control is maintained with a streamlined electronics design. This paper describes the hardware design as well as the software control algorithm. The challenges of closing the system control loop digitally is discussed. Control loop margin and power system performance is presented. Lab measurements are shown and compared to the system response of a hardware model running actual flight software.
A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

PubMed

Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

2009-01-01

For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.
A VLSI VAX chip set

NASA Astrophysics Data System (ADS)

Johnson, W. N.; Herrick, W. V.; Grundmann, W. J.

1984-10-01

For the first time, VLSI technology is used to compress the full functinality and comparable performance of the VAX 11/780 super-minicomputer into a 1.2 M transistor microprocessor chip set. There was no subsetting of the 304 instruction set and the 17 data types, nor reduction in hardware support for the 4 Gbyte virtual memory management architecture. The chipset supports an integral 8 kbyte memory cache, a 13.3 Mbyte/s system bus, and sophisticated multiprocessing. High performance is achieved through microcode optimizations afforded by the large control store, tightly coupled address and data caches, the use of internal and external 32 bit datapaths, the extensive aplication of both microlevel and macrolevel pipelining, and the use of specialized hardware assists.
Cooperative Mission Concepts Using Biomorphic Explorers

NASA Technical Reports Server (NTRS)

Thakoor, S.; Miralles, C.; Martin, T.; Kahn, R.; Zurek, R.

2000-01-01

Inspired by the immense variety of naturally curious explorers (insects, animals, and birds), their wellintegrated biological sensor-processor suites, efficiently packaged in compact but highly dexterous forms, and their complex, intriguing, cooperative behavior, this paper focuses on "Biomorphic Explorers", their defination/classification, their designs, and presents planetary exploration scenarios based on the designs. Judicious blend of bio-inspired concepts and recent advances in micro-air vehicles, microsensors, microinstruments, MEMS, and microprocessors clearly suggests that the time of small, dedicated, low cost explorers that capture some of the key features of biological systems has arrived. Just as even small insects like ants, termites, honey bees etc working cooperatively in colonies can achieve big tasks, the biomorphic explorers hold the potential for obtaining science in-accessible by current large singular exploration platforms.
Development of land based radar polarimeter processor system

NASA Technical Reports Server (NTRS)

Kronke, C. W.; Blanchard, A. J.

1983-01-01

The processing subsystem of a land based radar polarimeter was designed and constructed. This subsystem is labeled the remote data acquisition and distribution system (RDADS). The radar polarimeter, an experimental remote sensor, incorporates the RDADS to control all operations of the sensor. The RDADS uses industrial standard components including an 8-bit microprocessor based single board computer, analog input/output boards, a dynamic random access memory board, and power supplis. A high-speed digital electronics board was specially designed and constructed to control range-gating for the radar. A complete system of software programs was developed to operate the RDADS. The software uses a powerful real time, multi-tasking, executive package as an operating system. The hardware and software used in the RDADS are detailed. Future system improvements are recommended.
Update on radiation-hardened microcomputers for robotics and teleoperated systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sias, F.R. Jr.; Tulenko, J.S.

1993-12-31

Since many programs sponsored by the Department of Defense are being canceled, it is important to select carefully radiation-hardened microprocessors for projects that will mature (or will require continued support) several years in the future. At the present time there are seven candidate 32-bit processors that should be considered for long-range planning for high-performance radiation-hardened computer systems. For Department of Energy applications it is also important to consider efforts at standardization that require the use of the VxWorks operating system and hardware based on the VMEbus. Of the seven processors, one has been delivered and is operating and other systemsmore » are scheduled to be delivered late in 1993 or early in 1994. At the present time the Honeywell-developed RH32, the Harris RH-3000 and the Harris RHC-3000 are leading contenders for meeting DOE requirements for a radiation-hardened advanced 32-bit microprocessor. These are all either compatible with or are derivatives of the MIPS R3000 Reduced Instruction Set Computer. It is anticipated that as few as two of the seven radiation-hardened processors will be supported by the space program in the long run.« less
Development of a simple, self-contained flight test data acquisition system

NASA Technical Reports Server (NTRS)

Clarke, R.; Shane, D.; Roskam, J.; Rummer, D. I.

1982-01-01

The flight test system described combines state-of-the-art microprocessor technology and high accuracy instrumentation with parameter identification technology which minimize data and flight time requirements. The system was designed to avoid permanent modifications of the test airplane and allow quick installation. It is capable of longitudinal and lateral-directional stability and control derivative estimation. Details of this system, calibration and flight test procedures, and the results of the Cessna 172 flight test program are presented. The system proved easy to install, simple to operate, and capable of accurate estimation of stability and control parameters in the Cessna 172 flight tests.
A microprocessor-based automation test system for the experiment of the multi-stage compressor

NASA Astrophysics Data System (ADS)

Zhang, Huisheng; Lin, Chongping

1991-08-01

An automation test system that is controlled by the microprocessor and used in the multistage compressor experiment is described. Based on the analysis of the compressor experiment performances, a complete hardware system structure is set up. It is composed of a IBM PC/XT computer, a large scale sampled data system, the moving machine with three directions, the scanners, the digital instrumentation and some output devices. A program structure of real-time software system is described. The testing results show that this test system can take the measure of many parameter magnitudes in the blade row places and on a boundary layer in different states. The automatic extent and the accuracy of experiment is increased and the experimental cost is reduced.

Practical application to composite materials of a portable digital ultrasound device controlled by a microprocessor

NASA Astrophysics Data System (ADS)

Castel, J. G.; Husarek, V.

1987-06-01

The usefulness of a portable microprocessor-controlled ultrasound device for the periodic assessment of aircraft parts made of composite materials is shown. The performance of the device is demonstrated with the examples of a metallic honeycomb with a carbon-fiber skin, a phenolic honeycomb with a carbon skin, and a phenolic honeycomb with a Kevlar skin. Also considered are assessments of homogeneous carbon-fiber parts, including the study of artificial defects consisting of 1-2 mm diameter holes, and the assessment of the behavior of a carbon-titanium interface with separated zones. Advantages of the device include ease of adjustment, automated evaluation of the depth of defects, and the nearly-absolute reproducibility of adjustments.
Advanced Transport Operating System (ATOPS) color displays software description microprocessor system

NASA Technical Reports Server (NTRS)

Slominski, Christopher J.; Plyler, Valerie E.; Dickson, Richard W.

1992-01-01

This document describes the software created for the Sperry Microprocessor Color Display System used for the Advanced Transport Operating Systems (ATOPS) project on the Transport Systems Research Vehicle (TSRV). The software delivery known as the 'baseline display system', is the one described in this document. Throughout this publication, module descriptions are presented in a standardized format which contains module purpose, calling sequence, detailed description, and global references. The global reference section includes procedures and common variables referenced by a particular module. The system described supports the Research Flight Deck (RFD) of the TSRV. The RFD contains eight cathode ray tubes (CRTs) which depict a Primary Flight Display, Navigation Display, System Warning Display, Takeoff Performance Monitoring System Display, and Engine Display.
The development of a microprocessor-controlled linearly-actuated valve assembly

NASA Technical Reports Server (NTRS)

Wall, R. H.

1984-01-01

The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.
LLL 8080 BASIC-II interpreter user's manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

McGoldrick, P.R.; Dickinson, J.; Allison, T.G.

1978-04-03

Scientists are finding increased applications for microprocessors as process controllers in their experiments. However, while microprocessors are small and inexpensive, they are difficult to program in machine or assembly language. A high-level language is needed to enable scientists to develop their own microcomputer programs for their experiments on location. Recognizing this need, LLL contracted to have such a language developed. This report describes the resulting LLL BASIC interpreter, which opeates with LLL's 8080-based MCS-8 microcomputer system. All numerical operations are done using Advanced Micro Device's Am9511 arithmetic processor chip or optionally by using a software simulation of that chip. 1more » figure.« less
A Low Noise, Microprocessor-Controlled, Internally Digitizing Rotating-Vane Electric Field Mill for Airborne Platforms

NASA Technical Reports Server (NTRS)

Bateman, M. G.; Stewart, M. F.; Blakeslee, R. J.; Podgorny, s. J.; Christian, H. J.; Mach, D. M.; Bailey, J. C.; Daskar, D.

2006-01-01

This paper reports on a new generation of aircraft-based rotating-vane style electric field mills designed and built at NASA's Marshall Spaceflight Center. The mills have individual microprocessors that digitize the electric field signal at the mill and respond to commands from the data system computer. The mills are very sensitive (1 V/m per bit), have a wide dynamic range (115 dB), and are very low noise (+/-1 LSB). Mounted on an aircraft, these mills can measure fields from +/-1 V/m to +/-500 kV/m. Once-per-second commanding from the data collection computer to each mill allows for precise timing and synchronization. The mills can also be commanded to execute a self-calibration in flight, which is done periodically to monitor the status and health of each mill.
Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

PubMed

Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

2014-03-28

Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression. Copyright © 2014 Elsevier Inc. All rights reserved.
Functional Anatomy of the Human Microprocessor.

PubMed

Nguyen, Tuan Anh; Jo, Myung Hyun; Choi, Yeon-Gil; Park, Joha; Kwon, S Chul; Hohng, Sungchul; Kim, V Narry; Woo, Jae-Sung

2015-06-04

MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8 molecules. Together with a 23-amino acid peptide from DGCR8, DROSHA constitutes a minimal functional core. DROSHA serves as a "ruler" by measuring 11 bp from the basal ssRNA-dsRNA junction. DGCR8 interacts with the stem and apical elements through its dsRNA-binding domains and RNA-binding heme domain, respectively, allowing efficient and accurate processing. DROSHA and DGCR8, respectively, recognize the basal UG and apical UGU motifs, which ensure proper orientation of the complex. These findings clarify controversies over the action mechanism of DROSHA and allow us to build a general model for pri-miRNA processing. Copyright © 2015 Elsevier Inc. All rights reserved.
Performance Evaluation of Communication Software Systems for Distributed Computing

NASA Technical Reports Server (NTRS)

Fatoohi, Rod

1996-01-01

In recent years there has been an increasing interest in object-oriented distributed computing since it is better quipped to deal with complex systems while providing extensibility, maintainability, and reusability. At the same time, several new high-speed network technologies have emerged for local and wide area networks. However, the performance of networking software is not improving as fast as the networking hardware and the workstation microprocessors. This paper gives an overview and evaluates the performance of the Common Object Request Broker Architecture (CORBA) standard in a distributed computing environment at NASA Ames Research Center. The environment consists of two testbeds of SGI workstations connected by four networks: Ethernet, FDDI, HiPPI, and ATM. The performance results for three communication software systems are presented, analyzed and compared. These systems are: BSD socket programming interface, IONA's Orbix, an implementation of the CORBA specification, and the PVM message passing library. The results show that high-level communication interfaces, such as CORBA and PVM, can achieve reasonable performance under certain conditions.
Design of signal reception and processing system of embedded ultrasonic endoscope

NASA Astrophysics Data System (ADS)

Li, Ming; Yu, Feng; Zhang, Ruiqiang; Li, Yan; Chen, Xiaodong; Yu, Daoyin

2009-11-01

Embedded Ultrasonic Endoscope, based on embedded microprocessor and embedded real-time operating system, sends a micro ultrasonic probe into coelom through the biopsy channel of the Electronic Endoscope to get the fault histology features of digestive organs by rotary scanning, and acquires the pictures of the alimentary canal mucosal surface. At the same time, ultrasonic signals are processed by signal reception and processing system, forming images of the full histology of the digestive organs. Signal Reception and Processing System is an important component of Embedded Ultrasonic Endoscope. However, the traditional design, using multi-level amplifiers and special digital processing circuits to implement signal reception and processing, is no longer satisfying the standards of high-performance, miniaturization and low power requirements that embedded system requires, and as a result of the high noise that multi-level amplifier brought, the extraction of small signal becomes hard. Therefore, this paper presents a method of signal reception and processing based on double variable gain amplifier and FPGA, increasing the flexibility and dynamic range of the Signal Reception and Processing System, improving system noise level, and reducing power consumption. Finally, we set up the embedded experiment system, using a transducer with the center frequency of 8MHz to scan membrane samples, and display the image of ultrasonic echo reflected by each layer of membrane, with a frame rate of 5Hz, verifying the correctness of the system.
The MOS silicon gate technology and the first microprocessors

NASA Astrophysics Data System (ADS)

Faggin, F.

2015-12-01

Today we are so used to the enormous capabilities of microelectronics that it is hard to imagine what it might have been like in the early Sixties and Seventies when much of the technology we use today was being developed. This paper will first present a brief history of microelectronics and computers, taking us to the threshold of the inventions of the MOS silicon gate technology and the microprocessor. These two creations provided the basic technology that would allow only a few years later to merge microelectronics and computers into the first commercial monolithic computer. By the late Seventies, the first monolithic computer weighting less than one gram, occupying a volume of less than one cubic centimeter, dissipating less than one Watt, and selling for less than ten dollars, could perform more information processing than the UNIVAC I, the first commercial electronic computer introduced in 1951, made with 5200 vacuum tubes, dissipating 125kW, weighting 13 metric tons, occupying a room larger than 35m2, and selling for more than one million dollars per unit. The first-person story of the SGT and the early microprocessors will be told by the Italian-born physicist who led both projects.
A Microprocessor-Based Real-Time Simulator of a Turbofan Engine

DTIC Science & Technology

1988-01-01

NASA AVSCOM Technical Memorandum 100889 Technical Report 88-C-011 Lfl A Microprocessor-Based Real-Time Simulator of a Turbofan Engine CD I Jonathan S...Accession For NTIS GRA&I A MICROPROCESSOR-BASED REAL-TIME SIMULATOR DTIC TABUnannounced OF A TURBOFAN ENGINE Justifiaation, Jonathan S. Litt Propulsion...the F100 engine without augmentation (without afterburning). HYTESS is a simplified simulation written in FORTRAN of a generalized turbofan engine . To
Electrical characterization of standard and radiation-hardened RCA CDP1856D 4-BIT, CMOS, bus buffer/separator

NASA Technical Reports Server (NTRS)

Stokes, R. L.

1979-01-01

Tests performed to determine accuracy and efficiency of bus separators used in microprocessors are presented. Functional, AC parametric, and DC parametric tests were performed in a Tektronix S-3260 automated test system. All the devices passed the functional tests and yielded nominal values in the parametric test.
Regulation of Plant Microprocessor Function in Shaping microRNA Landscape.

PubMed

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem-loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.
Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

PubMed Central

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed. PMID:29922322
Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis.

PubMed

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2017-02-01

There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation ( p = .001), paretic limb health ( p = .04), sounds ( p = .02), and well-being ( p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety.
Clearing a Path: The 16-Bit Operating System Jungle Offers Confusion, Not Standardization.

ERIC Educational Resources Information Center

Pournelle, Jerry

1984-01-01

Discusses the design and limited uses of the Pascal, MS-DOS, CP/M, and PC-DOS operating systems as standard operating systems for 16-bit microprocessors, especially with the more sophisticated microcomputers currently being developed. Advantages and disadvantages of Unix--a multitasking, multiuser operating system--as a standard operating system…
A Monitoring System for Vegetable Greenhouses based on a Wireless Sensor Network

PubMed Central

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetatables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring. PMID:22163391
Trends in modern system theory

NASA Technical Reports Server (NTRS)

Athans, M.

1976-01-01

The topics considered are related to linear control system design, adaptive control, failure detection, control under failure, system reliability, and large-scale systems and decentralized control. It is pointed out that the design of a linear feedback control system which regulates a process about a desirable set point or steady-state condition in the presence of disturbances is a very important problem. The linearized dynamics of the process are used for design purposes. The typical linear-quadratic design involving the solution of the optimal control problem of a linear time-invariant system with respect to a quadratic performance criterion is considered along with gain reduction theorems and the multivariable phase margin theorem. The stumbling block in many adaptive design methodologies is associated with the amount of real time computation which is necessary. Attention is also given to the desperate need to develop good theories for large-scale systems, the beginning of a microprocessor revolution, the translation of the Wiener-Hopf theory into the time domain, and advances made in dynamic team theory, dynamic stochastic games, and finite memory stochastic control.
Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

NASA Astrophysics Data System (ADS)

González, Diego; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

2013-12-01

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.
A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

NASA Astrophysics Data System (ADS)

Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.

2003-10-01

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Aerospace Applications of Microprocessors

NASA Technical Reports Server (NTRS)

1980-01-01

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed.
Event parallelism: Distributed memory parallel computing for high energy physics experiments

NASA Astrophysics Data System (ADS)

Nash, Thomas

1989-12-01

This paper describes the present and expected future development of distributed memory parallel computers for high energy physics experiments. It covers the use of event parallel microprocessor farms, particularly at Fermilab, including both ACP multiprocessors and farms of MicroVAXES. These systems have proven very cost effective in the past. A case is made for moving to the more open environment of UNIX and RISC processors. The 2nd Generation ACP Multiprocessor System, which is based on powerful RISC system, is described. Given the promise of still more extraordinary increases in processor performance, a new emphasis on point to point, rather than bussed, communication will be required. Developments in this direction are described.
The new 34-meter antenna

NASA Technical Reports Server (NTRS)

Pompa, M. F.

1986-01-01

The new 34-m high efficiency Azimuth - Elevation antenna configuration, including its features, dynamic characteristics and performance at 8.4-GHz frequencies is described. The current-technology features of this antenna produce a highly reliable configuration by incorporation of a main wheel and track azimuth support, central pintle pivot bearing, close tolerance surface panels and all-welded construction. Also described are basic drive controls that, as slaved to three automatic microprocessors, provide accurate and safe control of the antenna's steering tasks. At this time antenna installations are completed at Goldstone and Canberra and have operationally supported the Voyager - Uranus encounter. A third installation is being constructed currently in Madrid and is scheduled for completion in late 1986.
Modeling and control study of the NASA 0.3-meter transonic cryogenic tunnel for use with sulfur hexafluoride medium

NASA Technical Reports Server (NTRS)

Balakrishna, S.; Kilgore, W. Allen

1992-01-01

The NASA Langley 0.3-m Transonic Cryogenic Tunnel is to be modified to operate with sulfur hexafluoride gas while retaining its present capability to operate with nitrogen. The modified tunnel will provide high Reynolds number flow on aerodynamic models with two different test gases. The document details a study of the SF6 tunnel performance boundaries, thermodynamic modeling of the tunnel process, nonlinear dynamical simulation of math model to yield tunnel responses, the closed loop control requirements, control laws, and mechanization of the control laws on the microprocessor based controller.
Advanced detection, isolation, and accommodation of sensor failures in turbofan engines: Real-time microcomputer implementation

NASA Technical Reports Server (NTRS)

Delaat, John C.; Merrill, Walter C.

1990-01-01

The objective of the Advanced Detection, Isolation, and Accommodation Program is to improve the overall demonstrated reliability of digital electronic control systems for turbine engines. For this purpose, an algorithm was developed which detects, isolates, and accommodates sensor failures by using analytical redundancy. The performance of this algorithm was evaluated on a real time engine simulation and was demonstrated on a full scale F100 turbofan engine. The real time implementation of the algorithm is described. The implementation used state-of-the-art microprocessor hardware and software, including parallel processing and high order language programming.
Network Coding on Heterogeneous Multi-Core Processors for Wireless Sensor Networks

PubMed Central

Kim, Deokho; Park, Karam; Ro, Won W.

2011-01-01

While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine. PMID:22164053
[Extension of cardiac monitoring function by used of ordinary ECG machine].

PubMed

Chen, Zhencheng; Jiang, Yong; Ni, Lili; Wang, Hongyan

2002-06-01

This paper deals with a portable monitor system on liquid crystal display (LCD) based on this available ordinary ECG machine, which is low power and suitable for China's specific condition. Apart from developing the overall scheme of the system, this paper also has completed the design of the hardware and the software. The 80c196 single chip microcomputer is taken as the central microprocessor and real time electrocardiac single is data treated and analyzed in the system. With the performance of ordinary monitor, this machine also possesses the following functions: five types of arrhythmia analysis, alarm, freeze, and record of automatic pappering, convenient in carrying, with alternate-current (AC) or direct-current (DC) powered. The hardware circuit is simplified and the software structure is optimized in this paper. Multiple low power designs and LCD unit design are adopted and completed in it. Popular in usage, low in cost price, the portable monitor system will have a valuable influence on China's monitor system field.
Full temperature single event upset characterization of two microprocessor technologies

NASA Technical Reports Server (NTRS)

Nichols, Donald K.; Coss, James R.; Smith, L. S.; Rax, Bernard; Huebner, Mark

1988-01-01

Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.
Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

DTIC Science & Technology

2016-02-05

SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they... microprocessors in a way that they can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of...Progress The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they can be added and
Mold heating and cooling microprocessor conversion. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoffman, D.P.

Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessormore » board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.« less
A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2003-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and capacity computers because of their generality, scalability, and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently-released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.
SEMG-controlled telephone interface for people with disabilities.

PubMed

Chen, Yu-Luen; Lai, Jin-Shin; Luh, Jer-Junn; Kuo, Te-Son

2002-01-01

This paper proposes the development of a surface electromyographic (SEMG)-controlled telephone interface for the disabled. The system is composed of three major components: (1) a SEMG receiving/signal-processing module; (2) a row-column scanning interface for the telephone dialling pad; and (3) a main controller, the Intel-8951 microprocessor. The design concept was based on the idea of using a SEMG generated by the disabled and converting it into a trigger pulse. This could allow convenient control of the dialing motion in the row-column scanning keys of a telephone dialling pad. People with disabilities are competent for certain kinds of work such as being a telephone operator. The increase of opportunities to perform a job for the disabled would help them live independently.
A versatile microprocessor-controlled hybrid receiver. [with firmware control for operation over large frequency uncertainty

NASA Technical Reports Server (NTRS)

Grant, T. L.

1978-01-01

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.
Technology and the future of medical equipment maintenance.

PubMed

Wear, J O

1999-05-01

Maintenance of medical equipment has been changing rapidly in the past few years. It is changing more rapidly in developed countries, but changes are also occurring in developing countries. Some of the changes may permit improved maintenance on the higher technology equipment in developing countries, since they do not require onsite expertise. Technology has had an increasing impact on the development of medical equipment with the increased use of microprocessors and computers. With miniaturization from space technology and electronic chip design, powerful microprocessors and computers have been built into medical equipment. The improvement in manufacturing technology has increased the quality of parts and therefore the medical equipment. This has resulted in increased mean time between failures and reduced maintenance needs. This has made equipment more reliable in remote areas and developing countries. The built-in computers and advances in software design have brought about self-diagnostics in medical equipment. The technicians now have a strong tool to be used in maintenance. One problem in this area is getting access to the self-diagnostics. Some manufacturers will not readily provide this access to the owner of the equipment. Advances in telecommunications in conjunction with self-diagnostics make available remote diagnosis and repair. Since components can no longer be repaired, a remote repair technician can instruct an operator or an on-site repairman on board replacement. In case of software problems, the remote repair technician may perform the repairs over the telephone. It is possible for the equipment to be monitored remotely by modern without interfering with the operation of the equipment. These changes in technology require the training of biomedical engineering technicians (BMETs) to change. They must have training in computers and telecommunications. Some of this training can be done with telecommunications and computers.
49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2013 CFR

2013-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...
49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2012 CFR

2012-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...
49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2011 CFR

2011-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...
49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...
49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2014 CFR

2014-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...
The comparison of transfemoral amputees using mechanical and microprocessor- controlled prosthetic knee under different walking speeds: A randomized cross-over trial.

PubMed

Cao, Wujing; Yu, Hongliu; Zhao, Weiliang; Meng, Qiaoling; Chen, Wenming

2018-04-20

The microprocessor-controlled prosthetic knees have been introduced to transfemoral amputees due to advances in biomedical engineering. A body of scientific literature has shown that the microprocessor-controlled prosthetic knees improve the gait and functional abilities of persons with transfemoral amputation. The aim of this study was to propose a new microprocessor-controlled prosthetic knee (MPK) and compare it with non-microprocessor-controlled prosthetic knees (NMPKs) under different walking speeds. The microprocessor-controlled prosthetic knee (i-KNEE) with hydraulic damper was developed. The comfortable self-selected walking speeds of 12 subjects with i-KNEE and NMPK were obtained. The maximum swing flexion knee angle and gait symmetry were compared in i-KNEE and NMPK condition. The comfortable self-selected walking speeds of some subjects were higher with i-KNEE while some were not. There was no significant difference in comfortable self-selected walking speed between the i-KNEE and the NMPK condition (P= 0.138). The peak prosthetic knee flexion during swing in the i-KNEE condition was between sixty and seventy degree under any walking speed. In the NMPK condition, the maximum swing flexion knee angle changed significantly. And it increased with walking speed. There is no significant difference in knee kinematic symmetry when the subjects wear the i-KNEE or NMPK. The results of this study indicated that the new microprocessor-controlled prosthetic knee was suitable for transfemoral amputees. The maximum swing flexion knee angle under different walking speeds showed different properties in the NMPK and i-KNEE condition. The i-KNEE was more adaptive to speed changes. There was little difference of comfortable self-selected walking speed between i-KNEE and NMPK condition.

Distributed GPU Computing in GIScience

NASA Astrophysics Data System (ADS)

Jiang, Y.; Yang, C.; Huang, Q.; Li, J.; Sun, M.

2013-12-01

Geoscientists strived to discover potential principles and patterns hidden inside ever-growing Big Data for scientific discoveries. To better achieve this objective, more capable computing resources are required to process, analyze and visualize Big Data (Ferreira et al., 2003; Li et al., 2013). Current CPU-based computing techniques cannot promptly meet the computing challenges caused by increasing amount of datasets from different domains, such as social media, earth observation, environmental sensing (Li et al., 2013). Meanwhile CPU-based computing resources structured as cluster or supercomputer is costly. In the past several years with GPU-based technology matured in both the capability and performance, GPU-based computing has emerged as a new computing paradigm. Compare to traditional computing microprocessor, the modern GPU, as a compelling alternative microprocessor, has outstanding high parallel processing capability with cost-effectiveness and efficiency(Owens et al., 2008), although it is initially designed for graphical rendering in visualization pipe. This presentation reports a distributed GPU computing framework for integrating GPU-based computing within distributed environment. Within this framework, 1) for each single computer, computing resources of both GPU-based and CPU-based can be fully utilized to improve the performance of visualizing and processing Big Data; 2) within a network environment, a variety of computers can be used to build up a virtual super computer to support CPU-based and GPU-based computing in distributed computing environment; 3) GPUs, as a specific graphic targeted device, are used to greatly improve the rendering efficiency in distributed geo-visualization, especially for 3D/4D visualization. Key words: Geovisualization, GIScience, Spatiotemporal Studies Reference : 1. Ferreira de Oliveira, M. C., & Levkowitz, H. (2003). From visual data exploration to visual data mining: A survey. Visualization and Computer Graphics, IEEE Transactions on, 9(3), 378-394. 2. Li, J., Jiang, Y., Yang, C., Huang, Q., & Rice, M. (2013). Visualizing 3D/4D Environmental Data Using Many-core Graphics Processing Units (GPUs) and Multi-core Central Processing Units (CPUs). Computers & Geosciences, 59(9), 78-89. 3. Owens, J. D., Houston, M., Luebke, D., Green, S., Stone, J. E., & Phillips, J. C. (2008). GPU computing. Proceedings of the IEEE, 96(5), 879-899.
Microprocessor Controlled Isometric Contractions of Cat Gastrocnemius Muscle.

DTIC Science & Technology

1981-12-01

A-A15 504 AIR FORCE INST OF TECH WRIGHT-PATTERSON AFS OH 5CHOO--ETC F/6 6/2 MICROPROCESSOR CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROC-ETC(U) D...CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROCNEMIUS MUSCLE THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of...1981 Appzoved for public release; distribution unlimited. AFIT/GE/EE/81D-4O \\ MICROPROCESSOR CONTROLLED ISOMETRIC COMUtCTIONS OF CAT GASTfOCNEMIUS i
Microprocessor based implementation of attitude and shape control of large space structures

NASA Technical Reports Server (NTRS)

Reddy, A. S. S. R.

1984-01-01

The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.
Global identification of target recognition and cleavage by the Microprocessor in human ES cells

PubMed Central

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-01-01

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein–RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3′ overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. PMID:25326327
Identifying, Quantifying, Extracting and Enhancing Implicit Parallelism

ERIC Educational Resources Information Center

Agarwal, Mayank

2009-01-01

The shift of the microprocessor industry towards multicore architectures has placed a huge burden on the programmers by requiring explicit parallelization for performance. Implicit Parallelization is an alternative that could ease the burden on programmers by parallelizing applications "under the covers" while maintaining sequential semantics…
Development of the functional simulator for the Galileo attitude and articulation control system

NASA Technical Reports Server (NTRS)

Namiri, M. K.

1983-01-01

A simulation program for verifying and checking the performance of the Galileo Spacecraft's Attitude and Articulation Control Subsystem's (AACS) flight software is discussed. The program, which is called Functional Simulator (FUNSIM), provides a simple method of interfacing user-supplied mathematical models coded in FORTRAN which describes spacecraft dynamics, sensors, and actuators; this is done with the AACS flight software, coded in HAL/S (High-level Advanced Language/Shuttle). It is thus able to simulate the AACS flight software accurately to the HAL/S statement level in the environment of a mainframe computer system. FUNSIM also has a command and data subsystem (CDS) simulator. It is noted that the input/output data and timing are simulated with the same precision as the flight microprocessor. FUNSIM uses a variable stepsize numerical integration algorithm complete with individual error bound control on the state variable to solve the equations of motion. The program has been designed to provide both line printer and matrix dot plotting of the variables requested in the run section and to provide error diagnostics.
Multitasking operating systems for microprocessors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cramer, T.

1981-01-01

Microprocessors, because of their low cost, low power consumption, and small size, have caused an explosion in the number of innovative computer applications. Although there is a great deal of variation in microprocessor applications software, there is relatively little variation in the operating-system-level software from one application to the next. Nonetheless, operating system software, especially when multitasking is involved, can be very time consuming and expensive to develop. The major microprocessor manufacturers have acknowledged the need for operating systems in microprocessor applications and are now supplying real-time multitasking operating system software that is adaptable to a wide variety of usermore » systems. Use of this existing operating system software will decrease the number of redundant operating system development efforts, thus freeing programmers to work on more creative and productive problems. This paper discusses the basic terminology and concepts involved with multitasking operating systems. It is intended to provide a general understanding of the subject, so that the reader will be prepared to evaluate specific operating system software according to his or her needs. 2 references.« less
Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

NASA Astrophysics Data System (ADS)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.
UWE-3, in-orbit performance and lessons learned of a modular and flexible satellite bus for future pico-satellite formations

NASA Astrophysics Data System (ADS)

Busch, S.; Bangert, P.; Dombrovski, S.; Schilling, K.

2015-12-01

Formations of small satellites offer promising perspectives due to improved temporal and spatial coverage and resolution at reasonable costs. The UWE-program addresses in-orbit demonstrations of key technologies to enable formations of cooperating distributed spacecraft at pico-satellite level. In this context, the CubeSat UWE-3 addresses experiments for evaluation of real-time attitude determination and control. UWE-3 introduces also a modular and flexible pico-satellite bus as a robust and extensible base for future missions. Technical objective was a very low power consumption of the COTS-based system, nevertheless providing a robust performance of this miniature satellite by advanced microprocessor redundancy and fault detection, identification and recovery software. This contribution addresses the UWE-3 design and mission results with emphasis on the operational experiences of the attitude determination and control system.
Towards the formal specification of the requirements and design of a processor interface unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'
AnRAD: A Neuromorphic Anomaly Detection Framework for Massive Concurrent Data Streams.

PubMed

Chen, Qiuwen; Luley, Ryan; Wu, Qing; Bishop, Morgan; Linderman, Richard W; Qiu, Qinru

2018-05-01

The evolution of high performance computing technologies has enabled the large-scale implementation of neuromorphic models and pushed the research in computational intelligence into a new era. Among the machine learning applications, unsupervised detection of anomalous streams is especially challenging due to the requirements of detection accuracy and real-time performance. Designing a computing framework that harnesses the growing computing power of the multicore systems while maintaining high sensitivity and specificity to the anomalies is an urgent research topic. In this paper, we propose anomaly recognition and detection (AnRAD), a bioinspired detection framework that performs probabilistic inferences. We analyze the feature dependency and develop a self-structuring method that learns an efficient confabulation network using unlabeled data. This network is capable of fast incremental learning, which continuously refines the knowledge base using streaming data. Compared with several existing anomaly detection approaches, our method provides competitive detection quality. Furthermore, we exploit the massive parallel structure of the AnRAD framework. Our implementations of the detection algorithm on the graphic processing unit and the Xeon Phi coprocessor both obtain substantial speedups over the sequential implementation on general-purpose microprocessor. The framework provides real-time service to concurrent data streams within diversified knowledge contexts, and can be applied to large problems with multiple local patterns. Experimental results demonstrate high computing performance and memory efficiency. For vehicle behavior detection, the framework is able to monitor up to 16000 vehicles (data streams) and their interactions in real time with a single commodity coprocessor, and uses less than 0.2 ms for one testing subject. Finally, the detection network is ported to our spiking neural network simulator to show the potential of adapting to the emerging neuromorphic architectures.
Low cost Czochralski crystal growing technology. Near implementation of the flat plate photovoltaic cost reduction of the low cost solar array project

NASA Technical Reports Server (NTRS)

Roberts, E. G.

1980-01-01

Equipment developed for the manufacture of over 100 kg of silicon ingot from one crucible by rechanging from another crucible is described. Attempts were made to eliminate the cost of raising the furnace temperature to 250 C above the melting point of silicon by using an RF coil to melt polycrystalline silicon rod as a means of rechanging the crucible. Microprocessor control of the straight growth process was developed and domonstrated for both 4 inch and 6 inch diameter. Both meltdown and melt stabilization processes were achieved using operator prompting through the microprocessor. The use of the RF work coil in poly rod melting as a heat sink in the accelerated growth process was unsuccessful. The total design concept for fabrication and interfacing of the total cold crucible system was completed.
A new device for monitoring early motor development: prenatal nicotine-induced changes.

PubMed

Schlumpf, M; Gähwiler, M; Ribary, U; Lichtensteiger, W

1988-05-01

A new type of activity meter has been designed especially for young rats. It consists of a warmed platform for the animal, a TV camera with monitor and a microprocessor. The TV camera detects the animal as a black figure on a light background. This picture is digitalized and stored in a Z80 microprocessor. Every 200 msec a new image is compared to the foregoing one. The total number of black points that are changing from black to white and vice versa provides a measure for motor activity of the animal. Prenatally nicotine-treated rat pups were tested on the activity meter. The developmental pattern of motor activity was different for male and female pups. Motor activity of nicotine-treated male pups differed significantly from controls at postnatal days 7 and 15 while this drug effect was not seen in females.
Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.
Transient fault behavior in a microprocessor: A case study

NASA Technical Reports Server (NTRS)

Duba, Patrick

1989-01-01

An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made.
Automatic multi-banking of memory for microprocessors

NASA Technical Reports Server (NTRS)

Wiker, G. A. (Inventor)

1984-01-01

A microprocessor system is provided with added memories to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch.
Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

NASA Technical Reports Server (NTRS)

King, K. D.

2003-01-01

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.
49 CFR 229.27 - Annual tests.

Code of Federal Regulations, 2011 CFR

2011-10-01

... DMU locomotive or an MU locomotive, equipped with a microprocessor-based event recorder that includes...) A microprocessor-based event recorder with a self-monitoring feature equipped to verify that all...
Debris measure subsystem of the nanosatellite IRECIN

NASA Astrophysics Data System (ADS)

Ferrante, M.; di Ciolo, L.; Ortenzi, A.; Petrozzi, M.; del Re, V.

2003-09-01

The on board resources, needed to perform the mission tasks, are very limited in nano-satellites. This paper proposes an Electronic real-time system that acquires space debris measures. It uses a piezo-electric sensor. The described device is a subsystem on board of the IRECIN nanosatellite composed mainly by a r.i.s.c. microprocessor, an electronic part that interfaces to the debris sensor in order to provide a low noise electrical and suitable range to ADC 12 bit converter, and finally a memory in order to store the data. The microprocessor handles the Debris Measure System measuring the impacts number, their intensity and storing their waves form. This subsystem is able to communicate with the other IRECIN subsystems through I2C Bus and principally with the "Main Microprocessor" subsystem allowing the data download directly to the Ground Station. Moreover this subsystem lets free the "Main Microprocessor Board" from the management and charge of debris data. All electronic components are SMD technology in order to reduce weight and size. The realized Electronic board are completely developed, realized and tested at the Vitrociset S.P.A. under control of Research and Development Group. The proposed system is implemented on the IRECIN, a modular nanosatellite weighting less than 1.5 kg, constituted by sixteen external sides with surface-mounted solar cells and three internal Al plates, kept together by four steel bars. Lithium-ions batteries are added for eclipse operations. Attitude is determined by two three-axis magnetometers and the solar panels data. Control is provided by an active magnetic control system. The spacecraft will be spin-stabilized with the spin-axis normal to the orbit. debris and micrometeoroids mass and velocity.
Design and Experiment of Electrooculogram (EOG) System and Its Application to Control Mobile Robot

NASA Astrophysics Data System (ADS)

Sanjaya, W. S. M.; Anggraeni, D.; Multajam, R.; Subkhi, M. N.; Muttaqien, I.

2017-03-01

In this paper, we design and investigate a biological signal detection of eye movements (Electrooculogram). To detect a signal of Electrooculogram (EOG) used 4 instrument amplifier process; differential instrumentation amplifier, High Pass Filter (HPF) with 3 stage filters, Low Pass Filter (LPF) with 3 stage filters and Level Shifter circuit. The total of amplifying is 1000 times of gain, with frequency range 0.5-30 Hz. IC OP-Amp OP07 was used for all amplifying process. EOG signal will be read as analog input for Arduino microprocessor, and will interfaced with serial communication to PC Monitor using Processing® software. The result of this research show a differences value of eye movements. Differences signal of EOG have been applied to navigation control of the mobile robot. In this research, all communication process using Bluetooth HC-05.

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