Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, A.N.; Soden, J.M.

1998-12-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

Ion-beam apparatus and method for analyzing and controlling integrated circuits

DOEpatents

Campbell, Ann N.; Soden, Jerry M.

1998-01-01

An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

Picosecond imaging of signal propagation in integrated circuits

NASA Astrophysics Data System (ADS)

Frohmann, Sven; Dietz, Enrico; Dittrich, Helmar; Hübers, Heinz-Wilhelm

2017-04-01

Optical analysis of integrated circuits (IC) is a powerful tool for analyzing security functions that are implemented in an IC. We present a photon emission microscope for picosecond imaging of hot carrier luminescence in ICs in the near-infrared spectral range from 900 to 1700 nm. It allows for a semi-invasive signal tracking in fully operational ICs on the gate or transistor level with a timing precision of approximately 6 ps. The capabilities of the microscope are demonstrated by imaging the operation of two ICs made by 180 and 60 nm process technology.

Using NCAP to predict RFI effects in linear bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.

1980-11-01

Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Integrated circuit authentication using photon-limited x-ray microscopy.

PubMed

Markman, Adam; Javidi, Bahram

2016-07-15

A counterfeit integrated circuit (IC) may contain subtle changes to its circuit configuration. These changes may be observed when imaged using an x-ray; however, the energy from the x-ray can potentially damage the IC. We have investigated a technique to authenticate ICs under photon-limited x-ray imaging. We modeled an x-ray image with lower energy by generating a photon-limited image from a real x-ray image using a weighted photon-counting method. We performed feature extraction on the image using the speeded-up robust features (SURF) algorithm. We then authenticated the IC by comparing the SURF features to a database of SURF features from authentic and counterfeit ICs. Our experimental results with real and counterfeit ICs using an x-ray microscope demonstrate that we can correctly authenticate an IC image captured using orders of magnitude lower energy x-rays. To the best of our knowledge, this Letter is the first one on using a photon-counting x-ray imaging model and relevant algorithms to authenticate ICs to prevent potential damage.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Automated Visual Inspection Of Integrated Circuits

NASA Astrophysics Data System (ADS)

Noppen, G.; Oosterlinck, Andre J.

1989-07-01

One of the major application fields of image processing techniques is the 'visual inspection'. For a number of rea-sons, the automated visual inspection of Integrated Circuits (IC's) has drawn a lot of attention. : Their very strict design makes them very suitable for an automated inspection. : There is already a lot of experience in the comparable Printed Circuit Board (PCB) and mask inspection. : The mechanical handling of wafers and dice is already an established technology. : Military and medical IC's should be a 100 % failproof. : IC inspection gives a high and allinost immediate payback. In this paper we wil try to give an outline of the problems involved in IC inspection, and the algorithms and methods used to overcome these problems. We will not go into de-tail, but we will try to give a general understanding. Our attention will go to the following topics. : An overview of the inspection process, with an emphasis on the second visual inspection. : The problems encountered in IC inspection, as opposed to the comparable PCB and mask inspection. : The image acquisition devices that can be used to obtain 'inspectable' images. : A general overview of the algorithms that can be used. : A short description of the algorithms developed at the ESAT-MI2 division of the katholieke Universiteit Leuven.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Survey of key technologies on millimeter-wave CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Yu, Fei; Gao, Lei; Li, Lixiang; Cai, Shuo; Wang, Wei; Wang, Chunhua

2018-05-01

In order to provide guidance for the development of high performance millimeter-wave complementary metal oxide semiconductor (MMW-CMOS) integrated circuits (IC), this paper provides a survey of key technologies on MMW-CMOS IC. Technical background of MMW wireless communications is described. Then the recent development of the critical technologies of the MMW-CMOS IC are introduced in detail and compared. A summarization is given, and the development prospects on MMW-CMOS IC are also discussed.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Realization of MEMS-IC Vertical Integration Utilizing Smart Bumpless Bonding

NASA Astrophysics Data System (ADS)

Shiozaki, Masayoshi; Moriguchi, Makoto; Sasaki, Sho; Oba, Masatoshi

This paper reports fundamental technologies, properties, and new experimental results of SBB (Smart Bumpless Bonding) to realize MEMS-IC vertical integration. Although conventional bonding technologies have had difficulties integrating MEMS and its processing circuit because of their rough bonding surfaces, fragile structures, and thermal restriction, SBB technology realized the vertical integration without thermal treatment, any adhesive materials including bumps, and chemical mechanical polishing. The SBB technology bonds sealing parts for vacuum sealing and electrodes for electrical connection simultaneously as published in previous experimental study. The plasma CVD SiO2 is utilized to realize vacuum sealing as sealing material. And Au projection studs are formed on each electrode and connected electrically between two wafers by compressive plastic deformation and surface activation. In this paper, new experimental results including vacuum sealing properties, electrical improvement, IC bonding results on the described fundamental concept and properties are reported.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

PubMed

Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

PubMed Central

Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

2016-01-01

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

PubMed

Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

2010-02-21

Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

Apparatus and method for defect testing of integrated circuits

DOEpatents

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

SEM probe of IC radiation sensitivity

NASA Technical Reports Server (NTRS)

Gauthier, M. K.; Stanley, A. G.

1979-01-01

Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

ERIC Educational Resources Information Center

Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

2010-01-01

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

ERIC Educational Resources Information Center

Muyskens, Mark A.

1997-01-01

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lew M.

2005-01-01

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

NASA Technical Reports Server (NTRS)

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

PubMed Central

Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

2013-01-01

A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

A Way to End the IC Designer Shortage.

ERIC Educational Resources Information Center

Robinson, Arthur L.

1980-01-01

Discusses the problem of the shortage of engineers capable of designing advanced integrated circuits (IC) and presents some suggestions for increasing the number of IC designers in universities and semiconductor companies. (HM)

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Emergency OSL/TL dosimetry with integrated circuits from mobile phones

NASA Astrophysics Data System (ADS)

Sholom, S.; McKeever, S. W. S.

2014-09-01

Integrated circuits (ICs) from several mobile phones were studied as possible emergency dosimeters using optically stimulated luminescence (OSL) and thermoluminescence (TL) techniques. Measurement protocols were developed for ICs that take into consideration the effect of sensitization of the samples with increasing dose as well as fading of the signals after sample exposure. It was found that the OSL technique has a higher sensitivity with ICs when compared to TL, while the TL signals were characterized by better stability with time after exposure. Values of minimum measurable doses were found to be in the range between a few tens of mGy and several tens of mGy for the tested samples. It was concluded that ICs from mobile phones could be used for emergency dose reconstruction.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

PubMed

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-08-04

The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

An analog integrated circuit beamformer for high-frequency medical ultrasound imaging.

PubMed

Gurun, Gokce; Zahorian, Jaime S; Sisman, Alper; Karaman, Mustafa; Hasler, Paul E; Degertekin, F Levent

2012-10-01

We designed and fabricated a dynamic receive beamformer integrated circuit (IC) in 0.35-μm CMOS technology. This beamformer IC is suitable for integration with an annular array transducer for high-frequency (30-50 MHz) intravascular ultrasound (IVUS) imaging. The beamformer IC consists of receive preamplifiers, an analog dynamic delay-and-sum beamformer, and buffers for 8 receive channels. To form an analog dynamic delay line we designed an analog delay cell based on the current-mode first-order all-pass filter topology, as the basic building block. To increase the bandwidth of the delay cell, we explored an enhancement technique on the current mirrors. This technique improved the overall bandwidth of the delay line by a factor of 6. Each delay cell consumes 2.1-mW of power and is capable of generating a tunable time delay between 1.75 ns to 2.5 ns. We successfully integrated the fabricated beamformer IC with an 8-element annular array. Experimental test results demonstrated the desired buffering, preamplification and delaying capabilities of the beamformer.

A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

NASA Astrophysics Data System (ADS)

Smith, Michael John Sebastian

Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

In situ high-resolution thermal microscopy on integrated circuits.

PubMed

Zhuo, Guan-Yu; Su, Hai-Ching; Wang, Hsien-Yi; Chan, Ming-Che

2017-09-04

The miniaturization of metal tracks in integrated circuits (ICs) can cause abnormal heat dissipation, resulting in electrostatic discharge, overvoltage breakdown, and other unwanted issues. Unfortunately, locating areas of abnormal heat dissipation is limited either by the spatial resolution or imaging acquisition speed of current thermal analytical techniques. A rapid, non-contact approach to the thermal imaging of ICs with sub-μm resolution could help to alleviate this issue. In this work, based on the intensity of the temperature-dependent two-photon fluorescence (TPF) of Rhodamine 6G (R6G) material, we developed a novel fast and non-invasive thermal microscopy with a sub-μm resolution. Its application to the location of hotspots that may evolve into thermally induced defects in ICs was also demonstrated. To the best of our knowledge, this is the first study to present high-resolution 2D thermal microscopic images of ICs, showing the generation, propagation, and distribution of heat during its operation. According to the demonstrated results, this scheme has considerable potential for future in situ hotspot analysis during the optimization stage of IC development.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

III–V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2–4 μm Wavelength Range

PubMed Central

Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

2017-01-01

The availability of silicon photonic integrated circuits (ICs) in the 2–4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III–V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III–V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy. PMID:28777291

Coplanar monolithic integrated circuits for low-noise communication and radar systems

NASA Astrophysics Data System (ADS)

Bessemoulin, Alexandre; Verweyen, Ludger; Marsetz, Waldemar; Massler, Hermann; Neumann, Markus; Hulsmann, Axel; Schlechtweg, Michael

1999-12-01

This paper presents coplanar millimeter-wave monolithic integrated circuits with high performance and small size for use in low noise communication and radar system applications. Technology and modeling issues with respect to active and passive elements are discussed first. In a second step, the potential of coplanar waveguides to realize compact ICs is illustrated through various design examples, such as low noise amplifiers, mixers and power amplifiers. The performance of multifunctional ICs is also presented by comparing simulated and measured results for a complete 77 GHz Transceive MMIC.

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement

NASA Astrophysics Data System (ADS)

Muyskens, Mark

1997-07-01

Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety of data-acquisition systems. Applications range from general chemistry to physical chemistry, particularly where computer interfaced, digital temperature measurement is desired. Included is a detailed description of our current design with suggestions for improvement and a performance evaluation of the precision in differential measurement and the time constant for responding to temperature change.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

2016-01-01

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

PubMed

Gao, Pingqi; Zhang, Qing

2014-02-14

Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1989-05-01

The objectives of this research are to develop analytical and computer aided design techniques for monolithic microwave and millimeter wave integrated circuits (MMIC and MIMIC) and subsystems and to design and fabricate those ICs. Emphasis was placed on heterojunction-based devices, especially the High Electron Mobility Transition (HEMT), for both low noise and medium power microwave and millimeter wave applications. Circuits to be considered include monolithic low noise amplifiers, power amplifiers, and distributed and feedback amplifiers. Interactive computer aided design programs were developed, which include large signal models of InP MISFETs and InGaAs HEMTs. Further, a new unconstrained optimization algorithm POSM was developed and implemented in the general Analysis and Design program for Integrated Circuit (ADIC) for assistance in the design of largesignal nonlinear circuits.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Modularized construction of general integrated circuits on individual carbon nanotubes.

PubMed

Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

2014-06-11

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

Fully Integrated Biopotential Acquisition Analog Front-End IC

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

2015-01-01

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

NASA Technical Reports Server (NTRS)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Low-power analog integrated circuits for wireless ECG acquisition systems.

PubMed

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

Innovative Teaching of IC Design and Manufacture Using the Superchip Platform

ERIC Educational Resources Information Center

Wilson, P. R.; Wilcock, R.; McNally, I.; Swabey, M.

2010-01-01

This paper describes how an intelligent chip architecture has allowed a large cohort of undergraduate (UG) students to be given effective practical insight into integrated circuit (IC) design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the "Superchip," was developed, which allows multiple student…

Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

ERIC Educational Resources Information Center

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

SiC Integrated Circuits for Power Device Drivers Able to Operate in Harsh Environments

NASA Astrophysics Data System (ADS)

Godignon, P.; Alexandru, M.; Banu, V.; Montserrat, J.; Jorda, X.; Vellvehi, M.; Schmidt, B.; Michel, P.; Millan, J.

2014-08-01

The currently developed SiC electronic devices are more robust to high temperature operation and radiation exposure damage than correspondingly rated Si ones. In order to integrate the existent SiC high power and high temperature electronics into more complex systems, a SiC integrated circuit (IC) technology capable of operation at temperatures substantially above the conventional ones is required. Therefore, this paper is a step towards the development of ICs-control electronics that have to attend the harsh environment power applications. Concretely, we present the development of SiC MESFET-based digital circuitry, able to integrate gate driver for SiC power devices. Furthermore, a planar lateral power MESFET is developed with the aim of its co-integration on the same chip with the previously mentioned SiC digital ICs technology. And finally, experimental results on SiC Schottky-gated devices irradiated with protons and electrons are presented. This development is based on the Tungsten-Schottky interface technology used for the fabrication of stable SiC Schottky diodes for the European Space Agency Mission BepiColombo.

GaAs integrated circuits and heterojunction devices

NASA Astrophysics Data System (ADS)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Scanning capacitance microscope as a tool for the characterization of integrated circuits

NASA Astrophysics Data System (ADS)

Born, A.; Wiesendanger, R.

With the decreasing size of integrated circuits (ICs), there is an increasing demand for the measurement of doping profiles with high spatial resolution. The scanning capacitance microscope (SCM) offers the possibility of measuring 2D dopant profiles with spatial resolution of less than 20 nm. A great problem of the SCM technique is the influence of previous measurements on subsequent ones. We have observed hysteresis in the SCM images and measured low-frequency C-V curves with high-frequency equipment. A theoretical model was developed to understand this phenomenon. We are now undertaking the first steps using the SCM as a standard device for the characterization of ICs.

Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

PubMed

Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

2018-01-01

Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

A Solder Based Self Assembly Project in an Introductory IC Fabrication Course

ERIC Educational Resources Information Center

Rao, Madhav; Lusth, John C.; Burkett, Susan L.

2015-01-01

Integrated circuit (IC) fabrication principles is an elective course in a senior undergraduate and early graduate student's curriculum. Over the years, the semiconductor industry relies heavily on students with developed expertise in the area of fabrication techniques, learned in an IC fabrication theory and laboratory course. The theory course…

Integrated circuit detector technology in abdominal CT: added value in obese patients.

PubMed

Morsbach, Fabian; Bickelhaupt, Sebastian; Rätzer, Susan; Schmidt, Bernhard; Alkadhi, Hatem

2014-02-01

The purpose of this article was to assess the effect of an integrated circuit (IC) detector for abdominal CT on image quality. In the first study part, an abdominal phantom was scanned with various extension rings using a CT scanner equipped with a conventional discrete circuit (DC) detector and on the same scanner with an IC detector (120 kVp, 150 effective mAs, and 75 effective mAs). In the second study part, 20 patients were included who underwent abdominal CT both with the IC detector and previously at similar protocol parameters (120 kVp tube current-time product and 150 reference mAs using automated tube current modulation) with the DC detector. Images were reconstructed with filtered back projection. Image quality in the phantom was higher for images acquired with the IC compared with the DC detector. There was a gradually increasing noise reduction with increasing phantom sizes, with the highest (37% in the largest phantom) at 75 effective mAs (p < 0.001). In patients, noise was overall significantly (p = 0.025) reduced by 6.4% using the IC detector. Similar to the phantom, there was a gradual increase in noise reduction to 7.9% in patients with a body mass index of 25 kg/m(2) or lower (p = 0.008). Significant correlation was found in patients between noise and abdominal diameter in DC detector images (r = 0.604, p = 0.005), whereas no such correlation was found for the IC detector (r = 0.427, p = 0.060). Use of an IC detector in abdominal CT improves image quality and reduces image noise, particularly in overweight and obese patients. This noise reduction has the potential for dose reduction in abdominal CT.

An integrated control and readout circuit for implantable multi-target electrochemical biosensing.

PubMed

Ghoreishizadeh, Sara S; Baj-Rossi, Camilla; Cavallini, Andrea; Carrara, Sandro; De Micheli, Giovanni

2014-12-01

We describe an integrated biosensor capable of sensing multiple molecular targets using both cyclic voltammetry (CV) and chronoamperometry (CA). In particular, we present our custom IC to realize voltage control and current readout of the biosensors. A mixed-signal circuit block generates sub-Hertz triangular waveform for the biosensors by means of a direct-digital-synthesizer to control CV. A current to pulse-width converter is realized to output the data for CA measurement. The IC is fabricated in 0.18 μm technology. It consumes 220 μW from 1.8 V supply voltage, making it suitable for remotely-powered applications. Electrical measurements show excellent linearity in sub- μA current range. Electrochemical measurements including CA measurements of glucose and lactate and CV measurements of the anti-cancer drug Etoposide have been acquired with the fabricated IC and compared with a commercial equipment. The results obtained with the fabricated IC are in good agreement with those of the commercial equipment for both CV and CA measurements.

Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

2001-01-01

In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits.

PubMed

Obeng, Yaw; Okoro, C A; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J

The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2013-01-01

A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

Soldering Tool for Integrated Circuits

NASA Technical Reports Server (NTRS)

Takahashi, Ted H.

1987-01-01

Many connections soldered simultaneously in confined spaces. Improved soldering tool bonds integrated circuits onto printed-circuit boards. Intended especially for use with so-called "leadless-carrier" integrated circuits.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

A study on the recycling of scrap integrated circuits by leaching.

PubMed

Lee, Ching-Hwa; Tang, Li-Wen; Popuri, Srinivasa R

2011-07-01

In order to minimize the problem of pollution and to conserve limited natural resources, a method to recover the valuable metals such as gold, silver and copper) present in the scrap integrated circuits (ICs) was developed in the present study. Roasting, grinding, screening, magnetic separation, melting and leaching were adopted to investigate the efficiency of recovery of gold, silver and copper from scrap ICs. The collected scrap IC samples were roasted at 850 °C to destroy their plastic resin sealing material, followed by screening and magnetic separation to separate the metals from the resin residue. The non-ferrous materials (0.840 mm) were mainly composed of copper and could be melted into a copper alloy. Non-ferrous materials containing gold (860.05 ppm), silver (1323.12 ppm) and copper (37259.7 ppm) (size less than 50 mesh) were recovered 100% by a leaching process and thiourea was used as a leaching reagent.

INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

PubMed

Sholom, S; McKeever, S W S

2016-09-01

In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Analog/digital pH meter system I.C.

NASA Technical Reports Server (NTRS)

Vincent, Paul; Park, Jea

1992-01-01

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Intermetallic compounds in 3D integrated circuits technology: a brief review

NASA Astrophysics Data System (ADS)

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-12-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Intermetallic compounds in 3D integrated circuits technology: a brief review

PubMed Central

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

Abstract The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed. PMID:29057024

Intermetallic compounds in 3D integrated circuits technology: a brief review.

PubMed

Annuar, Syahira; Mahmoodian, Reza; Hamdi, Mohd; Tu, King-Ning

2017-01-01

The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

Integrated circuit-based instrumentation for microchip capillary electrophoresis.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Martel, S; Elliott, D G; Backhouse, C J

2010-09-01

Although electrophoresis with laser-induced fluorescence (LIF) detection has tremendous potential in lab on chip-based point-of-care disease diagnostics, the wider use of microchip electrophoresis has been limited by the size and cost of the instrumentation. To address this challenge, the authors designed an integrated circuit (IC, i.e. a microelectronic chip, with total silicon area of <0.25 cm2, less than 5 mmx5 mm, and power consumption of 28 mW), which, with a minimal additional infrastructure, can perform microchip electrophoresis with LIF detection. The present work enables extremely compact and inexpensive portable systems consisting of one or more complementary metal-oxide-semiconductor (CMOS) chips and several other low-cost components. There are, to the authors' knowledge, no other reports of a CMOS-based LIF capillary electrophoresis instrument (i.e. high voltage generation, switching, control and interface circuit combined with LIF detection). This instrument is powered and controlled using a universal serial bus (USB) interface to a laptop computer. The authors demonstrate this IC in various configurations and can readily analyse the DNA produced by a standard medical diagnostic protocol (end-labelled polymerase chain reaction (PCR) product) with a limit of detection of approximately 1 ng/microl (approximately 1 ng of total DNA). The authors believe that this approach may ultimately enable lab-on-a-chip-based electrophoretic instruments that cost on the order of several dollars.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

DOEpatents

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Pyrolysis characteristics of integrated circuit boards at various particle sizes and temperatures.

PubMed

Chiang, Hung-Lung; Lin, Kuo-Hsiung; Lai, Mei-Hsiu; Chen, Ting-Chien; Ma, Sen-Yi

2007-10-01

A pyrolysis method was employed to recycle the metals and brominated compounds blended into printed circuit boards. This research investigated the effect of particle size and process temperature on the element composition of IC boards and pyrolytic residues, liquid products, and water-soluble ionic species in the exhaust, with the overall goal being to identify the pyrolysis conditions that will have the least impact on the environment. Integrated circuit (IC) boards were crushed into 5-40 mesh (0.71-4.4mm), and the crushed particles were pyrolyzed at temperatures ranging from 200 to 500 degrees C. The thermal decomposition kinetics were measured by a thermogravimetric (TG) analyzer. The composition of pyrolytic residues was analyzed by Energy Dispersive X-ray Spectrometer (EDS), Inductively Coupled Plasma Atomic Emission Spectrometer (ICP-AES) and Inductively Coupled Plasma-Mass Spectrometry (ICP-MS). In addition, the element compositions of liquid products were analyzed by ICP-AES and ICP-MS. Pyrolytic exhaust was collected by a water-absorption system in an ice-bath cooler, and IC analysis showed that the absorbed solution comprised 11 ionic species. Based on the pyrolytic kinetic parameters of TG analysis and pyrolytic residues at various temperatures for 30 min, the effect of particle size was insignificant in this study, and temperature was the key factor for the IC board pyrolysis. Two stages of decomposition were found for IC board pyrolysis under nitrogen atmosphere. The activation energy was 38-47 kcal/mol for the first-stage reaction and 5.2-9.4 kcal/mol for the second-stage reaction. Metal content was low in the liquid by-product of the IC board pyrolysis process, which is an advantage in that the liquid product could be used as a fuel. Brominate and ammonium were the main water-soluble ionic species of the pyrolytic exhaust. A plan for their safe and effective disposal must be developed if the pyrolytic recycling process is to be applied to IC boards.

The basic circuit of the IC: tectothalamic neurons with different patterns of synaptic organization send different messages to the thalamus

PubMed Central

Ito, Tetsufumi; Oliver, Douglas L.

2012-01-01

The inferior colliculus (IC) in the midbrain of the auditory system uses a unique basic circuit to organize the inputs from virtually all of the lower auditory brainstem and transmit this information to the medial geniculate body (MGB) in the thalamus. Here, we review the basic circuit of the IC, the neuronal types, the organization of their inputs and outputs. We specifically discuss the large GABAergic (LG) neurons and how they differ from the small GABAergic (SG) and the more numerous glutamatergic neurons. The somata and dendrites of LG neurons are identified by axosomatic glutamatergic synapses that are lacking in the other cell types and exclusively contain the glutamate transporter VGLUT2. Although LG neurons are most numerous in the central nucleus of the IC (ICC), an analysis of their distribution suggests that they are not specifically associated with one set of ascending inputs. The inputs to ICC may be organized into functional zones with different subsets of brainstem inputs, but each zone may contain the same three neuron types. However, the sources of VGLUT2 axosomatic terminals on the LG neuron are not known. Neurons in the dorsal cochlear nucleus, superior olivary complex, intermediate nucleus of the lateral lemniscus, and IC itself that express the gene for VGLUT2 only are the likely origin of the dense VGLUT2 axosomatic terminals on LG tectothalamic neurons. The IC is unique since LG neurons are GABAergic tectothalamic neurons in addition to the numerous glutamatergic tectothalamic neurons. SG neurons evidently target other auditory structures. The basic circuit of the IC and the LG neurons in particular, has implications for the transmission of information about sound through the midbrain to the MGB. PMID:22855671

Sensor readout detector circuit

DOEpatents

Chu, Dahlon D.; Thelen, Jr., Donald C.

1998-01-01

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Sensor readout detector circuit

DOEpatents

Chu, D.D.; Thelen, D.C. Jr.

1998-08-11

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation.

PubMed

Chen, Chang Hao; McCullagh, Elizabeth A; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C

2017-03-01

The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics. A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC. The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design. A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2017-01-01

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

An assessment of the impact of the Department of Defense very high speed integrated circuit program

NASA Astrophysics Data System (ADS)

1982-01-01

The technical and economic effects of the Department of Defense's (DoD) development program for very-high-speed integrated circuits (VHSIC) are examined. The probable effects of this program on the domestic aspects and international position of the integrated-circuit (IC) industry as they relate to the interests of the general public and the DoD are considered. The report presents a review of the unique DoD needs that motivate VHSIC research and development; an estimate of the degree of which these needs are likely to be met by the VHSIC program; a discussion of the effects of the program's demands for manpower, materials, and design and processing technologies; the problems connected with the program's technology export controls; and an assessment of the impact of the program on the structure of the U.S. integrated-circuit industry, its continued development and production of civilian consumer products, and its international competitive position.

The use of hybrid integrated circuit techniques in biotelemetry applications

NASA Technical Reports Server (NTRS)

Fryer, T. B.

1977-01-01

A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

Technology CAD for integrated circuit fabrication technology development and technology transfer

NASA Astrophysics Data System (ADS)

Saha, Samar

2003-07-01

In this paper systematic simulation-based methodologies for integrated circuit (IC) manufacturing technology development and technology transfer are presented. In technology development, technology computer-aided design (TCAD) tools are used to optimize the device and process parameters to develop a new generation of IC manufacturing technology by reverse engineering from the target product specifications. While in technology transfer to manufacturing co-location, TCAD is used for process centering with respect to high-volume manufacturing equipment of the target manufacturing equipment of the target manufacturing facility. A quantitative model is developed to demonstrate the potential benefits of the simulation-based methodology in reducing the cycle time and cost of typical technology development and technology transfer projects over the traditional practices. The strategy for predictive simulation to improve the effectiveness of a TCAD-based project, is also discussed.

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

InP-based three-dimensional photonic integrated circuits

NASA Astrophysics Data System (ADS)

Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

Device-level and module-level three-dimensional integrated circuits created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-07-01

This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

NASA Astrophysics Data System (ADS)

Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

2017-02-01

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

NASA Astrophysics Data System (ADS)

Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

High ESD Breakdown-Voltage InP HBT Transimpedance Amplifier IC for Optical Video Distribution Systems

NASA Astrophysics Data System (ADS)

Sano, Kimikazu; Nagatani, Munehiko; Mutoh, Miwa; Murata, Koichi

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000V for power supply terminals, ±200V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7pA/√Hz averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

A bipolar analog front-end integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low noise, low power, high bandwidth, radiation hard, silicon bipolar transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using CBIC-U2, 4 GHz f(sub T) complementary bipolar technology. Each channel contains the following functions: low noise preamplification, pulse shaping, and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 micron pitch double-sided silicon strip detector. The chip measures 6.8 mm by 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to four times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Phi = 10(exp 14) protons/sq cm have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

Development of high-performance printed organic field-effect transistors and integrated circuits.

PubMed

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

NASA Technical Reports Server (NTRS)

Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

2016-01-01

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

Layout-aware simulation of soft errors in sub-100 nm integrated circuits

NASA Astrophysics Data System (ADS)

Balbekov, A.; Gorbunov, M.; Bobkov, S.

2016-12-01

Single Event Transient (SET) caused by charged particle traveling through the sensitive volume of integral circuit (IC) may lead to different errors in digital circuits in some cases. In technologies below 180 nm, a single particle can affect multiple devices causing multiple SET. This fact adds the complexity to fault tolerant devices design, because the schematic design techniques become useless without their layout consideration. The most common layout mitigation technique is a spatial separation of sensitive nodes of hardened circuits. Spatial separation decreases the circuit performance and increases power consumption. Spacing should thus be reasonable and its scaling follows the device dimensions' scaling trend. This paper presents the development of the SET simulation approach comprised of SPICE simulation with "double exponent" current source as SET model. The technique uses layout in GDSII format to locate nearby devices that can be affected by a single particle and that can share the generated charge. The developed software tool automatizes multiple simulations and gathers the produced data to present it as the sensitivity map. The examples of conducted simulations of fault tolerant cells and their sensitivity maps are presented in this paper.

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Reducing image noise in computed tomography (CT) colonography: effect of an integrated circuit CT detector.

PubMed

Liu, Yu; Leng, Shuai; Michalak, Gregory J; Vrieze, Thomas J; Duan, Xinhui; Qu, Mingliang; Shiung, Maria M; McCollough, Cynthia H; Fletcher, Joel G

2014-01-01

To investigate whether the integrated circuit (IC) detector results in reduced noise in computed tomography (CT) colonography (CTC). Three hundred sixty-six consecutive patients underwent clinically indicated CTC using the same CT scanner system, except for a difference in CT detectors (IC or conventional). Image noise, patient size, and scanner radiation output (volume CT dose index) were quantitatively compared between patient cohorts using each detector system, with separate comparisons for the abdomen and pelvis. For the abdomen and pelvis, despite significantly larger patient sizes in the IC detector cohort (both P < 0.001), image noise was significantly lower (both P < 0.001), whereas volume CT dose index was unchanged (both P > 0.18). Based on the observed image noise reduction, radiation dose could alternatively be reduced by approximately 20% to result in similar levels of image noise. Computed tomography colonography images acquired using the IC detector had significantly lower noise than images acquired using the conventional detector. This noise reduction can permit further radiation dose reduction in CTC.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Photonic Integrated Circuits

NASA Technical Reports Server (NTRS)

Krainak, Michael; Merritt, Scott

2016-01-01

Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

PubMed

Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

2013-12-01

Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

NASA Technical Reports Server (NTRS)

Lin, Shu; Uehara, Gregory T.; Nakamura, Eric B.; Chu, Cecilia W. P.

1996-01-01

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

NASA Technical Reports Server (NTRS)

Lin, Shu; Uehara, Gregory T.; Nakamura, Eric B.; Chu, Cecilia W. P.

1996-01-01

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement

Reusable vibration resistant integrated circuit mounting socket

DOEpatents

Evans, Craig N.

1995-01-01

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Large Scale Integrated Circuits for Military Applications.

DTIC Science & Technology

1977-05-01

economic incentive for riarrowing this gap is examined, y (U)^wo"categories of cost are analyzed: the direct life cycle cost of the integrated circuit...dependence of these costs on the physical charac- teristics of the integrated circuits is discussed. (U) The economic and physical characteristics of... economic incentive for narrowing this gap is examined. Two categories of cost are analyzed: the direct life cycle cost of the integrated circuit

Optical waveguide circuit board with a surface-mounted optical receiver array

NASA Astrophysics Data System (ADS)

Thomson, J. E.; Levesque, Harold; Savov, Emil; Horwitz, Fred; Booth, Bruce L.; Marchegiano, Joseph E.

1994-03-01

A photonic circuit board is fabricated for potential application to interchip and interboard parallel optical links. The board comprises photolithographically patterned polymer optical waveguides on a conventional glass-epoxy electrical circuit board and a surface-mounted integrated circuit (IC) package that optically and electrically couples to an optoelectronic IC. The waveguide circuits include eight-channel arrays of straights, cross-throughs, curves, self- aligning interconnects to multi-fiber ribbon, and out-of-plane turning mirrors. A coherent, fused bundle of optical fibers couples light between 45-deg waveguide mirrors and a GaAs receiver array in the IC package. The fiber bundle is easily aligned to the mirrors and the receivers and is amenable to surface mounting and hermetic sealing. The waveguide-receiver- array board achieved error-free data rates up to 1.25 Gbits/s per channel, and modal noise was shown to be negligible.

Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

PubMed Central

Roever, Stefan

2012-01-01

A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

Electro-optical Probing Of Terahertz Integrated Circuits

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Using Tablet PCs and Interactive Software in IC Design Courses to Improve Learning

ERIC Educational Resources Information Center

Simoni, M.

2011-01-01

This paper describes an initial study of using tablet PCs and interactive course software in integrated circuit (IC) design courses. A rapidly growing community is demonstrating how this technology can improve learning and retention of material by facilitating interaction between faculty and students via cognitive exercises during lectures. While…

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

NASA Astrophysics Data System (ADS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-08-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.

3D-ICs created using oblique processing

NASA Astrophysics Data System (ADS)

Burckel, D. Bruce

2016-03-01

This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

NASA Astrophysics Data System (ADS)

Aoyagi, Masahiro; Nakagawa, Hiroshi

1997-07-01

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

2016-01-01

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

2009-01-01

The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Monolithically integrated bacteriorhodopsin/semiconductor opto-electronic integrated circuit for a bio-photoreceiver.

PubMed

Xu, J; Bhattacharya, P; Váró, G

2004-03-15

The light-sensitive protein, bacteriorhodopsin (BR), is monolithically integrated with an InP-based amplifier circuit to realize a novel opto-electronic integrated circuit (OEIC) which performs as a high-speed photoreceiver. The circuit is realized by epitaxial growth of the field-effect transistors, currently used semiconductor device and circuit fabrication techniques, and selective area BR electro-deposition. The integrated photoreceiver has a responsivity of 175 V/W and linear photoresponse, with a dynamic range of 16 dB, with 594 nm photoexcitation. The dynamics of the photochemical cycle of BR has also been modeled and a proposed equivalent circuit simulates the measured BR photoresponse with good agreement.

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

PubMed

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1993-12-31

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components.« less

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1995-08-29

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components. 11 figs.« less

Integrated circuits, and design and manufacture thereof

DOEpatents

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

LEC GaAs for integrated circuit applications

NASA Technical Reports Server (NTRS)

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Integrated-Circuit Pseudorandom-Number Generator

NASA Technical Reports Server (NTRS)

Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

1992-01-01

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

PubMed

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

NASA Technical Reports Server (NTRS)

Moorthy, Hari T.; Lin, Shu; Uehara, Gregory T.

1997-01-01

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

PubMed Central

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

2009-12-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Laser Integration on Silicon Photonic Circuits Through Transfer Printing

DTIC Science & Technology

2017-03-10

AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...TYPE Final 3. DATES COVERED (From - To) 15 Sep 2015 to 14 Sep 2016 4. TITLE AND SUBTITLE Laser integration on silicon photonic circuits through...parallel integration of III-V lasers on silicon photonic integrated circuits. The report discusses the technological process that has been developed as

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

Integrated circuit cooled turbine blade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.

A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channelmore » connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.« less

Addressable-Matrix Integrated-Circuit Test Structure

NASA Technical Reports Server (NTRS)

Sayah, Hoshyar R.; Buehler, Martin G.

1991-01-01

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation

PubMed Central

Chen, Chang Hao; McCullagh, Elizabeth A.; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C.

2017-01-01

The ability to record and to control action potential firing in neuronal circuits of the brain is critical to understand how the brain functions on the cellular and network levels. Recent development of optogenetic proteins allows direct stimulation or inhibition of action potential firing of neurons upon optical illumination. In this paper, we combined a low-noise and high input impedance (or low input capacitance) neural recording amplifier, and a high current laser/LED driver in a monolithic integrated circuit (IC) for simultaneous neural recording and optogenetic neural control. The low input capacitance of the amplifier (9.7 pF) was achieved through adding a dedicated unity gain input stage optimized for high impedance metal electrodes. The input referred noise of the amplifier was measured to be 4.57 µVrms, which is lower than the estimated thermal noise of the metal electrode. Thus, action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of ~6.6. The LED/laser current driver delivers a maximum current of 330 mA to generate adequate light for optogenetic control. We experimentally tested the functionality of the IC with an anesthetized Mongolian gerbil and recorded auditory stimulated action potentials from the inferior colliculus. Furthermore, we showed that spontaneous firing of 5th (trigeminal) nerve fibers was inhibited using the optogenetic protein Halorhodopsin. A noise model was also derived including the equivalent electronic components of the metal electrode and the high current driver to guide the design. PMID:28221990

An integrated circuit switch

NASA Technical Reports Server (NTRS)

Bonin, E. L.

1969-01-01

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

Wide-band polarization controller for Si photonic integrated circuits.

PubMed

Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

2016-12-15

A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo S.; Keymeulen, Didier; Ramesham, Rajeshuni; Neff, Joseph; Katkoori, Srinivas

2006-01-01

Demonstration of a self-reconfigurable Integrated Circuit (IC) that would operate under extreme temperature (-180 C and 120 C) and radiation (300krad), without the protection of thermal controls and radiation shields. Self-Reconfigurable Electronics platform: a) Evolutionary Processor (EP) to run reconfiguration mechanism; b) Reconfigurable chip (FPGA, FPAA, etc).

Mouldable all-carbon integrated circuits.

PubMed

Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

2013-01-01

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Mouldable all-carbon integrated circuits

NASA Astrophysics Data System (ADS)

Sun, Dong-Ming; Timmermans, Marina Y.; Kaskela, Antti; Nasibulin, Albert G.; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I.; Ohno, Yutaka

2013-08-01

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027cm2V-1s-1 and an ON/OFF ratio of 105. The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage

DTIC Science & Technology

2017-03-01

camouflage; obfuscation; SAT; key extraction; reverse engineering; security; trusted electronics Introduction Integrated Circuit (IC) designs are...Encryption Algorithms”, Hardware Oriented Security and Trust , 2015. 3. Rajendran J., Pino, Y., Sinanoglu, O., Karri, R., “Security Analysis of Logic

Correlation of the ionisation response at selected points of IC sensitive regions with SEE sensitivity parameters under pulsed laser irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gordienko, A V; Mavritskii, O B; Egorov, A N

2014-12-31

The statistics of the ionisation response amplitude measured at selected points and their surroundings within sensitive regions of integrated circuits (ICs) under focused femtosecond laser irradiation is obtained for samples chosen from large batches of two types of ICs. A correlation between these data and the results of full-chip scanning is found for each type. The criteria for express validation of IC single-event effect (SEE) hardness based on ionisation response measurements at selected points are discussed. (laser applications and other topics in quantum electronics)

ELECTRONIC INTEGRATING CIRCUIT

DOEpatents

Englemann, R.H.

1963-08-20

An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

Microwave GaAs Integrated Circuits On Quartz Substrates

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Package for integrated optic circuit and method

DOEpatents

Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

1998-01-01

A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

Package for integrated optic circuit and method

DOEpatents

Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

1998-08-04

A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

Mod 1 ICS TI Report: ICS Conversion of a 140% HPGe Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bounds, John Alan

This report evaluates the Mod 1 ICS, an electrically cooled 140% HPGe detector. It is a custom version of the ORTEC Integrated Cooling System (ICS) modified to make it more practical for us to use in the field. Performance and operating characteristics of the Mod 1 ICS are documented, noting both pros and cons. The Mod 1 ICS is deemed a success. Recommendations for a Mod 2 ICS, a true field prototype, are provided.

Present, future of automotive hybrid IC applications discussed

NASA Astrophysics Data System (ADS)

Matsuda, Nobuyoshi; Fukuoka, Atuhisa

1987-09-01

Hybrid ICs are presently utilized in various fields such as commercial televisions, VTRs, and audio devices, industrial usage of communication equipment, computers, terminals, and automobiles. Its applications and environments are various and diverse. The functions required for hybrid ICs vary from simple high density mounting for a system to the realization of high mechanisms with the application of function timing. The functions are properly used depending upon the system with its hybrid ICs and its circuit composition. Considering structure and reliability requirements for automotive hybrid ICs, an application example for hybrid ICs which use the package (COMPACT), will be discussed.

Improving depiction of temporal bone anatomy with low-radiation dose CT by an integrated circuit detector in pediatric patients: a preliminary study.

PubMed

He, Jingzhen; Zu, Yuliang; Wang, Qing; Ma, Xiangxing

2014-12-01

The purpose of this study was to determine the performance of low-dose computed tomography (CT) scanning with integrated circuit (IC) detector in defining fine structures of temporal bone in children by comparing with the conventional detector. The study was performed with the approval of our institutional review board and the patients' anonymity was maintained. A total of 86 children<3 years of age underwent imaging of temporal bone with low-dose CT (80 kV/150 mAs) equipped with either IC detector or conventional discrete circuit (DC) detector. The image noise was measured for quantitative analysis. Thirty-five structures of temporal bone were further assessed and rated by 2 radiologists for qualitative analysis. κ Statistics were performed to determine the agreement reached between the 2 radiologists on each image. Mann-Whitney U test was used to determine the difference in image quality between the 2 detector systems. Objective analysis showed that the image noise was significantly lower (P<0.001) with the IC detector than with the DC detector. The κ values for qualitative assessment of the 35 fine anatomical structures revealed high interobserver agreement. The delineation for 30 of the 35 landmarks (86%) with the IC detector was superior to that with the conventional DC detector (P<0.05) although there were no differences in the delineation of the remaining 5 structures (P>0.05). The low-dose CT images acquired with the IC detector provide better depiction of fine osseous structures of temporal bone than that with the conventional DC detector.

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

NASA Astrophysics Data System (ADS)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Wide-temperature integrated operational amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad (Inventor); Levanas, Greg (Inventor); Chen, Yuan (Inventor); Cozy, Raymond S. (Inventor); Greenwell, Robert (Inventor); Terry, Stephen (Inventor); Blalock, Benjamin J. (Inventor)

2009-01-01

The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.

Assessment of image quality and low-contrast detectability in abdominal CT of obese patients: comparison of a novel integrated circuit with a conventional discrete circuit detector at different tube voltages.

PubMed

Euler, A; Heye, T; Kekelidze, M; Bongartz, G; Szucs-Farkas, Z; Sommer, C; Schmidt, B; Schindera, Sebastian T

2015-03-01

To compare image quality and low-contrast detectability of an integrated circuit (IC) detector in abdominal CT of obese patients with conventional detector technology at low tube voltages. A liver phantom with 45 lesions was placed in a water container to mimic an obese patient and examined on two different CT systems at 80, 100 and 120 kVp. The systems were equipped with either the IC or conventional detector. Image noise was measured, and the contrast-to-noise-ratio (CNR) was calculated. Low-contrast detectability was assessed independently by three radiologists. Radiation dose was estimated by the volume CT dose index (CTDIvol). The image noise was significantly lower, and the CNR was significantly higher with the IC detector at 80, 100 and 120 kVp, respectively (P = 0.023). The IC detector resulted in an increased lesion detection rate at 80 kVp (38.1 % vs. 17.2 %) and 100 kVp (57.0 % vs. 41.0 %). There was no difference in the detection rate between the IC detector at 100 kVp and the conventional detector at 120 kVp (57.0 % vs. 62.2 %). The CTDIvol at 80, 100 and 120 kVp measured 4.5-5.2, 7.3-7.9 and 9.8-10.2 mGy, respectively. The IC detector at 100 kVp resulted in similar low-contrast detectability compared to the conventional detector with a 120-kVp protocol at a radiation dose reduction of 37 %.

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

PubMed

Cai, Jinguang; Lv, Chao; Watanabe, Akira

2018-01-10

Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices.

PubMed

Vanhoestenberghe, A; Donaldson, N

2013-06-01

Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

Test Structures For Bumpy Integrated Circuits

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Micromachined integrated quantum circuit containing a superconducting qubit

NASA Astrophysics Data System (ADS)

Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

Development, Integration and Testing of Automated Triggering Circuit for Hybrid DC Circuit Breaker

NASA Astrophysics Data System (ADS)

Kanabar, Deven; Roy, Swati; Dodiya, Chiragkumar; Pradhan, Subrata

2017-04-01

A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed.

Non-invasive current and voltage imaging techniques for integrated circuits using scanning probe microscopy. Final report, LDRD Project FY93 and FY94

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, A.N.; Cole, E.I. Jr.; Tangyunyong, Paiboon

This report describes the first practical, non-invasive technique for detecting and imaging currents internal to operating integrated circuits (ICs). This technique is based on magnetic force microscopy and was developed under Sandia National Laboratories` LDRD (Laboratory Directed Research and Development) program during FY 93 and FY 94. LDRD funds were also used to explore a related technique, charge force microscopy, for voltage probing of ICs. This report describes the technical work performed under this LDRD as well as the outcomes of the project in terms of publications and awards, intellectual property and licensing, synergistic work, potential future work, hiring ofmore » additional permanent staff, and benefits to DOE`s defense programs (DP).« less

Integrated Circuit Immunity

NASA Technical Reports Server (NTRS)

Sketoe, J. G.; Clark, Anthony

2000-01-01

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Displacement Damage in Bipolar Linear Integrated Circuits

NASA Technical Reports Server (NTRS)

Rax, B. G.; Johnston, A. H.; Miyahira, T.

2000-01-01

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Silica Integrated Optical Circuits Based on Glass Photosensitivity

NASA Technical Reports Server (NTRS)

Abushagur, Mustafa A. G.

1999-01-01

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Subsurface microscopy of interconnect layers of an integrated circuit.

PubMed

Köklü, F Hakan; Unlü, M Selim

2010-01-15

We apply the NA-increasing lens technique to confocal and wide-field backside microscopy of integrated circuits. We demonstrate 325 nm (lambda(0)/4) lateral spatial resolution while imaging metal structures located inside the interconnect layer of an integrated circuit. Vectorial field calculations are presented justifying our findings.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Good trellises for IC implementation of viterbi decoders for linear block codes

NASA Technical Reports Server (NTRS)

Lin, Shu; Moorthy, Hari T.; Uehara, Gregory T.

1996-01-01

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T = 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Silicon photonic IC embedded optical-PCB for high-speed interconnect application

NASA Astrophysics Data System (ADS)

Kallega, Rakshitha; Nambiar, Siddharth; Kumar, Abhai; Ranganath, Praveen; Selvaraja, Shankar Kumar

2018-02-01

Optical-Printed Circuit Board (PCB) is an emerging optical interconnect technology to bridge the gap between the board edge and the processing module. The technology so far has been used as a broadband transmitter using polymer waveguides in the PCB. In this paper, we report a Silicon Nitride based photonic IC embedded in the PCB along with the polymers as waveguides in the PCB. The motivation for such integration is to bring routing capability and to reduce the power loss due to broadcasting mode.

Silicon millimetre-wave integrated-circuit (SIMMWIC) SPST switch

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-10-01

The first silicon millimetre-wave integrated circuit (SIMMWIC) has been successfully fabricated. This circuit is a monolithic SPST switch with a 3 dB bandwidth of 20 percent and a minimum isolation of 21.6 dB across the band (centre frequency is 36.75 GHz). This monolithic circuit is a low-cost reproducible building block for all millimetre-wave control applications.

Bioluminescent bioreporter integrated circuit

DOEpatents

Simpson, Michael L.; Sayler, Gary S.; Paulus, Michael J.

2000-01-01

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

High frequency characteristic of a monolithic 500 °C OpAmp-RC integrator in SiC bipolar IC technology

NASA Astrophysics Data System (ADS)

Tian, Ye; Zetterling, Carl-Mikael

2017-09-01

This paper presents a comprehensive investigation of the frequency response of a monolithic OpAmp-RC integrator implemented in a 4H-SiC bipolar IC technology. The circuits and devices have been measured and characterized from 27 to 500 °C. The devices have been modelled to identify that the substrate capacitance is a dominant factor affecting the OpAmp's high-frequency response. Large Miller compensation capacitors of more than 540 pF are required to ensure stability of the internal OpAmp. The measured unit-gain-bandwidth product of the OpAmp is ∼1.1 MHz at 27 °C, and decreases to ∼0.5 MHz at 500 °C mainly due to the reduction of the transistor's current gain. On the other hand, it is not necessary to compensate the integrator in a relatively wide bandwidth ∼0.7 MHz over the investigated temperature range. At higher frequencies, the integrator's frequency response has been identified to be significantly affected by that of the OpAmp and load impedance. This work demonstrates the potential of this technology for high temperature applications requiring bandwidths of several megahertz.

Microwave integrated circuit for Josephson voltage standards

NASA Technical Reports Server (NTRS)

Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

1980-01-01

A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications.

PubMed

Bhattacharyya, Mayukh; Gruenwald, Waldemar; Jansen, Dirk; Reindl, Leonhard; Aghassi-Hagmann, Jasmin

2018-05-07

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

PubMed Central

Gruenwald, Waldemar; Jansen, Dirk; Aghassi-Hagmann, Jasmin

2018-01-01

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 mm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches. PMID:29735939

Microwave integrated circuits for space applications

NASA Technical Reports Server (NTRS)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Warpage of QFN Package in Post Mold Cure Process of integrated circuit packaging

NASA Astrophysics Data System (ADS)

Sriwithoon, Nattha; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about warpage of QFN package in post mold cure process of integrated circuit (IC) packages using pre-plated (PPF) leadframe. For IC package, epoxy molding compound (EMC) are molded by cross linking of compound stiffness but incomplete crosslinked network and leading the fully cured thermoset by post mold cure (PMC) process. The cure temperature of PMC can change microstructure of EMC in term of stress inside the package and effect to warpage of the package due to coefficient of thermal expansion (CTE) between EMC and leadframe. In experiment, cure temperatures were varied to check the effect of internal stress due to different cure temperature after completed post mold cure for TDFN 2×3 8L. The cure temperature were varied with 180 °C, 170 °C, 160 °C, and 150°C with cure time 4 and 6 hours, respectively. For analysis, the TDFN 2×3 8L packages were analyzed the warpage by thickness gauge and scanning acoustic microscope (SAM) after take the test samples out from the oven cure. The results confirmed that effect of different CTE between EMC and leadframe due to different cure temperature resulting to warpage of the TDFN 2×3 8L packages.

Millimeter-wave and terahertz integrated circuit antennas

NASA Technical Reports Server (NTRS)

Rebeiz, Gabriel M.

1992-01-01

This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

NASA Astrophysics Data System (ADS)

Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

2017-11-01

In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium-nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (~2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs.

Chemical sensors fabricated by a photonic integrated circuit foundry

NASA Astrophysics Data System (ADS)

Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

2018-02-01

We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

PubMed

Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

2010-11-07

We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

A multifactor regulatory circuit involving H-NS, VirF and an antisense RNA modulates transcription of the virulence gene icsA of Shigella flexneri.

PubMed

Tran, Chi Nhan; Giangrossi, Mara; Prosseda, Gianni; Brandi, Anna; Di Martino, Maria Letizia; Colonna, Bianca; Falconi, Maurizio

2011-10-01

The icsA gene of Shigella encodes a structural protein involved in colonization of the intestinal mucosa by bacteria. This gene is expressed upon invasion of the host and is controlled by a complex regulatory circuit involving the nucleoid protein H-NS, the AraC-like transcriptional activator VirF, and a 450 nt antisense RNA (RnaG) acting as transcriptional attenuator. We investigated on the interplay of these factors at the molecular level. DNase I footprints reveal that both H-NS and VirF bind to a region including the icsA and RnaG promoters. H-NS is shown to repress icsA transcription at 30°C but not at 37°C, suggesting a significant involvement of this protein in the temperature-regulated expression of icsA. We also demonstrate that VirF directly stimulates icsA transcription and is able to alleviate H-NS repression in vitro. According to these results, icsA expression is derepressed in hns- background and overexpressed when VirF is provided in trans. Moreover, we find that RnaG-mediated transcription attenuation depends on 80 nt at its 5'-end, a stretch carrying the antisense region. Bases engaged in the initial contact leading to sense-antisense pairing have been identified using synthetic RNA and DNA oligonucleotides designed to rebuild and mutagenize the two stem-loop motifs of the antisense region.

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

PubMed Central

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

2017-01-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

PubMed

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

2017-08-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Design of high-speed burst mode clock and data recovery IC for passive optical network

NASA Astrophysics Data System (ADS)

Yan, Minhui; Hong, Xiaobin; Huang, Wei-Ping; Hong, Jin

2005-09-01

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for the saturation of frequency control voltage is therefore developed for the BMCDR, and the parameters of the circuit blocks can be readily adjusted and optimized based on the behavioural model. The newly designed BMCDR utilizes the 0.18um standard CMOS technology and is shown to be capable of operating at bit rate of 2.5Gbps, as well as the recovery time of one bit period in our simulation. The developed behaviour model is verified by comparing with the detailed circuit simulation.

Vortex spin-torque oscillator stabilized by phase locked loop using integrated circuits

NASA Astrophysics Data System (ADS)

Kreissig, Martin; Lebrun, R.; Protze, F.; Merazzo-Jaimes, K.; Hem, J.; Vila, L.; Ferreira, R.; Cyrille, M.-C.; Ellinger, F.; Cros, V.; Ebels, U.; Bortolotti, P.

2017-05-01

Spin-torque nano-oscillators (STO) are candidates for the next technological implementation of spintronic devices in commercial electronic systems. For use in microwave applications, improving the noise figures by efficient control of their phase dynamics is a mandatory requirement. In order to achieve this, we developed a compact phase locked loop (PLL) based on custom integrated circuits (ICs) and demonstrate that it represents an efficient way to reduce the phase noise level of a vortex based STO. The advantage of our approach to phase stabilize STOs is that our compact system is highly reconfigurable e.g. in terms of the frequency divider ratio N, RF gain and loop gain. This makes it robust against device to device variations and at the same time compatible with a large range of STOs. Moreover, by taking advantage of the natural highly non-isochronous nature of the STO, the STO frequency can be easily controlled by e.g. changing the divider ratio N.

Parallelism in integrated fluidic circuits

NASA Astrophysics Data System (ADS)

Bousse, Luc J.; Kopf-Sill, Anne R.; Parce, J. W.

1998-04-01

Many research groups around the world are working on integrated microfluidics. The goal of these projects is to automate and integrate the handling of liquid samples and reagents for measurement and assay procedures in chemistry and biology. Ultimately, it is hoped that this will lead to a revolution in chemical and biological procedures similar to that caused in electronics by the invention of the integrated circuit. The optimal size scale of channels for liquid flow is determined by basic constraints to be somewhere between 10 and 100 micrometers . In larger channels, mixing by diffusion takes too long; in smaller channels, the number of molecules present is so low it makes detection difficult. At Caliper, we are making fluidic systems in glass chips with channels in this size range, based on electroosmotic flow, and fluorescence detection. One application of this technology is rapid assays for drug screening, such as enzyme assays and binding assays. A further challenge in this area is to perform multiple functions on a chip in parallel, without a large increase in the number of inputs and outputs. A first step in this direction is a fluidic serial-to-parallel converter. Fluidic circuits will be shown with the ability to distribute an incoming serial sample stream to multiple parallel channels.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

PubMed

Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

2015-06-01

Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

Investigation for connecting waveguide in off-planar integrated circuits.

PubMed

Lin, Jie; Feng, Zhifang

2017-09-01

The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Nonlinear relaxation algorithms for circuit simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Saleh, R.A.

Circuit simulation is an important Computer-Aided Design (CAD) tool in the design of Integrated Circuits (IC). However, the standard techniques used in programs such as SPICE result in very long computer-run times when applied to large problems. In order to reduce the overall run time, a number of new approaches to circuit simulation were developed and are described. These methods are based on nonlinear relaxation techniques and exploit the relative inactivity of large circuits. Simple waveform-processing techniques are described to determine the maximum possible speed improvement that can be obtained by exploiting this property of large circuits. Three simulation algorithmsmore » are described, two of which are based on the Iterated Timing Analysis (ITA) method and a third based on the Waveform-Relaxation Newton (WRN) method. New programs that incorporate these techniques were developed and used to simulate a variety of industrial circuits. The results from these simulations are provided. The techniques are shown to be much faster than the standard approach. In addition, a number of parallel aspects of these algorithms are described, and a general space-time model of parallel-task scheduling is developed.« less

The Effects of Space Radiation on Linear Integrated Circuit

NASA Technical Reports Server (NTRS)

Johnston, A.

2000-01-01

Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

PubMed

Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

2008-02-01

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Multipurpose instrumentation cable provides integral thermocouple circuit

NASA Technical Reports Server (NTRS)

Zellner, G.

1967-01-01

Multipurpose cable with an integral thermocouple circuit measures strain, vibration, pressure, throughout a wide temperature range. This cable reduces bulky and complex circuitry by eliminating separate thermocouples for each transducer.

Optoelectronic Integrated Circuits For Neural Networks

NASA Technical Reports Server (NTRS)

Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

1990-01-01

Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

Nanoscale x-ray imaging of circuit features without wafer etching

NASA Astrophysics Data System (ADS)

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

Nanoscale x-ray imaging of circuit features without wafer etching.

PubMed

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

Nanoscale x-ray imaging of circuit features without wafer etching

DOE PAGES

Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

2017-03-24

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

PubMed

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

PubMed

Shen, Wen-Wei; Chen, Kuan-Neng

2017-12-01

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Micromachined Integrated Quantum Circuit Containing a Superconducting Qubit

NASA Astrophysics Data System (ADS)

Brecht, T.; Chu, Y.; Axline, C.; Pfaff, W.; Blumoff, J. Z.; Chou, K.; Krayzman, L.; Frunzio, L.; Schoelkopf, R. J.

2017-04-01

We present a device demonstrating a lithographically patterned transmon integrated with a micromachined cavity resonator. Our two-cavity, one-qubit device is a multilayer microwave-integrated quantum circuit (MMIQC), comprising a basic unit capable of performing circuit-QED operations. We describe the qubit-cavity coupling mechanism of a specialized geometry using an electric-field picture and a circuit model, and obtain specific system parameters using simulations. Fabrication of the MMIQC includes lithography, etching, and metallic bonding of silicon wafers. Superconducting wafer bonding is a critical capability that is demonstrated by a micromachined storage-cavity lifetime of 34.3 μ s , corresponding to a quality factor of 2 ×106 at single-photon energies. The transmon coherence times are T1=6.4 μ s , and T2echo=11.7 μ s . We measure qubit-cavity dispersive coupling with a rate χq μ/2 π =-1.17 MHz , constituting a Jaynes-Cummings system with an interaction strength g /2 π =49 MHz . With these parameters we are able to demonstrate circuit-QED operations in the strong dispersive regime with ease. Finally, we highlight several improvements and anticipated extensions of the technology to complex MMIQCs.

Organic printed photonics: From microring lasers to integrated circuits

PubMed Central

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-01-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

Organic printed photonics: From microring lasers to integrated circuits.

PubMed

Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

2015-09-01

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Multislice imaging of integrated circuits by precession X-ray ptychography.

PubMed

Shimomura, Kei; Hirose, Makoto; Takahashi, Yukio

2018-01-01

A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wide Q range and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

RF to millimeter wave integration and module technologies

NASA Astrophysics Data System (ADS)

Vähä-Heikkilä, T.

2015-04-01

Radio Frequency (RF) consumer applications have boosted silicon integrated circuits (IC) and corresponding technologies. More and more functions are integrated to ICs and their performance is also increasing. However, RF front-end modules with filters and switches as well as antennas still need other way of integration. This paper focuses to RF front-end module and antenna developments as well as to the integration of millimeter wave radios. VTT Technical Research Centre of Finland has developed both Low Temperature Co-fired Ceramics (LTCC) and Integrated Passive Devices (IPD) integration platforms for RF and millimeter wave integrated modules. In addition to in-house technologies, VTT is using module and component technologies from other commercial sources.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

Image Noise, CNR, and Detectability of Low-Contrast, Low-Attenuation Liver Lesions in a Phantom: Effects of Radiation Exposure, Phantom Size, Integrated Circuit Detector, and Iterative Reconstruction.

PubMed

Goenka, Ajit H; Herts, Brian R; Dong, Frank; Obuchowski, Nancy A; Primak, Andrew N; Karim, Wadih; Baker, Mark E

2016-08-01

Purpose To assess image noise, contrast-to-noise ratio (CNR) and detectability of low-contrast, low-attenuation liver lesions in a semianthropomorphic phantom by using either a discrete circuit (DC) detector and filtered back projection (FBP) or an integrated circuit (IC) detector and iterative reconstruction (IR) with changes in radiation exposure and phantom size. Materials and Methods An anthropomorphic phantom without or with a 5-cm-thick fat-mimicking ring (widths, 30 and 40 cm) containing liver inserts with four spherical lesions was scanned with five exposure settings on each of two computed tomography scanners, one equipped with a DC detector and the other with an IC detector. Images from the DC and IC detector scanners were reconstructed with FBP and IR, respectively. Image noise and lesion CNR were measured. Four radiologists evaluated lesion presence on a five-point diagnostic confidence scale. Data analyses included receiver operating characteristic (ROC) curve analysis and noninferiority analysis. Results The combination of IC and IR significantly reduced image noise (P < .001) (with the greatest reduction in the 40-cm phantom and at lower exposures) and improved lesion CNR (P < .001). There was no significant difference in area under the ROC curve between detector-reconstruction combinations at fixed exposure for either phantom. Reader accuracy with IC-IR was noninferior at 50% (100 mAs [effective]) and 25% (300 mAs [effective]) exposure reduction for the 30- and 40-cm phantoms, respectively (adjusted P < .001 and .04 respectively). IC-IR improved readers' confidence in the presence of a lesion (P = .029) independent of phantom size or exposure level. Conclusion IC-IR improved objective image quality and lesion detection confidence but did not result in superior diagnostic accuracy when compared with DC-FBP. Moderate exposure reductions maintained comparable diagnostic accuracy for both detector-reconstruction combinations. Lesion detection in the 40

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

System-level integrated circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Applying analog integrated circuits for HERO protection

NASA Technical Reports Server (NTRS)

Willis, Kenneth E.; Blachowski, Thomas J.

1994-01-01

One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

Magnet-wire wrapping tool for integrated circuits

NASA Technical Reports Server (NTRS)

Takahashi, T. H.

1972-01-01

Wire-dispensing tool which resembles mechanical pencil is used to wrap magnet wire around integrated circuit terminals uniformly and securely without damaging insulative coating on wire. Tool is hand-held and easily manipulated to execute wire wrapping movements.

Creating a FIESTA (Framework for Integrated Earth Science and Technology Applications) with MagIC

NASA Astrophysics Data System (ADS)

Minnett, R.; Koppers, A. A. P.; Jarboe, N.; Tauxe, L.; Constable, C.

2017-12-01

The Magnetics Information Consortium (https://earthref.org/MagIC) has recently developed a containerized web application to considerably reduce the friction in contributing, exploring and combining valuable and complex datasets for the paleo-, geo- and rock magnetic scientific community. The data produced in this scientific domain are inherently hierarchical and the communities evolving approaches to this scientific workflow, from sampling to taking measurements to multiple levels of interpretations, require a large and flexible data model to adequately annotate the results and ensure reproducibility. Historically, contributing such detail in a consistent format has been prohibitively time consuming and often resulted in only publishing the highly derived interpretations. The new open-source (https://github.com/earthref/MagIC) application provides a flexible upload tool integrated with the data model to easily create a validated contribution and a powerful search interface for discovering datasets and combining them to enable transformative science. MagIC is hosted at EarthRef.org along with several interdisciplinary geoscience databases. A FIESTA (Framework for Integrated Earth Science and Technology Applications) is being created by generalizing MagIC's web application for reuse in other domains. The application relies on a single configuration document that describes the routing, data model, component settings and external services integrations. The container hosts an isomorphic Meteor JavaScript application, MongoDB database and ElasticSearch search engine. Multiple containers can be configured as microservices to serve portions of the application or rely on externally hosted MongoDB, ElasticSearch, or third-party services to efficiently scale computational demands. FIESTA is particularly well suited for many Earth Science disciplines with its flexible data model, mapping, account management, upload tool to private workspaces, reference metadata, image

Integrated biocircuits: engineering functional multicellular circuits and devices.

PubMed

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

35 GHz integrated circuit rectifying antenna with 33 percent efficiency

NASA Technical Reports Server (NTRS)

Yoo, T.-W.; Chang, K.

1991-01-01

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

Integrated circuit layer image segmentation

NASA Astrophysics Data System (ADS)

Masalskis, Giedrius; Petrauskas, Romas

2010-09-01

In this paper we present IC layer image segmentation techniques which are specifically created for precise metal layer feature extraction. During our research we used many samples of real-life de-processed IC metal layer images which were obtained using optical light microscope. We have created sequence of various image processing filters which provides segmentation results of good enough precision for our application. Filter sequences were fine tuned to provide best possible results depending on properties of IC manufacturing process and imaging technology. Proposed IC image segmentation filter sequences were experimentally tested and compared with conventional direct segmentation algorithms.

Bioluminescent bioreporter integrated circuit detection methods

DOEpatents

Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

2005-06-14

Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

Half-dose non-contrast CT in the investigation of urolithiasis: image quality improvement with third-generation integrated circuit CT detectors.

PubMed

Wang, Jun; Kang, Tony; Arepalli, Chesnal; Barrett, Sarah; O'Connell, Tim; Louis, Luck; Nicolaou, Savvakis; McLaughlin, Patrick

2015-06-01

The objective of this study is to establish the effect of third-generation integrated circuit (IC) CT detector on objective image quality in full- and half-dose non-contrast CT of the urinary tract. 51 consecutive patients with acute renal colic underwent non-contrast CT of the urinary tract using a 128-slice dual-source CT before (n = 24) and after (n = 27) the installation of third-generation IC detectors. Half-dose images were generated using projections from detector A using the dual-source RAW data. Objective image noise in the liver, spleen, right renal cortex, and right psoas muscle was compared between DC and IC cohorts for full-dose and half-dose images reconstructed with FBP and IR algorithms using 1 cm(2) regions of interest. Presence and size of obstructing ureteric calculi were also compared for full-dose and half-dose reconstructions using DC and IC detectors. No statistical difference in age and lateral body size was found between patients in the IC and DC cohorts. Radiation dose, as measured by size-specific dose estimates, did not differ significantly either between the two cohorts (10.02 ± 4.54 mGy IC vs. 12.28 ± 7.03 mGy DC). At full dose, objective image noise was not significantly lower in the IC cohort as compared to the DC cohort for the liver, spleen, and right psoas muscle. At half dose, objective image noise was lower in the IC cohort as compared to DC cohort at the liver (21.32 IC vs. 24.99 DC, 14.7% decrease, p < 0.001), spleen (19.33 IC vs. 20.83 DC, 7.20% decrease, p = 0.02), and right renal cortex (20.28 IC vs. 22.98 DC, 11.7% decrease, p = 0.005). Mean obstructing ureteric calculi size was not significantly different when comparison was made between full-dose and half-dose images, regardless of detector type (p > 0.05 for all comparisons). Third-generation IC detectors result in lower objective image noise at full- and half-radiation dose levels as compared with traditional DC detectors. The magnitude of noise reduction was greater

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

NASA Technical Reports Server (NTRS)

Johnston, Allan H.; Rax, Bernard G.

2006-01-01

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Integrating anatomy and function for zebrafish circuit analysis.

PubMed

Arrenberg, Aristides B; Driever, Wolfgang

2013-01-01

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

Integrated circuit cell library

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

2005-01-01

According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

Quality control and authentication of packaged integrated circuits using enhanced-spatial-resolution terahertz time-domain spectroscopy and imaging

NASA Astrophysics Data System (ADS)

Ahi, Kiarash; Shahbazmohamadi, Sina; Asadizanjani, Navid

2018-05-01

In this paper, a comprehensive set of techniques for quality control and authentication of packaged integrated circuits (IC) using terahertz (THz) time-domain spectroscopy (TDS) is developed. By material characterization, the presence of unexpected materials in counterfeit components is revealed. Blacktopping layers are detected using THz time-of-flight tomography, and thickness of hidden layers is measured. Sanded and contaminated components are detected by THz reflection-mode imaging. Differences between inside structures of counterfeit and authentic components are revealed through developing THz transmission imaging. For enabling accurate measurement of features by THz transmission imaging, a novel resolution enhancement technique (RET) has been developed. This RET is based on deconvolution of the THz image and the THz point spread function (PSF). The THz PSF is mathematically modeled through incorporating the spectrum of the THz imaging system, the axis of propagation of the beam, and the intensity extinction coefficient of the object into a Gaussian beam distribution. As a result of implementing this RET, the accuracy of the measurements on THz images has been improved from 2.4 mm to 0.1 mm and bond wires as small as 550 μm inside the packaging of the ICs are imaged.

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Integrated Circuits in the Introductory Electronics Laboratory

ERIC Educational Resources Information Center

English, Thomas C.; Lind, David A.

1973-01-01

Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

PubMed

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

Chemical etching for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1981-01-01

Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

Integrated biocircuits: engineering functional multicellular circuits and devices

NASA Astrophysics Data System (ADS)

Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

2018-04-01

Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

Self-contained sub-millimeter wave rectifying antenna integrated circuit

NASA Technical Reports Server (NTRS)

Siegel, Peter H. (Inventor)

2004-01-01

The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

PubMed

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

1984-01-01

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Monolithic microwave integrated circuits: Interconnections and packaging considerations

NASA Astrophysics Data System (ADS)

Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

Foundry fabricated photonic integrated circuit optical phase lock loop.

PubMed

Bałakier, Katarzyna; Fice, Martyn J; Ponnampalam, Lalitha; Graham, Chris S; Wonfor, Adrian; Seeds, Alwyn J; Renaud, Cyril C

2017-07-24

This paper describes the first foundry-based InP photonic integrated circuit (PIC) designed to work within a heterodyne optical phase locked loop (OPLL). The PIC and an external electronic circuit were used to phase-lock a single-line semiconductor laser diode to an incoming reference laser, with tuneable frequency offset from 4 GHz to 12 GHz. The PIC contains 33 active and passive components monolithically integrated on a single chip, fully demonstrating the capability of a generic foundry PIC fabrication model. The electronic part of the OPLL consists of commercially available RF components. This semi-packaged system stabilizes the phase and frequency of the integrated laser so that an absolute frequency, high-purity heterodyne signal can be generated when the OPLL is in operation, with phase noise lower than -100 dBc/Hz at 10 kHz offset from the carrier. This is the lowest phase noise level ever demonstrated by monolithically integrated OPLLs.

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

NASA Technical Reports Server (NTRS)

D'Addario, Larry R.; Wang, Douglas

2016-01-01

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it

Quantum dot rolled-up microtube optoelectronic integrated circuit.

PubMed

Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

2013-05-15

A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively.

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, Edward H.; Tuckerman, David B.

1991-01-01

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, James H.; Lavietes, Anthony D.

1998-05-29

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radio nuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components.

Ambient temperature cadmium zinc telluride radiation detector and amplifier circuit

DOEpatents

McQuaid, J.H.; Lavietes, A.D.

1998-05-26

A low noise, low power consumption, compact, ambient temperature signal amplifier for a Cadmium Zinc Telluride (CZT) radiation detector is disclosed. The amplifier can be used within a larger system (e.g., including a multi-channel analyzer) to allow isotopic analysis of radionuclides in the field. In one embodiment, the circuit stages of the low power, low noise amplifier are constructed using integrated circuit (IC) amplifiers , rather than discrete components, and include a very low noise, high gain, high bandwidth dual part preamplification stage, an amplification stage, and an filter stage. The low noise, low power consumption, compact, ambient temperature amplifier enables the CZT detector to achieve both the efficiency required to determine the presence of radionuclides and the resolution necessary to perform isotopic analysis to perform nuclear material identification. The present low noise, low power, compact, ambient temperature amplifier enables a CZT detector to achieve resolution of less than 3% full width at half maximum at 122 keV for a Cobalt-57 isotope source. By using IC circuits and using only a single 12 volt supply and ground, the novel amplifier provides significant power savings and is well suited for prolonged portable in-field use and does not require heavy, bulky power supply components. 9 figs.

Viewing Integrated-Circuit Interconnections By SEM

NASA Technical Reports Server (NTRS)

Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

1990-01-01

Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

PubMed Central

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

SiGe Integrated Circuit Developments for SQUID/TES Readout

NASA Astrophysics Data System (ADS)

Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

2018-03-01

SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits.

PubMed

Khuri-Yakub, B T; Oralkan, Omer; Nikoozadeh, Amin; Wygant, Ira O; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O'Donnell, Matthew; Truong, Uyen; Sahn, David J

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics.

Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

PubMed Central

Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Technical Reports Server (NTRS)

Pavlidis, Dimitris

1991-01-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Astrophysics Data System (ADS)

Pavlidis, Dimitris

1991-02-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-08

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

PubMed

Shulaker, Max Marcel; Van Rethy, Jelle; Wu, Tony F; Liyanage, Luckshitha Suriyasena; Wei, Hai; Li, Zuanyi; Pop, Eric; Gielen, Georges; Wong, H-S Philip; Mitra, Subhasish

2014-04-22

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit.

PubMed

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-21

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10 -9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

NASA Astrophysics Data System (ADS)

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-12-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10-9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

A low-power RFID integrated circuits for intelligent healthcare systems.

PubMed

Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

2010-11-01

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

1990 MTT-S International Microwave Symposium and Exhibition and Microwave and Millimeter-Wave Monolithic IC Symposium, Dallas, TX, May 7-10, 1990, Proceedings

NASA Astrophysics Data System (ADS)

McQuiddy, David N., Jr.; Sokolov, Vladimir

1990-12-01

The present conference discusses microwave filters, lightwave technology for microwave antennas, planar and quasi-planar guides, mixers and VCOs, cavity filters, discontinuity and coupling effects, control circuits, power dividers and phase shifters, microwave ICs, biological effects and medical applications, CAD and modeling for MMICs, directional couplers, MMIC design trends, microwave packaging and manufacturing, monolithic ICs, and solid-state devices and circuits. Also discussed are microwave and mm-wave superconducting technology, MICs for communication systems, the merging of optical and microwave technologies, microwave power transistors, ferrite devices, network measurements, advanced transmission-line structures, FET devices and circuits, field theory of IC discontinuities, active quasi-optical techniques, phased-array techniques and circuits, nonlinear CAD, sub-mm wave devices, and high power devices.

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

NASA Astrophysics Data System (ADS)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

High-voltage integrated active quenching circuit for single photon count rate up to 80 Mcounts/s.

PubMed

Acconcia, Giulia; Rech, Ivan; Gulinatti, Angelo; Ghioni, Massimo

2016-08-08

Single photon avalanche diodes (SPADs) have been subject to a fast improvement in recent years. In particular, custom technologies specifically developed to fabricate SPAD devices give the designer the freedom to pursue the best detector performance required by applications. A significant breakthrough in this field is represented by the recent introduction of a red enhanced SPAD (RE-SPAD) technology, capable of attaining a good photon detection efficiency in the near infrared range (e.g. 40% at a wavelength of 800 nm) while maintaining a remarkable timing resolution of about 100ps full width at half maximum. Being planar, the RE-SPAD custom technology opened the way to the development of SPAD arrays particularly suited for demanding applications in the field of life sciences. However, to achieve such excellent performance custom SPAD detectors must be operated with an external active quenching circuit (AQC) designed on purpose. Next steps toward the development of compact and practical multichannel systems will require a new generation of monolithically integrated AQC arrays. In this paper we present a new, fully integrated AQC fabricated in a high-voltage 0.18 µm CMOS technology able to provide quenching pulses up to 50 Volts with fast leading and trailing edges. Although specifically designed for optimal operation of RE-SPAD devices, the new AQC is quite versatile: it can be used with any SPAD detector, regardless its fabrication technology, reaching remarkable count rates up to 80 Mcounts/s and generating a photon detection pulse with a timing jitter as low as 119 ps full width at half maximum. The compact design of our circuit has been specifically laid out to make this IC a suitable building block for monolithically integrated AQC arrays.

Analysis of a Statistical Relationship Between Dose and Error Tallies in Semiconductor Digital Integrated Circuits for Application to Radiation Monitoring Over a Wireless Sensor Network

NASA Astrophysics Data System (ADS)

Colins, Karen; Li, Liqian; Liu, Yu

2017-05-01

Mass production of widely used semiconductor digital integrated circuits (ICs) has lowered unit costs to the level of ordinary daily consumables of a few dollars. It is therefore reasonable to contemplate the idea of an engineered system that consumes unshielded low-cost ICs for the purpose of measuring gamma radiation dose. Underlying the idea is the premise of a measurable correlation between an observable property of ICs and radiation dose. Accumulation of radiation-damage-induced state changes or error events is such a property. If correct, the premise could make possible low-cost wide-area radiation dose measurement systems, instantiated as wireless sensor networks (WSNs) with unshielded consumable ICs as nodes, communicating error events to a remote base station. The premise has been investigated quantitatively for the first time in laboratory experiments and related analyses performed at the Canadian Nuclear Laboratories. State changes or error events were recorded in real time during irradiation of samples of ICs of different types in a 60Co gamma cell. From the error-event sequences, empirical distribution functions of dose were generated. The distribution functions were inverted and probabilities scaled by total error events, to yield plots of the relationship between dose and error tallies. Positive correlation was observed, and discrete functional dependence of dose quantiles on error tallies was measured, demonstrating the correctness of the premise. The idea of an engineered system that consumes unshielded low-cost ICs in a WSN, for the purpose of measuring gamma radiation dose over wide areas, is therefore tenable.

Gigahertz flexible graphene transistors for microwave integrated circuits.

PubMed

Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

2014-08-26

Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

Tunable electromagnetically induced transparency in integrated silicon photonics circuit.

PubMed

Li, Ang; Bogaerts, Wim

2017-12-11

We comprehensively simulate and experimentally demonstrate a novel approach to generate tunable electromagnetically induced transparency (EIT) in a fully integrated silicon photonics circuit. It can also generate tunable fast and slow light. The circuit is a single ring resonator with two integrated tunable reflectors inside, which form an embedded Fabry-Perot (FP) cavity inside the ring cavity. The mode of the FP cavity can be controlled by tuning the reflections using integrated thermo-optic tuners. Under correct tuning conditions, the interaction of the FP mode and the ring resonance mode will generate a Fano resonance and an EIT response. The extinction ratio and bandwidth of the EIT can be tuned by controlling the reflectors. Measured group delay proves that both fast light and slow light can be generated under different tuning conditions. A maximum group delay of 1100 ps is observed because of EIT. Pulse advance around 1200 ps is also demonstrated.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, David R.

1989-01-01

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, D.R.

1989-09-12

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Abbaspour, R.; Brown, D. K.; Bakir, M. S.

2017-02-01

This paper presents the fabrication and electrical characterization of high aspect-ratio (AR) sub-micron diameter through silicon vias (TSVs) for densely interconnected three-dimensional (3D) stacked integrated circuits (ICs). The fabricated TSV technology features an AR of 16:1 with 680 nm diameter copper (Cu) core and 920 nm overall diameter. To address the challenges in scaling TSVs, scallop-free low roughness nano-Bosch silicon etching and direct Cu electroplating on a titanium-nitride (TiN) diffusion barrier layer have been developed as key enabling modules. The electrical resistance of the sub-micron TSVs is measured to be on average 1.2 Ω, and the Cu resistivity is extracted to be approximately 2.95 µΩ cm. Furthermore, the maximum achievable current-carrying capacity (CCC) of the scaled TSVs is characterized to be approximately 360 µA for the 680 nm Cu core.

Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

PubMed Central

Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

2016-01-01

Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than −30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10−9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers. PMID:28000735

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Advances in integrated photonic circuits for packet-switched interconnection

NASA Astrophysics Data System (ADS)

Williams, Kevin A.; Stabile, Ripalta

2014-03-01

Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lashin, A. V., E-mail: LashinAV@lhp.ru; Kozyrev, A. V.

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

NASA Astrophysics Data System (ADS)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on

Non-Contact Circuit for Real-Time Electric and Magnetic Field Measurements

DTIC Science & Technology

2015-10-01

addresses these needs, and additionally has “smart” features that adjust integrated circuits ( ICs ) on the sensor during start-up based upon the...Hall effect sensors, the datasheet information on the MLX91205 gives a dynamic range of 66 to 96 dB for frequencies of 10 Hz and 10 kHz, respectively...Electric Field Sensors. 18 August 2009. 4. Melexis. IMC-Hall Current Sensor, MLX91205 Datasheet . June. 2012 5. Vinci SJ, Hull DM. Electrostatic

On-chip enzymatic microbiofuel cell-powered integrated circuits.

PubMed

Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

2017-05-16

A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

Capable Copper Electrodeposition Process for Integrated Circuit - substrate Packaging Manufacturing

NASA Astrophysics Data System (ADS)

Ghanbari, Nasrin

This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20microm to 100microm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20microm - 200microm, fine traces with varying widths of 3microm - 30microm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead

Flexible circuits with integrated switches for robotic shape sensing

NASA Astrophysics Data System (ADS)

Harnett, C. K.

2016-05-01

Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

Photonic integrated circuits based on silica and polymer PLC

NASA Astrophysics Data System (ADS)

Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

2013-03-01

Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

Integrated readout electronics for Belle II pixel detector

NASA Astrophysics Data System (ADS)

Blanco, R.; Leys, R.; Perić, I.

2018-03-01

This paper describes the readout components for Belle II that have been designed as integrated circuits. The ICs are connected to DEPFET sensor by bump bonding. Three types of ICs have been developed: SWITCHER for pixel matrix control, DCD for readout and digitizing of sensor signals and DHP for digital data processing. The ICs are radiation tolerant and use several novel features, such as the multiple-input differential amplifiers and the fast and radiation hard high-voltage drivers. SWITCHER and DCD have been developed at University of Heidelberg, Karlsruhe Institute of Technology (KIT) and DHP at Bonn University. The IC-development started in 2009 and was accomplished in 2016 with the submissions of final designs. The final ICs for Belle II pixel detector and the related measurement results will be presented in this contribution.

Printed stretchable circuit on soft elastic substrate for wearable application

NASA Astrophysics Data System (ADS)

Yuan, Wei; Wu, Xinzhou; Gu, Weibing; Lin, Jian; Cui, Zheng

2018-01-01

In this paper, a flexible and stretchable circuit has been fabricated by the printing method based on Ag NWs/PDMS composite. The randomly oriented Ag NWs were buried in PDMS to form a conductive and stretchable electrode. Stable conductivity was achieved with a large range of tensile strain (0-50%) after the initial stretching/releasing cycle. The stable electrical response is due to the buckling of the Ag NWs/PDMS composite layer. Furthermore, printed stretchable circuits integrated with commercial ICs have been demonstrated for wearable applications. Project supported by the National Program on Key Basic Research Project (No. 2015CB351901), the Strategic Priority Research Program of the Chinese Academy of Sciences (No. XDA09020201), and the National Science Foundation of China (Nos. 51603227, 51603228).

Generation of optical vortices in an integrated optical circuit

NASA Astrophysics Data System (ADS)

Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

2017-09-01

In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

Diffused Silicon Transistors and Switches (1954-55): The Beginning of Integrated Circuit Technology

NASA Astrophysics Data System (ADS)

Holonyak, N.

2003-09-01

Silicon (Si) transistor and integrated circuit (IC) technology has grown so big, and become so important, that it is now hard to recognize where, apart from the invention of the transistor itself (Bardeen and Brattain, Dec 16, 1947), it had its origin. In spite of obvious differences in Ge and Si, in 1950-55 it was not evident in many laboratories, concentrating only on Ge, what form of Ge transistor (grown, alloyed, jet-etched, etc.) might be expected to prevail, with Si not even being considered (or being dismissed outright). What was the need for Si and, at the time, such a seemingly intractable peculiar new technology? The requirement on switching devices of low leakage, and thus the need to leave Ge in favor of Si, led directly in 1954-55 (Bell Telephone Laboratories, BTL) to the exploration of impurity-diffusion and metallization technology to realize Si transistors and p-n-p-n switches. This technology, a more or less ideal thin-layer technology that can be referenced from a single surface (and which indeed has proven to be basically invariant and constantly growing), led further to the discovery (1955) of the protective Si oxide, oxide masking and patterning, and the fundamental basis of the integrated circuit (i.e., device-to-device interconnection by patterned metallization across the oxide). We recount some of the exploratory diffused-impurity Si device development of 1954-55 at BTL, particularly the work in and near Moll's group, that helped to establish the basis for today's electronics. The Si diffused-impurity devices of 1954-55 are described, including work and data not previously reported or broadly known—in fact, much work and data (a new technology) that was carried across the Country to a place that became known as Silicon Valley. For further perspective, an appendix is included of independent early suggestions of Bardeen (Urbana notebook, Feb 1952) to leave Ge in favor of diffused Si devices.

Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

PubMed

Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

2016-06-22

We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals.

A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

NASA Astrophysics Data System (ADS)

Bezuidenhout, P.; Land, K.; Joubert, T.-H.

2016-02-01

Electrochemical biosensing is used to detect specific analytes in fluids, such as bacterial and chemical contaminants. A common implementation of an electrochemical readout is a potentiostat, which usually includes potentiometric, amperometric, and impedimetric detection. Recently several researchers have developed small, low-cost, single-chip silicon-based potentiostats. With the advances in heterogeneous integration technology, low-power potentiostats can be implemented on paper and similar low cost substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated by an electrochemical redox reaction in the system is measured. In order to measure low current values, the noise of the circuit must be minimized, which is accomplished with a pre-amplification front-end stage, typically designed around an operational amplifier core. An appropriate circuit design for a low-power and low-cost amperometric front-end is identified, taking the heterogeneous integration of various components into account. The operational amplifier core is on a bare custom CMOS chip, which will be integrated onto the paper substrate alongside commercial off-the-shelf electronic components. A general-purpose low-power two-stage CMOS amplifier circuit is designed and simulated for the ams 350 nm 5 V process. After the layout design and verification, the IC was submitted for a multi-project wafer manufacturing run. The simulated results are a bandwidth of 2.4 MHz, a common-mode rejection ratio of 70.04 dB, and power dissipation of 0.154 mW, which are comparable with the analytical values.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, D.R.

1988-04-20

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Information Commons for Rice (IC4R)

PubMed Central

2016-01-01

Rice is the most important staple food for a large part of the world's human population and also a key model organism for plant research. Here, we present Information Commons for Rice (IC4R; http://ic4r.org), a rice knowledgebase featuring adoption of an extensible and sustainable architecture that integrates multiple omics data through community-contributed modules. Each module is developed and maintained by different committed groups, deals with data collection, processing and visualization, and delivers data on-demand via web services. In the current version, IC4R incorporates a variety of rice data through multiple committed modules, including genome-wide expression profiles derived entirely from RNA-Seq data, resequencing-based genomic variations obtained from re-sequencing data of thousands of rice varieties, plant homologous genes covering multiple diverse plant species, post-translational modifications, rice-related literatures and gene annotations contributed by the rice research community. Unlike extant related databases, IC4R is designed for scalability and sustainability and thus also features collaborative integration of rice data and low costs for database update and maintenance. Future directions of IC4R include incorporation of other omics data and association of multiple omics data with agronomically important traits, dedicating to build IC4R into a valuable knowledgebase for both basic and translational researches in rice. PMID:26519466

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

PubMed

Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

2017-02-01

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

NASA Astrophysics Data System (ADS)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

In situ fabricated 3D micro-lenses for photonic integrated circuits.

PubMed

Thomas, R; Li, J; Ladak, Sam; Barrow, D; Smowton, P M

2018-05-14

Aspheric astigmatic polymer micro-lenses were fabricated directly onto photonic integrated circuits using two-photon lithography. We observed a 12.6 dB improvement in the free space coupling efficiency between integrated ridge laser pairs with micro-lenses to those without.

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-29

... INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and... Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on... Commission's electronic docket (EDIS) at http://edis.usitc.gov , and will be available for inspection during...

77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Docket No. 2899] Certain Integrated Circuit Packages Provided With... complaint entitled Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and..., telephone (202) 205-2000. The public version of the complaint can be accessed on the Commission's electronic...

IC-tagged proteins are able to interact with each other and perform complex reactions when integrated into muNS-derived inclusions.

PubMed

Brandariz-Nuñez, Alberto; Otero-Romero, Iria; Benavente, Javier; Martinez-Costas, Jose M

2011-09-20

We have recently developed a versatile tagging system (IC-tagging) that causes relocation of the tagged proteins to ARV muNS-derived intracellular globular inclusions. In the present study we demonstrate (i) that the IC-tag can be successfully fused either to the amino or carboxyl terminus of the protein to be tagged and (ii) that IC-tagged proteins are able to interact between them and perform complex reactions that require such interactions while integrated into muNS inclusions, increasing the versatility of the IC-tagging system. Also, our studies with the DsRed protein add some light on the structure/function relationship of the evolution of DsRed chromophore. Copyright © 2011 Elsevier B.V. All rights reserved.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Design automation for integrated nonlinear logic circuits (Conference Presentation)

NASA Astrophysics Data System (ADS)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

The use of light emission in failure analysis of CMOS ICs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hawkins, C.F.; Soden, J.M.; Cole, E.I. Jr.

1990-01-01

The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

Organic membrane photonic integrated circuits (OMPICs).

PubMed

Amemiya, Tomohiro; Kanazawa, Toru; Hiratani, Takuo; Inoue, Daisuke; Gu, Zhichen; Yamasaki, Satoshi; Urakami, Tatsuhiro; Arai, Shigehisa

2017-08-07

We propose the concept of organic membrane photonic integrated circuits (OMPICs), which incorporate various functions needed for optical signal processing into a flexible organic membrane. We describe the structure of several devices used within the proposed OMPICs (e.g., transmission lines, I/O couplers, phase shifters, photodetectors, modulators), and theoretically investigate their characteristics. We then present a method of fabricating the photonic devices monolithically in an organic membrane and demonstrate the operation of transmission lines and I/O couplers, the most basic elements of OMPICs.

An integrated circuit floating point accumulator

NASA Technical Reports Server (NTRS)

Goldsmith, T. C.

1977-01-01

Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

Digital correlator with fewer IC's

NASA Technical Reports Server (NTRS)

Apple, G. G.; Rubin, L.

1979-01-01

Digital correlator requires only few integrated circuits to determine synchronization of two 24-bit digital words. Circuit is easily reduced or expanded to accommodate shorter or longer words and can be utilized in industrial and commercial data processing and telecommunications.

Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

NASA Technical Reports Server (NTRS)

Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

1981-01-01

Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

Chemical vapor deposition for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1980-01-01

Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

Design and status of the RF-digitizer integrated circuit

NASA Technical Reports Server (NTRS)

Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

1991-01-01

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

NASA Astrophysics Data System (ADS)

O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

2016-02-01

CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

A novel readout integrated circuit for ferroelectric FPA detector

NASA Astrophysics Data System (ADS)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

Testing Fixture For Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Romanofsky, Robert; Shalkhauser, Kurt

1989-01-01

Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

Spatial gradients and multidimensional dynamics in a neural integrator circuit

PubMed Central

Miri, Andrew; Daie, Kayvon; Arrenberg, Aristides B.; Baier, Herwig; Aksay, Emre; Tank, David W.

2011-01-01

In a neural integrator, the variability and topographical organization of neuronal firing rate persistence can provide information about the circuit’s functional architecture. Here we use optical recording to measure the time constant of decay of persistent firing (“persistence time”) across a population of neurons comprising the larval zebrafish oculomotor velocity-to-position neural integrator. We find extensive persistence time variation (10-fold; coefficients of variation 0.58–1.20) across cells within individual larvae. We also find that the similarity in firing between two neurons decreased as the distance between them increased and that a gradient in persistence time was mapped along the rostrocaudal and dorsoventral axes. This topography is consistent with the emergence of persistence time heterogeneity from a circuit architecture in which nearby neurons are more strongly interconnected than distant ones. Collectively, our results can be accounted for by integrator circuit models characterized by multiple dimensions of slow firing rate dynamics. PMID:21857656

Universal discrete Fourier optics RF photonic integrated circuit architecture.

PubMed

Hall, Trevor J; Hasan, Mehedi

2016-04-04

This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO_3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

A clocking discipline for two-phase digital integrated circuits

NASA Astrophysics Data System (ADS)

Noice, D. C.

1983-09-01

Sooner or later a designer of digital circuits must face the problem of timing verification so he can avoid errors caused by clock skew, critical races, and hazards. Unlike previous verification methods, such as timing simulation and timing analysis, the approach presented here guarantees correct operation despite uncertainty about delays in the circuit. The result is a clocking discipline that deals with timing abstractions only. It is not based on delay calculations; it is only concerned with the correct, synchronous operation at some clock rate. Accordingly, it may be used earlier in the design cycle, which is particularly important to integrated circuit designs. The clocking discipline consists of a notation of clocking types, and composition rules for using the types. Together, the notation and rules define a formal theory of two phase clocking. The notation defines the names and exact characteristics for different signals that are used in a two phase digital system. The notation makes it possible to develop rules for propagating the clocking types through particular circuits.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Mems: Platform for Large-Scale Integrated Vacuum Electronic Circuits

DTIC Science & Technology

2017-03-20

SECURITY CLASSIFICATION OF: The objective of the LIVEC advanced study project was to develop a platform for large-scale integrated vacuum electronic ...Distribution Unlimited UU UU UU UU 20-03-2017 1-Jul-2014 30-Jun-2015 Final Report: MEMS Platform for Large-Scale Integrated Vacuum Electronic ... Electronic Circuits (LIVEC) Contract No: W911NF-14-C-0093 COR Dr. James Harvey U.S. ARO RTP, NC 27709-2211 Phone: 702-696-2533 e-mail

A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

NASA Astrophysics Data System (ADS)

Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

2014-06-01

This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

DTIC Science & Technology

1993-02-10

new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

Quantum dash based single section mode locked lasers for photonic integrated circuits.

PubMed

Joshi, Siddharth; Calò, Cosimo; Chimot, Nicolas; Radziunas, Mindaugas; Arkhipov, Rostislav; Barbet, Sophie; Accard, Alain; Ramdane, Abderrahim; Lelarge, Francois

2014-05-05

We present the first demonstration of an InAs/InP Quantum Dash based single-section frequency comb generator designed for use in photonic integrated circuits (PICs). The laser cavity is closed using a specifically designed Bragg reflector without compromising the mode-locking performance of the self pulsating laser. This enables the integration of single-section mode-locked laser in photonic integrated circuits as on-chip frequency comb generators. We also investigate the relations between cavity modes in such a device and demonstrate how the dispersion of the complex mode frequencies induced by the Bragg grating implies a violation of the equi-distance between the adjacent mode frequencies and, therefore, forbids the locking of the modes in a classical Bragg Device. Finally we integrate such a Bragg Mirror based laser with Semiconductor Optical Amplifier (SOA) to demonstrate the monolithic integration of QDash based low phase noise sources in PICs.

FAST: a framework for simulation and analysis of large-scale protein-silicon biosensor circuits.

PubMed

Gu, Ming; Chakrabartty, Shantanu

2013-08-01

This paper presents a computer aided design (CAD) framework for verification and reliability analysis of protein-silicon hybrid circuits used in biosensors. It is envisioned that similar to integrated circuit (IC) CAD design tools, the proposed framework will be useful for system level optimization of biosensors and for discovery of new sensing modalities without resorting to laborious fabrication and experimental procedures. The framework referred to as FAST analyzes protein-based circuits by solving inverse problems involving stochastic functional elements that admit non-linear relationships between different circuit variables. In this regard, FAST uses a factor-graph netlist as a user interface and solving the inverse problem entails passing messages/signals between the internal nodes of the netlist. Stochastic analysis techniques like density evolution are used to understand the dynamics of the circuit and estimate the reliability of the solution. As an example, we present a complete design flow using FAST for synthesis, analysis and verification of our previously reported conductometric immunoassay that uses antibody-based circuits to implement forward error-correction (FEC).

On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

PubMed

He, Li; Li, Mo

2014-05-01

The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

Fully Printed Stretchable Thin-Film Transistors and Integrated Logic Circuits.

PubMed

Cai, Le; Zhang, Suoming; Miao, Jinshui; Yu, Zhibin; Wang, Chuan

2016-12-27

This paper reports intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits directly printed on elastomeric polydimethylsiloxane (PDMS) substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO 3 ) nanoparticles. The BaTiO 3 /PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. This work may offer an entry into more sophisticated stretchable electronic systems with monolithically integrated sensors, actuators, and displays, fabricated by scalable and low-cost methods for real life applications.

76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-17

... Integrated Circuit Semiconductor Chips and Products Containing the Same; Notice of a Commission Determination... certain large scale integrated circuit semiconductor chips and products containing same by reason of... existence of a domestic industry. The Commission's notice of investigation named several respondents...

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Measurement and Analysis of Multiple Output Transient Propagation in BJT Analog Circuits

NASA Astrophysics Data System (ADS)

Roche, Nicolas J.-H.; Khachatrian, A.; Warner, J. H.; Buchner, S. P.; McMorrow, D.; Clymer, D. A.

2016-08-01

The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET's propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET's shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path.

The Magnetics Information Consortium (MagIC)

NASA Astrophysics Data System (ADS)

Johnson, C.; Constable, C.; Tauxe, L.; Koppers, A.; Banerjee, S.; Jackson, M.; Solheid, P.

2003-12-01

The Magnetics Information Consortium (MagIC) is a multi-user facility to establish and maintain a state-of-the-art relational database and digital archive for rock and paleomagnetic data. The goal of MagIC is to make such data generally available and to provide an information technology infrastructure for these and other research-oriented databases run by the international community. As its name implies, MagIC will not be restricted to paleomagnetic or rock magnetic data only, although MagIC will focus on these kinds of information during its setup phase. MagIC will be hosted under EarthRef.org at http://earthref.org/MAGIC/ where two "integrated" web portals will be developed, one for paleomagnetism (currently functional as a prototype that can be explored via the http://earthref.org/databases/PMAG/ link) and one for rock magnetism. The MagIC database will store all measurements and their derived properties for studies of paleomagnetic directions (inclination, declination) and their intensities, and for rock magnetic experiments (hysteresis, remanence, susceptibility, anisotropy). Ultimately, this database will allow researchers to study "on the internet" and to download important data sets that display paleo-secular variations in the intensity of the Earth's magnetic field over geological time, or that display magnetic data in typical Zijderveld, hysteresis/FORC and various magnetization/remanence diagrams. The MagIC database is completely integrated in the EarthRef.org relational database structure and thus benefits significantly from already-existing common database components, such as the EarthRef Reference Database (ERR) and Address Book (ERAB). The ERR allows researchers to find complete sets of literature resources as used in GERM (Geochemical Earth Reference Model), REM (Reference Earth Model) and MagIC. The ERAB contains addresses for all contributors to the EarthRef.org databases, and also for those who participated in data collection, archiving and

Integrated circuit electrometer and sweep circuitry for an atmospheric probe

NASA Technical Reports Server (NTRS)

Zimmerman, L. E.

1971-01-01

The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

PubMed

Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

2016-06-18

This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

PubMed Central

Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

2016-01-01

This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

Photonic crystal ring resonator based optical filters for photonic integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, S., E-mail: mail2robinson@gmail.com

In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which ismore » highly suitable of photonic integrated circuits.« less

Dual-function photonic integrated circuit for frequency octo-tupling or single-side-band modulation.

PubMed

Hasan, Mehedi; Maldonado-Basilio, Ramón; Hall, Trevor J

2015-06-01

A dual-function photonic integrated circuit for microwave photonic applications is proposed. The circuit consists of four linear electro-optic phase modulators connected optically in parallel within a generalized Mach-Zehnder interferometer architecture. The photonic circuit is arranged to have two separate output ports. A first port provides frequency up-conversion of a microwave signal from the electrical to the optical domain; equivalently single-side-band modulation. A second port provides tunable millimeter wave carriers by frequency octo-tupling of an appropriate amplitude RF carrier. The circuit exploits the intrinsic relative phases between the ports of multi-mode interference couplers to provide substantially all the static optical phases needed. The operation of the proposed dual-function photonic integrated circuit is verified by computer simulations. The performance of the frequency octo-tupling and up-conversion functions is analyzed in terms of the electrical signal to harmonic distortion ratio and the optical single side band to unwanted harmonics ratio, respectively.

A SPICE2 Model for the M732 Analog Timer Integrated Circuit.

DTIC Science & Technology

1982-06-01

I AD-All? 019 ARMY ARMAMENT RESEARCH AND DEVELOPMENT C01MAND DOVER-ETC F/ S 1/ I A SPICES MODEL FOR THE M739 ANALOG TIMER INTEGRATED CIRCUIT. (U) I...JUN $I .J P TOBAK UNCLASSIFIED AR ID-20Di S I-AD-E06 3 NL ADI- A SPICE2 MODEL FOR THE M3 ANALOG TIMR INTERNATED CIRCIT, JOHN P. TOMA DTIC JUNE 1992 13...ARrIID-TR-82001 -;AZ/ 4 " 4. TITLE (and Subtitle) S . TYPE OF REPORT & PERIOD COVERED A SPICE2 MODEL FOR THE M732 ANALOG TIMER Final INTEGRATED CIRCUIT

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-04

... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... that there exists a domestic industry with respect to each of the asserted patents. The complaint named...

Four-Channel PC/104 MIL-STD-1553 Circuit Board

NASA Technical Reports Server (NTRS)

Cox, Gary L.

2004-01-01

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

NASA Astrophysics Data System (ADS)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Integrated circuit amplifiers for multi-electrode intracortical recording.

PubMed

Jochum, Thomas; Denison, Timothy; Wolf, Patrick

2009-02-01

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

NASA Technical Reports Server (NTRS)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

ICECAP: an integrated, general-purpose, automation-assisted IC50/EC50 assay platform.

PubMed

Li, Ming; Chou, Judy; King, Kristopher W; Jing, Jing; Wei, Dong; Yang, Liyu

2015-02-01

IC50 and EC50 values are commonly used to evaluate drug potency. Mass spectrometry (MS)-centric bioanalytical and biomarker labs are now conducting IC50/EC50 assays, which, if done manually, are tedious and error-prone. Existing bioanalytical sample preparation automation systems cannot meet IC50/EC50 assay throughput demand. A general-purpose, automation-assisted IC50/EC50 assay platform was developed to automate the calculations of spiking solutions and the matrix solutions preparation scheme, the actual spiking and matrix solutions preparations, as well as the flexible sample extraction procedures after incubation. In addition, the platform also automates the data extraction, nonlinear regression curve fitting, computation of IC50/EC50 values, graphing, and reporting. The automation-assisted IC50/EC50 assay platform can process the whole class of assays of varying assay conditions. In each run, the system can handle up to 32 compounds and up to 10 concentration levels per compound, and it greatly improves IC50/EC50 assay experimental productivity and data processing efficiency. © 2014 Society for Laboratory Automation and Screening.

75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-05

... Integrated Circuit Semiconductor Chips and Products Containing Same; Notice of Investigation AGENCY: U.S... of certain large scale integrated circuit semiconductor chips and products containing same by reason... alleges that an industry in the United States exists as required by subsection (a)(2) of section 337. The...

Ka-band to L-band frequency down-conversion based on III-V-on-silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Van Gasse, K.; Wang, Z.; Uvin, S.; De Deckere, B.; Mariën, J.; Thomassen, L.; Roelkens, G.

2017-12-01

In this work, we present the design, simulation and characterization of a frequency down-converter based on III-V-on-silicon photonic integrated circuit technology. We first demonstrate the concept using commercial discrete components, after which we demonstrate frequency conversion using an integrated mode-locked laser and integrated modulator. In our experiments, five channels in the Ka-band (27.5-30 GHz) with 500 MHz bandwidth are down-converted to the L-band (1.5 GHz). The breadboard demonstration shows a conversion efficiency of - 20 dB and a flat response over the 500 MHz bandwidth. The simulation of a fully integrated circuit indicates that a positive conversion gain can be obtained on a millimeter-sized photonic integrated circuit.

Aperture efficiency of integrated-circuit horn antennas

NASA Technical Reports Server (NTRS)

Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

1991-01-01

The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

SiGe/Si Monolithically Integrated Amplifier Circuits

NASA Technical Reports Server (NTRS)

Katehi, Linda P. B.; Bhattacharya, Pallab

1998-01-01

With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

NASA Astrophysics Data System (ADS)

Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

2017-06-01

In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

The neural circuits of innate fear: detection, integration, action, and memorization

PubMed Central

Silva, Bianca A.; Gross, Cornelius T.

2016-01-01

How fear is represented in the brain has generated a lot of research attention, not only because fear increases the chances for survival when appropriately expressed but also because it can lead to anxiety and stress-related disorders when inadequately processed. In this review, we summarize recent progress in the understanding of the neural circuits processing innate fear in rodents. We propose that these circuits are contained within three main functional units in the brain: a detection unit, responsible for gathering sensory information signaling the presence of a threat; an integration unit, responsible for incorporating the various sensory information and recruiting downstream effectors; and an output unit, in charge of initiating appropriate bodily and behavioral responses to the threatful stimulus. In parallel, the experience of innate fear also instructs a learning process leading to the memorization of the fearful event. Interestingly, while the detection, integration, and output units processing acute fear responses to different threats tend to be harbored in distinct brain circuits, memory encoding of these threats seems to rely on a shared learning system. PMID:27634145

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

PubMed

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Integrated proteomics identified novel activation of dynein IC2-GR-COX-1 signaling in neurofibromatosis type I (NF1) disease model cells.

PubMed

Hirayama, Mio; Kobayashi, Daiki; Mizuguchi, Souhei; Morikawa, Takashi; Nagayama, Megumi; Midorikawa, Uichi; Wilson, Masayo M; Nambu, Akiko N; Yoshizawa, Akiyasu C; Kawano, Shin; Araki, Norie

2013-05-01

Neurofibromatosis type 1 (NF1) tumor suppressor gene product, neurofibromin, functions in part as a Ras-GAP, and though its loss is implicated in the neuronal abnormality of NF1 patients, its precise cellular function remains unclear. To study the molecular mechanism of NF1 pathogenesis, we prepared NF1 gene knockdown (KD) PC12 cells, as a NF1 disease model, and analyzed their molecular (gene and protein) expression profiles with a unique integrated proteomics approach, comprising iTRAQ, 2D-DIGE, and DNA microarrays, using an integrated protein and gene expression analysis chart (iPEACH). In NF1-KD PC12 cells showing abnormal neuronal differentiation after NGF treatment, of 3198 molecules quantitatively identified and listed in iPEACH, 97 molecules continuously up- or down-regulated over time were extracted. Pathway and network analysis further revealed overrepresentation of calcium signaling and transcriptional regulation by glucocorticoid receptor (GR) in the up-regulated protein set, whereas nerve system development was overrepresented in the down-regulated protein set. The novel up-regulated network we discovered, "dynein IC2-GR-COX-1 signaling," was then examined in NF1-KD cells. Validation studies confirmed that NF1 knockdown induces altered splicing and phosphorylation patterns of dynein IC2 isomers, up-regulation and accumulation of nuclear GR, and increased COX-1 expression in NGF-treated cells. Moreover, the neurite retraction phenotype observed in NF1-KD cells was significantly recovered by knockdown of the dynein IC2-C isoform and COX-1. In addition, dynein IC2 siRNA significantly inhibited nuclear translocation and accumulation of GR and up-regulation of COX-1 expression. These results suggest that dynein IC2 up-regulates GR nuclear translocation and accumulation, and subsequently causes increased COX-1 expression, in this NF1 disease model. Our integrated proteomics strategy, which combines multiple approaches, demonstrates that NF1-related neural

Temporal integration and 1/f power scaling in a circuit model of cerebellar interneurons.

PubMed

Maex, Reinoud; Gutkin, Boris

2017-07-01

Inhibitory interneurons interconnected via electrical and chemical (GABA A receptor) synapses form extensive circuits in several brain regions. They are thought to be involved in timing and synchronization through fast feedforward control of principal neurons. Theoretical studies have shown, however, that whereas self-inhibition does indeed reduce response duration, lateral inhibition, in contrast, may generate slow response components through a process of gradual disinhibition. Here we simulated a circuit of interneurons (stellate and basket cells) of the molecular layer of the cerebellar cortex and observed circuit time constants that could rise, depending on parameter values, to >1 s. The integration time scaled both with the strength of inhibition, vanishing completely when inhibition was blocked, and with the average connection distance, which determined the balance between lateral and self-inhibition. Electrical synapses could further enhance the integration time by limiting heterogeneity among the interneurons and by introducing a slow capacitive current. The model can explain several observations, such as the slow time course of OFF-beam inhibition, the phase lag of interneurons during vestibular rotation, or the phase lead of Purkinje cells. Interestingly, the interneuron spike trains displayed power that scaled approximately as 1/ f at low frequencies. In conclusion, stellate and basket cells in cerebellar cortex, and interneuron circuits in general, may not only provide fast inhibition to principal cells but also act as temporal integrators that build a very short-term memory. NEW & NOTEWORTHY The most common function attributed to inhibitory interneurons is feedforward control of principal neurons. In many brain regions, however, the interneurons are densely interconnected via both chemical and electrical synapses but the function of this coupling is largely unknown. Based on large-scale simulations of an interneuron circuit of cerebellar cortex, we

Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

NASA Astrophysics Data System (ADS)

Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

2017-07-01

Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

NASA Technical Reports Server (NTRS)

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

1987-01-01

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

NASA Technical Reports Server (NTRS)

Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

1987-01-01

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

NASA Technical Reports Server (NTRS)

Seaward, R. C.

1967-01-01

Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

PubMed Central

Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

2008-01-01

The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

PubMed

LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

2014-06-02

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

PubMed

Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

2016-07-25

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

PubMed

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Design, Fabrication and Integration of a NaK-Cooled Circuit

NASA Technical Reports Server (NTRS)

Garber, Anne; Godfroy, Thomas

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned to for use with lithium. Due to a shi$ in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a fill design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped liquid metal NaK flow circuit.

Scalable, Lightweight, Integrated and Quick-to-Assemble (SLIQ) Hyperdrives for Functional Circuit Dissection.

PubMed

Liang, Li; Oline, Stefan N; Kirk, Justin C; Schmitt, Lukas Ian; Komorowski, Robert W; Remondes, Miguel; Halassa, Michael M

2017-01-01

Independently adjustable multielectrode arrays are routinely used to interrogate neuronal circuit function, enabling chronic in vivo monitoring of neuronal ensembles in freely behaving animals at a single-cell, single spike resolution. Despite the importance of this approach, its widespread use is limited by highly specialized design and fabrication methods. To address this, we have developed a Scalable, Lightweight, Integrated and Quick-to-assemble multielectrode array platform. This platform additionally integrates optical fibers with independently adjustable electrodes to allow simultaneous single unit recordings and circuit-specific optogenetic targeting and/or manipulation. In current designs, the fully assembled platforms are scalable from 2 to 32 microdrives, and yet range 1-3 g, light enough for small animals. Here, we describe the design process starting from intent in computer-aided design, parameter testing through finite element analysis and experimental means, and implementation of various applications across mice and rats. Combined, our methods may expand the utility of multielectrode recordings and their continued integration with other tools enabling functional dissection of intact neural circuits.

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-04

... Circuit Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... public record for this investigation may be viewed on the Commission's electronic docket (EDIS) at http... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

Study of IEMP Effects on IC Operational Amplifier Circuits

DTIC Science & Technology

1975-12-10

plasma focus to study their IEMP responses with and without superposition of TREE responses. The 30-kJ plasma focus device produced photons primarily in the 8- to 100-keV range with pulse widths typically in the range of 10 to 15 nsec. Pulses of electrons were also deposited on the external leads of the operational amplifiers to determine the characteristic responses. These units were operated in circuits with closed-loop gains ranging from 5 to 100. During direct irradiation of the operational amplifiers, it was found that the IEMP responses (caused

Interface design for CMOS-integrated Electrochemical Impedance Spectroscopy (EIS) biosensors.

PubMed

Manickam, Arun; Johnson, Christopher Andrew; Kavusi, Sam; Hassibi, Arjang

2012-10-29

Electrochemical Impedance Spectroscopy (EIS) is a powerful electrochemical technique to detect biomolecules. EIS has the potential of carrying out label-free and real-time detection, and in addition, can be easily implemented using electronic integrated circuits (ICs) that are built through standard semiconductor fabrication processes. This paper focuses on the various design and optimization aspects of EIS ICs, particularly the bio-to-semiconductor interface design. We discuss, in detail, considerations such as the choice of the electrode surface in view of IC manufacturing, surface linkers, and development of optimal bio-molecular detection protocols. We also report experimental results, using both macro- and micro-electrodes to demonstrate the design trade-offs and ultimately validate our optimization procedures.

Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

PubMed

Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

2016-02-01

Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed. Copyright © 2015 Elsevier Ltd. All rights reserved.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

NASA Astrophysics Data System (ADS)

Heck, Martijn J. R.

2017-01-01

Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hamlet, Jason; Pierson, Lyndon; Bauer, Todd

Supply chain security to detect, deter, and prevent the counterfeiting of networked and stand-alone integrated circuits (ICs) is critical to cyber security. Sandia National Laboratory researchers have developed IC ID to leverage Physically Unclonable Functions (PUFs) and strong cryptographic authentication to create a unique fingerprint for each integrated circuit. IC ID assures the authenticity of ICs to prevent tampering or malicious substitution.

Fabrication Of High-Tc Superconducting Integrated Circuits

NASA Technical Reports Server (NTRS)

Bhasin, Kul B.; Warner, Joseph D.

1992-01-01

Microwave ring resonator fabricated to demonstrate process for fabrication of passive integrated circuits containing high-transition-temperature superconductors. Superconductors increase efficiencies of communication systems, particularly microwave communication systems, by reducing ohmic losses and dispersion of signals. Used to reduce sizes and masses and increase aiming accuracies and tracking speeds of millimeter-wavelength, electronically steerable antennas. High-Tc superconductors preferable for such applications because they operate at higher temperatures than low-Tc superconductors do, therefore, refrigeration systems needed to maintain superconductivity designed smaller and lighter and to consume less power.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.