Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Implementation of activity-based costing (ABC) to drive cost reduction efforts in a semiconductor manufacturing operation

NASA Astrophysics Data System (ADS)

Naguib, Hussein; Bol, Igor I.; Lora, J.; Chowdhry, R.

1994-09-01

This paper presents a case study on the implementation of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The cost reduction activities were conducted through the efforts of 11 cross-functional teams which included members of the finance, purchasing, technology development, process engineering, equipment engineering, production control, and facility groups. The activities of these cross functional teams were coordinated by a cost council. It will be shown that these activities have resulted in a 57% reduction in the wafer manufacturing cost of the new product line. Factors contributed to successful implementation of an ABC management system are discussed.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Soft x-ray speckle from rough surfaces

NASA Astrophysics Data System (ADS)

Porter, Matthew Stanton

Dynamic light scattering has been of great use in determining diffusion times for polymer solutions. At the same time, polymer thin films are becoming of increasing importance, especially in the semiconductor industry where they are used as photoresists and interlevel dielectrics. As the dimensions of these devices decrease we will reach a point where lasers will no longer be able to probe the length scales of interest. Current laser wavelengths limit the size of observable diffusion lengths to 180-700 nm. This dissertation will discuss attempts at pushing dynamic fight scattering experiments into the soft x-ray region so that we can examine fluctuations in polymer thin films on the molecular length scale. The dissertation explores the possibility of carrying out a dynamic light scattering experiment in the soft x-ray regime. A detailed account of how to meet the basic requirements for a coherent scattering experiment in the soft x-ray regime win be given. In addition, a complete description of the chamber design will be discussed. We used our custom designed scattering chamber to collect reproducible coherent soft x-ray scattering data from etched silicon wafers and from polystyrene coated silicon wafers. The data from the silicon wafers followed the statistics for a well-developed speckle pattern while the data from the polystyrene films exhibited Poisson statistics. We used the data from both the etched wafers and the polystyrene coated wafers to place a lower limit of ~20 Å on the RMS surface roughness of samples which will produce well defined speckle patterns for the current detector setup. Future experiments which use the criteria set forth in this dissertation have the opportunity to be even more successful than this dissertation project.

Calligraphic Poling of Ferroelectric Material

NASA Technical Reports Server (NTRS)

Mohageg, Makan; Strekalov, Dmitry; Savchenkov, Anatoliy; Matsko, Adrey; Maleki, Lute; Iltchenko, Vladimir

2007-01-01

Calligraphic poling is a technique for generating an arbitrary, possibly complex pattern of localized reversal in the direction of permanent polarization in a wafer of LiNbO3 or other ferroelectric material. The technique is so named because it involves a writing process in which a sharp electrode tip is moved across a surface of the wafer to expose the wafer to a polarizing electric field in the desired pattern. The technique is implemented by use of an apparatus, denoted a calligraphic poling machine (CPM), that includes the electrode and other components as described in more detail below.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Three-dimensional magnetic induction model of an octagonal edge-defined film-fed growth system

NASA Astrophysics Data System (ADS)

Rajendran, S.; Holmes, K.; Menna, A.

1994-03-01

Silicon wafers for the photovoltaic industry are produced by growing thin octagonal tubes by the edge-defined film-fed growth (EFG) process. The thermal origin of the wafer thickness variations was studied with a three-dimensional (3D) magnetic induction model. The implementation of the computer code and the significance of the computed results for improving the thickness uniformity are discussed.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

CD and defect improvement challenges for immersion processes

NASA Astrophysics Data System (ADS)

Ehara, Keisuke; Ema, Tatsuhiko; Yamasaki, Toshinari; Nakagawa, Seiji; Ishitani, Seiji; Morita, Akihiko; Kim, Jeonghun; Kanaoka, Masashi; Yasuda, Shuichi; Asai, Masaya

2009-03-01

The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

NASA Astrophysics Data System (ADS)

Weatherwax Scott, Caroline; Tsareff, Christopher R.

1990-06-01

One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles played by the process engineering expert and the knowledge engineer are discussed. The features of the systems are shown, particularly the interactive quality of the consultations and the ease of system use.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

NASA Astrophysics Data System (ADS)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-03-01

This report describes work to advance the manufacturing line capabilities in crystal growth and laser cutting of Mobil Solar's unique edge-defined film-fed growth (EFG) octagon technology and to reduce the manufacturing costs of 10 cm x 10 cm polycrystalline silicon EFG wafers. The report summarizes the significant technical improvements in EFG technology achieved in the first 6 months of the PVMaT Phase 2 and the success in meeting program milestones. Technical results are reported for each of the three main pregrain areas: Task 5 -- Thin octagon growth (crystal growth) to reduce the thickness of the octagon to 200 microns; Task 6 -- Laser cutting-to improve the laser cutting process so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and Task 7 -- Process control and product specification to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Throughput increase by adjustment of the BARC drying time with coat track process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Long, Ryan

2005-05-01

Throughput of a coater module within the coater track is related to the solvent evaporation rate from the material that is being coated. Evaporation rate is controlled by the spin dynamics of the wafer and airflow dynamics over the wafer. Balancing these effects is the key to achieving very uniform coatings across a flat unpatterned wafer. As today"s coat tracks are being pushed to higher throughputs to match the scanner, the coat module throughput must be increased as well. For chemical manufacturers the evaporation rate of the material depends on the solvent used. One measure of relative evaporation rates is to compare flash points of a solvent. The lower the flash point, the quicker the solvent will evaporate. It is possible to formulate products with these volatile solvents although at a price. Shipping and manufacturing a more flammable product increase chances of fire, thereby increasing insurance premiums. Also, the end user of these chemicals will have to take extra precautions in the fab and in storage of these more flammable chemicals. An alternative coat process is possible which would allow higher throughput in a distinct coat module without sacrificing safety. A tradeoff is required for this process, that being a more complicated coat process and a higher viscosity chemical. The coat process uses the fact that evaporation rate depends on the spin dynamics of the wafer by utilizing a series of spin speeds that first would set the thickness of the material followed by a high spin speed to remove the residual solvent. This new process can yield a throughput of over 150 wafers per hour (wph) given two coat modules. The thickness uniformity of less than 2 nm (3 sigma) is still excellent, while drying times are shorter than 10 seconds to achieve the 150 wph throughput targets.

ROI on yield data analysis systems through a business process management strategy

NASA Astrophysics Data System (ADS)

Rehani, Manu; Strader, Nathan; Hanson, Jeff

2005-05-01

The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

2012-08-01

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm 2 and 100 × 100 μm 2 . Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

High-speed bipolar phototransistors in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Zimmermann, H

2013-03-01

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm 2 and 100×100 μm 2 . Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p + wafer with a p - epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

New dynamic silicon photonic components enabled by MEMS technology

NASA Astrophysics Data System (ADS)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

New methodology for dynamic lot dispatching

NASA Astrophysics Data System (ADS)

Tai, Wei-Herng; Wang, Jiann-Kwang; Lin, Kuo-Cheng; Hsu, Yi-Chin

1994-09-01

This paper presents a new dynamic dispatching rule to improve delivery. The dynamic dispatching rule named `SLACK and OTD (on time delivery)' is developed for focusing on due date and target cycle time under the environment of IC manufacturing. This idea uses traditional SLACK policy to control long term due date and new OTD policy to reflect the short term stage queue time. Through the fuzzy theory, these two policies are combined as the dispatching controller to define the lot priority in the entire production line. Besides, the system would automatically update the lot priority according to the current line situation. Since the wafer dispatching used to be controlled by critical ratio that indicates the low customer satisfaction. And the overall slack time in the front end of the process is greater compared to that in the rear end of the process which reveals that the machines in the rear end are overloaded by rush orders. When SLACK and OTD are used the due date control has been gradually improved. The wafer with either a long stage queue time or urgent due date will be pushed through the overall production line instead of jammed in the front end. A demand pull system is also developed to satisfy not only due date but also the quantity of monthly demand. The SLACK and OTD rule has been implemented in Taiwan Semiconductor Manufacturing Company for eight months with beneficial results. In order to clearly monitor the SLACK and OTD policy, a method called box chart is generated to simulate the entire production system. From the box chart, we can not only monitor the result of decision policy but display the production situation on the density figure. The production cycle time and delivery situation can also be investigated.

Reticle haze: an industrial approach

NASA Astrophysics Data System (ADS)

Gough, Stuart; Gérard, Xavier; Bichebois, Pascal; Roche, Agnès; Sundermann, Frank; Guyader, Véronique; Bièron, Yann; Galvier, Jean; Nicoleau, Serge

2007-02-01

Crystal growth on advanced reticles is currently a world wide industrial problem in high end semiconductor production environment, crystals are mainly found on reticles that use high energy photons at 193nm wavelength. The most common crystals to be found on masks are ammonium sulphate, a combination of sulphate, from maskshop residues after clean, pellicle materials and storage conditions and amines from clean room, tool and storage environments. High energy photons act as a catalyst to form crystals on both the pattern side as well as the backglass surface. After a number of exposures crystals can grow in size and eventually become printable. In order to detect HAZE before critical dimensions have been reached suitable detection methods need to be implemented to ensure image integrity. These detection methods are different and complementary depending on the surface to be inspected. Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Differences between wafer and bake plate temperature uniformity in proximity bake: a theoretical and experimental study

NASA Astrophysics Data System (ADS)

Ramanan, Natarajan; Kozman, Austin; Sims, James B.

2000-06-01

As the lithography industry moves toward finer features, specifications on temperature uniformity of the bake plates are expected to become more stringent. Consequently, aggressive improvements are needed to conventional bake station designs to make them perform significantly better than current market requirements. To this end, we have conducted a rigorous study that combines state-of-the-art simulation tools and experimental methods to predict the impact of the parameters that influence the uniformity of the wafer in proximity bake. The key observation from this detailed study is that the temperature uniformity of the wafer in proximity mode depends on a number of parameters in addition to the uniformity of the bake plate itself. These parameters include the lid design, the air flow distribution around the bake chamber, bake plate design and flatness of the bake plate and wafer. By performing careful experimental studies that were guided by extensive numerical simulations, we were able to understand the relative importance of each of these parameters. In an orderly fashion, we made appropriate design changes to curtail or eliminate the nonuniformity caused by each of these parameters. After implementing all these changes, we have now been able to match or improve the temperature uniformity of the wafer in proximity with that of a contact measurement on the bake plate. The wafer temperature uniformity is also very close to the theoretically predicted uniformity of the wafer.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

PubMed

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

PubMed Central

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project. PMID:24065877

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

PubMed

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

New getter configuration at wafer level for assuring long term stability of MEMs

NASA Astrophysics Data System (ADS)

Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

2003-01-01

The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

Development of a plan for automating integrated circuit processing

NASA Technical Reports Server (NTRS)

1971-01-01

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

Numerical modeling of carrier gas flow in atomic layer deposition vacuum reactor: A comparative study of lattice Boltzmann models

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Dongqing; Chien Jen, Tien; Li, Tao

2014-01-15

This paper characterizes the carrier gas flow in the atomic layer deposition (ALD) vacuum reactor by introducing Lattice Boltzmann Method (LBM) to the ALD simulation through a comparative study of two LBM models. Numerical models of gas flow are constructed and implemented in two-dimensional geometry based on lattice Bhatnagar–Gross–Krook (LBGK)-D2Q9 model and two-relaxation-time (TRT) model. Both incompressible and compressible scenarios are simulated and the two models are compared in the aspects of flow features, stability, and efficiency. Our simulation outcome reveals that, for our specific ALD vacuum reactor, TRT model generates better steady laminar flow features all over the domainmore » with better stability and reliability than LBGK-D2Q9 model especially when considering the compressible effects of the gas flow. The LBM-TRT is verified indirectly by comparing the numerical result with conventional continuum-based computational fluid dynamics solvers, and it shows very good agreement with these conventional methods. The velocity field of carrier gas flow through ALD vacuum reactor was characterized by LBM-TRT model finally. The flow in ALD is in a laminar steady state with velocity concentrated at the corners and around the wafer. The effects of flow fields on precursor distributions, surface absorptions, and surface reactions are discussed in detail. Steady and evenly distributed velocity field contribute to higher precursor concentration near the wafer and relatively lower particle velocities help to achieve better surface adsorption and deposition. The ALD reactor geometry needs to be considered carefully if a steady and laminar flow field around the wafer and better surface deposition are desired.« less

Composition of the C6+ Fraction of Natural Gas by Multiple Porous Layer Open Tubular Capillaries Maintained at Low Temperatures.

PubMed

Burger, Jessica L; Lovestead, Tara M; Bruno, Thomas J

2016-03-17

As the sources of natural gas become more diverse, the trace constituents of the C 6 + fraction are of increasing interest. Analysis of fuel gas (including natural gas) for compounds with more than 6 carbon atoms (the C 6 + fraction) has historically been complex and expensive. Hence, this is a procedure that is used most often in troubleshooting rather than for day-to-day operations. The C 6 + fraction affects gas quality issues and safety considerations such as anomalies associated with odorization. Recent advances in dynamic headspace vapor collection can be applied to this analysis and provide a faster, less complex alternative for compositional determination of the C 6 + fraction of natural gas. Porous layer open tubular capillaries maintained at low temperatures (PLOT-cryo) form the basis of a dynamic headspace sampling method that was developed at NIST initially for explosives in 2009. This method has been recently advanced by the combining of multiple PLOT capillary traps into one "bundle," or wafer, resulting in a device that allows the rapid trapping of relatively large amounts of analyte. In this study, natural gas analytes were collected by flowing natural gas from the laboratory (gas out of the wall) or a prepared surrogate gas flowing through a chilled wafer. The analytes were then removed from the PLOT-cryo wafer by thermal desorption and subsequent flushing of the wafer with helium. Gas chromatography (GC) with mass spectrometry (MS) was then used to identify the analytes.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Ion Dynamics in a Single and Dual Radio Frequency Sheath Measured by Laser-Induced Fluorescence

NASA Astrophysics Data System (ADS)

Moore, Nathaniel Breckenridge

Ion dynamics are investigated in a single and dual radio frequency sheath as a function of radius above a 30 cm diameter biased silicon wafer for the first time in an industrial inductively coupled (440 kHz, 500 W) plasma etch tool. Ion velocity distribution (IVD) function measurements in the argon plasma are taken using laser induced fluorescence (LIF). Planar sheets of laser light enter the chamber both parallel and perpendicular to the surface of the wafer in order to measure both parallel and perpendicular IVDs at thousands of spatial positions. A fast (30 ns exposure) CCD camera measures the resulting fluorescence with a spatial resolution of 0.4 mm. The dual-frequency bias on the wafer is comprised of a 2 MHz low frequency (LF) bias and a 19 MHz high frequency (HF) bias. The laser is phase locked to the LF bias and IVD measurements are taken at several different LF phases. Ion energy distribution (IED) function measurements and calculated moments are compared for several cases. For the LF case (no HF), the IEDs were found to be highly phase dependent and were varied radially up to 10%. Calculated mean velocity vectors showed large impact angles near the surface of the wafer with the largest angles observed near the wafer edge. The LF experimental results are compared with simulations designed specifically for this particular plasma tool and showed good qualitative agreement. For the dual frequency case, IEDs were measured at two disparate phases of the phase-locked LF bias. IEDs were found to be multi-peaked and were well-approximated by a sum of Maxwellian distributions. The calculated fluxes in the dual frequency case were found to be substantially more radially uniform than the single frequency bias case. For industrial applications, this radially uniform ion flux is evidently a trade off with the undesirable multi-peaked structure in the IEDs.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Composition of the C6+ Fraction of Natural Gas by Multiple Porous Layer Open Tubular Capillaries Maintained at Low Temperatures*

PubMed Central

Burger, Jessica L.; Lovestead, Tara M.; Bruno, Thomas J.

2017-01-01

As the sources of natural gas become more diverse, the trace constituents of the C6+ fraction are of increasing interest. Analysis of fuel gas (including natural gas) for compounds with more than 6 carbon atoms (the C6+ fraction) has historically been complex and expensive. Hence, this is a procedure that is used most often in troubleshooting rather than for day-to-day operations. The C6+ fraction affects gas quality issues and safety considerations such as anomalies associated with odorization. Recent advances in dynamic headspace vapor collection can be applied to this analysis and provide a faster, less complex alternative for compositional determination of the C6+ fraction of natural gas. Porous layer open tubular capillaries maintained at low temperatures (PLOT-cryo) form the basis of a dynamic headspace sampling method that was developed at NIST initially for explosives in 2009. This method has been recently advanced by the combining of multiple PLOT capillary traps into one “bundle,” or wafer, resulting in a device that allows the rapid trapping of relatively large amounts of analyte. In this study, natural gas analytes were collected by flowing natural gas from the laboratory (gas out of the wall) or a prepared surrogate gas flowing through a chilled wafer. The analytes were then removed from the PLOT-cryo wafer by thermal desorption and subsequent flushing of the wafer with helium. Gas chromatography (GC) with mass spectrometry (MS) was then used to identify the analytes. PMID:29332993

Method and device for predicting wavelength dependent radiation influences in thermal systems

DOEpatents

Kee, Robert J.; Ting, Aili

1996-01-01

A method and apparatus for predicting the spectral (wavelength-dependent) radiation transport in thermal systems including interaction by the radiation with partially transmitting medium. The predicted model of the thermal system is used to design and control the thermal system. The predictions are well suited to be implemented in design and control of rapid thermal processing (RTP) reactors. The method involves generating a spectral thermal radiation transport model of an RTP reactor. The method also involves specifying a desired wafer time dependent temperature profile. The method further involves calculating an inverse of the generated model using the desired wafer time dependent temperature to determine heating element parameters required to produce the desired profile. The method also involves controlling the heating elements of the RTP reactor in accordance with the heating element parameters to heat the wafer in accordance with the desired profile.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

NASA Astrophysics Data System (ADS)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

Development of a Wafer Positioning System for the Sandia Extreme Ultraviolet Lithography Tool

NASA Technical Reports Server (NTRS)

Wronosky, John B.; Smith, Tony G.; Darnold, Joel R.

1996-01-01

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development. This paper describes the design, implementation, and functional capability of the system. Specifics regarding control system electronics, including software and control algorithm structure, as well as performance design goals and test results are presented. Potential system enhancements, some of which are in process, are also discussed.

Tip/tilt-compensated through-focus scanning optical microscopy

NASA Astrophysics Data System (ADS)

Lee, Jun Ho; Park, Jun Hyung; Jeong, Dohwan; Shin, Eun Ji; Park, Chris

2016-11-01

Through-Focus Optical Microscopy (TSOM), with nanometer scale lateral and vertical sensitivity matching those of scanning electron microscopy, has been demonstrated to be utilized for 3D inspection and metrology. There have been sensitivity and instability issues in acquiring through-focus images because TSOM 3D information is indirectly extracted by differentiating a target TSOM image from reference TSOM images. This paper first reports on the optical axis instability that occurs during the scanning process of TSOM when implemented in an existing patterned wafer inspection tool by moving the wafer plane; this is followed by quantitative confirmation of the optical/mechanical instability using a new TSOM tool on an optical bench with a Shack-Hartmann wavefront sensor and a tip/tilt sensor. Then, this paper proposes two tip/tilt compensated TSOM optical acquisition methods that can be applied with adaptive optics. The first method simply adopts a tip/tilt mirror with a quad cell in a simple closed loop, while the second method adopts a highorder deformable mirror with a Shack-Hartmann sensor. The second method is able to correct high-order residual aberrations as well as to perform through-focus scanning without z-axis movement, while the first method is easier to implement in pre-existing wafer inspection systems with only minor modification.

Ultra-high aggregate bandwidth two-dimensional multiple-wavelength diode laser arrays

NASA Astrophysics Data System (ADS)

Chang-Hasnain, Connie

1993-12-01

Two-dimensional (2D) multi-wavelength vertical cavity surface emitting laser (VCSEL) arrays is promising for ultrahigh aggregate capacity optical networks. A 2D VCSEL array emitting 140 distinct wavelengths was reported by implementing a spatially graded layer in the VCSEL structure, which in turn creates a wavelength spread. Concentrtion was on epitaxial growth techniques to make reproducible and repeatable multi-wavelength VCSEL arrays. Our approach to fabricate the spatially graded layer involves creating a nonuniform substrate surface temperature across the wafer during the growth of the cavity spacer region using the fact that the molecular beam epitaxy growth of GaAs is highly sensitive to the substrate temperature. Growth is investigated with the use of a patterned spacer (either a Ga or Si substrate) placed in-between the substrate and its heater. The temperature distribution on such wafers is used to guide our experiments. A reflectivity measurement apparatus that is capable of mapping a 2 in. wafer with a 100 microns diameter resolution was built for diagnosing our wafers. In this first six-month report, our calculations, the various experimental results, and a discussion on future directions are presented.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Modeling physical vapor deposition of energetic materials

DOE PAGES

Shirvan, Koroush; Forrest, Eric C.

2018-03-28

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Modeling physical vapor deposition of energetic materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shirvan, Koroush; Forrest, Eric C.

Morphology and microstructure of organic explosive films formed using physical vapor deposition (PVD) processes strongly depends on local surface temperature during deposition. Currently, there is no accurate means of quantifying the local surface temperature during PVD processes in the deposition chambers. This study focuses on using a multiphysics computational fluid dynamics tool, STARCCM+, to simulate pentaerythritol tetranitrate (PETN) deposition. The PETN vapor and solid phase were simulated using the volume of fluid method and its deposition in the vacuum chamber on spinning silicon wafers was modeled. The model also included the spinning copper cooling block where the wafers are placedmore » along with the chiller operating with forced convection refrigerant. Implicit time-dependent simulations in two- and three-dimensional were performed to derive insights in the governing physics for PETN thin film formation. PETN is deposited at the rate of 14 nm/s at 142.9 °C on a wafer with an initial temperature of 22 °C. The deposition of PETN on the wafers was calculated at an assumed heat transfer coefficient (HTC) of 400 W/m 2 K. This HTC proved to be the most sensitive parameter in determining the local surface temperature during deposition. Previous experimental work found noticeable microstructural changes with 0.5 mm fused silica wafers in place of silicon during the PETN deposition. This work showed that fused silica slows initial wafer cool down and results in ~10 °C difference for the surface temperature at 500 μm PETN film thickness. It was also found that the deposition surface temperature is insensitive to the cooling power of the copper block due to the copper block's very large heat capacity and thermal conductivity relative to the heat input from the PVD process. Future work should incorporate the addition of local stress during PETN deposition. Lastly, based on simulation results, it is also recommended to investigate the impact of wafer surface energy on the PETN microstructure and morphology formation.« less

Ultrafast carrier dynamics in a p-type GaN wafer under different carrier distributions

NASA Astrophysics Data System (ADS)

Fang, Yu; Yang, Junyi; Yang, Yong; Wu, Xingzhi; Xiao, Zhengguo; Zhou, Feng; Song, Yinglin

2016-02-01

The dependence of the carrier distribution on photoexcited carrier dynamics in a p-type Mg-doped GaN (GaN:Mg) wafer were systematically measured by femtosecond transient absorption (TA) spectroscopy. The homogeneity of the carrier distribution was modified by tuning the wavelength of the UV pulse excitation around the band gap of GaN:Mg. The TA kinetics appeared to be biexponential for all carrier distributions, and only the slower component decayed faster as the inhomogeneity of the carrier distribution increased. It was concluded that the faster component (50-70 ps) corresponded to the trap process of holes by the Mg acceptors, and the slower component (150-600 ps) corresponded to the combination of non-radiative surface recombination and intrinsic carrier recombination via dislocations. Moreover, the slower component increased gradually with the incident fluence due to the saturation of surface states.

Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gajski, D.D.; Sameh, A.H.; Wisniewski, J.A.

1982-01-01

With the rapid advances in semiconductor technology, the construction of Wafer Scale Integration (WSI)-multiprocessors consisting of a large number of processors is now feasible. We illustrate the implementation of some basic linear algebra algorithms on such multiprocessors.

Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

NASA Astrophysics Data System (ADS)

Bakhshizadeh, N.; Sivoththaman, S.

2017-12-01

Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

Enhancing Scheduling Performance for a Wafer Fabrication Factory: The Biobjective Slack-Diversifying Nonlinear Fluctuation-Smoothing Rule

PubMed Central

Chen, Toly; Wang, Yu Cheng

2012-01-01

A biobjective slack-diversifying nonlinear fluctuation-smoothing rule (biSDNFS) is proposed in the present work to improve the scheduling performance of a wafer fabrication factory. This rule was derived from a one-factor bi-objective nonlinear fluctuation-smoothing rule (1f-biNFS) by dynamically maximizing the standard deviation of the slack, which has been shown to benefit scheduling performance by several previous studies. The efficacy of the biSDNFS was validated with a simulated case; evidence was found to support its effectiveness. We also suggested several directions in which it can be exploited in the future. PMID:23509446

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Curved channel MCP improvement program

NASA Technical Reports Server (NTRS)

Laprade, Bruce N.; Corbett, Michael B.

1987-01-01

Blowholes and blemishes were determined to start at two stages of manufacturing. Sperical blowholes resulted from trapped gas between the high melting temperature bond glass and the MCP wafer. During thermal processing, the trapped gas expanded and displaced the softened channel glass to form a spherical inclusion. This defect was eliminated by grinding the prefritted bond wafer and channel plate wafer to a flatness which ensured intimate contact prior to fusion. Elliptical blowholes or blemishes were introduced during the fiber draw stage. Contaminants trapped between the core bar and clad tubing volatized providing large quantities of expanding gas. These pockets of gas became elongated to an ellipsoidal shape during fiber draw. Special cleanliness procedures were developed for the grinding, polishing, and acid etching of core bars. Improvements in channel curvature fabrication were implemented. The design of the shearing fixture was evaluated. A new design was developed which eliminated an off-axis moment. The shearing furnace design was evaluated. Steady state thermal conditions instead of thermal transient conditions were determined to reduce curvature nonuniformity.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Numerical and experimental simulation of linear shear piezoelectric phased arrays for structural health monitoring

NASA Astrophysics Data System (ADS)

Wang, Wentao; Zhang, Hui; Lynch, Jerome P.; Cesnik, Carlos E. S.; Li, Hui

2017-04-01

A novel d36-type piezoelectric wafer fabricated from lead magnesium niobate-lead titanate (PMN-PT) is explored for the generation of in-plane horizontal shear waves in plate structures. The study focuses on the development of a linear phased array (PA) of PMN-PT wafers to improve the damage detection capabilities of a structural health monitoring (SHM) system. An attractive property of in-plane horizontal shear waves is that they are nondispersive yet sensitive to damage. This study characterizes the directionality of body waves (Lamb and horizontal shear) created by a single PMN-PT wafer bonded to the surface of a metallic plate structure. Second, a linear PA is designed from PMN-PT wafers to steer and focus Lamb and horizontal shear waves in a plate structure. Numerical studies are conducted to explore the capabilities of a PMN-PT-based PA to detect damage in aluminum plates. Numerical simulations are conducted using the Local Interaction Simulation Approach (LISA) implemented on a parallelized graphical processing unit (GPU) for high-speed execution. Numerical studies are further validated using experimental tests conducted with a linear PA. The study confirms the ability of an PMN-PT phased array to accurately detect and localize damage in aluminum plates.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

A Summary of Lightpipe Radiation Thermometry Research at NIST

PubMed Central

Tsai, Benjamin K.

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed. PMID:27274914

A Summary of Lightpipe Radiation Thermometry Research at NIST.

PubMed

Tsai, Benjamin K

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

Comparison of Experimental Methods for Estimating Matrix Diffusion Coefficients for Contaminant Transport Modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Telfeyan, Katherine Christina; Ware, Stuart Douglas; Reimus, Paul William

Diffusion cell and diffusion wafer experiments were conducted to compare methods for estimating matrix diffusion coefficients in rock core samples from Pahute Mesa at the Nevada Nuclear Security Site (NNSS). A diffusion wafer method, in which a solute diffuses out of a rock matrix that is pre-saturated with water containing the solute, is presented as a simpler alternative to the traditional through-diffusion (diffusion cell) method. Both methods yielded estimates of matrix diffusion coefficients that were within the range of values previously reported for NNSS volcanic rocks. The difference between the estimates of the two methods ranged from 14 to 30%,more » and there was no systematic high or low bias of one method relative to the other. From a transport modeling perspective, these differences are relatively minor when one considers that other variables (e.g., fracture apertures, fracture spacings) influence matrix diffusion to a greater degree and tend to have greater uncertainty than diffusion coefficients. For the same relative random errors in concentration measurements, the diffusion cell method yields diffusion coefficient estimates that have less uncertainty than the wafer method. However, the wafer method is easier and less costly to implement and yields estimates more quickly, thus allowing a greater number of samples to be analyzed for the same cost and time. Given the relatively good agreement between the methods, and the lack of any apparent bias between the methods, the diffusion wafer method appears to offer advantages over the diffusion cell method if better statistical representation of a given set of rock samples is desired.« less

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

NASA Astrophysics Data System (ADS)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Comparison of experimental methods for estimating matrix diffusion coefficients for contaminant transport modeling

NASA Astrophysics Data System (ADS)

Telfeyan, Katherine; Ware, S. Doug; Reimus, Paul W.; Birdsell, Kay H.

2018-02-01

Diffusion cell and diffusion wafer experiments were conducted to compare methods for estimating effective matrix diffusion coefficients in rock core samples from Pahute Mesa at the Nevada Nuclear Security Site (NNSS). A diffusion wafer method, in which a solute diffuses out of a rock matrix that is pre-saturated with water containing the solute, is presented as a simpler alternative to the traditional through-diffusion (diffusion cell) method. Both methods yielded estimates of effective matrix diffusion coefficients that were within the range of values previously reported for NNSS volcanic rocks. The difference between the estimates of the two methods ranged from 14 to 30%, and there was no systematic high or low bias of one method relative to the other. From a transport modeling perspective, these differences are relatively minor when one considers that other variables (e.g., fracture apertures, fracture spacings) influence matrix diffusion to a greater degree and tend to have greater uncertainty than effective matrix diffusion coefficients. For the same relative random errors in concentration measurements, the diffusion cell method yields effective matrix diffusion coefficient estimates that have less uncertainty than the wafer method. However, the wafer method is easier and less costly to implement and yields estimates more quickly, thus allowing a greater number of samples to be analyzed for the same cost and time. Given the relatively good agreement between the methods, and the lack of any apparent bias between the methods, the diffusion wafer method appears to offer advantages over the diffusion cell method if better statistical representation of a given set of rock samples is desired.

Overlay performance assessment of MAPPER's FLX-1200 (Conference Presentation)

NASA Astrophysics Data System (ADS)

Lattard, Ludovic; Servin, Isabelle; Pradelles, Jonathan; Blancquaert, Yoann; Rademaker, Guido; Pain, Laurent; de Boer, Guido; Brandt, Pieter; Dansberg, Michel; Jager, Remco J. A.; Peijster, Jerry J. M.; Slot, Erwin; Steenbrink, Stijn W. H. K.; Vergeer, Niels; Wieland, Marco

2017-04-01

Mapper Lithography has introduced its first product, the FLX-1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

Diffusion of oxygen in cork.

PubMed

Lequin, Sonia; Chassagne, David; Karbowiak, Thomas; Simon, Jean-Marc; Paulin, Christian; Bellat, Jean-Pierre

2012-04-04

This work reports measurements of effective oxygen diffusion coefficient in raw cork. Kinetics of oxygen transfer through cork is studied at 298 K thanks to a homemade manometric device composed of two gas compartments separated by a cork wafer sample. The first compartment contains oxygen, whereas the second one is kept under dynamic vacuum. The pressure decrease in the first compartment is recorded as a function of time. The effective diffusion coefficient D(eff) is obtained by applying Fick's law to transient state using a numerical method based on finite differences. An analytical model derived from Fick's law applied to steady state is also proposed. Results given by these two methods are in close agreement with each other. The harmonic average of the effective diffusion coefficients obtained from the distribution of 15 cork wafers of 3 mm thickness is 1.1 × 10(-9) m(2) s(-1) with a large distribution over four decades. The statistical analysis of the Gaussian distribution obtained on a 3 mm cork wafer is extrapolated to a 48 mm cork wafer, which length corresponds to a full cork stopper. In this case, the probability density distribution gives a mean value of D(eff) equal to 1.6 × 10(-9) m(2) s(-1). This result shows that it is possible to obtain the effective diffusion coefficient of oxygen through cork from short time (few days) measurements performed on a thin cork wafer, whereas months are required to obtain the diffusion coefficient for a full cork stopper. Permeability and oxygen transfer rate are also calculated for comparison with data from other studies.

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure

DOE PAGES

Persaud, A.; Ji, Q.; Feinberg, E.; ...

2017-06-08

Here, a new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number ofmore » parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further red ucing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Finally, ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.« less

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure

NASA Astrophysics Data System (ADS)

Persaud, A.; Ji, Q.; Feinberg, E.; Seidl, P. A.; Waldron, W. L.; Schenkel, T.; Lal, A.; Vinayakumar, K. B.; Ardanuc, S.; Hammer, D. A.

2017-06-01

A new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number of parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further reducing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure.

PubMed

Persaud, A; Ji, Q; Feinberg, E; Seidl, P A; Waldron, W L; Schenkel, T; Lal, A; Vinayakumar, K B; Ardanuc, S; Hammer, D A

2017-06-01

A new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number of parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further reducing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

NASA Astrophysics Data System (ADS)

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Integrated otpical monitoring of MEMS for closed-loop control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Wang, Limin; McCormick, W. B.; Rittenhouse, S. A.; Famouri, Parviz F.; Hornak, Lawrence A.

2003-01-01

Robust control and failure assessment of MEMS employed in physically demanding, mission critical applications will allow for higher degrees of quality assurance in MEMS operation. Device fault detection and closed-loop control require detailed knowledge of the operational states of MEMS over the lifetime of the device, obtained by a means decoupled from the system. Preliminary through-wafer optical monitoring research efforts have shown that through-wafer optical probing is suitable for characterizing and monitoring the behavior of MEMS, and can be implemented in an integrated optical monitoring package for continuous in-situ device monitoring. This presentation will discuss research undertaken to establish integrated optical device metrology for closed-loop control of a MUMPS fabricated lateral harmonic oscillator. Successful linear closed-loop control results using a through-wafer optical microprobe position feedback signal will be presented. A theoretical optical output field intensity study of grating structures, fabricated on the shuttle of the resonator, was performed to improve the position resolution of the optical microprobe position signal. Through-wafer microprobe signals providing a positional resolution of 2 μm using grating structures will be shown, along with initial binary Fresnel diffractive optical microelement design layout, process development, and testing results. Progress in the design, fabrication, and test of integrated optical elements for multiple microprobe signal delivery and recovery will be discussed, as well as simulation of device system model parameter changes for failure assessment.

Comparison of experimental methods for estimating matrix diffusion coefficients for contaminant transport modeling

DOE PAGES

Telfeyan, Katherine Christina; Ware, Stuart Doug; Reimus, Paul William; ...

2018-01-31

Here, diffusion cell and diffusion wafer experiments were conducted to compare methods for estimating effective matrix diffusion coefficients in rock core samples from Pahute Mesa at the Nevada Nuclear Security Site (NNSS). A diffusion wafer method, in which a solute diffuses out of a rock matrix that is pre-saturated with water containing the solute, is presented as a simpler alternative to the traditional through-diffusion (diffusion cell) method. Both methods yielded estimates of effective matrix diffusion coefficients that were within the range of values previously reported for NNSS volcanic rocks. The difference between the estimates of the two methods ranged frommore » 14 to 30%, and there was no systematic high or low bias of one method relative to the other. From a transport modeling perspective, these differences are relatively minor when one considers that other variables (e.g., fracture apertures, fracture spacings) influence matrix diffusion to a greater degree and tend to have greater uncertainty than effective matrix diffusion coefficients. For the same relative random errors in concentration measurements, the diffusion cell method yields effective matrix diffusion coefficient estimates that have less uncertainty than the wafer method. However, the wafer method is easier and less costly to implement and yields estimates more quickly, thus allowing a greater number of samples to be analyzed for the same cost and time. Given the relatively good agreement between the methods, and the lack of any apparent bias between the methods, the diffusion wafer method appears to offer advantages over the diffusion cell method if better statistical representation of a given set of rock samples is desired.« less

Comparison of experimental methods for estimating matrix diffusion coefficients for contaminant transport modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Telfeyan, Katherine Christina; Ware, Stuart Doug; Reimus, Paul William

Here, diffusion cell and diffusion wafer experiments were conducted to compare methods for estimating effective matrix diffusion coefficients in rock core samples from Pahute Mesa at the Nevada Nuclear Security Site (NNSS). A diffusion wafer method, in which a solute diffuses out of a rock matrix that is pre-saturated with water containing the solute, is presented as a simpler alternative to the traditional through-diffusion (diffusion cell) method. Both methods yielded estimates of effective matrix diffusion coefficients that were within the range of values previously reported for NNSS volcanic rocks. The difference between the estimates of the two methods ranged frommore » 14 to 30%, and there was no systematic high or low bias of one method relative to the other. From a transport modeling perspective, these differences are relatively minor when one considers that other variables (e.g., fracture apertures, fracture spacings) influence matrix diffusion to a greater degree and tend to have greater uncertainty than effective matrix diffusion coefficients. For the same relative random errors in concentration measurements, the diffusion cell method yields effective matrix diffusion coefficient estimates that have less uncertainty than the wafer method. However, the wafer method is easier and less costly to implement and yields estimates more quickly, thus allowing a greater number of samples to be analyzed for the same cost and time. Given the relatively good agreement between the methods, and the lack of any apparent bias between the methods, the diffusion wafer method appears to offer advantages over the diffusion cell method if better statistical representation of a given set of rock samples is desired.« less

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Enhanced capture rate for haze defects in production wafer inspection

NASA Astrophysics Data System (ADS)

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

PubMed

Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

2016-03-01

Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

Economics of ingot slicing with an internal diameter saw for low-cost solar cells

NASA Technical Reports Server (NTRS)

Daud, T.; Liu, J. K.; Fiegl, G.

1981-01-01

Slicing of silicon ingots using diamond impregnated internal diameter blade saws has been a standard technology of the semiconductor industry. This paper describes work on improvements to this technology for 10 cm diameter ingot slicing. Ingot rotation, dynamic blade edge control with feedback, mechanized blade dressing and development of thinner blades are the approaches tried. A comparison of the results for wafering with and without ingot rotation is also made. A sensitivity analysis of the major cost elements in wafering is performed for 10 cm diameter ingot and extended to the 15 cm diameter ingot case. Various parameter values such as machine cost, feed rate and consumable materials cost are identified both for single and multiple ingot slicing.

Investigation of the Static and Dynamic Characteristics for a Wafer-Fused C-band VCSEL in the Mode of the Optical-Electric Converter

NASA Astrophysics Data System (ADS)

Belkin, M. E.

2018-01-01

The results of an experimental study for a long wavelength vertical cavity surface-emitting laser of a wafer-fused construction as an effective resonant cavity enhanced photodetector of analog optical signals are described. The device is of interest for a number of promising microwave photonics applications and for creation of a low-cost photoreceiver in a high-speed fiber optics telecommunication system with dense wavelength division multiplexing. The schematic of the testbed, the original technique allowing to calculate the passband of the built-in optical cavity, and the results of measuring dark current, current responsivity, amplitude- and phase-frequency characteristics during the process of photo-detection are demonstrated.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation

NASA Astrophysics Data System (ADS)

Jackson, Michael J.; Jackson, Biyun L.; Goorsky, Mark S.

2011-11-01

Sulfur passivation and subsequent wafer-bonding treatments are demonstrated for III-V semiconductor applications using GaAs-GaAs direct wafer-bonded structures. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native-oxide-etch treatments. The electrical conductivity across a sulfur-treated 400 - °C-bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 min) at elevated temperatures (500-600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur-treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the observed temperature dependence of zero-bias conductance using a model for tunneling through a grain boundary reveals that the addition of sulfur at the interface lowered the interfacial energy barrier by 0.2 eV. The interface resistance for these sulfur-treated structures is 0.03 Ω.cm at room temperature. These results emphasize that sulfur-passivation techniques reduce interface states that otherwise limit the implementation of wafer bonding for high-efficiency solar cells and other devices.

Output blue light evaluation for phosphor based smart white LED wafer level packages.

PubMed

Kolahdouz, Zahra; Rostamian, Ali; Kolahdouz, Mohammadreza; Ma, Teng; van Zeijl, Henk; Zhang, Kouchi

2016-02-22

This study presents a blue light detector for evaluating the output light of phosphor based white LED package. It is composed of a silicon stripe-shaped photodiode designed and implemented in a 2 μm BiCMOS process which can be used for wafer level integration of different passive and active devices all in just 5 lithography steps. The final device shows a high selectivity to blue light. The maximum responsivity at 480 nm is matched with the target blue LED illumination. The designed structure have better responsivity compared to simple photodiode structure due to reducing the effect of dead layer formation close to the surface because of implantation. It has also a two-fold increase in the responsivity and quantum efficiency compared to previously similar published sensors.

Electron beam throughput from raster to imaging

NASA Astrophysics Data System (ADS)

Zywno, Marek

2016-12-01

Two architectures of electron beam tools are presented: single beam MEBES Exara designed and built by Etec Systems for mask writing, and the Reflected E-Beam Lithography tool (REBL), designed and built by KLA-Tencor under a DARPA Agreement No. HR0011-07-9-0007. Both tools have implemented technologies not used before to achieve their goals. The MEBES X, renamed Exara for marketing purposes, used an air bearing stage running in vacuum to achieve smooth continuous scanning. The REBL used 2 dimensional imaging to distribute charge to a 4k pixel swath to achieve writing times on the order of 1 wafer per hour, scalable to throughput approaching optical projection tools. Three stage architectures were designed for continuous scanning of wafers: linear maglev, rotary maglev, and dual linear maglev.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

High dynamic range CMOS-based mammography detector for FFDM and DBT

NASA Astrophysics Data System (ADS)

Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

2016-03-01

Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

Transforming information from silicon testing and design characterization into numerical data sets for yield learning

NASA Astrophysics Data System (ADS)

Yang, Thomas; Shen, Yang; Zhang, Yifan; Sweis, Jason; Lai, Ya-Chieh

2017-03-01

Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from test result diagnostics. Product engineers will analyze the diagnostic results and perform a number of physical failure analyses to detect systematic defects which cause yield loss for these sets of wafers in order to feedback the information to process engineers for process improvements. Most of time, the systematic defects that are detected are major issues or just one of the causes for the overall yield loss. This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Solar Spectrum Photocatalytic Conversion of CO2 and Water Vapor Into Hydrocarbons Using TiO2 Nanoparticle Membranes

NASA Astrophysics Data System (ADS)

Rani, Sanju; Bao, Ningzhong; Roy, Somnath C.

2014-01-01

A viable option for recycling carbon dioxide is through the sunlight-powered photocatalytic conversion of CO2 and water vapor into hydrocarbon fuels over highly active nanocatalysts. With photocatalytic CO2 reduction sunlight, a renewable energy source as durable as the sun, is used to drive the catalytic reaction with the resultant fuel products compatible with the current hydrocarbon-based energy infrastructure. The use of co-catalyst (Cu, Pt)-sensitized TiO2 nanoparticle wafers in the photocatalytic conversion of CO2 and water vapor to hydrocarbon fuels, with optimal humidity levels and exposure times established. We also attempted to increase product formation by sputtering both co-catalysts on the nanoparticle wafer's surface, with the resulting product rates significantly higher than that of either the Cu or Pt coated samples. When the TiO2 nanoparticle wafers are used in a flow-through membrane implementation we find a significant increase in product rates of formation, including methane, hydrogen, and carbon monoxide. We believe that nanocatalyst-based flow-through membranes are a viable route for achieving large-scale and low cost photocatalytic solar fuel production.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Fourier ptychographic microscopy at telecommunication wavelengths using a femtosecond laser

NASA Astrophysics Data System (ADS)

Ahmed, Ishtiaque; Alotaibi, Maged; Skinner-Ramos, Sueli; Dominguez, Daniel; Bernussi, Ayrton A.; de Peralta, Luis Grave

2017-12-01

We report the implementation of the Fourier Ptychographic Microscopy (FPM) technique, a phase retrieval technique, at telecommunication wavelengths using a low-coherence ultrafast pulsed laser source. High quality images, near speckle-free, were obtained with the proposed approach. We demonstrate that FPM can also be used to image periodic features through a silicon wafer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-05-20

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-11-25

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Micro-scale heat-exchangers for Joule-Thomson cooling.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gross, Andrew John

2014-01-01

This project focused on developing a micro-scale counter flow heat exchangers for Joule-Thomson cooling with the potential for both chip and wafer scale integration. This project is differentiated from previous work by focusing on planar, thin film micromachining instead of bulk materials. A process will be developed for fabricating all the devices mentioned above, allowing for highly integrated micro heat exchangers. The use of thin film dielectrics provides thermal isolation, increasing efficiency of the coolers compared to designs based on bulk materials, and it will allow for wafer-scale fabrication and integration. The process is intended to implement a CFHX asmore » part of a Joule-Thomson cooling system for applications with heat loads less than 1mW. This report presents simulation results and investigation of a fabrication process for such devices.« less

Development of dual-polarization LEKIDs for CMB observations

NASA Astrophysics Data System (ADS)

McCarrick, Heather; Abitbol, Maximilian H.; Ade, Peter A. R.; Barry, Peter; Bryan, Sean; Che, George; Day, Peter; Doyle, Simon; Flanigan, Daniel; Johnson, Bradley R.; Jones, Glenn; LeDuc, Henry G.; Limon, Michele; Mauskopf, Philip; Miller, Amber; Tucker, Carole; Zmuidzinas, Jonas

2016-07-01

We discuss the design considerations and initial measurements from arrays of dual-polarization, lumped-element kinetic inductance detectors (LEKIDs) nominally designed for cosmic microwave background (CMB) studies. The detectors are horn-coupled, and each array element contains two single-polarization LEKIDs, which are made from thin-film aluminum and optimized for a single spectral band centered on 150 GHz. We are developing two array architectures, one based on 160 micron thick silicon wafers and the other based on silicon-on-insulator (SOI) wafers with a 30 micron thick device layer. The 20-element test arrays (40 LEKIDs) are characterized with both a linearly-polarized electronic millimeter wave source and a thermal source. We present initial measurements including the noise spectra, noise-equivalent temperature, and responsivity. We discuss future testing and further design optimizations to be implemented.

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

NASA Astrophysics Data System (ADS)

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Surface recombination velocity imaging of wet-cleaned silicon wafers using quantitative heterodyne lock-in carrierography

NASA Astrophysics Data System (ADS)

Sun, Qiming; Melnikov, Alexander; Mandelis, Andreas; Pagliaro, Robert H.

2018-01-01

InGaAs-camera based heterodyne lock-in carrierography (HeLIC) is developed for surface recombination velocity (SRV) imaging characterization of bare (oxide-free) hydrogen passivated Si wafer surfaces. Samples prepared using four different hydrofluoric special-solution etching conditions were tested, and a quantitative assessment of their surface quality vs. queue-time after the hydrogen passivation process was made. The data acquisition time for an SRV image was about 3 min. A "round-trip" frequency-scan mode was introduced to minimize the effects of signal transients on data self-consistency. Simultaneous best fitting of HeLIC amplitude-frequency dependencies at various queue-times was used to guarantee the reliability of resolving surface and bulk carrier recombination/transport properties. The dynamic range of the measured SRV values was established from 0.1 to 100 m/s.

Sensor-based atomic layer deposition for rapid process learning and enhanced manufacturability

NASA Astrophysics Data System (ADS)

Lei, Wei

In the search for sensor based atomic layer deposition (ALD) process to accelerate process learning and enhance manufacturability, we have explored new reactor designs and applied in-situ process sensing to W and HfO 2 ALD processes. A novel wafer scale ALD reactor, which features fast gas switching, good process sensing compatibility and significant similarity to the real manufacturing environment, is constructed. The reactor has a unique movable reactor cap design that allows two possible operation modes: (1) steady-state flow with alternating gas species; or (2) fill-and-pump-out cycling of each gas, accelerating the pump-out by lifting the cap to employ the large chamber volume as ballast. Downstream quadrupole mass spectrometry (QMS) sampling is applied for in-situ process sensing of tungsten ALD process. The QMS reveals essential surface reaction dynamics through real-time signals associated with byproduct generation as well as precursor introduction and depletion for each ALD half cycle, which are then used for process learning and optimization. More subtle interactions such as imperfect surface saturation and reactant dose interaction are also directly observed by QMS, indicating that ALD process is more complicated than the suggested layer-by-layer growth. By integrating in real-time the byproduct QMS signals over each exposure and plotting it against process cycle number, the deposition kinetics on the wafer is directly measured. For continuous ALD runs, the total integrated byproduct QMS signal in each ALD run is also linear to ALD film thickness, and therefore can be used for ALD film thickness metrology. The in-situ process sensing is also applied to HfO2 ALD process that is carried out in a furnace type ALD reactor. Precursor dose end-point control is applied to precisely control the precursor dose in each half cycle. Multiple process sensors, including quartz crystal microbalance (QCM) and QMS are used to provide real time process information. The sensing results confirm the proposed surface reaction path and once again reveal the complexity of ALD processes. The impact of this work includes: (1) It explores new ALD reactor designs which enable the implementation of in-situ process sensors for rapid process learning and enhanced manufacturability; (2) It demonstrates in the first time that in-situ QMS can reveal detailed process dynamics and film growth kinetics in wafer-scale ALD process, and thus can be used for ALD film thickness metrology. (3) Based on results from two different processes carried out in two different reactors, it is clear that ALD is a more complicated process than normally believed or advertised, but real-time observation of the operational chemistries in ALD by in-situ sensors provides critical insight to the process and the basis for more effective process control for ALD applications.

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

NASA Technical Reports Server (NTRS)

Powell, J. Anthony

2001-01-01

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2013-10-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45 nm through 14/10 nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques, such as litho-etch-litho-etch, sidewall image transfer, line/cut mask, and self-aligned structures, have been implemented to solution required device scaling. Advances in dry plasma etch process control across wafer uniformity and etch selectivity to both masking materials have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes, such as trilayer etches, aggressive critical dimension shrink techniques, and the extension of resist trim processes, have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across-design variation, defectivity, profile stability within wafer, within lot, and across tools has been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated total patterning solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. We will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2012-03-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45nm through 14/10nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques such as litho-etch-litho-etch, sidewall image transfer, line/cut mask and self-aligned structures have been implemented to solution required device scaling. Advances in dry plasma etch process control, across wafer uniformity and etch selectivity to both masking materials and have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes such as trilayer etches, aggressive CD shrink techniques, and the extension of resist trim processes have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across design variation, defectivity, profile stability within wafer, within lot, and across tools have been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated Total Patterning Solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. This paper will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Positioning performance of a maglev fine positioning system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wronosky, J.B.; Smith, T.G.; Jordan, J.D.

1996-12-01

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) research tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development experience. System enhancements, implemented on a second generation design for an ARPA National Center for Advanced Information Component Manufacturing (NCAICM) project, introduced active structural control for the levitated structure of the system. Magnetic levitation (maglev) is emerging as an important technology for wafer positioning systems in advanced lithography applications. The advantages ofmore » maglev stem from the absence of physical contact. The resulting lack of friction enables accurate, fast positioning. Maglev systems are mechanically simple, accomplishing full six degree-of-freedom suspension and control with a minimum of moving parts. Power-efficient designs, which reduce the possibility of thermal distortion of the platen, are achievable. Manufacturing throughput will be improved in future systems with the addition of active structural control of the positioning stages. This paper describes the design, implementation, and functional capability of the maglev fine positioning system. Specifics regarding performance design goals and test results are presented.« less

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Airborne chemical contamination of a chemically amplified resist

NASA Astrophysics Data System (ADS)

MacDonald, Scott A.; Clecak, Nicholas J.; Wendt, H. R.; Willson, C. Grant; Snyder, Clinton D.; Knors, C. J.; Deyoe, N. B.; Maltabes, John G.; Morrow, James R.; McGuire, Anne E.; Holmes, Steven J.

1991-06-01

We have found that the performance of the t-BOC/onium salt resist system is severely degraded by vapor from organic bases. This effect is very pronounced and can be observed when the coated wafers stand for 15 minutes in air containing as little as 15 parts per billion (ppb) of an organic base. The observed effect, caused by this chemical contamination, depends on the tone of the resist system. For negative tone systems the UV exposure dose, required to obtain the correct linewidth, increases. While for the positive tone system, one observes the generation of a skin at the resist-air interface. Both effects are caused by the photogenerated acid being neutralized by the airborne organic base. There are a wide variety of commonly used materials which can liberate trace amounts of volatile amines and degrade resist performance. For example, fresh paint on a laboratory wall can exhibit this detrimental effect. These effects can be minimized by storing and processing the resist coated wafers in air that has passed through a specially designed, high efficiency carbon filter. The implementation of localized air filtration, to bathe the resist in chemically pure air, enabled this resist system to operate in a manufacturing environment at a rate of 100 wafers/hour.

GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies.

PubMed

Yoon, Jongseung; Jo, Sungjin; Chun, Ik Su; Jung, Inhwa; Kim, Hoon-Sik; Meitl, Matthew; Menard, Etienne; Li, Xiuling; Coleman, James J; Paik, Ungyu; Rogers, John A

2010-05-20

Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices to radio-frequency electronics and most forms of optoelectronics. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.

Growth and Implementation of Carbon-Doped AlGaN Layers for Enhancement-Mode HEMTs on 200 mm Si Substrates

NASA Astrophysics Data System (ADS)

Su, Jie; Posthuma, Niels; Wellekens, Dirk; Saripalli, Yoga N.; Decoutere, Stefaan; Arif, Ronald; Papasouliotis, George D.

2016-12-01

We are reporting the growth of AlGaN based enhancement-mode high electron mobility transistors (HEMTs) on 200 mm silicon (111) substrates using a single wafer metalorganic chemical vapor deposition reactor. It is found that TMAl pre-dosing conditions are critical in controlling the structural quality, surface morphology, and wafer bow of the HEMT stack. Optimal structural quality and pit-free surface are demonstrated for AlGaN HEMTs with pre-dosing temperature at 750°C. Intrinsically, carbon-doped AlGaN, is used as the current blocking layer in the HEMT structures. The lateral buffer breakdown and device breakdown characteristics, reach 400 V at a leakage current of 1 μA/mm measured at 150°C. The fabricated HEMT devices, with a Mg doped p-GaN gate layer, are operating in enhancement mode reaching a positive threshold voltage of 2-2.5 V, a low on-resistance of 10.5 Ω mm with a high drain saturation current of 0.35 A/mm, and a low forward bias gate leakage current of 0.5 × 10-6 A/mm ( V gs = 7 V). Tight distribution of device parameters across the 200 mm wafers and over repeat process runs is observed.

Internal gas and liquid distributor for electrodeionization device

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Henry, Michael P.; Datta, Saurav

2016-05-17

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The gas and aqueous fluid are introduced into each basic wafer via a porous gas distributor which disperses the gas as micro-sized bubbles laterally throughout the distributor before entering the wafer. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme or inorganic catalyst to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Controlling aliased dynamics in motion systems? An identification for sampled-data control approach

NASA Astrophysics Data System (ADS)

Oomen, Tom

2014-07-01

Sampled-data control systems occasionally exhibit aliased resonance phenomena within the control bandwidth. The aim of this paper is to investigate the aspect of these aliased dynamics with application to a high performance industrial nano-positioning machine. This necessitates a full sampled-data control design approach, since these aliased dynamics endanger both the at-sample performance and the intersample behaviour. The proposed framework comprises both system identification and sampled-data control. In particular, the sampled-data control objective necessitates models that encompass the intersample behaviour, i.e., ideally continuous time models. Application of the proposed approach on an industrial wafer stage system provides a thorough insight and new control design guidelines for controlling aliased dynamics.

Superconducting Vacuum-Gap Crossovers for High Performance Microwave Applications

NASA Technical Reports Server (NTRS)

Denis, Kevin L.; Brown, Ari D.; Chang, Meng-Ping; Hu, Ron; U-Yen, Kongpop; Wollack, Edward J.

2016-01-01

The design and fabrication of low-loss wide-bandwidth superconducting vacuum-gap crossovers for high performance millimeter wave applications are described. In order to reduce ohmic and parasitic losses at millimeter wavelengths a vacuum gap is preferred relative to dielectric spacer. Here, vacuum-gap crossovers were realized by using a sacrificial polymer layer followed by niobium sputter deposition optimized for coating coverage over an underlying niobium signal layer. Both coplanar waveguide and microstrip crossover topologies have been explored in detail. The resulting fabrication process is compatible with a bulk micro-machining process for realizing waveguide coupled detectors, which includes sacrificial wax bonding, and wafer backside deep reactive ion etching for creation of leg isolated silicon membrane structures. Release of the vacuum gap structures along with the wax bonded wafer after DRIE is implemented in the same process step used to complete the detector fabrication. ?

Superconducting micro-resonator arrays with ideal frequency spacing

NASA Astrophysics Data System (ADS)

Liu, X.; Guo, W.; Wang, Y.; Dai, M.; Wei, L. F.; Dober, B.; McKenney, C. M.; Hilton, G. C.; Hubmayr, J.; Austermann, J. E.; Ullom, J. N.; Gao, J.; Vissers, M. R.

2017-12-01

We present a wafer trimming technique for producing superconducting micro-resonator arrays with highly uniform frequency spacing. With the light-emitting diode mapper technique demonstrated previously, we first map the measured resonance frequencies to the physical resonators. Then, we fine-tune each resonator's frequency by lithographically trimming a small length, calculated from the deviation of the measured frequency from its design value, from the interdigitated capacitor. We demonstrate this technique on a 127-resonator array made from titanium-nitride and show that the uniformity of frequency spacing is greatly improved. The array yield in terms of frequency collisions improves from 84% to 97%, while the quality factors and noise properties are unaffected. The wafer trimming technique provides an easy-to-implement tool to improve the yield and multiplexing density of large resonator arrays, which is important for various applications in photon detection and quantum computing.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Process tool monitoring and matching using interferometry technique

NASA Astrophysics Data System (ADS)

Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

Wafer-level packaging with compression-controlled seal ring bonding

DOEpatents

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Prediction of ppm level electrical failure by using physical variation analysis

NASA Astrophysics Data System (ADS)

Hou, Hsin-Ming; Kung, Ji-Fu; Hsu, Y.-B.; Yamazaki, Y.; Maruyama, Kotaro; Toyoshima, Yuya; Chen, Chu-en

2016-03-01

The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology. Each of these factors play an important role in making the process more effective by ensuring that certain design- and process-specific parameters are kept within acceptable variation. Since chip size and pattern density are increasing accordingly, in-line real time catching the in-chip weak patterns/defects per million opportunities (WP-DPMO) plays more and more significant role for product yield with high density memory. However, the current in-line inspection tools focus on single layer defect inspection, not effectively and efficiently to catch multi-layer weak patterns/defects even through voltage contrast and/or special test structure design [1]-[2]. In general, the multi-layer weak patterns/defects are escaped easily by using in-line inspection and cause ignorance of product dysfunction until off-line time-consuming final PFA/EFA will be used. To effectively and efficiently in-line real time monitor the potential multi-layer weak patterns, we quantify the bridge electrical metric between contact and gate electrodes into CD physical metric via big data from the larger field of view (FOV: 8k x 16k with 3 nm pixel equalizes to image main field size 34 um x 34 um @ 3 nm pixel) e-beam quality image contour compared to layout GDS database (D2DB) as shown in Fig. 1. Hadoop-based distributed parallel computing is implemented to improve the performance of big data architectures, Fig. 2. Therefore, the state of art in-line real time catching in-chip potential multi-layer weak patterns can be proven and achieved by following some studying cases [3]. Therefore, manufacturing sources of variations can be partitioned to systematic and random variations by applying statistical techniques based on the big data fundamental infrastructures. After big data handling, the in-chip CD and AA variations are distinguished by their spatial correlation distance. For local variations (LV) there is no correlation, whereas for global variations (GV) the correlation distance is very large [7]-[9]. This is the first time to certificate the validation of spatial distribution from the affordable bias contour big data fundamental infrastructures. And then apply statistical techniques to dig out the variation sources. The GV come from systematic issue, which could be compensated by adaptive LT condition or OPC correction. But LV comes from random issue, which being considered as intrinsic problem such as structure, material, tool capability… etc. In this paper studying, we can find out the advanced technology node SRAM contact CD local variation (LV) dominates in total variation, about 70%. It often plays significant in-line real time catching WP-DPMO role of the product yield loss, especially for wafer edge is the worst loss within wafer distribution and causes serious reliability concern. The major root cause of variations comes from the PR material induced burr defect (LV), the second one comes from GV enhanced wafer edge short opportunity, which being attributed to three factors, first one factor is wafer edge CD deliberated enlargement for yield improvement as shown in Fig. 10. Second factor is overlaps/AA shifts due to tool capability dealing with incoming wafer's war page issue and optical periphery layout dependent working pitch issue as shown in Fig. 9 (1)., the last factor comes from wafer edge burr enhanced by wafer edge larger Photo Resistance (PR) spin centrifugal force. After implementing KPIs such as GV related AA/CD indexes as shown in Fig. 9 (1) and 10, respectively, and LV related burr index as shown in Fig. 11., we can construct the parts per million (PPM) level short probability model via multi-variables regression, canonical correlation analysis and logistic transformation. The model provides prediction of PPM level electrical failure by using in-line real time physical variation analysis. However in order to achieve Total Quality Management (TQM), the adaptive Statistical Process Control (SPC) charts can be implemented to in-line real time catch PPM level product malfunction at manufacturing stage. Applying for early stage monitor likes incoming raw material, Photo Resistance (PR) … etc., the LV related burr KPI SPC charts could be a powerful quality inspection vehicle. To sum up the paper's contributions, the state of art in-line real time catching in-chip potential multi-layer physical weak patterns can be proven and achieved effectively and efficiently to associate with PPM level product dysfunction.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

NASA Technical Reports Server (NTRS)

Bartelt, Hartmut (Editor)

1990-01-01

The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

Epitaxial thinning process

NASA Technical Reports Server (NTRS)

Siegel, C. M. (Inventor)

1984-01-01

A method is described for thinning an epitaxial layer of a wafer that is to be used in producing diodes having a specified breakdown voltage and which also facilitates the thinning process. Current is passed through the epitaxial layer, by connecting a current source between the substrate of the wafer and an electrolyte in which the wafer is immersed. When the wafer is initially immersed, the voltage across the wafer initially drops and then rises at a steep rate. When light is applied to the wafer the voltage drops, and when the light is interrupted the voltage rises again. These changes in voltage, each indicate the breakdown voltage of a Schottky diode that could be prepared from the wafer at that time. The epitaxial layer is thinned by continuing to apply current through the wafer while it is immersed and light is applied, to form an oxide film and when the oxide film is thick the wafer can then be cleaned of oxide and the testing and thinning continued. Uninterrupted thinning can be achieved by first forming an oxide film, and then using an electrolyte that dissolves the oxide about as fast as it is being formed, to limit the thickness of the oxide layer.

Thin layer composite unimorph ferroelectric driver and sensor

NASA Technical Reports Server (NTRS)

Hellbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Jr., Antony (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

2004-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

NASA Technical Reports Server (NTRS)

Helbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Antony, Jr. (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

1995-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

High-performance fused indium gallium arsenide/silicon photodiode

NASA Astrophysics Data System (ADS)

Kang, Yimin

Modern long haul, high bit rate fiber-optic communication systems demand photodetectors with high sensitivity. Avalanche photodiodes (APDs) exhibit superior sensitivity performance than other types of photodetectors by virtual of its internal gain mechanism. This dissertation work further advances the APD performance by applying a novel materials integration technique. It is the first successful demonstration of wafer fused InGaAs/Si APDs with low dark current and low noise. APDs generally adopt separate absorption and multiplication (SAM) structure, which allows independent optimization of materials properties in two distinct regions. While the absorption material needs to have high absorption coefficient in the target wavelength range to achieve high quantum efficiency, it is desirable for the multiplication material to have large discrepancy between its electron and hole ionization coefficients to reduce noise. According to these criteria, InGaAs and Si are the ideal materials combination. Wafer fusion is the enabling technique that makes this theoretical ideal an experimental possibility. APDs fabricated on the fused InGaAs/Si wafer with mesa structure exhibit low dark current and low noise. Special device fabrication techniques and high quality wafer fusion reduce dark current to nano ampere level at unity gain, comparable to state-of-the-art commercial III/V APDs. The small excess noise is attributed to the large difference in ionization coefficients between electrons and holes in silicon. Detailed layer structure designs are developed specifically for fused InGaAs/Si APDs based on principles similar to those used in traditional InGaAs/InP APDs. An accurate yet straightforward technique for device structural parameters extraction is also proposed. The extracted results from the fabricated APDs agree with device design parameters. This agreement also confirms that the fusion interface has negligible effect on electric field distributions for devices fabricated from high quality fusion materials. The feasibility of fused InGaAs/Si APD for analog systems is also explored. Preliminary two-tone measurement shows that a moderately high dynamic range of 70 dBc/Hz1/2 for broadband Spur Free Dynamic Range (SFDR) or 82 dBc/Hz2/3 suboctave SFDR, up to 50 muA of optical current, can be achieved. The theoretical analyses of SNR show that fused InGaAs/Si APD receivers can provide larger Signal-to-Noise Ratio (SNR) than their III/V counterparts.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Optic probe for semiconductor characterization

DOEpatents

Sopori, Bhushan L [Denver, CO; Hambarian, Artak [Yerevan, AM

2008-09-02

Described herein is an optical probe (120) for use in characterizing surface defects in wafers, such as semiconductor wafers. The optical probe (120) detects laser light reflected from the surface (124) of the wafer (106) within various ranges of angles. Characteristics of defects in the surface (124) of the wafer (106) are determined based on the amount of reflected laser light detected in each of the ranges of angles. Additionally, a wafer characterization system (100) is described that includes the described optical probe (120).

All-optical lithography process for contacting nanometer precision donor devices

NASA Astrophysics Data System (ADS)

Ward, D. R.; Marshall, M. T.; Campbell, D. M.; Lu, T. M.; Koepke, J. C.; Scrymgeour, D. A.; Bussmann, E.; Misra, S.

2017-11-01

We describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

All-optical lithography process for contacting nanometer precision donor devices

DOE PAGES

Ward, Daniel Robert; Marshall, Michael Thomas; Campbell, DeAnna Marie; ...

2017-11-06

In this article, we describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

All-optical lithography process for contacting nanometer precision donor devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, Daniel Robert; Marshall, Michael Thomas; Campbell, DeAnna Marie

In this article, we describe an all-optical lithography process that can make electrical contact to nanometer-precision donor devices fabricated in silicon using scanning tunneling microscopy (STM). This is accomplished by implementing a cleaning procedure in the STM that allows the integration of metal alignment marks and ion-implanted contacts at the wafer level. Low-temperature transport measurements of a patterned device establish the viability of the process.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

An Update on Structural Seal Development at NASA GRC

NASA Technical Reports Server (NTRS)

Dunlap, Pat; Steinetz, Bruce; Finkbeiner, Josh; DeMange, Jeff; Taylor, Shawn; Daniels, Chris; Oswald, Jay

2006-01-01

A viewgraph presentation describing advanced structural seal development for NASA exploration is shown. The topics include: 1) GRC Structural Seals Team Research Areas; 2) Research Areas & Objective; 3) Wafer Seal Geometry/Flow Investigations; 4) Wafer Seal Installation DOE Study; 5) Results of Wafer Seal Installation DOE Study; 6) Wafer Geometry Study: Thickness Variations; 7) Wafer Geometry Study: Full-Size vs. Half-Size Wafers; 8) Spring Tube Seal Development; 9) Resiliency Improvement for Rene 41 Spring Tube; 10) Spring Tube Seals: Go-Forward Plan; 11) High Temperature Seal Preloader Development: TZM Canted Coil Spring; 12) TZM Canted Coil Spring Development; 13) Arc Jet Test Rig Development; and 14) Arc Jet Test Rig Status.

Strong emission of terahertz radiation from nanostructured Ge surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Chul; Maeng, Inhee; Kee, Chul-Sik, E-mail: cskee@gist.ac.kr

2015-06-29

Indirect band gap semiconductors are not efficient emitters of terahertz radiation. Here, we report strong emission of terahertz radiation from germanium wafers with nanostructured surfaces. The amplitude of THz radiation from an array of nano-bullets (nano-cones) is more than five (three) times larger than that from a bare-Ge wafer. The power of the terahertz radiation from a Ge wafer with an array of nano-bullets is comparable to that from n-GaAs wafers, which have been widely used as a terahertz source. We find that the THz radiation from Ge wafers with the nano-bullets is even more powerful than that from n-GaAsmore » for frequencies below 0.6 THz. Our results suggest that introducing properly designed nanostructures on indirect band gap semiconductor wafers is a simple and cheap method to improve the terahertz emission efficiency of the wafers significantly.« less

Method for nanomachining high aspect ratio structures

DOEpatents

Yun, Wenbing; Spence, John; Padmore, Howard A.; MacDowell, Alastair A.; Howells, Malcolm R.

2004-11-09

A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

1978-01-01

Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Arrangement, Dopant Source, And Method For Making Solar Cells

DOEpatents

Rohatgi, Ajeet; Krygowski, Thomas W.

1999-10-26

Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place. Finally, the cell wafers receive an anti-reflective coating and electrical contacts for the purpose of gathering electrical charge.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

PubMed

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Automatic cassette to cassette radiant impulse processor

NASA Astrophysics Data System (ADS)

Sheets, Ronald E.

1985-01-01

Single wafer rapid annealing using high temperature isothermal processing has become increasingly popular in recent years. In addition to annealing, this process is also being investigated for suicide formation, passivation, glass reflow and alloying. Regardless of the application, there is a strong necessity to automate in order to maintain process control, repeatability, cleanliness and throughput. These requirements have been carefully addressed during the design and development of the Model 180 Radiant Impulse Processor which is a totally automatic cassette to cassette wafer processing system. Process control and repeatability are maintained by a closed loop optical pyrometer system which maintains the wafer at the programmed temperature-time conditions. Programmed recipes containing up to 10 steps may be easily entered on the computer keyboard or loaded in from a recipe library stored on a standard 5 {1}/{4″} floppy disk. Cold wall heating chamber construction, controlled environment (N 2, A, forming gas) and quartz wafer carriers prevent contamination of the wafer during high temperature processing. Throughputs of 150-240 wafers per hour are achieved by quickly heating the wafer to temperature (450-1400°C) in 3-6 s with a high intensity, uniform (± 1%) radiant flux of 100 {W}/{cm 2}, parallel wafer handling system and a wafer cool down stage.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Methane production using resin-wafer electrodeionization

DOEpatents

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Misfit strain of oxygen precipitates in Czochralski silicon studied with energy-dispersive X-ray diffraction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gröschel, A., E-mail: alexander.groeschel@fau.de; Will, J.; Bergmann, C.

Annealed Czochralski Silicon wafers containing SiO{sub x} precipitates have been studied by high energy X-ray diffraction in a defocused Laue setup using a laboratory tungsten tube. The energy dispersive evaluation of the diffracted Bragg intensity of the 220 reflection within the framework of the statistical dynamical theory yields the static Debye-Waller factor E of the crystal, which gives access to the strain induced by the SiO{sub x} precipitates. The results are correlated with precipitate densities and sizes determined from transmission electron microscopy measurements of equivalent wafers. This allows for the determination of the constrained linear misfit ε between precipitate andmore » crystal lattice. For samples with octahedral precipitates the values ranging from ε = 0.39 (+0.28/−0.12) to ε = 0.48 (+0.34/−0.16) indicate that self-interstitials emitted into the matrix during precipitate growth contribute to the lattice strain. In this case, the expected value calculated from literature values is ε = 0.26 ± 0.05. Further, the precise evaluation of Pendellösung oscillations in the diffracted Bragg intensity of as-grown wafers reveals a thermal Debye-Waller parameter for the 220 reflection B{sup 220}(293 K) of 0.5582 ± 0.0039 Å{sup 2} for a structure factor based on spherically symmetric scattering contributions.« less

Improving Resonance Characteristics of Gas Sensors by Chemical Etching of Quartz Plates

NASA Astrophysics Data System (ADS)

Raicheva, Z.; Georgieva, V.; Grechnikov, A.; Gadjanova, V.; Angelov, Ts; Vergov, L.; Lazarov, Y.

2012-12-01

The paper presents the results of the influence of the etching process of AT-cut quartz plates on the resonance parameters and the QCM sensors. Quartz wafers (100 μm thick, with a diameter of 8 mm), divided into five groups, have been etched in [NH4]2 F2: H2O = 1:1 solution at temperatures in the range from 70°C to 90°C. The influence of etching temperature on the surface morphology of quartz wafers has been estimated by Atomic Force Microscopy (AFM). A correlation between the etching temperature and the dynamic characteristics is obtained. The optimal etching conditions for removing the surface damages caused by the mechanical treatment of the quartz wafers and for obtaining a clean surface were determined. The typical parameters of fabricated resonators on the quartz plates etched in the temperature range from 70°C to 90°C are as follows: Frequency, Fs 16 MHz ± 100 kHz Motional resistance, Rs less 10 Ω Motional inductance, Lq higher than 3 mH Motional capacitance, Cq less 30 fF Static capacitance, Co around 5 pF Quality factor, Q from 46 000 to 70 000 Sorption properties of QCM - MoO3 are evaluated at NH3 concentrations in the interval from 100 ppm to 500 ppm.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Dynamic Chemically Driven Dewetting, Spreading, and Self-Running of Sessile Droplets on Crystalline Silicon.

PubMed

Arscott, Steve

2016-12-06

A chemically driven dewetting effect is demonstrated using sessile droplets of dilute hydrofluoric acid on chemically oxidized silicon wafers. The dewetting occurs as the thin oxide is slowly etched by the droplet and replaced by a hydrogen-terminated surface; the result of this is a gradual increase in the contact angle of the droplet with time. The time-varying work of adhesion is calculated from the time-varying contact angle; this corresponds to the changing chemical nature of the surface during dewetting and can be modeled by the well-known logistic (sigmoid) function often used for the modeling of restricted growth, in this case, the transition from an oxidized surface to a hydrogen-terminated silicon surface. The observation of the time-varying contact angle allows one to both measure the etch rate of the silicon oxide and estimate the hydrogenation rate as a function of HF concentration and wafer type. In addition to this, at a certain HF concentration, a self-running droplet effect is observed. In contrast, on hydrogen-terminated silicon wafers, a chemically induced spreading effect is observed using sessile droplets of nitric acid. The droplet spreading can also be modeled using a logistical function, where the restricted growth is the transition from hydrogen-terminated to a chemically induced oxidized silicon surface. The chemically driven dewetting and spreading observed here add to the methods available to study dynamic wetting (e.g., the moving three-phase contact line) of sessile droplets on surfaces. By slowing down chemical kinetics of the wetting, one is able to record the changing profile of the sessile droplet with time and gather information concerning the time-varying surface chemistry. The data also indicates a chemical interface hysteresis (CIH) that is compared to contact angle hysteresis (CAH). The approach can also be used to study the chemical etching and deposition behavior of thin films using liquids by monitoring the macroscopic droplet profile and relating this to the time-varying physical and chemical interface phenomena.

A hybrid solution using computational prediction and measured data to accurately determine process corrections with reduced overlay sampling

NASA Astrophysics Data System (ADS)

Noyes, Ben F.; Mokaberi, Babak; Mandoy, Ram; Pate, Alex; Huijgen, Ralph; McBurney, Mike; Chen, Owen

2017-03-01

Reducing overlay error via an accurate APC feedback system is one of the main challenges in high volume production of the current and future nodes in the semiconductor industry. The overlay feedback system directly affects the number of dies meeting overlay specification and the number of layers requiring dedicated exposure tools through the fabrication flow. Increasing the former number and reducing the latter number is beneficial for the overall efficiency and yield of the fabrication process. An overlay feedback system requires accurate determination of the overlay error, or fingerprint, on exposed wafers in order to determine corrections to be automatically and dynamically applied to the exposure of future wafers. Since current and future nodes require correction per exposure (CPE), the resolution of the overlay fingerprint must be high enough to accommodate CPE in the overlay feedback system, or overlay control module (OCM). Determining a high resolution fingerprint from measured data requires extremely dense overlay sampling that takes a significant amount of measurement time. For static corrections this is acceptable, but in an automated dynamic correction system this method creates extreme bottlenecks for the throughput of said system as new lots have to wait until the previous lot is measured. One solution is using a less dense overlay sampling scheme and employing computationally up-sampled data to a dense fingerprint. That method uses a global fingerprint model over the entire wafer; measured localized overlay errors are therefore not always represented in its up-sampled output. This paper will discuss a hybrid system shown in Fig. 1 that combines a computationally up-sampled fingerprint with the measured data to more accurately capture the actual fingerprint, including local overlay errors. Such a hybrid system is shown to result in reduced modelled residuals while determining the fingerprint, and better on-product overlay performance.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Performance improvements of binary diffractive structures via optimization of the photolithography and dry etch processes

NASA Astrophysics Data System (ADS)

Welch, Kevin; Leonard, Jerry; Jones, Richard D.

2010-08-01

Increasingly stringent requirements on the performance of diffractive optical elements (DOEs) used in wafer scanner illumination systems are driving continuous improvements in their associated manufacturing processes. Specifically, these processes are designed to improve the output pattern uniformity of off-axis illumination systems to minimize degradation in the ultimate imaging performance of a lithographic tool. In this paper, we discuss performance improvements in both photolithographic patterning and RIE etching of fused silica diffractive optical structures. In summary, optimized photolithographic processes were developed to increase critical dimension uniformity and featuresize linearity across the substrate. The photoresist film thickness was also optimized for integration with an improved etch process. This etch process was itself optimized for pattern transfer fidelity, sidewall profile (wall angle, trench bottom flatness), and across-wafer etch depth uniformity. Improvements observed with these processes on idealized test structures (for ease of analysis) led to their implementation in product flows, with comparable increases in performance and yield on customer designs.

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

PubMed Central

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Projection x-ray topography system at 1-BM x-ray optics test beamline at the advanced photon source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stoupin, Stanislav, E-mail: sstoupin@aps.anl.gov; Liu, Zunping; Trakhtenberg, Emil

2016-07-27

Projection X-ray topography of single crystals is a classic technique for the evaluation of intrinsic crystal quality of large crystals. In this technique a crystal sample and an area detector (e.g., X-ray film) collecting intensity of a chosen crystallographic reflection are translated simultaneously across an X-ray beam collimated in the diffraction scattering plane (e.g., [1, 2]). A bending magnet beamline of a third-generation synchrotron source delivering x-ray beam with a large horizontal divergence, and therefore, a large horizontal beam size at a crystal sample position offers an opportunity to obtain X-ray topographs of large crystalline samples (e.g., 6-inch wafers) inmore » just a few exposures. Here we report projection X-ray topography system implemented recently at 1-BM beamline of the Advanced Photon Source. A selected X-ray topograph of a 6-inch wafer of 4H-SiC illustrates capabilities and limitations of the technique.« less

Distributed feedback interband cascade lasers with top grating and corrugated sidewalls

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, Feng; Stocker, Michael; Pham, John

Distributed feedback (DFB) interband cascade lasers (ICLs) with a 1st order top surface grating were designed and fabricated. Partially corrugated sidewalls were implemented to suppress high order lateral modes. The DFB ICLs have 4 mm long and 4.5 mu m wide ridge waveguides and are mounted epi-up on AlN submounts. We demonstrated a continuous-wave (CW) DFB ICL, from a first wafer which has a large detuning of the gain peak from the DFB wavelength, with a side mode suppression ratio of 30 dB. With proper matching of grating feedback and the gain peak wavelength for the second wafer, a DFBmore » ICL was demonstrated with a maximum CW output power and a maximum wall plug efficiency reaching 42 mW and 2%, respectively, at 25 degrees C. The lasing wavelengths of both lasers are around 3.3 mu m at 25 degrees C. Published by AIP Publishing.« less

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE PAGES

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

2016-07-04

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Wafer-scale Thermodynamically Stable GaN Nanorods via Two-Step Self-Limiting Epitaxy for Optoelectronic Applications

NASA Astrophysics Data System (ADS)

Kum, Hyun; Seong, Han-Kyu; Lim, Wantae; Chun, Daemyung; Kim, Young-Il; Park, Youngsoo; Yoo, Geonwook

2017-01-01

We present a method of epitaxially growing thermodynamically stable gallium nitride (GaN) nanorods via metal-organic chemical vapor deposition (MOCVD) by invoking a two-step self-limited growth (TSSLG) mechanism. This allows for growth of nanorods with excellent geometrical uniformity with no visible extended defects over a 100 mm sapphire (Al2O3) wafer. An ex-situ study of the growth morphology as a function of growth time for the two self-limiting steps elucidate the growth dynamics, which show that formation of an Ehrlich-Schwoebel barrier and preferential growth in the c-plane direction governs the growth process. This process allows monolithic formation of dimensionally uniform nanowires on templates with varying filling matrix patterns for a variety of novel electronic and optoelectronic applications. A color tunable phosphor-free white light LED with a coaxial architecture is fabricated as a demonstration of the applicability of these nanorods grown by TSSLG.

Liquid crystal uncooled thermal imager development

NASA Astrophysics Data System (ADS)

Clark, H. R.; Bozler, C. O.; Berry, S. R.; Reich, R. K.; Bos, P. J.; Finnemeyer, V. A.; Bryant, D. R.; McGinty, C.

2016-09-01

An uncooled thermal imager is being developed based on a liquid crystal (LC) transducer. Without any electrical connections, the LC transducer pixels change the long-wavelength infrared (LWIR) scene directly into a visible image as opposed to an electric signal in microbolometers. The objectives are to develop an imager technology scalable to large formats (tens of megapixels) while maintaining or improving the noise equivalent temperature difference (NETD) compared to microbolometers. The present work is demonstrating that the LCs have the required performance (sensitivity, dynamic range, speed, etc.) to enable a more flexible uncooled imager. Utilizing 200-mm wafers, a process has been developed and arrays have been fabricated using aligned LCs confined in 20×20-μm cavities elevated on thermal legs. Detectors have been successfully fabricated on both silicon and fused silica wafers using less than 10 photolithographic mask steps. A breadboard camera system has been assembled to test the imagers. Various sensor configurations are described along with advantages and disadvantages of component arrangements.

Effects of a chirped bias voltage on ion energy distributions in inductively coupled plasma reactors

NASA Astrophysics Data System (ADS)

Lanham, Steven J.; Kushner, Mark J.

2017-08-01

The metrics for controlling reactive fluxes to wafers for microelectronics processing are becoming more stringent as feature sizes continue to shrink. Recent strategies for controlling ion energy distributions to the wafer involve using several different frequencies and/or pulsed powers. Although effective, these strategies are often costly or present challenges in impedance matching. With the advent of matching schemes for wide band amplifiers, other strategies to customize ion energy distributions become available. In this paper, we discuss results from a computational investigation of biasing substrates using chirped frequencies in high density, electronegative inductively coupled plasmas. Depending on the frequency range and chirp duration, the resulting ion energy distributions exhibit components sampled from the entire frequency range. However, the chirping process also produces transient shifts in the self-generated dc bias due to the reapportionment of displacement and conduction with frequency to balance the current in the system. The dynamics of the dc bias can also be leveraged towards customizing ion energy distributions.

Guided growth of horizontal GaN nanowires on quartz and their transfer to other substrates.

PubMed

Goren-Ruck, Lior; Tsivion, David; Schvartzman, Mark; Popovitz-Biro, Ronit; Joselevich, Ernesto

2014-03-25

The guided growth of horizontal nanowires has so far been demonstrated on a limited number of substrates. In most cases, the nanowires are covalently bonded to the substrate where they grow and cannot be transferred to other substrates. Here we demonstrate the guided growth of well-aligned horizontal GaN nanowires on quartz and their subsequent transfer to silicon wafers by selective etching of the quartz while maintaining their alignment. The guided growth was observed on different planes of quartz with varying degrees of alignment. We characterized the crystallographic orientations of the nanowires and proposed a new mechanism of "dynamic graphoepitaxy" for their guided growth on quartz. The transfer of the guided nanowires enabled the fabrication of back-gated field-effect transistors from aligned nanowire arrays on oxidized silicon wafers and the production of crossbar arrays. The guided growth of transferrable nanowires opens up the possibility of massively parallel integration of nanowires into functional systems on virtually any desired substrate.

An Evaluation of High Temperature Airframe Seals for Advanced Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

DeMange, Jeffrey J.; Dunlap, Patrick H.; Steinetz, Bruce M.; Drlik, Gary J.

2007-01-01

High temperature seals are required for advanced hypersonic airframe applications. In this study, both spring tube thermal barriers and innovative wafer seal systems were evaluated under relevant hypersonic test conditions (temperatures, pressures, etc.) via high temperature compression testing and room temperature flow assessments. Thermal barriers composed of a Rene 41 spring tube filled with Saffil insulation and overbraided with a Nextel 312 sheath showed acceptable performance at 1500 F in both short term and longer term compression testing. Nextel 440 thermal barriers with Rene 41 spring tubes and Saffil insulation demonstrated good compression performance up to 1750 F. A silicon nitride wafer seal/compression spring system displayed excellent load performance at temperatures as high as 2200 F and exhibited room temperature leakage values that were only 1/3 those for the spring tube rope seals. For all seal candidates evaluated, no significant degradation in leakage resistance was noted after high temperature compression testing. In addition to these tests, a superalloy seal suitable for dynamic seal applications was optimized through finite element techniques.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

PubMed

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

NASA Astrophysics Data System (ADS)

Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

2018-03-01

We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

PubMed Central

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

Ileostomy - changing your pouch

MedlinePlus

... it right away. If you have a pouch system made of 2 pieces (a pouch and a wafer) you ... pouch and barrier or wafer (wafers are part of a 2-piece pouch system). Use a stoma guide with different sizes and ...

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, D.C.; Fox, R.J.

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semi-conductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, Dimitrios C.; Fox, Richard J.

1981-01-01

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semiconductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

NASA Astrophysics Data System (ADS)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

Advanced manufacturing rules check (MRC) for fully automated assessment of complex reticle designs

NASA Astrophysics Data System (ADS)

Gladhill, R.; Aguilar, D.; Buck, P. D.; Dawkins, D.; Nolke, S.; Riddick, J.; Straub, J. A.

2005-11-01

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization and qualification.

Enhancing crystalline silicon solar cell efficiency with SixGe1-x layers

NASA Astrophysics Data System (ADS)

Ali, Adnan; Cheow, S. L.; Azhari, A. W.; Sopian, K.; Zaidi, Saleem H.

Crystalline silicon (c-Si) solar cell represents a cost effective, environment-friendly, and proven renewable energy resource. Industrially manufacturing of c-Si solar has now matured in terms of efficiency and cost. Continuing cost-effective efficiency enhancement requires transition towards thinner wafers in near term and thin-films in the long term. Successful implementation of either of these alternatives must address intrinsic optical absorption limitation of Si. Bandgap engineering through integration with SixGe1-x layers offers an attractive, inexpensive option. With the help of PC1D software, role of SixGe1-x layers in conventional c-Si solar cells has been intensively investigated in both wafer and thin film configurations by varying Ge concentration, thickness, and placement. In wafer configuration, increase in Ge concentration leads to enhanced absorption through bandgap broadening with an efficiency enhancement of 8% for Ge concentrations of less than 20%. At higher Ge concentrations, despite enhanced optical absorption, efficiency is reduced due to substantial lowering of open-circuit voltage. In 5-25-μm thickness, thin-film solar cell configurations, efficiency gain in excess of 30% is achievable. Therefore, SixGe1-x based thin-film solar cells with an order of magnitude reduction in costly Si material are ideally-suited both in terms of high efficiency and cost. Recent research has demonstrated significant improvement in epitaxially grown SixGe1-x layers on nanostructured Si substrates, thereby enhancing potential of this approach for next generation of c-Si based photovoltaics.

Serial Section Scanning Electron Microscopy (S3EM) on Silicon Wafers for Ultra-Structural Volume Imaging of Cells and Tissues

PubMed Central

Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

2012-01-01

High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S3EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation. PMID:22523574

Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

PubMed

Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

2012-01-01

High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

Steel bridge fatigue crack detection with piezoelectric wafer active sensors

NASA Astrophysics Data System (ADS)

Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

2010-04-01

Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2001-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2001-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discemible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2000-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Stevenson, Joel O'Don; Ward, Pamela Peardon Denise

2002-07-16

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Detection and characterization of microdefects and microprecipitates in Si wafers by Brewster angle illumination using an optical fiber system

NASA Astrophysics Data System (ADS)

Taijing, Lu; Toyoda, Koichi; Nango, Nobuhito; Ogawa, Tomoya

1991-10-01

Microdefects and microprecipitates were non-destructively detected in bulk and near surface of a Si wafer by Brewster angle illumination using an optical fiber system, because the p-component of the illumination enters completely into the wafer and then makes scattering from the defects while the other s-component reflects on the wafer surface so as to deviate from an objective lens for the detection of the scattering. Some results of observations and discussions will be done here about the scatterers in epitaxially grown Si layers, denuded zones of Si wafers, annealed amorphous SiC films, SIMOX specimens and slip bands in Si crystals.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Residual Stress and Fracture of PECVD Thick Oxide Films for Power MEMS Structures and Devices

DTIC Science & Technology

2007-06-01

Residual stress leads to large overall wafer bow, which makes further processing difficult. For example some microfabrication machines , such as chemical...curvature will be measured across the wafer surface in 12 scans, rotating 24 the wafer by 300 between each scan. In situ wafer curvature will be...SiOx. 4.1. Introduction As introduced earlier (Sec.1), in Power MEMS (micro energy- harvesting devices such as micro heat engines and related components

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Precision of a CAD/CAM-engineered surgical template based on a facebow for orthognathic surgery: an experiment with a rapid prototyping maxillary model.

PubMed

Lee, Jae-Won; Lim, Se-Ho; Kim, Moon-Key; Kang, Sang-Hoon

2015-12-01

We examined the precision of a computer-aided design/computer-aided manufacturing-engineered, manufactured, facebow-based surgical guide template (facebow wafer) by comparing it with a bite splint-type orthognathic computer-aided design/computer-aided manufacturing-engineered surgical guide template (bite wafer). We used 24 rapid prototyping (RP) models of the craniofacial skeleton with maxillary deformities. Twelve RP models each were used for the facebow wafer group and the bite wafer group (experimental group). Experimental maxillary orthognathic surgery was performed on the RP models of both groups. Errors were evaluated through comparisons with surgical simulations. We measured the minimum distances from 3 planes of reference to determine the vertical, lateral, and anteroposterior errors at specific measurement points. The measured errors were compared between experimental groups using a t test. There were significant intergroup differences in the lateral error when we compared the absolute values of the 3-D linear distance, as well as vertical, lateral, and anteroposterior errors between experimental groups. The bite wafer method exhibited little lateral error overall and little error in the anterior tooth region. The facebow wafer method exhibited very little vertical error in the posterior molar region. The clinical precision of the facebow wafer method did not significantly exceed that of the bite wafer method. Copyright © 2015 Elsevier Inc. All rights reserved.

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Dynamic Curvature and Stress Studies for MBE CdTe on Si and GaAs Substrates

NASA Astrophysics Data System (ADS)

Jacobs, R. N.; Jaime Vasquez, M.; Lennon, C. M.; Nozaki, C.; Almeida, L. A.; Pellegrino, J.; Arias, J.; Taylor, C.; Wissman, B.

2015-09-01

Infrared focal plane arrays (IRFPA) based on HgCdTe semiconductor alloys have been shown to be ideal for tactical and strategic applications. High density (>1 M pixel), high operability HgCdTe detectors on large area, low-cost composite substrates, such as CdTe-buffered Si or GaAs, are envisioned for next-generation IRFPAs. Thermal expansion mismatch is among various material parameters that govern the structural properties of the final detector layer. It has previously been shown that thermal expansion mismatch plays the dominant role in the residual stress characteristics of these heteroepitaxial structures (Jacobs et al. in J Electron Mater 37:1480, 2008). The wafer curvature (bowing) resulting from residual stress, is a likely source of problems that may occur during subsequent processing. This includes cracking of the film and substrate during post-growth annealing processes or even certain characterization techniques. In this work, we examine dynamic curvature and stress during molecular beam epitaxy (MBE), of CdTe on Si and GaAs substrates. The effect of temperature changes on wafer curvature throughout the growth sequence is documented using a multi-beam optical sensor developed by K-Space Associates. This monitoring technique makes possible the study of growth sequences which employ annealing schemes and/or interlayers to influence the final residual stress state of the heteroepitaxial structures.

Static/dynamic trade-off performance of PZT thick film micro-actuators

NASA Astrophysics Data System (ADS)

Bienaimé, Alex; Chalvet, Vincent; Clévy, Cédric; Gauthier-Manuel, Ludovic; Baron, Thomas; Rakotondrabe, Micky

2015-07-01

Piezoelectric actuators are widespread in the design of micro/nanorobotic tools and microsystems. Studies toward the integration of such actuators in complex micromechatronic systems require the size reduction of these actuators while retaining a wide range of performance. Two main fabrication processes are currently used for the fabrication of piezoelectric actuators, providing very different behaviors: (i) the use of a bulk lead zirconate titanate (PZT) layer and (ii) the use of thin film growth. In this paper, we propose a trade-off between these two extreme processes and technologies in order to explore the performance of new actuators. This resulted in the design and fabrication of thick film PZT unimorph cantilevers. They allowed a high level of performance, both in the static (displacement) and dynamic (first resonance frequency) regimes, in addition to being small in size. Such cantilever sizes are obtained through the wafer scale bonding and thinning of a PZT plate onto a silicon on insulator wafer. The piezoelectric cantilevers have a 26 μm thick PZT layer with a 5 μm thick silicon layer, over a length of 4 mm and a width of 150 μm. Experimental characterization has shown that the static displacements obtained are in excess of 4.8 μm V-1 and the resonance frequencies are up to 1103 Hz, which are useful for large displacements and low voltage actuators.

In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

NASA Astrophysics Data System (ADS)

Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

2015-09-01

In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

The opportunity and challenge of spin coat based nanoimprint lithography

NASA Astrophysics Data System (ADS)

Jung, Wooyung; Cho, Jungbin; Choi, Eunhyuk; Lim, Yonghyun; Bok, Cheolkyu; Tsuji, Masatoshi; Kobayashi, Kei; Kono, Takuya; Nakasugi, Tetsuro

2017-03-01

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Applications of β-limit dextrin as a matrix forming excipient for fast disintegrating buccal dosage formats.

PubMed

Qi, Xin; Tester, Richard; Liu, Yu; Mullin, Margaret

2012-01-01

To compare the properties of buccal delivery matrices (wafers) made with dextrin, β-limit dextrin and pre-gelatinised starch. The constituent α-glucans were tested for their mucoadhesive properties in solution plus their content of crystalline material (differential scanning calorimetry, DSC). Wafers were made by lyophilisation of aqueous solutions/dispersions of the α-glucans. Physical properties of the wafers were evaluated using texture analysis, dissolution coupled to photography and scanning electron microscopy (SEM). The results highlighted how the β-limit dextrins chemical and physical properties were ideally suited for the production of buccal delivery wafers. Dissolution testing confirmed the excellent hydration profile of the β-limit dextrin (within wafers) with time. Using SEM it was evident that the homogeneous "bee-hive" like structure of the β-limit dextrin wafers, unlike the other α-glucans, provided a rapidly hydratable strong porous matrix. The β-limit dextrin α-glucan makes a superb (lyophilised) mucoadhesive delivery structure for the delivery of active agents to the buccal mucosa.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2002-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2000-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

MOCVD process technology for affordable, high-yield, high-performance MESFET structures. Phase 3: MIMIC

NASA Astrophysics Data System (ADS)

1993-01-01

Under the MIMIC Program, Spire has pursued improvements in the manufacturing of low cost, high quality gallium arsenide MOCVD wafers for advanced MIMIC FET applications. As a demonstration of such improvements, Spire was tasked to supply MOCVD wafers for comparison to MBE wafers in the fabrication of millimeter and microwave integrated circuits. In this, the final technical report for Spire's two-year MIMIC contract, we report the results of our work. The main objectives of Spire's MIMIC Phase 3 Program, as outlined in the Statement of Work, were as follows: Optimize the MOCVD growth conditions for the best possible electrical and morphological gallium arsenide. Optimization should include substrate and source qualification as well as determination of the optimum reactor growth conditions; Perform all work on 75 millimeter diameter wafers, using a reactor capable of at least three wafers per run; and Evaluate epitaxial layers using electrical, optical, and morphological tests to obtain thickness, carrier concentration, and mobility data across wafers.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

NASA Astrophysics Data System (ADS)

Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

2003-07-01

In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

United States Air Force High School Apprenticeship Program. 1990 Program Management Report. Volume 3

DTIC Science & Technology

1991-04-18

User Guide Shelly Knupp 73 Computer-Aided Design (CAD) Area Christopher O’Dell 74 Electron Beam Lithography Suzette Yu 68 Flight Dynamics Laboratory 75...fabrication. I Mr. Ed Davis, for the background knowledge of device processes and I information on electron beam lithography . Captain Mike Cheney, for...researcher may write gates on to the wafer by a process called lithography . This is the most crucial and complex part of the process. Two types of proven

Array automated assembly, phase 2

NASA Technical Reports Server (NTRS)

Taylor, W. E.

1978-01-01

An analysis was made of cost tradeoffs for shaping modified square wafers from cylindrical crystals. Tests were conducted of the effectiveness of texture etching for removal of surface damage on sawed wafers. A single step texturing etch appeared adequate for removal of surface damage on wafers cut with multiple blade reciprocating slurry saws.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Wafer chamber having a gas curtain for extreme-UV lithography

DOEpatents

Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

2001-01-01

An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

Heterogeneously integrated microsystem-on-a-chip

DOEpatents

Chanchani, Rajen [Albuquerque, NM

2008-02-26

A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Vertical and lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Okuno, Yae L.; Bowers, John E.; Jayaraman, Vijay

2001-09-01

A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Overlay improvements using a real time machine learning algorithm

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Kubis, Michael; Henke, Wolfgang; Slotboom, Daan; Hoogenboom, Tom; Mulkens, Jan; Coogans, Martyn; ten Berge, Peter; Verkleij, Dick; van de Mast, Frank

2014-04-01

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

PubMed

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Surface quality of silicon wafer improved by hydrodynamic effect polishing

NASA Astrophysics Data System (ADS)

Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

2014-08-01

Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

Large-Format HgCdTe Dual-Band Long-Wavelength Infrared Focal-Plane Arrays

NASA Astrophysics Data System (ADS)

Smith, E. P. G.; Venzor, G. M.; Gallagher, A. M.; Reddy, M.; Peterson, J. M.; Lofgreen, D. D.; Randolph, J. E.

2011-08-01

Raytheon Vision Systems (RVS) continues to further its capability to deliver state-of-the-art high-performance, large-format, HgCdTe focal-plane arrays (FPAs) for dual-band long-wavelength infrared (L/LWIR) detection. Specific improvements have recently been implemented at RVS in molecular-beam epitaxy (MBE) growth and wafer fabrication and are reported in this paper. The aim of the improvements is to establish producible processes for 512 × 512 30- μm-unit-cell L/LWIR FPAs, which has resulted in: the growth of triple-layer heterojunction (TLHJ) HgCdTe back-to-back photodiode detector designs on 6 cm × 6 cm CdZnTe substrates with 300-K Fourier-transform infrared (FTIR) cutoff wavelength uniformity of ±0.1 μm across the entire wafer; demonstration of detector dark-current performance for the longer-wavelength detector band approaching that of single-color liquid-phase epitaxy (LPE) LWIR detectors; and uniform, high-operability, 512 × 512 30- μm-unit-cell FPA performance in both LWIR bands.

Phosphorus Diffusion Gettering Efficacy in Upgraded Metallurgical-Grade Solar Silicon

NASA Astrophysics Data System (ADS)

Jiménez, A.; del Cañizo, C.; Cid, C.; Peral, A.

2018-05-01

In the context of the continuous price reduction in photovoltaics (PV) in recent years, Si feedstock continues to be a relevant component in the cost breakdown of a PV module, highlighting the need for low-cost, low-capital expenditure (CAPEX) silicon technologies to further reduce this cost component. Upgraded metallurgical-grade silicon (UMG Si) has recently received much attention, improving its quality and even attaining, in some cases, solar cell efficiencies similar to those of conventional material. However, some technical challenges still have to be addressed when processing this material to compensate efficiently for the high content of impurities and contaminants. Adaptation of a conventional solar cell process to monocrystalline UMG Si wafers has been studied in this work. In particular, a tailored phosphorus diffusion gettering step followed by a low-temperature anneal at 700°C was implemented, resulting in enhanced bulk lifetime and emitter recombination properties. In spite of the need for further research and material optimization, UMG Si wafers were successfully processed, achieving efficiencies in the range of 15% for a standard laboratory solar cell process with aluminum back surface field.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Excitation condition analysis of guided wave on PFA tubes for ultrasonic flow meter.

PubMed

Li, Xuan; Xiao, Xufeng; Cao, Li

2016-12-01

Impurity accumulation, which decreases the accuracy of flow measurement, is a critical problem when applying Z-shaped or U-shaped ultrasonic flow meters on straight PFA tubes. It can be expected that the guided wave can be used to implement flow measurement on straight PFA tubes. In this paper, the propagation of guided wave is explained by finite element simulations for the flow meter design. Conditions of guided wave generation, including the excitation frequency and the wedge structure, are studied in the simulations. The wedge is designed as a cone which is friendly to be manufactured and installed. The cone angle, the piezoelectric wafer's resonant frequency and the vibration directions are studied in the simulations. The simulations shows that the propagation of guided wave in thin PFA tubes is influenced by the piezoelectric wafers' resonant frequency and the vibration direction when the mode is on the 'water line'. Based on the results of the simulations, an experiment is conducted to verify the principles of excitation conditions, which performs flow measurement on a straight PFA tube well. Copyright © 2016 Elsevier B.V. All rights reserved.

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

Investigation of hyper-NA scanner emulation for photomask CDU performance

NASA Astrophysics Data System (ADS)

Poortinga, Eric; Scheruebl, Thomas; Conley, Will; Sundermann, Frank

2007-02-01

As the semiconductor industry moves toward immersion lithography using numerical apertures above 1.0 the quality of the photomask becomes even more crucial. Photomask specifications are driven by the critical dimension (CD) metrology within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately, tolerances of device electrical properties drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process, and photomask quality. Tightening of photomask specifications is one mechanism for meeting the wafer CD targets. The challenge lies in determining how photomask level metrology results influence wafer level imaging performance. Can it be inferred that photomask level CD performance is the direct contributor to wafer level CD performance? With respect to phase shift masks, criteria such as phase and transmission control are generally tightened with each technology node. Are there other photomask relevant influences that effect wafer CD performance? A comprehensive study is presented supporting the use of scanner emulation based photomask CD metrology to predict wafer level within chip CD uniformity (CDU). Using scanner emulation with the photomask can provide more accurate wafer level prediction because it inherently includes all contributors to image formation related to the 3D topography such as the physical CD, phase, transmission, sidewall angle, surface roughness, and other material properties. Emulated images from different photomask types were captured to provide CD values across chip. Emulated scanner image measurements were completed using an AIMS TM45-193i with its hyper-NA, through-pellicle data acquisition capability including the Global CDU Map TM software option for AIMS TM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CDU data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using scanner emulation based photomask CD metrology.

Advanced overlay: sampling and modeling for optimized run-to-run control

NASA Astrophysics Data System (ADS)

Subramany, Lokesh; Chung, WoongJae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Gutjahr, Karsten; Park, DongSuk; Snow, Patrick; Garcia-Medina, Miguel; Yap, Lipkong; Demirer, Onur Nihat; Pierson, Bill; Robinson, John C.

2016-03-01

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the "sample plan" of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Method of Fabricating Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

NASA Technical Reports Server (NTRS)

Choi, Sang Hyouk (Inventor); Park, Yeonjoon (Inventor)

2017-01-01

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Choi, Sang Hyouk (Inventor)

2016-01-01

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Wafer characteristics via reflectometry

DOEpatents

Sopori, Bhushan L.

2010-10-19

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

1984-01-01

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

Multivariable control of a rapid thermal processor using ultrasonic sensors

NASA Astrophysics Data System (ADS)

Dankoski, Paul C. P.

The semiconductor manufacturing industry faces the need for tighter control of thermal budget and process variations as circuit feature sizes decrease. Strategies to meet this need include supervisory control, run-to-run control, and real-time feedback control. Typically, the level of control chosen depends upon the actuation and sensing available. Rapid Thermal Processing (RTP) is one step of the manufacturing cycle requiring precise temperature control and hence real-time feedback control. At the outset of this research, the primary ingredient lacking from in-situ RTP temperature control was a suitable sensor. This research looks at an alternative to the traditional approach of pyrometry, which is limited by the unknown and possibly time-varying wafer emissivity. The technique is based upon the temperature dependence of the propagation time of an acoustic wave in the wafer. The aim of this thesis is to evaluate the ultrasonic sensors as a potentially viable sensor for control in RTP. To do this, an experimental implementation was developed at the Center for Integrated Systems. Because of the difficulty in applying a known temperature standard in an RTP environment, calibration to absolute temperature is nontrivial. Given reference propagation delays, multivariable model-based feedback control is applied to the system. The modelling and implementation details are described. The control techniques have been applied to a number of research processes including rapid thermal annealing and rapid thermal crystallization of thin silicon films on quartz/glass substrates.

Outcome of patients affected by newly diagnosed glioblastoma undergoing surgery assisted by 5-aminolevulinic acid guided resection followed by BCNU wafers implantation: a 3-year follow-up.

PubMed

Della Puppa, Alessandro; Lombardi, Giuseppe; Rossetto, Marta; Rustemi, Oriela; Berti, Franco; Cecchin, Diego; Gardiman, Marina Paola; Rolma, Giuseppe; Persano, Luca; Zagonel, Vittorina; Scienza, Renato

2017-01-01

The purpose of the study was to evaluate the clinical outcome of the association of BCNU wafers implantation and 5-aminolevulinic acid (5-ALA) fluorescence in the treatment of patients with newly diagnosed glioblastoma (ndGBM). Clinical and surgical data from patients who underwent 5-ALA surgery followed by BCNU wafers implantation were retrospectively evaluated (20 patients, Group I) and compared with data of patients undergoing surgery with BCNU wafers alone (42 patients, Group II) and 5-ALA alone (59 patients, Group III). Patients undergoing 5-ALA assisted resection followed by BCNU wafers implantation (Group I) resulted long survivors (>3 years) in 15 % of cases and showed a median PFS and MS of 11 and 22 months, respectively. Patients treated with BCNU wafers presented a significantly higher survival when tumor was removed with the assistance of 5-ALA (22 months with vs 18 months without 5-ALA, p < 0.0001); these data could be partially explained by the significantly higher CRET achieved in patients operated with 5-ALA assistance (80 % with vs 47 %% without 5-ALA). Moreover, patients of Group I showed a significant increased survival compared with Group III (5-ALA without BCNU) (22 months with vs 21 months without BCNU wafers, p = 0.0025) even with a comparable CRET (80 % vs 76 %, respectively). The occurrence of adverse events related to wafers did not significantly increase with 5-ALA (20 % with and 19 % without 5-ALA) and did not impact in survival outcome. In conclusion, our experience shows that on selected ndGBM patients 5-ALA technology and BCNU wafers implantation show a synergic action on patients' outcome without increasing adverse events occurrence.

ArF scanner performance improvement by using track integrated CD optimization

NASA Astrophysics Data System (ADS)

Huang, Jacky; Yu, Shinn-Sheng; Ke, Chih-Ming; Wu, Timothy; Wang, Yu-Hsi; Gau, Tsai-Sheng; Wang, Dennis; Li, Allen; Yang, Wenge; Kaoru, Araki

2006-03-01

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Planning for the semiconductor manufacturer of the future

NASA Technical Reports Server (NTRS)

Fargher, Hugh E.; Smith, Richard A.

1992-01-01

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

Evaluating diffraction-based overlay

NASA Astrophysics Data System (ADS)

Li, Jie; Tan, Asher; Jung, JinWoo; Goelzer, Gary; Smith, Nigel; Hu, Jiangtao; Ham, Boo-Hyun; Kwak, Min-Cheol; Kim, Cheol-Hong; Nam, Suk-Woo

2012-03-01

We evaluate diffraction-based overlay (DBO) metrology using two test wafers. The test wafers have different film stacks designed to test the quality of DBO data under a range of film conditions. We present DBO results using traditional empirical approach (eDBO). eDBO relies on linear response of the reflectance with respect to the overlay displacement within a small range. It requires specially designed targets that consist of multiple pads with programmed shifts. It offers convenience of quick recipe setup since there is no need to establish a model. We measure five DBO targets designed with different pitches and programmed shifts. The correlations of five eDBO targets and the correlation of eDBO to image-based overlay are excellent. The targets of 800nm and 600nm pitches have better dynamic precision than targets of 400nm pitch, which agrees with simulated results on signal/noise ratio. 3σ of less than 0.1nm is achieved for both wafers using the best configured targets. We further investigate the linearity assumption of eDBO algorithm. Simulation results indicate that as the pitch of DBO targets gets smaller, the nonlinearity error, i.e., the error in the overlay measurement results caused by deviation from ideal linear response, becomes bigger. We propose a nonlinearity correction (NLC) by including higher order terms in the optical response. The new algorithm with NLC improves measurement consistency for DBO targets of same pitch but different programmed shift, due to improved accuracy. The results from targets with different pitches, however, are improved marginally, indicating the presence of other error sources.

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Sulfur passivation techniques for III-V wafer bonding

NASA Astrophysics Data System (ADS)

Jackson, Michael James

The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the observed temperature dependence of zero bias conductance using a model for tunneling through a grain boundary reveals that the addition of sulfur at the interface lowered the interfacial energy barrier by 0.2 eV. The interface resistance for these sulfur-treated structures is less than 0.03 O·cm 2 at room temperature. These results emphasize that sulfur passivation techniques reduce interface states that otherwise limit the implementation of wafer bonding for high efficiency solar cells and other devices.

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Measurement and thermal modeling of sapphire substrate temperature at III-Nitride MOVPE conditions

DOE PAGES

Creighton, J. Randall; Coltrin, Michael E.; Figiel, Jeffrey J.

2017-04-01

Here, growth rates and alloy composition of AlGaN grown by MOVPE is often very temperature dependent due to the presence of gas-phase parasitic chemical processes. These processes make wafer temperature measurement highly important, but in fact such measurements are very difficult because of substrate transparency in the near- IR (~900 nm) where conventional pyrometers detect radiation. The transparency problem can be solved by using a mid-IR pyrometer operating at a wavelength (~7500 nm) where sapphire is opaque. We employ a mid- IR pyrometer to measure the sapphire wafer temperature and simultaneously a near-IR pyrometer to measure wafer pocket temperature, whilemore » varying reactor pressure in both a N 2 and H 2 ambient. Near 1300 °C, as the reactor pressure is lowered from 300 Torr to 10 Torr the wafer temperature drops dramatically, and the ΔT between the pocket and wafer increases from ~20 °C to ~250 °C. Without the mid-IR pyrometer the large wafer temperature change with pressure would not have been noted. In order to explain this behavior we have developed a quasi-2D thermal model that includes a proper accounting of the pressure-dependent thermal contact resistance, and also accounts for sapphire optical transmission. The model and experimental results demonstrate that at most growth conditions the majority of the heat is transported from the wafer pocket to the wafer via gas conduction, in the free molecular flow limit. In this limit gas conductivity is independent of gap size but first order in pressure, and can quantitatively explain results from 20 to 300 Torr. Further analysis yields a measure of the thermal accommodation coefficients; α(H 2) =0.23, α(N 2) =0.50, which are in the range typically measured.« less

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

NASA Astrophysics Data System (ADS)

Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

2015-03-01

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

MiRNA-181d Expression Significantly Affects Treatment Responses to Carmustine Wafer Implantation.

PubMed

Sippl, Christoph; Ketter, Ralf; Bohr, Lisa; Kim, Yoo Jin; List, Markus; Oertel, Joachim; Urbschat, Steffi

2018-05-26

Standard therapeutic protocols for glioblastoma, the most aggressive type of brain cancer, include surgery followed by chemoradiotherapy. Additionally, carmustine-eluting wafers can be implanted locally into the resection cavity. To evaluate microRNA (miRNA)-181d as a prognostic marker of responses to carmustine wafer implantation. A total of 80 glioblastoma patients (40/group) were included in a matched pair analysis. One group (carmustine wafer group) received concomitant chemoradiotherapy with carmustine wafer implantation (Stupp protocol). The second group (control group) received only concomitant chemoradiotherapy. All tumor specimens were subjected to evaluations of miRNA-181d expression, results were correlated with further individual clinical data. The Cancer Genome Atlas (TCGA) dataset of 149 patients was used as an independent cohort to validate the results. Patients in the carmustine wafer group with low miRNA-181d expression had significantly longer overall (hazard ratio [HR], 35.03, [95% confidence interval (CI): 3.50-350.23], P = .002) and progression-free survival (HR, 20.23, [95% CI: 2.19-186.86], P = .008) than patients of the same group with a high miRNA-181d expression. These correlations were not observed in the control group. The nonsignificance in the control group was confirmed in the independent TCGA dataset. The carmustine wafer group patients with low miRNA-181d expression also had a significantly longer progression-free (P = .049) and overall survival (OS) (P = .034), compared with control group patients. Gross total resection correlated significantly with longer OS (P = .023). MiRNA-181d expression significantly affects treatment responses to carmustine wafer implantation.

Modelling deformation and fracture in confectionery wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

2015-01-22

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

NASA Astrophysics Data System (ADS)

Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

2017-04-01

Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

Room-temperature wafer bonding of LiNbO3 and SiO2 using a modified surface activated bonding method

NASA Astrophysics Data System (ADS)

Takigawa, Ryo; Higurashi, Eiji; Asano, Tanemasa

2018-06-01

In this paper, we report room-temperature bonding of LiNbO3 (LN) and SiO2/Si for the realization of a LN on insulator (LNOI)/Si hybrid wafer. We investigate the applicability of a modified surface activated bonding (SAB) method for the direct bonding of LN and a thermally grown SiO2 layer. The modified SAB method using ion beam bombardment demonstrates the room-temperature wafer bonding of LN and SiO2. The bonded wafer was successfully cut into 0.5 × 0.5 mm2 dies without interfacial debonding owing to the applied stress during dicing. In addition, the surface energy of the bonded wafer was estimated to be approximately 1.8 J/m2 using the crack opening method. These results indicate that a strong bond strength can be achieved, which may be sufficient for device applications.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Modelling deformation and fracture in confectionery wafers

NASA Astrophysics Data System (ADS)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Dual-Beam Sample Preparation | Materials Science | NREL

Science.gov Websites

images showing cutting of trenches to remove a wafer section and transferring that section to a grid post section and transferring that section to a grid post. Here the wafer section is lifted out and seen from , extracted from the wafer then transferred and welded to a TEM grid post. Final thinning down to a thickness

Thin edge-defined film-fed growth (EFG) octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1992-03-01

Mobil Solar Energy Corp. investigated manufacturing crystalline silicon wafers using the edge-defined film-fed growth (EFG) technique. This report identifies the following: (1) current capabilities for manufacturing 200-micron-thick crystalline silicon wafers (10 cm x 10 cm) produced by growing octagons using the EFG technique and laser cutting them into wafers; (2) potential manufacturing improvements from decreasing the thickness of the wafers, improving the quality of the laser cut edge, and increasing cutting speed, all of which lead to reduce manufacturing costs, improved performance, and increased production capacities; (3) problems that impede achieving these potentials; and (4) costs and other requirements involved in overcoming the problems.

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

BCB Bonding Technology of Back-Side Illuminated COMS Device

NASA Astrophysics Data System (ADS)

Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

2018-03-01

Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Submicron patterned metal hole etching

DOEpatents

McCarthy, Anthony M.; Contolini, Robert J.; Liberman, Vladimir; Morse, Jeffrey

2000-01-01

A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

[The Detection of Ultra-Broadband Terahertz Spectroscopy of InP Wafer by Using Coherent Heterodyne Time-Domain Spectrometer].

PubMed

Zhang, Liang-liang; Zhang, Rui; Xu, Xiao-yan; Zhang, Cun-lin

2016-02-01

Indium Phosphide (InP) has attracted great physical interest because of its unique characteristics and is indispensable to both optical and electronic devices. However, the optical property of InP in the terahertz range (0. 110 THz) has not yet been fully characterized and systematically studied. The former researches about the properties of InP concentrated on the terahertz frequency between 0.1 and 4 THz. The terahertz optical properties of the InP in the range of 4-10 THz are still missing. It is fairly necessary to fully understand its properties in the entire terahertz range, which results in a better utilization as efficient terahertz devices. In this paper, we study the optical properties of undoped (100) InP wafer in the ultra-broad terahertz frequency range (0.5-18 THz) by using air-biased-coherent-detection (ABCD) system, enabling the coherent detection of terahertz wave in gases, which leads to a significant improvement on the dynamic range and sensitivity of the system. The advantage of this method is broad frequency bandwidth from 0.2 up to 18 THz which is only mainly limited by laser pulse duration since it uses ionized air as terahertz emitter and detector instead of using an electric optical crystal or photoconductive antenna. The terahertz pulse passing through the InP wafer is delayed regarding to the reference pulse and has much lower amplitude. In addition, the frequency spectrum amplitude of the terahertz sample signal drops to the noise floor level from 6.7 to 12.1 THz. At the same time InP wafer is opaque at the frequencies spanning from 6.7 to 12.1 THz. In the frequency regions of 0.8-6.7 and 12.1-18 THz it has relativemy low absorption coefficient. Meanwhile, the refractive index increases monotonously in the 0.8-6.7 THz region and 12.1-18 THz region. These findings will contribute to the design of InP based on nonlinear terahertz devices.

Single-mode VCSEL operation via photocurrent feedback

NASA Astrophysics Data System (ADS)

Riyopoulos, Spilios

1999-04-01

On-axis channeling through the use of photoactive layers in VCSEL cavities is proposed to counteract hole burning and mode switching. The photoactive layers act as variable resistivity screens whose radial `aperture' is controlled by the light itself. It is numerically demonstrated that absorption of a small fraction of the light intensity suffices for significant on axis current peaking and single mode operation at currents many times threshold, with minimum efficiency loss and optical mode distortion. Fabrication is implemented during the molecular beam epitaxy phase without wafer post processing, as for oxide apertures.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Wafering economies for industrialization from a wafer manufacturer's viewpoint

NASA Technical Reports Server (NTRS)

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Germanium Plasmon Enhanced Resonators for Label-Free Terahertz Protein Sensing

NASA Astrophysics Data System (ADS)

Bettenhausen, Maximilian; Römer, Friedhard; Witzigmann, Bernd; Flesch, Julia; Kurre, Rainer; Korneev, Sergej; Piehler, Jacob; You, Changjiang; Kazmierczak, Marcin; Guha, Subhajit; Capellini, Giovanni; Schröder, Thomas

2018-03-01

A Terahertz protein sensing concept based on subwavelength Ge resonators is presented. Ge bowtie resonators, compatible with CMOS fabrication technology, have been designed and characterized with a resonance frequency of 0.5 THz and calculated local intensity enhancement of 10.000. Selective biofunctionalization of Ge resonators on Si wafer was achieved in one step using lipoic acid-HaloTag ligand (LA-HTL) for biofunctionalization and passivation. The results lay the foundation for future investigation of protein tertiary structure and the dynamics of protein hydration shell in response to protein conformation changes.

Reflective optical imaging systems with balanced distortion

DOEpatents

Hudyma, Russell M.

2001-01-01

Optical systems compatible with extreme ultraviolet radiation comprising four reflective elements for projecting a mask image onto a substrate are described. The four optical elements comprise, in order from object to image, convex, concave, convex and concave mirrors. The optical systems are particularly suited for step and scan lithography methods. The invention enables the use of larger slit dimensions associated with ring field scanning optics, improves wafer throughput, and allows higher semiconductor device density. The inventive optical systems are characterized by reduced dynamic distortion because the static distortion is balanced across the slit width.

Heating device for semiconductor wafers

DOEpatents

Vosen, Steven R.

1999-01-01

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Heating device for semiconductor wafers

DOEpatents

Vosen, S.R.

1999-07-27

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

Compact particle accelerator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elizondo-Decanini, Juan M.

2017-08-29

A compact particle accelerator having an input portion configured to receive power to produce particles for acceleration, where the input portion includes a switch, is provided. In a general embodiment, a vacuum tube receives particles produced from the input portion at a first end, and a plurality of wafer stacks are positioned serially along the vacuum tube. Each of the plurality of wafer stacks include a dielectric and metal-oxide pair, wherein each of the plurality of wafer stacks further accelerate the particles in the vacuum tube. A beam shaper coupled to a second end of the vacuum tube shapes themore » particles accelerated by the plurality of wafer stacks into a beam and an output portion outputs the beam.« less

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

Induction soldering of photovoltaic system components

DOEpatents

Kumaria, Shashwat; de Leon, Briccio

2015-11-17

A method comprises positioning a pair of photovoltaic wafers in a side-by-side arrangement. An interconnect is placed on the pair of wafers such that the interconnect overlaps both wafers of the pair, solder material being provided between the interconnect and the respective wafers. A solder head is then located adjacent the interconnect, and the coil is energized to effect inductive heating of the solder material. The solder head comprises an induction coil shaped to define an eye, and a magnetic field concentrator located at least partially in the eye of the coil. The magnetic field concentrator defines a passage extending axially through the eye of the coil, and may be of a material with a high magnetic permeability.

Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology

NASA Astrophysics Data System (ADS)

Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

2014-01-01

The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

NASA Astrophysics Data System (ADS)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Preliminary results for mask metrology using spatial heterodyne interferometry

NASA Astrophysics Data System (ADS)

Bingham, Philip R.; Tobin, Kenneth; Bennett, Marylyn H.; Marmillion, Pat

2003-12-01

Spatial heterodyne interferometry (SHI) is an imaging technique that captures both the phase and amplitude of a complex wavefront in a single high-speed image. This technology was developed at the Oak Ridge National Laboratory (ORNL) and is currently being implemented for semiconductor wafer inspection by nLine Corporation. As with any system that measures phase, metrology and inspection of surface structures is possible by capturing a wavefront reflected from the surface. The interpretation of surface structure heights for metrology applications can become very difficult with the many layers of various materials used on semiconductor wafers, so inspection (defect detection) has been the primary focus for semiconductor wafers. However, masks used for photolithography typically only contain a couple well-defined materials opening the doors to high-speed mask metrology in 3 dimensions in addition to inspection. Phase shift masks often contain structures etched out of the transparent substrate material for phase shifting. While these structures are difficult to inspect using only intensity, the phase and amplitude images captured with SHI can produce very good resolution of these structures. The phase images also provide depth information that is crucial for these phase shift regions. Preliminary testing has been performed to determine the feasibility of SHI for high-speed non-contact mask metrology using a prototype SHI system with 532 nm wavelength illumination named the Visible Alpha Tool (VAT). These results show that prototype SHI system is capable of performing critical dimension measurements on 400nm lines with a repeatability of 1.4nm and line height measurements with a repeatability of 0.26nm. Additionally initial imaging of an alternating aperture phase shift mask has shown the ability of SHI to discriminate between typical phase shift heights.

Method and apparatus for monitoring plasma processing operations

DOEpatents

Smith, Jr., Michael Lane; Ward, Pamela Denise Peardon; Stevenson, Joel O'Don

2002-01-01

The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). Another aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system. A final aspect of the present invention relates to a network a plurality of plasma monitoring systems, including with remote capabilities (i.e., outside of the clean room).

Low-cost far infrared bolometer camera for automotive use

NASA Astrophysics Data System (ADS)

Vieider, Christian; Wissmar, Stanley; Ericsson, Per; Halldin, Urban; Niklaus, Frank; Stemme, Göran; Källhammer, Jan-Erik; Pettersson, Håkan; Eriksson, Dick; Jakobsen, Henrik; Kvisterøy, Terje; Franks, John; VanNylen, Jan; Vercammen, Hans; VanHulsel, Annick

2007-04-01

A new low-cost long-wavelength infrared bolometer camera system is under development. It is designed for use with an automatic vision algorithm system as a sensor to detect vulnerable road users in traffic. Looking 15 m in front of the vehicle it can in case of an unavoidable impact activate a brake assist system or other deployable protection system. To achieve our cost target below €100 for the sensor system we evaluate the required performance and can reduce the sensitivity to 150 mK and pixel resolution to 80 x 30. We address all the main cost drivers as sensor size and production yield along with vacuum packaging, optical components and large volume manufacturing technologies. The detector array is based on a new type of high performance thermistor material. Very thin Si/SiGe single crystal multi-layers are grown epitaxially. Due to the resulting valence barriers a high temperature coefficient of resistance is achieved (3.3%/K). Simultaneously, the high quality crystalline material provides very low 1/f-noise characteristics and uniform material properties. The thermistor material is transferred from the original substrate wafer to the read-out circuit using adhesive wafer bonding and subsequent thinning. Bolometer arrays can then be fabricated using industry standard MEMS process and materials. The inherently good detector performance allows us to reduce the vacuum requirement and we can implement wafer level vacuum packaging technology used in established automotive sensor fabrication. The optical design is reduced to a single lens camera. We develop a low cost molding process using a novel chalcogenide glass (GASIR®3) and integrate anti-reflective and anti-erosion properties using diamond like carbon coating.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic

NASA Astrophysics Data System (ADS)

Cramer, Hugo; Mc Namara, Elliott; van Laarhoven, Rik; Jaganatharaja, Ram; de la Fuente, Isabel; Hsu, Sharon; Belletti, Filippo; Popadic, Milos; Tu, Ward; Huang, Wade

2017-03-01

The logic manufacturing process requires small in-device metrology targets to exploit the full dose correction potential of the modern scanners and process tools. A high-NA angular resolved scatterometer (YieldStar S-1250D) was modified to demonstrate the possibility of OCD measurements on 5x5µm2 targets. The results obtained on test wafers in a logic manufacturing environment, measured after litho and after core etch, showed a good correlation to larger reference targets and AEI to ADI intra-field CDU correlation, thereby demonstrating the feasibility of OCD on such small targets. The data was used to determine a reduction potential of 55% for the intra-field CD variation, using 145 points per field on a few inner fields, and 33% of the process induced across wafer CD variation using 16 points per field full wafer. In addition, the OCD measurements reveal valuable information on wafer-to-wafer layer height variations within a lot.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

Semiconductor laser using multimode interference principle

NASA Astrophysics Data System (ADS)

Gong, Zisu; Yin, Rui; Ji, Wei; Wu, Chonghao

2018-01-01

Multimode interference (MMI) structure is introduced in semiconductor laser used in optical communication system to realize higher power and better temperature tolerance. Using beam propagation method (BPM), Multimode interference laser diode (MMI-LD) is designed and fabricated in InGaAsP/InP based material. As a comparison, conventional semiconductor laser using straight single-mode waveguide is also fabricated in the same wafer. With a low injection current (about 230 mA), the output power of the implemented MMI-LD is up to 2.296 mW which is about four times higher than the output power of the conventional semiconductor laser. The implemented MMI-LD exhibits stable output operating at the wavelength of 1.52 μm and better temperature tolerance when the temperature varies from 283.15 K to 293.15 K.

X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Developing quartz wafer mold manufacturing process for patterned media

NASA Astrophysics Data System (ADS)

Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

2009-04-01

Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Wafer-fused semiconductor radiation detector

DOEpatents

Lee, Edwin Y.; James, Ralph B.

2002-01-01

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Composite HPMC and sodium alginate based buccal formulations for nicotine replacement therapy.

PubMed

Okeke, Obinna C; Boateng, Joshua S

2016-10-01

Smoking cessation is of current topical interest due to the significant negative health and economic impact in many countries. This study aimed to develop buccal films and wafers comprising HPMC and sodium alginate (SA) for potential use in nicotine replacement therapy via the buccal mucosa, as a cheap but effective alternative to currently used nicotine patch and chewing gum. The formulations were characterised using texture analyser (tensile and hardness, mucoadhesion), scanning electron microscopy, X-ray diffractometry, attenuated total reflection-Fourier transform infrared (ATR-FTIR), differential scanning calorimetry (DSC) and swelling capacity. Drug loaded films and wafers were characterised for content uniformity (HPLC) whilst the drug loaded wafers only were further characterised for in vitro drug dissolution. SA modified and improved the functional properties of HPMC at optimum ratio of HPMC: SA of 1.25: 0.75. Generally, both films and wafers (blank and drug loaded) were amorphous in nature which impacted on swelling and mucoadhesive performance. HPMC-SA composite wafers showed a porous internal morphology with higher mucoadhesion, swelling index and drug loading capacity compared to the HPMC-SA composite films which were non-porous. The study demonstrates the potential use of composite HPMC-SA wafers in the buccal delivery nicotine. Copyright © 2016 Elsevier B.V. All rights reserved.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

A Lorentz force actuated magnetic field sensor with capacitive read-out

NASA Astrophysics Data System (ADS)

Stifter, M.; Steiner, H.; Kainz, A.; Keplinger, F.; Hortschitz, W.; Sauter, T.

2013-05-01

We present a novel design of a resonant magnetic field sensor with capacitive read-out permitting wafer level production. The device consists of a single-crystal silicon cantilever manufactured from the device layer of an SOI wafer. Cantilevers represent a very simple structure with respect to manufacturing and function. On the top of the structure, a gold lead carries AC currents that generate alternating Lorentz forces in an external magnetic field. The free end oscillation of the actuated cantilever depends on the eigenfrequencies of the structure. Particularly, the specific design of a U-shaped structure provides a larger force-to-stiffness-ratio than standard cantilevers. The electrodes for detecting cantilever deflections are separately fabricated on a Pyrex glass-wafer. They form the counterpart to the lead on the freely vibrating planar structure. Both wafers are mounted on top of each other. A custom SU-8 bonding process on wafer level creates a gap which defines the equilibrium distance between sensing electrodes and the vibrating structure. Additionally to the capacitive read-out, the cantilever oscillation was simultaneously measured with laser Doppler vibrometry through proper windows in the SOI handle wafer. Advantages and disadvantages of the asynchronous capacitive measurement configuration are discussed quantitatively and presented by a comprehensive experimental characterization of the device under test.

Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

High fill-factor micromirror array using a self-aligned vertical comb drive actuator with two rotational axes

NASA Astrophysics Data System (ADS)

Kim, Minsoo; Park, Jae-Hyoung; Jeon, Jin-A.; Yoo, Byung-Wook; Park, I. H.; Kim, Yong-Kweon

2009-03-01

We present a two-axis micromirror array with high fill-factor, using a new fabrication procedure on the full wafer scale. The micromirror comprises a self-aligned vertical comb drive actuator with a mirror plate mounted on it and electrical lines on a bottom substrate. A high-aspect-ratio vertical comb drive was built using a bulk micromachining technique on a silicon-on-insulator (SOI) wafer. The thickness of the torsion spring was adjusted using multiple silicon etching steps to enhance the static angular deflection of the mirrors. To address the array, electrical lines were fabricated on a glass substrate and combined with the comb actuators using an anodic bonding process. The silicon mirror plate was fabricated together with the actuator using a wafer bonding process and segmented at the final release step. The actuator and addressing lines were hidden behind the mirror plate, resulting in a high fill-factor of 84% in an 8 × 8 array of micromirrors, each 340 µm × 340 µm. The fabricated mirror plate has a high-quality optical surface with an average surface roughness (Ra) of 4 nm and a curvature radius of 0.9 m. The static and dynamic responses of the micromirror were characterized by comparing the measured results with the calculated values. The maximum static optical deflection for the outer axis is 4.32° at 60 V, and the maximum inner axis tilting angle is 2.82° at 96 V bias. The torsion resonance frequencies along the outer and inner axes were 1.94 kHz and 0.95 kHz, respectively.

Local delivery of cancer-cell glycolytic inhibitors in high-grade glioma

PubMed Central

Wicks, Robert T.; Azadi, Javad; Mangraviti, Antonella; Zhang, Irma; Hwang, Lee; Joshi, Avadhut; Bow, Hansen; Hutt-Cabezas, Marianne; Martin, Kristin L.; Rudek, Michelle A.; Zhao, Ming; Brem, Henry; Tyler, Betty M.

2015-01-01

Background 3-bromopyruvate (3-BrPA) and dichloroacetate (DCA) are inhibitors of cancer-cell specific aerobic glycolysis. Their application in glioma is limited by 3-BrPA's inability to cross the blood-brain-barrier and DCA's dose-limiting toxicity. The safety and efficacy of intracranial delivery of these compounds were assessed. Methods Cytotoxicity of 3-BrPA and DCA were analyzed in U87, 9L, and F98 glioma cell lines. 3-BrPA and DCA were incorporated into biodegradable pCPP:SA wafers, and the maximally tolerated dose was determined in F344 rats. Efficacies of the intracranial 3-BrPA wafer and DCA wafer were assessed in a rodent allograft model of high-grade glioma, both as a monotherapy and in combination with temozolomide (TMZ) and radiation therapy (XRT). Results 3-BrPA and DCA were found to have similar IC50 values across the 3 glioma cell lines. 5% 3-BrPA wafer-treated animals had significantly increased survival compared with controls (P = .0027). The median survival of rats with the 50% DCA wafer increased significantly compared with both the oral DCA group (P = .050) and the controls (P = .02). Rats implanted on day 0 with a 5% 3-BrPA wafer in combination with TMZ had significantly increased survival over either therapy alone. No statistical difference in survival was noted when the wafers were added to the combination therapy of TMZ and XRT, but the 5% 3-BrPA wafer given on day 0 in combination with TMZ and XRT resulted in long-term survivorship of 30%. Conclusion Intracranial delivery of 3-BrPA and DCA polymer was safe and significantly increased survival in an animal model of glioma, a potential novel therapeutic approach. The combination of intracranial 3-BrPA and TMZ provided a synergistic effect. PMID:25053853

Slopes To Prevent Trapping of Bubbles in Microfluidic Channels

NASA Technical Reports Server (NTRS)

Greer, Harold E.; Lee, Michael C.; Smith, J. Anthony; Willis, Peter A.

2010-01-01

The idea of designing a microfluidic channel to slope upward along the direction of flow of the liquid in the channel has been conceived to help prevent trapping of gas bubbles in the channel. In the original application that gave rise to this idea, the microfluidic channels are parts of micro-capillary electrophoresis (microCE) devices undergoing development for use on Mars in detecting compounds indicative of life. It is necessary to prevent trapping of gas bubbles in these devices because uninterrupted liquid pathways are essential for sustaining the electrical conduction and flows that are essential for CE. The idea is also applicable to microfluidic devices that may be developed for similar terrestrial microCE biotechnological applications or other terrestrial applications in which trapping of bubbles in microfluidic channels cannot be tolerated. A typical microCE device in the original application includes, among other things, multiple layers of borosilicate float glass wafers. Microfluidic channels are formed in the wafers, typically by use of wet chemical etching. The figure presents a simplified cross section of part of such a device in which the CE channel is formed in the lowermost wafer (denoted the channel wafer) and, according to the present innovation, slopes upward into a via hole in another wafer (denoted the manifold wafer) lying immediately above the channel wafer. Another feature of the present innovation is that the via hole in the manifold wafer is made to taper to a wider opening at the top to further reduce the tendency to trap bubbles. At the time of reporting the information for this article, an effort to identify an optimum technique for forming the slope and the taper was in progress. Of the techniques considered thus far, the one considered to be most promising is precision milling by use of femtosecond laser pulses. Other similar techniques that may work equally well are precision milling using a focused ion beam, or a small diamond-tipped drill bit.

Advanced excimer laser technologies enable green semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Fukuda, Hitomi; Yoo, Youngsun; Minegishi, Yuji; Hisanaga, Naoto; Enami, Tatsuo

2014-03-01

"Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental "green cost" of laser operations in high-volume manufacturing environment (HVM) - primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton's Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry's transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

Successful demonstration of a comprehensive lithography defect monitoring strategy

NASA Astrophysics Data System (ADS)

Peterson, Ingrid B.; Breaux, Louis H.; Cross, Andrew; von den Hoff, Michael

2003-07-01

This paper describes the validation of the methodology, the model and the impact of an optimized Lithography Defect Monitoring Strategy at two different semiconductor manufacturing factories. The lithography defect inspection optimization was implemented for the Gate Module at both factories running 0.13-0.15μm technologies on 200mm wafers, one running microprocessor and the other memory devices. As minimum dimensions and process windows decrease in the lithography area, new technologies and technological advances with resists and resist systems are being implemented to meet the demands. Along with these new technological advances in the lithography area comes potentially unforeseen defect issues. The latest lithography processes involve new resists in extremely thin, uniform films, exposing the films under conditions of highly optimized focus and illumination, and finally removing the resist completely and cleanly. The lithography cell is defined as the cluster of process equipment that accomplishes the coating process (surface prep, resist spin, edge-bead removal and soft bake), the alignment and exposure, and the developing process (post-exposure bake, develop, rinse) of the resist. Often the resist spinning process involves multiple materials such as BARC (bottom ARC) and / or TARC (top ARC) materials in addition to the resist itself. The introduction of these new materials with the multiple materials interfaces and the tightness of the process windows leads to an increased variety of defect mechanisms in the lithography area. Defect management in the lithography area has become critical to successful product introduction and yield ramp. The semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originate within the lithography cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the lithography process module have the widest range of sizes, from full-wafer to suboptical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects as shown in Figure 1. Others fall into the category of lithography micro defects, Figure 2. They are characterized as having low topography such as stains, developer spots, satellites, are very small such as micro-bridging, partial micro-bridging, micro-bubbles, CD variation and single isolated missing or deformed contacts or vias. Lithography is the only area of the fab besides CMP in which defect excursions can be corrected by reworking the wafers. The opportunity to fix defect problems without scrapping wafers is best served by a defect inspection strategy that captures the full range of all relevant defect types with a proper balance between the costs of monitoring and inspection and the potential cost of yield loss. In the previous paper [1] it was shown that a combination of macro inspection and high numerical aperture (NA) brightfield imaging inspection technology is best suited for the application in the case of the idealized fab modeled. In this paper we will report on the successful efforts in implementing and validating the lithography defect monitoring strategy at two existing 200 mm factories running 0.15 μm and 0.13 μm design rules.

Mobil Solar Energy Corporation thin EFG octagons. Semiannual subcontract report, 1 April 1992--30 September 1992

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kalejs, J.P.

1993-09-01

This report describes work carried out for the PVMaT program at Mobil Solar for the period covering April 1, 1992, to September 30, 1992. Mobil Solar is developing advanced technology for growing and cutting 200-{mu}m-thick edge-defined film-fed growth (EFG) octagon tubes that will reduce the manufacturing costs of 10-cm {times} 10-cm polycrystalline EFG silicon wafers. Mobil Solar has made progress in identifying factors that impact on thickness nonuniformity and means to reduce the deleterious impact of ambient-related effects that have caused reduction in crystal growth productivity and wafer yield. The current main obstacle to meeting material yield targets arises duemore » to the buckling produced by thermal stress. Studies of laser cutting of EFG silicon using ND:YAG and dye lasers are underway to develop reduced damage cutting methods. Mobil Solar has carried out design reviews for crystal growth and laser cutting equipment. A task has been initiated to evaluate new online sensors for crystal growth process control and to study implementation of advanced control concepts for productivity and yield improvements.« less

A cMUT probe for ultrasound-guided focused ultrasound targeted therapy.

PubMed

Gross, Dominique; Coutier, Caroline; Legros, Mathieu; Bouakaz, Ayache; Certon, Dominique

2015-06-01

Ultrasound-mediated targeted therapy represents a promising strategy in the arsenal of modern therapy. Capacitive micromachined ultrasonic transducer (cMUT) technology could overcome some difficulties encountered by traditional piezoelectric transducers. In this study, we report on the design, fabrication, and characterization of an ultrasound-guided focused ultrasound (USgFUS) cMUT probe dedicated to preclinical evaluation of targeted therapy (hyperthermia, thermosensitive liposomes activation, and sonoporation) at low frequency (1 MHz) with simultaneous ultrasonic imaging and guidance (15 to 20 MHz). The probe embeds two types of cMUT arrays to perform the modalities of targeted therapy and imaging respectively. The wafer-bonding process flow employed for the manufacturing of the cMUTs is reported. One of its main features is the possibility of implementing two different gap heights on the same wafer. All the design and characterization steps of the devices are described and discussed, starting from the array design up to the first in vitro measurements: optical (microscopy) and electrical (impedance) measurements, arrays' electroacoustic responses, focused pressure field mapping (maximum peak-to-peak pressure = 2.5 MPa), and the first B-scan image of a wire-target phantom.

Instructions for Plastic Encapsulated Microcircuit(PEM) Selection, Screening and Qualification.

NASA Technical Reports Server (NTRS)

King, Terry; Teverovsky, Alexander; Leidecker, Henning

2002-01-01

The use of Plastic Encapsulated Microcircuits (PEMs) is permitted on NASA Goddard Space Flight Center (GSFC) spaceflight applications, provided each use is thoroughly evaluated for thermal, mechanical, and radiation implications of the specific application and found to meet mission requirements. PEMs shall be selected for their functional advantage and availability, not for cost saving; the steps necessary to ensure reliability usually negate any initial apparent cost advantage. A PEM shall not be substituted for a form, fit and functional equivalent, high reliability, hermetic device in spaceflight applications. Due to the rapid change in wafer-level designs typical of commercial parts and the unknown traceability between packaging lots and wafer lots, lot specific testing is required for PEMs, unless specifically excepted by the Mission Assurance Requirements (MAR) for the project. Lot specific qualification, screening, radiation hardness assurance analysis and/or testing, shall be consistent with the required reliability level as defined in the MAR. Developers proposing to use PEMs shall address the following items in their Performance Assurance Implementation Plan: source selection (manufacturers and distributors), storage conditions for all stages of use, packing, shipping and handling, electrostatic discharge (ESD), screening and qualification testing, derating, radiation hardness assurance, test house selection and control, data collection and retention.

Real-time OHT Dispatching Mechanism for the Interbay Automated Material Handling System with Shortcuts and Bypasses

NASA Astrophysics Data System (ADS)

Pan, Cong; Zhang, Jie; Qin, Wei

2017-05-01

As a key to improve the performance of the interbay automated material handling system (AMHS) in 300 mm semiconductor wafer fabrication system, the real-time overhead hoist transport (OHT) dispatching problem has received much attention. This problem is first formulated as a special form of assignment problem and it is proved that more than one solution will be obtained by Hungarian algorithm simultaneously. Through proposing and strictly proving two propositions related to the characteristics of these solutions, a modified Hungarian algorithm is designed to distinguish these solutions. Finally, a new real-time OHT dispatching method is carefully designed by implementing the solution obtained by the modified Hungarian algorithm. The experimental results of discrete event simulations show that, compared with conventional Hungarian algorithm dispatching method, the proposed dispatching method that chooses the solution with the maximum variance respectively reduces on average 4 s of the average waiting time and average lead time of wafer lots, and its performance is rather stable in multiple different scenarios of the interbay AMHS with different quantities of shortcuts. This research provides an efficient real-time OHT dispatching mechanism for the interbay AMHS with shortcuts and bypasses.

Impact of Beads and Drops on a Repellent Solid Surface: A Unified Description

NASA Astrophysics Data System (ADS)

Arora, S.; Fromental, J.-M.; Mora, S.; Phou, Ty; Ramos, L.; Ligoure, C.

2018-04-01

We investigate freely expanding sheets formed by ultrasoft gel beads, and liquid and viscoelastic drops, produced by the impact of the bead or drop on a silicon wafer covered with a thin layer of liquid nitrogen that suppresses viscous dissipation thanks to an inverse Leidenfrost effect. Our experiments show a unified behavior for the impact dynamics that holds for solids, liquids, and viscoelastic fluids and that we rationalize by properly taking into account elastocapillary effects. In this framework, the classical impact dynamics of solids and liquids, as far as viscous dissipation is negligible, appears as the asymptotic limits of a universal theoretical description. A novel material-dependent characteristic velocity that includes both capillary and bulk elasticity emerges from this unified description of the physics of impact.

Top coat or no top coat for immersion lithography?

NASA Astrophysics Data System (ADS)

Stepanenko, N.; Kim, Hyun-Woo; Kishimura, S.; Van Den Heuvel, D.; Vandenbroeck, N.; Kocsis, M.; Foubert, P.; Maenhoudt, M.; Ercken, M.; Van Roey, F.; Gronheid, R.; Pollentier, I.; Vangoidsenhoven, D.; Delvaux, C.; Baerts, C.; O'Brien, S.; Fyen, W.; Wells, G.

2006-03-01

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the material's refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the material's dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

PubMed

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Numerical simulation and experimental validation of the dynamics of multiple bubble merger during pool boiling under microgravity conditions.

PubMed

Abarajith, H S; Dhir, V K; Warrier, G; Son, G

2004-11-01

Numerical simulation and experimental validation of the growth and departure of multiple merging bubbles and associated heat transfer on a horizontal heated surface during pool boiling under variable gravity conditions have been performed. A finite difference scheme is used to solve the equations governing mass, momentum, and energy in the vapor liquid phases. The vapor-liquid interface is captured by a level set method that is modified to include the influence of phase change at the liquid-vapor interface. Water is used as test liquid. The effects of reduced gravity condition and orientation of the bubbles on the bubble diameter, interfacial structure, bubble merger time, and departure time, as well as local heat fluxes, are studied. In the experiments, multiple vapor bubbles are produced on artificial cavities in the 2-10 micrometer diameter range, microfabricated on the polished silicon wafer with given spacing. The wafer was heated electrically from the back with miniature strain gage type heating elements in order to control the nucleation superheat. The experiments conducted in normal Earth gravity and in the low gravity environment of KC-135 aircraft are used to validate the numerical simulations.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to achieving millisecond lifetimes in kerfless silicon materials. Laser fired contacts to n-Si were developed for the first time using a Al/Sb/Ti metal stack giving contact resistances < 5 mOhm-cm2 when fired through several different dielectric layers. A new 2 step laser+chemical etch isolation technique was developed using a sacrificial top coating which avoids laser damage to Si passivation. Regarding the heterojunction emitter, analysis of front FHJ (1D) and IBC (2D) cells with range of p-layer conditions found that a 2-stage high/low doped p-layer was optimum: the low doped region has lower defects giving higher Voc and the high doped region gave a better contact to the metal. A significant effort was spent studying the patterning process and its contribution to degradation of passivation and reproducibility. Several promising new cleaning, contact and deposition patterning and processing approaches were implemented leading to fabrication of several runs with cells having 19-20% efficiency which were stable over several months. This program resulted in the training and support of 12 graduate students, publication of 21 journal papers and 14 conference papers.« less

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

The effects of the NICE Technology Appraisal 121 (gliadel and temozolomide) on survival in high-grade glioma.

PubMed

Barr, James Geoffrey; Grundy, Paul L

2012-12-01

The prognosis of high-grade glioma (HGG) is poor with a median survival of about 1 year for glioblastoma. In 2007, NICE published a technology appraisal (TA121) recommending the use of carmustine wafers (Gliadel) and systemic therapy with temozolomide for selected patients with HGG. Outcomes for HGG surgery in the United Kingdom with these combined treatments have not been published. Retrospective audit of consecutive patients in a single unit with carmustine wafer implantation. Fifty-nine patients had carmustine wafers implanted at primary surgery, between October 2005 and October 2010 at Wessex Neurological Centre, Southampton, UK. Patients were given chemotherapeutic treatments strictly according to NICE TA121. Survival was calculated using Kaplan-Meier method. Fifty-five patients had WHO grade IV tumours and four had grade III. Median age was 61 years. At follow-up, 39 patients had died. Median survival was 15.3 months. Eight patients (13.5%) experienced post-operative complications (including five infections) for which four had the carmustine wafers removed. Forty-seven (80%) patients were treated with radical radiotherapy (55-60 Gy) and six (10%) patients received palliative radiotherapy (30 Gy). Thirty-seven patients (63%) received concomitant temozolomide chemotherapy. In the subset of 37 patients receiving multimodal treatment with radical radiotherapy and concomitant temozolomide, median survival was 15.8 months compared with 7.4 months in those not receiving multimodal treatment. Carmustine wafers for primary HGG surgery in accordance with the NICE TA121 were associated with a median survival of 15.3 months; this is improved compared with previously reported randomised trials. Multimodal treatment with carmustine wafers, radical radiotherapy and concomitant temozolomide was associated with improved survival. Increased incidence of infections was observed in cases receiving carmustine wafers.

Photolithography and Selective Etching of an Array of Quartz Tuning Fork Resonators with Improved Impact Resistance Characteristics

NASA Astrophysics Data System (ADS)

Lee, Sungkyu

2001-08-01

Quartz tuning fork blanks with improved impact-resistant characteristics for use in Qualcomm mobile station modem (MSM)-3000 central processing unit (CPU) chips for code division multiple access (CDMA), personal communication system (PCS), and global system for mobile communication (GSM) systems were designed using finite element method (FEM) analysis and suitable processing conditions were determined for the reproducible precision etching of a Z-cut quartz wafer into an array of tuning forks. Negative photoresist photolithography for the additive process was used in preference to positive photoresist photolithography for the subtractive process to etch the array of quartz tuning forks. The tuning fork pattern was transferred via a conventional photolithographical chromium/quartz glass template using a standard single-sided aligner and subsequent negative photoresist development. A tightly adhering and pinhole-free 600/2000 Å chromium/gold mask was coated over the developed photoresist pattern which was subsequently stripped in acetone. This procedure was repeated on the back surface of the wafer. With the protective metallization area of the tuning fork geometry thus formed, etching through the quartz wafer was performed at 80°C in a ± 1.5°C controlled bath containing a concentrated solution of ammonium bifluoride to remove the unwanted areas of the quartz wafer. The quality of the quartz wafer surface finish after quartz etching depended primarily on the surface finish of the quartz wafer prior to etching and the quality of quartz crystals used. Selective etching of a 100 μm quartz wafer could be achieved within 90 min at 80°C. A selective etching procedure with reproducible precision has thus been established and enables the photolithographic mass production of miniature tuning fork resonators.

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

NASA Astrophysics Data System (ADS)

Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

2018-01-01

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Local interstitial delivery of z-butylidenephthalide by polymer wafers against malignant human gliomas

PubMed Central

Harn, Horng-Jyh; Lin, Shinn-Zong; Lin, Po-Cheng; Liu, Cyong-Yue; Liu, Po-Yen; Chang, Li-Fu; Yen, Ssu-Yin; Hsieh, Dean-Kuo; Liu, Fu-Chen; Tai, Dar-Fu; Chiou, Tzyy-Wen

2011-01-01

We have shown that the natural compound z-butylidenephthalide (Bdph), isolated from the chloroform extract of Angelica sinensis, has antitumor effects. Because of the limitation of the blood-brain barrier, the Bdph dosage required for treatment of glioma is relatively high. To solve this problem, we developed a local-release system with Bdph incorporated into a biodegradable polyanhydride material, p(CPP-SA; Bdph-Wafer), and investigated its antitumor effects. On the basis of in vitro release kinetics, we demonstrated that the Bdph-Wafer released 50% of the available Bdph by the sixth day, and the release reached a plateau phase (90% of Bdph) by the 30th day. To investigate the in situ antitumor effects of the Bdph-Wafer on glioblastoma multiforme (GBM), we used 2 xenograft animal models—F344 rats (for rat GBM) and nude mice (for human GBM)—which were injected with RG2 and DBTRG-05MG cells, respectively, for tumor formation and subsequently treated subcutaneously with Bdph-Wafers. We observed a significant inhibitory effect on tumor growth, with no significant adverse effects on the rodents. Moreover, we demonstrated that the antitumor effect of Bdph on RG2 cells was via the PKC pathway, which upregulated Nurr77 and promoted its translocation from the nucleus to the cytoplasm. Finally, to study the effect of the interstitial administration of Bdph in cranial brain tumor, Bdph-Wafers were surgically placed in FGF-SV40 transgenic mice. Our Bdph-Wafer significantly reduced tumor size in a dose-dependent manner. In summary, our study showed that p(CPP-SA) containing Bdph delivered a sufficient concentration of Bdph to the tumor site and effectively inhibited the tumor growth in the glioma. PMID:21565841

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

NASA Astrophysics Data System (ADS)

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Capillary liquid chromatography-microchip atmospheric pressure chemical ionization-mass spectrometry.

PubMed

Ostman, Pekka; Jäntti, Sirkku; Grigoras, Kestas; Saarela, Ville; Ketola, Raimo A; Franssila, Sami; Kotiaho, Tapio; Kostiainen, Risto

2006-07-01

A miniaturized nebulizer chip for capillary liquid chromatography-atmospheric pressure chemical ionization-mass spectrometry (capillary LC-microchip APCI-MS) is presented. The APCI chip consists of two wafers, a silicon wafer and a Pyrex glass wafer. The silicon wafer has a DRIE etched through-wafer nebulizer gas inlet, an edge capillary insertion channel, a stopper, a vaporizer channel and a nozzle. The platinum heater electrode and pads for electrical connection were patterned on to the Pyrex glass wafer. The two wafers were joined by anodic bonding, creating a microchip version of an APCI-source. The sample inlet capillary from an LC column is directly connected to the vaporizer channel of the APCI chip. The etched nozzle in the microchip forms a narrow sample plume, which is ionized by an external corona needle, and the formed ions are analyzed by a mass spectrometer. The nebulizer chip enables for the first time the use of low flow rate separation techniques with APCI-MS. The performance of capillary LC-microchip APCI-MS was tested with selected neurosteroids. The capillary LC-microchip APCI-MS provides quantitative repeatability and good linearity. The limits of detection (LOD) with a signal-to-noise ratio (S/N) of 3 in MS/MS mode for the selected neurosteroids were 20-1000 fmol (10-500 nmol l(-1)). LODs (S/N = 3) with commercial macro APCI with the same compounds using the same MS were about 10 times higher. Fast heat transfer allows the use of the optimized temperature for each compound during an LC run. The microchip APCI-source provides a convenient and easy method to combine capillary LC to any API-MS equipped with an APCI source. The advantages and potentials of the microchip APCI also make it a very attractive interface in microfluidic APCI-MS.

Field trials of solid triple lure (trimedlure, methyl eugenol, raspberry ketone, and DDVP) dispensers for detection and male annihilation of Ceratitis capitata, Bactrocera dorsalis, and Bactrocera cucurbitae (Diptera: Tephritidae) in Hawaii.

PubMed

Vargas, Roger I; Souder, Steven K; Mackey, Bruce; Cook, Peter; Morse, Joseph G; Stark, John D

2012-10-01

Solid Mallet TMR (trimedlure [TML], methyl eugenol [ME], raspberry ketone [RK]) wafers and Mallet CMR (ceralure, ME, RK, benzyl acetate) wafers impregnated with DDVP (2,2-dichlorovinyl dimethyl phosphate) insecticide were measured in traps as potential detection and male annihilation technique (MAT) devices. Comparisons were made with 1) liquid lure and insecticide formulations, 2) solid cones and plugs with an insecticidal strip, and 3) solid single and double lure wafers with DDVP for captures of Mediterranean fruit fly, Ceratitis capitata (Wiedemann); oriental fruit fly, Bactrocera dorsalis Hendel; and melon fly, B. cucurbitae Coquillett. Bucket and Jackson traps were tested in a coffee plantation near Eleele, Kauai Island, HI (trials at high populations) and avocado orchards near Kona, HI Island, HI (trials at low populations). Captures of all three species with Mallet TMR were not different from Mallet CMR; therefore, subsequent experiments did not include Mallet CMR because of higher production costs. In MAT trials near Eleele, HI captures in AWPM traps with Mallet TMR wafers were equal to any other solid lure (single or double) except the Mallet ME wafer. In survey trials near Kona, captures of C. capitata, B. cucurbitae, and B. dorsalis with Mallet TMR wafers were equal to those for the standard TML, ME, and C-L traps used in FL and CA. A solid Mallet TMR wafer is safer, more convenient to handle, and may be used in place of several individual lure and trap systems, potentially reducing costs of large survey and detection programs in Florida and California, and MAT programs in Hawaii.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

[Fatty acids in confectionery products].

PubMed

Daniewski, M; Mielniczuk, E; Jacórzyński, B; Pawlicka, M; Balas, J; Filipek, A; Górnicka, M

2000-01-01

The content of fat and fatty acids in 144 different confectionery products purchased on the market in Warsaw region during 1997-1999 have been investigated. In examined confectionery products considerable variability of both fat and fatty acids content have been found. The content of fat varied from 6.6% (coconut cookies) up to 40% (chocolate wafers). Saturated fatty acids were present in both cis and trans form. Especially trans fatty acids reach (above 50%) were fats extracted from nut wafers, coconuts wafers.

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

Active high-power RF switch and pulse compression system

DOEpatents

Tantawi, Sami G.; Ruth, Ronald D.; Zolotorev, Max

1998-01-01

A high-power RF switching device employs a semiconductor wafer positioned in the third port of a three-port RF device. A controllable source of directed energy, such as a suitable laser or electron beam, is aimed at the semiconductor material. When the source is turned on, the energy incident on the wafer induces an electron-hole plasma layer on the wafer, changing the wafer's dielectric constant, turning the third port into a termination for incident RF signals, and. causing all incident RF signals to be reflected from the surface of the wafer. The propagation constant of RF signals through port 3, therefore, can be changed by controlling the beam. By making the RF coupling to the third port as small as necessary, one can reduce the peak electric field on the unexcited silicon surface for any level of input power from port 1, thereby reducing risk of damaging the wafer by RF with high peak power. The switch is useful to the construction of an improved pulse compression system to boost the peak power of microwave tubes driving linear accelerators. In this application, the high-power RF switch is placed at the coupling iris between the charging waveguide and the resonant storage line of a pulse compression system. This optically controlled high power RF pulse compression system can handle hundreds of Megawatts of power at X-band.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less

Fundamental understanding of wave generation and reception using d(36) type piezoelectric transducers.

PubMed

Zhou, Wensong; Li, Hui; Yuan, Fuh-Gwo

2015-03-01

A new piezoelectric wafer made from a PMN-PT single crystal with dominant piezoelectric coefficient d36 is proposed to generate and detect guided waves on isotropic plates. The in-plane shear coupled with electric field arising from the piezoelectric coefficient is not usually present for conventional piezoelectric wafers, such as lead zirconate titanate (PZT). The direct piezoelectric effect of coefficient d36 indicates that under external in-plane shear stress the charge is induced on a face perpendicular to the poled z-direction. On thin plates, this type of piezoelectric wafer will generate shear horizontal (SH) waves in two orthogonal wave propagation directions as well as two Lamb wave modes in other wave propagation directions. Finite element analyses are employed to explore the wave disturbance in terms of time-varying displacements excited by the d36 wafer in different directions of wave propagation to understand all the guided wave modes accurately. Experiments are conducted to examine the voltage responses received by this type of wafer, and also investigate results of tuning frequency and effects of d31 piezoelectric coefficient, which is intentionally ignored in the finite element analysis. All results demonstrate the main features and utility of proposed d36 piezoelectric wafer for guided wave generation and detection in structural health monitoring. Copyright © 2014 Elsevier B.V. All rights reserved.

A novel approach of chemical mechanical polishing using environment-friendly slurry for mercury cadmium telluride semiconductors

PubMed Central

Zhang, Zhenyu; Wang, Bo; Zhou, Ping; Guo, Dongming; Kang, Renke; Zhang, Bi

2016-01-01

A novel approach of chemical mechanical polishing (CMP) is developed for mercury cadmium telluride (HgCdTe or MCT) semiconductors. Firstly, fixed-abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water. Secondly, the MCT wafers are polished using the developed CMP slurry. The CMP slurry consists of mainly SiO2 nanospheres, H2O2, and malic and citric acids, which are different from previous CMP slurries, in which corrosive and toxic chemical reagents are usually employed. Finally, the polished MCT wafers are cleaned and dried by deionized water and compressed air, respectively. The novel approach of CMP is environment-friendly. Surface roughness Ra, and peak-to-valley (PV) values of 0.45, and 4.74 nm are achieved, respectively on MCT wafers after CMP. The first and second passivating processes are observed in electrochemical measurements on MCT wafers. The fundamental mechanisms of CMP are proposed according to the X-ray photoelectron spectroscopy (XPS) and electrochemical measurements. Malic and citric acids dominate the first passivating process, and the CMP slurry governs the second process. Te4+3d peaks are absent after CMP induced by the developed CMP slurry, indicating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2 and malic and citric acids solutions. PMID:26926622

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

DOE Office of Scientific and Technical Information (OSTI.GOV)

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In thismore » manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented« less

Accurate characterization of wafer bond toughness with the double cantilever specimen

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Spearing, S. Mark

2008-01-01

The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

PubMed Central

Grant, Nicholas E.

2016-01-01

A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

150-nm generation lithography equipment

NASA Astrophysics Data System (ADS)

Deguchi, Nobuyoshi; Uzawa, Shigeyuki

1999-07-01

Lithography by step-and-scan exposure is expected to be the mainstream for semiconductor manufacturing below 180 nm resolution patterns. We have developed a scanner for 150 nm features on either 200 mm or 300 mm wafers. For this system, the synchronous stage system has been redesigned which makes it possible to improve imaging performance and overlay accuracy. A new 300 mm wafer stage enhances productivity while weighting almost the same as the stage for 200 mm wafers. The mainbody mechanical frame incorporates reactive force receiver system to counter the inertial energy and vibrational issues associated with high speed wafer and reticle stage scanning. This report outlines the total system design, new technologies and performance data of the Cannon FPA-5000ES2 step-and-scan exposure tool developed for the 150 nm generation lithography.

Laser treatment of plasma-hydrogenated silicon wafers for thin layer exfoliation

NASA Astrophysics Data System (ADS)

Ghica, Corneliu; Nistor, Leona Cristina; Teodorescu, Valentin Serban; Maraloiu, Adrian; Vizireanu, Sorin; Scarisoreanu, Nae Doinel; Dinescu, Maria

2011-03-01

We have studied by transmission electron microscopy the microstructural effects induced by pulsed laser annealing in comparison with thermal treatments of RF plasma hydrogenated Si wafers aiming for further application in the smart-cut procedure. While thermal annealing mainly produces a slight decrease of the density of plasma-induced planar defects and an increase of the size and number of plasma-induced nanocavities in the Si matrix, pulsed laser annealing of RF plasma hydrogenated Si wafers with a 355 nm wavelength radiation results in both the healing of defects adjacent to the wafer surface and the formation of a well defined layer of nanometric cavities at a depth of 25-50 nm. In this way, a controlled fracture of single crystal layers of Si thinner than 50 nm is favored.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Carbon mediated reduction of silicon dioxide and growth of copper silicide particles in uniform width channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pizzocchero, Filippo; Bøggild, Peter; Booth, Timothy J.

We show that surface arc-discharge deposited carbon plays a critical intermediary role in the breakdown of thermally grown oxide diffusion barriers of 90 nm on a silicon wafer at 1035 °C in an Ar/H{sub 2} atmosphere, resulting in the formation of epitaxial copper silicide particles in ≈ 10 μm wide channels, which are aligned with the intersections of the (100) surface of the wafer and the (110) planes on an oxidized silicon wafer, as well as endotaxial copper silicide nanoparticles within the wafer bulk. We apply energy dispersive x-ray spectroscopy, in combination with scanning and transmission electron microscopy of focusedmore » ion beam fabricated lammelas and trenches in the structure to elucidate the process of their formation.« less

Environmentally benign processing of YAG transparent wafers

NASA Astrophysics Data System (ADS)

Yang, Yan; Wu, Yiquan

2015-12-01

Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

Multiplexing of adjacent vortex modes with the forked grating coupler

NASA Astrophysics Data System (ADS)

Nadovich, Christopher T.; Kosciolek, Derek J.; Crouse, David T.; Jemison, William D.

2017-08-01

For vortex fiber multiplexing to reach practical commercial viability, simple silicon photonic interfaces with vortex fiber will be required. These interfaces must support multiplexing. Toward this goal, an efficient singlefed multimode Forked Grating Coupler (FGC) for coupling two different optical vortex OAM charges to or from the TE0 and TE1 rectangular waveguide modes has been developed. A simple, apodized device implemented with e-beam lithography and a conventional dual-etch processing on SOI wafer exhibits low crosstalk and reasonable mode match. Advanced designs using this concept are expected to further improve performance.

Process control systems: integrated for future process technologies

NASA Astrophysics Data System (ADS)

Botros, Youssry; Hajj, Hazem M.

2003-06-01

Process Control Systems (PCS) are becoming more crucial to the success of Integrated Circuit makers due to their direct impact on product quality, cost, and Fab output. The primary objective of PCS is to minimize variability by detecting and correcting non optimal performance. Current PCS implementations are considered disparate, where each PCS application is designed, deployed and supported separately. Each implementation targets a specific area of control such as equipment performance, wafer manufacturing, and process health monitoring. With Intel entering the nanometer technology era, tighter process specifications are required for higher yields and lower cost. This requires areas of control to be tightly coupled and integrated to achieve the optimal performance. This requirement can be achieved via consistent design and deployment of the integrated PCS. PCS integration will result in several benefits such as leveraging commonalities, avoiding redundancy, and facilitating sharing between implementations. This paper will address PCS implementations and focus on benefits and requirements of the integrated PCS. Intel integrated PCS Architecture will be then presented and its components will be briefly discussed. Finally, industry direction and efforts to standardize PCS interfaces that enable PCS integration will be presented.

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Organ-on-a-Chip for Aerospace Physiology and Toxicology

DTIC Science & Technology

2014-12-15

Products (Chicago, IL) supplied the Laboratory Corona Treater. Silicon wafers, 3” with > orientation were obtained from Wafer World Incorporated...was flowed at a process pressure of 500 mT. The plasma was ignited at discharge power of 250 W at 30 kHz and allowed to run for 1 minute. The wafer...slide and PDMS channel surfaces was performed one of two ways. Either using a handheld corona tool operated in a chemical safety hood or the PDMS slabs

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

NASA Technical Reports Server (NTRS)

Horowitz, Stephen; Chen, Tai-An; Chandrasekaran, Venkataraman; Tedjojuwono, Ken; Cattafesta, Louis; Nishida, Toshikazu; Sheplak, Mark

2004-01-01

This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Virtual optical interfaces for the transportation industry

NASA Astrophysics Data System (ADS)

Hejmadi, Vic; Kress, Bernard

2010-04-01

We present a novel implementation of virtual optical interfaces for the transportation industry (automotive and avionics). This new implementation includes two functionalities in a single device; projection of a virtual interface and sensing of the position of the fingers on top of the virtual interface. Both functionalities are produced by diffraction of laser light. The device we are developing include both functionalities in a compact package which has no optical elements to align since all of them are pre-aligned on a single glass wafer through optical lithography. The package contains a CMOS sensor which diffractive objective lens is optimized for the projected interface color as well as for the IR finger position sensor based on structured illumination. Two versions are proposed: a version which senses the 2d position of the hand and a version which senses the hand position in 3d.

Reflective optical imaging system with balanced distortion

DOEpatents

Chapman, Henry N.; Hudyma, Russell M.; Shafer, David R.; Sweeney, Donald W.

1999-01-01

An optical system compatible with short wavelength (extreme ultraviolet) An optical system compatible with short wavelength (extreme ultraviolet) radiation comprising four reflective elements for projecting a mask image onto a substrate. The four optical elements comprise, in order from object to image, convex, concave, convex and concave mirrors. The optical system is particularly suited for step and scan lithography methods. The invention enables the use of larger slit dimensions associated with ring field scanning optics, improves wafer throughput and allows higher semiconductor device density. The inventive optical system is characterized by reduced dynamic distortion because the static distortion is balanced across the slit width.

Scanning electron microscope automatic defect classification of process induced defects

NASA Astrophysics Data System (ADS)

Wolfe, Scott; McGarvey, Steve

2017-03-01

With the integration of high speed Scanning Electron Microscope (SEM) based Automated Defect Redetection (ADR) in both high volume semiconductor manufacturing and Research and Development (R and D), the need for reliable SEM Automated Defect Classification (ADC) has grown tremendously in the past few years. In many high volume manufacturing facilities and R and D operations, defect inspection is performed on EBeam (EB), Bright Field (BF) or Dark Field (DF) defect inspection equipment. A comma separated value (CSV) file is created by both the patterned and non-patterned defect inspection tools. The defect inspection result file contains a list of the inspection anomalies detected during the inspection tools' examination of each structure, or the examination of an entire wafers surface for non-patterned applications. This file is imported into the Defect Review Scanning Electron Microscope (DRSEM). Following the defect inspection result file import, the DRSEM automatically moves the wafer to each defect coordinate and performs ADR. During ADR the DRSEM operates in a reference mode, capturing a SEM image at the exact position of the anomalies coordinates and capturing a SEM image of a reference location in the center of the wafer. A Defect reference image is created based on the Reference image minus the Defect image. The exact coordinates of the defect is calculated based on the calculated defect position and the anomalies stage coordinate calculated when the high magnification SEM defect image is captured. The captured SEM image is processed through either DRSEM ADC binning, exporting to a Yield Analysis System (YAS), or a combination of both. Process Engineers, Yield Analysis Engineers or Failure Analysis Engineers will manually review the captured images to insure that either the YAS defect binning is accurately classifying the defects or that the DRSEM defect binning is accurately classifying the defects. This paper is an exploration of the feasibility of the utilization of a Hitachi RS4000 Defect Review SEM to perform Automatic Defect Classification with the objective of the total automated classification accuracy being greater than human based defect classification binning when the defects do not require multiple process step knowledge for accurate classification. The implementation of DRSEM ADC has the potential to improve the response time between defect detection and defect classification. Faster defect classification will allow for rapid response to yield anomalies that will ultimately reduce the wafer and/or the die yield.

Mask characterization for CDU budget breakdown in advanced EUV lithography

NASA Astrophysics Data System (ADS)

Nikolsky, Peter; Strolenberg, Chris; Nielsen, Rasmus; Nooitgedacht, Tjitte; Davydova, Natalia; Yang, Greg; Lee, Shawn; Park, Chang-Min; Kim, Insung; Yeo, Jeong-Ho

2012-11-01

As the ITRS Critical Dimension Uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and a high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. In this paper we will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for an advanced EUV lithography with 1D and 2D feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CD's and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples in this paper. Also mask stack reflectivity variations should be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We observed also MEEF-through-field fingerprints in the studied EUV cases. Variations of MEEF may also play a role for the total intrafield CDU and may be taken into account for EUV Lithography. We characterized MEEF-through-field for the reviewed features, the results to be discussed in our paper, but further analysis of this phenomenon is required. This comprehensive approach to characterization of the mask part of EUV CDU characterization delivers an accurate and integral CDU Budget Breakdown per product/process and Litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps to extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Mask characterization for critical dimension uniformity budget breakdown in advanced extreme ultraviolet lithography

NASA Astrophysics Data System (ADS)

Nikolsky, Peter; Strolenberg, Chris; Nielsen, Rasmus; Nooitgedacht, Tjitte; Davydova, Natalia; Yang, Greg; Lee, Shawn; Park, Chang-Min; Kim, Insung; Yeo, Jeong-Ho

2013-04-01

As the International Technology Roadmap for Semiconductors critical dimension uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. We will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for advanced extreme ultraviolet (EUV) lithography with 1D (dense lines) and 2D (dense contacts) feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CDs and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples. Mask stack reflectivity variations should also be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We also observed mask error enhancement factor (MEEF) through field fingerprints in the studied EUV cases. Variations of MEEF may play a role towards the total intrafield CDU and may need to be taken into account for EUV lithography. We characterized MEEF-through-field for the reviewed features, with results herein, but further analysis of this phenomenon is required. This comprehensive approach to quantifying the mask part of the overall EUV CDU contribution helps deliver an accurate and integral CDU BB per product/process and litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jankowski, A.F.; Hayes, J.P.; Kanna, R.L.

The formation of high energy density, storage devices is achievable using composite material systems. Alternate layering of carbon aerogel wafers and Ni foils with rnicroporous separators is a prospective composite for capacitor applications. An inherent problem exists to form a physical bond between Ni and the porous carbon wafer. The bonding process must be limited to temperatures less than 1000{degrees}C, at which point the aerogel begins to degrade. The advantage of a low temperature eutectic in the Ni-Ti alloy system solves this problem. Ti, a carbide former, is readily adherent as a sputter deposited thin film onto the carbon wafer.more » A vacuum bonding process is then used to join the Ni foil and Ti coating through eutectic phase formation. The parameters required for successfld bonding are described along with a structural characterization of the Ni foil-carbon aerogel wafer interface.« less

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

NASA Astrophysics Data System (ADS)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Grain-boundary type and distribution in silicon carbide coatings and wafers

NASA Astrophysics Data System (ADS)

Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

2018-03-01

Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

A randomized controlled trial to assess the pain associated with the debond of orthodontic fixed appliances

PubMed Central

Mangnall, Louise A R; Dietrich, Thomas; Scholey, John M

2013-01-01

Objective: To determine patient experience of pain during treatment with fixed orthodontic appliances, expectations of pain during debond and whether biting on a soft acrylic wafer during debond decreases pain experience. Design: Multicentre randomized controlled trial. Setting: Three UK hospital based orthodontic departments: Mid-Staffordshire NHS Foundation Trust, Birmingham Dental Hospital and University Hospital of North Staffordshire. Materials and methods: Ninety patients were randomly allocated to either the control (n = 45) or wafer group (n = 45). A visual analogue scale-based questionnaire was completed pre-debond to determine pain experience during treatment and expectations of pain during debond. The appliances were debonded and those in the wafer group bit on a soft acrylic wafer. A second questionnaire was completed post-debond to assess the pain experienced. Results: Biting on an acrylic wafer significantly reduced the pain experienced when debonding the posterior teeth (P≤0·05). Thirty-nine per cent found the lower anterior teeth the most painful. The expected pain was significantly greater than that actually experienced (P≤0·0001). Greater pain during treatment correlated with increased expectations and increased actually experienced pain (P≤0·0001). Conclusions: Biting on a soft acrylic wafer during debond of the posterior teeth reduces the pain experienced. The lower anterior teeth are the most painful. The pain expected is significantly greater than actually experienced. Patients who had greater pain during treatment expected and experienced greater pain at debond. PMID:24009318

Carmustine wafer implantation for high-grade gliomas: Evidence-based safety efficacy and practical recommendations from the Neuro-oncology Club of the French Society of Neurosurgery.

PubMed

Roux, A; Caire, F; Guyotat, J; Menei, P; Metellus, P; Pallud, J

2017-12-01

There is a growing body of evidence that carmustine wafer implantation during surgery is an effective therapeutic adjunct to the standard combined radio-chemotherapy regimen using temozolomide in newly diagnosed and recurrent high-grade glioma patient management with a statistically significant survival benefit demonstrated across several randomized clinical trials, as well as prospective and retrospective studies (grade A recommendation). Compelling clinical data also support the safety of carmustine wafer implantation (grade A recommendation) in these patients and suggest that observed adverse events can be avoided in experienced neurosurgeon hands. Furthermore, carmustine wafer implantation does not seem to impact negatively on the quality of life and the completion of adjuvant oncological treatments (grade C recommendation). Moreover, emerging findings support the potential of high-grade gliomas molecular status, especially the O(6)-Methylguanine-DNA Methyltransferase promoter methylation status, in predicting the efficacy of such a surgical strategy, especially at recurrence (grade B recommendation). Finally, carmustine wafer implantation appears to be cost-effective in high-grade glioma patients when performed by an experienced team and when total or subtotal resection can be achieved. Altogether, these data underline the current need for a new randomized clinical trial to assess the impact of a maximal safe resection with carmustine wafer implantation followed by the standard combined chemoradiation protocol stratified by molecular status in high-grade glioma patients. Copyright © 2017 Elsevier Masson SAS. All rights reserved.

Influence of the distance between target surface and focal point on the expansion dynamics of a laser-induced silicon plasma with spatial confinement

NASA Astrophysics Data System (ADS)

Zhang, Dan; Chen, Anmin; Wang, Xiaowei; Wang, Ying; Sui, Laizhi; Ke, Da; Li, Suyu; Jiang, Yuanfei; Jin, Mingxing

2018-05-01

Expansion dynamics of a laser-induced plasma plume, with spatial confinement, for various distances between the target surface and focal point were studied by the fast photography technique. A silicon wafer was ablated to induce the plasma with a Nd:YAG laser in an atmospheric environment. The expansion dynamics of the plasma plume depended on the distance between the target surface and focal point. In addition, spatially confined time-resolved images showed the different structures of the plasma plumes at different distances between the target surface and focal point. By analyzing the plume images, the optimal distance for emission enhancement was found to be approximately 6 mm away from the geometrical focus using a 10 cm focal length lens. This optimized distance resulted in the strongest compression ratio of the plasma plume by the reflected shock wave. Furthermore, the duration of the interaction between the reflected shock wave and the plasma plume was also prolonged.

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

Single-order, subwavelength resonant nanograting as a uniformly hot substrate for surface-enhanced Raman spectroscopy.

PubMed

Deng, Xuegong; Braun, Gary B; Liu, Sheng; Sciortino, Paul F; Koefer, Bob; Tombler, Thomas; Moskovits, Martin

2010-05-12

The surface-enhanced Raman spectroscopy (SERS) activity and the optical reflectance of a subwavelength gold nanograting fabricated entirely using top down technologies on silicon wafers are presented. The grating consists of 120 nm gold cladding on top of parallel silica nanowires constituting the grating's lines, with gaps between nanowires <10 nm wide at their narrowest point. The grating produces inordinately intense SERS and shows very strong polarization dependence. Reflectance measurements for the optimized grating indicate that (when p-polarization is used and at least one of the incident electric field components lies across the grating lines) the reflectance drops to <1% at resonance, indicating that essentially all of the radiant energy falling on the surface is coupled into the grating. The SERS intensity and the reflectance at resonance anticorrelate predicatively, suggesting that reflectance measurements can provide a nondestructive, wafer-level test of SERS efficacy. The SERS performance of the gratings is very uniform and reproducible. Extensive measurements on samples cut from both the same wafer and from different wafers, produce a SERS intensity distribution function that is similar to that obtained for ordinary Raman measurements carried out at multiple locations on a polished (100) silicon wafer.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muir, R.; Heebner, J.

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

PubMed Central

Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

2013-01-01

Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE PAGES

Muir, R.; Heebner, J.

2017-10-24

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

PubMed

Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

2012-07-15

The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

NASA Astrophysics Data System (ADS)

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

OPC model data collection for 45-nm technology node using automatic CD-SEM offline recipe creation

NASA Astrophysics Data System (ADS)

Fischer, Daniel; Talbi, Mohamed; Wei, Alex; Menadeva, Ovadya; Cornell, Roger

2007-03-01

Optical and Process Correction in the 45nm node is requiring an ever higher level of characterization. The greater complexity drives a need for automation of the metrology process allowing more efficient, accurate and effective use of the engineering resources and metrology tool time in the fab, helping to satisfy what seems an insatiable appetite for data by lithographers and modelers charged with development of 45nm and 32nm processes. The scope of the work referenced here is a 45nm design cycle "full-loop automation", starting with gds formatted target design layout and ending with the necessary feedback of one and two dimensional printed wafer metrology. In this paper the authors consider the key elements of software, algorithmic framework and Critical Dimension Scanning Electron Microscope (CDSEM) functionality necessary to automate its recipe creation. We evaluate specific problems with the methodology of the former art, "on-tool on-wafer" recipe construction, and discuss how the implementation of the design based recipe generation improves upon the overall metrology process. Individual target-by-target construction, use of a one pattern recognition template fits all approach, a blind navigation to the desired measurement feature, lengthy sessions on tool to construct recipes and limited ability to determine measurement quality in the resultant data set are each discussed as to how the state of the art Design Based Metrology (DBM) approach is implemented. The offline created recipes have shown pattern recognition success rates of up to 100% and measurement success rates of up to 93% for line/space as well as for 2D Minimum/Maximum measurements without manual assists during measurement.

Proceedings of the Low-Cost Solar Array Wafering Workshop

NASA Technical Reports Server (NTRS)

Morrison, A. D.

1982-01-01

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Lapped substrate for enhanced backsurface reflectivity in a thermophotovoltaic energy conversion system

DOEpatents

Baldasaro, Paul F; Brown, Edward J; Charache, Greg W; DePoy, David M

2000-01-01

A method for fabricating a thermophotovoltaic energy conversion cell including a thin semiconductor wafer substrate (10) having a thickness (.beta.) calculated to decrease the free carrier absorption on a heavily doped substrate; wherein the top surface of the semiconductor wafer substrate is provided with a thermophotovoltaic device (11), a metallized grid (12) and optionally an antireflective (AR) overcoating; and, the bottom surface (10') of the semiconductor wafer substrate (10) is provided with a highly reflecting coating which may comprise a metal coating (14) or a combined dielectric/metal coating (17).

Lapped substrate for enhanced backsurface reflectivity in a thermophotovoltaic energy conversion system

DOEpatents

Baldasaro, Paul F; Brown, Edward J; Charache, Greg W; DePoy, David M

2000-09-05

A method for fabricating a thermophotovoltaic energy conversion cell including a thin semiconductor wafer substrate (10) having a thickness (.beta.) calculated to decrease the free carrier absorption on a heavily doped substrate; wherein the top surface of the semiconductor wafer substrate is provided with a thermophotovoltaic device (11), a metallized grid (12) and optionally an antireflective (AR) overcoating; and, the bottom surface (10') of the semiconductor wafer substrate (10) is provided with a highly reflecting coating which may comprise a metal coating (14) or a combined dielectric/metal coating (17).

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Development of SiC Large Tapered Crystal Growth

NASA Technical Reports Server (NTRS)

Neudeck, Phil

2010-01-01

Majority of very large potential benefits of wide band gap semiconductor power electronics have NOT been realized due in large part to high cost and high defect density of commercial wafers. Despite 20 years of development, present SiC wafer growth approach is yet to deliver majority of SiC's inherent performance and cost benefits to power systems. Commercial SiC power devices are significantly de-rated in order to function reliably due to the adverse effects of SiC crystal dislocation defects (thousands per sq cm) in the SiC wafer.

Integral resonator gyroscope

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor); Challoner, A. Dorian (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor); Yee, Karl Y. (Inventor)

2008-01-01

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Method of producing an integral resonator sensor and case

NASA Technical Reports Server (NTRS)

Challoner, A. Dorian (Inventor); Yee, Karl Y. (Inventor); Shcheglov, Kirill V. (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor)

2005-01-01

The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

NASA Astrophysics Data System (ADS)

Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

2003-09-01

The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

DOEpatents

Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

2011-07-12

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Report on recent results of the PERCIVAL soft X-ray imager

NASA Astrophysics Data System (ADS)

Khromova, A.; Cautero, G.; Giuressi, D.; Menk, R.; Pinaroli, G.; Stebel, L.; Correa, J.; Marras, A.; Wunderer, C. B.; Lange, S.; Tennert, M.; Niemann, M.; Hirsemann, H.; Smoljanin, S.; Reza, S.; Graafsma, H.; Göttlicher, P.; Shevyakov, I.; Supra, J.; Xia, Q.; Zimmer, M.; Guerrini, N.; Marsh, B.; Sedgwick, I.; Nicholls, T.; Turchetta, R.; Pedersen, U.; Tartoni, N.; Hyun, H. J.; Kim, K. S.; Rah, S. Y.; Hoenk, M. E.; Jewell, A. D.; Jones, T. J.; Nikzad, S.

2016-11-01

The PERCIVAL (Pixelated Energy Resolving CMOS Imager, Versatile And Large) soft X-ray 2D imaging detector is based on stitched, wafer-scale sensors possessing a thick epi-layer, which together with back-thinning and back-side illumination yields elevated quantum efficiency in the photon energy range of 125-1000 eV. Main application fields of PERCIVAL are foreseen in photon science with FELs and synchrotron radiation. This requires high dynamic range up to 105 ph @ 250 eV paired with single photon sensitivity with high confidence at moderate frame rates in the range of 10-120 Hz. These figures imply the availability of dynamic gain switching on a pixel-by-pixel basis and a highly parallel, low noise analog and digital readout, which has been realized in the PERCIVAL sensor layout. Different aspects of the detector performance have been assessed using prototype sensors with different pixel and ADC types. This work will report on the recent test results performed on the newest chip prototypes with the improved pixel and ADC architecture. For the target frame rates in the 10-120 Hz range an average noise floor of 14e- has been determined, indicating the ability of detecting single photons with energies above 250 eV. Owing to the successfully implemented adaptive 3-stage multiple-gain switching, the integrated charge level exceeds 4 · 106 e- or 57000 X-ray photons at 250 eV per frame at 120 Hz. For all gains the noise level remains below the Poisson limit also in high-flux conditions. Additionally, a short overview over the updates on an oncoming 2 Mpixel (P2M) detector system (expected at the end of 2016) will be reported.

BCNU wafer placement with temozolomide (TMZ) in the immediate postoperative period after tumor resection followed by radiation therapy with TMZ in patients with newly diagnosed high grade glioma: final results of a prospective, multi-institutional, phase II trial.

PubMed

Burri, Stuart H; Prabhu, Roshan S; Sumrall, Ashley L; Brick, Wendy; Blaker, Brian D; Heideman, Brent E; Boltes, Peggy; Kelly, Renee; Symanowski, James T; Wiggins, Walter F; Ashby, Lynn; Norton, H James; Judy, Kevin; Asher, Anthony L

2015-06-01

Temozolomide (TMZ) and BCNU have demonstrated anti-glioma synergism in preclinical models. We report final data from a prospective, multi-institutional study of BCNU wafers and early TMZ followed by radiation therapy with TMZ in patients with newly diagnosed malignant glioma. 65 patients were consented in 4 institutions, and 46 patients (43 GBM, 3 AA) were eligible for analysis. After resection and BCNU wafer placement, TMZ began on day four postoperatively. Radiation and TMZ (RT/TMZ) were then administered, followed by monthly TMZ at 200 mg/m2 for the first 26 patients, which was reduced to 150 mg/m2 for the remaining 20 patients. Non-hematologic toxicities were minimal. Nine of 27 patients (33 %) who received 200 mg/m2 TMZ, but only 1 of 20 (5 %) who received 150 mg/m2, experienced grade 3/4 thrombocytopenia. Median progression free survival (PFS) and overall survival (OS) period was 8.5 and 18 months, respectively. The 1-year OS rate was 76 %, which is a significant improvement compared with the historical control 1-year OS rate of 59 % (p = 0.023). However, there was no difference in 1-year OS compared with standard RT/TMZ (p = 0.12) or BCNU wafer followed by RT/TMZ (p = 0.87) in post hoc analyses. Early post-operative TMZ can be safely administered with BCNU wafers following resection of malignant glioma at the 150 mg/m2 dose level. Although there was an OS benefit compared to historical control, there was no indication of benefit for BCNU wafers and early TMZ in addition to standard RT/TMZ or early TMZ in addition to regimens of BCNU wafers followed by RT/TMZ.

SiC Seeded Crystal Growth

NASA Astrophysics Data System (ADS)

Glass, R. C.; Henshall, D.; Tsvetkov, V. F.; Carter, C. H., Jr.

1997-07-01

The availability of relatively large (30 mm) SiC wafers has been a primary reason for the renewed high level of interest in SiC semiconductor technology. Projections that 75 mm SiC wafers will be available in 2 to 3 years have further peaked this interest. Now both 4H and 6H polytypes are available, however, the micropipe defects that occur to a varying extent in all wafers produced to date are seen by many as preventing the commercialization of many types of SiC devices, especially high current power devices. Most views on micropipe formation are based around Frank's theory of a micropipe being the hollow core of a screw dislocation with a huge Burgers vector (several times the unit cell) and with the diameter of the core having a direct relationship with the magnitude of the Burgers vector. Our results show that there are several mechanisms or combinations of these mechanisms which cause micropipes in SiC boules grown by the seeded sublimation method. Additional considerations such as polytype variations, dislocations and both impurity and diameter control add to the complexity of producing high quality wafers. Recent results at Cree Research, Inc., including wafers with micropipe densities of less than 1 cm - 2 (with 1 cm2 areas void of micropipes), indicate that micropipes will be reduced to a level that makes high current devices viable and that they may be totally eliminated in the next few years. Additionally, efforts towards larger diameter high quality substrates have led to production of 50 mm diameter 4H and 6H wafers for fabrication of LEDs and the demonstration of 75 mm wafers. Low resistivity and semi-insulating electrical properties have also been attained through improved process and impurity control. Although challenges remain, the industry continues to make significant progress towards large volume SiC-based semiconductor fabrication.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Multiple internal seal right micro-electro-mechanical system vacuum package

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor); Wiberg, Dean V. (Inventor); Hayworth, Ken J. (Inventor); Yee, Karl Y. (Inventor); Bae, Youngsam (Inventor); Challoner, A. Dorian (Inventor); Peay, Chris S. (Inventor)

2007-01-01

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

PubMed

Nativ, Amit; Feldman, Haim; Shaked, Natan T

2018-05-01

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

NASA Technical Reports Server (NTRS)

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.;

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Piezoelectric Vibrational and Acoustic Alert for a Personal Communication Device

NASA Technical Reports Server (NTRS)

Woodard, Stanley E. (Inventor); Hellbaum, Richard F. (Inventor); Daugherty, Robert H. (Inventor); Scholz, Raymond C. (Inventor); Little, Bruce D. (Inventor); Fox, Robert L. (Inventor); Denhardt, Gerald A. (Inventor); Jang, SeGon (Inventor); Balein, Rizza (Inventor)

2001-01-01

An alert apparatus for a personal communication device includes a mechanically prestressed piezoelectric wafer positioned within the personal communication device and an alternating voltage input line coupled at two points of the wafer where polarity is recognized. The alert apparatus also includes a variable frequency device coupled to the alternating voltage input line, operative to switch the alternating voltage on the alternating voltage input line at least between an alternating voltage having a first frequency and an alternating voltage having a second frequency. The first frequency is preferably sufficiently high so as to cause the wafer to vibrate at a resulting frequency that produces a sound perceptible by a human ear, and the second frequency is preferably sufficiently low so as to cause the wafer to vibrate at a resulting frequency that produces a vibration readily felt by a holder of the personal communication device.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

NASA Astrophysics Data System (ADS)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Design and use of multiple blade slurry sawing in a production atmosphere

NASA Technical Reports Server (NTRS)

Lynah, F. P., Jr.; Ross, J. B.

1982-01-01

The technique and uses of the multiple blade slurry (MBS) saw are considered. Multiple bands of steel are arranged in a frame and the frame is reciprocated with the steel bands to a workpiece, while simultaneously applying abrasive at the point of contact. The blades wear slots in the workpiece and progress through the piece resulting in several parts of wafers. The transition to MBA from diamond slicing is justified by savings resulting from minimized kerf losses, minimized subsurface damage, and improved surface quality off the saw. This allows wafering much closer to finished thickness specifications. The current state of the art MBS technology must be significantly improved if the low cost solar array (LSA) goals are to be attained. It is concluded that although MBS will never be the answer to every wafering requirement, the economical production of wafers to LSA project specifications will be achieved.

Multiple internal seal ring micro-electro-mechanical system vacuum packaging method

NASA Technical Reports Server (NTRS)

Hayworth, Ken J. (Inventor); Yee, Karl Y. (Inventor); Shcheglov, Kirill V. (Inventor); Bae, Youngsam (Inventor); Wiberg, Dean V. (Inventor); Challoner, A. Dorian (Inventor); Peay, Chris S. (Inventor)

2008-01-01

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

NASA Astrophysics Data System (ADS)

Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

2001-07-01

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

Sub-Kelvin resistance thermometer

NASA Technical Reports Server (NTRS)

Castles, Stephen H. (Inventor)

1992-01-01

A device capable of accurate temperature measurement down to 0.01 K of a particular object is discussed. The device is comprised of the following: a heat sink wafer; a first conducting pad bonded near one end of the heat sink wafer; a second conducting pad bonded near the other end of the heat sink wafer; and an oblong doped semiconductor crystal such as germanium. The oblong doped semiconductor crystal has a third conducting pad bonded on its bottom surface with the oblong doped semiconductor crystal bonded to the heat sink wafer by having the fourth conducting pad bonded to the first conducting pad. A wire is bonded between the second and third conducting pads. Current and voltage wires bonded to the first and second conducting pads measure the change in resistance of the oblong doped semiconductor crystal; this indicates the temperature of the object whose temperature is to be measured.

Fluxless eutectic bonding of GaAs-on-Si by using Ag/Sn solder

NASA Astrophysics Data System (ADS)

Eo, Sung-Hwa; Kim, Dae-Seon; Jeong, Ho-Jung; Jang, Jae-Hyung

2013-11-01

Fluxless GaAs-on-Si wafer bonding using Ag/Sn solder was investigated to realize uniform and void-free heterogeneous material integration. The effects of the diffusion barrier, Ag/Sn thickness, and Ar plasma treatment were studied to achieve the optimal fluxless bonding process. Pt on a GaAs wafer and Mo on a Si wafer act as diffusion barriers by preventing the flow of Ag/Sn solder into both the wafers. The bonding strength is closely related to the Ag/Sn thickness and Ar plasma treatment. A shear strength test was carried out to investigate the bonding strength. Under identical bonding conditions, the Ag/Sn thickness was optimized to achieve higher bonding strength and to avoid the formation of voids due to thermal stress. An Ar plasma pretreatment process improved the bonding strength because the Ar plasma removed carbon contaminants and metal-oxide bonds from the metal surface.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Solid state photomultiplier for astronomy, phase 2

NASA Technical Reports Server (NTRS)

Besser, P. J.; Hays, K. M.; Laviolette, R. A.

1989-01-01

Epitaxial layers with varying donor concentration profiles were grown on silicon substrate wafers using chemical vapor deposition (CVD) techniques, and solid state photomultiplier (SSPM) devices were fabricated from the wafers. Representative detectors were tested in a low background photon flux, low temperature environment to determine the device characteristics for comparison to NASA goals for astronomical applications. The SSPM temperatures varied between 6 and 11 K with background fluxes in the range from less than 5 x 10 to the 6th power to 10 to the 13th power photons/square cm per second at wavelengths of 3.2 and 20 cm. Measured parameters included quantum efficiency, dark count rate and bias current. Temperature for optimal performance is 10 K, the highest ever obtained for SSPMs. The devices exhibit a combination of the lowest dark current and highest quantum efficiency yet achieved. Experimental data were reduced, analyzed and used to generate recommendations for future studies. The background and present status of the microscopic theory of SSPM operation were reviewed and summarized. Present emphasis is on modeling of the avalanche process which is the basis for SSPM operation. Approaches to the solution of the Boltzmann transport equation are described and the treatment of electron scattering mechanisms is presented. The microscopic single-electron transport theory is ready to be implemented for large-scale computations.

Advanced FTIR technology for the chemical characterization of product wafers

NASA Astrophysics Data System (ADS)

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

PubMed Central

Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

2012-01-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

PubMed

Gurun, Gokce; Hasler, Paul; Degertekin, F

2011-08-01

This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

Extended vertical range roughness measurements in non-ideal environments

NASA Astrophysics Data System (ADS)

Creath, Katherine

2011-09-01

This paper describes recent research into developing an extended range dynamic interferometry technique where the range is extended vertically to enhance surface roughness measurements made in non-ideal environments. Utilizing short pulses from two sources on either side of a frame transfer in a CCD sensor, data can be taken fast enough in noisy shop environments to make measurements in the presence of vibration, and air turbulence. A key application of this technique is monitoring of surface roughness of large optics during the polishing process by making in situ measurements from fine grind through to the final polish. It is anticipated that this monitoring can help speed up what is now a very lengthy process. This same technique is applicable to many other types of measurements including MEMS devices, as it is not affected by dispersion in windows covering devices, and for measuring features on flat panel display glass or semiconductor wafers. This paper describes the technique, and presents results of a variety of sample measurements including: bare glass in various states of polish from fine grind to final polish, scratches and pits in a roughened semiconductor wafer, a DMD MEMS device, and various calibration standards. Performance in terms of repeatabilitity of step heights and roughness for this proof of concept is in the +/-2% range.

Very-large-area CCD image sensors: concept and cost-effective research

NASA Astrophysics Data System (ADS)

Bogaart, E. W.; Peters, I. M.; Kleimann, A. C.; Manoury, E. J. P.; Klaassens, W.; de Laat, W. T. F. M.; Draijer, C.; Frost, R.; Bosiers, J. T.

2009-01-01

A new-generation full-frame 36x48 mm2 48Mp CCD image sensor with vertical anti-blooming for professional digital still camera applications is developed by means of the so-called building block concept. The 48Mp devices are formed by stitching 1kx1k building blocks with 6.0 µm pixel pitch in 6x8 (hxv) format. This concept allows us to design four large-area (48Mp) and sixty-two basic (1Mp) devices per 6" wafer. The basic image sensor is relatively small in order to obtain data from many devices. Evaluation of the basic parameters such as the image pixel and on-chip amplifier provides us statistical data using a limited number of wafers. Whereas the large-area devices are evaluated for aspects typical to large-sensor operation and performance, such as the charge transport efficiency. Combined with the usability of multi-layer reticles, the sensor development is cost effective for prototyping. Optimisation of the sensor design and technology has resulted in a pixel charge capacity of 58 ke- and significantly reduced readout noise (12 electrons at 25 MHz pixel rate, after CDS). Hence, a dynamic range of 73 dB is obtained. Microlens and stack optimisation resulted in an excellent angular response that meets with the wide-angle photography demands.

Variability aware compact model characterization for statistical circuit design optimization

NASA Astrophysics Data System (ADS)

Qiao, Ying; Qian, Kun; Spanos, Costas J.

2012-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

NASA Technical Reports Server (NTRS)

Anthony, Thomas R. (Inventor)

1983-01-01

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.