OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

NASA Astrophysics Data System (ADS)

Khade, R. H.; Chaudhari, D. S.

2018-03-01

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen-Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.

Stress-dependent voltage offsets from polymer insulators used in rock mechanics and material testing

NASA Astrophysics Data System (ADS)

Carlson, G. G.; Dahlgren, R.; Vanderbilt, V. C.; Johnston, M. J.; Dunson, C.; Gray, A.; Freund, F.

2013-12-01

Dielectric insulators are used in a variety of laboratory settings when performing experiments in rock mechanics, petrology, and electromagnetic studies of rocks in the fields of geophysics, material science, and civil engineering. These components may be used to electrically isolate geological samples from the experimental equipment, to perform a mechanical compliance function between brittle samples and the loading equipment, to match ultrasonic transducers, or perform other functions. In many experimental configurations the insulators bear the full brunt of force applied to the sample but do not need to withstand high voltages, therefore the insulators are often thin sheets of mechanically tough polymers. From an instrument perspective, transduction from various types of mechanical perturbation has been qualitatively compared for a number of polymers [1, 2] and these error sources are readily apparent during high-impedance measurements if not mitigated. However even when following best practices, a force-dependent voltage signal still remains and its behavior is explored in this presentation. In this experiment two thin sheets (0.25 mm) of high-density polyethylene (HDPE) were set up in a stack, held alternately between three aluminum bars; this stack was placed on the platen of a 60T capacity hydraulic testing machine. The surface area, A, over which the force is applied to the PE sheets in this sandwich is roughly 40 square cm, each sheet forming a parallel-plate capacitor having roughly 320 pF [3], assuming the relative dielectric permittivity of PE is ~2.3. The outer two aluminum bars were connected to the LO input of the electrometer and the central aluminum bar was connected to the HI input of a Keithley model 617 electrometer. Once the stack is mechanically well-seated with no air gaps, the voltage offset is observed to be a linear function of the baseline voltage for a given change in applied force. For a periodically applied force of 66.7 kN the voltage offsets were measured as a function of initial voltage, and these data were fit with a linear function that was constrained to pass through the origin. The best fit solution had a correlation coefficient of R = 0.85 and a slope of approximately -0.0228 volts/volt. The voltage offset when normalized is demonstrated to be constant -2.28 % for both positive and negative polarities over nearly 3 orders of baseline voltage magnitude. From this, the voltage-force coefficient is derived to be -0.34 ppm/N. This correlates well to a first-order parallel plate capacitor model that assumes constant area, and small deformation such that the polymer may be mechanically modeled by a spring that obeys Hooke's law. This simple model predicts that the coefficient of proportionality is a function of Young's modulus E = 0.8 GPa and surface area of the insulator, theoretically -1/EA = -0.31 ppm/N. The outcome of this work is an improved insulator made from ultra-high molecular weight (UHMW) polyethylene and other approaches toward the minimization of and compensation for these experimental artifacts. References: [1] Keithley Instruments, Low level measurements handbook, 'Choosing the best insulator,' 2-11 (2004). [2] Ibid., 2-26. [3] A. Skumiel, 'How to transform mechanical work into electrical energy using a capacitor,' European Journal of Physics 32, 625-630 (2011).

Redox artifacts in electrophysiological recordings

PubMed Central

Berman, Jonathan M.

2013-01-01

Electrophysiological techniques make use of Ag/AgCl electrodes that are in direct contact with cells or bath. In the bath, electrodes are exposed to numerous experimental conditions and chemical reagents that can modify electrode voltage. We examined voltage offsets created in Ag/AgCl electrodes by exposure to redox reagents used in electrophysiological studies. Voltage offsets were measured in reference to an electrode separated from the solution by an agar bridge. The reducing reagents Tris-2-carboxyethly-phosphine, dithiothreitol (DTT), and glutathione, as well as the oxidizing agent H2O2 used at experimentally relevant concentrations reacted with Ag in the electrodes to produce voltage offsets. Chloride ions and strong acids and bases produced offsets at millimolar concentrations. Electrolytic depletion of the AgCl layer, to replicate voltage clamp and sustained use, resulted in increased sensitivity to flow and DTT. Offsets were sensitive to electrode silver purity and to the amount and method of chloride deposition. For example, exposure to 10 μM DTT produced a voltage offset between 10 and 284 mV depending on the chloride deposition method. Currents generated by these offsets are significant and dependent on membrane conductance and by extension the expression of ion channels and may therefore appear to be biological in origin. These data demonstrate a new source of artifacts in electrophysiological recordings that can affect measurements obtained from a variety of experimental techniques from patch clamp to two-electrode voltage clamp. PMID:23344161

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

PubMed Central

Rahman, Labonnah Farzana; Reaz, Mamun Bin Ibne; Yin, Chia Chieu; Ali, Mohammad Alauddin Mohammad; Marufuzzaman, Mohammad

2014-01-01

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. PMID:25299266

Temperature Induced Voltage Offset Drifts in Silicon Carbide Pressure Sensors

NASA Technical Reports Server (NTRS)

Okojie, Robert S.; Lukco, Dorothy; Nguyen, Vu; Savrun, Ender

2012-01-01

We report the reduction of transient drifts in the zero pressure offset voltage in silicon carbide (SiC) pressure sensors when operating at 600 C. The previously observed maximum drift of +/- 10 mV of the reference offset voltage at 600 C was reduced to within +/- 5 mV. The offset voltage drifts and bridge resistance changes over time at test temperature are explained in terms of the microstructure and phase changes occurring within the contact metallization, as analyzed by Auger electron spectroscopy and field emission scanning electron microscopy. The results have helped to identify the upper temperature reliable operational limit of this particular metallization scheme to be 605 C.

Onboard electrical calibration of the ASTER VNIR

NASA Astrophysics Data System (ADS)

Sakuma, Fumihiro; Kikuchi, Masakuni; Inada, Hitomi

2013-10-01

The Advanced Space-borne Thermal Emission and Reflection Radiometer (ASTER) is one of the five sensors on the NASA's Terra satellite on orbit since December 1999. ASTER consists of three radiometers, the Visible and Near InfraRed (VNIR), the Short-Wave InfraRed (SWIR) and Thermal InfraRed (TIR) whose spatial resolutions are 15 m, 30 m and 90 m, respectively. Unfortunately the SWIR image data are saturated since April 2008 due to the offset rise caused by the cooler temperature rise, but the VNIR and the TIR are taking Earth images of good quality. The VNIR and the TIR experienced responsivity degradation while the SWIR showed little change. From the lamp calibration, Band 1 decreased the most among three VNIR bands and 31% in thirteen years. The VNIR has the electrical calibration mode to check the healthiness of the electrical circuits through the charge coupled device (CCD). Four voltage levels from Line 1 to Line 4, which are from 2.78 V to 3.10 V, are input to the CCD in the onboard calibration sequence and the output digital numbers (DNs) are detected in the images. These input voltages are monitored as telemetry data and have been stable up to now. From the electrical calibration we can check stabilities of the offset, gain ratio and gain stability of the electric circuit. The output level of the Line1 input is close to the offset level which is measured while observing the earth at night. The trend of the Line 1 output is compared to the offset level. They are similar but are not exactly the same. The trend of the even pixel and odd pixel is the same so the saturated offset levels of the odd pixel is corrected by using the even pixel trend. The gain ratio trend shows that the ratio is stable. But the ratio values are different from those measured before launch. The difference comes up to 10% for the Band 2. The correct gain ratio should be applied to the vicarious calibration result because the onboard calibration is measured with the Normal gain whereas the vicarious calibration often measures with the High gain. The cause of the VNIR responsivity degradation is not known but one of the causes might be the change of the electric circuit. The band 3 gain shows 16 % decrease whereas the gain changes of the band 1 and band 2 are 5% to 8%. The responsivity decrease after 1000 days since launch might be controlled by the electric circuit change.

Zero-bias offsets in I-V characteristics of the staircase type quantum well infrared photodetectors

NASA Astrophysics Data System (ADS)

Nutku, Ferhat; Erol, Ayse; Arikan, M. Cetin; Ergun, Yuksel

2014-11-01

In this work, observed zero-bias offsets in I-V characteristics and differences in J-V characteristics of staircase quantum well infrared photodetectors were investigated. Temperature and voltage sweep rate dependence of the zero-bias offsets were studied on mesa structures shaped in different diameters. Furthermore, effect of mesa diameter on J-V characteristics was investigated. The temperature, initial bias voltage and voltage sweep rate dependence of the zero-bias offsets were explained by a qualitative model, which is based on a RC equivalent circuit of the quantum well infrared photodetector.

AC coupled three op-amp biopotential amplifier with active DC suppression.

PubMed

Spinelli, E M; Mayosky, M A

2000-12-01

A three op-amps instrumentation amplifier (I.A) with active dc suppression is presented. dc suppression is achieved by means of a controlled floating source at the input stage, to compensate electrode and op-amps offset voltages. This isolated floating source is built around an optical-isolated device using a general-purpose optocoupler, working as a photovoltaic generator. The proposed circuit has many interesting characteristics regarding simplicity and cost, while preserving common mode rejection ratio (CMRR) and high input impedance characteristics of the classic three op-amps I.A. As an example, a biopotential amplifier with a gain of 80 dB, a lower cutoff frequency of 0.1 Hz, and a dc input range of +/- 8 mV was built and tested. Using general-purpose op-amps, a CMRR of 105 was achieved without trimmings.

Frequency-Offset Cartesian Feedback Based on Polyphase Difference Amplifiers

PubMed Central

Zanchi, Marta G.; Pauly, John M.; Scott, Greig C.

2010-01-01

A modified Cartesian feedback method called “frequency-offset Cartesian feedback” and based on polyphase difference amplifiers is described that significantly reduces the problems associated with quadrature errors and DC-offsets in classic Cartesian feedback power amplifier control systems. In this method, the reference input and feedback signals are down-converted and compared at a low intermediate frequency (IF) instead of at DC. The polyphase difference amplifiers create a complex control bandwidth centered at this low IF, which is typically offset from DC by 200–1500 kHz. Consequently, the loop gain peak does not overlap DC where voltage offsets, drift, and local oscillator leakage create errors. Moreover, quadrature mismatch errors are significantly attenuated in the control bandwidth. Since the polyphase amplifiers selectively amplify the complex signals characterized by a +90° phase relationship representing positive frequency signals, the control system operates somewhat like single sideband (SSB) modulation. However, the approach still allows the same modulation bandwidth control as classic Cartesian feedback. In this paper, the behavior of the polyphase difference amplifier is described through both the results of simulations, based on a theoretical analysis of their architecture, and experiments. We then describe our first printed circuit board prototype of a frequency-offset Cartesian feedback transmitter and its performance in open and closed loop configuration. This approach should be especially useful in magnetic resonance imaging transmit array systems. PMID:20814450

A 4 GHz phase locked loop design in 65 nm CMOS for the Jiangmen Underground Neutrino Observatory detector

NASA Astrophysics Data System (ADS)

Parkalian, N.; Robens, M.; Grewing, C.; Christ, V.; Kruth, A.; Liebau, D.; Muralidharan, P.; Nielinger, D.; Roth, C.; Yegin, U.; Zambanini, A.; van Waasen, S.

2018-02-01

This paper presents a 4 GHz phase locked loop (PLL), which is implemented in a 65 nm standard CMOS process to provide low noise and high frequency sampling clocks for readout electronics to be used in the Jiangmen Underground Neutrino Observatory (JUNO) experiment. Based on the application requirements the target of the design is to find the best compromise between power consumption, area and phase noise for a highly reliable topology. The design implements a novel method for the charge pump that suppresses current mismatch when the PLL is locked. This reduces static phase offset at the inputs of the phase-frequency detector (PFD) that otherwise would introduce spurs at the PLL output. In addition, a technique of amplitude regulation for the voltage controlled oscillator (VCO) is presented to provide low noise and reliable operation. The combination of thin and thick oxide varactor transistors ensures optimum tuning range and linearity over process as well as temperature changes for the VCO without additional calibration steps. The current mismatch at the output of the charge pump for the control voltage at about half the 1 V supply voltage is below 0.3% and static phase offset down to 0.25% is reached. The total PLL consumes 18.5 mW power at 1.8 V supply for the VCO and 1 V supply for the other parts.

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor.

PubMed

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-06-14

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 V RMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame.

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor

PubMed Central

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-01-01

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame. PMID:28613250

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

PubMed Central

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-01-01

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

PubMed

Huang, Haiyun; Wang, Dejun; Xu, Yue

2015-10-27

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Study of mechanism of stress-induced threshold voltage shift and recovery in top-gate amorphous-InGaZnO4 thin-film transistors with source- and drain-offsets

NASA Astrophysics Data System (ADS)

Mativenga, Mallory; Kang, Dong Han; Lee, Ung Gi; Jang, Jin

2012-09-01

Bias instability of top-gate amorphous-indium-gallium-zinc-oxide thin-film transistors with source- and drain-offsets is reported. Positive and negative gate bias-stress (VG_STRESS) respectively induce reversible negative threshold-voltage shift (ΔVTH) and reduction in on-current. Migration of positive charges towards the offsets lowers the local resistance of the offsets, resulting in the abnormal negative ΔVTH under positive VG_STRESS. The reduction in on-current under negative VG_STRESS is due to increase in resistance of the offsets when positive charges migrate away from the offsets. Appropriate drain and source bias-stresses applied simultaneously with VG_STRESS either suppress or enhance the instability, verifying lateral ion migration to be the instability mechanism.

Method and system for controlling a synchronous machine over full operating range

DOEpatents

Walters, James E.; Gunawan, Fani S.; Xue, Yanhong

2002-01-01

System and method for controlling a synchronous machine are provided. The method allows for calculating a stator voltage index. The method further allows for relating the magnitude of the stator voltage index against a threshold voltage value. An offset signal is generated based on the results of the relating step. A respective state of operation of the machine is determined. The offset signal is processed based on the respective state of the machine.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Note: Rapid offset reduction of impedance bridges taking into account instrumental damping and phase shifting.

PubMed

van der Wel, C M; Kortschot, R J; Bakelaar, I A; Erné, B H; Kuipers, B W M

2013-03-01

The sensitivity of an imperfectly balanced impedance bridge is limited by the remaining offset voltage. Here, we present a procedure for offset reduction in impedance measurements using a lock-in amplifier, by applying a complex compensating voltage external to the bridge. This procedure takes into account instrumental damping and phase shifting, which generally occur at the high end of the operational frequency range. Measurements demonstrate that the output of the circuit rapidly converges to the instrumentally limited noise at any frequency.

Electrometer Amplifier With Overload Protection

NASA Technical Reports Server (NTRS)

Woeller, F. H.; Alexander, R.

1986-01-01

Circuit features low noise, input offset, and high linearity. Input preamplifier includes input-overload protection and nulling circuit to subtract dc offset from output. Prototype dc amplifier designed for use with ion detector has features desirable in general laboratory and field instrumentation.

Temperature and Voltage Offsets in High- ZT Thermoelectrics

NASA Astrophysics Data System (ADS)

Levy, George S.

2018-06-01

Thermodynamic temperature can take on different meanings. Kinetic temperature is an expectation value and a function of the kinetic energy distribution. Statistical temperature is a parameter of the distribution. Kinetic temperature and statistical temperature, identical in Maxwell-Boltzmann statistics, can differ in other statistics such as those of Fermi-Dirac or Bose-Einstein when a field is present. Thermal equilibrium corresponds to zero statistical temperature gradient, not zero kinetic temperature gradient. Since heat carriers in thermoelectrics are fermions, the difference between these two temperatures may explain voltage and temperature offsets observed during meticulous Seebeck measurements in which the temperature-voltage curve does not go through the origin. In conventional semiconductors, temperature offsets produced by fermionic electrical carriers are not observable because they are shorted by heat phonons in the lattice. In high- ZT materials, however, these offsets have been detected but attributed to faulty laboratory procedures. Additional supporting evidence for spontaneous voltages and temperature gradients includes data collected in epistatic experiments and in the plasma Q-machine. Device fabrication guidelines for testing the hypothesis are suggested including using unipolar junctions stacked in a superlattice, alternating n/ n + and p/ p + junctions, selecting appropriate dimensions, doping, and loading.

Temperature and Voltage Offsets in High-ZT Thermoelectrics

NASA Astrophysics Data System (ADS)

Levy, George S.

2017-10-01

Thermodynamic temperature can take on different meanings. Kinetic temperature is an expectation value and a function of the kinetic energy distribution. Statistical temperature is a parameter of the distribution. Kinetic temperature and statistical temperature, identical in Maxwell-Boltzmann statistics, can differ in other statistics such as those of Fermi-Dirac or Bose-Einstein when a field is present. Thermal equilibrium corresponds to zero statistical temperature gradient, not zero kinetic temperature gradient. Since heat carriers in thermoelectrics are fermions, the difference between these two temperatures may explain voltage and temperature offsets observed during meticulous Seebeck measurements in which the temperature-voltage curve does not go through the origin. In conventional semiconductors, temperature offsets produced by fermionic electrical carriers are not observable because they are shorted by heat phonons in the lattice. In high-ZT materials, however, these offsets have been detected but attributed to faulty laboratory procedures. Additional supporting evidence for spontaneous voltages and temperature gradients includes data collected in epistatic experiments and in the plasma Q-machine. Device fabrication guidelines for testing the hypothesis are suggested including using unipolar junctions stacked in a superlattice, alternating n/n + and p/p + junctions, selecting appropriate dimensions, doping, and loading.

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

PubMed Central

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording.

PubMed

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-05-19

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

PubMed Central

Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

2016-01-01

High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter. PMID:27213382

An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

NASA Astrophysics Data System (ADS)

Fessler, P.; Coffin, J.; Eberlé, H.; de Raad Iseli, C.; Hilt, B.; Huss, D.; Krummenacher, F.; Lutz, J. R.; Prévot, G.; Renouprez, A.; Sigward, M. H.; Schwaller, B.; Voltolini, C.

1999-01-01

Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 μs and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent.

Methods, systems and apparatus for controlling operation of two alternating current (AC) machines

DOEpatents

Gallegos-Lopez, Gabriel [Torrance, CA; Nagashima, James M [Cerritos, CA; Perisic, Milun [Torrance, CA; Hiti, Silva [Redondo Beach, CA

2012-02-14

A system is provided for controlling two AC machines. The system comprises a DC input voltage source that provides a DC input voltage, a voltage boost command control module (VBCCM), a five-phase PWM inverter module coupled to the two AC machines, and a boost converter coupled to the inverter module and the DC input voltage source. The boost converter is designed to supply a new DC input voltage to the inverter module having a value that is greater than or equal to a value of the DC input voltage. The VBCCM generates a boost command signal (BCS) based on modulation indexes from the two AC machines. The BCS controls the boost converter such that the boost converter generates the new DC input voltage in response to the BCS. When the two AC machines require additional voltage that exceeds the DC input voltage required to meet a combined target mechanical power required by the two AC machines, the BCS controls the boost converter to drive the new DC input voltage generated by the boost converter to a value greater than the DC input voltage.

Effect of Energy Input on Microstructure and Mechanical Properties of Titanium Aluminide Alloy Fabricated by the Additive Manufacturing Process of Electron Beam Melting

PubMed Central

Mohammad, Ashfaq; Alahmari, Abdulrahman M.; Mohammed, Muneer Khan; Renganayagalu, Ravi Kottan; Moiduddin, Khaja

2017-01-01

Titanium aluminides qualify adequately for advanced aero-engine applications in place of conventional nickel based superalloys. The combination of high temperature properties and lower density gives an edge to the titanium aluminide alloys. Nevertheless, challenges remain on how to process these essentially intermetallic alloys in to an actual product. Electron Beam Melting (EBM), an Additive Manufacturing Method, can build complex shaped solid parts from a given feedstock powder, thus overcoming the shortcomings of the conventional processing techniques such as machining and forging. The amount of energy supplied by the electron beam has considerable influence on the final build quality in the EBM process. Energy input is decided by the beam voltage, beam scan speed, beam current, and track offset distance. In the current work, beam current and track offset were varied to reflect three levels of energy input. Microstructural and mechanical properties were evaluated for these samples. The microstructure gradually coarsened from top to bottom along the build direction. Whereas higher energy favored lath microstructure, lower energy tended toward equiaxed grains. Computed tomography analysis revealed a greater amount of porosity in low energy samples. In addition, the lack of bonding defects led to premature failure in the tension test of low energy samples. Increase in energy to a medium level largely cancelled out the porosity, thereby increasing the strength. However, this trend did not continue with the high energy samples. Electron microscopy and X-ray diffraction investigations were carried out to understand this non-linear behavior of the strength in the three samples. Overall, the results of this work suggest that the input energy should be considered primarily whenever any new alloy system has to be processed through the EBM route. PMID:28772572

Effect of Energy Input on Microstructure and Mechanical Properties of Titanium Aluminide Alloy Fabricated by the Additive Manufacturing Process of Electron Beam Melting.

PubMed

Mohammad, Ashfaq; Alahmari, Abdulrahman M; Mohammed, Muneer Khan; Renganayagalu, Ravi Kottan; Moiduddin, Khaja

2017-02-21

Titanium aluminides qualify adequately for advanced aero-engine applications in place of conventional nickel based superalloys. The combination of high temperature properties and lower density gives an edge to the titanium aluminide alloys. Nevertheless, challenges remain on how to process these essentially intermetallic alloys in to an actual product. Electron Beam Melting (EBM), an Additive Manufacturing Method, can build complex shaped solid parts from a given feedstock powder, thus overcoming the shortcomings of the conventional processing techniques such as machining and forging. The amount of energy supplied by the electron beam has considerable influence on the final build quality in the EBM process. Energy input is decided by the beam voltage, beam scan speed, beam current, and track offset distance. In the current work, beam current and track offset were varied to reflect three levels of energy input. Microstructural and mechanical properties were evaluated for these samples. The microstructure gradually coarsened from top to bottom along the build direction. Whereas higher energy favored lath microstructure, lower energy tended toward equiaxed grains. Computed tomography analysis revealed a greater amount of porosity in low energy samples. In addition, the lack of bonding defects led to premature failure in the tension test of low energy samples. Increase in energy to a medium level largely cancelled out the porosity, thereby increasing the strength. However, this trend did not continue with the high energy samples. Electron microscopy and X-ray diffraction investigations were carried out to understand this non-linear behavior of the strength in the three samples. Overall, the results of this work suggest that the input energy should be considered primarily whenever any new alloy system has to be processed through the EBM route.

Low voltage to high voltage level shifter and related methods

NASA Technical Reports Server (NTRS)

Mentze, Erik J. (Inventor); Buck, Kevin M. (Inventor); Hess, Herbert L. (Inventor); Cox, David F. (Inventor)

2006-01-01

A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

A low-power CMOS trans-impedance amplifier for FM/cw ladar imaging system

NASA Astrophysics Data System (ADS)

Hu, Kai; Zhao, Yi-qiang; Sheng, Yun; Zhao, Hong-liang; Yu, Hai-xia

2013-09-01

A scannerless ladar imaging system based on a unique frequency modulation/continuous wave (FM/cw) technique is able to entirely capture the target environment, using a focal plane array to construct a 3D picture of the target. This paper presents a low power trans-impedance amplifier (TIA) designed and implemented by 0.18 μm CMOS technology, which is used in the FM/cw imaging ladar with a 64×64 metal-semiconductor-metal(MSM) self-mixing detector array. The input stage of the operational amplifier (op amp) in TIA is realized with folded cascade structure to achieve large open loop gain and low offset. The simulation and test results of TIA with MSM detectors indicate that the single-end trans-impedance gain is beyond 100 kΩ, and the -3 dB bandwidth of Op Amp is beyond 60 MHz. The input common mode voltage ranges from 0.2 V to 1.5 V, and the power dissipation is reduced to 1.8 mW with a supply voltage of 3.3 V. The performance test results show that the TIA is a candidate for preamplifier of the read-out integrated circuit (ROIC) in the FM/cw scannerless ladar imaging system.

Design of a probe for two-dimensional small angle detection

NASA Astrophysics Data System (ADS)

He, Haixia; Wang, Xuanze; Zhong, Yuning; Yang, Liangen; Cao, Hongduan

2008-10-01

A novel two-dimensional small angle probe is introduced, which is based on principle of auto-collimation and utilizes quadrant Si-photoelectric detector (QPD) as detection device. AC modulation, AC magnification and absolute value demodulation are incorporated to restrain the DC excursion caused by background light and noise etc and to improve the sensitivity and stability of angle detection. To ensure that while the laser is shining, the current signal (converted into voltage signal) of QPD also is linear to the AC modulation voltage, this paper adopted AC modulation signal (5400Hz) with a DC offset. AC magnification circuit with reasonable parameters is designed to inhibit DC drift and the impact of industrial frequency noise and to ensure good amplification to signal frequency at the same time. A piezoelectric-driven micro-angle generator is designed to demarcate the angle. The calibration data are input to single chip, and the measurement of angles can be shown in SMC1602A.

Optical analog data link with simple self-test feature

DOEpatents

Witkover, Richard L.

1986-01-01

A communications circuit for optically transmitting analog data signals free of excessive ripple, while having rapid response time. The invention is further characterized by being adapted to provide an immediate indication of the failure of the optical transmission link of the circuit. Commercially available voltage to frequency converter chips are used in conjunction with suitable wiring arrays and in combination with readily available indicator means for constructing the communication circuit of the invention. A V/F converter in the communications circuit is coupled to an offset adjustment means to cause the converter to continuously produce a string of output voltage pulses having a frequency of about 1 Khz responsive to the input analog signal to the converter being zero. The continuous presence of the 1 Khz frequency on the optical transmission link is monitored at the receiving end of the communication circuit and the indicator means is connected to immediately provide an easily detected indication of a failure of the optical transmission link to transmit the 1 Khz frequency pulses.

Optical analog data link with simple self-test feature

DOEpatents

Witkover, R.L.

1984-02-01

A communications circuit for optically transmitting analog data signals free of excessive ripple, while having rapid response time. The invention is further characterized by being adapted to provide an immediate indication of the failure of the optical transmission link of the circuit. Commerically available voltage to frequency converter chips are used in conjunction with suitable wiring arrays and in combination with readily available indicator means for constructing the communication circuit of the invention. A V/F converter in the communications circuit is coupled to an offset adjustment means to cause the converter to continuously produce a string of output voltage pulses having a frequency of about 1Khz responsive to the input analog signal to the converter being zero. The continuous presence of the 1Khz frequency on the optical transmission link is monitored at the receiving end of the communication circuit and the indicator means is connected to immediately provide an easily detected indication of a failure of the optical transmission link to transmit the 1Khz frequency pulses.

Symmetric voltage-controlled variable resistance

NASA Technical Reports Server (NTRS)

Vanelli, J. C.

1978-01-01

Feedback network makes resistance of field-effect transistor (FET) same for current flowing in either direction. It combines control voltage with source and load voltages to give symmetric current/voltage characteristics. Since circuit produces same magnitude output voltage for current flowing in either direction, it introduces no offset in presense of altering polarity signals. It is therefore ideal for sensor and effector circuits in servocontrol systems.

Timing discriminator using leading-edge extrapolation

DOEpatents

Gottschalk, Bernard

1983-01-01

A discriminator circuit to recover timing information from slow-rising pulses by means of an output trailing edge, a fixed time after the starting corner of the input pulse, which is nearly independent of risetime and threshold setting. This apparatus comprises means for comparing pulses with a threshold voltage; a capacitor to be charged at a certain rate when the input signal is one-third threshold voltage, and at a lower rate when the input signal is two-thirds threshold voltage; current-generating means for charging the capacitor; means for comparing voltage capacitor with a bias voltage; a flip-flop to be set when the input pulse reaches threshold voltage and reset when capacitor voltage reaches the bias voltage; and a clamping means for discharging the capacitor when the input signal returns below one-third threshold voltage.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

PubMed

Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

2017-09-09

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

PubMed Central

Han, Seong-Tae; Baek, Donghyun

2017-01-01

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB. PMID:28891927

Comparative investigation of InGaP/GaAs/GaAsBi and InGaP/GaAs heterojunction bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Yi-Chen; Tsai, Jung-Hui, E-mail: jhtsai@nknucc.nknu.edu.tw; Chiang, Te-Kuang

2015-10-15

In this article the characteristics of In{sub 0.49}Ga{sub 0.51}P/GaAs/GaAs{sub 0.975}Bi{sub 0.025} and In{sub 0.49}Ga{sub 0.51}P/GaAs heterojunction bipolar transistor (HBTs) are demonstrated and compared by two-dimensional simulated analysis. As compared to the traditional InGaP/GaAs HBT, the studied InGaP/GaAs/GaAsBi HBT exhibits a higher collector current, a lower base-emitter (B–E) turn-on voltage, and a relatively lower collector-emitter offset voltage of only 7 mV. Because the more electrons stored in the base is further increased in the InGaP/GaAs/GaAsBi HBT, it introduces the collector current to increase and the B–E turn-on voltage to decrease for low input power applications. However, the current gain is slightlymore » smaller than the traditional InGaP/GaAs HBT attributed to the increase of base current for the minority carriers stored in the GaAsBi base.« less

Inverter ratio failure detector

NASA Technical Reports Server (NTRS)

Wagner, A. P.; Ebersole, T. J.; Andrews, R. E. (Inventor)

1974-01-01

A failure detector which detects the failure of a dc to ac inverter is disclosed. The inverter under failureless conditions is characterized by a known linear relationship of its input and output voltages and by a known linear relationship of its input and output currents. The detector includes circuitry which is responsive to the detector's input and output voltages and which provides a failure-indicating signal only when the monitored output voltage is less by a selected factor, than the expected output voltage for the monitored input voltage, based on the known voltages' relationship. Similarly, the detector includes circuitry which is responsive to the input and output currents and provides a failure-indicating signal only when the input current exceeds by a selected factor the expected input current for the monitored output current based on the known currents' relationship.

Correction of Thermal Gradient Errors in Stem Thermocouple Hygrometers

PubMed Central

Michel, Burlyn E.

1979-01-01

Stem thermocouple hygrometers were subjected to transient and stable thermal gradients while in contact with reference solutions of NaCl. Both dew point and psychrometric voltages were directly related to zero offset voltages, the latter reflecting the size of the thermal gradient. Although slopes were affected by absolute temperature, they were not affected by water potential. One hygrometer required a correction of 1.75 bars water potential per microvolt of zero offset, a value that was constant from 20 to 30 C. PMID:16660685

Timing discriminator using leading-edge extrapolation

DOEpatents

Gottschalk, B.

1981-07-30

A discriminator circuit to recover timing information from slow-rising pulses by means of an output trailing edge, a fixed time after the starting corner of the input pulse, which is nearly independent of risetime and threshold setting is described. This apparatus comprises means for comparing pulses with a threshold voltage; a capacitor to be charged at a certain rate when the input signal is one-third threshold voltage, and at a lower rate when the input signal is two-thirds threshold voltage; current-generating means for charging the capacitor; means for comparing voltage capacitor with a bias voltage; a flip-flop to be set when the input pulse reaches threshold voltage and reset when capacitor voltage reaches the bias voltage; and a clamping means for discharging the capacitor when the input signal returns below one-third threshold voltage.

Logarithmic circuit with wide dynamic range

NASA Technical Reports Server (NTRS)

Wiley, P. H.; Manus, E. A. (Inventor)

1978-01-01

A circuit deriving an output voltage that is proportional to the logarithm of a dc input voltage susceptible to wide variations in amplitude includes a constant current source which forward biases a diode so that the diode operates in the exponential portion of its voltage versus current characteristic, above its saturation current. The constant current source includes first and second, cascaded feedback, dc operational amplifiers connected in negative feedback circuit. An input terminal of the first amplifier is responsive to the input voltage. A circuit shunting the first amplifier output terminal includes a resistor in series with the diode. The voltage across the resistor is sensed at the input of the second dc operational feedback amplifier. The current flowing through the resistor is proportional to the input voltage over the wide range of variations in amplitude of the input voltage.

Pseudo-Hall Effect in Graphite on Paper Based Four Terminal Devices for Stress Sensing Applications

NASA Astrophysics Data System (ADS)

Qamar, Afzaal; Sarwar, Tuba; Dinh, Toan; Foisal, A. R. M.; Phan, Hoang-Phuong; Viet Dao, Dzung

2017-04-01

A cost effective and easy to fabricate stress sensor based on pseudo-Hall effect in Graphite on Paper (GOP) has been presented in this article. The four terminal devices were developed by pencil drawing with hand on to the paper substrate. The stress was applied to the paper containing four terminal devices with the input current applied at two terminals and the offset voltage observed at other two terminals called pseudo-Hall effect. The GOP stress sensor showed significant response to the applied stress which was smooth and linear. These results showed that the pseudo-Hall effect in GOP based four terminal devices can be used for cost effective, flexible and easy to make stress, strain or force sensors.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, X.

1996-12-17

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window. 5 figs.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, Xucheng

1996-01-01

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

Upgrades to the Closed Bomb Facility and Measurement of Propellant Burning Rate

DTIC Science & Technology

2010-01-01

attenuation ratio myScope.WriteString (":CHAN1:RANGe " + CStr (Me.tbVRange.value)) ‘Sets the vertical voltage range myScope.WriteString (":CHAN1...OFFSet " + CStr (Me.tboffset.value)) ‘Sets the voltage offset myScope.WriteString ":CHAN1:PROB:STYP SING" ‘Sets the signal type...myScope.WriteString (":TRIG:EDGE:SOURce CHAN" + CStr (Int(val(GetRegistry(CollType, cCHANNEL))))) ‘Sets the source channel myScope.WriteString

System and methods for reducing harmonic distortion in electrical converters

DOEpatents

Kajouke, Lateef A; Perisic, Milun; Ransom, Ray M

2013-12-03

Systems and methods are provided for delivering energy using an energy conversion module. An exemplary method for delivering energy from an input interface to an output interface using an energy converison module coupled between the input interface and the output interface comprises the steps of determining an input voltage reference for the input interface based on a desired output voltage and a measured voltage and the output interface, determining a duty cycle control value based on a ratio of the input voltage reference and the measured voltage, operating one or more switching elements of the energy conversion module to deliver energy from the input interface to the output interface to the output interface with a duty cycle influenced by the dute cycle control value.

A Low Power Linear Phase Programmable Long Delay Circuit.

PubMed

Rodriguez-Villegas, Esther; Logesparan, Lojini; Casson, Alexander J

2014-06-01

A novel linear phase programmable delay is being proposed and implemented in a 0.35 μm CMOS process. The delay line consists of N cascaded cells, each of which delays the input signal by Td/N, where Td is the total line delay. The delay generated by each cell is programmable by changing a clock frequency and is also fully independent of the frequency of the input signal. The total delay hence depends only on the chosen clock frequency and the total number of cascaded cells. The minimum clock frequency is limited by the maximum time a voltage signal can effectively be held by an individual cell. The maximum number of cascaded cells will be limited by the effects of accumulated offset due to transistor mismatch, which eventually will affect the operating mode of the individual transistors in a cell. This latter limitation has however been dealt with in the topology by having an offset compensation mechanism that makes possible having a large number of cascaded cells and hence a long resulting delay. The delay line has been designed for scalp-based neural activity analysis that is predominantly in the sub-100 Hz frequency range. For these signals, the delay generated by a 31-cell cascade has been demonstrated to be programmable from 30 ms to 3 s. Measurement results demonstrate a 31 stage, 50 Hz bandwidth, 0.3 s delay that operates from a 1.1 V supply with power consumption of 270 nW.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Milkov, Mihail M.

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed.

On the reliability of voltage and power as input parameters for the characterization of high power ultrasound applications

NASA Astrophysics Data System (ADS)

Haller, Julian; Wilkens, Volker

2012-11-01

For power levels up to 200 W and sonication times up to 60 s, the electrical power, the voltage and the electrical impedance (more exactly: the ratio of RMS voltage and RMS current) have been measured for a piezocomposite high intensity therapeutic ultrasound (HITU) transducer with integrated matching network, two piezoceramic HITU transducers with external matching networks and for a passive dummy 50 Ω load. The electrical power and the voltage were measured during high power application with an inline power meter and an RMS voltage meter, respectively, and the complex electrical impedance was indirectly measured with a current probe, a 100:1 voltage probe and a digital scope. The results clearly show that the input RMS voltage and the input RMS power change unequally during the application. Hence, the indication of only the electrical input power or only the voltage as the input parameter may not be sufficient for reliable characterizations of ultrasound transducers for high power applications in some cases.

60 V tolerance full symmetrical switch for battery monitor IC

NASA Astrophysics Data System (ADS)

Zhang, Qidong; Yang, Yintang; Chai, Changchun

2017-06-01

For stacked battery monitoring IC high speed and high precision voltage acquisition requirements, this paper introduces a kind of symmetrical type high voltage switch circuit. This kind of switch circuit uses the voltage following structure, which eliminates the leakage path of input signals. At the same time, this circuit adopts a high speed charge pump structure, in any case the input signal voltage is higher than the supply voltage, it can fast and accurately turn on high voltage MOS devices, and convert the battery voltage to an analog to digital converter. The proposed high voltage full symmetry switch has been implemented in a 0.18 μm BCD process; simulated and measured results show that the proposed switch can always work properly regardless of the polarity of the voltage difference between the input signal ports and an input signal higher than the power supply. Project supported by the National Natural Science Foundation of China (No. 61334003).

AC to DC Bridgeless Boost Converter for Ultra Low Input Energy Harvesting

NASA Astrophysics Data System (ADS)

Dawam, A. H. A.; Muhamad, M.

2018-03-01

This paper presents design of circuit which converts low input AC voltage to a higher output DC voltage. A buck-boost topology and boost topology are combined to condition cycle of an AC input voltage. the unique integration of a combining circuit of buck-boost and boost circuit have been proposed in order to introduce a new direct ac-dc power converter topology without conventional diode bridge rectifier. The converter achieved to convert a milli-volt scale of input AC voltage into a volt scale of output DC voltages which is from 400mV to 3.3V.

MULTIPLIER CIRCUIT

DOEpatents

Thomas, R.E.

1959-01-20

An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses

Dual side control for inductive power transfer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Hunter; Sealy, Kylee; Gilchrist, Aaron

An apparatus for dual side control includes a measurement module that measures a voltage and a current of an IPT system. The voltage includes an output voltage and/or an input voltage and the current includes an output current and/or an input current. The output voltage and the output current are measured at an output of the IPT system and the input voltage and the input current measured at an input of the IPT system. The apparatus includes a max efficiency module that determines a maximum efficiency for the IPT system. The max efficiency module uses parameters of the IPT systemmore » to iterate to a maximum efficiency. The apparatus includes an adjustment module that adjusts one or more parameters in the IPT system consistent with the maximum efficiency calculated by the max efficiency module.« less

High-frequency matrix converter with square wave input

DOEpatents

Carr, Joseph Alexander; Balda, Juan Carlos

2015-03-31

A device for producing an alternating current output voltage from a high-frequency, square-wave input voltage comprising, high-frequency, square-wave input a matrix converter and a control system. The matrix converter comprises a plurality of electrical switches. The high-frequency input and the matrix converter are electrically connected to each other. The control system is connected to each switch of the matrix converter. The control system is electrically connected to the input of the matrix converter. The control system is configured to operate each electrical switch of the matrix converter converting a high-frequency, square-wave input voltage across the first input port of the matrix converter and the second input port of the matrix converter to an alternating current output voltage at the output of the matrix converter.

The Series Connected Buck Boost Regulator Concept for High Efficiency Light Weight DC Voltage Regulation

NASA Technical Reports Server (NTRS)

Birchenough, Arthur G.

2003-01-01

Improvements in the efficiency and size of DC-DC converters have resulted from advances in components, primarily semiconductors, and improved topologies. One topology, which has shown very high potential in limited applications, is the Series Connected Boost Unit (SCBU), wherein a small DC-DC converter output is connected in series with the input bus to provide an output voltage equal to or greater than the input voltage. Since the DC-DC converter switches only a fraction of the power throughput, the overall system efficiency is very high. But this technique is limited to applications where the output is always greater than the input. The Series Connected Buck Boost Regulator (SCBBR) concept extends partial power processing technique used in the SCBU to operation when the desired output voltage is higher or lower than the input voltage, and the implementation described can even operate as a conventional buck converter to operate at very low output to input voltage ratios. This paper describes the operation and performance of an SCBBR configured as a bus voltage regulator providing 50 percent voltage regulation range, bus switching, and overload limiting, operating above 98 percent efficiency. The technique does not provide input-output isolation.

Non-linear Membrane Properties in Entorhinal Cortical Stellate Cells Reduce Modulation of Input-Output Responses by Voltage Fluctuations

PubMed Central

Fernandez, Fernando R.; Malerba, Paola; White, John A.

2015-01-01

The presence of voltage fluctuations arising from synaptic activity is a critical component in models of gain control, neuronal output gating, and spike rate coding. The degree to which individual neuronal input-output functions are modulated by voltage fluctuations, however, is not well established across different cortical areas. Additionally, the extent and mechanisms of input-output modulation through fluctuations have been explored largely in simplified models of spike generation, and with limited consideration for the role of non-linear and voltage-dependent membrane properties. To address these issues, we studied fluctuation-based modulation of input-output responses in medial entorhinal cortical (MEC) stellate cells of rats, which express strong sub-threshold non-linear membrane properties. Using in vitro recordings, dynamic clamp and modeling, we show that the modulation of input-output responses by random voltage fluctuations in stellate cells is significantly limited. In stellate cells, a voltage-dependent increase in membrane resistance at sub-threshold voltages mediated by Na+ conductance activation limits the ability of fluctuations to elicit spikes. Similarly, in exponential leaky integrate-and-fire models using a shallow voltage-dependence for the exponential term that matches stellate cell membrane properties, a low degree of fluctuation-based modulation of input-output responses can be attained. These results demonstrate that fluctuation-based modulation of input-output responses is not a universal feature of neurons and can be significantly limited by subthreshold voltage-gated conductances. PMID:25909971

Non-linear Membrane Properties in Entorhinal Cortical Stellate Cells Reduce Modulation of Input-Output Responses by Voltage Fluctuations.

PubMed

Fernandez, Fernando R; Malerba, Paola; White, John A

2015-04-01

The presence of voltage fluctuations arising from synaptic activity is a critical component in models of gain control, neuronal output gating, and spike rate coding. The degree to which individual neuronal input-output functions are modulated by voltage fluctuations, however, is not well established across different cortical areas. Additionally, the extent and mechanisms of input-output modulation through fluctuations have been explored largely in simplified models of spike generation, and with limited consideration for the role of non-linear and voltage-dependent membrane properties. To address these issues, we studied fluctuation-based modulation of input-output responses in medial entorhinal cortical (MEC) stellate cells of rats, which express strong sub-threshold non-linear membrane properties. Using in vitro recordings, dynamic clamp and modeling, we show that the modulation of input-output responses by random voltage fluctuations in stellate cells is significantly limited. In stellate cells, a voltage-dependent increase in membrane resistance at sub-threshold voltages mediated by Na+ conductance activation limits the ability of fluctuations to elicit spikes. Similarly, in exponential leaky integrate-and-fire models using a shallow voltage-dependence for the exponential term that matches stellate cell membrane properties, a low degree of fluctuation-based modulation of input-output responses can be attained. These results demonstrate that fluctuation-based modulation of input-output responses is not a universal feature of neurons and can be significantly limited by subthreshold voltage-gated conductances.

Self-aligned photolithography for the fabrication of fully transparent high-voltage devices

NASA Astrophysics Data System (ADS)

Zhang, Yonghui; Mei, Zengxia; Huo, Wenxing; Wang, Tao; Liang, Huili; Du, Xiaolong

2018-05-01

High-voltage devices, working in the range of hundreds of volts, are indispensable elements in the driving or readout circuits for various kinds of displays, integrated microelectromechanical systems and x-ray imaging sensors. However, the device performances are found hardly uniform or repeatable due to the misalignment issue, which are extremely common for offset drain high-voltage devices. To resolve this issue, this article reports a set of self-aligned photolithography technology for the fabrication of high-voltage devices. High-performance fully-transparent high-voltage thin film transistors, diodes and logic inverters are successfully fabricated with this technology. Unlike other self-aligned routes, opaque masks are introduced on the backside of the transparent substrate to facilitate proximity exposure method. The photolithography process is simulated and analyzed with technology computer aided design simulation to explain the working principle of the proximity exposure method. The substrate thickness is found to be vital for the implementation of this technology based on both simulation and experimental results. The electrical performance of high-voltage devices is dependent on the offset length, which can be delicately modulated by changing the exposure dose. The presented self-aligned photolithography technology is proved to be feasible in high-voltage circuits, demonstrating its huge potential in practical industrial applications.

Apparatus for providing a servo drive signal in a high-speed stepping interferometer

NASA Technical Reports Server (NTRS)

Schindler, R. A. (Inventor)

1979-01-01

An analog voltage approximately linearly proportional to a desired offset from the present null position of a moving mirror in an interferometer is applied to the mirror moving means. As the mirror moves to the next null position, as determined by the analog voltage, the fringes of a laser reference interference pattern are detected. At the occurrence of each fringe the analog voltage is reduced proportionally so that when the next null position is reached, this driving analog is effectively zero. A binary up/down counter, by its internal count, causes a digital/analog converter to supply the analog voltage to the mirror moving means. Fringe detection and direction of movement logic cause the binary up/down counter to be decremented from its offset count as the mirror is moved to the new null position. Undesirable movement of the mirror due to vibration or other sources causes a correcting drive signal to be applied to the mirror moving means that is proportional to the distance of movement.

MT6425CA: a 640 X 512-25μm CTIA ROIC for SWIR InGaAs detector arrays

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Mahsereci, Yigit Uygar; Altiner, Caglar; Akin, Tayfun

2012-06-01

This paper reports the development of a new CTIA ROIC (MT6425CA) suitable for SWIR InGaAs detector arrays. MT6425CA has a format of 640 × 512 with a pixel pitch of 25 μm and has a system-on-chip architecture, where all the critical timing and biasing for this ROIC are generated by programmable blocks on-chip. MT6425CA is a highly configurable and flexible ROIC, where many of its features can be programmed through a 3-wire serial interface allowing on-the-fly configuration of many ROIC features. The ROIC runs on 3.3V supply voltage at nominal clock speed of 10 MHz clock. It performs snapshot operation both using Integrate-Then-Read (ITR) and Integrate-While- Read (IWR) modes. The CTIA type pixel input circuitry has a full-well-capacity (FWC) of about 320,000e-, with an input referred read noise of less than 110e- at 300K. MT6425CA has programmable number of outputs, where 4, 2, or 1 output can be selected along with an analog reference for pseudo-differential operation. The integration time can be programmed up to 1s in steps of 0.1μs. The gain and offset in the ROIC can be programmed to adjust the output offset and voltage swing. ROIC dissipates less than 130mW from a 3.3V supply at full speed and full frame size with 4 outputs, providing both low-power and low-noise operation. MT6425CA is fabricated using a modern mixed-signal CMOS process on 200mm CMOS wafers with a high yield above 75%, yielding more than 50 working parts per wafer. It has been silicon verified, and tested parts are available either in wafer and die levels with a complete documentation including test reports and wafer maps. A USB based camera electronics and camera development platform with software are available to help customers to evaluate the imaging performance of MT6425CA in a fast and efficient way.

Apparatus for Controlling Low Power Voltages in Space Based Processing Systems

NASA Technical Reports Server (NTRS)

Petrick, David J. (Inventor)

2017-01-01

A low power voltage control circuit for use in space missions includes a switching device coupled between an input voltage and an output voltage. The switching device includes a control input coupled to an enable signal, wherein the control input is configured to selectively turn the output voltage on or off based at least in part on the enable signal. A current monitoring circuit is coupled to the output voltage and configured to produce a trip signal, wherein the trip signal is active when a load current flowing through the switching device is determined to exceed a predetermined threshold and is inactive otherwise. The power voltage control circuit is constructed of space qualified components.

Resonant-Type Smooth Impact Drive Mechanism Actuator Operating at Lower Input Voltages

NASA Astrophysics Data System (ADS)

Morita, Takeshi; Nishimura, Takuma; Yoshida, Ryuichi; Hosaka, Hiroshi

2013-07-01

We report on the design and fabrication of a resonant-type smooth impact drive mechanism (SIDM) actuator based on a multilayered piezoelectric ceramic transducer. Conventional SIDMs use off-resonant sawtooth-shaped displacement in developing stick-slip motion of a slider, but require large input voltages for high-speed operation. In contrast, in resonant-type SIDMs, a quasi-sawtooth-shaped displacement is obtained by combining two resonant vibrational modes. This driving principle enables low input voltage operations. In combining the modes, their frequency ratio must be 1:2. To design and optimize the stator transducer to generate sawtooth-shaped displacements, a transfer matrix method was adopted. With a preload of 270 mN, the no-load speed was 40 mm/s under a driving voltage of 1.6 V (peak to peak). This input voltage was one-sixth that of previous SIDMs for the same performance. Concurrently, heat generation was significantly reduced because dielectric losses were suppressed under the lower input voltage operation.

Analysis of the possibility of a PGA309 integrated circuit application in pressure sensors

NASA Astrophysics Data System (ADS)

Walendziuk, Wojciech; Baczewski, Michal; Idzkowski, Adam

2016-09-01

This article present the results of research concerning the analysis of the possibilities of applying a PGA309 integrated circuit in transducers used for pressure measurement. The experiments were done with the use of a PGA309EVM-USB evaluation circuit with a BD|SENSORS pressure sensor. A specially prepared MATLAB script was used in the process of the calibration setting choice and the results analysis. The article discusses the worked out algorithm that processes the measurement results, i.e. the algorithm which calculates the desired gain and the offset adjustment voltage of the transducer measurement bridge in relation to the input signal range of the integrated circuit and the temperature of the environment (temperature compensation). The checking procedure was conducted in a measurement laboratory and the obtained result were analyzed and discussed.

The Analog Revolution and Its On-Going Role in Modern Analytical Measurements.

PubMed

Enke, Christie G

2015-12-15

The electronic revolution in analytical instrumentation began when we first exceeded the two-digit resolution of panel meters and chart recorders and then took the first steps into automated control. It started with the first uses of operational amplifiers (op amps) in the analog domain 20 years before the digital computer entered the analytical lab. Their application greatly increased both accuracy and precision in chemical measurement and they provided an elegant means for the electronic control of experimental quantities. Later, laboratory and personal computers provided an unlimited readout resolution and enabled programmable control of instrument parameters as well as storage and computation of acquired data. However, digital computers did not replace the op amp's critical role of converting the analog sensor's output to a robust and accurate voltage. Rather it added a new role: converting that voltage into a number. These analog operations are generally the limiting portions of our computerized instrumentation systems. Operational amplifier performance in gain, input current and resistance, offset voltage, and rise time have improved by a remarkable 3-4 orders of magnitude since their first implementations. Each 10-fold improvement has opened the doors for the development of new techniques in all areas of chemical analysis. Along with some interesting history, the multiple roles op amps play in modern instrumentation are described along with a number of examples of new areas of analysis that have been enabled by their improvements.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Development of high-bandgap AlGaInP solar cells grown by organometallic vapor-phase epitaxy

DOE PAGES

Perl, Emmett E.; Simon, John; Geisz, John F.; ...

2016-03-29

AlGaInP solar cells with bandgaps between 1.9 and 2.2 eV are investigated for use in next-generation multijunction photovoltaic devices. This quaternary alloy is of great importance to the development of III-V solar cells with five or more junctions and for cells optimized for operation at elevated temperatures because of the high bandgaps required in these designs. In this work, we explore the conditions for the organometallic vapor-phase epitaxy growth of AlGaInP and study their effects on cell performance. Initial efforts focused on developing ~2.0-eV AlGaInP solar cells with a nominal aluminum composition of 12%. Under the direct spectrum at 1000more » W/m 2 (AM1.5D), the best of these samples had an open-circuit voltage of 1.59 V, a bandgap-voltage offset of 440 mV, a fill factor of 88.0%, and an efficiency of 14.8%. We then varied the aluminum composition of the alloy from 0% to 24% and were able to tune the bandgap of the AlGaInP layers from ~1.9 to ~2.2 eV. Furthermore, while the samples with a higher aluminum composition exhibited a reduced quantum efficiency and increased bandgap-voltage offset, the bandgap-voltage offset remained at 500 mV or less, up to a bandgap of ~2.1 eV.« less

High Input Voltage, Silicon Carbide Power Processing Unit Performance Demonstration

NASA Technical Reports Server (NTRS)

Bozak, Karin E.; Pinero, Luis R.; Scheidegger, Robert J.; Aulisio, Michael V.; Gonzalez, Marcelo C.; Birchenough, Arthur G.

2015-01-01

A silicon carbide brassboard power processing unit has been developed by the NASA Glenn Research Center in Cleveland, Ohio. The power processing unit operates from two sources - a nominal 300-Volt high voltage input bus and a nominal 28-Volt low voltage input bus. The design of the power processing unit includes four low voltage, low power supplies that provide power to the thruster auxiliary supplies, and two parallel 7.5 kilowatt power supplies that are capable of providing up to 15 kilowatts of total power at 300-Volts to 500-Volts to the thruster discharge supply. Additionally, the unit contains a housekeeping supply, high voltage input filter, low voltage input filter, and master control board, such that the complete brassboard unit is capable of operating a 12.5 kilowatt Hall Effect Thruster. The performance of unit was characterized under both ambient and thermal vacuum test conditions, and the results demonstrate the exceptional performance with full power efficiencies exceeding 97. With a space-qualified silicon carbide or similar high voltage, high efficiency power device, this design could evolve into a flight design for future missions that require high power electric propulsion systems.

High Input Voltage, Silicon Carbide Power Processing Unit Performance Demonstration

NASA Technical Reports Server (NTRS)

Bozak, Karin E.; Pinero, Luis R.; Scheidegger, Robert J.; Aulisio, Michael V.; Gonzalez, Marcelo C.; Birchenough, Arthur G.

2015-01-01

A silicon carbide brassboard power processing unit has been developed by the NASA Glenn Research Center in Cleveland, Ohio. The power processing unit operates from two sources: a nominal 300 Volt high voltage input bus and a nominal 28 Volt low voltage input bus. The design of the power processing unit includes four low voltage, low power auxiliary supplies, and two parallel 7.5 kilowatt (kW) discharge power supplies that are capable of providing up to 15 kilowatts of total power at 300 to 500 Volts (V) to the thruster. Additionally, the unit contains a housekeeping supply, high voltage input filter, low voltage input filter, and master control board, such that the complete brassboard unit is capable of operating a 12.5 kilowatt Hall effect thruster. The performance of the unit was characterized under both ambient and thermal vacuum test conditions, and the results demonstrate exceptional performance with full power efficiencies exceeding 97%. The unit was also tested with a 12.5kW Hall effect thruster to verify compatibility and output filter specifications. With space-qualified silicon carbide or similar high voltage, high efficiency power devices, this would provide a design solution to address the need for high power electric propulsion systems.

Low frequency noise elimination technique for 24-bit Σ-Δ data acquisition systems.

PubMed

Qu, Shao-Bo; Robert, Olivier; Lognonné, Philippe; Zhou, Ze-Bing; Yang, Shan-Qing

2015-03-01

Low frequency 1/f noise is one of the key limiting factors of high precision measurement instruments. In this paper, digital correlated double sampling is implemented to reduce the offset and low frequency 1/f noise of a data acquisition system with 24-bit sigma delta (Σ-Δ) analog to digital converter (ADC). The input voltage is modulated by cross-coupled switches, which are synchronized to the sampling clock, and converted into digital signal by ADC. By using a proper switch frequency, the unwanted parasitic signal frequencies generated by the switches are avoided. The noise elimination processing is made through the principle of digital correlated double sampling, which is equivalent to a time shifted subtraction for the sampled voltage. The low frequency 1/f noise spectrum density of the data acquisition system is reduced to be flat down to the measurement frequency lower limit, which is about 0.0001 Hz in this paper. The noise spectrum density is eliminated by more than 60 dB at 0.0001 Hz, with a residual noise floor of (9 ± 2) nV/Hz(1/2) which is limited by the intrinsic white noise floor of the ADC above its corner frequency.

THE POSITIVITY OFFSET THEORY OF ANHEDONIA IN SCHIZOPHRENIA.

PubMed

Strauss, Gregory P; Frost, Katherine H; Lee, Bern G; Gold, James M

2017-03-01

Prior studies have concluded that schizophrenia patients are not anhedonic because they do not report reduced experience of positive emotion to pleasant stimuli. The current study challenged this view by applying quantitative methods validated in the Evaluative Space Model of emotional experience to test the hypothesis that schizophrenia patients evidence a reduction in the normative "positivity offset" (i.e., the tendency to experience higher levels of positive than negative emotional output when stimulus input is absent or weak). Participants included 76 schizophrenia patients and 60 healthy controls who completed an emotional experience task that required reporting the level of positive emotion, negative emotion, and arousal to photographs. Results indicated that although schizophrenia patients evidenced intact capacity to experience positive emotion at high levels of stimulus input, they displayed a diminished positivity offset. Reductions in the positivity offset may underlie volitional disturbance, limiting approach behaviors toward novel stimuli in neutral environments.

Method and apparatus for controlling a microturbine

DOEpatents

Garces, Luis Jose; Cardinal, Mark Edward; Sinha, Gautam; Dame, Mark Edward

2005-08-02

An apparatus for controlling a microturbine, the apparatus including: a rectifier adapted for converting at least one generated voltage from the microturbine to a DC link voltage; an inverter adapted for converting the DC link voltage to at least one inverter output voltage, the at least one inverter output voltage being electrically coupled to an external power bus; a starter drive adapted for converting at least one starter input voltage to at least one starter output voltage, the at least one starter input voltage being electrically coupled to the external power bus, the at least one starter output voltage being electrically coupled to the microturbine.

Enhanced Response Time of Electrowetting Lenses with Shaped Input Voltage Functions.

PubMed

Supekar, Omkar D; Zohrabi, Mo; Gopinath, Juliet T; Bright, Victor M

2017-05-16

Adaptive optical lenses based on the electrowetting principle are being rapidly implemented in many applications, such as microscopy, remote sensing, displays, and optical communication. To characterize the response of these electrowetting lenses, the dependence upon direct current (DC) driving voltage functions was investigated in a low-viscosity liquid system. Cylindrical lenses with inner diameters of 2.45 and 3.95 mm were used to characterize the dynamic behavior of the liquids under DC voltage electrowetting actuation. With the increase of the rise time of the input exponential driving voltage, the originally underdamped system response can be damped, enabling a smooth response from the lens. We experimentally determined the optimal rise times for the fastest response from the lenses. We have also performed numerical simulations of the lens actuation with input exponential driving voltage to understand the variation in the dynamics of the liquid-liquid interface with various input rise times. We further enhanced the response time of the devices by shaping the input voltage function with multiple exponential rise times. For the 3.95 mm inner diameter lens, we achieved a response time improvement of 29% when compared to the fastest response obtained using single-exponential driving voltage. The technique shows great promise for applications that require fast response times.

Low Power, High Voltage Power Supply with Fast Rise/Fall Time

NASA Technical Reports Server (NTRS)

Bearden, Douglas B. (Inventor)

2007-01-01

A low power, high voltage power supply system includes a high voltage power supply stage and a preregulator for programming the power supply stage so as to produce an output voltage which is a predetermined fraction of a desired voltage level. The power supply stage includes a high voltage, voltage doubler stage connected to receive the output voltage from the preregulator and for, when activated, providing amplification of the output voltage to the desired voltage level. A first feedback loop is connected between the output of the preregulator and an input of the preregulator while a second feedback loop is connected between the output of the power supply stage and the input of the preregulator.

Low power, high voltage power supply with fast rise/fall time

NASA Technical Reports Server (NTRS)

Bearden, Douglas B. (Inventor)

2007-01-01

A low power, high voltage power supply system includes a high voltage power supply stage and a preregulator for programming the power supply stage so as to produce an output voltage which is a predetermined fraction of a desired voltage level. The power supply stage includes a high voltage, voltage doubler stage connected to receive the output voltage from the preregulator and for, when activated, providing amplification of the output voltage to the desired voltage level. A first feedback loop is connected between the output of the preregulator and an input of the preregulator while a second feedback loop is connected between the output of the power supply stage and the input of the preregulator.

Generation of electrical power

DOEpatents

Hursen, Thomas F.; Kolenik, Steven A.; Purdy, David L.

1976-01-01

A heat-to-electricity converter is disclosed which includes a radioactive heat source and a thermoelectric element of relatively short overall length capable of delivering a low voltage of the order of a few tenths of a volt. Such a thermoelectric element operates at a higher efficiency than longer higher-voltage elements; for example, elements producing 6 volts. In the generation of required power, thermoelectric element drives a solid-state converter which is controlled by input current rather than input voltage and operates efficiently for a high signal-plus-noise to signal ratio of current. The solid-state converter has the voltage gain necessary to deliver the required voltage at the low input of the thermoelectric element.

Phase locking of a semiconductor double-quantum-dot single-atom maser

NASA Astrophysics Data System (ADS)

Liu, Y.-Y.; Hartke, T. R.; Stehlik, J.; Petta, J. R.

2017-11-01

We experimentally study the phase stabilization of a semiconductor double-quantum-dot (DQD) single-atom maser by injection locking. A voltage-biased DQD serves as an electrically tunable microwave frequency gain medium. The statistics of the maser output field demonstrate that the maser can be phase locked to an external cavity drive, with a resulting phase noise L =-99 dBc/Hz at a frequency offset of 1.3 MHz. The injection locking range, and the phase of the maser output relative to the injection locking input tone are in good agreement with Adler's theory. Furthermore, the electrically tunable DQD energy level structure allows us to rapidly switch the gain medium on and off, resulting in an emission spectrum that resembles a frequency comb. The free running frequency comb linewidth is ≈8 kHz and can be improved to less than 1 Hz by operating the comb in the injection locked regime.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Offset Compound Gear Drive

NASA Technical Reports Server (NTRS)

Stevens, Mark A.; Handschuh, Robert F.; Lewicki, David G.

2010-01-01

The Offset Compound Gear Drive is an in-line, discrete, two-speed device utilizing a special offset compound gear that has both an internal tooth configuration on the input end and external tooth configuration on the output end, thus allowing it to mesh in series, simultaneously, with both a smaller external tooth input gear and a larger internal tooth output gear. This unique geometry and offset axis permits the compound gear to mesh with the smaller diameter input gear and the larger diameter output gear, both of which are on the same central, or primary, centerline. This configuration results in a compact in-line reduction gear set consisting of fewer gears and bearings than a conventional planetary gear train. Switching between the two output ratios is accomplished through a main control clutch and sprag. Power flow to the above is transmitted through concentric power paths. Low-speed operation is accomplished in two meshes. For the purpose of illustrating the low-speed output operation, the following example pitch diameters are given. A 5.0 pitch diameter (PD) input gear to 7.50 PD (internal tooth) intermediate gear (0.667 reduction mesh), and a 7.50 PD (external tooth) intermediate gear to a 10.00 PD output gear (0.750 reduction mesh). Note that it is not required that the intermediate gears on the offset axis be of the same diameter. For this example, the resultant low-speed ratio is 2:1 (output speed = 0.500; product of stage one 0.667 reduction and stage two 0.750 stage reduction). The design is not restricted to the example pitch diameters, or output ratio. From the output gear, power is transmitted through a hollow drive shaft, which, in turn, drives a sprag during which time the main clutch is disengaged.

High Power Microwave (HPM) and Ionizing Radiation Effects on CMOS Devices

DTIC Science & Technology

2010-03-01

24 xviii Symbol Page VIH minimum input voltage for proper high voltage output...38 VOH output voltage corresponding to VIH ...design. The high level at the input, VIH , along with VDD, define the maximum permitted “Logic 1” region, which allows for proper state change for a

Precision absolute-value amplifier for a precision voltmeter

DOEpatents

Hearn, W.E.; Rondeau, D.J.

1982-10-19

Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resistor is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resistor. The output current through the load resistor is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resistor. A second gain determining resistor is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier. The source and drain circuit of the third transistor is connected between the minus input of the third amplifier and a voltage-frequency converter, constituting an output device. A polarity detector is also provided, comprising a pair of transistors having their inputs connected to the outputs of the first and second differential amplifiers. The outputs of the polarity detector are connected to gates which switch the output of the voltage-frequency converter between up and down counting outputs.

Precision absolute value amplifier for a precision voltmeter

DOEpatents

Hearn, William E.; Rondeau, Donald J.

1985-01-01

Bipolar inputs are afforded by the plus inputs of first and second differential input amplifiers. A first gain determining resister is connected between the minus inputs of the differential amplifiers. First and second diodes are connected between the respective minus inputs and the respective outputs of the differential amplifiers. First and second FETs have their gates connected to the outputs of the amplifiers, while their respective source and drain circuits are connected between the respective minus inputs and an output lead extending to a load resister. The output current through the load resister is proportional to the absolute value of the input voltage difference between the bipolar input terminals. A third differential amplifier has its plus input terminal connected to the load resister. A second gain determining resister is connected between the minus input of the third differential amplifier and a voltage source. A third FET has its gate connected to the output of the third amplifier. The source and drain circuit of the third transistor is connected between the minus input of the third amplifier and a voltage-frequency converter, constituting an output device. A polarity detector is also provided, comprising a pair of transistors having their inputs connected to the outputs of the first and second differential amplifiers. The outputs of the polarity detector are connected to gates which switch the output of the voltage-frequency converter between up and down counting outputs.

Influence of asymmetric attenuation of single and paired dendritic inputs on summation of synaptic potentials and initiation of action potentials.

PubMed

Fortier, Pierre A; Bray, Chelsea

2013-04-16

Previous studies revealed mechanisms of dendritic inputs leading to action potential initiation at the axon initial segment and backpropagation into the dendritic tree. This interest has recently expanded toward the communication between different parts of the dendritic tree which could preprocess information before reaching the soma. This study tested for effects of asymmetric voltage attenuation between different sites in the dendritic tree on summation of synaptic inputs and action potential initiation using the NEURON simulation environment. Passive responses due to the electrical equivalent circuit of the three-dimensional neuron architecture with leak channels were examined first, followed by the responses after adding voltage-gated channels and finally synaptic noise. Asymmetric attenuation of voltage, which is a function of asymmetric input resistance, was seen between all pairs of dendritic sites but the transfer voltages (voltage recorded at the opposite site from stimulation among a pair of dendritic sites) were equal and also summed linearly with local voltage responses during simultaneous stimulation of both sites. In neurons with voltage-gated channels, we reproduced the observations where a brief stimulus to the proximal ascending dendritic branch of a pyramidal cell triggers a local action potential but a long stimulus triggers a somal action potential. Combined stimulation of a pair of sites in this proximal dendrite did not alter this pattern. The attraction of the action potential onset toward the soma with a long stimulus in the absence of noise was due to the higher density of voltage-gated sodium channels at the axon initial segment. This attraction was, however, negligible at the most remote distal dendritic sites and was replaced by an effect due to high input resistance. Action potential onset occurred at the dendritic site of higher input resistance among a pair of remote dendritic sites, irrespective of which of these two sites received the synaptic input. Exploration of the parameter space showed how the gradient of voltage-gated channel densities and input resistances along a dendrite could draw the action potential onset away from the stimulation site. The attraction of action potential onset toward the higher density of voltage-gated channels in the soma during stimulation of the proximal dendrite was, however, reduced after the addition of synaptic noise. Copyright © 2012 IBRO. Published by Elsevier Ltd. All rights reserved.

Fuel Cell/Electrochemical Cell Voltage Monitor

NASA Technical Reports Server (NTRS)

Vasquez, Arturo

2012-01-01

A concept has been developed for a new fuel cell individual-cell-voltage monitor that can be directly connected to a multi-cell fuel cell stack for direct substack power provisioning. It can also provide voltage isolation for applications in high-voltage fuel cell stacks. The technology consists of basic modules, each with an 8- to 16-cell input electrical measurement connection port. For each basic module, a power input connection would be provided for direct connection to a sub-stack of fuel cells in series within the larger stack. This power connection would allow for module power to be available in the range of 9-15 volts DC. The relatively low voltage differences that the module would encounter from the input electrical measurement connection port, coupled with the fact that the module's operating power is supplied by the same substack voltage input (and so will be at similar voltage), provides for elimination of high-commonmode voltage issues within each module. Within each module, there would be options for analog-to-digital conversion and data transfer schemes. Each module would also include a data-output/communication port. Each of these ports would be required to be either non-electrical (e.g., optically isolated) or electrically isolated. This is necessary to account for the fact that the plurality of modules attached to the stack will normally be at a range of voltages approaching the full range of the fuel cell stack operating voltages. A communications/ data bus could interface with the several basic modules. Options have been identified for command inputs from the spacecraft vehicle controller, and for output-status/data feeds to the vehicle.

A 1.8 GHz Voltage-Controlled Oscillator using CMOS Technology

NASA Astrophysics Data System (ADS)

Maisurah, M. H. Siti; Emran, F. Nazif; Norman Fadhil, Idham M.; Rahim, A. I. Abdul; Razman, Y. Mohamed

2011-05-01

A Voltage-Controlled Oscillator (VCO) for 1.8 GHz application has been designed using a combination of both 0.13 μm and 0.35 μm CMOS technology. The VCO has a large tuning range, which is from 1.39 GHz to 1.91 GHz, using a control voltage from 0 to 3V. The VCO exhibits a low phase-noise at 1.8 GHz which is around -119.8dBc/Hz at a frequency offset of 1 MHz.

Biased low differential input impedance current receiver/converter device and method for low noise readout from voltage-controlled detectors

DOEpatents

Degtiarenko, Pavel V [Williamsburg, VA; Popov, Vladimir E [Newport News, VA

2011-03-22

A first stage electronic system for receiving charge or current from voltage-controlled sensors or detectors that includes a low input impedance current receiver/converter device (for example, a transimpedance amplifier), which is directly coupled to the sensor output, a source of bias voltage, and the device's power supply (or supplies), which use the biased voltage point as a baseline.

Series-Connected Buck Boost Regulators

NASA Technical Reports Server (NTRS)

Birchenough, Arthur G.

2005-01-01

A series-connected buck boost regulator (SCBBR) is an electronic circuit that bucks a power-supply voltage to a lower regulated value or boosts it to a higher regulated value. The concept of the SCBBR is a generalization of the concept of the SCBR, which was reported in "Series-Connected Boost Regulators" (LEW-15918), NASA Tech Briefs, Vol. 23, No. 7 (July 1997), page 42. Relative to prior DC-voltage-regulator concepts, the SCBBR concept can yield significant reductions in weight and increases in power-conversion efficiency in many applications in which input/output voltage ratios are relatively small and isolation is not required, as solar-array regulation or battery charging with DC-bus regulation. Usually, a DC voltage regulator is designed to include a DC-to-DC converter to reduce its power loss, size, and weight. Advances in components, increases in operating frequencies, and improved circuit topologies have led to continual increases in efficiency and/or decreases in the sizes and weights of DC voltage regulators. The primary source of inefficiency in the DC-to-DC converter portion of a voltage regulator is the conduction loss and, especially at high frequencies, the switching loss. Although improved components and topology can reduce the switching loss, the reduction is limited by the fact that the converter generally switches all the power being regulated. Like the SCBR concept, the SCBBR concept involves a circuit configuration in which only a fraction of the power is switched, so that the switching loss is reduced by an amount that is largely independent of the specific components and circuit topology used. In an SCBBR, the amount of power switched by the DC-to-DC converter is only the amount needed to make up the difference between the input and output bus voltage. The remaining majority of the power passes through the converter without being switched. The weight and power loss of a DC-to-DC converter are determined primarily by the amount of power processed. In the SCBBR, the unswitched majority of the power is passed through with very little power loss, and little if any increase in the sizes of the converter components is needed to enable the components to handle the unswitched power. As a result, the power-conversion efficiency of the regulator can be very high, as shown in the example of Figure 1. A basic SCBBR includes a DC-to-DC converter (see Figure 2). The switches and primary winding of a transformer in the converter is connected across the input bus, while the secondary winding and switches are connected in series with the output bus, so that the output voltage is the sum of the input voltage and the secondary voltage of the converter. In the breadboard SCBBR, the input voltage applied to the primary winding is switched by use of metal oxide/semiconductor field-effect transistors (MOSFETs) in a full bridge circuit; the secondary winding is center-tapped, with two MOSFET switches and diode rectifiers connected in opposed series in each leg. The sets of opposed switches and rectifiers are what enable operation in either a boost or a buck mode. In the boost mode, input voltage and current, and the output voltage and current are all positive; that is, the secondary voltage is added to the input voltage and the net output voltage can be regulated at a value equal or greater than the input voltage. In the buck mode, input voltage is still positive and the current still flows in the same direction in the secondary, but the switches are controlled such that some power flows from the secondary to the primary. The voltage across the secondary and the current into the primary are reversed. The result is that the output voltage is lower than the input voltage, and some power is recirculated from the converter secondary back to the input. Quantitatively, the advantage of an SCBBR is a direct function of the regulation range required. If, for example, a regulation range of 20 percent is required for a 500-W supply, th it suffices to design the DC-to-DC converter in the SCBBR for a power rating of only 100 W. The switching loss and size are much smaller than those of a conventional regulator that must be rated for switching of all 500 W. The reduction in size and the increase in efficiency are not directly proportional to switched-power ratio of 5:1 because the additional switches contribute some conduction loss and the input and output filters must be larger than those typically required for a 100-W converter. Nevertheless, the power loss and the size can be much smaller than those of a 500-W converter.

Power-control switch

NASA Technical Reports Server (NTRS)

Kessler, L. L.

1976-01-01

Constant-current source creates drive current independent of input-voltage variations, 50% reduction in power loss in base drive circuitry, maintains essentially constant charge rate, and improves rise-time consistency over input voltage range.

Disinfection by electrohydraulic treatment.

PubMed

Allen, M; Soike, K

1967-04-28

Electrohydraulic treatment was applied to suspensions of Escherichia coli, spores of Bacillus subtilis var. niger, Saccharomyces cerevisiae, and bacteriophage T2 at an input energy that, in most cases, was below the energy required to sterilize. The input energy was held relatively constant for each of these microorganisms, but the capacitance and voltage were varied. Data are presented which show the degree of disinfection as a function of capacitance and voltage. In all cases, the degree of disinfection for a given input energy increases as both capacitance and voltage are lowered.

Apparatus and method for detecting and measuring changes in linear relationships between a number of high frequency signals

DOEpatents

Bittner, J.W.; Biscardi, R.W.

1991-03-19

An electronic measurement circuit is disclosed for high speed comparison of the relative amplitudes of a predetermined number of electrical input signals independent of variations in the magnitude of the sum of the signals. The circuit includes a high speed electronic switch that is operably connected to receive on its respective input terminals one of said electrical input signals and to have its common terminal serve as an input for a variable-gain amplifier-detector circuit that is operably connected to feed its output to a common terminal of a second high speed electronic switch. The respective terminals of the second high speed electronic switch are operably connected to a plurality of integrating sample and hold circuits, which in turn have their outputs connected to a summing logic circuit that is operable to develop first, second and third output voltages, the first output voltage being proportional to a predetermined ratio of sums and differences between the compared input signals, the second output voltage being proportional to a second summed ratio of predetermined sums and differences between said input signals, and the third output voltage being proportional to the sum of signals to the summing logic circuit. A servo system that is operably connected to receive said third output signal and compare it with a reference voltage to develop a slowly varying feedback voltage to control the variable-gain amplifier in said common amplifier-detector circuit in order to make said first and second output signals independent of variations in the magnitude of the sum of said input signals. 2 figures.

Apparatus and method for detecting and measuring changes in linear relationships between a number of high frequency signals

DOEpatents

Bittner, John W.; Biscardi, Richard W.

1991-01-01

An electronic measurement circuit for high speed comparison of the relative amplitudes of a predetermined number of electrical input signals independent of variations in the magnitude of the sum of the signals. The circuit includes a high speed electronic switch that is operably connected to receive on its respective input terminals one of said electrical input signals and to have its common terminal serve as an input for a variable-gain amplifier-detector circuit that is operably connected to feed its output to a common terminal of a second high speed electronic switch. The respective terminals of the second high speed electronic switch are operably connected to a plurality of integrating sample and hold circuits, which in turn have their outputs connected to a summing logic circuit that is operable to develop first, second and third output voltages, the first output voltage being proportional to a predetermined ratio of sums and differences between the compared input signals, the second output voltage being proportional to a second summed ratio of predetermined sums and differences between said input signals, and the third output voltage being proportional to the sum of signals to the summing logic circuit. A servo system that is operably connected to receive said third output signal and compare it with a reference voltage to develop a slowly varying feedback voltage to control the variable-gain amplifier in said common amplifier-detector circuit in order to make said first and second output signals independent of variations in the magnitude of the sum of said input signals.

Piezoelectric Vibrational and Acoustic Alert for a Personal Communication Device

NASA Technical Reports Server (NTRS)

Woodard, Stanley E. (Inventor); Hellbaum, Richard F. (Inventor); Daugherty, Robert H. (Inventor); Scholz, Raymond C. (Inventor); Little, Bruce D. (Inventor); Fox, Robert L. (Inventor); Denhardt, Gerald A. (Inventor); Jang, SeGon (Inventor); Balein, Rizza (Inventor)

2001-01-01

An alert apparatus for a personal communication device includes a mechanically prestressed piezoelectric wafer positioned within the personal communication device and an alternating voltage input line coupled at two points of the wafer where polarity is recognized. The alert apparatus also includes a variable frequency device coupled to the alternating voltage input line, operative to switch the alternating voltage on the alternating voltage input line at least between an alternating voltage having a first frequency and an alternating voltage having a second frequency. The first frequency is preferably sufficiently high so as to cause the wafer to vibrate at a resulting frequency that produces a sound perceptible by a human ear, and the second frequency is preferably sufficiently low so as to cause the wafer to vibrate at a resulting frequency that produces a vibration readily felt by a holder of the personal communication device.

Improved Reliability of SiC Pressure Sensors for Long Term High Temperature Applications

NASA Technical Reports Server (NTRS)

Okojie, R. S.; Nguyen, V.; Savrun, E.; Lukco, D.

2011-01-01

We report advancement in the reliability of silicon carbide pressure sensors operating at 600 C for extended periods. The large temporal drifts in zero pressure offset voltage at 600 C observed previously were significantly suppressed to allow improved reliable operation. This improvement was the result of further enhancement of the electrical and mechanical integrity of the bondpad/contact metallization, and the introduction of studded bump bonding on the pad. The stud bump contact promoted strong adhesion between the Au bond pad and the Au die-attach. The changes in the zero offset voltage and bridge resistance over time at temperature were explained by the microstructure and phase changes within the contact metallization, that were analyzed with Auger electron spectroscopy (AES) and field emission scanning electron microscopy (FE-SEM).

A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.

PubMed

Wang, Yi-Xiao; Chen, Wei-Ming; Wu, Chung-Yu

2014-01-01

This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.

Voltage controlled current source

DOEpatents

Casne, Gregory M.

1992-01-01

A seven decade, voltage controlled current source is described for use in testing intermediate range nuclear instruments that covers the entire test current range of from 10 picoamperes to 100 microamperes. High accuracy is obtained throughout the entire seven decades of output current with circuitry that includes a coordinated switching scheme responsive to the input signal from a hybrid computer to control the input voltage to an antilog amplifier, and to selectively connect a resistance to the antilog amplifier output to provide a continuous output current source as a function of a preset range of input voltage. An operator controlled switch provides current adjustment for operation in either a real-time simulation test mode or a time response test mode.

An integrated signal conditioner for high-frequency inductive position sensors

NASA Astrophysics Data System (ADS)

Rahal, Mohamad; Demosthenous, Andreas

2010-01-01

This paper describes the design, implementation and evaluation of a signal conditioner application-specific integrated circuit (ASIC) for high-frequency inductive non-contact position sensors. These sensors employ a radio frequency technology based on an antenna planar arrangement and a resonant target, have a high inherent resolution (0.1% of antenna length) and can measure target position over a wide distance range (<0.1 mm to >10 m). However, due to the relatively high-frequency excitation (1 MHz typically) and to the specific layouts of these sensors, there is unwanted capacitive coupling between the transmitter and receiver coils; this type of distortion reduces linearity and resolution. The ASIC, which is the first generation of its kind for this type of sensor, employs a differential mixer topology which suppresses the capacitive coupling offsets. The system architecture and circuit details are presented. The ASIC was fabricated in a 0.6 µm high-voltage CMOS technology occupying an area of 8 mm2. It dissipates about 30 mA from a 24 V power supply. The ASIC was tested with a high-frequency inductive position sensor (with an antenna length of 10.8 cm). The measured input-referred offset due to transmitter crosstalk is on average about 22 µV over a wide phase difference variation (-99° to +117°) between the transmitter and demodulating signals.

System and method for motor speed estimation of an electric motor

DOEpatents

Lu, Bin [Kenosha, WI; Yan, Ting [Brookfield, WI; Luebke, Charles John [Sussex, WI; Sharma, Santosh Kumar [Viman Nagar, IN

2012-06-19

A system and method for a motor management system includes a computer readable storage medium and a processing unit. The processing unit configured to determine a voltage value of a voltage input to an alternating current (AC) motor, determine a frequency value of at least one of a voltage input and a current input to the AC motor, determine a load value from the AC motor, and access a set of motor nameplate data, where the set of motor nameplate data includes a rated power, a rated speed, a rated frequency, and a rated voltage of the AC motor. The processing unit is also configured to estimate a motor speed based on the voltage value, the frequency value, the load value, and the set of nameplate data and also store the motor speed on the computer readable storage medium.

DC attenuation meter

DOEpatents

Hargrove, Douglas L.

2004-09-14

A portable, hand-held meter used to measure direct current (DC) attenuation in low impedance electrical signal cables and signal attenuators. A DC voltage is applied to the signal input of the cable and feedback to the control circuit through the signal cable and attenuators. The control circuit adjusts the applied voltage to the cable until the feedback voltage equals the reference voltage. The "units" of applied voltage required at the cable input is the system attenuation value of the cable and attenuators, which makes this meter unique. The meter may be used to calibrate data signal cables, attenuators, and cable-attenuator assemblies.

Series resonant converter with auxiliary winding turns: analysis, design and implementation

NASA Astrophysics Data System (ADS)

Lin, Bor-Ren

2018-05-01

Conventional series resonant converters have researched and applied for high-efficiency power units due to the benefit of its low switching losses. The main problems of series resonant converters are wide frequency variation and high circulating current. Thus, resonant converter is limited at narrow input voltage range and large input capacitor is normally adopted in commercial power units to provide the minimum hold-up time requirement when AC power is off. To overcome these problems, the resonant converter with auxiliary secondary windings are presented in this paper to achieve high voltage gain at low input voltage case such as hold-up time duration when utility power is off. Since the high voltage gain is used at low input voltage cased, the frequency variation of the proposed converter compared to the conventional resonant converter is reduced. Compared to conventional resonant converter, the hold-up time in the proposed converter is more than 40ms. The larger magnetising inductance of transformer is used to reduce the circulating current losses. Finally, a laboratory prototype is constructed and experiments are provided to verify the converter performance.

Chemical sensors are hybrid-input memristors

NASA Astrophysics Data System (ADS)

Sysoev, V. I.; Arkhipov, V. E.; Okotrub, A. V.; Pershin, Y. V.

2018-04-01

Memristors are two-terminal electronic devices whose resistance depends on the history of input signal (voltage or current). Here we demonstrate that the chemical gas sensors can be considered as memristors with a generalized (hybrid) input, namely, with the input consisting of the voltage, analyte concentrations and applied temperature. The concept of hybrid-input memristors is demonstrated experimentally using a single-walled carbon nanotubes chemical sensor. It is shown that with respect to the hybrid input, the sensor exhibits some features common with memristors such as the hysteretic input-output characteristics. This different perspective on chemical gas sensors may open new possibilities for smart sensor applications.

Ferroresonant flux coupled battery charger

NASA Technical Reports Server (NTRS)

McLyman, Colonel W. T. (Inventor)

1987-01-01

A battery charger for incorporation into an electric-powered vehicle is disclosed. The charger includes a ferroresonant voltage-regulating circuit for providing an output voltage proportional to the frequency of an input AC voltage. A high frequency converter converts a DC voltage supplied, for example, from a rectifier connected to a standard AC outlet, to a controlled frequency AC voltage which is supplied to the input of the ferroresonant circuit. The ferroresonant circuit includes an output, a saturable core transformer connected across the output, and a first linear inductor and a capacitor connected in series across the saturable core transformer and tuned to resonate at the third harmonic of the AC voltage from the high frequency converter. The ferroresonant circuit further includes a second linear inductor connected between the input of the ferroresonant circuit and the saturable core transformer. The output voltage from the ferroresonant circuit is rectified and applied across a pair of output terminals adapted to be connected to the battery to be charged. A feedback circuit compares the voltage across the output terminals with a reference voltage and controls the frequency of the AC voltage produced by the high frequency converter to maintain the voltage across the output terminals at a predetermined value. The second linear inductor provides a highly reactive load in the event of a fault across the output terminals to render the charger short-circuit proof.

Piezoelectric transformers for low-voltage generation of gas discharges and ionic winds in atmospheric air

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnson, Michael J.; Go, David B., E-mail: dgo@nd.edu; Department of Chemical and Biomolecular Engineering, University of Notre Dame, Notre Dame, Indianapolis 46556

To generate a gas discharge (plasma) in atmospheric air requires an electric field that exceeds the breakdown threshold of ∼30 kV/cm. Because of safety, size, or cost constraints, the large applied voltages required to generate such fields are often prohibitive for portable applications. In this work, piezoelectric transformers are used to amplify a low input applied voltage (<30 V) to generate breakdown in air without the need for conventional high-voltage electrical equipment. Piezoelectric transformers (PTs) use their inherent electromechanical resonance to produce a voltage amplification, such that the surface of the piezoelectric exhibits a large surface voltage that can generate corona-like dischargesmore » on its corners or on adjacent electrodes. In the proper configuration, these discharges can be used to generate a bulk air flow called an ionic wind. In this work, PT-driven discharges are characterized by measuring the discharge current and the velocity of the induced ionic wind with ionic winds generated using input voltages as low as 7 V. The characteristics of the discharge change as the input voltage increases; this modifies the resonance of the system and subsequent required operating parameters.« less

Wide-temperature integrated operational amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad (Inventor); Levanas, Greg (Inventor); Chen, Yuan (Inventor); Cozy, Raymond S. (Inventor); Greenwell, Robert (Inventor); Terry, Stephen (Inventor); Blalock, Benjamin J. (Inventor)

2009-01-01

The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.

Zero-voltage DC/DC converter with asymmetric pulse-width modulation for DC micro-grid system

NASA Astrophysics Data System (ADS)

Lin, Bor-Ren

2018-04-01

This paper presents a zero-voltage switching DC/DC converter for DC micro-grid system applications. The proposed circuit includes three half-bridge circuit cells connected in primary-series and secondary-parallel in order to lessen the voltage rating of power switches and current rating of rectifier diodes. Thus, low voltage stress of power MOSFETs can be adopted for high-voltage input applications with high switching frequency operation. In order to achieve low switching losses and high circuit efficiency, asymmetric pulse-width modulation is used to turn on power switches at zero voltage. Flying capacitors are used between each circuit cell to automatically balance input split voltages. Therefore, the voltage stress of each power switch is limited at Vin/3. Finally, a prototype is constructed and experiments are provided to demonstrate the circuit performance.

Four-Quadrant Analog Multipliers Using G4-FETs

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Blalock, Benjamin; Christoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

2006-01-01

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

THE POSITIVITY OFFSET THEORY OF ANHEDONIA IN SCHIZOPHRENIA

PubMed Central

Strauss, Gregory P.; Frost, Katherine H.; Lee, Bern G.; Gold, James M.

2016-01-01

Prior studies have concluded that schizophrenia patients are not anhedonic because they do not report reduced experience of positive emotion to pleasant stimuli. The current study challenged this view by applying quantitative methods validated in the Evaluative Space Model of emotional experience to test the hypothesis that schizophrenia patients evidence a reduction in the normative “positivity offset” (i.e., the tendency to experience higher levels of positive than negative emotional output when stimulus input is absent or weak). Participants included 76 schizophrenia patients and 60 healthy controls who completed an emotional experience task that required reporting the level of positive emotion, negative emotion, and arousal to photographs. Results indicated that although schizophrenia patients evidenced intact capacity to experience positive emotion at high levels of stimulus input, they displayed a diminished positivity offset. Reductions in the positivity offset may underlie volitional disturbance, limiting approach behaviors toward novel stimuli in neutral environments. PMID:28497008

A 160 μA biopotential acquisition IC with fully integrated IA and motion artifact suppression.

PubMed

Van Helleputte, Nick; Kim, Sunyoung; Kim, Hyejung; Kim, Jong Pal; Van Hoof, Chris; Yazicioglu, Refet Firat

2012-12-01

This paper proposes a 3-channel biopotential monitoring ASIC with simultaneous electrode-tissue impedance measurements which allows real-time estimation of motion artifacts on each channel using an an external μC. The ASIC features a high performance instrumentation amplifier with fully integrated sub-Hz HPF rejecting rail-to-rail electrode-offset voltages. Each readout channel further has a programmable gain amplifier and programmable 4th order low-pass filter. Time-multiplexed 12 b SAR-ADCs are used to convert all the analog data to digital. The ASIC achieves >; 115 dB of CMRR (at 50/60 Hz), a high input impedance of >; 1 GΩ and low noise (1.3 μVrms in 100 Hz). Unlike traditional methods, the ASIC is capable of actual motion artifact suppression in the analog domain before final amplification. The complete ASIC core operates from 1.2 V with 2 V digital IOs and consumes 200 μW when all 3 channels are active.

Application of neural models as controllers in mobile robot velocity control loop

NASA Astrophysics Data System (ADS)

Cerkala, Jakub; Jadlovska, Anna

2017-01-01

This paper presents the application of an inverse neural models used as controllers in comparison to classical PI controllers for velocity tracking control task used in two-wheel, differentially driven mobile robot. The PI controller synthesis is based on linear approximation of actuators with equivalent load. In order to obtain relevant datasets for training of feed-forward multi-layer perceptron based neural network used as neural model, the mathematical model of mobile robot, that combines its kinematic and dynamic properties such as chassis dimensions, center of gravity offset, friction and actuator parameters is used. Neural models are trained off-line to act as an inverse dynamics of DC motors with particular load using data collected in simulation experiment for motor input voltage step changes within bounded operating area. The performances of PI controllers versus inverse neural models in mobile robot internal velocity control loops are demonstrated and compared in simulation experiment of navigation control task for line segment motion in plane.

Batteryless Electroencephalography (EEG): Subthreshold Voltage System-on-a-Chip (SoC) Design for Neurophysiological Measurement

DTIC Science & Technology

2015-03-01

example, be harvested via thermoelectric coupling requiring only a 1 °C temperature gradient (supplied by the human scalp at ambient room...controller. The amplifier chain will consist of a differential low-noise amplifier (LNA) with digitally modulated , voltage-offset control and a variable...result in decreased vertical resolution of the digitized signal, even in conjunction with the VOC/VGA modulation described above. Figure 4 shows

High speed preamplifier circuit, detection electronics, and radiation detection systems therefrom

DOEpatents

Riedel, Richard A [Knoxville, TN; Wintenberg, Alan L [Knoxville, TN; Clonts, Lloyd G [Knoxville, TN; Cooper, Ronald G [Oak Ridge, TN

2010-09-21

A preamplifier circuit for processing a signal provided by a radiation detector includes a transimpedance amplifier coupled to receive a current signal from a detector and generate a voltage signal at its output. A second amplification stage has an input coupled to an output of the transimpedance amplifier for providing an amplified voltage signal. Detector electronics include a preamplifier circuit having a first and second transimpedance amplifier coupled to receive a current signal from a first and second location on a detector, respectively, and generate a first and second voltage signal at respective outputs. A second amplification stage has an input coupled to an output of the transimpedance amplifiers for amplifying the first and said second voltage signals to provide first and second amplified voltage signals. A differential output stage is coupled to the second amplification stage for receiving the first and second amplified voltage signals and providing a pair of outputs from each of the first and second amplified voltage signals. Read out circuitry has an input coupled to receive both of the pair of outputs, the read out circuitry having structure for processing each of the pair of outputs, and providing a single digital output having a time-stamp therefrom.

Radiation detection system

DOEpatents

Riedel, Richard A [Knoxville, TN; Wintenberg, Alan L [Knoxville, TN; Clonts, Lloyd G [Knoxville, TN; Cooper, Ronald G [Oak Ridge, TN

2012-02-14

A preamplifier circuit for processing a signal provided by a radiation detector includes a transimpedance amplifier coupled to receive a current signal from a detector and generate a voltage signal at its output. A second amplification stage has an input coupled to an output of the transimpedance amplifier for providing an amplified voltage signal. Detector electronics include a preamplifier circuit having a first and second transimpedance amplifier coupled to receive a current signal from a first and second location on a detector, respectively, and generate a first and second voltage signal at respective outputs. A second amplification stage has an input coupled to an output of the transimpedance amplifiers for amplifying the first and said second voltage signals to provide first and second amplified voltage signals. A differential output stage is coupled to the second amplification stage for receiving the first and second amplified voltage signals and providing a pair of outputs from each of the first and second amplified voltage signals. Read out circuitry has an input coupled to receive both of the pair of outputs, the read out circuitry having structure for processing each of the pair of outputs, and providing a single digital output having a time-stamp therefrom.

High voltage electrical amplifier having a short rise time

DOEpatents

Christie, David J.; Dallum, Gregory E.

1991-01-01

A circuit, comprising an amplifier and a transformer is disclosed that produces a high power pulse having a fast response time, and that responds to a digital control signal applied through a digital-to-analog converter. The present invention is suitable for driving a component such as an electro-optic modulator with a voltage in the kilovolt range. The circuit is stable at high frequencies and during pulse transients, and its impedance matching circuit matches the load impedance with the output impedance. The preferred embodiment comprises an input stage compatible with high-speed semiconductor components for amplifying the voltage of the input control signal, a buffer for isolating the input stage from the output stage; and a plurality of current amplifiers connected to the buffer. Each current amplifier is connected to a field effect transistor (FET), which switches a high voltage power supply to a transformer which then provides an output terminal for driving a load. The transformer comprises a plurality of transmission lines connected to the FETs and the load. The transformer changes the impedance and voltage of the output. The preferred embodiment also comprises a low voltage power supply for biasing the FETs at or near an operational voltage.

High ESD Breakdown-Voltage InP HBT Transimpedance Amplifier IC for Optical Video Distribution Systems

NASA Astrophysics Data System (ADS)

Sano, Kimikazu; Nagatani, Munehiko; Mutoh, Miwa; Murata, Koichi

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000V for power supply terminals, ±200V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7pA/√Hz averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

Membrane voltage fluctuations reduce spike frequency adaptation and preserve output gain in CA1 pyramidal neurons in a high conductance state

PubMed Central

Fernandez, Fernando R.; Broicher, Tilman; Truong, Alan; White, John A.

2011-01-01

Modulating the gain of the input-output function of neurons is critical for processing of stimuli and network dynamics. Previous gain control mechanisms have suggested that voltage fluctuations play a key role in determining neuronal gain in vivo. Here we show that, under increased membrane conductance, voltage fluctuations restore Na+ current and reduce spike frequency adaptation in rat hippocampal CA1 pyramidal neurons in vitro. As a consequence, membrane voltage fluctuations produce a leftward shift in the f-I relationship without a change in gain, relative to an increase in conductance alone. Furthermore, we show that these changes have important implications for the integration of inhibitory inputs. Due to the ability to restore Na+ current, hyperpolarizing membrane voltage fluctuations mediated by GABAA-like inputs can increase firing rate in a high conductance state. Finally, our data show that the effects on gain and synaptic integration are mediated by voltage fluctuations within a physiologically relevant range of frequencies (10–40 Hz). PMID:21389243

Voltage balanced multilevel voltage source converter system

DOEpatents

Peng, Fang Zheng; Lai, Jih-Sheng

1997-01-01

A voltage balanced multilevel converter for high power AC applications such as adjustable speed motor drives and back-to-back DC intertie of adjacent power systems. This converter provides a multilevel rectifier, a multilevel inverter, and a DC link between the rectifier and the inverter allowing voltage balancing between each of the voltage levels within the multilevel converter. The rectifier is equipped with at least one phase leg and a source input node for each of the phases. The rectifier is further equipped with a plurality of rectifier DC output nodes. The inverter is equipped with at least one phase leg and a load output node for each of the phases. The inverter is further equipped with a plurality of inverter DC input nodes. The DC link is equipped with a plurality of rectifier charging means and a plurality of inverter discharging means. The plurality of rectifier charging means are connected in series with one of the rectifier charging means disposed between and connected in an operable relationship with each adjacent pair of rectifier DC output nodes. The plurality of inverter discharging means are connected in series with one of the inverter discharging means disposed between and connected in an operable relationship with each adjacent pair of inverter DC input nodes. Each of said rectifier DC output nodes are individually electrically connected to the respective inverter DC input nodes. By this means, each of the rectifier DC output nodes and each of the inverter DC input nodes are voltage balanced by the respective charging and discharging of the rectifier charging means and the inverter discharging means.

Voltage balanced multilevel voltage source converter system

DOEpatents

Peng, F.Z.; Lai, J.S.

1997-07-01

Disclosed is a voltage balanced multilevel converter for high power AC applications such as adjustable speed motor drives and back-to-back DC intertie of adjacent power systems. This converter provides a multilevel rectifier, a multilevel inverter, and a DC link between the rectifier and the inverter allowing voltage balancing between each of the voltage levels within the multilevel converter. The rectifier is equipped with at least one phase leg and a source input node for each of the phases. The rectifier is further equipped with a plurality of rectifier DC output nodes. The inverter is equipped with at least one phase leg and a load output node for each of the phases. The inverter is further equipped with a plurality of inverter DC input nodes. The DC link is equipped with a plurality of rectifier charging means and a plurality of inverter discharging means. The plurality of rectifier charging means are connected in series with one of the rectifier charging means disposed between and connected in an operable relationship with each adjacent pair of rectifier DC output nodes. The plurality of inverter discharging means are connected in series with one of the inverter discharging means disposed between and connected in an operable relationship with each adjacent pair of inverter DC input nodes. Each of said rectifier DC output nodes are individually electrically connected to the respective inverter DC input nodes. By this means, each of the rectifier DC output nodes and each of the inverter DC input nodes are voltage balanced by the respective charging and discharging of the rectifier charging means and the inverter discharging means. 15 figs.

Adaptive gain, equalization, and wavelength stabilization techniques for silicon photonic microring resonator-based optical receivers

NASA Astrophysics Data System (ADS)

Palermo, Samuel; Chiang, Patrick; Yu, Kunzhi; Bai, Rui; Li, Cheng; Chen, Chin-Hui; Fiorentino, Marco; Beausoleil, Ray; Li, Hao; Shafik, Ayman; Titriku, Alex

2016-03-01

Interconnect architectures based on high-Q silicon photonic microring resonator devices offer a promising solution to address the dramatic increase in datacenter I/O bandwidth demands due to their ability to realize wavelength-division multiplexing (WDM) in a compact and energy efficient manner. However, challenges exist in realizing efficient receivers for these systems due to varying per-channel link budgets, sensitivity requirements, and ring resonance wavelength shifts. This paper reports on adaptive optical receiver design techniques which address these issues and have been demonstrated in two hybrid-integrated prototypes based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. A 10Gb/s powerscalable architecture employs supply voltage scaling of a three inverter-stage transimpedance amplifier (TIA) that is adapted with an eye-monitor control loop to yield the necessary sensitivity for a given channel. As reduction of TIA input-referred noise is more critical at higher data rates, a 25Gb/s design utilizes a large input-stage feedback resistor TIA cascaded with a continuous-time linear equalizer (CTLE) that compensates for the increased input pole. When tested with a waveguide Ge PD with 0.45A/W responsivity, this topology achieves 25Gb/s operation with -8.2dBm sensitivity at a BER=10-12. In order to address microring drop filters sensitivity to fabrication tolerances and thermal variations, efficient wavelength-stabilization control loops are necessary. A peak-power-based monitoring loop which locks the drop filter to the input wavelength, while achieving compatibility with the high-speed TIA offset-correction feedback loop is implemented with a 0.7nm tuning range at 43μW/GHz efficiency.

ULTRA-STABILIZED D. C. AMPLIFIER

DOEpatents

Hartwig, E.C.; Kuenning, R.W.; Acker, R.C.

1959-02-17

An improved circuit is described for stabilizing the drift and minimizing the noise and hum level of d-c amplifiers so that the output voltage will be zero when the input is zero. In its detailed aspects, the disclosed circuit incorporates a d-c amplifier having a signal input, a second input, and an output circuit coupled back to the first input of the amplifier through inverse feedback means. An electronically driven chopper having a pair of fixed contacts and a moveable contact alternately connects the two inputs of a difference amplifier to the signal input. The A. E. error signal produced in the difference amplifier is amplified, rectified, and applied to the second input of the amplifier as the d-c stabilizing voltage.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shepard, Kenneth L.; Sturcken, Noah Andrew

Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage usingmore » the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.« less

Laminated piezoelectric transformer

NASA Technical Reports Server (NTRS)

Vazquez Carazo, Alfredo (Inventor)

2006-01-01

A laminated piezoelectric transformer is provided using the longitudinal vibration modes for step-up voltage conversion applications. The input portions are polarized to deform in a longitudinal plane and are bonded to an output portion. The deformation of the input portions is mechanically coupled to the output portion, which deforms in the same longitudinal direction relative to the input portion. The output portion is polarized in the thickness direction relative its electrodes, and piezoelectrically generates a stepped-up output voltage.

Self-Nulling Lock-in Detection Electronics for Capacitance Probe Electrometer

NASA Technical Reports Server (NTRS)

Blaes, Brent R.; Schaefer, Rembrandt T.

2012-01-01

A multi-channel electrometer voltmeter that employs self-nulling lock-in detection electronics in conjunction with a mechanical resonator with noncontact voltage sensing electrodes has been developed for space-based measurement of an Internal Electrostatic Discharge Monitor (IESDM). The IESDM is new sensor technology targeted for integration into a Space Environmental Monitor (SEM) subsystem used for the characterization and monitoring of deep dielectric charging on spacecraft. Use of an AC-coupled lock-in amplifier with closed-loop sense-signal nulling via generation of an active guard-driving feedback voltage provides the resolution, accuracy, linearity and stability needed for long-term space-based measurement of the IESDM. This implementation relies on adjusting the feedback voltage to drive the sense current received from the resonator s variable-capacitance-probe voltage transducer to approximately zero, as limited by the signal-to-noise performance of the loop electronics. The magnitude of the sense current is proportional to the difference between the input voltage being measured and the feedback voltage, which matches the input voltage when the sense current is zero. High signal-to-noise-ratio (SNR) is achieved by synchronous detection of the sense signal using the correlated reference signal derived from the oscillator circuit that drives the mechanical resonator. The magnitude of the feedback voltage, while the loop is in a settled state with essentially zero sense current, is an accurate estimate of the input voltage being measured. This technique has many beneficial attributes including immunity to drift, high linearity, high SNR from synchronous detection of a single-frequency carrier selected to avoid potentially noisy 1/f low-frequency spectrum of the signal-chain electronics, and high accuracy provided through the benefits of a driven shield encasing the capacitance- probe transducer and guarded input triaxial lead-in. Measurements obtained from a 2- channel prototype electrometer have demonstrated good accuracy (|error| < 0.2 V) and high stability. Twenty-four-hour tests have been performed with virtually no drift. Additionally, 5,500 repeated one-second measurements of 100 V input were shown to be approximately normally distributed with a standard deviation of 140 mV.

Dual physiological rate measurement instrument

NASA Technical Reports Server (NTRS)

Cooper, Tommy G. (Inventor)

1990-01-01

The object of the invention is to provide an instrument for converting a physiological pulse rate into a corresponding linear output voltage. The instrument which accurately measures the rate of an unknown rectangular pulse wave over an extended range of values comprises a phase-locked loop including a phase comparator, a filtering network, and a voltage-controlled oscillator, arranged in cascade. The phase comparator has a first input responsive to the pulse wave and a second input responsive to the output signal of the voltage-controlled oscillator. The comparator provides a signal dependent on the difference in phase and frequency between the signals appearing on the first and second inputs. A high-input impedance amplifier accepts an output from the filtering network and provides an amplified output DC signal to a utilization device for providing a measurement of the rate of the pulse wave.

TRIAC/SCR proportional control circuit

DOEpatents

Hughes, Wallace J.

1999-01-01

A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

Piezoelectric transformer and modular connections for high power and high voltage power supplies

NASA Technical Reports Server (NTRS)

Vazquez Carazo, Alfredo (Inventor)

2006-01-01

A modular design for combining piezoelectric transformers is provided for high voltage and high power conversion applications. The input portions of individual piezoelectric transformers are driven for a single power supply. This created the vibration and the conversion of electrical to electrical energy from the input to the output of the transformers. The output portions of the single piezoelectric transformers are combining in series and/or parallel to provide multiple outputs having different rating of voltage and current.

Frequency to Voltage Converter Analog Front-End Prototype

NASA Technical Reports Server (NTRS)

Mata, Carlos; Raines, Matthew

2012-01-01

The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

Precision electronic speed controller for an alternating-current motor

DOEpatents

Bolie, V.W.

A high precision controller for an alternating-current multi-phase electrical motor that is subject to a large inertial load. The controller was developed for controlling, in a neutron chopper system, a heavy spinning rotor that must be rotated in phase-locked synchronism with a reference pulse train that is representative of an ac power supply signal having a meandering line frequency. The controller includes a shaft revolution sensor which provides a feedback pulse train representative of the actual speed of the motor. An internal digital timing signal generator provides a reference signal which is compared with the feedback signal in a computing unit to provide a motor control signal. The motor control signal is a weighted linear sum of a speed error voltage, a phase error voltage, and a drift error voltage, each of which is computed anew with each revolution of the motor shaft. The speed error signal is generated by a novel vernier-logic circuit which is drift-free and highly sensitive to small speed changes. The phase error is also computed by digital logic, with adjustable sensitivity around a 0 mid-scale value. The drift error signal, generated by long-term counting of the phase error, is used to compensate for any slow changes in the average friction drag on the motor. An auxillary drift-byte status sensor prevents any disruptive overflow or underflow of the drift-error counter. An adjustable clocked-delay unit is inserted between the controller and the source of the reference pulse train to permit phase alignment of the rotor to any desired offset angle. The stator windings of the motor are driven by two amplifiers which are provided with input signals having the proper quadrature relationship by an exciter unit consisting of a voltage controlled oscillator, a binary counter, a pair of read-only memories, and a pair of digital-to-analog converters.

Voltage sensing systems and methods for passive compensation of temperature related intrinsic phase shift

DOEpatents

Davidson, James R.; Lassahn, Gordon D.

2001-01-01

A small sized electro-optic voltage sensor capable of accurate measurement of high levels of voltages without contact with a conductor or voltage source is provided. When placed in the presence of an electric field, the sensor receives an input beam of electromagnetic radiation into the sensor. A polarization beam displacer serves as a filter to separate the input beam into two beams with orthogonal linear polarizations. The beam displacer is oriented in such a way as to rotate the linearly polarized beams such that they enter a Pockels crystal at a preferred angle of 45 degrees. The beam displacer is therefore capable of causing a linearly polarized beam to impinge a crystal at a desired angle independent of temperature. The Pockels electro-optic effect induces a differential phase shift on the major and minor axes of the input beam as it travels through the Pockels crystal, which causes the input beam to be elliptically polarized. A reflecting prism redirects the beam back through the crystal and the beam displacer. On the return path, the polarization beam displacer separates the elliptically polarized beam into two output beams of orthogonal linear polarization representing the major and minor axes. In crystals that introduce a phase differential attributable to temperature, a compensating crystal is provided to cancel the effect of temperature on the phase differential of the input beam. The system may include a detector for converting the output beams into electrical signals, and a signal processor for determining the voltage based on an analysis of the output beams. The output beams are amplitude modulated by the frequency of the electric field and the amplitude of the output beams is proportional to the magnitude of the electric field, which is related to the voltage being measured.

Amplifier for measuring low-level signals in the presence of high common mode voltage

NASA Technical Reports Server (NTRS)

Lukens, F. E. (Inventor)

1985-01-01

A high common mode rejection differential amplifier wherein two serially arranged Darlington amplifier stages are employed and any common mode voltage is divided between them by a resistance network. The input to the first Darlington amplifier stage is coupled to a signal input resistor via an amplifier which isolates the input and presents a high impedance across this resistor. The output of the second Darlington stage is transposed in scale via an amplifier stage which has its input a biasing circuit which effects a finite biasing of the two Darlington amplifier stages.

Measuring Input Thresholds on an Existing Board

NASA Technical Reports Server (NTRS)

Kuperman, Igor; Gutrich, Daniel G.; Berkun, Andrew C.

2011-01-01

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Fully Integrated Biopotential Acquisition Analog Front-End IC

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

2015-01-01

A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 µm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm2. A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 µVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

Power conditioning system for energy sources

DOEpatents

Mazumder, Sudip K [Chicago, IL; Burra, Rajni K [Chicago, IL; Acharya, Kaustuva [Chicago, IL

2008-05-13

Apparatus for conditioning power generated by an energy source includes an inverter for converting a DC input voltage from the energy source to a square wave AC output voltage, and a converter for converting the AC output voltage from the inverter to a sine wave AC output voltage.

Comprehensive Testing of ASL-Owned Accelerometers

NASA Astrophysics Data System (ADS)

Evans, J. R.; Hutt, C. R.; Ringler, A. T.; de la Torre, T.

2011-12-01

The Albuquerque Seismological Laboratory (ASL) of the U.S. Geological Survey (USGS) has undertaken detailed testing of several commercial, off-the-shelf accelerometers to characterize production-standard examples of each instrument. The models tested are the Geotech PA-23, Guralp CMG-5TC, Kinemetrics ES-T (Episensor), Nanometrics Titan (sensor only), and RefTek RT-147-01/3. All are ±4 g accelerometers excepting the CMG-5TC at ±2 g (self noise could be depressed relative to 4-g variant). For dynamic tests, all were recorded on Quanterra Q330 (24-bit) or Q330HR (26-bit) recorders; for static tests high-precision multimeters were used (generally Agilent 3458A 81/2-digit or 34401A 61/2-digit). We also used a translational shake table (Anorad LW10-18-P-E-A-A-B-0) to input controlled test motions. We performed the tests described by Hutt et al. (2010; U.S. Geol. Surv. Open File Rep., 2009-1295, http://pubs.usgs.gov/of/2009/1295/) for these strong-motion sensors (Section 7, Recommended Testing for Strong Motion Acceleration Sensors). These recommended tests result from a public/private effort called "GST2" (the second Guidelines for Seismometer Testing workshop) and represent a consensus of experts in government, academia, and industry (a secondary goal of this work is vetting the tests in this consensus document). The recommended accelerometer tests are: 7.1 Power Demand (Start-up and Steady-State) 7.2 Static Sensitivity, Offset, and Linearity 7.3 Frequency Response and Bandwidth 7.4 Clip Level 7.5 Self Noise and Operating Range 7.6 Distortion 7.7 Orientation (Case to Actual) and Orthogonally 7.8 Translational Cross-Axis Sensitivity 7.9 Temperature Effects (Sensitivity and Offset) 7.10 Power Supply Voltage and Voltage-Noise Effects (Offset and Sensitivity) 7.11 Double Integration (Band-Limited Displacement Square Wave) To the degree the tests and analyses have progressed at this writing, the results are generally good but have revealed a number of issues needing attention. A complete set of test results will be provided at the conference. For example, median self noise of all units is within ANSS guidelines but some are as quiet as ~12 dB below the guidelines, while sensitivities of all but one (malfunctioning) channel are within the 1% guideline, and the orientations of axes relative to instrument cases are nearly all within the 1° guideline. (Any use of trade, firm, or product names is for descriptive purposes only and does not imply endorsement by the U.S. Government.)

78 FR 51463 - Energy Conservation Program: Energy Conservation Standards for Metal Halide Lamp Fixtures

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-20

... Efficiency at all Possible Voltages b. Posting the Highest and Lowest Efficiencies c. Test at Single Manufacturer-Declared Voltage d. Test at Highest-Rated Voltage e. Test on Input Voltage Based on Wattage and... at the highest voltage for which the ballast is designed to operate. [Dagger] P is defined as the...

TRIAC/SCR proportional control circuit

DOEpatents

Hughes, W.J.

1999-04-06

A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.

ELECTRONIC INTEGRATING CIRCUIT

DOEpatents

Englemann, R.H.

1963-08-20

An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

Analysis of improved dc and ac performances of an InGaP/GaAs heterojunction bipolar transistor with a graded Al xGa 1- xAs layer at emitter/base heterojunction

NASA Astrophysics Data System (ADS)

Cheng, Shiou-Ying

2004-07-01

An InGaP/GaAs heterojunction bipolar transistor (HBT) with a continuous conduction-band structure is demonstrated and theoretically investigated. This device exhibited good performance including lower turn-on voltage, lower offset voltage and smaller collector current saturation voltage. The novel aspect of device structure design is the adoption of the compositionally linear-graded AlGaAs layer between the InGaP-emitter and GaAs-base layers. Therefore, the device studied shows better dc and ac performances than a conventional device. Consequently, this causes the substantial benefit for practical analog and digital applications especially for lower operation voltage, lower power consumption commercial and military products.

Auto-steering apparatus and method

DOEpatents

McKay, Mark D.; Anderson, Matthew O.

2007-03-13

A vehicular guidance method involves providing a user interface using which data can be input to establish a contour for a vehicle to follow, the user interface further configured to receive information from a differential global positioning system (DGPS), determining cross track and offset data using information received from the DGPS, generating control values, using at least vehicular kinematics, the cross track, and the offset data, and providing an output to control steering of the vehicle, using the control values, in a direction to follow the established contour while attempting to minimize the cross track and the offset data.

Physical Theory of Voltage Fade in Lithium- and Manganese-Rich Transition Metal Oxides

DOE PAGES

Rinaldo, Steven G.; Gallagher, Kevin G.; Long, Brandon R.; ...

2015-03-04

Lithium- and manganese-rich (LMR) transition metal oxide cathodes are of interest for lithium-ion battery applications due to their increased energy density and decreased cost. However, the advantages in energy density and cost are offset, in part, due to the phenomena of voltage fade. Specifically, the voltage profiles (voltage as a function of capacity) of LMR cathodes transform from a high energy configuration to a lower energy configuration as they are repeatedly charged (Li removed) and discharged (Li inserted). Here, we propose a physical model of voltage fade that accounts for the emergence of a low voltage Li phase due tomore » the introduction of transition metal ion defects within a parent Li phase. The phenomenological model was re-cast in a general form and experimental LMR charge profiles were de-convoluted to extract the evolutionary behavior of various components of LMR capacitance profiles. Evolution of the voltage fade component was found to follow a universal growth curve with a maximal voltage fade capacity of ≈ 20% of the initial total capacity.« less

Graphene-assisted multiple-input high-base optical computing

PubMed Central

Hu, Xiao; Wang, Andong; Zeng, Mengqi; Long, Yun; Zhu, Long; Fu, Lei; Wang, Jian

2016-01-01

We propose graphene-assisted multiple-input high-base optical computing. We fabricate a nonlinear optical device based on a fiber pigtail cross-section coated with a single-layer graphene grown by chemical vapor deposition (CVD) method. An approach to implementing modulo 4 operations of three-input hybrid addition and subtraction of quaternary base numbers in the optical domain using multiple non-degenerate four-wave mixing (FWM) processes in graphene coated optical fiber device and (differential) quadrature phase-shift keying ((D)QPSK) signals is presented. We demonstrate 10-Gbaud modulo 4 operations of three-input quaternary hybrid addition and subtraction (A + B − C, A + C − B, B + C − A) in the experiment. The measured optical signal-to-noise ratio (OSNR) penalties for modulo 4 operations of three-input quaternary hybrid addition and subtraction (A + B − C, A + C − B, B + C − A) are measured to be less than 7 dB at a bit-error rate (BER) of 2 × 10−3. The BER performance as a function of the relative time offset between three signals (signal offset) is also evaluated showing favorable performance. PMID:27604866

Power supply

DOEpatents

Yakymyshyn, Christopher Paul; Hamilton, Pamela Jane; Brubaker, Michael Allen

2007-12-04

A modular, low weight impedance dropping power supply with battery backup is disclosed that can be connected to a high voltage AC source and provide electrical power at a lower voltage. The design can be scaled over a wide range of input voltages and over a wide range of output voltages and delivered power.

High dynamic range charge measurements

DOEpatents

De Geronimo, Gianluigi

2012-09-04

A charge amplifier for use in radiation sensing includes an amplifier, at least one switch, and at least one capacitor. The switch selectively couples the input of the switch to one of at least two voltages. The capacitor is electrically coupled in series between the input of the amplifier and the input of the switch. The capacitor is electrically coupled to the input of the amplifier without a switch coupled therebetween. A method of measuring charge in radiation sensing includes selectively diverting charge from an input of an amplifier to an input of at least one capacitor by selectively coupling an output of the at least one capacitor to one of at least two voltages. The input of the at least one capacitor is operatively coupled to the input of the amplifier without a switch coupled therebetween. The method also includes calculating a total charge based on a sum of the amplified charge and the diverted charge.

Utilizing zero-sequence switchings for reversible converters

DOEpatents

Hsu, John S.; Su, Gui-Jia; Adams, Donald J.; Nagashima, James M.; Stancu, Constantin; Carlson, Douglas S.; Smith, Gregory S.

2004-12-14

A method for providing additional dc inputs or outputs (49, 59) from a dc-to-ac inverter (10) for controlling motor loads (60) comprises deriving zero-sequence components (V.sub.ao, V.sub.bo, and V.sub.co) from the inverter (10) through additional circuit branches with power switching devices (23, 44, 46), transforming the voltage between a high voltage and a low voltage using a transformer or motor (42, 50), converting the low voltage between ac and dc using a rectifier (41, 51) or an H-bridge (61), and providing at least one low voltage dc input or output (49, 59). The transformation of the ac voltage may be either single phase or three phase. Where less than a 100% duty cycle is acceptable, a two-phase modulation of the switching signals controlling the inverter (10) reduces switching losses in the inverter (10). A plurality of circuits for carrying out the invention are also disclosed.

Two-electrode low supply voltage electrocardiogram signal amplifier.

PubMed

Dobrev, D

2004-03-01

Portable biomedical instrumentation has become an important part of diagnostic and treatment instrumentation, including telemedicine applications. Low-voltage and low-power design tendencies prevail. Modern battery cell voltages in the range of 3-3.6 V require appropriate circuit solutions. A two-electrode biopotential amplifier design is presented, with a high common-mode rejection ratio (CMRR), high input voltage tolerance and standard first-order high-pass characteristic. Most of these features are due to a high-gain first stage design. The circuit makes use of passive components of popular values and tolerances. Powered by a single 3 V source, the amplifier tolerates +/- 1 V common mode voltage, +/- 50 microA common mode current and 2 V input DC voltage, and its worst-case CMRR is 60 dB. The amplifier is intended for use in various applications, such as Holter-type monitors, defibrillators, ECG monitors, biotelemetry devices etc.

Static DC to DC Power Conditioning-Active Ripple Filter, 1 MHZ DC to DC Conversion, and Nonlinear Analysis. Ph.D. Thesis; [voltage regulation and conversion circuitry for spacecraft power supplies

NASA Technical Reports Server (NTRS)

Sander, W. A., III

1973-01-01

Dc to dc static power conditioning systems on unmanned spacecraft have as their inputs highly fluctuating dc voltages which they condition to regulated dc voltages. These input voltages may be less than or greater than the desired regulated voltages. The design of two circuits which address specific problems in the design of these power conditioning systems and a nonlinear analysis of one of the circuits are discussed. The first circuit design is for a nondissipative active ripple filter which uses an operational amplifier to amplify and cancel the sensed ripple voltage. A dc to dc converter operating at a switching frequency of 1 MHz is the second circuit discussed. A nonlinear analysis of the type of dc to dc converter utilized in designing the 1 MHz converter is included.

A 12 mV start-up converter using piezoelectric transformer for energy harvesting applications

NASA Astrophysics Data System (ADS)

Martinez, T.; Pillonnet, G.; Costa, F.

2016-11-01

This paper presents a novel topology of start-up converter for sub 100 mV thermal energy harvesting based on an Armstrong oscillator topology using a piezoelectric transformer (PT) and a normally-on MOSFET. Based on a Rosen-type PT and off-the-shelf components, the proposed startup topology begins to oscillate at 12 mV input voltage corresponding to a temperature gradient of 2°C and achieves 1 V output voltage with only 18 mV input voltage applied to the harvester.

Orthogonal fluxgate mechanism operated with dc biased excitation

NASA Astrophysics Data System (ADS)

Sasada, I.

2002-05-01

A mode of operation is presented for an orthogonal fluxgate built with a thin magnetic wire. By adding a proper dc bias to the wire excitation, the new mode is easily established. In this case, the fundamental component of the induced voltage at the sensing coil (secondary voltage) is made sensitive to the axial magnetic field, compared to the second harmonic in a conventional orthogonal fluxgate. The operating principle is explained using a magnetization rotation model. A method is proposed to cancel the offset that is inevitable when the magnetic anisotropy is present in a magnetic wire at an angle to its circumference. Experimental results are shown for a sensor head consisting of a 2-cm-long Co-based amorphous wire 120 μm in diameter with a 220-turn sensing coil. The sensitivity obtained is higher than that obtained using a conventional type of the orthogonal fluxgate built with the same sensor head. It is also demonstrated that the proposed method for canceling the offset works well.

Low Temperature Performance of High Power Density DC/DC Converter Modules

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.; Hammond, Ahmad; Gerber, Scott; Patterson, Richard L.; Overton, Eric

2001-01-01

In this paper, two second-generation high power density DC/DC converter modules have been evaluated at low operating temperatures. The power rating of one converter (Module 1) was specified at 150 W with an input voltage range of 36 to 75 V and output voltage of 12 V. The other converter (Module 2) was specified at 100 W with the same input voltage range and an output voltage of 3.3 V. The converter modules were evaluated in terms of their performance as a function of operating temperature in the range of 25 to -140 C. The experimental procedures along with the experimental data obtained are presented and discussed in this paper.

An in-flight investigation of a twin fuselage configuration in approach and landing

NASA Technical Reports Server (NTRS)

Weingarten, N. C.

1984-01-01

An in-flight investigation of the flying qualities of a twin fuselage aircraft design in the approach and landing flight phase was carried out in the USAF/AFWAL Total In-Flight Simulator (TIFS). The objective was to determine the effects of actual motion and visual cues on the pilot when he was offset from the centerline of the aircraft. The experiment variables were lateral pilot offset position (0, 30 and 50 feet) and effective roll mode time constant (.6, 1.2, 2.4 seconds). The evaluation included the final approach, flare and touchdown. Lateral runway offsets and 15 knot crosswinds were used to increase the pilot's workload and force him to make large lateral corrections in the final portion of the approach. Results indicated that large normal accelerations rather than just vertical displacements in rolling maneuvers had the most significant degrading effect on pilot ratings. The normal accelerations are a result of large lateral offset and fast roll mode time constant and caused the pilot to make unnecessary pitch inputs and get into a coupled pitch/roll oscillation while he was making line up and crosswind corrections. A potential criteria for lateral pilot offset position effects is proposed. When the ratio of incremented normal aceleration at the pilot station to the steady state roll rate for a step input reaches .01 to .02 g/deg/sec a deterioration of pilot rating and flying qualities level can be expected.

Chemically assembled double-dot single-electron transistor analyzed by the orthodox model considering offset charge

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kano, Shinya; Maeda, Kosuke; Majima, Yutaka, E-mail: majima@msl.titech.ac.jp

2015-10-07

We present the analysis of chemically assembled double-dot single-electron transistors using orthodox model considering offset charges. First, we fabricate chemically assembled single-electron transistors (SETs) consisting of two Au nanoparticles between electroless Au-plated nanogap electrodes. Then, extraordinary stable Coulomb diamonds in the double-dot SETs are analyzed using the orthodox model, by considering offset charges on the respective quantum dots. We determine the equivalent circuit parameters from Coulomb diamonds and drain current vs. drain voltage curves of the SETs. The accuracies of the capacitances and offset charges on the quantum dots are within ±10%, and ±0.04e (where e is the elementary charge),more » respectively. The parameters can be explained by the geometrical structures of the SETs observed using scanning electron microscopy images. Using this approach, we are able to understand the spatial characteristics of the double quantum dots, such as the relative distance from the gate electrode and the conditions for adsorption between the nanogap electrodes.« less

Entorhinal stellate cells show preferred spike phase-locking to theta inputs that is enhanced by correlations in synaptic activity

PubMed Central

Fernandez, Fernando R.; Malerba, Paola; Bressloff, Paul C.; White, John A.

2013-01-01

In active networks, excitatory and inhibitory synaptic inputs generate membrane voltage fluctuations that drive spike activity in a probabilistic manner. Despite this, some cells in vivo show a strong propensity to precisely lock to the local field potential and maintain a specific spike-phase relationship relative to other cells. In recordings from rat medial entorhinal cortical stellate cells, we measured spike phase-locking in response to sinusoidal “test” inputs in the presence of different forms of background membrane voltage fluctuations, generated via dynamic clamp. We find that stellate cells show strong and robust spike phase-locking to theta (4–12 Hz) inputs. This response occurs under a wide variety of background membrane voltage fluctuation conditions that include a substantial increase in overall membrane conductance. Furthermore, the IH current present in stellate cells is critical to the enhanced spike phase-locking response at theta. Finally, we show that correlations between inhibitory and excitatory conductance fluctuations, which can arise through feed-back and feed-forward inhibition, can substantially enhance the spike phase-locking response. The enhancement in locking is a result of a selective reduction in the size of low frequency membrane voltage fluctuations due to cancelation of inhibitory and excitatory current fluctuations with correlations. Hence, our results demonstrate that stellate cells have a strong preference for spike phase-locking to theta band inputs and that the absolute magnitude of locking to theta can be modulated by the properties of background membrane voltage fluctuations. PMID:23554484

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

NASA Astrophysics Data System (ADS)

Ikeda, Sho; Lee, Sang-Yeop; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

2015-04-01

In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is -123 dBc/Hz at an output frequency of 5.8 GHz.

A Single-Phase Embedded Z-Source DC-AC Inverter

PubMed Central

Kim, Se-Jin; Lim, Young-Cheol

2014-01-01

In the conventional DC-AC inverter consisting of two DC-DC converters with unipolar output capacitors, the output capacitor voltages of the DC-DC converters must be higher than the DC input voltage. To overcome this weakness, this paper proposes a single-phase DC-AC inverter consisting of two embedded Z-source converters with bipolar output capacitors. The proposed inverter is composed of two embedded Z-source converters with a common DC source and output AC load. Though the output capacitor voltages of the converters are relatively low compared to those of a conventional inverter, an equivalent level of AC output voltages can be obtained. Moreover, by controlling the output capacitor voltages asymmetrically, the AC output voltage of the proposed inverter can be higher than the DC input voltage. To verify the validity of the proposed inverter, experiments were performed with a DC source voltage of 38 V. By controlling the output capacitor voltages of the converters symmetrically or asymmetrically, the proposed inverter can produce sinusoidal AC output voltages. The experiments show that efficiencies of up to 95% and 97% can be achieved with the proposed inverter using symmetric and asymmetric control, respectively. PMID:25133241

A single-phase embedded Z-source DC-AC inverter.

PubMed

Kim, Se-Jin; Lim, Young-Cheol

2014-01-01

In the conventional DC-AC inverter consisting of two DC-DC converters with unipolar output capacitors, the output capacitor voltages of the DC-DC converters must be higher than the DC input voltage. To overcome this weakness, this paper proposes a single-phase DC-AC inverter consisting of two embedded Z-source converters with bipolar output capacitors. The proposed inverter is composed of two embedded Z-source converters with a common DC source and output AC load. Though the output capacitor voltages of the converters are relatively low compared to those of a conventional inverter, an equivalent level of AC output voltages can be obtained. Moreover, by controlling the output capacitor voltages asymmetrically, the AC output voltage of the proposed inverter can be higher than the DC input voltage. To verify the validity of the proposed inverter, experiments were performed with a DC source voltage of 38 V. By controlling the output capacitor voltages of the converters symmetrically or asymmetrically, the proposed inverter can produce sinusoidal AC output voltages. The experiments show that efficiencies of up to 95% and 97% can be achieved with the proposed inverter using symmetric and asymmetric control, respectively.

On the use of an Arduino-based controller to control the charging process of a wind turbine

NASA Astrophysics Data System (ADS)

Mahmuddin, Faisal; Yusran, Ahmad Muhtam; Klara, Syerly

2017-02-01

In order to avoid an excessive charging voltage which can damage power storage when converting wind energy using a turbine, it is necessary to control the charging voltage of the turbine generator. In the present study, a charging controller which uses an Arduino microcontroller, is designed. 3 (three) indicator lights are installed to indicate the battery charging process, power diversion to dummy load and battery power level. The performance of the designed controller is evaluated by simulating 3 cases. In this simulation, a battery with maximum voltage of 12.4 V is used. Case 1 is performed with input voltage equals the one set in Arduino which is 10 V. In this case, the battery is charged up to 10.8 V. In case 2, the input voltage is 13 V while the maximum voltage set in Arduino is also 13 V. In this case, the battery is charged up to maximum voltage of the battery. Moreover, the dummy load indicator is ON and charging indicator is OFF after the maximum charging voltage is reached because the electricity is flowed to the dummy load. In the final case, the input voltage is set to be 16 V while the maximum voltage set in Arduino is 13 V. In this case, the charging indicator is OFF and dummy load indicator is ON which means that the Arduino has successfully switched the power to be flowed to dummy load. From the 3 (three) cases, it can be concluded that the designed controller works perfectly to control the charging process of the wind turbine. Moreover, the charging time needed in each case can also be determined.

RATIO COMPUTER

DOEpatents

Post, R.F.

1958-11-11

An electronic computer circuit is described for producing an output voltage proportional to the product or quotient of tbe voltages of a pair of input signals. ln essence, the disclosed invention provides a computer having two channels adapted to receive separate input signals and each having amplifiers with like fixed amplification factors and like negatlve feedback amplifiers. One of the channels receives a constant signal for comparison purposes, whereby a difference signal is produced to control the amplification factors of the variable feedback amplifiers. The output of the other channel is thereby proportional to the product or quotient of input signals depending upon the relation of input to fixed signals in the first mentioned channel.

Flux trapping in multi-loop SQUIDs and its impact on SQUID-based absolute magnetometry

NASA Astrophysics Data System (ADS)

Schönau, T.; Zakosarenko, V.; Schmelz, M.; Anders, S.; Meyer, H.-G.; Stolz, R.

2018-07-01

The effect of flux trapping on the flux-voltage characteristics of multi-loop SQUID magnetometers was investigated by means of repeated cool-down cycles in a stepwise increased magnetic background field. For a SQUID with N parallel loops, N different flux offsets, each separated by {{{Φ }}}0/N, were observed even in zero magnetic field. These flux offsets further split into a so called fine structure, which can be explained by minor asymmetries in the SQUID design. The observed results are discussed with particular regard to their impact on the previously presented absolute SQUID cascade vector magnetometer.

Dual-Use Transducer for Use with a Boundary-Stiffened Panel and Method of Using the Same

NASA Technical Reports Server (NTRS)

Schiller, Noah H. (Inventor); Cabell, Randolph H. (Inventor)

2011-01-01

A transducer for use with a boundary-stiffened panel has an inter-digitated electrode (IDE) and a piezoelectric wafer portion positioned therebetween. The IDE and/or the wafer portion are triangular, with one edge or side aligned with a boundary edge of the panel. The transducer generates and transmits an output force to the panel in response to an input voltage signal from a sensor, which can be another transducer as described above or an accelerometer. A controller can generate an output force signal in response to the input voltage signal to help cancel the input voltage signal. A method of using the transducer minimizes vibration in the panel by connecting multiple transducers around a perimeter thereof. Motion is measured at different portions of the panel, and a voltage signal determined from the motion is transmitted to the transducers to generate an output force at least partially cancelling or damping the motion.

Electron emission controller with pulsed heating of filament

NASA Astrophysics Data System (ADS)

Durakiewicz, Tomasz

1996-11-01

A novel circuit has been invented for the versatile and safe stabilization of the electron emission current (Ie) produced by a hot filament in mass spectrometers or in ionization gauges. The voltage signal, which is directly proportional to Ie, is provided to the inverting input of a comparator, whereas the noninverting input is connected to the reference voltage. In addition to the commonly used negative feedback loop, a positive feedback loop was introduced by siting a resistor between the noninverting input and the output of the comparator, which results in a pulsation of the filament voltage. The pulses are rectangular, so that the power dissipated by the transistor in the filament power supply circuit is radically reduced. To refine the switching action of the transistor, the output of the comparator is connected through a capacitor to the transistor gate. A concise discussion of the phase shift between Ie, the filament temperature Tf, and the filament voltage Vf, including time constants for different modes of power dissipation, is included.

Electro-optic high voltage sensor

DOEpatents

Davidson, James R.; Seifert, Gary D.

2002-01-01

A small sized electro-optic voltage sensor capable of accurate measurement of high levels of voltages without contact with a conductor or voltage source is provided. When placed in the presence of an electric field, the sensor receives an input beam of electromagnetic radiation into the sensor. A polarization beam displacer serves as a filter to separate the input beam into two beams with orthogonal linear polarizations. The beam displacer is oriented in such a way as to rotate the linearly polarized beams such that they enter a Pockels crystal having at a preferred angle of 45 degrees. The beam displacer is therefore capable of causing a linearly polarized beam to impinge a crystal at a desired angle independent of temperature. The Pockels electro-optic effect induces a differential phase shift on the major and minor axes of the input beam as it travels through the Pockels crystal, which causes the input beam to be elliptically polarized. A reflecting prism redirects the beam back through the crystal and the beam displacer. On the return path, the polarization beam displacer separates the elliptically polarized beam into two output beams of orthogonal linear polarization representing the major and minor axes. The system may include a detector for converting the output beams into electrical signals, and a signal processor for determining the voltage based on an analysis of the output beams. The output beams are amplitude modulated by the frequency of the electric field and the amplitude of the output beams is proportional to the magnitude of the electric field, which is related to the voltage being measured.

Optically-powered Voltage-supply-device for Effective Utilization of Optical Energy in the Fiber-To-The-Home Network

NASA Astrophysics Data System (ADS)

Fukano, Hideki; Shinagawa, Takeshi; Tsuruta, Kenji

An optically powered device with using InGaAs-Photodiode has been developed. This study aims to harvest light energy (2.8∼500μW) from the FTTH (Fiber To The Home) network and to utilize it for operating remote sensors without external energy sources. First, we designed and evaluated the characteristics of the booster circuit and confirmed that it could boost an input voltage of 0.3 V to 3.0 V. Next, we also evaluated the characteristics of InGaAs photodiode and confirmed that it can output a voltage over 0.3 V at 10-μW input light. We demonstrate that a ready-made sensor can be operated with an input optical power as low as 10 μW.

ZERO SUPPRESSION FOR RECORDERS

DOEpatents

Fort, W.G.S.

1958-12-30

A zero-suppression circuit for self-balancing recorder instruments is presented. The essential elements of the circuit include a converter-amplifier having two inputs, one for a reference voltage and the other for the signal voltage under analysis, and a servomotor with two control windings, one coupled to the a-c output of the converter-amplifier and the other receiving a reference input. Each input circuit to the converter-amplifier has a variable potentiometer and the sliders of the potentiometer are ganged together for movement by the servoinotor. The particular noveity of the circuit resides in the selection of resistance values for the potentiometer and a resistor in series with the potentiometer of the signal circuit to ensure the full value of signal voltage variation is impressed on a recorder mechanism driven by servomotor.

A Binary Offset Effect in CCD Readout and Its Impact on Astronomical Data

NASA Astrophysics Data System (ADS)

Boone, K.; Aldering, G.; Copin, Y.; Dixon, S.; Domagalski, R. S.; Gangler, E.; Pecontal, E.; Perlmutter, S.

2018-06-01

We have discovered an anomalous behavior of CCD readout electronics that affects their use in many astronomical applications. An offset in the digitization of the CCD output voltage that depends on the binary encoding of one pixel is added to pixels that are read out one, two, and/or three pixels later. One result of this effect is the introduction of a differential offset in the background when comparing regions with and without flux from science targets. Conventional data reduction methods do not correct for this offset. We find this effect in 16 of 22 instruments investigated, covering a variety of telescopes and many different front-end electronics systems. The affected instruments include LRIS and DEIMOS on the Keck telescopes, WFC3 UVIS and STIS on HST, MegaCam on CFHT, SNIFS on the UH88 telescope, GMOS on the Gemini telescopes, HSC on Subaru, and FORS on VLT. The amplitude of the introduced offset is up to 4.5 ADU per pixel, and it is not directly proportional to the measured ADU level. We have developed a model that can be used to detect this “binary offset effect” in data, and correct for it. Understanding how data are affected and applying a correction for the effect is essential for precise astronomical measurements.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Ways to suppress click and pop for class D amplifiers

NASA Astrophysics Data System (ADS)

Haishi, Wang; Bo, Zhang; Jiang, Sun

2012-08-01

Undesirable audio click and pop may be generated in a speaker or headphone. Compared to linear (class A/B/AB) amplifiers, class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop. This article analyzes sources that generate click and pop in class D amplifiers, and corresponding ways to suppress them. For a class D amplifier with a single-ended input, click and pop is likely to be due to two factors. One is from a voltage difference (VDIF) between the voltage of an input capacitance (VCIN) and a reference voltage (VREF) of the input stage, and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage. In this article, a fast charging loop is introduced into the input stage to charge VCIN to roughly near VREF. Then a correction loop further charges or discharges VCIN, substantially equalizing it with VREF. Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC, and the power switches are disabled until the BFVC are set up successfully. A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process. Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.

OFFSET - RAY TRACING OPTICAL ANALYSIS OF OFFSET SOLAR COLLECTOR FOR SPACE STATION SOLAR DYNAMIC POWER SYSTEM

NASA Technical Reports Server (NTRS)

Jefferies, K.

1994-01-01

OFFSET is a ray tracing computer code for optical analysis of a solar collector. The code models the flux distributions within the receiver cavity produced by reflections from the solar collector. It was developed to model the offset solar collector of the solar dynamic electric power system being developed for Space Station Freedom. OFFSET has been used to improve the understanding of the collector-receiver interface and to guide the efforts of NASA contractors also researching the optical components of the power system. The collector for Space Station Freedom consists of 19 hexagonal panels each containing 24 triangular, reflective facets. Current research is geared toward optimizing flux distribution inside the receiver via changes in collector design and receiver orientation. OFFSET offers many options for experimenting with the design of the system. The offset parabolic collector model configuration is determined by an input file of facet corner coordinates. The user may choose other configurations by changing this file, but to simulate collectors that have other than 19 groups of 24 triangular facets would require modification of the FORTRAN code. Each of the roughly 500 facets in the assembled collector may be independently aimed to smooth out, or tailor, the flux distribution on the receiver's wall. OFFSET simulates the effects of design changes such as in receiver aperture location, tilt angle, and collector facet contour. Unique features of OFFSET include: 1) equations developed to pseudo-randomly select ray originating sources on the Sun which appear evenly distributed and include solar limb darkening; 2) Cone-optics technique used to add surface specular error to the ray originating sources to determine the apparent ray sources of the reflected sun; 3) choice of facet reflective surface contour -- spherical, ideal parabolic, or toroidal; 4) Gaussian distributions of radial and tangential components of surface slope error added to the surface normals at the ten nodal points on each facet; and 5) color contour plots of receiver incident flux distribution generated by PATRAN processing of FORTRAN computer code output. OFFSET output includes a file of input data for confirmation, a PATRAN results file containing the values necessary to plot the flux distribution at the receiver surface, a PATRAN results file containing the intensity distribution on a 40 x 40 cm area of the receiver aperture plane, a data file containing calculated information on the system configuration, a file including the X-Y coordinates of the target points of each collector facet on the aperture opening, and twelve P/PLOT input data files to allow X-Y plotting of various results data. OFFSET is written in FORTRAN (70%) for the IBM VM operating system. The code contains PATRAN statements (12%) and P/PLOT statements (18%) for generating plots. Once the program has been run on VM (or an equivalent system), the PATRAN and P/PLOT files may be transferred to a DEC VAX (or equivalent system) with access to PATRAN for PATRAN post processing. OFFSET was written in 1988 and last updated in 1989. PATRAN is a registered trademark of PDA Engineering. IBM is a registered trademark of International Business Machines Corporation. DEC VAX is a registered trademark of Digital Equipment Corporation.

Phase-locked loop design with fast-digital-calibration charge pump

NASA Astrophysics Data System (ADS)

Wang, San-Fu; Hwang, Tsuen-Shiau; Wang, Jhen-Ji

2016-02-01

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27-2.88 GHz frequency synthesiser fabricated in TSMC 0.18 μm CMOS 1.8 V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6 V. The proposed PLL has a total power consumption of 22.57 mW and a settling time of 10 μs or less.

A Microwave Tunable Bandpass Filter for Liquid Crystal Applications

NASA Astrophysics Data System (ADS)

Cao, Weiping; Jiang, Di; Liu, Yupeng; Yang, Yuanwang; Gan, Baichuan

2017-07-01

In this paper, a novel microwave continuously tunable band-pass filter, based on nematic liquid crystals (LCs), is proposed. It uses liquid crystal (LC) as the electro-optic material to mainly realize frequency shift at microwave band by changing the dielectric anisotropy, when applying the bias voltage. According to simulation results, it achieves 840 MHz offset. Comparing to the existing tunable filter, it has many advantages, such as continuously tunable, miniaturization, low processing costs, low tuning voltage, etc. Thus, it has shown great potentials in frequency domain and practical applications in modern communication.

Effect of solar-cell junction geometry on open-circuit voltage

NASA Technical Reports Server (NTRS)

Weizer, V. G.; Godlewski, M. P.

1985-01-01

Simple analytical models have been found that adequately describe the voltage behavior of both the stripe junction and dot junction grating cells as a function of junction area. While the voltage in the former case is found to be insensitive to junction area reduction, significant voltage increases are shown to be possible for the dot junction cell. With regard to cells in which the junction area has been increased in a quest for better performance, it was found that (1) texturation does not affect the average saturation current density J0, indicating that the texturation process is equivalent to a simple extension of junction area by a factor of square root of 3 and (2) the vertical junction cell geometry produces a sizable decrease in J0 that, unfortunately, is more than offset by the effects of attendant areal increases.

Design of shape memory alloy actuated intelligent parabolic antenna for space applications

NASA Astrophysics Data System (ADS)

Kalra, Sahil; Bhattacharya, Bishakh; Munjal, B. S.

2017-09-01

The deployment of large flexible antennas is becoming critical for space applications today. Such antenna systems can be reconfigured in space for variable antenna footprint, and hence can be utilized for signal transmission to different geographic locations. Due to quasi-static shape change requirements, coupled with the demand of large deflection, shape memory alloy (SMA) based actuators are uniquely suitable for this system. In this paper, we discuss the design and development of a reconfigurable parabolic antenna structure. The reflector skin of the antenna is vacuum formed using a metalized polycarbonate shell. Two different strategies are chosen for the antenna actuation. Initially, an SMA wire based offset network is formed on the back side of the reflector. A computational model is developed using equivalent coefficient of thermal expansion (ECTE) for the SMA wire. Subsequently, the interaction between the antenna and SMA wire is modeled as a constrained recovery system, using a 1D modified Brinson model. Joule effect based SMA phase transformation is considered for the relationship between input voltage and temperature at the SMA wire. The antenna is modeled using ABAQUS based finite element methodology. The deflection found through the computational model is compared with that measured in experiment. Subsequently, a point-wise actuation system is developed for higher deflection. For power-minimization, an auto-locking device is developed. The performance of the new configuration is compared with the offset-network configuration. It is envisaged that the study will provide a comprehensive procedure for the design of intelligent flexible structures especially suitable for space applications.

Power characteristics in GMAW: Experimental and numerical investigation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Joensson, P.G.; Szekely, J.; Madigan, R.B.

1995-03-01

The voltage and power distributions in gas metal arc welding (GMAW) were studied both experimentally and numerically. The principal voltage drop takes place in the arc, which also constitutes the dominant power contribution. Within the arc, the dominating voltage contributions are from the arc column and the cathode fall, while the anode fall and the electrode regions are less significant. The power input to the arc column increases with both increasing current and increasing arc length. These results indicate that it is critical to control the arc length in order to control the power input to the system.

Directly induced swing for closed loop control of electroslag remelting furnace

DOEpatents

Damkroger, Brian

1998-01-01

An apparatus and method for controlling an electroslag remelting furnace, imposing a periodic fluctuation on electrode drive speed and thereby generating a predictable voltage swing signal. The fluctuation is preferably done by imposition of a sine, square, or sawtooth wave on the drive dc offset signal.

Influence of voltage input to heavy metal removal from electroplating wastewater using electrocoagulation process

NASA Astrophysics Data System (ADS)

Wulan, D. R.; Cahyaningsih, S.; Djaenudin

2017-03-01

In medium capacity, electroplating industry usually treats wastewater until 5 m3 per day. Heavy metal content becomes concern that should be reduced. Previous studies performed electrocoagulation method on laboratory scale, either batch or continuous. This study was aimed to compare the influence of voltage input variation into heavy metal removal in electroplating wastewater treatment using electrocoagulation process on laboratory-scale in order to determine the optimum condition for scaling up the reactor into pilot-scale. The laboratory study was performed in 1.5 L glass reactor in batch system using wastewater from electroplating industry, the voltage input varied at 20, 30 and 40 volt. The electrode consisted of aluminium 32 cm2 as sacrifice anode and copper 32 cm2 as cathode. During 120 min electrocoagulation process, the pH value was measured using pH meter, whereas the heavy metal of chromium, copper, iron, and zinc concentration were analysed using Atomic Absorption Spectrophotometer (AAS). Result showed that removal of heavy metals from wastewater increased due to the increasing of voltage input. Different initial concentration of heavy metals on wastewater, resulted the different detention time. At pilot-scale reactor with 30 V voltage input, chromium, iron, and zinc reached removal efficiency until 89-98%, when copper reached 79% efficiency. At 40V, removal efficiencies increased on same detention time, i.e. chromium, iron, and zinc reached 89-99%, whereas copper reached 85%. These removal efficiencies have complied the government standard except for copper that had higher initial concentration in wastewater. Kinetic rate also calculated in this study as the basic factor for scaling up the process.

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

NASA Astrophysics Data System (ADS)

Zubrzycka, W.; Kasinski, K.

2018-04-01

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier feedback resistor independent of the leakage current level and polarity. The simulation results of the double, switchable, Krummenacher circuit-based feedback application in the CSA with a pulsed reset functionality are presented.

47 CFR 80.959 - Radiotelephone transmitter.

Code of Federal Regulations, 2010 CFR

2010-10-01

... watts into 50 ohms nominal resistance when operated with its rated supply voltage. The transmitter must... capability of the transmitter, measurements of primary supply voltage and transmitter output power must be... voltage measured at the power input terminals to the transmitter terminated in a matching artificial load...

MOSFET analog memory circuit achieves long duration signal storage

NASA Technical Reports Server (NTRS)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

High static gain single-phase PFC based on a hybrid boost converter

NASA Astrophysics Data System (ADS)

Flores Cortez, Daniel; Maccarini, Marcello C.; Mussa, Samir A.; Barbi, Ivo

2017-05-01

In this paper, a single-phase unity power factor rectifier, based on a hybrid boost converter, resulting from the integration of a conventional dc-dc boost converter and a switched-capacitor voltage doubler is proposed, analysed, designed and tested. The high-power rectifier is controlled by two feedback loops with the same control strategy employed in the conventional boost-based rectifier. The main feature of the proposed rectifier is its ability to output a dc voltage larger than the double of the peak value of the input line voltage, while subjecting the power switches to half of the dc-link voltage, which contributes to reducing the cost and increasing the efficiency. Experimental data were obtained from a laboratory prototype with an input voltage of 220 Vrms, line frequency of 60 Hz, output voltage of 800 Vdc, load power of 1000 W and switching frequency of 50 kHz. The efficiency of the prototype, measured in the laboratory, was 96.5% for full load and 97% for half load.

Membrane voltage changes in passive dendritic trees: a tapering equivalent cylinder model.

PubMed

Poznański, R R

1988-01-01

An exponentially tapering equivalent cylinder model is employed in order to approximate the loss of the dendritic trunk parameter observed from anatomical data on apical and basilar dendrites of CA1 and CA3 hippocampal pyramidal neurons. This model allows dendritic trees with a relative paucity of branching to be treated. In particular, terminal branches are not required to end at the same electrotonic distance. The Laplace transform method is used to obtain analytic expressions for the Green's function corresponding to an instantaneous pulse of current injected at a single point along a tapering equivalent cylinder with sealed ends. The time course of the voltage in response to an arbitrary input is computed using the Green's function in a convolution integral. Examples of current input considered are (1) an infinitesimally brief (Dirac delta function) pulse and (2) a step pulse. It is demonstrated that inputs located on a tapering equivalent cylinder are more effective at the soma than identically placed inputs on a nontapering equivalent cylinder. Asymptotic solutions are derived to enable the voltage response behaviour over both relatively short and long time periods to be analysed. Semilogarithmic plots of these solutions provide a basis for estimating the membrane time constant tau m from experimental transients. Transient voltage decrement from a clamped soma reveals that tapering tends to reduce the error associated with inadequate voltage clamping of the dendritic membrane. A formula is derived which shows that tapering tends to increase the estimate of the electrotonic length parameter L.

Electro-optic high voltage sensor

DOEpatents

Davidson, James R.; Seifert, Gary D.

2003-09-16

A small sized electro-optic voltage sensor capable of accurate measurement of high voltages without contact with a conductor or voltage source is provided. When placed in the presence of an electric field, the sensor receives an input beam of electromagnetic radiation. A polarization beam displacer separates the input beam into two beams with orthogonal linear polarizations and causes one linearly polarized beam to impinge a crystal at a desired angle independent of temperature. The Pockels effect elliptically polarizes the beam as it travels through the crystal. A reflector redirects the beam back through the crystal and the beam displacer. On the return path, the polarization beam displacer separates the elliptically polarized beam into two output beams of orthogonal linear polarization. The system may include a detector for converting the output beams into electrical signals and a signal processor for determining the voltage based on an analysis of the output beams.

47 CFR 73.51 - Determining operating power.

Code of Federal Regulations, 2011 CFR

2011-10-01

... stage of the transmitter, using the following formula: Where: Antenna input power = Ep × Ip × F Ep=DC input voltage of final radio stage. Ip=Total DC input current of final radio stage. F= Efficiency factor...

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

PubMed Central

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

2017-01-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

PubMed

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

2017-08-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Automatic NMR field-frequency lock-pulsed phase locked loop approach.

PubMed

Kan, S; Gonord, P; Fan, M; Sauzade, M; Courtieu, J

1978-06-01

A self-contained deuterium frequency-field lock scheme for a high-resolution NMR spectrometer is described. It is based on phase locked loop techniques in which the free induction decay signal behaves as a voltage-controlled oscillator. By pulsing the spins at an offset frequency of a few hundred hertz and using a digital phase-frequency discriminator this method not only eliminates the usual phase, rf power, offset adjustments needed in conventional lock systems but also possesses the automatic pull-in characteristics that dispense with the use of field sweeps to locate the NMR line prior to closure of the lock loop.

In-flight calibration of the spin axis offset of a fluxgate magnetometer with an electron drift instrument

NASA Astrophysics Data System (ADS)

Leinweber, H. K.; Russell, C. T.; Torkar, K.

2012-10-01

We show that the spin axis offset of a fluxgate magnetometer can be calibrated with an electron drift instrument (EDI) and that the required input time interval is relatively short. For missions such as Cluster or the upcoming Magnetospheric Multiscale (MMS) mission the spin axis offset of a fluxgate magnetometer could be determined on an orbital basis. An improvement of existing methods for finding spin axis offsets via comparison of accurate measurements of the field magnitude is presented, that additionally matches the gains of the two instruments that are being compared. The technique has been applied to EDI data from the Cluster Active Archive and fluxgate magnetometer data processed with calibration files also from the Cluster Active Archive. The method could prove to be valuable for the MMS mission because the four MMS spacecraft will only be inside the interplanetary field (where spin axis offsets can be calculated from Alfvénic fluctuations) for short periods of time and during unusual solar wind conditions.

A low-voltage fully balanced CMFF transconductor with improved linearity

NASA Astrophysics Data System (ADS)

Calvo, B.; Celma, S.; Alegre, J. P.; Sanz, M. T.

2007-05-01

This paper presents a new low-voltage pseudo-differential continuous-time CMOS transconductor for wideband applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Simulation results for a 0.35 μm CMOS design show a 1:2 G m tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 200 μA p-p differential output. The proposed cell consumes less than 1.2 mW from a single 2.0 V supply.

Phase detector for three-phase power factor controller

NASA Technical Reports Server (NTRS)

Nola, F. J. (Inventor)

1984-01-01

A phase detector for the three phase power factor controller (PFC) is described. The phase detector for each phase includes an operational amplifier which senses the current phase angle for that phase by sensing the voltage across the phase thyristor. Common mode rejection is achieved by providing positive feedback between the input and output of the voltage sensing operational amplifier. this feedback preferably comprises a resistor connected between the output and input of the operational amplifier. The novelty of the invention resides in providing positive feedback such that switching of the operational amplifier is synchronized with switching of the voltage across the thyristor. The invention provides a solution to problems associated with high common mode voltage and enables use of lower cost components than would be required by other approaches.

A digital prediction algorithm for a single-phase boost PFC

NASA Astrophysics Data System (ADS)

Qing, Wang; Ning, Chen; Weifeng, Sun; Shengli, Lu; Longxing, Shi

2012-12-01

A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF (power factor) with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The startup and the recovery times respectively are about 0.1 s and 0.02 s without overshoot. The experimental results also verify the validity of the proposed method.

A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

PubMed

Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

2012-01-01

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

Offset Compound Gear Inline Two-Speed Drive

NASA Technical Reports Server (NTRS)

Stevens, Mark A. (Inventor); Handschuh, Robert F. (Inventor); Lewicki, David G. (Inventor)

2012-01-01

A two-speed transmission having an input shaft and an output shaft, the transmission being capable of transitioning between fixed ratios, the high-range ratio being direct 1:1 and the low-range ratio being about 2:1. The transmission is a simple lightweight, yet robust, configuration utilizing only two gear meshes, being comprised of an input gear, a cluster gear, and an output gear. The transmission is controlled with a clutch and a sprag and with the input and output shafts turning in the same direction.

Offset Compound Gear Inline Two-Speed Drive

NASA Technical Reports Server (NTRS)

Stevens, Mark A. (Inventor); Handschuh, Robert F. (Inventor); Lewicki, David G. (Inventor)

2014-01-01

A two-speed transmission having an input shaft and an output shaft, the transmission being capable of transitioning between fixed ratios, the high-range ratio being direct 1:1 and the low-range ratio being about 2:1. The transmission is a simple lightweight, yet robust, configuration utilizing only two gear meshes, being comprised of an input gear, a cluster gear, and an output gear. The transmission is controlled with a clutch and a sprag and with the input and output shafts turning in the same direction.

Single flux quantum voltage amplifiers

NASA Astrophysics Data System (ADS)

Golomidov, Vladimir; Kaplunenko, Vsevolod; Khabipov, Marat; Koshelets, Valery; Kaplunenko, Olga

The novel elements of the Rapid Single Flux Quantum (RSFQ) logic family — a Quasi Digital Voltage Parallel and Series Amplifiers (QDVA) have been computer simulated, designed and experimentally investigated. The Parallel QDVA consists of six stages and provides multiplication of the input voltage with factor five. The output resistance of the QDVA is five times larger than the input so this amplifier seems to be a good matching stage between RSFQL and usual semiconductor electronics. The series QDVA provides a gain factor four and involves two doublers connected by transmission line. The proposed parallel QDVA can be integrated on the same chip with a SQUID sensor.

Single Event Burnout in DC-DC Converters for the LHC Experiments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Claudio H. Rivetta et al.

High voltage transistors in DC-DC converters are prone to catastrophic Single Event Burnout in the LHC radiation environment. This paper presents a systematic methodology to analyze single event effects sensitivity in converters and proposes solutions based on de-rating input voltage and output current or voltage.

75 FR 16957 - Energy Conservation Program: Test Procedures for Battery Chargers and External Power Supplies

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-02

... Procedures C. Review of Single-Voltage External Power Supply Test Procedure D. Multiple-Voltage External...) Deletions of Existing Definitions (b) Revisions to Existing Definitions (c) Additions of New Definitions 4. Test Apparatus and General Instructions (a) Confidence Intervals (b) Temperature (c) AC Input Voltage...

Setups for in vitro assessment of RFID interference on pacemakers

NASA Astrophysics Data System (ADS)

Mattei, E.; Censi, F.; Delogu, A.; Ferrara, A.; Calcagnini, G.

2013-08-01

The aim of this study is to propose setups for in vitro assessment of RFID (radiofrequency identification) interference on pacemakers (PM). The voltage induced at the input stage of the PM by low-frequency (LF) and high-frequency (HF) RFID transmitters has been used to quantify the amount of the interference. A commercial PM was modified in order to measure the voltage at its input stage when exposed to a sinusoidal signal at 125 kHz and 13.56 MHz. At both frequencies, two antennas with different dimensions (diameter = 10 cm and 30 cm, respectively) were used to generate the interfering field, and the induced voltage was measured between the lead tip and the PM case (unipolar voltage), and between the tip and ring electrodes (bipolar voltage). The typical lead configurations adopted in similar studies or proposed by international standards, as well as lead paths closer to actual physiological implants were tested. At 125 kHz, the worst-case condition differs for the two antennas: the 10 cm antenna induced the highest voltage in the two-loop spiral configuration, whereas the 30 cm antenna in the 225 cm2 loop configuration. At 13.56 MHz, the highest voltage was observed for both the antennas in the 225 cm2 loop configuration. Bipolar voltages were found to be lower than the unipolar voltages induced in the same configurations, this difference being not as high as one could expect from theoretical considerations. The worst-case scenario, in terms of the induced voltage at the PM input stage, has been identified both for LF and HF readers, and for two sizes of transmitting antennas. These findings may provide the basis for the definition of a standard implant configuration and a lead path to test the EMI effects of LF and HF RFID transmitters on active implantable devices.

Directly induced swing for closed loop control of electroslag remelting furnace

DOEpatents

Damkroger, B.

1998-04-07

An apparatus and method are disclosed for controlling an electroslag remelting furnace, imposing a periodic fluctuation on electrode drive speed and thereby generating a predictable voltage swing signal. The fluctuation is preferably done by imposition of a sine, square, or sawtooth wave on the drive dc offset signal. 8 figs.

An In-Rush Current Suppression Technique for the Solid-State Transfer Switch System

NASA Astrophysics Data System (ADS)

Cheng, Po-Tai; Chen, Yu-Hsing

More and more utility companies provide dual power feeders as a premier service of high power quality and reliability. To take advantage of this, the solid-state transfer switch (STS) is adopted to protect the sensitive load against the voltage sag. However, the fast transfer process may cause in-rush current on the load-side transformer due to the resulting DC-offset in its magnetic flux as the load-transfer is completed. The in-rush current can reach 2∼6 p.u. and it may trigger the over-current protections on the power feeder. This paper develops a flux estimation scheme and a thyristor gating scheme based on the impulse commutation bridge STS (ICBSTS) to minimize the DC-offset on the magnetic flux. By sensing the line voltages of both feeders, the flux estimator can predict the peak transient flux linkage at the moment of load-transfer and evaluate a suitable moment for the transfer to minimize the in-rush current. Laboratory test results are presented to validate the performance of the proposed system.

Programmable differential capacitance-to-voltage converter for MEMS accelerometers

NASA Astrophysics Data System (ADS)

Royo, G.; Sánchez-Azqueta, C.; Gimeno, C.; Aldea, C.; Celma, S.

2017-05-01

Capacitive MEMS sensors exhibit an excellent noise performance, high sensitivity and low power consumption. They offer a huge range of applications, being the accelerometer one of its main uses. In this work, we present the design of a capacitance-to-voltage converter in CMOS technology to measure the acceleration from the capacitance variations. It is based on a low-power, fully-differential transimpedance amplifier with low input impedance and a very low input noise.

Analysis performance of proton exchange membrane fuel cell (PEMFC)

NASA Astrophysics Data System (ADS)

Mubin, A. N. A.; Bahrom, M. H.; Azri, M.; Ibrahim, Z.; Rahim, N. A.; Raihan, S. R. S.

2017-06-01

Recently, the proton exchange membrane fuel cell (PEMFC) has gained much attention to the technology of renewable energy due to its mechanically ideal and zero emission power source. PEMFC performance reflects from the surroundings such as temperature and pressure. This paper presents an analysis of the performance of the PEMFC by developing the mathematical thermodynamic modelling using Matlab/Simulink. Apart from that, the differential equation of the thermodynamic model of the PEMFC is used to explain the contribution of heat to the performance of the output voltage of the PEMFC. On the other hand, the partial pressure equation of the hydrogen is included in the PEMFC mathematical modeling to study the PEMFC voltage behaviour related to the input variable input hydrogen pressure. The efficiency of the model is 33.8% which calculated by applying the energy conversion device equations on the thermal efficiency. PEMFC’s voltage output performance is increased by increasing the hydrogen input pressure and temperature.

Design and dSpace interfacing of current fed high gain dc to dc boost converter for low voltage applications

NASA Astrophysics Data System (ADS)

Mukhopadhyay, Debraj; Das, Subhrajit; Arunkumar, G.; Elangovan, D.; Ragunath, G.

2017-11-01

In this paper a current fed interleaved DC - DC boost converter which has an isolated topology and used for high voltage step up is proposed. A basic DC to DC boost converter converts uncontrolled DC voltage into controlled DC voltage of higher magnitude. Whereas this topology has the advantages of lower input current ripple, lesser output voltage, lesser stress on switches, faster transient response, improved reliability and much lesser electromagnetic emission over the conventional DC to DC boost converter. Most important benefit of this interleaved DC to DC boost converter is much higher efficiency. The input current is divided into two paths, substantially ohmic loss (I2R) and inductor ac loss gets reduced and finally the system achieves much higher efficiency. With recent mandates on energy saving interleaved DC to DC boost converter may be used as a very powerful tool to maintain good power density keeping the input current manageable. Higher efficiency also allows higher switching frequency and as a result the topology becomes more compact and cost friendly. The proposed topology boosts 48v DC to 200 V DC. Switching frequency is 100 kHz and PSIM 9.1 Platform has been used for the simulation.

ELECTRONIC MULTIPLIER

DOEpatents

Collier, D.M.; Meeks, L.A.; Palmer, J.P.

1961-01-31

S>An electronic multiplier is described for use in analog computers. Two electrical input signals are received; one controls the slope of a saw-tooth voltage wave while the other controls the time duration of the wave. A condenser and diode clamps are provided to sustain the crest voltage reached by the wave, and for storing that voltage to provide an output signal which is a steady d-c voltage.

Potential for ag residue collection, economics and environmental benefits

NASA Astrophysics Data System (ADS)

Hettenhaus, J. R.

2003-12-01

Removing excess corn stover and cereal straws after erosion requirements have been satisfied offers much potential as a renewable feedstock for initial biorefineries, producing fuels, chemicals and materials while reducing crop inputs, increasing farm income and offsetting greenhouse gas emissions. Two biorefinery site studies are presented for the production of fuel ethanol: SW Nebraska and Western Oklahoma. Results include excess available, delivered cost, net income to the farmer, improved SOM from move to no-till and GHG reduction from fossil fuel offset

Sequencing and fan-out mechanism for causing a set of at least two sequential instructions to be performed in a dataflow processing computer

DOEpatents

Grafe, Victor G.; Hoch, James E.

1993-01-01

A sequencing and data fanout mechanism is provided for a dataflow processor is activated by an input token which causes a sequence of operations to occur by initiating a first instruction to act on data contained within the token and then executing a sequential thread of instructions identified by either a repeat count and an offset within the token, or by an offset within each preceding instruction.

Self-Calibration Approach for Mixed Signal Circuits in Systems-on-Chip

NASA Astrophysics Data System (ADS)

Jung, In-Seok

MOSFET scaling has served industry very well for a few decades by proving improvements in transistor performance, power, and cost. However, they require high test complexity and cost due to several issues such as limited pin count and integration of analog and digital mixed circuits. Therefore, self-calibration is an excellent and promising method to improve yield and to reduce manufacturing cost by simplifying the test complexity, because it is possible to address the process variation effects by means of self-calibration technique. Since the prior published calibration techniques were developed for a specific targeted application, it is not easy to be utilized for other applications. In order to solve the aforementioned issues, in this dissertation, several novel self-calibration design techniques in mixed-signal mode circuits are proposed for an analog to digital converter (ADC) to reduce mismatch error and improve performance. These are essential components in SOCs and the proposed self-calibration approach also compensates the process variations. The proposed novel self-calibration approach targets the successive approximation (SA) ADC. First of all, the offset error of the comparator in the SA-ADC is reduced using the proposed approach by enabling the capacitor array in the input nodes for better matching. In addition, the auxiliary capacitors for each capacitor of DAC in the SA-ADC are controlled by using synthesized digital controller to minimize the mismatch error of the DAC. Since the proposed technique is applied during foreground operation, the power overhead in SA-ADC case is minimal because the calibration circuit is deactivated during normal operation time. Another benefit of the proposed technique is that the offset voltage of the comparator is continuously adjusted for every step to decide one-bit code, because not only the inherit offset voltage of the comparator but also the mismatch of DAC are compensated simultaneously. Synthesized digital calibration control circuit operates as fore-ground mode, and the controller has been highly optimized for low power and better performance with simplified structure. In addition, in order to increase the sampling clock frequency of proposed self-calibration approach, novel variable clock period method is proposed. To achieve high speed SAR operation, a variable clock time technique is used to reduce not only peak current but also die area. The technique removes conversion time waste and extends the SAR operation speed easily. To verify and demonstrate the proposed techniques, a prototype charge-redistribution SA-ADCs with the proposed self-calibration is implemented in a 130nm standard CMOS process. The prototype circuit's silicon area is 0.0715 mm 2 and consumers 4.62mW with 1.2V power supply.

Method and Apparatus for Improving the Resolution of Digitally Sampled Analog Data

NASA Technical Reports Server (NTRS)

Liaghati, Amir L. (Inventor)

2017-01-01

A system and method is described for converting an analog signal into a digital signal. The gain and offset of an ADC is dynamically adjusted so that the N-bits of input data are assigned to a narrower channel instead of the entire input range of the ADC. This provides greater resolution in the range of interest without generating longer digital data strings.

Pre-electrospray ionisation manifold methylation and post-electrospray ionisation manifold cleavage/ion cluster formation observed during electrospray ionisation of chloramphenicol in solutions of methanol and acetonitrile for liquid chromatography-mass spectrometry employing a commercial quadrupole ion trap mass analyser.

PubMed

Sichilongo, Kwenga F; Famuyiwa, Samson O; Kibechu, Rose

2011-01-01

We have observed unusual mass spectra of chloramphenicol (CAP) in solutions of methanol or acetonitrile showing intense ions at m/z 297, m/z 311, m/z 325 and m/z 339. The observed ions were different from those which are traditionally observed in the full scan ESI mass spectra of CAP with ions of m/z 321, m/z 323 and m/z 325. We have evidence to show that this process starts with offline methylation of CAP in solutions of methanol or acetonitrile to give m/z 339. Investigations using nuclear magnetic resonance (NMR) spectroscopy showed that there is a methylene group somewhere within the CAP molecule but not attached to any of the carbon atoms when the CAP is dissolved in methanol or acetonitrile before infusion into the mass spectrometer. The possible locations of attachment were speculated to be the electronegative atoms apart from the chlorine atoms due to valence considerations. The methylene group is attached to the nitrogen atom and forms a bond as observed in the MS/MS spectra of m/z 297, m/z 311, m/z 325 and m/z 339 which give m/z 183 as the base peak in all cases. Further experiments showed that there is cleavage of the methylated CAP molecule followed by cluster ion formation involving addition of methylene groups to the CAP fragment with m/z 183 to produce ions of m/z including m/z 297, m/z 311, m/z 325 and m/z 339. This process occurs in the mass spectrometer in the region housing the tube lens and is triggered when the ions are accelerated through this region by application of a negative tube lens offset voltage. This region affords collision of the charged droplets with a collision gas in this case nitrogen to strip the droplets of their solvent molecules. Experiments to follow the intensities of m/z 183, m/z 311, m/z 321, m/z 323, m/z 325 and m/z 339 as the tube lens offset voltage was varied were done in which the intensities of m/z 311, m/z 325 and m/z 339 were observed to be at their peak when the tube lens offset voltage was set at -40 V. When the tube lens offset voltage is swung to +40 V, thus decelerating the ions through the capillary skimmer region via the tube lens, the traditionally observed spectra with m/z 321, m/z 323 and m/z 325 were observed.

Two-electrode non-differential biopotential amplifier.

PubMed

Dobrev, D

2002-09-01

A circuit is proposed for a non-differential two-electrode biopotential amplifier, with a current source and a transimpedance amplifier as a potential equaliser for its inputs, fully emulating a differential amplifier. The principle of operation is that the current in the input of the transimpedance amplifier is sensed and made to flow with the same value in the other input. The circuit has a simple structure and uses a small number of components. The current source maintains balanced common-mode interference currents, thus ensuring high signal input impedance. In addition, these currents can be tolerated up to more than 10 microA per input, at a supply voltage of +/- 5 V. A two-electrode differential amplifier with 2 x 10 Mohm input resistances to the reference point allows less than 0.5 microA per input. The circuit can be useful in cases of biosignal acquisition by portable instruments, using low supply voltages, from subjects in areas of high electromagnetic fields. Examples include biosignal recordings in electric power stations and electrically powered locomotives, where traditionally designed input amplifier stages can be saturated.

Annealing effects on hydrogenated diamond NOR logic circuits

NASA Astrophysics Data System (ADS)

Liu, J. W.; Oosato, H.; Liao, M. Y.; Imura, M.; Watanabe, E.; Koide, Y.

2018-04-01

Here, hydrogenated diamond (H-diamond) NOR logic circuits composed of two p-type enhancement-mode (E-mode) metal-oxide-semiconductor field-effect-transistors (MOSFETs) and a load resistor are fabricated and characterized. The fabrication process and the annealing effect on the electrical properties of the NOR logic circuit are demonstrated. There are distinct logical characteristics for the as-received and 300 °C annealed NOR logic circuits. When one or both input voltages for the E-mode MOSFETs are -10.0 V and "high" signals, output voltages respond 0 V and "low" signals. Instead, when both input voltages are 0 V and "low" signals, output voltage responds -10.0 V and a "high" signal. After annealing at 400 °C, the NOR logical characteristics are damaged, which is possibly attributed to the degradation of the H-diamond MOSFETs.

Direct current ballast circuit for metal halide lamp

NASA Technical Reports Server (NTRS)

Lutus, P. (Inventor)

1981-01-01

A direct current ballast circuit for a two electrode metal halide lamp is described. Said direct current ballast circuit includes a low voltage DC input and a high frequency power amplifier and power transformer for developing a high voltage output. The output voltage is rectified by diodes and filtered by inductor and capacitor to provide a regulated DC output through commutating diodes to one terminal of the lamp at the output terminal. A feedback path from the output of the filter capacitor through the bias resistor to power the high frequency circuit which includes the power amplifier and the power transformer for sustaining circuit operations during low voltage transients on the input DC supply is described. A current sensor connected to the output of the lamp through terminal for stabilizing lamp current following breakdown of the lamp is described.

Series Connected Buck-Boost Regulator

NASA Technical Reports Server (NTRS)

Birchenough, Arthur G. (Inventor)

2006-01-01

A Series Connected Buck-Boost Regulator (SCBBR) that switches only a fraction of the input power, resulting in relatively high efficiencies. The SCBBR has multiple operating modes including a buck, a boost, and a current limiting mode, so that an output voltage of the SCBBR ranges from below the source voltage to above the source voltage.

Solutions for transients in arbitrarily branching cables: III. Voltage clamp problems.

PubMed

Major, G

1993-07-01

Branched cable voltage recording and voltage clamp analytical solutions derived in two previous papers are used to explore practical issues concerning voltage clamp. Single exponentials can be fitted reasonably well to the decay phase of clamped synaptic currents, although they contain many underlying components. The effective time constant depends on the fit interval. The smoothing effects on synaptic clamp currents of dendritic cables and series resistance are explored with a single cylinder + soma model, for inputs with different time courses. "Soma" and "cable" charging currents cannot be separated easily when the soma is much smaller than the dendrites. Subtractive soma capacitance compensation and series resistance compensation are discussed. In a hippocampal CA1 pyramidal neurone model, voltage control at most dendritic sites is extremely poor. Parameter dependencies are illustrated. The effects of series resistance compound those of dendritic cables and depend on the "effective capacitance" of the cell. Plausible combinations of parameters can cause order-of-magnitude distortions to clamp current waveform measures of simulated Schaeffer collateral inputs. These voltage clamp problems are unlikely to be solved by the use of switch clamp methods.

Soft switching resonant converter with duty-cycle control in DC micro-grid system

NASA Astrophysics Data System (ADS)

Lin, Bor-Ren

2018-01-01

Resonant converter has been widely used for the benefits of low switching losses and high circuit efficiency. However, the wide frequency variation is the main drawback of resonant converter. This paper studies a new modular resonant converter with duty-cycle control to overcome this problem and realise the advantages of low switching losses, no reverse recovery current loss, balance input split voltages and constant frequency operation for medium voltage direct currentgrid or system network. Series full-bridge (FB) converters are used in the studied circuit in order to reduce the voltage stresses and power rating on power semiconductors. Flying capacitor is used between two FB converters to balance input split voltages. Two circuit modules are paralleled on the secondary side to lessen the current rating of rectifier diodes and the size of magnetic components. The resonant tank is operated at inductive load circuit to help power switches to be turned on at zero voltage with wide load range. The pulse-width modulation scheme is used to regulate output voltage. Experimental verifications are provided to show the performance of the proposed circuit.

Low-power low-voltage superior-order curvature corrected voltage reference

NASA Astrophysics Data System (ADS)

Popa, Cosmin

2010-06-01

A complementary metal oxide semiconductor (CMOS) voltage reference with a logarithmic curvature-correction will be presented. The first-order compensation is realised using an original offset voltage follower (OVF) block as a proportional to absolute temperature (PTAT) voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. The new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier (ADA) block for compensating the logarithmic temperature dependent term from the first-order compensated voltage reference. In order to increase the circuit accuracy, an original temperature-dependent current generator will be designed for computing the exact type of the implemented curvature-correction. The relatively small complexity of the current squarer allows an important increasing of the circuit accuracy that could be achieved by increasing the current generator complexity. As a result of operating most of the MOS transistors in weak inversion, the original proposed voltage reference could be valuable for low-power applications. The circuit is implemented in 0.35 μm CMOS technology and consumes only 60μA for t = 25°C, being supplied at the minimal supply voltage V DD = 1.75V. The temperature coefficient of the reference voltage is 8.7 ppm/°C, while the line sensitivity is 0.75 mV/V for a supply voltage between 1.75 V and 7 V.

Design, experiments and simulation of voltage transformers on the basis of a differential input D-dot sensor.

PubMed

Wang, Jingang; Gao, Can; Yang, Jie

2014-07-17

Currently available traditional electromagnetic voltage sensors fail to meet the measurement requirements of the smart grid, because of low accuracy in the static and dynamic ranges and the occurrence of ferromagnetic resonance attributed to overvoltage and output short circuit. This work develops a new non-contact high-bandwidth voltage measurement system for power equipment. This system aims at the miniaturization and non-contact measurement of the smart grid. After traditional D-dot voltage probe analysis, an improved method is proposed. For the sensor to work in a self-integrating pattern, the differential input pattern is adopted for circuit design, and grounding is removed. To prove the structure design, circuit component parameters, and insulation characteristics, Ansoft Maxwell software is used for the simulation. Moreover, the new probe was tested on a 10 kV high-voltage test platform for steady-state error and transient behavior. Experimental results ascertain that the root mean square values of measured voltage are precise and that the phase error is small. The D-dot voltage sensor not only meets the requirement of high accuracy but also exhibits satisfactory transient response. This sensor can meet the intelligence, miniaturization, and convenience requirements of the smart grid.

Frequency Preference Response to Oscillatory Inputs in Two-dimensional Neural Models: A Geometric Approach to Subthreshold Amplitude and Phase Resonance.

PubMed

Rotstein, Horacio G

2014-01-01

We investigate the dynamic mechanisms of generation of subthreshold and phase resonance in two-dimensional linear and linearized biophysical (conductance-based) models, and we extend our analysis to account for the effect of simple, but not necessarily weak, types of nonlinearities. Subthreshold resonance refers to the ability of neurons to exhibit a peak in their voltage amplitude response to oscillatory input currents at a preferred non-zero (resonant) frequency. Phase-resonance refers to the ability of neurons to exhibit a zero-phase (or zero-phase-shift) response to oscillatory input currents at a non-zero (phase-resonant) frequency. We adapt the classical phase-plane analysis approach to account for the dynamic effects of oscillatory inputs and develop a tool, the envelope-plane diagrams, that captures the role that conductances and time scales play in amplifying the voltage response at the resonant frequency band as compared to smaller and larger frequencies. We use envelope-plane diagrams in our analysis. We explain why the resonance phenomena do not necessarily arise from the presence of imaginary eigenvalues at rest, but rather they emerge from the interplay of the intrinsic and input time scales. We further explain why an increase in the time-scale separation causes an amplification of the voltage response in addition to shifting the resonant and phase-resonant frequencies. This is of fundamental importance for neural models since neurons typically exhibit a strong separation of time scales. We extend this approach to explain the effects of nonlinearities on both resonance and phase-resonance. We demonstrate that nonlinearities in the voltage equation cause amplifications of the voltage response and shifts in the resonant and phase-resonant frequencies that are not predicted by the corresponding linearized model. The differences between the nonlinear response and the linear prediction increase with increasing levels of the time scale separation between the voltage and the gating variable, and they almost disappear when both equations evolve at comparable rates. In contrast, voltage responses are almost insensitive to nonlinearities located in the gating variable equation. The method we develop provides a framework for the investigation of the preferred frequency responses in three-dimensional and nonlinear neuronal models as well as simple models of coupled neurons.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, V.R.; Miller, D.R.

1982-05-18

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistane heaters. Temperature-sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive-heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct tempertures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional-frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electrons is required to operate the instrument.

Device and method for measuring the coefficient of performance of a heat pump

DOEpatents

Brantley, Vanston R.; Miller, Donald R.

1984-01-01

A method and instrument is provided which allows quick and accurate measurement of the coefficient of performance of an installed electrically powered heat pump including auxiliary resistance heaters. Temperature sensitive resistors are placed in the return and supply air ducts to measure the temperature increase of the air across the refrigerant and resistive heating elements of the system. The voltages across the resistors which are directly proportional to the respective duct temperatures are applied to the inputs of a differential amplifier so that its output voltage is proportional to the temperature difference across the unit. A voltage-to-frequency converter connected to the output of the differential amplifier converts the voltage signal to a proportional frequency signal. A digital watt meter is used to measure the power to the unit and produces a signal having a frequency proportional to the input power. A digital logic circuit ratios the temperature difference signal and the electric power input signal in a unique manner to produce a single number which is the coefficient of performance of the unit over the test interval. The digital logic and an in-situ calibration procedure enables the instrument to make these measurements in such a way that the ratio of heat flow/power input is obtained without computations. No specialized knowledge of thermodynamics or electronics is required to operate the instrument.

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.

PubMed

Dell' Anna, Francesco; Dong, Tao; Li, Ping; Wen, Yumei; Azadmehr, Mehdi; Casu, Mario; Berg, Yngvar

2018-04-17

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

Mechanisms of Gain Control by Voltage-Gated Channels in Intrinsically-Firing Neurons

PubMed Central

Patel, Ameera X.; Burdakov, Denis

2015-01-01

Gain modulation is a key feature of neural information processing, but underlying mechanisms remain unclear. In single neurons, gain can be measured as the slope of the current-frequency (input-output) relationship over any given range of inputs. While much work has focused on the control of basal firing rates and spike rate adaptation, gain control has been relatively unstudied. Of the limited studies on gain control, some have examined the roles of synaptic noise and passive somatic currents, but the roles of voltage-gated channels present ubiquitously in neurons have been less explored. Here, we systematically examined the relationship between gain and voltage-gated ion channels in a conductance-based, tonically-active, model neuron. Changes in expression (conductance density) of voltage-gated channels increased (Ca2+ channel), reduced (K+ channels), or produced little effect (h-type channel) on gain. We found that the gain-controlling ability of channels increased exponentially with the steepness of their activation within the dynamic voltage window (voltage range associated with firing). For depolarization-activated channels, this produced a greater channel current per action potential at higher firing rates. This allowed these channels to modulate gain by contributing to firing preferentially at states of higher excitation. A finer analysis of the current-voltage relationship during tonic firing identified narrow voltage windows at which the gain-modulating channels exerted their effects. As a proof of concept, we show that h-type channels can be tuned to modulate gain by changing the steepness of their activation within the dynamic voltage window. These results show how the impact of an ion channel on gain can be predicted from the relationship between channel kinetics and the membrane potential during firing. This is potentially relevant to understanding input-output scaling in a wide class of neurons found throughout the brain and other nervous systems. PMID:25816008

Lightweight, high-frequency transformers

NASA Technical Reports Server (NTRS)

Schwarze, G. E.

1983-01-01

The 25-kVA space transformer was developed under contract by Thermal Technology Laboratory, Buffalo, N. Y. The NASA Lewis transformer technology program attempted to develop the baseline technology. For the 25-kVA transformer the input voltage was chosen as 200 V, the output voltage as 1500 V, the input voltage waveform as square wave, the duty cycle as continuous, the frequency range (within certain constraints) as 10 to 40 kHz, the operating temperatures as 85 deg. and 130 C, the baseplate temperature as 50 C, the equivalent leakage inductance as less than 10 micro-h, the operating environment as space, and the life expectancy as 10 years. Such a transformer can also be used for aircraft, ship and terrestrial applications.

Detonation control

DOEpatents

Mace, Jonathan L.; Seitz, Gerald J.; Bronisz, Lawrence E.

2016-10-25

Detonation control modules and detonation control circuits are provided herein. A trigger input signal can cause a detonation control module to trigger a detonator. A detonation control module can include a timing circuit, a light-producing diode such as a laser diode, an optically triggered diode, and a high-voltage capacitor. The trigger input signal can activate the timing circuit. The timing circuit can control activation of the light-producing diode. Activation of the light-producing diode illuminates and activates the optically triggered diode. The optically triggered diode can be coupled between the high-voltage capacitor and the detonator. Activation of the optically triggered diode causes a power pulse to be released from the high-voltage capacitor that triggers the detonator.

Quality engineering tools focused on high power LED driver design using boost power stages in switch mode

NASA Astrophysics Data System (ADS)

Ileana, Ioan; Risteiu, Mircea; Marc, Gheorghe

2016-12-01

This paper is a part of our research dedicated to high power LED lamps designing. The boost-up selected technology wants to meet driver producers' tendency in the frame of efficiency and disturbances constrains. In our work we used modeling and simulation tools for implementing scenarios of the driver work when some controlling functions are executed (output voltage/ current versus input voltage and fixed switching frequency, input and output electric power transfer versus switching frequency, transient inductor voltage analysis, and transient out capacitor analysis). Some electrical and thermal stress conditions are also analyzed. Based on these aspects, a high reliable power LED driver has been designed.

Voltage mode electronically tunable full-wave rectifier

NASA Astrophysics Data System (ADS)

Petrović, Predrag B.; Vesković, Milan; Đukić, Slobodan

2017-01-01

The paper presents a new realization of bipolar full-wave rectifier of input sinusoidal signals, employing one MO-CCCII (multiple output current controlled current conveyor), a zero-crossing detector (ZCD), and one resistor connected to fixed potential. The circuit provides the operating frequency up to 10 MHz with increased linearity and precision in processing of input voltage signal, with a very low harmonic distortion. The errors related to the signal processing and errors bound were investigated and provided in the paper. The PSpice simulations are depicted and agree well with the theoretical anticipation. The maximum power consumption of the converter is approximately 2.83 mW, at ±1.2 V supply voltages.

The contribution of cationic conductances to the potential of rod photoreceptors.

PubMed

Moriondo, Andrea; Rispoli, Giorgio

2010-05-01

The contribution of cationic conductances in shaping the rod photovoltage was studied in light adapted cells recorded under whole-cell voltage- or current-clamp conditions. Depolarising current steps (of size comparable to the light-regulated current) produced monotonic responses when the prepulse holding potential (V (h)) was -40 mV (i.e. corresponding to the membrane potential in the dark). At V (h) = -60 mV (simulating the steady-state response to an intense background of light) current injections <35 pA (mimicking a light decrement) produced instead an initial depolarisation that declined to a plateau, and voltage transiently overshot V (h) at the stimulus offset. Current steps >40 pA produced a steady depolarisation to approximately -16 mV at both V (h). The difference between the responses at the two V (h) was primarily generated by the slow delayed-rectifier-like K(+) current (I (Kx)), which therefore strongly affects both the photoresponse rising and falling phase. The steady voltage observed at both V (h) in response to large current injections was instead generated by Ca-activated K(+) channels (I (KCa)), as previously found. Both I (Kx) and I (KCa) oppose the cation influx, occurring at the light stimulus offset through the cGMP-gated channels and the voltage-activated Ca(2+) channels (I (Ca)). This avoids that the cation influx could erratically depolarise the rod past its normal resting value, thus allowing a reliable dim stimuli detection, without slowing down the photovoltage recovery kinetics. The latter kinetics was instead accelerated by the hyperpolarisation-activated, non-selective current (I (h)) and I (Ca). Blockade of all K(+) currents with external TEA unmasked a I (Ca)-dependent regenerative behaviour.

Compensation for electrical converter nonlinearities

DOEpatents

Perisic, Milun; Ransom, Ray M; Kajouke, Lateef A

2013-11-19

Systems and methods are provided for delivering energy from an input interface to an output interface. An electrical system includes an input interface, an output interface, an energy conversion module between the input interface and the output interface, an inductive element between the input interface and the energy conversion module, and a control module. The control module determines a compensated duty cycle control value for operating the energy conversion module to produce a desired voltage at the output interface and operates the energy conversion module to deliver energy to the output interface with a duty cycle that is influenced by the compensated duty cycle control value. The compensated duty cycle control value is influenced by the current through the inductive element and accounts for voltage across the switching elements of the energy conversion module.

How economic contexts shape calculations of yield in biodiversity offsetting.

PubMed

Carver, L; Sullivan, S

2017-10-01

We examined and analyzed methods used to create numerical equivalence between sites affected by development and proposed conservation offset sites. Application of biodiversity offsetting metrics in development impact and mitigation assessments is thought to standardize biodiversity conservation outcomes, sometimes termed yield by those conducting these calculations. The youth of biodiversity offsetting in application, however, means little is known about how biodiversity valuations and offset contracts between development and offset sites are agreed on in practice or about long-term conservation outcomes. We examined how sites were made commensurable and how biodiversity gains or yields were calculated and negotiated for a specific offset contract in a government-led pilot study of biodiversity offsets in England. Over 24 months, we conducted participant observations of various stages in the negotiation of offset contracts through repeated visits to 3 (anonymized) biodiversity offset contract sites. We conducted 50 semistructured interviews of stakeholders in regional and local government, the private sector, and civil society. We used a qualitative data analysis software program (DEDOOSE) to textually analyze interview transcriptions. We also compared successive iterations of biodiversity-offsetting calculation spreadsheets and planning documents. A particular focus was the different iterations of a specific biodiversity impact assessment in which the biodiversity offsetting metric developed by the U.K.'s Department for Environment, Food and Rural Affairs was used. We highlight 3 main findings. First, biodiversity offsetting metrics were amended in creative ways as users adapted inputs to metric calculations to balance and negotiate conflicting requirements. Second, the practice of making different habitats equivalent to each other through the application of biodiversity offsetting metrics resulted in commensuration outcomes that may not provide projected conservation gains. Third, the pressure of creating value for money diminished projected conservation yields. © 2017 The Authors. Conservation Biology published by Wiley Periodicals, Inc. on behalf of Society for Conservation Biology.

Meter circuit for tuning RF amplifiers

NASA Technical Reports Server (NTRS)

Longthorne, J. E.

1973-01-01

Circuit computes and indicates efficiency of RF amplifier as inputs and other parameters are varied. Voltage drop across internal resistance of ammeter is amplified by operational amplifier and applied to one multiplier input. Other input is obtained through two resistors from positive terminal of power supply.

Temperature compensated and self-calibrated current sensor

DOEpatents

Yakymyshyn, Christopher Paul; Brubaker, Michael Allen; Yakymyshyn, Pamela Jane

2007-09-25

A method is described to provide temperature compensation and reduction of drift due to aging for a current sensor based on a plurality of magnetic field sensors positioned around a current carrying conductor. The offset voltage signal generated by each magnetic field sensor is used to correct variations in the output signal due to temperature variations and aging.

Optimal pulse design for communication-oriented slow-light pulse detection.

PubMed

Stenner, Michael D; Neifeld, Mark A

2008-01-21

We present techniques for designing pulses for linear slow-light delay systems which are optimal in the sense that they maximize the signal-to-noise ratio (SNR) and signal-to-noise-plus-interference ratio (SNIR) of the detected pulse energy. Given a communication model in which input pulses are created in a finite temporal window and output pulse energy in measured in a temporally-offset output window, the SNIR-optimal pulses achieve typical improvements of 10 dB compared to traditional pulse shapes for a given output window offset. Alternatively, for fixed SNR or SNIR, window offset (detection delay) can be increased by 0.3 times the window width. This approach also invites a communication-based model for delay and signal fidelity.

Frequency downconversion and phase noise in MIT.

PubMed

Watson, S; Williams, R J; Griffiths, H; Gough, W; Morris, A

2002-02-01

High-frequency (3-30 MHz) operation of MIT systems offers advantages in terms of the larger induced signal amplitudes compared to systems operating in the low- or medium-frequency ranges. Signal distribution at HF, however, presents difficulties, in particular with isolation and phase stability. It is therefore valuable to translate received signals to a lower frequency range through heterodyne downconversion, a process in which relative signal amplitude and phase information is in theory retained. Measurement of signal amplitude and phase is also simplified at lower frequencies. The paper presents details of measurements on a direct phase measurement system utilizing heterodyne downconversion and compares the relative performance of three circuit configurations. The 100-sample average precision of a circuit suitable for use as a receiver within an MIT system was 0.008 degrees for input amplitude -21 dBV. As the input amplitude was reduced from -21 to -72 dBV variation in the measured phase offset was observed, with the offset varying by 1.8 degrees. The precision of the circuit deteriorated with decreasing input amplitude, but was found to provide a 100-sample average precision of <0.022 degrees down to an input amplitude of -60 dBV. The characteristics of phase noise within the system are discussed.

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

PubMed

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

PubMed Central

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-il Dan; Ko, Hyoungho

2015-01-01

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms. PMID:26473877

Hearing aid malfunction detection system

NASA Technical Reports Server (NTRS)

Kessinger, R. L. (Inventor)

1977-01-01

A malfunction detection system for detecting malfunctions in electrical signal processing circuits is disclosed. Malfunctions of a hearing aid in the form of frequency distortion and/or inadequate amplification by the hearing aid amplifier, as well as weakening of the hearing aid power supply are detectable. A test signal is generated and a timed switching circuit periodically applies the test signal to the input of the hearing aid amplifier in place of the input signal from the microphone. The resulting amplifier output is compared with the input test signal used as a reference signal. The hearing aid battery voltage is also periodically compared to a reference voltage. Deviations from the references beyond preset limits cause a warning system to operate.

Full-wave receiver architecture for the homodyne motion sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haugen, Peter C.; Dallum, Gregory E.; Welsh, Patrick A.

A homodyne motion sensor or detector based on ultra-wideband radar utilizes the entire received waveform through implementation of a voltage boosting receiver. The receiver includes a receiver input and a receiver output. A first diode is connected to the receiver output. A first charge storage capacitor is connected from between the first diode and the receiver output to ground. A second charge storage capacitor is connected between the receiver input and the first diode. A second diode is connected from between the second charge storage capacitor and the first diode to ground. The dual diode receiver performs voltage boosting ofmore » a RF signal received at the receiver input, thereby enhancing receiver sensitivity.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chinthavali, Madhu Sudhan; Campbell, Steven L

This paper presents an analytical model for wireless power transfer system used in electric vehicle application. The equivalent circuit model for each major component of the system is described, including the input voltage source, resonant network, transformer, nonlinear diode rectifier load, etc. Based on the circuit model, the primary side compensation capacitance, equivalent input impedance, active / reactive power are calculated, which provides a guideline for parameter selection. Moreover, the voltage gain curve from dc output to dc input is derived as well. A hardware prototype with series-parallel resonant stage is built to verify the developed model. The experimental resultsmore » from the hardware are compared with the model predicted results to show the validity of the model.« less

Full-wave receiver architecture for the homodyne motion sensor

DOEpatents

Haugen, Peter C; Dallum, Gregory E; Welsh, Patrick A; Romero, Carlos E

2013-11-19

A homodyne motion sensor or detector based on ultra-wideband radar utilizes the entire received waveform through implementation of a voltage boosting receiver. The receiver includes a receiver input and a receiver output. A first diode is connected to the receiver output. A first charge storage capacitor is connected from between the first diode and the receiver output to ground. A second charge storage capacitor is connected between the receiver input and the first diode. A second diode is connected from between the second charge storage capacitor and the first diode to ground. The dual diode receiver performs voltage boosting of a RF signal received at the receiver input, thereby enhancing receiver sensitivity.

Origin of negative resistance in anion migration controlled resistive memory

NASA Astrophysics Data System (ADS)

Banerjee, Writam; Wu, Facai; Hu, Yuan; Wu, Quantan; Wu, Zuheng; Liu, Qi; Liu, Ming

2018-03-01

Resistive random access memory (RRAM) is one of the most promising emerging nonvolatile technologies for the futuristic memory devices. Resistive switching behavior often shows negative resistance (NR), either voltage controlled or current controlled. In this work, the origin of a current compliance dependent voltage controlled NR effect during the resetting of anion migration based RRAM devices is discussed. The N-type voltage controlled NR is a high field driven phenomena. The current conduction within the range of a certain negative voltage is mostly dominated by space charge limited current. But with the higher negative voltage, a field induced tunneling effect is generated in the NR region. The voltage controlled NR is strongly dependent on the compliance current. The area independent behavior indicates the filamentary switching. The peak to valley ratio (PVR) is > 5. The variation of PVR as a function of the conduction band offset is achieved. Compared to other reported works, based on the PVR, it is possible to distinguish the RRAM types. Generally, due to the higher electric field effect on the metallic bridge during RESET, the electrochemical metallization type RRAM shows much higher PVR than the valance change type RRAM.

Air Brayton Solar Receiver, phase 2

NASA Technical Reports Server (NTRS)

Deanda, L. E.

1981-01-01

An air Brayton solar receiver (ABSR) is discussed. The ABSR consists of a cylindrical, insulated, offset plate fin heat exchanger which is mounted at the focal plane of a fully tracking parabolic solar collector. The receiver transfer heat from the concentrated solar radiation (which impinges on the inside walls of the heat exchanger) to the working fluid i.e., air. The hot air would then e used to drive a small Brayton cycle heat engine. The engine in turn drives a generator which produces electrical energy. Symmetrical and asymmetrical solar power input into the ABSR are analyzed. The symmetrical cases involve the baseline incident flux and the axially shifted incident fluxes. The asymmetrical cases correspond to the solar fluxes that are obtained by reduced solar input from one half of the concentrator or by receiver offset of plus or minus 1 inch from the concentrator optical axis.

Single-Event Transient Response of Comparator Pre-Amplifiers in a Complementary SiGe Technology

NASA Astrophysics Data System (ADS)

Ildefonso, Adrian; Lourenco, Nelson E.; Fleetwood, Zachary E.; Wachter, Mason T.; Tzintzarov, George N.; Cardoso, Adilson S.; Roche, Nicolas J.-H.; Khachatrian, Ani; McMorrow, Dale; Buchner, Stephen P.; Warner, Jeffrey H.; Paki, Pauline; Kaynak, Mehmet; Tillack, Bernd; Cressler, John D.

2017-01-01

The single-event transient (SET) response of the pre-amplification stage of two latched comparators designed using either npn or pnp silicon-germanium heterojunction bipolar transistors (SiGe HBTs) is investigated via two-photon absorption (TPA) carrier injection and mixed-mode TCAD simulations. Experimental data and TCAD simulations showed an improved SET response for the pnp comparator circuit. 2-D raster scans revealed that the devices in the pnp circuit exhibit a reduction in sensitive area of up to 80% compared to their npn counterparts. In addition, by sweeping the input voltage, the sensitive operating region with respect to SETs was determined. By establishing a figure-of-merit, relating the transient peaks and input voltage polarities, the pnp device was determined to have a 21.4% improved response with respect to input voltage. This study has shown that using pnp devices is an effective way to mitigate SETs, and could enable further radiation-hardening-by-design techniques.

Method and apparatus for stabilizing pulsed microwave amplifiers

DOEpatents

Hopkins, Donald B.

1993-01-01

Phase and amplitude variations at the output of a high power pulsed microwave amplifier arising from instabilities of the driving electron beam are suppressed with a feed-forward system that can stabilize pulses which are too brief for regulation by conventional feedback techniques. Such variations tend to be similar during successive pulses. The variations are detected during each pulse by comparing the amplifier output with the low power input signal to obtain phase and amplitude error signals. This enables storage of phase and amplitude correction signals which are used to make compensating changes in the low power input signal during the following amplifier output pulse which suppress the variations. In the preferred form of the invention, successive increments of the correction signals for each pulse are stored in separate channels of a multi-channel storage. Sequential readout of the increments during the next pulse provides variable control voltages to a voltage controlled phase shifter and voltage controlled amplitude modulator in the amplifier input signal path.

Electric generation and ratcheted transport of contact-charged drops

NASA Astrophysics Data System (ADS)

Cartier, Charles A.; Graybill, Jason R.; Bishop, Kyle J. M.

2017-10-01

We describe a simple microfluidic system that enables the steady generation and efficient transport of aqueous drops using only a constant voltage input. Drop generation is achieved through an electrohydrodynamic dripping mechanism by which conductive drops grow and detach from a grounded nozzle in response to an electric field. The now-charged drops are transported down a ratcheted channel by contact charge electrophoresis powered by the same voltage input used for drop generation. We investigate how the drop size, generation frequency, and transport velocity depend on system parameters such as the liquid viscosity, interfacial tension, applied voltage, and channel dimensions. The observed trends are well explained by a series of scaling analyses that provide insight into the dominant physical mechanisms underlying drop generation and ratcheted transport. We identify the conditions necessary for achieving reliable operation and discuss the various modes of failure that can arise when these conditions are violated. Our results demonstrate that simple electric inputs can power increasingly complex droplet operations with potential opportunities for inexpensive and portable microfluidic systems.

Electric generation and ratcheted transport of contact-charged drops.

PubMed

Cartier, Charles A; Graybill, Jason R; Bishop, Kyle J M

2017-10-01

We describe a simple microfluidic system that enables the steady generation and efficient transport of aqueous drops using only a constant voltage input. Drop generation is achieved through an electrohydrodynamic dripping mechanism by which conductive drops grow and detach from a grounded nozzle in response to an electric field. The now-charged drops are transported down a ratcheted channel by contact charge electrophoresis powered by the same voltage input used for drop generation. We investigate how the drop size, generation frequency, and transport velocity depend on system parameters such as the liquid viscosity, interfacial tension, applied voltage, and channel dimensions. The observed trends are well explained by a series of scaling analyses that provide insight into the dominant physical mechanisms underlying drop generation and ratcheted transport. We identify the conditions necessary for achieving reliable operation and discuss the various modes of failure that can arise when these conditions are violated. Our results demonstrate that simple electric inputs can power increasingly complex droplet operations with potential opportunities for inexpensive and portable microfluidic systems.

Method and apparatus for stabilizing pulsed microwave amplifiers

DOEpatents

Hopkins, D.B.

1993-01-26

Phase and amplitude variations at the output of a high power pulsed microwave amplifier arising from instabilities of the driving electron beam are suppressed with a feed-forward system that can stabilize pulses which are too brief for regulation by conventional feedback techniques. Such variations tend to be similar during successive pulses. The variations are detected during each pulse by comparing the amplifier output with the low power input signal to obtain phase and amplitude error signals. This enables storage of phase and amplitude correction signals which are used to make compensating changes in the low power input signal during the following amplifier output pulse which suppress the variations. In the preferred form of the invention, successive increments of the correction signals for each pulse are stored in separate channels of a multi-channel storage. Sequential readout of the increments during the next pulse provides variable control voltages to a voltage controlled phase shifter and voltage controlled amplitude modulator in the amplifier input signal path.

A nanoscale piezoelectric transformer for low-voltage transistors.

PubMed

Agarwal, Sapan; Yablonovitch, Eli

2014-11-12

A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

In vivo voltage-dependent influences on summation of synaptic potentials in neurons of the lateral nucleus of the amygdala

PubMed Central

Rosenkranz, J. Amiel

2012-01-01

The amygdala has a fundamental role in driving affective behaviors in response to sensory cues. To accomplish this, neurons of the lateral nucleus (LAT) must integrate a large number of synaptic inputs. A wide range of factors influence synaptic integration, including membrane potential, voltage-gated ion channels and GABAergic inhibition. However, little is known about how these factors modulate integration of synaptic inputs in LAT neurons in vivo. The purpose of this study was to determine the voltage-dependent factors that modify in vivo integration of synaptic inputs in the soma of LAT neurons. In vivo intracellular recordings from anesthetized rats were used to measure post-synaptic potentials (PSPs) and clusters of PSPs across a range of membrane potentials. These studies found that the relationship between membrane potential and PSP clusters was sublinear, due to a reduction of cluster amplitude and area at depolarized membrane potentials. In combination with intracellular delivery of pharmacological agents, it was found that the voltage-dependent suppression of PSP clusters was sensitive to tetraethylammonium (TEA), but not cesium or a blocker of fast GABAergic inhibition. These findings indicate that integration of PSPs in LAT neurons in vivo is strongly modified by somatic membrane potential, likely through voltage-dependent TEA-sensitive potassium channels. Conditions that lead to a shift in membrane potential, or a modulation of the number or function of these ion channels will lead to a more uniform capacity for integration across voltages, and perhaps greatly facilitate amygdala-dependent behaviors. PMID:22989917

Input integration around the dendritic branches in hippocampal dentate granule cells.

PubMed

Kamijo, Tadanobu Chuyo; Hayakawa, Hirofumi; Fukushima, Yasuhiro; Kubota, Yoshiyuki; Isomura, Yoshikazu; Tsukada, Minoru; Aihara, Takeshi

2014-08-01

Recent studies have shown that the dendrites of several neurons are not simple translators but are crucial facilitators of excitatory postsynaptic potential (EPSP) propagation and summation of synaptic inputs to compensate for inherent voltage attenuation. Granule cells (GCs)are located at the gateway for valuable information arriving at the hippocampus from the entorhinal cortex. However, the underlying mechanisms of information integration along the dendrites of GCs in the hippocampus are still unclear. In this study, we investigated the input integration around dendritic branches of GCs in the rat hippocampus. We applied differential spatiotemporal stimulations to the dendrites using a high-speed glutamate-uncaging laser. Our results showed that when two sites close to and equidistant from a branching point were simultaneously stimulated, a nonlinear summation of EPSPs was observed at the soma. In addition, nonlinear summation (facilitation) depended on the stimulus location and was significantly blocked by the application of a voltage-dependent Ca(2+) channel antagonist. These findings suggest that the nonlinear summation of EPSPs around the dendritic branches of hippocampal GCs is a result of voltage-dependent Ca(2+) channel activation and may play a crucial role in the integration of input information.

Hybrid zero-voltage switching (ZVS) control for power inverters

DOEpatents

Amirahmadi, Ahmadreza; Hu, Haibing; Batarseh, Issa

2016-11-01

A power inverter combination includes a half-bridge power inverter including first and second semiconductor power switches receiving input power having an intermediate node therebetween providing an inductor current through an inductor. A controller includes input comparison circuitry receiving the inductor current having outputs coupled to first inputs of pulse width modulation (PWM) generation circuitry, and a predictive control block having an output coupled to second inputs of the PWM generation circuitry. The predictive control block is coupled to receive a measure of Vin and an output voltage at a grid connection point. A memory stores a current control algorithm configured for resetting a PWM period for a switching signal applied to control nodes of the first and second power switch whenever the inductor current reaches a predetermined upper limit or a predetermined lower limit.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE PAGES

Seif, Johannes Peter; Menda, Deneb; Descoeudres, Antoine; ...

2016-08-01

Here, amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers -- inserted between substrate and (front or rear) contacts -- since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. Asmore » a consequence, device implementation of such films as window layers -- without degraded carrier collection -- demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seif, Johannes Peter, E-mail: johannes.seif@alumni.epfl.ch; Ballif, Christophe; De Wolf, Stefaan

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation ofmore » such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermionic (field) emission, the device performance is mainly dictated by the passivation of its surfaces. In this context, compared to the standard amorphous silicon layers, the wide-bandgap oxide layers applied here passivate remarkably better at these temperatures, which may represent an additional benefit under practical operation conditions.« less

A Survey of Architectural Techniques for Near-Threshold Computing

DOE PAGES

Mittal, Sparsh

2015-12-28

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. In low-voltage computing and specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate and performance loss etc. Our paper surveys several re- cent techniques which aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlightmore » their similarities and differences. Ultimately, we hope that this paper will provide insights into state-of-art NTC techniques to researchers and system-designers and inspire further research in this field.« less

A Survey of Architectural Techniques for Near-Threshold Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. In low-voltage computing and specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate and performance loss etc. Our paper surveys several re- cent techniques which aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlightmore » their similarities and differences. Ultimately, we hope that this paper will provide insights into state-of-art NTC techniques to researchers and system-designers and inspire further research in this field.« less

The electrical properties of n-ZnO/p-SnO heterojunction diodes

NASA Astrophysics Data System (ADS)

Javaid, K.; Xie, Y. F.; Luo, H.; Wang, M.; Zhang, H. L.; Gao, J. H.; Zhuge, F.; Liang, L. Y.; Cao, H. T.

2016-09-01

In the present work, n-type zinc oxide (ZnO) and p-type tin monoxide (SnO) based heterostructure diodes were fabricated on an indium-tin-oxide glass using the radio frequency magnetron sputtering technique. The prepared ZnO/SnO diodes exhibited a typical rectifying behavior, with a forward to reverse current ratio about 500 ± 5 at 2 V and turn on voltage around 1.6 V. The built-in voltage of the diode was extracted to be 0.5 V based on the capacitance-voltage (C-V) measurement. The valence and conduction band offsets were deliberated through the band energy diagram of ZnO/SnO heterojunction, as 1.08 eV and 0.41 eV, respectively. The potential barrier-dependent carrier transportation mechanism across the space charge region was also investigated.

Biased-probe-induced water ion injection into amorphous polymers investigated by electric force microscopy

NASA Astrophysics Data System (ADS)

Knorr, Nikolaus; Rosselli, Silvia; Miteva, Tzenka; Nelles, Gabriele

2009-06-01

Although charging of insulators by atomic force microscopy (AFM) has found widespread interest, often with data storage or nanoxerography in mind, less attention has been paid to the charging mechanism and the nature of the charge. Here we present a systematic study on charging of amorphous polymer films by voltage pulses applied to conducting AFM probes. We find a quadratic space charge limited current law of Kelvin probe force microscopy and electrostatic force microscopy peak volumes in pulse height, offset by a threshold voltage, and a power law in pulse width of positive exponents smaller than one. We interpret the results by a charging mechanism of injection and surface near accumulation of aqueous ions stemming from field induced water adsorption, with threshold voltages linked to the water affinities of the polymers.

Electronic circuit provides accurate sensing and control of dc voltage

NASA Technical Reports Server (NTRS)

Loftus, W. D.

1966-01-01

Electronic circuit used relay coil to sense and control dc voltage. The control relay is driven by a switching transistor that is biased to cutoff for all input up to slightly less than the threshold level.

A single supply biopotential amplifier.

PubMed

Spinelli, E M; Martinez, N H; Mayosky, M A

2001-04-01

A biopotential amplifier for single supply operation is presented. It uses a Driven Right Leg Circuit (DRL) to drive the patient's body to a DC common mode voltage, centering biopotential signals with respect to the amplifier's input voltage range. This scheme ensures proper range operation when a single power supply is used. The circuit described is especially suited for low consumption, battery-powered applications, requiring a single battery and avoiding switching voltage inverters to achieve dual supplies. The generic circuit is described and, as an example, a biopotential amplifier with a gain of 60 dB and a DC input range of +/-200 mV was implemented using low power operational amplifiers. A Common Mode Rejection Ratio (CMRR) of 126 dB at 50 Hz was achieved without trimming.

Integrated circuit electrometer and sweep circuitry for an atmospheric probe

NASA Technical Reports Server (NTRS)

Zimmerman, L. E.

1971-01-01

The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

Geologic fracturing method and resulting fractured geologic structure

DOEpatents

Mace, Jonathan L.; Bradley, Christopher R.; Greening, Doran R.; Steedman, David W.

2016-11-08

Detonation control modules and detonation control circuits are provided herein. A trigger input signal can cause a detonation control module to trigger a detonator. A detonation control module can include a timing circuit, a light-producing diode such as a laser diode, an optically triggered diode, and a high-voltage capacitor. The trigger input signal can activate the timing circuit. The timing circuit can control activation of the light-producing diode. Activation of the light-producing diode illuminates and activates the optically triggered diode. The optically triggered diode can be coupled between the high-voltage capacitor and the detonator. Activation of the optically triggered diode causes a power pulse to be released from the high-voltage capacitor that triggers the detonator.

Four-gate transistor analog multiplier circuit

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Design, Experiments and Simulation of Voltage Transformers on the Basis of a Differential Input D-dot Sensor

PubMed Central

Wang, Jingang; Gao, Can; Yang, Jie

2014-01-01

Currently available traditional electromagnetic voltage sensors fail to meet the measurement requirements of the smart grid, because of low accuracy in the static and dynamic ranges and the occurrence of ferromagnetic resonance attributed to overvoltage and output short circuit. This work develops a new non-contact high-bandwidth voltage measurement system for power equipment. This system aims at the miniaturization and non-contact measurement of the smart grid. After traditional D-dot voltage probe analysis, an improved method is proposed. For the sensor to work in a self-integrating pattern, the differential input pattern is adopted for circuit design, and grounding is removed. To prove the structure design, circuit component parameters, and insulation characteristics, Ansoft Maxwell software is used for the simulation. Moreover, the new probe was tested on a 10 kV high-voltage test platform for steady-state error and transient behavior. Experimental results ascertain that the root mean square values of measured voltage are precise and that the phase error is small. The D-dot voltage sensor not only meets the requirement of high accuracy but also exhibits satisfactory transient response. This sensor can meet the intelligence, miniaturization, and convenience requirements of the smart grid. PMID:25036333

E-beam high voltage switching power supply

DOEpatents

Shimer, Daniel W.; Lange, Arnold C.

1997-01-01

A high power, solid state power supply is described for producing a controllable, constant high voltage output under varying and arcing loads suitable for powering an electron beam gun or other ion source. The present power supply is most useful for outputs in a range of about 100-400 kW or more. The power supply is comprised of a plurality of discrete switching type dc-dc converter modules, each comprising a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, and an output rectifier for producing a dc voltage at the output of each module. The inputs to the converter modules are fed from a common dc rectifier/filter and are linked together in parallel through decoupling networks to suppress high frequency input interactions. The outputs of the converter modules are linked together in series and connected to the input of the transmission line to the load through a decoupling and line matching network. The dc-dc converter modules are phase activated such that for n modules, each module is activated equally 360.degree./n out of phase with respect to a successive module. The phased activation of the converter modules, combined with the square current waveforms out of the step up transformers, allows the power supply to operate with greatly reduced output capacitance values which minimizes the stored energy available for discharge into an electron beam gun or the like during arcing. The present power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle using simulated voltage feedback signals and voltage feedback loops. Circuitry is also provided for sensing incipient arc currents reflected at the output of the power supply and for simultaneously decoupling the power supply circuitry from the arcing load.

E-beam high voltage switching power supply

DOEpatents

Shimer, D.W.; Lange, A.C.

1997-03-11

A high power, solid state power supply is described for producing a controllable, constant high voltage output under varying and arcing loads suitable for powering an electron beam gun or other ion source. The present power supply is most useful for outputs in a range of about 100-400 kW or more. The power supply is comprised of a plurality of discrete switching type dc-dc converter modules, each comprising a voltage regulator, an inductor, an inverter for producing a high frequency square wave current of alternating polarity, an improved inverter voltage clamping circuit, a step up transformer, and an output rectifier for producing a dc voltage at the output of each module. The inputs to the converter modules are fed from a common dc rectifier/filter and are linked together in parallel through decoupling networks to suppress high frequency input interactions. The outputs of the converter modules are linked together in series and connected to the input of the transmission line to the load through a decoupling and line matching network. The dc-dc converter modules are phase activated such that for n modules, each module is activated equally 360{degree}/n out of phase with respect to a successive module. The phased activation of the converter modules, combined with the square current waveforms out of the step up transformers, allows the power supply to operate with greatly reduced output capacitance values which minimizes the stored energy available for discharge into an electron beam gun or the like during arcing. The present power supply also provides dynamic response to varying loads by controlling the voltage regulator duty cycle using simulated voltage feedback signals and voltage feedback loops. Circuitry is also provided for sensing incipient arc currents reflected at the output of the power supply and for simultaneously decoupling the power supply circuitry from the arcing load. 7 figs.

High temperature charge amplifier for geothermal applications

DOEpatents

Lindblom, Scott C.; Maldonado, Frank J.; Henfling, Joseph A.

2015-12-08

An amplifier circuit in a multi-chip module includes a charge to voltage converter circuit, a voltage amplifier a low pass filter and a voltage to current converter. The charge to voltage converter receives a signal representing an electrical charge and generates a voltage signal proportional to the input signal. The voltage amplifier receives the voltage signal from the charge to voltage converter, then amplifies the voltage signal by the gain factor to output an amplified voltage signal. The lowpass filter passes low frequency components of the amplified voltage signal and attenuates frequency components greater than a cutoff frequency. The voltage to current converter receives the output signal of the lowpass filter and converts the output signal to a current output signal; wherein an amplifier circuit output is selectable between the output signal of the lowpass filter and the current output signal.

Differential Amplifier with Current-Mirror Load: Influence of Current Gain, Early Voltage, and Supply Voltage on the DC Output Voltage

ERIC Educational Resources Information Center

Paulik, G. F.; Mayer, R. P.

2012-01-01

A differential amplifier composed of an emitter-coupled pair is useful as an example in lecture presentations and laboratory experiments in electronic circuit analysis courses. However, in an active circuit with zero input load V[subscript id], both laboratory measurements and PSPICE and LTspice simulation results for the output voltage…

Method and apparatus to provide power conversion with high power factor

DOEpatents

Perreault, David J.; Lim, Seungbum; Otten, David M.

2017-05-23

A power converter circuit rectifies a line voltage and applies the rectified voltage to a stack of capacitors. Voltages on the capacitors are coupled to a plurality of regulating converters to be converted to regulated output signals. The regulated output signals are combined and converted to a desired DC output voltage of the power converter. Input currents of the regulating converters are modulated in a manner that enhances the power factor of the power converter.

OBSAPS Data Acquisition System: Operator’s Manual and System Overview

DTIC Science & Technology

2011-05-01

Explanation of Druck Voltage to Depth Conversion used during OBSAPS (April-May’11)   25   Druck  Pressure  sensor  conversion  from...for H-91, PA Voltage, PA Current and Sonobuoy and Druck pressure sensor analog inputs. 6. Software settable thresholds for H-91, PA Voltage, PA...17. Custom dry side box for Druck Pressure Sensor supply voltage and dropping resistor. 18. Battery 9-30VDC for supplying Druck power 19. Druck PTX

Role of electron-phonon coupling and thermal expansion on band gaps, carrier mobility, and interfacial offsets in kesterite thin-film solar cells

NASA Astrophysics Data System (ADS)

Monserrat, Bartomeu; Park, Ji-Sang; Kim, Sunghyun; Walsh, Aron

2018-05-01

The efficiencies of solar cells based on kesterite Cu2ZnSnS4 (CZTS) and Cu2ZnSnSe4 (CZTSe) are limited by a low open-circuit voltage due to high rates of non-radiative electron-hole recombination. To probe the origin of this bottleneck, we calculate the band offset of CZTS(Se) with CdS, confirming a weak spike of 0.1 eV for CZTS/wurtzite-CdS and a strong spike of 0.4 eV for CZTSe/wurtzite-CdS. We also consider the effects of temperature on the band alignment, finding that increasing temperature significantly enhances the spike-type offset. We further resolve an outstanding discrepancy between the measured and calculated phonon frequencies for the kesterites, and use these to estimate the upper limit of electron and hole mobilities based on optic phonon Fröhlich scattering, which uncovers an intrinsic asymmetry with faster (minority carrier) electron mobility.

106 17 Telemetry Standards Chapter 2

DTIC Science & Technology

2017-07-31

high frequency STC space -time code SOQPSK shaped offset quadrature phase shift keying UHF ultra- high frequency US&P United States...and Possessions VCO voltage-controlled oscillator VHF very- high frequency WCS Wireless Communication Service Telemetry Standards, RCC Standard...get interference. a. Telemetry Bands Air and space -to-ground telemetering is allocated in the ultra- high frequency (UHF) bands 1435 to 1535, 2200

Particle sensor array

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor); Blaes, Brent R. (Inventor); Lieneweg, Udo (Inventor)

1994-01-01

A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.

Diplexer switch

NASA Technical Reports Server (NTRS)

Grauling, C. H., Jr.; Parker, T. W.

1977-01-01

Switch achieves high isolation and continuous input/output matching by using resonant coupling structure of diplexer. Additionally, dc bias network used to control switch is decoupled from RF input and output lines. Voltage transients in external circuits are thus minimized.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.

PubMed

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-12-31

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal-oxide-semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation

PubMed Central

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-01-01

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal–oxide–semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms. PMID:26729122

Shock Ignition Sensitivity of Multiply-Shocked TNT

DTIC Science & Technology

1982-07-01

inynsj’ea prodaat. UNCLASSI FIED SECURITY CLASSIFICATION OF THIS PAGE MUert Date Emo REPOR DOCMENTTIONPAGEREAL) INSTRUCTIONS REPORT___...pressure through the following equation, (0.027) (12) where Av = signal voltage (volts) e = input voltage (volts) P = shock pressure (GPa). Fig. 17

Input Power Characteristics of the Thyristor Variable Voltage Power Conditioner

DOT National Transportation Integrated Search

1973-11-01

A laboratory study was made of transformer and thyristor voltage control for speed control of a rotary induction motor. The test program consisted of two parts; the first dealing with measurements of the induction motor characteristics and the second...

A Low Power Low Phase Noise Oscillator for MICS Transceivers

PubMed Central

Li, Dawei; Liu, Dongsheng; Kang, Chaojian; Zou, Xuecheng

2017-01-01

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm2 area. The measured phase noise is −108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage. PMID:28085107

A Low Power Low Phase Noise Oscillator for MICS Transceivers.

PubMed

Li, Dawei; Liu, Dongsheng; Kang, Chaojian; Zou, Xuecheng

2017-01-12

A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm² area. The measured phase noise is -108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage.

Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

DTIC Science & Technology

2010-01-01

margin measurement 28 Any voltage above the line marked VIH is considered a valid logic high on the input of the gate. VIH and VIL are defined...can handle any voltage noise level at the input up to VIL without changing state. The region in between VIL and VIH is considered an invalid logic...29 Table 2.2: Intrinsic device characteristics derived from SPETCRE simulations   VIH  (V)  VIL (V)  High Noise Margin  (V)  Low Noise Margin (V

Rail-to-rail differential input amplification stage with main and surrogate differential pairs

DOEpatents

Britton, Jr., Charles Lanier; Smith, Stephen Fulton

2007-03-06

An operational amplifier input stage provides a symmetrical rail-to-rail input common-mode voltage without turning off either pair of complementary differential input transistors. Secondary, or surrogate, transistor pairs assume the function of the complementary differential transistors. The circuit also maintains essentially constant transconductance, constant slew rate, and constant signal-path supply current as it provides rail-to-rail operation.

Systems and methods for process and user driven dynamic voltage and frequency scaling

DOEpatents

Mallik, Arindam [Evanston, IL; Lin, Bin [Hillsboro, OR; Memik, Gokhan [Evanston, IL; Dinda, Peter [Evanston, IL; Dick, Robert [Evanston, IL

2011-03-22

Certain embodiments of the present invention provide a method for power management including determining at least one of an operating frequency and an operating voltage for a processor and configuring the processor based on the determined at least one of the operating frequency and the operating voltage. The operating frequency is determined based at least in part on direct user input. The operating voltage is determined based at least in part on an individual profile for processor.

Input-current shaped ac to dc converters

NASA Technical Reports Server (NTRS)

1986-01-01

The problem of achieving near unity power factor while supplying power to a dc load from a single phase ac source of power is examined. Power processors for this application must perform three functions: input current shaping, energy storage, and output voltage regulation. The methods available for performing each of these three functions are reviewed. Input current shaping methods are either active or passive, with the active methods divided into buck-like and boost-like techniques. In addition to large reactances, energy storage methods include resonant filters, active filters, and active storage schemes. Fast voltage regulation can be achieved by post regulation or by supplementing the current shaping topology with an extra switch. Some indications of which methods are best suited for particular applications concludes the discussion.

Background-free balanced optical cross correlator

DOEpatents

Nejadmalayeri, Amir Hossein; Kaertner, Franz X

2014-12-23

A balanced optical cross correlator includes an optical waveguide, a first photodiode including a first n-type semiconductor and a first p-type semiconductor positioned about the optical waveguide on a first side of the optical waveguide's point of symmetry, and a second photodiode including a second n-type semiconductor and a second p-type semiconductor positioned about the optical waveguide on a second side of the optical waveguide's point of symmetry. A balanced receiver including first and second inputs is configured to produce an output current or voltage that reflects a difference in currents or voltages, originating from the first and the second photodiodes of the balanced cross correlator and fed to the first input and to the second input of the balanced receiver.

Gas tube-switched high voltage DC power converter

DOEpatents

She, Xu; Bray, James William; Sommerer, Timothy John; Chokhawala, Rahul

2018-05-15

A direct current (DC)-DC converter includes a transformer and a gas tube-switched inverter circuit. The transformer includes a primary winding and a secondary winding. The gas tube-switched inverter circuit includes first and second inverter load terminals and first and second inverter input terminals. The first and second inverter load terminals are coupled to the primary winding. The first and second inverter input terminals are couplable to a DC node. The gas tube-switched inverter circuit further includes a plurality of gas tube switches respectively coupled between the first and second inverter load terminals and the first and second inverter input terminals. The plurality of gas tube switches is configured to operate to generate an alternating current (AC) voltage at the primary winding.

Power inverter with optical isolation

DOEpatents

Duncan, Paul G.; Schroeder, John Alan

2005-12-06

An optically isolated power electronic power conversion circuit that includes an input electrical power source, a heat pipe, a power electronic switch or plurality of interconnected power electronic switches, a mechanism for connecting the switch to the input power source, a mechanism for connecting comprising an interconnecting cable and/or bus bar or plurality of interconnecting cables and/or input bus bars, an optically isolated drive circuit connected to the switch, a heat sink assembly upon which the power electronic switch or switches is mounted, an output load, a mechanism for connecting the switch to the output load, the mechanism for connecting including an interconnecting cable and/or bus bar or plurality of interconnecting cables and/or output bus bars, at least one a fiber optic temperature sensor mounted on the heat sink assembly, at least one fiber optic current sensor mounted on the load interconnection cable and/or output bus bar, at least one fiber optic voltage sensor mounted on the load interconnection cable and/or output bus bar, at least one fiber optic current sensor mounted on the input power interconnection cable and/or input bus bar, and at least one fiber optic voltage sensor mounted on the input power interconnection cable and/or input bus bar.

Voltages induced on a power distribution line by overhead cloud lightning

NASA Technical Reports Server (NTRS)

Yacoub, Ziad; Rubinstein, Marcos; Uman, Martin A.; Thomson, Ewen M.; Medelius, Pedro J.

1991-01-01

Voltages induced by overhead cloud lightning on a 448 m open circuited power distribution line and the corresponding north-south component of the lightning magnetic field were simultaneously measured at the NASA Kennedy Space Center during the summer of 1986. The incident electric field was calculated from the measured magnetic field. The electric field was then used as an input to the computer program, EMPLIN, that calculated the voltages at the two ends of the power line. EMPLIN models the frequency domain field/power coupling theory found, for example, in Ianoz et al. The direction of the source, which is also one of the inputs to EMPLIN, was crudely determined from a three station time delay technique. The authors found reasonably good agreement between calculated and measured waveforms.

Heliocentric interplanetary low thrust trajectory optimization program, supplement 1, part 2

NASA Technical Reports Server (NTRS)

Mann, F. I.; Horsewood, J. L.

1978-01-01

The improvements made to the HILTOP electric propulsion trajectory computer program are described. A more realistic propulsion system model was implemented in which various thrust subsystem efficiencies and specific impulse are modeled as variable functions of power available to the propulsion system. The number of operating thrusters are staged, and the beam voltage is selected from a set of five (or less) constant voltages, based upon the application of variational calculus. The constant beam voltages may be optimized individually or collectively. The propulsion system logic is activated by a single program input key in such a manner as to preserve the HILTOP logic. An analysis describing these features, a complete description of program input quantities, and sample cases of computer output illustrating the program capabilities are presented.

ELECTRONIC TRIGGER CIRCUIT

DOEpatents

Russell, J.A.G.

1958-01-01

An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

Design, production, and testing of field effect transistors. [cryogenic MOSFETS

NASA Technical Reports Server (NTRS)

Sclar, N.

1982-01-01

Cryogenic MOSFETS (CRYOFETS), specifically designed for low temperature preamplifier application with infrared extrinsic detectors were produced and comparatively tested with p-channel MOSFETs under matched conditions. The CRYOFETs exhibit lower voltage thresholds, high source-follower gains at lower bias voltage, and lower dc offset source voltage. The noise of the CRYOFET is found to be 2 to 4 times greater than the MOSFET with a correspondingly lower figure of merit (which is established for source-follower amplifiers). The device power dissipation at a gain of 0.98 is some two orders of magnitude lower than for the MOSFET. Further, CRYOFETs are free of low temperature I vs V character hysteresis and balky conduction turn-on effects and operate effectively in the 2.4 to 20 K range. These devices have promise for use on long term duration sensor missions and for on-focal-plane signal processing at low temperatures.

An all digital phase locked loop for FM demodulation.

NASA Technical Reports Server (NTRS)

Greco, J.; Garodnick, J.; Schilling, D. L.

1972-01-01

A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously and performs all required digital calculations within one sampling period, thereby performing as a real-time special-purpose computer. The SNR ratio is computed for frequency offsets and sinusoidal modulation, and experimental results verify the theoretical calculations.

Electroluminescence property of organic light emitting diode (OLED)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Özdemir, Orhan; Kavak, Pelin; Saatci, A. Evrim

2013-12-16

Transport properties of electrons and holes were investigated not only in a anthracene-containing poly(p-phenylene-ethynylene)- alt - poly(p-phenylene-vinylene) (PPE-PPV) polymer (AnE-PVstat) light emitting diodes (OLED) but also in an ITO/Ag/polymer/Ag electron and ITO/PEDOT:PSS/polymer/Au hole only devices. Mobility of injected carriers followed the Poole-Frenkel type conduction mechanism and distinguished in the frequency range due to the difference of transit times in admittance measurement. Beginning of light output took place at the turn-on voltage (or flat band voltage), 1.8 V, which was the difference of energy band gap of polymer and two barrier offsets between metals and polymer.

A High Efficiency Boost Converter with MPPT Scheme for Low Voltage Thermoelectric Energy Harvesting

NASA Astrophysics Data System (ADS)

Guan, Mingjie; Wang, Kunpeng; Zhu, Qingyuan; Liao, Wei-Hsin

2016-11-01

Using thermoelectric elements to harvest energy from heat has been of great interest during the last decade. This paper presents a direct current-direct current (DC-DC) boost converter with a maximum power point tracking (MPPT) scheme for low input voltage thermoelectric energy harvesting applications. Zero current switch technique is applied in the proposed MPPT scheme. Theoretical analysis on the converter circuits is explored to derive the equations for parameters needed in the design of the boost converter. Simulations and experiments are carried out to verify the theoretical analysis and equations. A prototype of the designed converter is built using discrete components and a low-power microcontroller. The results show that the designed converter can achieve a high efficiency at low input voltage. The experimental efficiency of the designed converter is compared with a commercial converter solution. It is shown that the designed converter has a higher efficiency than the commercial solution in the considered voltage range.

An isolated bridgeless AC-DC PFC converter using a LC resonant voltage doubler rectifier

NASA Astrophysics Data System (ADS)

Lee, Sin-woo; Do, Hyun-Lark

2016-12-01

This paper proposed an isolated bridgeless AC-DC power factor correction (PFC) converter using a LC resonant voltage doubler rectifier. The proposed converter is based on isolated conventional single-ended primary inductance converter (SEPIC) PFC converter. The conduction loss of rectification is reduced than a conventional one because the proposed converter is designed to eliminate a full-bridge rectifier at an input stage. Moreover, for zero-current switching (ZCS) operation and low voltage stresses of output diodes, the secondary of the proposed converter is designed as voltage doubler with a LC resonant tank. Additionally, an input-output electrical isolation is provided for safety standard. In conclusion, high power factor is achieved and efficiency is improved. The operational principles, steady-state analysis and design equations of the proposed converter are described in detail. Experimental results from a 60 W prototype at a constant switching frequency 100 kHz are presented to verify the performance of the proposed converter.

Active Mechanisms of Vibration Encoding and Frequency Filtering in Central Mechanosensory Neurons.

PubMed

Azevedo, Anthony W; Wilson, Rachel I

2017-10-11

To better understand biophysical mechanisms of mechanosensory processing, we investigated two cell types in the Drosophila brain (A2 and B1 cells) that are postsynaptic to antennal vibration receptors. A2 cells receive excitatory synaptic currents in response to both directions of movement: thus, twice per vibration cycle. The membrane acts as a low-pass filter, so that voltage and spiking mainly track the vibration envelope rather than individual cycles. By contrast, B1 cells are excited by only forward or backward movement, meaning they are sensitive to vibration phase. They receive oscillatory synaptic currents at the stimulus frequency, and they bandpass filter these inputs to favor specific frequencies. Different cells prefer different frequencies, due to differences in their voltage-gated conductances. Both Na + and K + conductances suppress low-frequency synaptic inputs, so cells with larger voltage-gated conductances prefer higher frequencies. These results illustrate how membrane properties and voltage-gated conductances can extract distinct stimulus features into parallel channels. Copyright © 2017 Elsevier Inc. All rights reserved.

High-Voltage-Input Level Translator Using Standard CMOS

NASA Technical Reports Server (NTRS)

Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

2011-01-01

proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

NASA Astrophysics Data System (ADS)

Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

2017-09-01

Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Rapid disinhibition by adjustment of PV intrinsic excitability during whisker map plasticity in mouse S1.

PubMed

Gainey, Melanie A; Aman, Joseph W; Feldman, Daniel E

2018-04-20

Rapid plasticity of layer (L) 2/3 inhibitory circuits is an early step in sensory cortical map plasticity, but its cellular basis is unclear. We show that, in mice of either sex, 1 day whisker deprivation drives rapid loss of L4-evoked feedforward inhibition and more modest loss of feedforward excitation in L2/3 pyramidal (PYR) cells, increasing E-I conductance ratio. Rapid disinhibition was due to reduced L4-evoked spiking by L2/3 parvalbumin (PV) interneurons, caused by reduced PV intrinsic excitability. This included elevated PV spike threshold, associated with an increase in low-threshold, voltage activated delayed rectifier (presumed Kv1) and A-type potassium currents. Excitatory synaptic input and unitary inhibitory output of PV cells were unaffected. Functionally, the loss of feedforward inhibition and excitation were precisely coordinated in L2/3 PYR cells, so that peak feedforward synaptic depolarization remained stable. Thus, rapid plasticity of PV intrinsic excitability offsets early weakening of excitatory circuits to homeostatically stabilize synaptic potentials in PYR cells of sensory cortex. SIGNIFICANCE STATEMENT Inhibitory circuits in cerebral cortex are highly plastic, but the cellular mechanisms and functional importance of this plasticity are incompletely understood. We show that brief (1-day) sensory deprivation rapidly weakens parvalbumin (PV) inhibitory circuits by reducing the intrinsic excitability of PV neurons. This involved a rapid increase in voltage-gated potassium conductances that control near-threshold spiking excitability. Functionally, the loss of PV-mediated feedforward inhibition in L2/3 pyramidal cells was precisely balanced with the separate loss of feedforward excitation, resulting in a net homeostatic stabilization of synaptic potentials. Thus, rapid plasticity of PV intrinsic excitability implements network-level homeostasis to stabilize synaptic potentials in sensory cortex. Copyright © 2018 the authors.

Limit circuit prevents overdriving of operational amplifier

NASA Technical Reports Server (NTRS)

Openshaw, F. L.

1967-01-01

Cutoff-type high gain amplifier coupled by a diode prevents overdriving of operational amplifier. An amplified feedback signal offsets the excess input signal that tends to cause the amplifier to exceed its preset limit. The output is, therfore, held to the set clamp level.

Activation of Ih and TTX-sensitive sodium current at subthreshold voltages during CA1 pyramidal neuron firing

PubMed Central

Yamada-Hanff, Jason

2015-01-01

We used dynamic clamp and action potential clamp techniques to explore how currents carried by tetrodotoxin-sensitive sodium channels and HCN channels (Ih) regulate the behavior of CA1 pyramidal neurons at resting and subthreshold voltages. Recording from rat CA1 pyramidal neurons in hippocampal slices, we found that the apparent input resistance and membrane time constant were strongly affected by both conductances, with Ih acting to decrease apparent input resistance and time constant and sodium current acting to increase both. We found that both Ih and sodium current were active during subthreshold summation of artificial excitatory postsynaptic potentials (EPSPs) generated by dynamic clamp, with Ih dominating at less depolarized voltages and sodium current at more depolarized voltages. Subthreshold sodium current—which amplifies EPSPs—was most effectively recruited by rapid voltage changes, while Ih—which blunts EPSPs—was maximal for slow voltage changes. The combined effect is to selectively amplify rapid EPSPs. We did similar experiments in mouse CA1 pyramidal neurons, doing voltage-clamp experiments using experimental records of action potential firing of CA1 neurons previously recorded in awake, behaving animals as command voltages to quantify flow of Ih and sodium current at subthreshold voltages. Subthreshold sodium current was larger and subthreshold Ih was smaller in mouse neurons than in rat neurons. Overall, the results show opposing effects of subthreshold sodium current and Ih in regulating subthreshold behavior of CA1 neurons, with subthreshold sodium current prominent in both rat and mouse CA1 pyramidal neurons and additional regulation by Ih in rat neurons. PMID:26289465

Assumption or Fact? Line-to-Neutral Voltage Expression in an Unbalanced 3-Phase Circuit during Inverter Switching

ERIC Educational Resources Information Center

Masrur, M. A.

2009-01-01

This paper discusses the situation in a 3-phase motor or any other 3-phase system operating under unbalanced operating conditions caused by an open fault in an inverter switch. A dc voltage source is assumed as the input to the inverter, and under faulty conditions of the inverter switch, the actual voltage applied between the line to neutral…

Parametric study of electromagnetic waves propagating in absorbing curved S ducts

NASA Technical Reports Server (NTRS)

Baumeister, Kenneth J.

1989-01-01

A finite-element Galerkin formulation has been developed to study attenuation of transverse magnetic (TM) waves propagating in two-dimensional S-curved ducts with absorbing walls. In the frequency range where the duct diameter and electromagnetic wave length are nearly equal, the effect of duct length, curvature (duct offset), and absorber wall thickness was examined. For a given offset in the curved duct, the length of the S-duct was found to significantly affect both the absorptive and reflective characteristics of the duct. For a straight and a curved duct with perfect electric conductor terminations, power attenuation contours were examined to determine electromagnetic wall properties associated with maximum input signal absorption. Offset of the S-duct was found to significantly affect the value of the wall permittivity associated with the optimal attenuation of the incident electromagnetic wave.

Ground potential rise monitor

DOEpatents

Allen, Zachery W [Mandan, ND; Zevenbergen, Gary A [Arvada, CO

2012-04-03

A device and method for detecting ground potential rise (GPR) comprising positioning a first electrode and a second electrode at a distance from each other into the earth. The voltage of the first electrode and second electrode is attenuated by an attenuation factor creating an attenuated voltage. The true RMS voltage of the attenuated voltage is determined creating an attenuated true RMS voltage. The attenuated true RMS voltage is then multiplied by the attenuation factor creating a calculated true RMS voltage. If the calculated true RMS voltage is greater than a first predetermined voltage threshold, a first alarm is enabled at a local location. If user input is received at a remote location acknowledging the first alarm, a first alarm acknowledgment signal is transmitted. The first alarm acknowledgment signal is then received at which time the first alarm is disabled.

Sliding-mode control of single input multiple output DC-DC converter

NASA Astrophysics Data System (ADS)

Zhang, Libo; Sun, Yihan; Luo, Tiejian; Wan, Qiyang

2016-10-01

Various voltage levels are required in the vehicle mounted power system. A conventional solution is to utilize an independent multiple output DC-DC converter whose cost is high and control scheme is complicated. In this paper, we design a novel SIMO DC-DC converter with sliding mode controller. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage DC bus and middle-voltage output terminals, which endow the converter with characteristics of simple structure, low cost, and convenient control. In addition, the sliding mode control (SMC) technique applied in our converter can enhance the performances of a certain SIMO DC-DC converter topology. The high-voltage DC bus can be regarded as the main power source to the high-voltage facility of the vehicle mounted power system, and the middle-voltage output terminals can supply power to the low-voltage equipment on an automobile. In the respect of control algorithm, it is the first time to propose the SMC-PID (Proportion Integration Differentiation) control algorithm, in which the SMC algorithm is utilized and the PID control is attended to the conventional SMC algorithm. The PID control increases the dynamic ability of the SMC algorithm by establishing the corresponding SMC surface and introducing the attached integral of voltage error, which endow the sliding-control system with excellent dynamic performance. At last, we established the MATLAB/SIMULINK simulation model, tested performance of the system, and built the hardware prototype based on Digital Signal Processor (DSP). Results show that the sliding mode control is able to track a required trajectory, which has robustness against the uncertainties and disturbances.

Sliding-mode control of single input multiple output DC-DC converter.

PubMed

Zhang, Libo; Sun, Yihan; Luo, Tiejian; Wan, Qiyang

2016-10-01

Various voltage levels are required in the vehicle mounted power system. A conventional solution is to utilize an independent multiple output DC-DC converter whose cost is high and control scheme is complicated. In this paper, we design a novel SIMO DC-DC converter with sliding mode controller. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage DC bus and middle-voltage output terminals, which endow the converter with characteristics of simple structure, low cost, and convenient control. In addition, the sliding mode control (SMC) technique applied in our converter can enhance the performances of a certain SIMO DC-DC converter topology. The high-voltage DC bus can be regarded as the main power source to the high-voltage facility of the vehicle mounted power system, and the middle-voltage output terminals can supply power to the low-voltage equipment on an automobile. In the respect of control algorithm, it is the first time to propose the SMC-PID (Proportion Integration Differentiation) control algorithm, in which the SMC algorithm is utilized and the PID control is attended to the conventional SMC algorithm. The PID control increases the dynamic ability of the SMC algorithm by establishing the corresponding SMC surface and introducing the attached integral of voltage error, which endow the sliding-control system with excellent dynamic performance. At last, we established the MATLAB/SIMULINK simulation model, tested performance of the system, and built the hardware prototype based on Digital Signal Processor (DSP). Results show that the sliding mode control is able to track a required trajectory, which has robustness against the uncertainties and disturbances.

System and method for determining stator winding resistance in an AC motor

DOEpatents

Lu, Bin [Kenosha, WI; Habetler, Thomas G [Snellville, GA; Zhang, Pinjia [Atlanta, GA; Theisen, Peter J [West Bend, WI

2011-05-31

A system and method for determining stator winding resistance in an AC motor is disclosed. The system includes a circuit having an input connectable to an AC source and an output connectable to an input terminal of an AC motor. The circuit includes at least one contactor and at least one switch to control current flow and terminal voltages in the AC motor. The system also includes a controller connected to the circuit and configured to modify a switching time of the at least one switch to create a DC component in an output of the system corresponding to an input to the AC motor and determine a stator winding resistance of the AC motor based on the injected DC component of the voltage and current.

Low-noise pulse conditioner

DOEpatents

Bird, David A.

1983-01-01

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits.

Frequency tuning of synaptic inhibition underlying duration-tuned neurons in the mammalian inferior colliculus

PubMed Central

Valdizón-Rodríguez, Roberto

2017-01-01

Inhibition plays an important role in creating the temporal response properties of duration-tuned neurons (DTNs) in the mammalian inferior colliculus (IC). Neurophysiological and computational studies indicate that duration selectivity in the IC is created through the convergence of excitatory and inhibitory synaptic inputs offset in time. We used paired-tone stimulation and extracellular recording to measure the frequency tuning of the inhibition acting on DTNs in the IC of the big brown bat (Eptesicus fuscus). We stimulated DTNs with pairs of tones differing in duration, onset time, and frequency. The onset time of a short, best-duration (BD), probe tone set to the best excitatory frequency (BEF) was varied relative to the onset of a longer-duration, nonexcitatory (NE) tone whose frequency was varied. When the NE tone frequency was near or within the cell’s excitatory bandwidth (eBW), BD tone-evoked spikes were suppressed by an onset-evoked inhibition. The onset of the spike suppression was independent of stimulus frequency, but both the offset and duration of the suppression decreased as the NE tone frequency departed from the BEF. We measured the inhibitory frequency response area, best inhibitory frequency (BIF), and inhibitory bandwidth (iBW) of each cell. We found that the BIF closely matched the BEF, but the iBW was broader and usually overlapped the eBW measured from the same cell. These data suggest that temporal selectivity of midbrain DTNs is created and preserved by having cells receive an onset-evoked, constant-latency, broadband inhibition that largely overlaps the cell’s excitatory receptive field. We conclude by discussing possible neural sources of the inhibition. NEW & NOTEWORTHY Duration-tuned neurons (DTNs) arise from temporally offset excitatory and inhibitory synaptic inputs. We used single-unit recording and paired-tone stimulation to measure the spectral tuning of the inhibitory inputs to DTNs. The onset of inhibition was independent of stimulus frequency; the offset and duration of inhibition systematically decreased as the stimulus departed from the cell’s best excitatory frequency. Best inhibitory frequencies matched best excitatory frequencies; however, inhibitory bandwidths were more broadly tuned than excitatory bandwidths. PMID:28100657

Programmable Multiple-Ramped-Voltage Power Supply

NASA Technical Reports Server (NTRS)

Ajello, Joseph M.; Howell, S. K.

1993-01-01

Ramp waveforms range up to 2,000 V. Laboratory high-voltage power-supply system puts out variety of stable voltages programmed to remain fixed with respect to ground or float with respect to ramp waveform. Measures voltages it produces with high resolution; automatically calibrates, zeroes, and configures itself; and produces variety of input/output signals for use with other instruments. Developed for use with ultraviolet spectrometer. Also applicable to control of electron guns in general and to operation of such diverse equipment used in measuring scattering cross sections of subatomic particles and in industrial electron-beam welders.

Switching Characteristics of Ferroelectric Transistor Inverters

NASA Technical Reports Server (NTRS)

Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

2010-01-01

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Charge control microcomputer device for vehicles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morishita, M.; Kouge, S.

1986-10-14

This patent describes a charge control microcomputer device for a vehicle, comprising: speed changing means for transmitting the output torque of an engine. The speed changing means includes a slip clutch means having an output with a variable slippage amount with respect to its input and controlled in accordance with an operating instruction. The speed changing means further includes a speed change gear for changing the rotational speed input thereto at an output thereto, the speed change gear receiving the output of the slip clutch means; a charging generator driven by the output of the speed change gear; a batterymore » charged by an output voltage of the charging generator; a voltage regulator for controlling the output voltage of the charging generator to a predetermined value; an engine controlling microcomputer for receiving data from the engine, to control the engine, the engine data comprising at least an engine speed signal; a charge control microcomputer for processing engine data from the engine controlling microcomputer and charge system data including terminal voltage data from the battery and generated voltage data from the changing generator; and a display unit for displaying detection data, including fault detection data, form the charge control microcomputer.« less

77 FR 13270 - Stainless Steel Bar From India: Preliminary Results and Partial Rescission of the Antidumping...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-06

... standard input-output norm (SION) for the exported product. DEPS credits can be used for any subsequent... section 773(a)(6)(C) of the Act for home market credit expenses (offset by interest revenue). We capped...

Thermal Aspects of Lithium-Ion Cells

NASA Technical Reports Server (NTRS)

Frank, H.; Shakkottai, P.; Ratnakumar, B. V.; Smart, M. C.; Huang, C. K.; Timmerman, P.; Surampudi, S.

2000-01-01

Objective of this investigation is to provide the necessary inputs for a thermal model of the Li-ion battery for the Mars 2001 Lander. Two alternate configurations of this battery are under development: a) prismatic parallel plate, and b) cylindrical spiral wound. Required thermal inputs for both consist of the following: a) heat generation rates, b) thermal mass, and c) thermal conductivity. Thermal mass and conductivity were computed on the basis of known properties and configuration of the cell components. The heat generation rates were taken as the product of current and difference between open circuit voltage (OCV) and operating voltages (CCV) at a given state-of charge (SOC). Herein, it was assumed that the enthalpy voltage was equal to the OCV. OCV vs SOC data were obtained experimentally and CCV vs SOC were taken from previously obtained discharge data.

A radial transmission line material measurement apparatus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warne, L.K.; Moyer, R.D.; Koontz, T.E.

1993-05-01

A radial transmission line material measurement sample apparatus (sample holder, offset short standards, measurement software, and instrumentation) is described which has been proposed, analyzed, designed, constructed, and tested. The purpose of the apparatus is to obtain accurate surface impedance measurements of lossy, possibly anisotropic, samples at low and intermediate frequencies (vhf and low uhf). The samples typically take the form of sections of the material coatings on conducting objects. Such measurements thus provide the key input data for predictive numerical scattering codes. Prediction of the sample surface impedance from the coaxial input impedance measurement is carried out by two techniques.more » The first is an analytical model for the coaxial-to-radial transmission line junction. The second is an empirical determination of the bilinear transformation model of the junction by the measurement of three full standards. The standards take the form of three offset shorts (and an additional lossy Salisbury load), which have also been constructed. The accuracy achievable with the device appears to be near one percent.« less

Basic Investigations of Dynamic Travel Time Estimation Model for Traffic Signals Control Using Information from Optical Beacons

NASA Astrophysics Data System (ADS)

Okutani, Iwao; Mitsui, Tatsuro; Nakada, Yusuke

In this paper put forward are neuron-type models, i.e., neural network model, wavelet neuron model and three layered wavelet neuron model(WV3), for estimating traveling time between signalized intersections in order to facilitate adaptive setting of traffic signal parameters such as green time and offset. Model validation tests using simulated data reveal that compared to other models, WV3 model works very fast in learning process and can produce more accurate estimates of travel time. Also, it is exhibited that up-link information obtainable from optical beacons, i.e., travel time observed during the former cycle time in this case, makes a crucial input variable to the models in that there isn't any substantial difference between the change of estimated and simulated travel time with the change of green time or offset when up-link information is employed as input while there appears big discrepancy between them when not employed.

Hybrid circuit achieves pulse regeneration with low power drain

NASA Technical Reports Server (NTRS)

Cancro, C. A.

1965-01-01

Hybrid tunnel diode-transistor circuit provides a solid-state, low power drain pulse regenerator, frequency limiter, or gated oscillator. When the feedback voltage exceeds the input voltage, the circuit functions as a pulse normalizer or a frequency limiter. If the circuit is direct coupled, it functions as a gated oscillator.

Time Triggered Ethernet System Testing Means and Method

NASA Technical Reports Server (NTRS)

Smithgall, William Todd (Inventor); Hall, Brendan (Inventor); Varadarajan, Srivatsan (Inventor)

2014-01-01

Methods and apparatus are provided for evaluating the performance of a Time Triggered Ethernet (TTE) system employing Time Triggered (TT) communication. A real TTE system under test (SUT) having real input elements communicating using TT messages with output elements via one or more first TTE switches during a first time interval schedule established for the SUT. A simulation system is also provided having input simulators that communicate using TT messages via one or more second TTE switches with the same output elements during a second time interval schedule established for the simulation system. The first and second time interval schedules are off-set slightly so that messages from the input simulators, when present, arrive at the output elements prior to messages from the analogous real inputs, thereby having priority over messages from the real inputs and causing the system to operate based on the simulated inputs when present.

VOLTAGE REGULATOR

DOEpatents

Von Eschen, R.L.; Scheele, P.F.

1962-04-24

A transistorized voltage regulator which provides very close voitage regulation up to about 180 deg F is described. A diode in the positive line provides a constant voltage drop from the input to a regulating transistor emitter. An amplifier is coupled to the positive line through a resistor and is connected between a difference circuit and the regulating transistor base which is negative due to the difference in voltage drop across thc diode and the resistor so that a change in the regulator output causes the amplifier to increase or decrease the base voltage and current and incrcase or decrease the transistor impedance to return the regulator output to normal. (AEC)

Bilateral comparison of 10 V standards between the NSAI-NML (Ireland) and the BIPM, February to March 2012 (part of the ongoing BIPM key comparison BIPM.EM-K11.b)

NASA Astrophysics Data System (ADS)

Power, O.; Solve, S.; Chayramy, R.; Stock, M.

2012-01-01

As part of the on-going BIPM key comparison BIPM.EM-K11.b, a comparison of the 10 V voltage reference standards of the BIPM and the National Standards Authority of Ireland-National Metrology Laboratory (NSAI-NML), Dublin, Ireland, was carried out from February to March 2012. Two BIPM Zener diode-based travelling standards (Fluke 732B), BIPM_C (ZC) and BIPM_D (ZD), were transported by freight to NSAI-NML. At NSAI-NML, the reference standard for DC voltage at the 10 V level consists of a group of characterized Zener diode-based electronic voltage standards. The output EMF (electromotive force) of each travelling standard was measured by direct comparison with the group standard. At the BIPM the travelling standards were calibrated, before and after the measurements at NSAI-NML, with the Josephson voltage standard. Results of all measurements were corrected for the dependence of the output voltages on internal temperature and ambient atmospheric pressure. The final result of the comparison is presented as the difference between the value assigned to DC voltage standard by NSAI-NML, at the level of 10 V, at NSAI-NML, UNML, and that assigned by the BIPM, at the BIPM, UBIPM, at the reference date of 23 February 2012. UNML - UBIPM = +0.83 µV, uc = 1.35 µV, at 10 V where uc is the combined standard uncertainty associated with the measured difference, including the uncertainty of the representation of the volt at the BIPM and at NSAI-NML, based on KJ-90, and the uncertainty related to the comparison. The final result is impacted by the anomalous offset between the NSAI-NML results for the two transfer standards. The reason for this offset hasn't been determined. However, the difference remains within the total combined standard uncertainty. Therefore, the comparison result shows that the voltage standards maintained by NSAI-NML and the BIPM were equivalent, within their stated expanded uncertainties, on the mean date of the comparison. Main text. To reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/. The final report has been peer-reviewed and approved for publication by the CCEM, according to the provisions of the CIPM Mutual Recognition Arrangement (CIPM MRA).

Switched integration amplifier-based photocurrent meter for accurate spectral responsivity measurement of photometers.

PubMed

Park, Seongchong; Hong, Kee-Suk; Kim, Wan-Seop

2016-03-20

This work introduces a switched integration amplifier (SIA)-based photocurrent meter for femtoampere (fA)-level current measurement, which enables us to measure a 10⁷ dynamic range of spectral responsivity of photometers even with a common lamp-based monochromatic light source. We described design considerations and practices about operational amplifiers (op-amps), switches, readout methods, etc., to compose a stable SIA of low offset current in terms of leakage current and gain peaking in detail. According to the design, we made six SIAs of different integration capacitance and different op-amps and evaluated their offset currents. They showed an offset current of (1.5-85) fA with a slow variation of (0.5-10) fA for an hour under opened input. Applying a detector to the SIA input, the offset current and its variation were increased and the SIA readout became noisier due to finite shunt resistance and nonzero shunt capacitance of the detector. One of the SIAs with 10 pF nominal capacitance was calibrated using a calibrated current source at the current level of 10 nA to 1 fA and at the integration time of 2 to 65,536 ms. As a result, we obtained a calibration formula for integration capacitance as a function of integration time rather than a single capacitance value because the SIA readout showed a distinct dependence on integration time at a given current level. Finally, we applied it to spectral responsivity measurement of a photometer. It is demonstrated that the home-made SIA of 10 pF was capable of measuring a 10⁷ dynamic range of spectral responsivity of a photometer.

Studies on Radar Sensor Networks

DTIC Science & Technology

2007-08-08

scheme in which 2-D image was created via adding voltages with the appropriate time offset. Simulation results show that our DCT-based scheme works...using RSNs in terms of the probability of miss detection PMD and the root mean square error (RMSE). Simulation results showed that multi-target detection... Simulation results are presented to evaluate the feasibility and effectiveness of the proposed JMIC algorithm in a query surveillance region. 5 SVD-QR and

Acoustic performance of dual-electrode electrostatic sound generators based on CVD graphene on polyimide film.

PubMed

Lee, Kyoung-Ryul; Jang, Sung Hwan; Jung, Inhwa

2018-08-10

We investigated the acoustic performance of electrostatic sound-generating devices consisting of bi-layer graphene on polyimide film. The total sound pressure level (SPL) of the sound generated from the devices was measured as a function of source frequency by sweeping, and frequency spectra were measured at 1/3 octave band frequencies. The relationship between various operation conditions and total SPL was determined. In addition, the effects of changing voltage level, adding a DC offset, and using two pairs of electrodes were evaluated. It should be noted that two pairs of electrode operations improved sound generation by about 10 dB over all frequency ranges compared with conventional operation. As for the sound-generating capability, total SPL was 70 dBA at 4 kHz when an AC voltage of 100 V pp was applied with a DC offset of 100 V. Acoustic characteristics differed from other types of graphene-based sound generators, such as graphene thermoacoustic devices and graphene polyvinylidene fluoride devices. The effects of diameter and distance between electrodes were also studied, and we found that diameter greatly influenced the frequency response. We anticipate that the design information provided in this paper, in addition to describing key parameters of electrostatic sound-generating devices, will facilitate the commercial development of electrostatic sound-generating systems.

An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

NASA Astrophysics Data System (ADS)

Chen, Hsin-Han; Hsieh, Chih-Cheng

2013-09-01

This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

Low-noise sub-harmonic injection locked multiloop ring oscillator

NASA Astrophysics Data System (ADS)

Weilin, Xu; Di, Wu; Xueming, Wei; Baolin, Wei; Jihai, Duan; Fadi, Gui

2016-09-01

A three-stage differential voltage-controlled ring oscillator is presented for wide-tuning and low-phase noise requirement of clock and data recovery circuit in ultra wideband (UWB) wireless body area network. To improve the performance of phase noise of delay cell with coarse and fine frequency tuning, injection locked technology together with pseudo differential architecture are adopted. In addition, a multiloop is employed for frequency boosting. Two RVCOs, the standard RVCO without the IL block and the proposed IL RVCO, were fabricated in SMIC 0.18 μm 1P6M Salicide CMOS process. The proposed IL RVCO exhibits a measured phase noise of -112.37 dBc/Hz at 1 MHz offset from the center frequency of 1 GHz, while dissipating a current of 8 mA excluding the buffer from a 1.8-V supply voltage. It shows a 16.07 dB phase noise improvement at 1 MHz offset compared to the standard topology. Project supported by the National Natural Science Foundation of China (No. 61264001), the Guangxi Natural Science Foundation (Nos. 2013GXNSFAA019333, 2015GXNSFAA139301, 2014GXNSFAA118386), the Graduate Education Innovation Program of GUET (No. GDYCSZ201457), the Project of Guangxi Education Department (No. LD14066B) and the High-Level-Innovation Team and Outstanding Scholar Project of Guangxi Higher Education Institutes.

Resistive Switching in All-Printed, Flexible and Hybrid MoS2-PVA Nanocomposite based Memristive Device Fabricated by Reverse Offset

PubMed Central

Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Gul, Jahan Zeb; Kim, Soo-Wan; Lim, Jong Hwan; Choi, Kyung Hyun

2016-01-01

Owing to the increasing interest in the nonvolatile memory devices, resistive switching based on hybrid nanocomposite of a 2D material, molybdenum disulphide (MoS2) and polyvinyl alcohol (PVA) is explored in this work. As a proof of concept, we have demonstrated the fabrication of a memory device with the configuration of PET/Ag/MoS2-PVA/Ag via an all printed, hybrid, and state of the art fabrication approach. Bottom Ag electrodes, active layer of hybrid MoS2-PVA nanocomposite and top Ag electrode are deposited by reverse offset, electrohydrodynamic (EHD) atomization and electrohydrodynamic (EHD) patterning respectively. The fabricated device displayed characteristic bistable, nonvolatile and rewritable resistive switching behavior at a low operating voltage. A decent off/on ratio, high retention time, and large endurance of 1.28 × 102, 105 sec and 1000 voltage sweeps were recorded respectively. Double logarithmic curve satisfy the trap controlled space charge limited current (TCSCLC) model in high resistance state (HRS) and ohmic model in low resistance state (LRS). Bendability test at various bending diameters (50-2 mm) for 1500 cycles was carried out to show the mechanical robustness of fabricated device. PMID:27811977

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

NASA Technical Reports Server (NTRS)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

Solid-state repetitive generator with a gyromagnetic nonlinear transmission line operating as a peak power amplifier

NASA Astrophysics Data System (ADS)

Gusev, A. I.; Pedos, M. S.; Rukin, S. N.; Timoshenkov, S. P.

2017-07-01

In this work, experiments were made in which gyromagnetic nonlinear transmission line (NLTL) operates as a peak power amplifier of the input pulse. At such an operating regime, the duration of the input pulse is close to the period of generated oscillations, and the main part of the input pulse energy is transmitted only to the first peak of the oscillations. Power amplification is achieved due to the voltage amplitude of the first peak across the NLTL output exceeding the voltage amplitude of the input pulse. In the experiments, the input pulse with an amplitude of 500 kV and a half-height pulse duration of 7 ns is applied to the NLTL with a natural oscillation frequency of ˜300 MHz. At the output of the NLTL in 40 Ω coaxial transmission line, the pulse amplitude is increased to 740 kV and the pulse duration is reduced to ˜2 ns, which correspond to power amplification of the input pulse from ˜6 to ˜13 GW. As a source of input pulses, a solid-state semiconductor opening switch generator was used, which allowed carrying out experiments at pulse repetition frequency up to 1 kHz in the burst mode of operation.

[Development of residual voltage testing equipment].

PubMed

Zeng, Xiaohui; Wu, Mingjun; Cao, Li; He, Jinyi; Deng, Zhensheng

2014-07-01

For the existing measurement methods of residual voltage which can't turn the power off at peak voltage exactly and simultaneously display waveforms, a new residual voltage detection method is put forward in this paper. First, the zero point of the power supply is detected with zero cross detection circuit and is inputted to a single-chip microcomputer in the form of pulse signal. Secend, when the zero point delays to the peak voltage, the single-chip microcomputer sends control signal to power off the relay. At last, the waveform of the residual voltage is displayed on a principal computer or oscilloscope. The experimental results show that the device designed in this paper can turn the power off at peak voltage and is able to accurately display the voltage waveform immediately after power off and the standard deviation of the residual voltage is less than 0.2 V at exactly one second and later.

RF rectifiers for EM power harvesting in a Deep Brain Stimulating device.

PubMed

Hosain, Md Kamal; Kouzani, Abbas Z; Tye, Susannah; Kaynak, Akif; Berk, Michael

2015-03-01

A passive deep brain stimulation (DBS) device can be equipped with a rectenna, consisting of an antenna and a rectifier, to harvest energy from electromagnetic fields for its operation. This paper presents optimization of radio frequency rectifier circuits for wireless energy harvesting in a passive head-mountable DBS device. The aim is to achieve a compact size, high conversion efficiency, and high output voltage rectifier. Four different rectifiers based on the Delon doubler, Greinacher voltage tripler, Delon voltage quadrupler, and 2-stage charge pumped architectures are designed, simulated, fabricated, and evaluated. The design and simulation are conducted using Agilent Genesys at operating frequency of 915 MHz. A dielectric substrate of FR-4 with thickness of 1.6 mm, and surface mount devices (SMD) components are used to fabricate the designed rectifiers. The performance of the fabricated rectifiers is evaluated using a 915 MHz radio frequency (RF) energy source. The maximum measured conversion efficiency of the Delon doubler, Greinacher tripler, Delon quadrupler, and 2-stage charge pumped rectifiers are 78, 75, 73, and 76 % at -5 dBm input power and for load resistances of 5-15 kΩ. The conversion efficiency of the rectifiers decreases significantly with the increase in the input power level. The Delon doubler rectifier provides the highest efficiency at both -5 and 5 dBm input power levels, whereas the Delon quadrupler rectifier gives the lowest efficiency for the same inputs. By considering both efficiency and DC output voltage, the charge pump rectifier outperforms the other three rectifiers. Accordingly, the optimised 2-stage charge pumped rectifier is used together with an antenna to harvest energy in our DBS device.

Two new families of high-gain dc-dc power electronic converters for dc-microgrids

NASA Astrophysics Data System (ADS)

Prabhala, Venkata Anand Kishore

Distributing the electric power in dc form is an appealing solution in many applications such as telecommunications, data centers, commercial buildings, and microgrids. A high gain dc-dc power electronic converter can be used to individually link low-voltage elements such as solar panels, fuel cells, and batteries to the dc voltage bus which is usually 400 volts. This way, it is not required to put such elements in a series string to build up their voltages. Consequently, each element can function at it optimal operating point regardless of the other elements in the system. In this dissertation, first a comparative study of dc microgrid architectures and their advantages over their ac counterparts is presented. Voltage level selection of dc distribution systems is discussed from the cost, reliability, efficiency, and safety standpoints. Next, a new family of non-isolated high-voltage-gain dc-dc power electronic converters with unidirectional power flow is introduced. This family of converters benefits from a low voltage stress across its switches. The proposed topologies are versatile as they can be utilized as single-input or double-input power converters. In either case, they draw continuous currents from their sources. Lastly, a bidirectional high-voltage-gain dc-dc power electronic converter is proposed. This converter is comprised of a bidirectional boost converter which feeds a switched-capacitor architecture. The switched-capacitor stage suggested here has several advantages over the existing approaches. For example, it benefits from a higher voltage gain while it uses less number of capacitors. The proposed converters are highly efficient and modular. The operating modes, dc voltage gain, and design procedure for each converter are discussed in details. Hardware prototypes have been developed in the lab. The results obtained from the hardware agree with those of the simulation models.

Performances estimation of a rotary traveling wave ultrasonic motor based on two-dimension analytical model.

PubMed

Ming, Y; Peiwen, Q

2001-03-01

The understanding of ultrasonic motor performances as a function of input parameters, such as the voltage amplitude, driving frequency, the preload on the rotor, is a key to many applications and control of ultrasonic motor. This paper presents performances estimation of the piezoelectric rotary traveling wave ultrasonic motor as a function of input voltage amplitude and driving frequency and preload. The Love equation is used to derive the traveling wave amplitude on the stator surface. With the contact model of the distributed spring-rigid body between the stator and rotor, a two-dimension analytical model of the rotary traveling wave ultrasonic motor is constructed. Then the performances of stead rotation speed and stall torque are deduced. With MATLAB computational language and iteration algorithm, we estimate the performances of rotation speed and stall torque versus input parameters respectively. The same experiments are completed with the optoelectronic tachometer and stand weight. Both estimation and experiment results reveal the pattern of performance variation as a function of its input parameters.

Democracy-independence trade-off in oscillating dendrites and its implications for grid cells.

PubMed

Remme, Michiel W H; Lengyel, Máté; Gutkin, Boris S

2010-05-13

Dendritic democracy and independence have been characterized for near-instantaneous processing of synaptic inputs. However, a wide class of neuronal computations requires input integration on long timescales. As a paradigmatic example, entorhinal grid fields have been thought to be generated by the democratic summation of independent dendritic oscillations performing direction-selective path integration. We analyzed how multiple dendritic oscillators embedded in the same neuron integrate inputs separately and determine somatic membrane voltage jointly. We found that the interaction of dendritic oscillations leads to phase locking, which sets an upper limit on the timescale for independent input integration. Factors that increase this timescale also decrease the influence that the dendritic oscillations exert on somatic voltage. In entorhinal stellate cells, interdendritic coupling dominates and causes these cells to act as single oscillators. Our results suggest a fundamental trade-off between local and global processing in dendritic trees integrating ongoing signals. Copyright 2010 Elsevier Inc. All rights reserved.

Complementary Paired G4FETs as Voltage-Controlled NDR Device

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Chen, Suheng; Blalock, Ben; Britton, Chuck; Prothro, Ben; Vandersand, James; Schrimph, Ron; Cristoloveanu, Sorin; Akavardar, Kerem; Gentil, P.

2009-01-01

It is possible to synthesize a voltage-controlled negative-differential-resistance (NDR) device or circuit by use of a pair of complementary G4FETs (four-gate field-effect transistors). [For more information about G4FETs, please see the immediately preceding article]. As shown in Figure 1, the present voltage-controlled NDR device or circuit is an updated version of a prior NDR device or circuit, known as a lambda diode, that contains a pair of complementary junction field-effect transistors (JFETs). (The lambda diode is so named because its current-versus- voltage plot bears some resemblance to an upper-case lambda.) The present version can be derived from the prior version by substituting G4FETs for the JFETs and connecting both JFET gates of each G4FET together. The front gate terminals of the G4FETs constitute additional terminals (that is, terminals not available in the older JFET version) to which one can apply control voltages VN and VP. Circuits in which NDR devices have been used include (1) Schmitt triggers and (2) oscillators containing inductance/ capacitance (LC) resonant circuits. Figure 2 depicts such circuits containing G4FET NDR devices like that of Figure 1. In the Schmitt trigger shown here, the G4FET NDR is loaded with an ordinary inversion-mode, p-channel, metal oxide/semiconductor field-effect transistor (inversion-mode PMOSFET), the VN terminal of the G4FET NDR device is used as an input terminal, and the input terminals of the PMOSFET and the G4FET NDR device are connected. VP can be used as an extra control voltage (that is, a control voltage not available in a typical prior Schmitt trigger) for adjusting the pinch-off voltage of the p-channel G4FET and thereby adjusting the trigger-voltage window. In the oscillator, a G4FET NDR device is loaded with a conventional LC tank circuit. As in other LC NDR oscillators, oscillation occurs because the NDR counteracts the resistance in the tank circuit. The advantage of this G4FET-NDR LC oscillator over a conventional LC NDR oscillator is that one can apply a time-varying signal to one of the extra control input terminals (VN or VP) to modulate the conductance of the NDR device and thereby amplitude-modulate the output signal.

Voltage controlled spintronic devices for logic applications

DOEpatents

You, Chun-Yeol; Bader, Samuel D.

2001-01-01

A reprogrammable logic gate comprising first and second voltage-controlled rotation transistors. Each transistor comprises three ferromagnetic layers with a spacer and insulating layer between the first and second ferromagnetic layers and an additional insulating layer between the second and third ferromagnetic layers. The third ferromagnetic layer of each transistor is connected to each other, and a constant external voltage source is applied to the second ferromagnetic layer of the first transistor. As input voltages are applied to the first ferromagnetic layer of each transistor, the relative directions of magnetization of the ferromagnetic layers and the magnitude of the external voltage determines the output voltage of the gate. By altering these parameters, the logic gate is capable of behaving as AND, OR, NAND, or NOR gates.

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

A low power and low phase-noise 91 96 GHz VCO in 90 nm CMOS

NASA Astrophysics Data System (ADS)

Lin, Yo-Sheng; Lan, Kai-Siang; Chuang, Ming-Yuan; Lin, Yu-Ching

2018-06-01

This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91 96 GHz, close to the simulated (92.1 96.7 GHz) and the calculated one (92.2 98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of - 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of -188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

A Boltzmann constant determination based on Johnson noise thermometry

NASA Astrophysics Data System (ADS)

Flowers-Jacobs, N. E.; Pollarolo, A.; Coakley, K. J.; Fox, A. E.; Rogalla, H.; Tew, W. L.; Benz, S. P.

2017-10-01

A value for the Boltzmann constant was measured electronically using an improved version of the Johnson Noise Thermometry (JNT) system at the National Institute of Standards and Technology (NIST), USA. This system is different from prior ones, including those from the 2011 determination at NIST and both 2015 and 2017 determinations at the National Institute of Metrology (NIM), China. As in all three previous determinations, the main contribution to the combined uncertainty is the statistical uncertainty in the noise measurement, which is mitigated by accumulating and integrating many weeks of cross-correlated measured data. The second major uncertainty contribution also still results from variations in the frequency response of the ratio of the measured spectral noise of the two noise sources, the sense resistor at the triple-point of water and the superconducting quantum voltage noise source. In this paper, we briefly describe the major differences between our JNT system and previous systems, in particular the input circuit and approach we used to match the frequency responses of the two noise sources. After analyzing and integrating 50 d of accumulated data, we determined a value: k~=1.380 642 9(69)× {{10}-23} J K-1 with a relative standard uncertainty of 5.0× {{10}-6} and relative offset -4.05× {{10}-6} from the CODATA 2014 recommended value.

Delta Modulation Technique for Improving the Sensitivity of Monobit Subsamplers in Radar and Coherent Receiver Applications

DOE PAGES

Rodenbeck, Christopher T.; Tracey, Keith J.; Barkley, Keith R.; ...

2014-08-01

This paper introduces a technique for improving the sensitivity of RF subsamplers in radar and coherent receiver applications. The technique, referred to herein as “delta modulation” (DM), feeds the time-average output of a monobit analog-to-digital converter (ADC) back to the ADC input, but with opposite polarity. Assuming pseudo-stationary modulation statistics on the sampled RF waveform, the feedback signal corrects for aggregate DC offsets present in the ADC that otherwise degrade ADC sensitivity. Two RF integrated circuits (RFICs) are designed to demonstrate the approach. One uses analog DM to create the feedback signal; the other uses digital DM to achieve themore » same result. A series of tests validates the designs. The dynamic time-domain response confirms the feedback loop’s basic operation. Measured output quantization imbalance, under noise-only input drive, significantly improves with the use of the DM circuit, even for large, deliberately induced DC offsets and wide temperature variation from -55°C to +85 °C. Examination of the corrected vs. uncorrected baseband spectrum under swept input signal-tonoise ratio (SNR) conditions demonstrates the effectiveness of this approach for realistic radar and coherent receiver applications. In conclusion, two-tone testing shows no impact of the DM technique on ADC linearity.« less

Stereo 3-D and non-stereo presentations of a computer-generated pictorial primary flight display with pathway augmentation

NASA Technical Reports Server (NTRS)

Nataupsky, Mark; Crittenden, Lucille

1988-01-01

Stereo 3-D was researched as a means to present cockpit displays which enhance a pilot's situational awareness while maintaining a desirable level of mental workload. The initial study at the NASA Langley Research Center used two different pathways-in-the-sky to augment a computer-generated pictorial primary flight display. One pathway resembled the outline of signposts, while the other pathway resembled a monorail. That display was configured for a curved approach to a landing such as could be used in a Microwave Landing System (MLS) approach. It could also be used for military transports which would have to fly a precision curved pathway. Each trial was initialized with the pilot on the desired flight path. After 2 seconds, he suddenly was shifted to one of eight flight path offsets. The pilot was then required to make the initial pitch and/or roll input to correct back to the nominal flight path. As soon as the input was made, the trial was over. No input was required for control trials with no flight path offset. Pilots responded statistically significantly faster when the display was presented in the stereo version than when it was presented in the nonstereo version.

A new low voltage level-shifted FVF current mirror with enhanced bandwidth and output resistance

NASA Astrophysics Data System (ADS)

Aggarwal, Bhawna; Gupta, Maneesha; Gupta, Anil Kumar; Sangal, Ankur

2016-10-01

This paper proposes a new high-performance level-shifted flipped voltage follower (LSFVF) based low-voltage current mirror (CM). The proposed CM utilises the low-supply voltage and low-input resistance characteristics of a flipped voltage follower (FVF) CM. In the proposed CM, level-shifting configuration is used to obtain a wide operating current range and resistive compensation technique is employed to increase the operating bandwidth. The peaking in frequency response is reduced by using an additional large MOSFET. Moreover, a very high output resistance (in GΩ range) along with low-current transfer error is achieved through super-cascode configuration for a wide current range (0-440 µA). Small signal analysis is carried out to show the improvements achieved at each step. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology. In the proposed CM, a bandwidth of 6.1799 GHz, 1% settling time of 0.719 ns, input and output resistances of 21.43 Ω and 1.14 GΩ, respectively, are obtained with a single supply voltage of 1 V. The layout of the proposed CM has been designed and post-layout simulation results have been shown. The post-layout simulation results for Monte Carlo and temperature analysis have also been included to show the reliability of the CM against the variations in process parameters and temperature changes.

Thermocouple-Signal-Conditioning Circuit

NASA Technical Reports Server (NTRS)

Simon, Richard A.

1991-01-01

Thermocouple-signal-conditioning circuit acting in conjunction with thermocouple, exhibits electrical behavior of voltage in series with resistance. Combination part of input bridge circuit of controller. Circuit configured for either of two specific applications by selection of alternative resistances and supply voltages. Includes alarm circuit detecting open circuit in thermocouple and provides off-scale output to signal malfunctions.

Deflection amplifier for image dissectors

NASA Technical Reports Server (NTRS)

Salomon, P. M.

1977-01-01

Balanced symmetrical y-axis amplifier uses zener-diode level shifting to interface operational amplifiers to high voltage bipolar output stages. Nominal voltage transfer characteristic is 40 differential output volts per input volt; bandwidth, between -3-dB points, is approximately 8 kHz; loop gain is nominally 89 dB with closed loop gain of 26 dB.

47 CFR 73.51 - Determining operating power.

Code of Federal Regulations, 2014 CFR

2014-10-01

...'s input power directly from the RF voltage, RF current, and phase angle; or (2) calculating the... dissipative network in the antenna system shall be made on FCC Form 302. The technical information supplied on... transmitter output within a tolerance of ±10 percent, to compensate for variations in line voltage or other...

47 CFR 73.51 - Determining operating power.

Code of Federal Regulations, 2012 CFR

2012-10-01

...'s input power directly from the RF voltage, RF current, and phase angle; or (2) calculating the... dissipative network in the antenna system shall be made on FCC Form 302. The technical information supplied on... transmitter output within a tolerance of ±10 percent, to compensate for variations in line voltage or other...

47 CFR 73.51 - Determining operating power.

Code of Federal Regulations, 2013 CFR

2013-10-01

...'s input power directly from the RF voltage, RF current, and phase angle; or (2) calculating the... dissipative network in the antenna system shall be made on FCC Form 302. The technical information supplied on... transmitter output within a tolerance of ±10 percent, to compensate for variations in line voltage or other...

Power factor control system for AC induction motors

NASA Technical Reports Server (NTRS)

Nola, F. J. (Inventor)

1977-01-01

A power factor control system for use with ac induction motors was designed which samples lines voltage and current through the motor and decreases power input to the motor proportional to the detected phase displacement between current and voltage. This system provides, less power to the motor, as it is less loaded.

Amorphous silicon thin-film transistor active-matrix for reflective cholesteric liquid crystal displays

NASA Astrophysics Data System (ADS)

Nahm, Jeong-Yeop

Reflective cholesteric liquid crystal displays (Ch-LCDs) have advantages, such as, high brightness, low power consumption, and wide viewing angle, since they do not need any polarizer, color filter, and backlight. Furthermore, due to their bistability Ch-LCDs can retain their images virtually forever without additional power consumption. But conventional passive-matrix addressing of Ch-LCDs allows only a slow image updating speed. Active-matrix addressing should allow fast image updating or video-rate operation. However, because the threshold voltage of cholesteric, liquid crystal is high (>20V), the switching devices for active-matrix addressing should satisfy required characteristics even under high bias conditions. In order to investigate the applicability of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) for the switching devices of active-matrix (AM) Ch-LCDs, the characteristics of conventional and gate offset high voltage a-Si:H TTFs were examined under high bias conditions. And it was concluded that high OFF-current of conventional a-Si:H TFTs and low ON-current of gate offset high voltage a-Si:H TFTs were main problems for reflective AM Ch-LCD applications. In order to improve the TFT characteristics under high bias conditions, we propose two new a-Si:H TFT structures called gate planarized (GP) and buried field plate (BFP) high voltage a-Si:H TFTs. Firstly, in the GP a-Si:H TFTs, we used a thick spin-coated benzocyclobutene (BCB) layer beneath a thin hydrogenated amorphous silicon nitride (a-SiNx:H) layer for gate insulator. The GP a-Si:H TFT showed normal TFT characteristic up to VGS = VDS = ˜100 V without any device failure. But TFT ON-current of GP a-Si:H TFT was reduced due to the introduction of the thick low dielectric BCB layer. Secondly, in the BFP a-Si:H TFT, an offset region and a buried field plate were introduced between the drain/source and gate electrodes to reduce the electric field in the pinch-off region. For this BFP a-Si:H TFT, a low OFF-current (1.04 pA) and a high ON/OFF-current ratio (5.68 x 106) up to VGS = VDS = ˜30 V were obtained. Based on our a-Si:H TFTs studies, we designed an a-Si:H TFT active-matrix panel and fabricated the AM Ch-LCDs either by optimizing a-Si:H TFT processing or adopting the GP a-Si:H TFT technology. The fabricated a-Si:H TFT active-matrix panels can be operated at the voltage of 50 and 60V, applied to the data and gate lines, respectively. With the a-Si:H TFT active-matrix panels, the AM Ch-LCDs were fabricated and operated with the frame rate of 60 Hz and the maximum contrast ratio of ˜30.

High Input Voltage Discharge Supply for High Power Hall Thrusters Using Silicon Carbide Devices

NASA Technical Reports Server (NTRS)

Pinero, Luis R.; Scheidegger, Robert J.; Aulsio, Michael V.; Birchenough, Arthur G.

2014-01-01

A power processing unit for a 15 kW Hall thruster is under development at NASA Glenn Research Center. The unit produces up to 400 VDC with two parallel 7.5 kW discharge modules that operate from a 300 VDC nominal input voltage. Silicon carbide MOSFETs and diodes were used in this design because they were the best choice to handle the high voltage stress while delivering high efficiency and low specific mass. Efficiencies in excess of 97 percent were demonstrated during integration testing with the NASA-300M 20 kW Hall thruster. Electromagnet, cathode keeper, and heater supplies were also developed and will be integrated with the discharge supply into a vacuum-rated brassboard power processing unit with full flight functionality. This design could be evolved into a flight unit for future missions that requires high power electric propulsion.

Remote Monitor Alarm System

NASA Technical Reports Server (NTRS)

Stute, Robert A. (Inventor); Galloway, F. Houston (Inventor); Medelius, Pedro J. (Inventor); Swindle, Robert W. (Inventor); Bierman, Tracy A. (Inventor)

1996-01-01

A remote monitor alarm system monitors discrete alarm and analog power supply voltage conditions at remotely located communications terminal equipment. A central monitoring unit (CMU) is connected via serial data links to each of a plurality of remote terminal units (RTUS) that monitor the alarm and power supply conditions of the remote terminal equipment. Each RTU can monitor and store condition information of both discrete alarm points and analog power supply voltage points in its associated communications terminal equipment. The stored alarm information is periodically transmitted to the CMU in response to sequential polling of the RTUS. The number of monitored alarm inputs and permissible voltage ranges for the analog inputs can be remotely configured at the CMU and downloaded into programmable memory at each RTU. The CMU includes a video display, a hard disk memory, a line printer and an audio alarm for communicating and storing the alarm information received from each RTU.

A programmable power processor for high power space applications

NASA Technical Reports Server (NTRS)

Lanier, J. R., Jr.; Graves, J. R.; Kapustka, R. E.; Bush, J. R., Jr.

1982-01-01

A Programmable Power Processor (P3) has been developed for application in future large space power systems. The P3 is capable of operation over a wide range of input voltage (26 to 375 Vdc) and output voltage (24 to 180 Vdc). The peak output power capability is 18 kW (180 V at 100 A). The output characteristics of the P3 can be programmed to any voltage and/or current level within the limits of the processor and may be controlled as a function of internal or external parameters. Seven breadboard P3s and one 'flight-type' engineering model P3 have been built and tested both individually and in electrical power systems. The programmable feature allows the P3 to be used in a variety of applications by changing the output characteristics. Test results, including efficiency at various input/output combinations, transient response, and output impedance, are presented.

Straight and chopped dc performance data for a Prestolite MTC-4001 motor and a general electric EV-1 controller

NASA Technical Reports Server (NTRS)

Edie, P. C.

1981-01-01

Performance data on the Prestolite MTC-4001 series wound dc motor and General Electric EV-1 Chopper Controller is supplied for the electric vehicle manufacturer. Data are provided for both straight and chopped dc input to the motor, at 2 motor temperature levels. Testing was done at 6 voltage increments to the motor, and 2 voltage increments to the controller. Data results are presented in both tabular and graphical forms. Tabular information includes motor voltage and current input data, motor speed and torque output data, power data and temperature data. Graphical information includes torque-speed, motor power output-speed, torque-current, and efficiency-speed plots under the various operating conditions. The data resulting from this testing show the speed-torque plots to have the most variance with operating temperature. The maximum motor efficiency is between 76% and 82%, regardless of temperature or mode of operation.

Transistor biased amplifier minimizes diode discriminator threshold attenuation

NASA Technical Reports Server (NTRS)

Larsen, R. N.

1967-01-01

Transistor biased amplifier has a biased diode discriminator driven by a high impedance /several megohms/ current source, rather than a voltage source with several hundred ohms output impedance. This high impedance input arrangement makes the incremental impedance of the threshold diode negligible relative to the input impedance.

Determination of nonlinear resistance voltage-current relationships by measuring harmonics

NASA Technical Reports Server (NTRS)

Stafford, J. M.

1971-01-01

Test configuration measures harmonic signal amplitudes generated in nonlinear resistance. Vacuum-type voltmeter measures low frequency sinusoidal input signal amplitude and wave-analyzer measures amplitude of harmonic signals generated in junction. Input signal harmonics amplitude must not exceed that of harmonics generated in nonlinear resistance.

Method and apparatus for monitoring the rotating frequency of de-energized induction motors

DOEpatents

Mikesell, H.E.; Lucy, E.

1998-02-03

The rotational speed of a coasting induction motor is measured by sensing e residual electrical voltages at the power terminals of the motor, thus eliminating the need for conventional tachometer equipment, additional mechanical components or modifications to the induction motor itself. The power terminal voltage signal is detected and transformed into a DC voltage proportional to the frequency of the signal. This DC voltage can be input to the control system of a variable frequency motor controller to regulate the output characteristics thereof relative to the speed of the coasting motor. 6 figs.

Method and apparatus for monitoring the rotating frequency of de-energized induction motors

DOEpatents

Mikesell, Harvey E.; Lucy, Eric

1998-01-01

The rotational speed of a coasting induction motor is measured by sensing e residual electrical voltages at the power terminals of the motor, thus eliminating the need for conventional tachometer equipment, additional mechanical components or modifications to the induction motor itself. The power terminal voltage signal is detected and transformed into a DC voltage proportional to the frequency of the signal. This DC voltage can be input to the control system of a variable frequency motor controller to regulate the output characteristics thereof relative to the speed of the coasting motor.

Ultralow-quiescent-current and wide-load-range low-dropout linear regulator with self-biasing technique for micropower battery management

NASA Astrophysics Data System (ADS)

Ozaki, Toshihiro; Hirose, Tetsuya; Asano, Hiroki; Kuroki, Nobutaka; Numa, Masahiro

2017-04-01

In this paper, we present a 151 nA quiescent and 6.8 mA maximum-output-current low-dropout (LDO) linear regulator for micropower battery management. The LDO regulator employs self-biasing and multiple-stacked cascode techniques to achieve efficient, accurate, and high-voltage-input-tolerant operation. Measurement results demonstrated that the proposed LDO regulator operates with an ultralow quiescent current of 151 nA. The maximum output currents with a 4.16 V output were 1.0 and 6.8 mA when the input voltages were 4.25 and 5.0 V, respectively.

Low-Power Low-Noise Amplifier Using Attenuation-Adaptive Noise Control for Ultrasound Imaging Systems.

PubMed

Jung, Sung-Jin; Hong, Seong-Kwan; Kwon, Oh-Kyong

2017-02-01

This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.

Jitter compensation circuit

DOEpatents

Sullivan, James S.; Ball, Don G.

1997-01-01

The instantaneous V.sub.co signal on a charging capacitor is sampled and the charge voltage on capacitor C.sub.o is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V.sub. co signal is split between a gain stage (G=0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V.sub.co signal is applied to the negative input of a differential amplifier gain stage (G=10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V.sub.co signal from the instantaneous value of sampled V.sub.co signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V.sub.co values squared divided by the total volt-second product of the magnetic compression circuit.

Jitter compensation circuit

DOEpatents

Sullivan, J.S.; Ball, D.G.

1997-09-09

The instantaneous V{sub co} signal on a charging capacitor is sampled and the charge voltage on capacitor C{sub o} is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V{sub co} signal is split between a gain stage (G = 0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V{sub co} signal is applied to the negative input of a differential amplifier gain stage (G = 10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V{sub co} signal from the instantaneous value of sampled V{sub co} signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator. The error signal is then compared to a voltage ramp that is proportional to the averaged V{sub co} values squared divided by the total volt-second product of the magnetic compression circuit. 11 figs.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

High Voltage TAL Performance

NASA Technical Reports Server (NTRS)

Jacobson, David T.; Jankovsky, Robert S.; Rawlin, Vincent K.; Manzella, David H.

2001-01-01

The performance of a two-stage, anode layer Hall thruster was evaluated. Experiments were conducted in single and two-stage configurations. In single-stage configuration, the thruster was operated with discharge voltages ranging from 300 to 1700 V. Discharge specific impulses ranged from 1630 to 4140 sec. Thruster investigations were conducted with input power ranging from 1 to 8.7 kW, corresponding to power throttling of nearly 9: 1. An extensive two-stage performance map was generated. Data taken with total voltage (sum of discharge and accelerating voltage) constant revealed a decrease in thruster efficiency as the discharge voltage was increased. Anode specific impulse values were comparable in the single and two-stage configurations showing no strong advantage for two-stage operation.

Exploring the Use of Alfven Waves in Magnetometer Calibration at Geosynchronous Orbit

NASA Technical Reports Server (NTRS)

Bentley, John; Sheppard, David; RIch, Frederick; Redmon, Robert; Loto'aniu, Paul; Chu, Donald

2016-01-01

An Alfven wave is a type magnetohydrodynamicwave that travels through a conducting fluid under the influence of a magnetic field. Researchers have successfully calculated offset vectors of magnetometers in interplanetary space by optimizing the offset to maximize certain Alfvenic properties of observed waves (Leinweber, Belcher). If suitable Alfven waves can be found in the magnetosphere at geosynchronous altitude then these techniques could be used to augment the overall calibration plan for magnetometers in this region such as on the GOES spacecraft, possibly increasing the time between regular maneuvers. Calibration maneuvers may be undesirable because they disrupt the activities of other instruments. Various algorithms to calculate an offset using Alfven waves were considered. A new variation of the Davis-Smith method was derived because it can be mathematically shown that the Davis-Smith method tolerates filtered data, which expands potential applications. The variant developed was designed to find only the offset in the plane normal to the main field because the overall direction of Earth's magnetic field rarely changes, and theory suggests the Alfvenic disturbances occur transverse to the main field. Other variations of the Davis-Smith method encounter problems with data containing waves that propagate in mostly the same direction. A searching algorithm was then designed to look for periods of time with potential Alfven waves in GOES 15 data based on parameters requiring that disturbances be normal to the main field and not change field magnitude. Final waves for calculation were hand-selected. These waves produced credible two-dimensional offset vectors when input to the Davis-Smith method. Multiple two-dimensional solutions in different planes can be combined to get a measurement of the complete offset. The resulting three dimensional offset did not show sufficient precision over several years to be used as a primary calibration method, but reflected changes in the offset fairly well, suggesting that the method could be helpful in monitoring trends of the offset vector when maneuvers cannot be used.

Design of a high voltage input - output ratio dc-dc converter dedicated to small power fuel cell systems

NASA Astrophysics Data System (ADS)

Béthoux, O.; Cathelin, J.

2010-12-01

Consuming chemical energy, fuel cells produce simultaneously heat, water and useful electrical power [J.M. Andújar, F. Segura, Renew. Sust. Energy Rev. 13, 2309 (2009)], [J. Larminie, A. Dicks, Fuel Cell Systems Explained, 2nd edn. (John Wiley & Sons, 2003)]. As a matter of fact, the voltage generated by a fuel cell strongly depends on both the load power demand and the operating conditions. Besides, as a result of many design aspects, fuel cells are low voltage and high current electric generators. On the contrary, electric loads are commonly designed for small voltage swing and a high V/I ratio in order to minimize Joule losses. Therefore, electric loads supplied by fuel cells are typically fed by means of an intermediate power voltage regulator. The specifications of such a power converter are to be able to step up the input voltage with a high ratio (a ratio of 10 is a classic situation) and also to work with an excellent efficiency (in order to minimize its size, its weight and its losses) [A. Shahin, B. Huang, J.P. Martin, S. Pierfederici, B. Davat, Energy Conv. Manag. 51, 56 (2010)]. This paper deals with the design of this essential ancillary device. It intends to bring out the best structure for fulfilling this function. Several dc-dc converters with large voltage step-up ratios are introduced. A topology based on a coupled inductor or tapped inductor is closely studied. A detailed modelling is performed with the purpose of providing designing rules. This model is validated with both simulation and implementation. The experimental prototype is based on the following specifications: the fuel cell output voltage ranges from a 50 V open-voltage to a 25 V rated voltage while the load requires a constant 250 V voltage. The studied coupled inductor converter is compared with a classic boost converter commonly used in this voltage elevating application. Even though the voltage regulator faces severe FC specifications, the measured efficiency reaches 96% at the rated power whereas conventional boost efficiency barely achieves 91.5% in the same operating conditions.

Performance analysis of electronic power transformer based on neuro-fuzzy controller.

PubMed

Acikgoz, Hakan; Kececioglu, O Fatih; Yildiz, Ceyhun; Gani, Ahmet; Sekkeli, Mustafa

2016-01-01

In recent years, electronic power transformer (EPT), which is also called solid state transformer, has attracted great interest and has been used in place of the conventional power transformers. These transformers have many important functions as high unity power factor, low harmonic distortion, constant DC bus voltage, regulated output voltage and compensation capability. In this study, proposed EPT structure contains a three-phase pulse width modulation rectifier that converts 800 Vrms AC to 2000 V DC bus at input stage, a dual active bridge converter that provides 400 V DC bus with 5:1 high frequency transformer at isolation stage and a three-phase two level inverter that is used to obtain AC output at output stage. In order to enhance dynamic performance of EPT structure, neuro fuzzy controllers which have durable and nonlinear nature are used in input and isolation stages instead of PI controllers. The main aim of EPT structure with the proposed controller is to improve the stability of power system and to provide faster response against disturbances. Moreover, a number of simulation results are carried out to verify EPT structure designed in MATLAB/Simulink environment and to analyze compensation ability for voltage harmonics, voltage flicker and voltage sag/swell conditions.

New low-level a-c amplifier provides adjustable noise cancellation and automatic temperature compensation

NASA Technical Reports Server (NTRS)

Smith, J. R., Jr.

1964-01-01

Circuit utilizing a transistorized differential amplifier is developed for biomedical use. This low voltage operating circuit provides adjustable cancellation at the input for unbalanced noise signals, and automatic temperature compensation is accomplished by a single active element across the input-output ends.

47 CFR 73.1820 - Station log.

Code of Federal Regulations, 2011 CFR

2011-10-01

... values): (A) Common point current. (B) When the operating power is determined by the indirect method, the efficiency factor F and either the product of the final amplifier input voltage and current or the calculated antenna input power. See § 73.51(e). (C) Antenna monitor phase or phase deviation indications. (D) Antenna...

Modular Apparatus and Method for Attaching Multiple Devices

NASA Technical Reports Server (NTRS)

Okojie, Robert S (Inventor)

2015-01-01

A modular apparatus for attaching sensors and electronics is disclosed. The modular apparatus includes a square recess including a plurality of cavities and a reference cavity such that a pressure sensor can be connected to the modular apparatus. The modular apparatus also includes at least one voltage input hole and at least one voltage output hole operably connected to each of the plurality of cavities such that voltage can be applied to the pressure sensor and received from the pressure sensor.

MULTIPLIER CIRCUIT

DOEpatents

Chase, R.L.

1963-05-01

An electronic fast multiplier circuit utilizing a transistor controlled voltage divider network is presented. The multiplier includes a stepped potentiometer in which solid state or transistor switches are substituted for mechanical wipers in order to obtain electronic switching that is extremely fast as compared to the usual servo-driven mechanical wipers. While this multiplier circuit operates as an approximation and in steps to obtain a voltage that is the product of two input voltages, any desired degree of accuracy can be obtained with the proper number of increments and adjustment of parameters. (AEC)

The Noise Level Optimization for Induction Magnetometer of SEP System

NASA Astrophysics Data System (ADS)

Zhu, W.; Fang, G.

2011-12-01

The Surface Electromagnetic Penetration (SEP) System, subsidized by the SinoProbe Plan in China, is designed for 3D conductivity imaging in geophysical mineral exploration, underground water distribution exploration, oil and gas reservoir exploration. Both the Controlled Source Audio Magnetotellurics (CSAMT) method and Magnetotellurics (MT) method can be surveyed by SEP system. In this article, an optimization design is introduced, which can minimize the noise level of the induction magnetometer for SEP system magnetic field's acquisition. The induction magnetometer transfers the rate of the magnetic field's change to voltage signal by induction coil, and amplified it by Low Noise Amplifier The noise parts contributed to the magnetometer are: the coil's thermal noise, the equivalent input voltage and current noise of the pre-amplifier. The coil's thermal noise is decided by coil's DC resistance. The equivalent input voltage and current noise of the pre-amplifier depend on the amplifier's type and DC operation condition. The design here optimized the DC operation point of pre-amplifier, adjusted the DC current source, and realized the minimum of total noise level of magnetometer. The calculation and test results show that: the total noise is about 1pT/√Hz, the thermal noise of coils is 1.7nV/√Hz, the preamplifier equivalent input voltage and current noise is 3nV/ √Hz and 0.1pA/√Hz, the weight of the magnetometer is 4.5kg and meet the requirement of SEP system.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Predicting cloud-to-ground lightning with neural networks

NASA Technical Reports Server (NTRS)

Barnes, Arnold A., Jr.; Frankel, Donald; Draper, James Stark

1991-01-01

A neural network is being trained to predict lightning at Cape Canaveral for periods up to two hours in advance. Inputs consist of ground based field mill data, meteorological tower data, lightning location data, and radiosonde data. High values of the field mill data and rapid changes in the field mill data, offset in time, provide the forecasts or desired output values used to train the neural network through backpropagation. Examples of input data are shown and an example of data compression using a hidden layer in the neural network is discussed.

Fast charge separation in a non-fullerene organic solar cell with a small driving force

NASA Astrophysics Data System (ADS)

Liu, Jing; Chen, Shangshang; Qian, Deping; Gautam, Bhoj; Yang, Guofang; Zhao, Jingbo; Bergqvist, Jonas; Zhang, Fengling; Ma, Wei; Ade, Harald; Inganäs, Olle; Gundogdu, Kenan; Gao, Feng; Yan, He

2016-07-01

Fast and efficient charge separation is essential to achieve high power conversion efficiency in organic solar cells (OSCs). In state-of-the-art OSCs, this is usually achieved by a significant driving force, defined as the offset between the bandgap (Egap) of the donor/acceptor materials and the energy of the charge transfer (CT) state (ECT), which is typically greater than 0.3 eV. The large driving force causes a relatively large voltage loss that hinders performance. Here, we report non-fullerene OSCs that exhibit ultrafast and efficient charge separation despite a negligible driving force, as ECT is nearly identical to Egap. Moreover, the small driving force is found to have minimal detrimental effects on charge transfer dynamics of the OSCs. We demonstrate a non-fullerene OSC with 9.5% efficiency and nearly 90% internal quantum efficiency despite a low voltage loss of 0.61 V. This creates a path towards highly efficient OSCs with a low voltage loss.

SEMICONDUCTOR DEVICES: A Ga-doped ZnO transparent conduct layer for GaN-based LEDs

NASA Astrophysics Data System (ADS)

Zhen, Liu; Xiaofeng, Wang; Hua, Yang; Yao, Duan; Yiping, Zeng

2010-09-01

An 8 μm thick Ga-doped ZnO (GZO) film grown by metal-source vapor phase epitaxy was deposited on a GaN-based light-emitting diode (LED) to substitute for the conventional ITO as a transparent conduct layer (TCL). Electroluminescence spectra exhibited that the intensity value of LED emission with a GZO TCL is markedly improved by 23.6% as compared to an LED with an ITO TCL at 20 mA. In addition, the forward voltage of the LED with a GZO TCL at 20 mA is higher than that of the conventional LED. To investigate the reason for the increase of the forward voltage, X-ray photoelectron spectroscopy was performed to analyze the interface properties of the GZO/p-GaN heterojunction. The large valence band offset (2:24 ± 0:21 eV) resulting from the formation of Ga2O3 in the GZO/p-GaN interface was attributed to the increase of the forward voltage.

Improved-Bandwidth Transimpedance Amplifier

NASA Technical Reports Server (NTRS)

Chapsky, Jacob

2009-01-01

The widest available operational amplifier, with the best voltage and current noise characteristics, is considered for transimpedance amplifier (TIA) applications where wide bandwidth is required to handle fast rising input signals (as for time-of-flight measurement cases). The added amplifier inside the TIA feedback loop can be configured to have slightly lower voltage gain than the bandwidth reduction factor.

Changes in behavioral responses of Lygus lineolaris (Hemiptera: Miridae) from various applied signal voltages during EPG recordings

USDA-ARS?s Scientific Manuscript database

A 3rd-generation AC-DC electrical penetration graph (EPG) monitor was used to study feeding behaviors of pre-reproductive adult Lygus lineolaris (Hemiptera: Miridae) on pinhead (<3mm) cotton squares, applying different signal voltages at several input impedances. The AC-DC monitor allows a user to s...

Intermediate conductance calcium-activated potassium channels modulate summation of parallel fiber input in cerebellar Purkinje cells.

PubMed

Engbers, Jordan D T; Anderson, Dustin; Asmara, Hadhimulya; Rehak, Renata; Mehaffey, W Hamish; Hameed, Shahid; McKay, Bruce E; Kruskic, Mirna; Zamponi, Gerald W; Turner, Ray W

2012-02-14

Encoding sensory input requires the expression of postsynaptic ion channels to transform key features of afferent input to an appropriate pattern of spike output. Although Ca(2+)-activated K(+) channels are known to control spike frequency in central neurons, Ca(2+)-activated K(+) channels of intermediate conductance (KCa3.1) are believed to be restricted to peripheral neurons. We now report that cerebellar Purkinje cells express KCa3.1 channels, as evidenced through single-cell RT-PCR, immunocytochemistry, pharmacology, and single-channel recordings. Furthermore, KCa3.1 channels coimmunoprecipitate and interact with low voltage-activated Cav3.2 Ca(2+) channels at the nanodomain level to support a previously undescribed transient voltage- and Ca(2+)-dependent current. As a result, subthreshold parallel fiber excitatory postsynaptic potentials (EPSPs) activate Cav3 Ca(2+) influx to trigger a KCa3.1-mediated regulation of the EPSP and subsequent after-hyperpolarization. The Cav3-KCa3.1 complex provides powerful control over temporal summation of EPSPs, effectively suppressing low frequencies of parallel fiber input. KCa3.1 channels thus contribute to a high-pass filter that allows Purkinje cells to respond preferentially to high-frequency parallel fiber bursts characteristic of sensory input.

System and method for determining stator winding resistance in an AC motor using motor drives

DOEpatents

Lu, Bin; Habetler, Thomas G; Zhang, Pinjia

2013-02-26

A system and method for determining the stator winding resistance of AC motors is provided. The system includes an AC motor drive having an input connectable to an AC source and an output connectable to an input terminal of an AC motor, a pulse width modulation (PWM) converter having switches therein to control current flow and terminal voltages in the AC motor, and a control system connected to the PWM converter. The control system generates a command signal to cause the PWM converter to control an output of the AC motor drive corresponding to an input to the AC motor, selectively generates a modified command signal to cause the PWM converter to inject a DC signal into the output of the AC motor drive, and determines a stator winding resistance of the AC motor based on the DC signal of at least one of the voltage and current.

Electric vehicle drive train with contactor protection

DOEpatents

Konrad, Charles E.; Benson, Ralph A.

1994-01-01

A drive train for an electric vehicle includes a traction battery, a power drive circuit, a main contactor for connecting and disconnecting the traction battery and the power drive circuit, a voltage detector across contacts of the main contactor, and a controller for controlling the main contactor to prevent movement of its contacts to the closed position when the voltage across the contacts exceeds a predetermined threshold, to thereby protect the contacts of the contactor. The power drive circuit includes an electric traction motor and a DC-to-AC inverter with a capacitive input filter. The controller also inhibits the power drive circuit from driving the motor and thereby discharging the input capacitor if the contacts are inadvertently opened during motoring. A precharging contactor is controlled to charge the input filter capacitor prior to closing the main contactor to further protect the contacts of the main contactor.

Electric vehicle drive train with contactor protection

DOEpatents

Konrad, C.E.; Benson, R.A.

1994-11-29

A drive train for an electric vehicle includes a traction battery, a power drive circuit, a main contactor for connecting and disconnecting the traction battery and the power drive circuit, a voltage detector across contacts of the main contactor, and a controller for controlling the main contactor to prevent movement of its contacts to the closed position when the voltage across the contacts exceeds a predetermined threshold, to thereby protect the contacts of the contactor. The power drive circuit includes an electric traction motor and a DC-to-AC inverter with a capacitive input filter. The controller also inhibits the power drive circuit from driving the motor and thereby discharging the input capacitor if the contacts are inadvertently opened during motoring. A precharging contactor is controlled to charge the input filter capacitor prior to closing the main contactor to further protect the contacts of the main contactor. 3 figures.

Microwave Driven Actuators Power Allocation and Distribution

NASA Technical Reports Server (NTRS)

Forbes, Timothy; Song, Kyo D.

2000-01-01

Design, fabrication and test of a power allocation and distribution (PAD) network for microwave driven actuators is presented in this paper. Development of a circuit that would collect power from a rectenna array amplify and distribute the power to actuators was designed and fabricated for space application in an actuator array driven by a microwave. A P-SPICE model was constructed initially for data reduction purposes, and was followed by a working real-world model. A voltage up - converter (VUC) is used to amplify the voltage from the individual rectenna. The testing yielded a 26:1 voltage amplification ratio with input voltage at 9 volts and a measured output voltage 230VDC. Future work includes the miniaturization of the circuitry, the use of microwave remote control, and voltage amplification technology for each voltage source. The objective of this work is to develop a model system that will collect DC voltage from an array of rectenna and propagate the voltage to an array of actuators.

Solid state safety jumper cables

DOEpatents

Kronberg, James W.

1993-01-01

Solid state jumper cables for connecting two batteries in parallel, having two bridge rectifiers for developing a reference voltage, a four-input decoder for determining which terminals are to be connected based on a comparison of the voltage at each of the four terminals to the reference voltage, and a pair of relays for effecting the correct connection depending on the determination of the decoder. No connection will be made unless only one terminal of each battery has a higher voltage than the reference voltage, indicating "positive" terminals, and one has a lower voltage than the reference voltage, indicating "negative" terminals, and that, therefore, the two high voltage terminals may be connected and the two lower voltage terminals may be connected. Current flows once the appropriate relay device is closed. The relay device is preferably a MOSFET (metal oxide semiconductor field effect transistor) combined with a series array of photodiodes that develop MOSFET gate-closing potential when the decoder output causes an LED to light.

Solid state safety jumper cables

DOEpatents

Kronberg, J.W.

1993-02-23

Solid state jumper cables for connecting two batteries in parallel, having two bridge rectifiers for developing a reference voltage, a four-input decoder for determining which terminals are to be connected based on a comparison of the voltage at each of the four terminals to the reference voltage, and a pair of relays for effecting the correct connection depending on the determination of the decoder. No connection will be made unless only one terminal of each battery has a higher voltage than the reference voltage, indicating positive'' terminals, and one has a lower voltage than the reference voltage, indicating negative'' terminals, and that, therefore, the two high voltage terminals may be connected and the two lower voltage terminals may be connected. Current flows once the appropriate relay device is closed. The relay device is preferably a MOSFET (metal oxide semiconductor field effect transistor) combined with a series array of photodiodes that develop MOSFET gate-closing potential when the decoder output causes an LED to light.

Frequency spectrum analyzer with phase-lock

DOEpatents

Boland, Thomas J.

1984-01-01

A frequency-spectrum analyzer with phase-lock for analyzing the frequency and amplitude of an input signal is comprised of a voltage controlled oscillator (VCO) which is driven by a ramp generator, and a phase error detector circuit. The phase error detector circuit measures the difference in phase between the VCO and the input signal, and drives the VCO locking it in phase momentarily with the input signal. The input signal and the output of the VCO are fed into a correlator which transfers the input signal to a frequency domain, while providing an accurate absolute amplitude measurement of each frequency component of the input signal.

Performance Analysis for Channel Estimation With 1-Bit ADC and Unknown Quantization Threshold

NASA Astrophysics Data System (ADS)

Stein, Manuel S.; Bar, Shahar; Nossek, Josef A.; Tabrikian, Joseph

2018-05-01

In this work, the problem of signal parameter estimation from measurements acquired by a low-complexity analog-to-digital converter (ADC) with $1$-bit output resolution and an unknown quantization threshold is considered. Single-comparator ADCs are energy-efficient and can be operated at ultra-high sampling rates. For analysis of such systems, a fixed and known quantization threshold is usually assumed. In the symmetric case, i.e., zero hard-limiting offset, it is known that in the low signal-to-noise ratio (SNR) regime the signal processing performance degrades moderately by ${2}/{\\pi}$ ($-1.96$ dB) when comparing to an ideal $\\infty$-bit converter. Due to hardware imperfections, low-complexity $1$-bit ADCs will in practice exhibit an unknown threshold different from zero. Therefore, we study the accuracy which can be obtained with receive data processed by a hard-limiter with unknown quantization level by using asymptotically optimal channel estimation algorithms. To characterize the estimation performance of these nonlinear algorithms, we employ analytic error expressions for different setups while modeling the offset as a nuisance parameter. In the low SNR regime, we establish the necessary condition for a vanishing loss due to missing offset knowledge at the receiver. As an application, we consider the estimation of single-input single-output wireless channels with inter-symbol interference and validate our analysis by comparing the analytic and experimental performance of the studied estimation algorithms. Finally, we comment on the extension to multiple-input multiple-output channel models.

Charge control microcomputer device for vehicle

DOE Office of Scientific and Technical Information (OSTI.GOV)

Morishita, M.; Kouge, S.

1986-08-26

A charge control microcomputer device is described for a vehicle, comprising: an AC generator driven by an engine for generating an output current, the generator having armature coils and a field coil; a battery charged by a rectified output of the generator and generating a terminal voltage; a voltage regulator for controlling a current flowing in the field coil, to control an output voltage of the generator to a predetermined value; an engine controlling microcomputer for receiving engine parameter data from the engine, to control the operation of the engine; a charge control microcomputer for processing input data including datamore » on at least one engine parameter output from the engine controlling microcomputer, and charge system data including at least one of battery terminal voltage data, generator voltage data and generator output current data, to provide a reference voltage for the voltage regulator.« less

Study of a control strategy for grid side converter in doubly- fed wind power system

NASA Astrophysics Data System (ADS)

Zhu, D. J.; Tan, Z. L.; Yuan, F.; Wang, Q. Y.; Ding, M.

2016-08-01

The grid side converter is an important part of the excitation system of doubly-fed asynchronous generator used in wind power system. As a three-phase voltage source PWM converter, it can not only transfer slip power in the form of active power, but also adjust the reactive power of the grid. This paper proposed a control approach for improving its performance. In this control approach, the dc voltage is regulated by a sliding mode variable structure control scheme and current by a variable structure controller based on the input output linearization. The theoretical bases of the sliding mode variable structure control were introduced, and the stability proof was presented. Switching function of the system has been deduced, sliding mode voltage controller model has been established, and the output of the outer voltage loop is the instruction of the inner current loop. Affine nonlinear model of two input two output equations on d-q axis for current has been established its meeting conditions of exact linearization were proved. In order to improve the anti-jamming capability of the system, a variable structure control was added in the current controller, the control law was deduced. The dual-loop control with sliding mode control in outer voltage loop and linearization variable structure control in inner current loop was proposed. Simulation results demonstrate the effectiveness of the proposed control strategy even during the dc reference voltage and system load variation.

A novel concept of fault current limiter based on saturable core in high voltage DC transmission system

NASA Astrophysics Data System (ADS)

Yuan, Jiaxin; Zhou, Hang; Gan, Pengcheng; Zhong, Yongheng; Gao, Yanhui; Muramatsu, Kazuhiro; Du, Zhiye; Chen, Baichao

2018-05-01

To develop mechanical circuit breaker in high voltage direct current (HVDC) system, a fault current limiter is required. Traditional method to limit DC fault current is to use superconducting technology or power electronic devices, which is quite difficult to be brought to practical use under high voltage circumstances. In this paper, a novel concept of high voltage DC transmission system fault current limiter (DCSFCL) based on saturable core was proposed. In the DCSFCL, the permanent magnets (PM) are added on both up and down side of the core to generate reverse magnetic flux that offset the magnetic flux generated by DC current and make the DC winding present a variable inductance to the DC system. In normal state, DCSFCL works as a smoothing reactor and its inductance is within the scope of the design requirements. When a fault occurs, the inductance of DCSFCL rises immediately and limits the steepness of the fault current. Magnetic field simulations were carried out, showing that compared with conventional smoothing reactor, DCSFCL can decrease the high steepness of DC fault current by 17% in less than 10ms, which verifies the feasibility and effectiveness of this method.

Multiple high voltage output DC-to-DC power converter

NASA Technical Reports Server (NTRS)

Cronin, Donald L. (Inventor); Farber, Bertrand F. (Inventor); Gehm, Hartmut K. (Inventor); Goldin, Daniel S. (Inventor)

1977-01-01

Disclosed is a multiple output DC-to-DC converter. The DC input power is filtered and passed through a chopper preregulator. The chopper output is then passed through a current source inverter controlled by a squarewave generator. The resultant AC is passed through the primary winding of a transformer, with high voltages induced in a plurality of secondary windings. The high voltage secondary outputs are each solid-state rectified for passage to individual output loads. Multiple feedback loops control the operation of the chopper preregulator, one being responsive to the current through the primary winding and another responsive to the DC voltage level at a selected output.

Voltage Stress on Y Capacitors from Indirect Lightning Pulses According to ED-14/DO-160

NASA Astrophysics Data System (ADS)

Meier, F.

2012-05-01

Transients due to lightning strikes on an aircraft's fuselage impose stress on the input filters of elec- tronic equipment. Permanent damage can occur when exceeding the voltage handling capacity of filter components causing a short circuit to ground. In ED-14/DO-160, section 22, a number of waveforms and levels are defined which are used to check the airworthiness of avionics equipment. Depending on pro- cedure and level, Y-capacitors are stressed by transient voltages which exceed their dielectric strength. The design engineer's task is a properly select the type and voltage rating of capacitors. With moderate simplifications, a LCR-series network is justified to calculate the peak voltage dependent on the capacitance.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2011-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Fingerprinted circuits and methods of making and identifying the same

NASA Technical Reports Server (NTRS)

Ferguson, Michael Ian (Inventor)

2012-01-01

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Switched-capacitor isolated LED driver

DOEpatents

Sanders, Seth R.; Kline, Mitchell

2016-03-22

A switched-capacitor voltage converter which is particularly well-suited for receiving a line voltage from which to drive current through a series of light emitting diodes (LEDs). Input voltage is rectified in a multi-level rectifier network having switched capacitors in an ascending-bank configuration for passing voltages in uniform steps between zero volts up to full received voltage V.sub.DC. A regulator section, operating on V.sub.DC, comprises switched-capacitor stages of H-bridge switching and flying capacitors. A current controlled oscillator drives the states of the switched-capacitor stages and changes its frequency to maintain a constant current to the load. Embodiments are described for isolating the load from the mains, utilizing an LC tank circuit or a multi-primary-winding transformer.

Electroactive polymer actuator based on a reduced graphene electrode

NASA Astrophysics Data System (ADS)

Im, Ki Hong; Choi, Hyonkwang

2014-03-01

We report an electroactive polymer (EAP) actuator using a reduced graphene electrode for a ionic polymer-metal composite actuator. Aqueous-reduced graphene is deposited to both sides of the ionic polymer membranes by using a simple inkjet printing process. The electrical and the optical properties of the reduced graphene were evaluated by using a four-point probe system, Raman spectroscopy, and Fourier-transform infrared attenuated total reflection spectroscopy. The actuator properties were evaluated from the curvatures of the ionic polymer graphene composite (IPGC) for various input voltages. From the results, we propose a new and simple isosceles trapezoidal element model for analyzing the relations among the input voltage, thickness, and curvature of IPGC.

Transient Response in a Dendritic Neuron Model for Current Injected at One Branch

PubMed Central

Rinzel, John; Rall, Wilfrid

1974-01-01

Mathematical expressions are obtained for the response function corresponding to an instantaneous pulse of current injected to a single dendritic branch in a branched dendritic neuron model. The theoretical model assumes passive membrane properties and the equivalent cylinder constraint on branch diameters. The response function when used in a convolution formula enables one to compute the voltage transient at any specified point in the dendritic tree for an arbitrary current injection at a given input location. A particular numerical example, for a brief current injection at a branch terminal, illustrates the attenuation and delay characteristics of the depolarization peak as it spreads throughout the neuron model. In contrast to the severe attenuation of voltage transients from branch input sites to the soma, the fraction of total input charge actually delivered to the soma and other trees is calculated to be about one-half. This fraction is independent of the input time course. Other numerical examples, which compare a branch terminal input site with a soma input site, demonstrate that, for a given transient current injection, the peak depolarization is not proportional to the input resistance at the injection site and, for a given synaptic conductance transient, the effective synaptic driving potential can be significantly reduced, resulting in less synaptic current flow and charge, for a branch input site. Also, for the synaptic case, the two inputs are compared on the basis of the excitatory post-synaptic potential (EPSP) seen at the soma and the total charge delivered to the soma. PMID:4424185

High temperature current mirror amplifier

DOEpatents

Patterson, III, Raymond B.

1984-05-22

A high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg.

Photovoltaic power system tests on an 8-kilowatt single-phase line-commutated inverter

NASA Technical Reports Server (NTRS)

Stover, J. B.

1978-01-01

Efficiency and power factor were measured as functions of solar array voltage and current. The effects of input shunt capacitance and series inductance were determined. Tests were conducted from 15 to 75 percent of the 8 kW rated inverter input power. Measured efficiencies ranged from 76 percent to 88 percent at about 50 percent of rated inverter input power. Power factor ranged from 36 percent to 72 percent.

Demonstration of the frequency offset errors introduced by an incorrect setting of the Zeeman/magnetic field adjustment on the cesium beam frequency standard

NASA Technical Reports Server (NTRS)

Kaufmann, D. C.

1976-01-01

The fine frequency setting of a cesium beam frequency standard is accomplished by adjusting the C field control with the appropriate Zeeman frequency applied to the harmonic generator. A novice operator in the field, even when using the correct Zeeman frequency input, may mistakenly set the C field to any one of seven major Beam I peaks (fingers) represented by the Ramsey curve. This can result in frequency offset errors of as much as 2.5 parts in ten to the tenth. The effects of maladjustment are demonstrated and suggestions are discussed on how to avoid the subtle traps associated with C field adjustments.

Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting

PubMed Central

Chaour, Issam; Fakhfakh, Ahmed; Kanoun, Olfa

2017-01-01

For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions. PMID:28282910

Design and Implementation of RF Energy Harvesting System for Low-Power Electronic Devices

NASA Astrophysics Data System (ADS)

Uzun, Yunus

2016-08-01

Radio frequency (RF) energy harvester systems are a good alternative for energizing of low-power electronics devices. In this work, an RF energy harvester is presented to obtain energy from Global System for Mobile Communications (GSM) 900 MHz signals. The energy harvester, consisting of a two-stage Dickson voltage multiplier circuit and L-type impedance matching circuits, was designed, simulated, fabricated and tested experimentally in terms of its performance. Simulation and experimental works were carried out for various input power levels, load resistances and input frequencies. Both simulation and experimental works have been carried out for this frequency band. An efficiency of 45% is obtained from the system at 0 dBm input power level using the impedance matching circuit. This corresponds to the power of 450 μW and this value is sufficient for many low-power devices. The most important parameters affecting the efficiency of the RF energy harvester are the input power level, frequency band, impedance matching and voltage multiplier circuits, load resistance and the selection of diodes. RF energy harvester designs should be optimized in terms of these parameters.

Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

PubMed

Ming Gu; Chakrabartty, Shantanu

2014-06-01

This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting.

PubMed

Chaour, Issam; Fakhfakh, Ahmed; Kanoun, Olfa

2017-03-09

For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from -40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions.

Constant Switching Frequency DTC for Matrix Converter Fed Speed Sensorless Induction Motor Drive

NASA Astrophysics Data System (ADS)

Mir, Tabish Nazir; Singh, Bhim; Bhat, Abdul Hamid

2018-05-01

The paper presents a constant switching frequency scheme for speed sensorless Direct Torque Control (DTC) of Matrix Converter fed Induction Motor Drive. The use of matrix converter facilitates improved power quality on input as well as motor side, along with Input Power Factor control, besides eliminating the need for heavy passive elements. Moreover, DTC through Space Vector Modulation helps in achieving a fast control over the torque and flux of the motor, with added benefit of constant switching frequency. A constant switching frequency aids in maintaining desired power quality of AC mains current even at low motor speeds, and simplifies input filter design of the matrix converter, as compared to conventional hysteresis based DTC. Further, stator voltage estimation from sensed input voltage, and subsequent stator (and rotor) flux estimation is done. For speed sensorless operation, a Model Reference Adaptive System is used, which emulates the speed dependent rotor flux equations of the induction motor. The error between conventionally estimated rotor flux (reference model) and the rotor flux estimated through the adaptive observer is processed through PI controller to generate the rotor speed estimate.

System and method to determine electric motor efficiency nonintrusively

DOEpatents

Lu, Bin [Kenosha, WI; Habetler, Thomas G [Snellville, GA; Harley, Ronald G [Lawrenceville, GA

2011-08-30

A system and method for nonintrusively determining electric motor efficiency includes a processor programed to, while the motor is in operation, determine a plurality of stator input currents, electrical input data, a rotor speed, a value of stator resistance, and an efficiency of the motor based on the determined rotor speed, the value of stator resistance, the plurality of stator input currents, and the electrical input data. The determination of the rotor speed is based on one of the input power and the plurality of stator input currents. The determination of the value of the stator resistance is based on at least one of a horsepower rating and a combination of the plurality of stator input currents and the electrical input data. The electrical input data includes at least one of an input power and a plurality of stator input voltages.

New approaches to provide ride-through for critical loads in electric power distribution systems

NASA Astrophysics Data System (ADS)

Montero-Hernandez, Oscar C.

2001-07-01

The extensive use of electronic circuits has enabled modernization, automation, miniaturization, high quality, low cost, and other achievements regarding electric loads in the last decades. However, modern electronic circuits and systems are extremely sensitive to disturbances from the electric power supply. In fact, the rate at which these disturbances happen is considerable as has been documented in recent years. In response to the power quality concerns presented previously, this dissertation is proposing new approaches to provide ride-through for critical loads during voltage disturbances with emphasis on voltage sags. In this dissertation, a new approach based on an AC-DC-AC system is proposed to provide ride-through for critical loads connected in buildings and/or an industrial system. In this approach, a three-phase IGBT inverter with a built in Dc-link voltage regulator is suitably controlled along with static by-pass switches to provide continuous power to critical loads. During a disturbance, the input utility source is disconnected and the power from the inverter is connected to the load. The remaining voltage in the AC supply is converted to DC and compensated before being applied to the inverter and the load. After detecting normal utility conditions, power from the utility is restored to the critical load. In order to achieve an extended ride-through capability a second approach is introduced. In this case, the Dc-link voltage regulator is performed by a DC-DC Buck-Boost converter. This new approach has the capability to mitigate voltage variations below and above the nominal value. In the third approach presented in this dissertation, a three-phase AC to AC boost converter is investigated. This converter provides a boosting action for the utility input voltages, right before they are applied to the load. The proposed Pulse Width Modulation (PWM) control strategy ensures independent control of each phase and compensates for both single-phase or poly-phase voltage sags. Algorithms capable of detecting voltage disturbances such as voltage sags, voltage swells, flicker, frequency change, and harmonics in a fast and reliable way are investigated and developed in this dissertation as an essential part of the approaches previously described. Simulation and experimental work has been done to validate the feasibility of all approaches under the most common voltage disturbances such as single-phase voltage sags and three-phase voltage sags.

A respiratory compensating system: design and performance evaluation.

PubMed

Chuang, Ho-Chiao; Huang, Ding-Yang; Tien, Der-Chi; Wu, Ren-Hong; Hsu, Chung-Hsien

2014-05-08

This study proposes a respiratory compensating system which is mounted on the top of the treatment couch for reverse motion, opposite from the direction of the targets (diaphragm and hemostatic clip), in order to offset organ displacement generated by respiratory motion. Traditionally, in the treatment of cancer patients, doctors must increase the field size for radiation therapy of tumors because organs move with respiratory motion, which causes radiation-induced inflammation on the normal tissues (organ at risk (OAR)) while killing cancer cells, and thereby reducing the patient's quality of life. This study uses a strain gauge as a respiratory signal capture device to obtain abdomen respiratory signals, a proposed respiratory simulation system (RSS) and respiratory compensating system to experiment how to offset the organ displacement caused by respiratory movement and compensation effect. This study verifies the effect of the respiratory compensating system in offsetting the target displacement using two methods. The first method uses linac (medical linear accelerator) to irradiate a 300 cGy dose on the EBT film (GAFCHROMIC EBT film). The second method uses a strain gauge to capture the patients' respiratory signals, while using fluoroscopy to observe in vivo targets, such as a diaphragm, to enable the respiratory compensating system to offset the displacements of targets in superior-inferior (SI) direction. Testing results show that the RSS position error is approximately 0.45 ~ 1.42 mm, while the respiratory compensating system position error is approximately 0.48 ~ 1.42 mm. From the EBT film profiles based on different input to the RSS, the results suggest that when the input respiratory signals of RSS are sine wave signals, the average dose (%) in the target area is improved by 1.4% ~ 24.4%, and improved in the 95% isodose area by 15.3% ~ 76.9% after compensation. If the respiratory signals input into the RSS respiratory signals are actual human respiratory signals, the average dose (%) in the target area is improved by 31.8% ~ 67.7%, and improved in the 95% isodose area by 15.3% ~ 86.4% (the above rates of improvements will increase with increasing respiratory motion displacement) after compensation. The experimental results from the second method suggested that about 67.3% ~ 82.5% displacement can be offset. In addition, gamma passing rate after compensation can be improved to 100% only when the displacement of the respiratory motion is within 10 ~ 30 mm. This study proves that the proposed system can contribute to the compensation of organ displacement caused by respiratory motion, enabling physicians to use lower doses and smaller field sizes in the treatment of tumors of cancer patients.

A respiratory compensating system: design and performance evaluation

PubMed Central

Huang, Ding‐Yang; Tien, Der‐Chi; Wu, Ren‐Hong; Hsu, Chung‐Hsien

2014-01-01

This study proposes a respiratory compensating system which is mounted on the top of the treatment couch for reverse motion, opposite from the direction of the targets (diaphragm and hemostatic clip), in order to offset organ displacement generated by respiratory motion. Traditionally, in the treatment of cancer patients, doctors must increase the field size for radiation therapy of tumors because organs move with respiratory motion, which causes radiation‐induced inflammation on the normal tissues (organ at risk (OAR)) while killing cancer cells, and thereby reducing the patient's quality of life. This study uses a strain gauge as a respiratory signal capture device to obtain abdomen respiratory signals, a proposed respiratory simulation system (RSS) and respiratory compensating system to experiment how to offset the organ displacement caused by respiratory movement and compensation effect. This study verifies the effect of the respiratory compensating system in offsetting the target displacement using two methods. The first method uses linac (medical linear accelerator) to irradiate a 300 cGy dose on the EBT film (GAFCHROMIC EBT film). The second method uses a strain gauge to capture the patients' respiratory signals, while using fluoroscopy to observe in vivo targets, such as a diaphragm, to enable the respiratory compensating system to offset the displacements of targets in superior‐inferior (SI) direction. Testing results show that the RSS position error is approximately 0.45 ~ 1.42 mm, while the respiratory compensating system position error is approximately 0.48 ~ 1.42 mm. From the EBT film profiles based on different input to the RSS, the results suggest that when the input respiratory signals of RSS are sine wave signals, the average dose (%) in the target area is improved by 1.4% ~ 24.4%, and improved in the 95% isodose area by 15.3% ~ 76.9% after compensation. If the respiratory signals input into the RSS respiratory signals are actual human respiratory signals, the average dose (%) in the target area is improved by 31.8% ~ 67.7%, and improved in the 95% isodose area by 15.3% ~ 86.4% (the above rates of improvements will increase with increasing respiratory motion displacement) after compensation. The experimental results from the second method suggested that about 67.3% ~ 82.5% displacement can be offset. In addition, gamma passing rate after compensation can be improved to 100% only when the displacement of the respiratory motion is within 10 ~ 30 mm. This study proves that the proposed system can contribute to the compensation of organ displacement caused by respiratory motion, enabling physicians to use lower doses and smaller field sizes in the treatment of tumors of cancer patients. PACS number: 87.19. Wx; 87.55. Km PMID:24892345

Entirely relaxed lattice-mismatched GaSb/GaAs/Si(001) heterostructure grown via metalorganic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Ha, Minh Thien Huu; Hoang Huynh, Sa; Binh Do, Huy; Nguyen, Tuan Anh; Luc, Quang Ho; Lee, Ching Ting; Chang, Edward Yi

2018-05-01

A GaSb epilayer is grown on a GaAs/Si(001) epitaxial substrate via metalorganic chemical vapor deposition. High-resolution transmission electron microscopy micrographs and high-resolution X-ray reciprocal space mapping indicate an entirely relaxed interfacial misfit (IMF) array GaSb epilayer. The valence-band offset and conduction-band offset of the Al2O3/GaSb/GaAs/Si structure are estimated to be 2.39 and 3.65 eV, respectively. The fabricated Al2O3/p-GaSb/GaAs/Si MOS capacitors exhibited good capacitance–voltage characteristics with a small accumulation frequency dispersion of approximately 1.05% per decade. These results imply that the GaSb epilayer grown on the GaAs/Si platform in the IMF mode can be used for future complementary metal–oxide semiconductor applications.

Two-axis direct fluid shear stress sensor

NASA Technical Reports Server (NTRS)

Bajikar, Sateesh (Inventor); Scott, Michael A. (Inventor); Adcock, Edward E. (Inventor)

2011-01-01

A micro sized multi-axis semiconductor skin friction/wall shear stress induced by fluid flow. The sensor design includes a shear/strain transduction gimble connected to a force collecting plate located at the flow boundary surface. The shear force collecting plate is interconnected by an arm to offset the tortional hinges from the fluid flow. The arm is connected to the shear force collecting plate through dual axis torsional hinges with piezoresistive torsional strain gauges. These gauges are disposed on the tortional hinges and provide a voltage output indicative of applied shear stress acting on the force collection plate proximate the flow boundary surface. Offsetting the torsional hinges creates a force concentration and resolution structure that enables the generation of a large stress on the strain gauge from small shear stress, or small displacement of the collecting plate. The design also isolates the torsional sensors from exposure to the fluid flow.

Audio-frequency analysis of inductive voltage dividers based on structural models

DOE Office of Scientific and Technical Information (OSTI.GOV)

Avramov, S.; Oldham, N.M.; Koffman, A.D.

1994-12-31

A Binary Inductive Voltage Divider (BIVD) is compared with a Decade Inductive Voltage Divider (DIVD) in an automatic IVD bridge. New detection and injection circuitry was designed and used to evaluate the IVDs with either the input or output tied to ground potential. In the audio frequency range the DIVD and BIVD error patterns are characterized for both in-phase and quadrature components. Differences between results obtained using a new error decomposition scheme based on structural modeling, and measurements using conventional IVD standards are reported.

Static Characteristics of the Ferroelectric Transistor Inverter

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Bidirectional converter for high-efficiency fuel cell powertrain

NASA Astrophysics Data System (ADS)

Fardoun, Abbas A.; Ismail, Esam H.; Sabzali, Ahmad J.; Al-Saffar, Mustafa A.

2014-03-01

In this paper, a new wide conversion ratio step-up and step-down converter is presented. The proposed converter is derived from the conventional Single Ended Primary Inductor Converter (SEPIC) topology and it is integrated with a capacitor-diode voltage multiplier, which offers a simple structure, reduced electromagnetic interference (EMI), and reduced semiconductors' voltage stresses. Other advantages include: continuous input and output current, extended step-up and step-down voltage conversion ratio without extreme low or high duty-cycle, simple control circuitry, and near-zero input and output ripple currents compared to other converter topologies. The low charging/discharging current ripple and wide gain features result in a longer life-span and lower cost of the energy storage battery system. In addition, the "near-zero" ripple capability improves the fuel cell durability. Theoretical analysis results obtained with the proposed structure are compared with other bi-direction converter topologies. Simulation and experimental results are presented to verify the performance of the proposed bi-directional converter.

Operational amplifier with adjustable frequency response.

PubMed

Gulisek, D; Hencek, M

1978-01-01

The authors describe an operational amplifier with an adjustable frequency response and its use in membrane physiology, using the voltage clamp and current clamp method. The amplifier eliminates feedback poles causing oscillation. It consists of a follower with a high input resistance in the form of a tube and of an actual amplifier with an adjustable frequency response allowing the abolition of clicks by one pole and of oscillation by two poles in the 500 Hz divided by infinity range. Further properties of the amplifier: a long-term voltage drift of 1 mv, a temperature voltage drift of 0.5 mv/degrees K, input resistance greater than 1 GOhm, amplification greater than 80 dB, output +/- 12 v, 25 ma, noise, measured from the width of the oscilloscope track in the presence of a ray of normal brightness, not exceeding 50 muv in the 0-250 kHz band, f1 = 1 MHz. A short report on the amplifier was published a few years ago (Gulísek and Hencek 1973).

Acoustic Emission Characteristics of Nanocrystalline Porous Silicon Device Driven as an Ultrasonic Speaker

NASA Astrophysics Data System (ADS)

Tsubaki, Kenji; Komoda, Takuya; Koshida, Nobuyoshi

2006-04-01

It is shown that the dc-superimposed driving mode is more useful for the efficient operation of a novel thermally induced ultrasonic emitter based on nanocrystalline porous silicon (nc-PS) than the conventional simple ac-voltage driving mode. The nc-PS device is composed of a patterned heater electrode, an nc-PS layer and a single crystalline silicon (c-Si) substrate. The almost complete thermally insulating property of nc-PS as a quantum-sized system makes it possible to apply the nc-PS device as an ultrasonic generator by efficient thermo acoustic conversion without any mechanical vibrations. In the dc-superimposed driving mode, the output frequency is the same as the input frequency and a stationary temperature rise is kept constant independent of input peak-to-peak voltage. In addition, power efficiency is significantly increases compared with that in the ac-voltage driving mode without affecting on the temperature rise. The present results suggest the further possibility of the nc-PS device being used as a functional speaker.

Generalized Optoelectronic Model of Series-Connected Multijunction Solar Cells

DOE PAGES

Geisz, John F.; Steiner, Myles A.; Garcia, Ivan; ...

2015-10-02

The emission of light from each junction in a series-connected multijunction solar cell, we found, both complicates and elucidates the understanding of its performance under arbitrary conditions. Bringing together many recent advances in this understanding, we present a general 1-D model to describe luminescent coupling that arises from both voltage-driven electroluminescence and voltage-independent photoluminescence in nonideal junctions that include effects such as Sah-Noyce-Shockley (SNS) recombination with n ≠ 2, Auger recombination, shunt resistance, reverse-bias breakdown, series resistance, and significant dark area losses. The individual junction voltages and currents are experimentally determined from measured optical and electrical inputs and outputs ofmore » the device within the context of the model to fit parameters that describe the devices performance under arbitrary input conditions. Furthermore, our techniques to experimentally fit the model are demonstrated for a four-junction inverted metamorphic solar cell, and the predictions of the model are compared with concentrator flash measurements.« less

Optimum Design of LLC Resonant Converter using Inductance Ratio (Lm/Lr)

NASA Astrophysics Data System (ADS)

Palle, Kowstubha; Krishnaveni, K.; Ramesh Reddy, Kolli

2017-06-01

The main benefits of LLC resonant dc/dc converter over conventional series and parallel resonant converters are its light load regulation, less circulating currents, larger bandwidth for zero voltage switching, and less tuning of switching frequency for controlled output. An unique analytical tool, called fundamental harmonic approximation with peak gain adjustment is used for designing the converter. In this paper, an optimum design of the converter is proposed by considering three different design criterions with different values of inductance ratio (Lm/Lr) to achieve good efficiency at high input voltage. The optimum design includes the analysis in operating range, switching frequency range, primary side losses of a switch and stability. The analysis is carried out with simulation using the software tools like MATLAB and PSIM. The performance of the optimized design is demonstrated for a design specification of 12 V, 5 A output operating with an input voltage range of 300-400 V using FSFR 2100 IC of Texas instruments.

Rhenium Disulfide Depletion-Load Inverter

NASA Astrophysics Data System (ADS)

McClellan, Connor; Corbet, Chris; Rai, Amritesh; Movva, Hema C. P.; Tutuc, Emanuel; Banerjee, Sanjay K.

2015-03-01

Many semiconducting Transition Metal Dichalcogenide (TMD) materials have been effectively used to create Field-Effect Transistor (FET) devices but have yet to be used in logic designs. We constructed a depletion-load voltage inverter using ultrathin layers of Rhenium Disulfide (ReS2) as the semiconducting channel. This ReS2 inverter was fabricated on a single micromechanically-exfoliated flake of ReS2. Electron beam lithography and physical vapor deposition were used to construct Cr/Au electrical contacts, an Alumina top-gate dielectric, and metal top-gate electrodes. By using both low (Aluminum) and high (Palladium) work-function metals as two separate top-gates on a single ReS2 flake, we create a dual-gated depletion mode (D-mode) and enhancement mode (E-mode) FETs in series. Both FETs displayed current saturation in the output characteristics as a result of the FET ``pinch-off'' mechanism and On/Off current ratios of 105. Field-effect mobilities of 23 and 17 cm2V-1s-1 and subthreshold swings of 97 and 551 mV/decade were calculated for the E-mode and D-mode FETs, respectively. With a supply voltage of 1V, at low/negative input voltages the inverter output was at a high logic state of 900 mV. Conversely with high/positive input voltages, the inverter output was at a low logic state of 500 mV. The inversion of the input signal demonstrates the potential for using ReS2 in future integrated circuit designs and the versatility of depletion-load logic devices for TMD research. NRI SWAN Center and ARL STTR Program.

Prediction of Trace Element based Energizing Sensor Control System using PWM

NASA Astrophysics Data System (ADS)

Zukri, Mohammad Nizar Bin Mohamed; Abu Bakar, Elmi Bin; Uchiyama, Naoki; Abdullah, Mohamad Nazir Bin

2018-05-01

A real-time system for field-work monitoring wastewater laden with heavy metal in industrial discharge through wireless communication network was developed. The monitoring system poses an interesting challenge in order to determine existing metal ion in the solution whereas the previous result only consider total dissolve ion. This paper aims to distinguish the metal ion based on reaction determination in solution. The control algorithm was implemented as generating voltage input for energize conductivity sensor since the voltage corresponding to oxidation and reaction based on standard reduction potential. Implementation of ATmega2560 microcontroller for control voltage fed on sensor equivalent to controlling the PWM duty cycle. PID controller was designed uses a microcontroller (Arduino) platform with manual tuning for identify reaction process and sufficient voltage input. From the experimental result, is found that the proposed PI controller has excellent tracking and measurement performance. Low-pass filter was applied in programming to make the system understand that signal has achieved stable. The development of hardware and software of the closed loop system has an enhancement of measurement performance and high feasibility for SME’s company in economic point of view. The desired objective is to achieve a system with the stable measurement and sufficient voltage supply. This system will provide an accurate and precise control efficiently without using costly component and complicated circuit.

Ultra-low-power conversion and management techniques for thermoelectric energy harvesting applications

NASA Astrophysics Data System (ADS)

Fleming, Jerry W.

2010-04-01

Thermoelectric energy harvesting has increasingly gained acceptance as a potential power source that can be used for numerous commercial and military applications. However, power electronic designers have struggled to incorporate energy harvesting methods into their designs due to the relatively small voltage levels available from many harvesting device technologies. In order to bridge this gap, an ultra-low input voltage power conversion method is needed to convert small amounts of scavenged energy into a usable form of electricity. Such a method would be an enabler for new and improved medical devices, sensor systems, and other portable electronic products. This paper addresses the technical challenges involved in ultra-low-voltage power conversion by providing a solution utilizing novel power conversion techniques and applied technologies. Our solution utilizes intelligent power management techniques to control unknown startup conditions. The load and supply management functionality is also controlled in a deterministic manner. The DC to DC converter input operating voltage is 20mV with a conversion efficiency of 90% or more. The output voltage is stored into a storage device such as an ultra-capacitor or lithium-ion battery for use during brown-out or unfavorable harvesting conditions. Applications requiring modular, low power, extended maintenance cycles, such as wireless instrumentation would significantly benefit from the novel power conversion and harvesting techniques outlined in this paper.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

High temperature current mirror amplifier

DOEpatents

Patterson, R.B. III.

1984-05-22

Disclosed is a high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg. 2 figs.

Low-noise pulse conditioner

DOEpatents

Bird, D.A.

1981-06-16

A low-noise pulse conditioner is provided for driving electronic digital processing circuitry directly from differentially induced input pulses. The circuit uses a unique differential-to-peak detector circuit to generate a dynamic reference signal proportional to the input peak voltage. The input pulses are compared with the reference signal in an input network which operates in full differential mode with only a passive input filter. This reduces the introduction of circuit-induced noise, or jitter, generated in ground referenced input elements normally used in pulse conditioning circuits, especially speed transducer processing circuits. This circuit may be used for conditioning the sensor signal from the Fidler coil in a gas centrifuge for separation of isotopic gaseous mixtures.

Synaptic control of the shape of the motoneuron pool input-output function

PubMed Central

Heckman, Charles J.

2017-01-01

Although motoneurons have often been considered to be fairly linear transducers of synaptic input, recent evidence suggests that strong persistent inward currents (PICs) in motoneurons allow neuromodulatory and inhibitory synaptic inputs to induce large nonlinearities in the relation between the level of excitatory input and motor output. To try to estimate the possible extent of this nonlinearity, we developed a pool of model motoneurons designed to replicate the characteristics of motoneuron input-output properties measured in medial gastrocnemius motoneurons in the decerebrate cat with voltage-clamp and current-clamp techniques. We drove the model pool with a range of synaptic inputs consisting of various mixtures of excitation, inhibition, and neuromodulation. We then looked at the relation between excitatory drive and total pool output. Our results revealed that the PICs not only enhance gain but also induce a strong nonlinearity in the relation between the average firing rate of the motoneuron pool and the level of excitatory input. The relation between the total simulated force output and input was somewhat more linear because of higher force outputs in later-recruited units. We also found that the nonlinearity can be increased by increasing neuromodulatory input and/or balanced inhibitory input and minimized by a reciprocal, push-pull pattern of inhibition. We consider the possibility that a flexible input-output function may allow motor output to be tuned to match the widely varying demands of the normal motor repertoire. NEW & NOTEWORTHY Motoneuron activity is generally considered to reflect the level of excitatory drive. However, the activation of voltage-dependent intrinsic conductances can distort the relation between excitatory drive and the total output of a pool of motoneurons. Using a pool of realistic motoneuron models, we show that pool output can be a highly nonlinear function of synaptic input but linearity can be achieved through adjusting the time course of excitatory and inhibitory synaptic inputs. PMID:28053245

Closed-loop analysis and control of a non-inverting buck-boost converter

NASA Astrophysics Data System (ADS)

Chen, Zengshi; Hu, Jiangang; Gao, Wenzhong

2010-11-01

In this article, a cascade controller is designed and analysed for a non-inverting buck-boost converter. The fast inner current loop uses sliding mode control. The slow outer voltage loop uses the proportional-integral (PI) control. Stability analysis and selection of PI gains are based on the nonlinear closed-loop error dynamics incorporating both the inner and outer loop controllers. The closed-loop system is proven to have a nonminimum phase structure. The voltage transient due to step changes of input voltage or resistance is predictable. The operating range of the reference voltage is discussed. The controller is validated by a simulation circuit. The simulation results show that the reference output voltage is well-tracked under system uncertainties or disturbances, confirming the validity of the proposed controller.

Nanowire NMOS Logic Inverter Characterization.

PubMed

Hashim, Yasir

2016-06-01

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Does soil C accrual under perennial grasses managed for bioenergy offset fertilizer induced N2O emission?

USDA-ARS?s Scientific Manuscript database

Perennial grasses (e.g., switchgrass (Panicum virgatum L.) and big bluestem (Andropogon gerdardii Vitman) are often touted as being low input and as having a C-neutral foot print, but managing them as bioenergy feedstock means adding nitrogenous fertilizer or inter-cropping with legumes, which can i...

[Comparative study of unidirectional transducers for invasive blood pressure monitoring].

PubMed

Matzek, F; Boenick, U; Frucht, U; Schroeder, P M

1989-03-01

This paper reports on the results of a study in which the offset drift, sensitivity error and drift, as well as the linearity error of six DPT's were investigated under normal ambient conditions and varying conditions of temperature, light, operating time and variation of supply voltage. In addition, the dynamic response, and the influence of storage at extreme temperatures, and resterilisation, was examined. The electrical and mechanical safety/reliability of DPT's was also investigated. The results obtained are compared.

First principles calculations of La2O3/GaAs interface properties under biaxial strain and hydrostatic pressure

NASA Astrophysics Data System (ADS)

Shi, Li-Bin; Li, Ming-Biao; Xiu, Xiao-Ming; Liu, Xu-Yang; Zhang, Kai-Cheng; Li, Chun-Ran; Dong, Hai-Kuan

2017-04-01

La2O3 is a potential dielectric material with high permittivity (high-κ) for metal-oxide-semiconductor (MOS) devices. However, band offsets and oxide defects should still be concerned. Smaller band offsets and carrier traps increase leakage current, and degenerate performance of the devices. In this paper, the interface behaviors of La2O3/GaAs under biaxial strain and hydrostatic pressure are investigated, which is performed by first principles calculations based on density functional theory (DFT). Strain engineering is attempted to improve performance of the metal/La2O3/GaAs devices. First of all, we creatively realize band alignment of La2O3/GaAs interface under biaxial strain and hydrostatic pressure. The proper biaxial tensile strain can effectively increase valence band offsets (VBO) and conduction band offsets (CBO), which can be used to suppress leakage current. However, the VBO will decrease with the increase of hydrostatic pressure, indicating that performance of the devices is degenerated. Then, a direct tunneling leakage current model is used to investigate current and voltage characteristics of the metal/La2O3/GaAs. The impact of biaxial strain and hydrostatic pressure on leakage current is discussed. At last, formation energies and transition levels of oxygen interstitial (Oi) and oxygen vacancy (VO) in La2O3 are assessed. We investigate how they will affect performance of the devices.

Control and Optimization of Regenerative Power Flow in 21st Century Airlifters

DTIC Science & Technology

2001-12-01

Figure 3.14. 32 R,=50 Li V , Input Voltage Respose Output Voltage Response’ vaAvB< 40V AVណ t t Figure 3.14. Time domain constraints for the converter...as it will influence the rate of rise of the current pulse. In the current work, L is limited to Self -inductance of the entire assembly is found under

Southern San Andreas Fault evaluation field activity: approaches to measuring small geomorphic offsets--challenges and recommendations for active fault studies

USGS Publications Warehouse

Scharer, Katherine M.; Salisbury, J. Barrett; Arrowsmith, J. Ramon; Rockwell, Thomas K.

2014-01-01

In southern California, where fast slip rates and sparse vegetation contribute to crisp expression of faults and microtopography, field and high‐resolution topographic data (<1  m/pixel) increasingly are used to investigate the mark left by large earthquakes on the landscape (e.g., Zielke et al., 2010; Zielke et al., 2012; Salisbury, Rockwell, et al., 2012, Madden et al., 2013). These studies measure offset streams or other geomorphic features along a stretch of a fault, analyze the offset values for concentrations or trends along strike, and infer that the common magnitudes reflect successive surface‐rupturing earthquakes along that fault section. Wallace (1968) introduced the use of such offsets, and the challenges in interpreting their “unique complex history” with offsets on the Carrizo section of the San Andreas fault; these were more fully mapped by Sieh (1978) and followed by similar field studies along other faults (e.g., Lindvall et al., 1989; McGill and Sieh, 1991). Results from such compilations spurred the development of classic fault behavior models, notably the characteristic earthquake and slip‐patch models, and thus constitute an important component of the long‐standing contrast between magnitude–frequency models (Schwartz and Coppersmith, 1984; Sieh, 1996; Hecker et al., 2013). The proliferation of offset datasets has led earthquake geologists to examine the methods and approaches for measuring these offsets, uncertainties associated with measurement of such features, and quality ranking schemes (Arrowsmith and Rockwell, 2012; Salisbury, Arrowsmith, et al., 2012; Gold et al., 2013; Madden et al., 2013). In light of this, the Southern San Andreas Fault Evaluation (SoSAFE) project at the Southern California Earthquake Center (SCEC) organized a combined field activity and workshop (the “Fieldshop”) to measure offsets, compare techniques, and explore differences in interpretation. A thorough analysis of the measurements from the field activity will be provided separately; this paper discusses the complications presented by such offset measurements using two channels from the San Andreas fault as illustrative cases. We conclude with best approaches for future data collection efforts based on input from the Fieldshop.

250 kV 6 mA compact Cockcroft-Walton high-voltage power supply.

PubMed

Ma, Zhan-Wen; Su, Xiao-Dong; Lu, Xiao-Long; Wei, Zhen; Wang, Jun-Run; Huang, Zhi-Wu; Miao, Tian-You; Su, Tong-Ling; Yao, Ze-En

2016-08-01

A compact power supply system for a compact neutron generator has been developed. A 4-stage symmetrical Cockcroft-Walton circuit is adopted to produce 250 kV direct current high-voltage. A 2-stage 280 kV isolation transformer system is used to drive the ion source power supply. For a compact structure, safety, and reliability during the operation, the Cockcroft-Walton circuit and the isolation transformer system are enclosed in an epoxy vessel containing the transformer oil whose size is about ∅350 mm × 766 mm. Test results indicate that the maximum output voltage of the power supply is 282 kV, and the stability of the output voltage is better than 0.63% when the high voltage power supply is operated at 250 kV, 6.9 mA with the input voltage varying ±10%.

PV source based high voltage gain current fed converter

NASA Astrophysics Data System (ADS)

Saha, Soumya; Poddar, Sahityika; Chimonyo, Kudzai B.; Arunkumar, G.; Elangovan, D.

2017-11-01

This work involves designing and simulation of a PV source based high voltage gain, current fed converter. It deals with an isolated DC-DC converter which utilizes boost converter topology. The proposed converter is capable of high voltage gain and above all have very high efficiency levels as proved by the simulation results. The project intends to produce an output of 800 V dc from a 48 V dc input. The simulation results obtained from PSIM application interface were used to analyze the performance of the proposed converter. Transformer used in the circuit steps up the voltage as well as to provide electrical isolation between the low voltage and high voltage side. Since the converter involves high switching frequency of 100 kHz, ultrafast recovery diodes are employed in the circuitry. The major application of the project is for future modeling of solar powered electric hybrid cars.

250 kV 6 mA compact Cockcroft-Walton high-voltage power supply

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ma, Zhan-Wen; Su, Xiao-Dong; Wei, Zhen

A compact power supply system for a compact neutron generator has been developed. A 4-stage symmetrical Cockcroft-Walton circuit is adopted to produce 250 kV direct current high-voltage. A 2-stage 280 kV isolation transformer system is used to drive the ion source power supply. For a compact structure, safety, and reliability during the operation, the Cockcroft-Walton circuit and the isolation transformer system are enclosed in an epoxy vessel containing the transformer oil whose size is about ∅350 mm × 766 mm. Test results indicate that the maximum output voltage of the power supply is 282 kV, and the stability of themore » output voltage is better than 0.63% when the high voltage power supply is operated at 250 kV, 6.9 mA with the input voltage varying ±10%.« less

Device for modular input high-speed multi-channel digitizing of electrical data

DOEpatents

VanDeusen, Alan L.; Crist, Charles E.

1995-09-26

A multi-channel high-speed digitizer module converts a plurality of analog signals to digital signals (digitizing) and stores the signals in a memory device. The analog input channels are digitized simultaneously at high speed with a relatively large number of on-board memory data points per channel. The module provides an automated calibration based upon a single voltage reference source. Low signal noise at such a high density and sample rate is accomplished by ensuring the A/D converters are clocked at the same point in the noise cycle each time so that synchronous noise sampling occurs. This sampling process, in conjunction with an automated calibration, yields signal noise levels well below the noise level present on the analog reference voltages.

Power supply standardization and optimization study

NASA Technical Reports Server (NTRS)

Ware, C. L.; Ragusa, E. V.

1972-01-01

A comprehensive design study of a power supply for use in the space shuttle and other space flight applications is presented. The design specifications are established for a power supply capable of supplying over 90 percent of the anticipated voltage requirements for future spacecraft avionics systems. Analyses and tradeoff studies were performed on several alternative design approaches to assure that the selected design would provide near optimum performance of the planned applications. The selected design uses a dc-to-dc converter incorporating regenerative current feedback with a time-ratio controlled duty cycle to achieve high efficiency over a wide variation in input voltage and output loads. The packaging concept uses an expandable mainframe capable of accommodating up to six inverter/regulator modules with one common input filter module.

Performance of a 14.9-kW laminated-frame dc series motor with chopper controller

NASA Technical Reports Server (NTRS)

Schwab, J. R.

1979-01-01

Traction motor using two types of excitation: ripple free dc from a motor generator set for baseline data and chopped dc as supplied by a battery and chopper controller was tested. For the same average values of input voltage and current, the power output was independent of the type of excitation. At the same speeds, motor efficiency at low power output (corresponding to low duty cycle of the controller) was 5 to 10 percentage points less on chopped dc than on ripple-free dc. This illustrates that for chopped waveforms, it is incorrect to calculate input power as the product of average voltage and average current. Locked-rotor torque, no load losses, and magnetic saturation data were so determined.

Real time speech formant analyzer and display

DOEpatents

Holland, George E.; Struve, Walter S.; Homer, John F.

1987-01-01

A speech analyzer for interpretation of sound includes a sound input which converts the sound into a signal representing the sound. The signal is passed through a plurality of frequency pass filters to derive a plurality of frequency formants. These formants are converted to voltage signals by frequency-to-voltage converters and then are prepared for visual display in continuous real time. Parameters from the inputted sound are also derived and displayed. The display may then be interpreted by the user. The preferred embodiment includes a microprocessor which is interfaced with a television set for displaying of the sound formants. The microprocessor software enables the sound analyzer to present a variety of display modes for interpretive and therapeutic used by the user.

Real time speech formant analyzer and display

DOEpatents

Holland, G.E.; Struve, W.S.; Homer, J.F.

1987-02-03

A speech analyzer for interpretation of sound includes a sound input which converts the sound into a signal representing the sound. The signal is passed through a plurality of frequency pass filters to derive a plurality of frequency formants. These formants are converted to voltage signals by frequency-to-voltage converters and then are prepared for visual display in continuous real time. Parameters from the inputted sound are also derived and displayed. The display may then be interpreted by the user. The preferred embodiment includes a microprocessor which is interfaced with a television set for displaying of the sound formants. The microprocessor software enables the sound analyzer to present a variety of display modes for interpretive and therapeutic used by the user. 19 figs.

A zero-voltage-switched three-phase interleaved buck converter

NASA Astrophysics Data System (ADS)

Hsieh, Yao-Ching; Huang, Bing-Siang; Lin, Jing-Yuan; Pham, Phu Hieu; Chen, Po-Hao; Chiu, Huang-Jen

2018-04-01

This paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.

Neuronal Spike Timing Adaptation Described with a Fractional Leaky Integrate-and-Fire Model

PubMed Central

Teka, Wondimu; Marinov, Toma M.; Santamaria, Fidel

2014-01-01

The voltage trace of neuronal activities can follow multiple timescale dynamics that arise from correlated membrane conductances. Such processes can result in power-law behavior in which the membrane voltage cannot be characterized with a single time constant. The emergent effect of these membrane correlations is a non-Markovian process that can be modeled with a fractional derivative. A fractional derivative is a non-local process in which the value of the variable is determined by integrating a temporal weighted voltage trace, also called the memory trace. Here we developed and analyzed a fractional leaky integrate-and-fire model in which the exponent of the fractional derivative can vary from 0 to 1, with 1 representing the normal derivative. As the exponent of the fractional derivative decreases, the weights of the voltage trace increase. Thus, the value of the voltage is increasingly correlated with the trajectory of the voltage in the past. By varying only the fractional exponent, our model can reproduce upward and downward spike adaptations found experimentally in neocortical pyramidal cells and tectal neurons in vitro. The model also produces spikes with longer first-spike latency and high inter-spike variability with power-law distribution. We further analyze spike adaptation and the responses to noisy and oscillatory input. The fractional model generates reliable spike patterns in response to noisy input. Overall, the spiking activity of the fractional leaky integrate-and-fire model deviates from the spiking activity of the Markovian model and reflects the temporal accumulated intrinsic membrane dynamics that affect the response of the neuron to external stimulation. PMID:24675903

Tools for Physiology Labs: Inexpensive Equipment for Physiological Stimulation

PubMed Central

Land, Bruce R.; Johnson, Bruce R.; Wyttenbach, Robert A.; Hoy, Ronald R.

2004-01-01

We describe the design of inexpensive equipment and software for physiological stimulation in the neurobiology teaching laboratory. The core component is a stimulus isolation unit (SIU) that uses DC-DC converters, rather than expensive high-voltage batteries, to generate isolated power at high voltage. The SIU has no offset when inactive and produces pulses up to 100 V with moderately fast (50 μs) rise times. We also describe two methods of stimulus timing control. The first is a simplified conventional, stand-alone analog pulse generator. The second uses a digital microcontroller interfaced with a personal computer. The SIU has performed well and withstood intensive use in our undergraduate physiology laboratory. This project is part of our ongoing effort to make reliable low-cost physiology equipment available for both student teaching and faculty research laboratories. PMID:23493817

Characterization of Low Noise, Precision Voltage Reference REF5025-HT Under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

The performance of Texas Instruments precision voltage reference REF5025-HT was assessed under extreme temperatures. This low noise, 2.5 V output chip is suitable for use in high temperature down-hole drilling applications, but no data existed on its performance at cryogenic temperatures. The device was characterized in terms of output voltage and supply current at different input voltage levels as a function of temperature between +210 C and -190 C. Line and load regulation characteristics were also established at six load levels and at different temperatures. Restart capability at extreme temperatures and the effects of thermal cycling, covering the test temperature range, on its operation and stability were also investigated. Under no load condition, the voltage reference chip exhibited good stability in its output over the temperature range of -50 C to +200 C. Outside that temperature range, output voltage did change as temperature was changed. For example, at the extreme temperatures of +210 C and - 190 C, the output level dropped to 2.43 V and 2.32 V, respectively as compared to the nominal value of 2.5 V. At cryogenic test temperatures of -100 C and -150 C the output voltage dropped by about 20%. The quiescent supply current of the voltage reference varied slightly with temperature but remained close to its specified value. In terms of line regulation, the device exhibited excellent stability between -50 C and +150 C over the entire input voltage range and load levels. At the other test temperatures, however, while line regulation became poor at cryogenic temperatures of -100 C and below, it suffered slight degradation at the extreme high temperature but only at the high load level of 10 mA. The voltage reference also exhibited very good load regulation with temperature down to -100 C, but its output dropped sharply at +210 C only at the heavy load of 10 mA. The semiconductor chip was able restart at the extreme temperatures of -190 C and +210 C, and the limited thermal cycling did not influence its characteristics and had no impact on its packaging as no structural or physical damage was observed.

Digitized synchronous demodulator

NASA Technical Reports Server (NTRS)

Woodhouse, Christopher E. (Inventor)

1990-01-01

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors.

Direct Current Amplifier. Report No. 92; AMPLIFICADOR DE CORRIENTE CONTINUA. Informe No. 92

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marazzi, C.

1963-01-01

A direct-current amplifier with low zero current and solid-state chopper for input is described. This amplifier can be used in control circuits and for general applications such as temperature measurement in thermocouples, amplifier for a photo-sensitive element, or zero amplifier in control systems. The input impedance is relatively low, serving principally as current amplifier. It is possible to obtain a symmetry characteristic for positive and negative values of the output voltage with respect to the input. (tr-auth)

Numerical investigation of the effect of driving voltage pulse shapes on the characteristics of low-pressure argon dielectric barrier discharge

DOE Office of Scientific and Technical Information (OSTI.GOV)

Eslami, E., E-mail: eeslami@iust.ac.ir; Barjasteh, A.; Morshedian, N.

2015-06-15

In this work, we numerically compare the effect of a sinusoidal, triangular, and rectangular pulsed voltage profile on the calculated particle production, electric current, and gas voltage in a dielectric barrier discharge. The total argon gas pressure of 400 Pa, the distance between dielectrics of 5 mm, the dielectric thickness of 0.7 mm, and the temperature of T = 300 K were considered as input parameters. The different driving voltage pulse shapes (triangular, rectangular, and sinusoidal) are considered as applied voltage with a frequency of 7 kHz and an amplitude of 700 V peak to peak. It is shown thatmore » applying a rectangular voltage, as compared with a sinusoidal or triangle voltage, increases the current peak, while the peak width is decreased. Higher current density is related to high production of charged particles, which leads to the generation of some highly active species, such as Ar* (4s level), and Ar** (4p level) in the gap.« less

Operation of a homeostatic sleep switch.

PubMed

Pimentel, Diogo; Donlea, Jeffrey M; Talbot, Clifford B; Song, Seoho M; Thurston, Alexander J F; Miesenböck, Gero

2016-08-18

Sleep disconnects animals from the external world, at considerable risks and costs that must be offset by a vital benefit. Insight into this mysterious benefit will come from understanding sleep homeostasis: to monitor sleep need, an internal bookkeeper must track physiological changes that are linked to the core function of sleep. In Drosophila, a crucial component of the machinery for sleep homeostasis is a cluster of neurons innervating the dorsal fan-shaped body (dFB) of the central complex. Artificial activation of these cells induces sleep, whereas reductions in excitability cause insomnia. dFB neurons in sleep-deprived flies tend to be electrically active, with high input resistances and long membrane time constants, while neurons in rested flies tend to be electrically silent. Correlative evidence thus supports the simple view that homeostatic sleep control works by switching sleep-promoting neurons between active and quiescent states. Here we demonstrate state switching by dFB neurons, identify dopamine as a neuromodulator that operates the switch, and delineate the switching mechanism. Arousing dopamine caused transient hyperpolarization of dFB neurons within tens of milliseconds and lasting excitability suppression within minutes. Both effects were transduced by Dop1R2 receptors and mediated by potassium conductances. The switch to electrical silence involved the downregulation of voltage-gated A-type currents carried by Shaker and Shab, and the upregulation of voltage-independent leak currents through a two-pore-domain potassium channel that we term Sandman. Sandman is encoded by the CG8713 gene and translocates to the plasma membrane in response to dopamine. dFB-restricted interference with the expression of Shaker or Sandman decreased or increased sleep, respectively, by slowing the repetitive discharge of dFB neurons in the ON state or blocking their entry into the OFF state. Biophysical changes in a small population of neurons are thus linked to the control of sleep-wake state.

Time maintenance system for the BMDO MSX spacecraft

NASA Technical Reports Server (NTRS)

Hermes, Martin J.

1994-01-01

The Johns Hopkins University Applied Physics Laboratory (APL) is responsible for designing and implementing a clock maintenance system for the Ballistic Missile Defense Organizations (BMDO) Midcourse Space Experiment (MSX) spacecraft. The MSX spacecraft has an on-board clock that will be used to control execution of time-dependent commands and to time tag all science and housekeeping data received from the spacecraft. MSX mission objectives have dictated that this spacecraft time, UTC(MSX), maintain a required accuracy with respect to UTC(USNO) of +/- 10 ms with a +/- 1 ms desired accuracy. APL's atomic time standards and the downlinked spacecraft time were used to develop a time maintenance system that will estimate the current MSX clock time offset during an APL pass and make estimates of the clock's drift and aging using the offset estimates from many passes. Using this information, the clock's accuracy will be maintained by uplinking periodic clock correction commands. The resulting time maintenance system is a combination of offset measurement, command/telemetry, and mission planning hardware and computing assets. All assets provide necessary inputs for deciding when corrections to the MSX spacecraft clock must be made to maintain its required accuracy without inhibiting other mission objectives. The MSX time maintenance system is described as a whole and the clock offset measurement subsystem, a unique combination of precision time maintenance and measurement hardware controlled by a Macintosh computer, is detailed. Simulations show that the system estimates the MSX clock offset to less than+/- 33 microseconds.

Heterojunction p-Cu2O/n-Ga2O3 diode with high breakdown voltage

NASA Astrophysics Data System (ADS)

Watahiki, Tatsuro; Yuda, Yohei; Furukawa, Akihiko; Yamamuka, Mikio; Takiguchi, Yuki; Miyajima, Shinsuke

2017-11-01

Heterojunction p-Cu2O/n-β-Ga2O3 diodes were fabricated on an epitaxially grown β-Ga2O3(001) layer. The reverse breakdown voltage of these p-n diodes reached 1.49 kV with a specific on-resistance of 8.2 mΩ cm2. The leakage current of the p-n diodes was lower than that of the Schottky barrier diode due to the higher barrier height against the electron. The ideality factor of the p-n diode was 1.31. It indicated that some portion of the recombination current at the interface contributed to the forward current, but the diffusion current was the dominant. The forward current more than 100 A/cm2 indicated the lower conduction band offset at the hetero-interface between Cu2O and Ga2O3 layers than that predicted from the bulk properties, resulting in such a high forward current without limitation. These results open the possibility of advanced device structures for wide bandgap Ga2O3 to achieve higher breakdown voltage and lower on-resistance.

A 0.7 V 6.66-9.36 GHz wide tuning range CMOS LC VCO with small chip size

NASA Astrophysics Data System (ADS)

Chen, Jun-Da; Zhang, Jie

2017-10-01

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is -110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about -1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about -180.7 and -191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.

Study of electron mobility in small molecular SAlq by transient electroluminescence method

NASA Astrophysics Data System (ADS)

Kumar, Pankaj; Jain, S. C.; Kumar, Vikram; Chand, Suresh; Kamalasanan, M. N.; Tandon, R. P.

2007-12-01

The study of electron mobility of bis(2-methyl 8-hydroxyquinoline) (triphenyl siloxy) aluminium (SAlq) by transient electroluminescence (EL) is presented. An EL device is fabricated in bilayer, ITO/N,N'-diphenyl-N, N'-bis(3-methylphenyl)-(1,1'-biphenyl)-4,4'-diamine (TPD)/SAlq/LiF/Al configuration. The temporal evaluation of the EL with respect to the step voltage pulse is characterized by a delay time followed by a fast initial rise, which is followed by a slower rise. The delay time between the applied electrical pulse and the onset of EL is correlated with the carrier mobility (electron in our case). Transient EL studies for SAlq have been carried out at different temperatures and different applied electric fields. The electron mobility in SAlq is found to be field and temperature dependent and calculated to be 6.9 × 10-7 cm2 V-1 s-1 at 2.5 × 106 V cm-1 and 308 K. The EL decays immediately as the voltage is turned off and does not depend on the amplitude of the applied voltage pulse or dc offset.

Advanced Power Conditioning System

NASA Technical Reports Server (NTRS)

Johnson, N. L.

1971-01-01

The second portion of the advanced power conditioning system development program is reported. Five 100-watt parallel power stages with majority-vote-logic feedback-regulator were breadboarded and tested to the design goals. The input voltage range was 22.1 to 57.4 volts at loads from zero to 500 watts. The maximum input ripple current was 200 mA pk-pk (not including spikes) at 511 watts load; the output voltage was 56V dc with a maximum change of 0.89 volts for all variations of line, load, and temperature; the maximum output ripple was 320 mV pk-pk at 512 watts load (dependent on filter capacitance value); the maximum efficiency was 93.9% at 212 watts and 50V dc input; the minimum efficiency was 87.2% at 80-watt load and 50V dc input; the efficiency was above 90% from 102 watts to 372 watts; the maximum excursion for an 80-watt load change was 2.1 volts with a recovery time of 7 milliseconds; and the unit performed within regulation limits from -20 C to +85 C. During the test sequence, margin tests and failure mode tests were run with no resulting degradation in performance.

Extended performance solar electric propulsion thrust system study. Volume 5. Capacitor-diode voltage multiplier: Technology evaluation

NASA Technical Reports Server (NTRS)

Martinelli, R. M.

1977-01-01

A 1-kW capacitor-diode voltage multiplier (CDVM) was designed, fabricated and tested to demonstrate the power of feasibility of high power CDVM's and to verify the analytical techniques that had been used to predict the performance characteristics of a 6-kw CDVM. High efficiency (96.2%), a low ratio of component weight to power (0.55 kg/kW), and low output ripple voltage (less than 1%, peak to peak) were obtained during the operation of a 1-kW CDVM various input line, load current, and load fault conditions.

Scalable Low-Power Deep Machine Learning with Analog Computation

DTIC Science & Technology

2013-07-19

transimpedance amplifier (TIA) that measures the output current 7 V Cf Vbias MP1 MN1 Vdd = 3 V 2.5 V 2.6 V + − Vox = 4.4 V 0.1 V + − 7 V Cf Vbias MP1 MN1 Vddt... amplifier . The amplifier has Cf as its feedback capacitor and the FG voltage Vfg as its input. The two MUXs at the sources of MP1 and MP2 control the...as a simple operational transconductor amplifier (OTA), converts voltage Vout to output current Iout. Vref determines the nominal voltage of Vout

Noise screen for attitude control system

NASA Technical Reports Server (NTRS)

Rodden, John J. (Inventor); Stevens, Homer D. (Inventor); Hong, David P. (Inventor); Hirschberg, Philip C. (Inventor)

2002-01-01

An attitude control system comprising a controller and a noise screen device coupled to the controller. The controller is adapted to control an attitude of a vehicle carrying an actuator system that is adapted to pulse in metered bursts in order to generate a control torque to control the attitude of the vehicle in response to a control pulse. The noise screen device is adapted to generate a noise screen signal in response to the control pulse that is generated when an input attitude error signal exceeds a predetermined deadband attitude level. The noise screen signal comprises a decaying offset signal that when combined with the attitude error input signal results in a net attitude error input signal away from the predetermined deadband level to reduce further control pulse generation.

RESONANT CAVITY EXCITATION SYSTEM

DOEpatents

Baker, W.R.; Kerns, Q.A.; Riedel, J.

1959-01-13

An apparatus is presented for exciting a cavity resonator with a minimum of difficulty and, more specifically describes a sub-exciter and an amplifier type pre-exciter for the high-frequency cxcitation of large cavities. Instead of applying full voltage to the main oscillator, a sub-excitation voltage is initially used to establish a base level of oscillation in the cavity. A portion of the cavity encrgy is coupled to the input of the pre-exciter where it is amplified and fed back into the cavity when the pre-exciter is energized. After the voltage in the cavity resonator has reached maximum value under excitation by the pre-exciter, full voltage is applied to the oscillator and the pre-exciter is tunned off. The cavity is then excited to the maximum high voltage value of radio frequency by the oscillator.

A high-voltage supply used on miniaturized RLG

NASA Astrophysics Data System (ADS)

Miao, Zhifei; Fan, Mingming; Wang, Yuepeng; Yin, Yan; Wang, Dongmei

2016-01-01

A high voltage power supply used in laser gyro is proposed in this paper. The power supply which uses a single DC 15v input and fly-back topology is adopted in the main circuit. The output of the power supply achieve high to 3.3kv voltage in order to light the RLG. The PFM control method is adopted to realize the rapid switching between the high voltage state and the maintain state. The resonant chip L6565 is used to achieve the zero voltage switching(ZVS), so the consumption is reduced and the power efficiency is improved more than 80%. A special circuit is presented in the control portion to ensure symmetry of the two RLG's arms current. The measured current accuracy is higher than 5‰ and the current symmetry of the two RLG's arms up to 99.2%.

Atmospheric plasma generation for LCD panel cleaning

NASA Astrophysics Data System (ADS)

Kim, Gyu-Sik; Won, Chung-Yuen; Choi, Ju-Yeop; Yim, C. H.

2007-12-01

UV lamp systems have been used for cleaning of display panels of TFT LCD or Plasma Display Panel (PDP). However, the needs for high efficient cleaning and low cost made high voltage plasma cleaning techniques to be developed and to be improved. Dielectric-barrier discharges (DBDs), also referred to as barrier discharges or silent discharges have for a long time been exclusively related to ozone generation. In this paper, a 6kW high voltage plasma power supply system was developed for LCD cleaning. The -phase input voltage is rectified and then inverter system is used to make a high frequency pulse train, which is rectified after passing through a high-power transformer. Finally, bi-directional high voltage pulse switching circuits are used to generate the high voltage plasma. Some experimental results showed the usefulness of atmospheric plasma for LCD panel cleaning.

The effects of the activation of the inner-hair-cell basolateral K+ channels on auditory nerve responses.

PubMed

Altoè, Alessandro; Pulkki, Ville; Verhulst, Sarah

2018-07-01

The basolateral membrane of the mammalian inner hair cell (IHC) expresses large voltage and Ca 2+ gated outward K + currents. To quantify how the voltage-dependent activation of the K + channels affects the functionality of the auditory nerve innervating the IHC, this study adopts a model of mechanical-to-neural transduction in which the basolateral K + conductances of the IHC can be made voltage-dependent or not. The model shows that the voltage-dependent activation of the K + channels (i) enhances the phase-locking properties of the auditory fiber (AF) responses; (ii) enables the auditory nerve to encode a large dynamic range of sound levels; (iii) enables the AF responses to synchronize precisely with the envelope of amplitude modulated stimuli; and (iv), is responsible for the steep offset responses of the AFs. These results suggest that the basolateral K + channels play a major role in determining the well-known response properties of the AFs and challenge the classical view that describes the IHC membrane as an electrical low-pass filter. In contrast to previous models of the IHC-AF complex, this study ascribes many of the AF response properties to fairly basic mechanisms in the IHC membrane rather than to complex mechanisms in the synapse. Copyright © 2018 Elsevier B.V. All rights reserved.

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

PubMed

Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

2017-01-10

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

Precision linear ramp function generator

DOEpatents

Jatko, W.B.; McNeilly, D.R.; Thacker, L.H.

1984-08-01

A ramp function generator is provided which produces a precise linear ramp function which is repeatable and highly stable. A derivative feedback loop is used to stabilize the output of an integrator in the forward loop and control the ramp rate. The ramp may be started from a selected baseline voltage level and the desired ramp rate is selected by applying an appropriate constant voltage to the input of the integrator.

Precision linear ramp function generator

DOEpatents

Jatko, W. Bruce; McNeilly, David R.; Thacker, Louis H.

1986-01-01

A ramp function generator is provided which produces a precise linear ramp unction which is repeatable and highly stable. A derivative feedback loop is used to stabilize the output of an integrator in the forward loop and control the ramp rate. The ramp may be started from a selected baseline voltage level and the desired ramp rate is selected by applying an appropriate constant voltage to the input of the integrator.

Load power device, system and method of load control and management employing load identification

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Yi; Luebke, Charles John; Schoepf, Thomas J.

A load power device includes a power input, at least one power output for at least one load, a plurality of sensors structured to sense voltage and current at the at least one power output, and a processor. The processor provides: (a) load identification based upon the sensed voltage and current, and (b) load control and management based upon the load identification.

A Design Methodology for Optoelectronic VLSI

DTIC Science & Technology

2007-01-01

current gets converted to a CMOS voltage level through a transimpedance amplifier circuit called a receiver. The output of the receiver is then...change the current flowing from the diode to a voltage that the logic inputs can use. That circuit is called a receiver. It is a transimpedance amplifier ...incorpo- rate random access memory circuits, SRAM or dynamic RAM (DRAM). These circuits use weak internal analog signals that are amplified by sense

Method and apparatus for current-output peak detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Geronimo, Gianluigi

2017-01-24

A method and apparatus for a current-output peak detector. A current-output peak detector circuit is disclosed and works in two phases. The peak detector circuit includes switches to switch the peak detector circuit from the first phase to the second phase upon detection of the peak voltage of an input voltage signal. The peak detector generates a current output with a high degree of accuracy in the second phase.

A 1 MW, 100 kV, less than 100 kg space based dc-dc power converter

NASA Technical Reports Server (NTRS)

Cooper, J. R.; White, C. W.

1991-01-01

A 1 MW dc-dc power converter has been designed which has an input voltage of 5 kV +/-3 percent, an output voltage of 100 kV +/- 0.25 percent, and a run time of 1000 s at full power. The estimated system mass is 83.8 kg, giving a power density of 11.9 kW/kg. The system exceeded the weight goal of 10 kW/kg through the use of innovative components and system concepts. The system volume is approximately 0.1 cu m, and the overall system efficiency is estimated to be 87 percent. Some of the unique system features include a 50-kHz H-bridge inverter using MOS-controlled thyristors as the switching devices, a resonance transformer to step up the voltage, open-cycle cryogenic hydrogen gas cooling, and a nonrigid, inflatable housing which provides on-demand pressurization of the power converter local environment. This system scales very well to higher output powers. The weight of the 10-MW system with the same input and output voltage requirements and overall system configuration is estimated to be 575.3 kg. This gives a power density of 17.4 kW/kg, significantly higher than the 11.9 kW/kg estimated at 1 MW.

A 1 MW, 100 kV, less than 100 kg space based dc-dc power converter

NASA Astrophysics Data System (ADS)

Cooper, J. R.; White, C. W.

A 1 MW dc-dc power converter has been designed which has an input voltage of 5 kV +/-3 percent, an output voltage of 100 kV +/- 0.25 percent, and a run time of 1000 s at full power. The estimated system mass is 83.8 kg, giving a power density of 11.9 kW/kg. The system exceeded the weight goal of 10 kW/kg through the use of innovative components and system concepts. The system volume is approximately 0.1 cu m, and the overall system efficiency is estimated to be 87 percent. Some of the unique system features include a 50-kHz H-bridge inverter using MOS-controlled thyristors as the switching devices, a resonance transformer to step up the voltage, open-cycle cryogenic hydrogen gas cooling, and a nonrigid, inflatable housing which provides on-demand pressurization of the power converter local environment. This system scales very well to higher output powers. The weight of the 10-MW system with the same input and output voltage requirements and overall system configuration is estimated to be 575.3 kg. This gives a power density of 17.4 kW/kg, significantly higher than the 11.9 kW/kg estimated at 1 MW.

Novel high-frequency energy-efficient pulsed-dc generator for capacitively coupled plasma discharge

NASA Astrophysics Data System (ADS)

Mamun, Md Abdullah Al; Furuta, Hiroshi; Hatta, Akimitsu

2018-03-01

The circuit design, assembly, and operating tests of a high-frequency and high-voltage (HV) pulsed dc generator (PDG) for capacitively coupled plasma (CCP) discharge inside a vacuum chamber are reported. For capacitive loads, it is challenging to obtain sharp rectangular pulses with fast rising and falling edges, requiring intense current for quick charging and discharging. The requirement of intense current generally limits the pulse operation frequency. In this study, we present a new type of PDG consisting of a pair of half-resonant converters and a constant current-controller circuit connected with HV solid-state power switches that can deliver almost rectangular high voltage pulses with fast rising and falling edges for CCP discharge. A prototype of the PDG is assembled to modulate from a high-voltage direct current (HVdc) input into a pulsed HVdc output, while following an input pulse signal and a set current level. The pulse rise time and fall time are less than 500 ns and 800 ns, respectively, and the minimum pulse width is 1 µs. The maximum voltage for a negative pulse is 1000 V, and the maximum repetition frequency is 500 kHz. During the pulse on time, the plasma discharge current is controlled steadily at the set value. The half-resonant converters in the PDG perform recovery of the remaining energy from the capacitive load at every termination of pulse discharge. The PDG performed with a high energy efficiency of 85% from the HVdc input to the pulsed dc output at a repetition rate of 1 kHz and with stable plasma operation in various discharge conditions. The results suggest that the developed PDG can be considered to be more efficient for plasma processing by CCP.

Novel high-frequency energy-efficient pulsed-dc generator for capacitively coupled plasma discharge.

PubMed

Mamun, Md Abdullah Al; Furuta, Hiroshi; Hatta, Akimitsu

2018-03-01

The circuit design, assembly, and operating tests of a high-frequency and high-voltage (HV) pulsed dc generator (PDG) for capacitively coupled plasma (CCP) discharge inside a vacuum chamber are reported. For capacitive loads, it is challenging to obtain sharp rectangular pulses with fast rising and falling edges, requiring intense current for quick charging and discharging. The requirement of intense current generally limits the pulse operation frequency. In this study, we present a new type of PDG consisting of a pair of half-resonant converters and a constant current-controller circuit connected with HV solid-state power switches that can deliver almost rectangular high voltage pulses with fast rising and falling edges for CCP discharge. A prototype of the PDG is assembled to modulate from a high-voltage direct current (HVdc) input into a pulsed HVdc output, while following an input pulse signal and a set current level. The pulse rise time and fall time are less than 500 ns and 800 ns, respectively, and the minimum pulse width is 1 µs. The maximum voltage for a negative pulse is 1000 V, and the maximum repetition frequency is 500 kHz. During the pulse on time, the plasma discharge current is controlled steadily at the set value. The half-resonant converters in the PDG perform recovery of the remaining energy from the capacitive load at every termination of pulse discharge. The PDG performed with a high energy efficiency of 85% from the HVdc input to the pulsed dc output at a repetition rate of 1 kHz and with stable plasma operation in various discharge conditions. The results suggest that the developed PDG can be considered to be more efficient for plasma processing by CCP.

Active Dendrites and Differential Distribution of Calcium Channels Enable Functional Compartmentalization of Golgi Cells.

PubMed

Rudolph, Stephanie; Hull, Court; Regehr, Wade G

2015-11-25

Interneurons are essential to controlling excitability, timing, and synaptic integration in neuronal networks. Golgi cells (GoCs) serve these roles at the input layer of the cerebellar cortex by releasing GABA to inhibit granule cells (grcs). GoCs are excited by mossy fibers (MFs) and grcs and provide feedforward and feedback inhibition to grcs. Here we investigate two important aspects of GoC physiology: the properties of GoC dendrites and the role of calcium signaling in regulating GoC spontaneous activity. Although GoC dendrites are extensive, previous studies concluded they are devoid of voltage-gated ion channels. Hence, the current view holds that somatic voltage signals decay passively within GoC dendrites, and grc synapses onto distal dendrites are not amplified and are therefore ineffective at firing GoCs because of strong passive attenuation. Using whole-cell recording and calcium imaging in rat slices, we find that dendritic voltage-gated sodium channels allow somatic action potentials to activate voltage-gated calcium channels (VGCCs) along the entire dendritic length, with R-type and T-type VGCCs preferentially located distally. We show that R- and T-type VGCCs located in the dendrites can boost distal synaptic inputs and promote burst firing. Active dendrites are thus critical to the regulation of GoC activity, and consequently, to the processing of input to the cerebellar cortex. In contrast, we find that N-type channels are preferentially located near the soma, and control the frequency and pattern of spontaneous firing through their close association with calcium-activated potassium (KCa) channels. Thus, VGCC types are differentially distributed and serve specialized functions within GoCs. Interneurons are essential to neural processing because they modulate excitability, timing, and synaptic integration within circuits. At the input layer of the cerebellar cortex, a single type of interneuron, the Golgi cell (GoC), carries these functions. The extent of inhibition depends on both spontaneous activity of GoCs and the excitatory synaptic input they receive. In this study, we find that different types of calcium channels are differentially distributed, with dendritic calcium channels being activated by somatic activity, boosting synaptic inputs and enabling bursting, and somatic calcium cannels promoting regular firing. We therefore challenge the current view that GoC dendrites are passive and identify the mechanisms that contribute to GoCs regulating the flow of sensory information in the cerebellar cortex. Copyright © 2015 the authors 0270-6474/15/3515492-13$15.00/0.

An 11 μ w, two-electrode transimpedance biosignal amplifier with active current feedback stabilization.

PubMed

Inan, O T; Kovacs, G T A

2010-04-01

A novel two-electrode biosignal amplifier circuit is demonstrated by using a composite transimpedance amplifier input stage with active current feedback. Micropower, low gain-bandwidth product operational amplifiers can be used, leading to the lowest reported overall power consumption in the literature for a design implemented with off-the-shelf commercial integrated circuits (11 μW). Active current feedback forces the common-mode input voltage to stay within the supply rails, reducing baseline drift and amplifier saturation problems that can be present in two-electrode systems. The bandwidth of the amplifier extends from 0.05-200 Hz and the midband voltage gain (assuming an electrode-to-skin resistance of 100 kΩ) is 48 dB. The measured output noise level is 1.2 mV pp, corresponding to a voltage signal-to-noise ratio approaching 50 dB for a typical electrocardiogram (ECG) level input of 1 mVpp. Recordings were taken from a subject by using the proposed two-electrode circuit and, simultaneously, a three-electrode standard ECG circuit. The residual of the normalized ensemble averages for both measurements was computed, and the power of this residual was 0.54% of the power of the standard ECG measurement output. While this paper primarily focuses on ECG applications, the circuit can also be used for amplifying other biosignals, such as the electroencephalogram.

ITER-like antenna capacitors voltage probes: Circuit/electromagnetic calculations and calibrations.

PubMed

Helou, W; Dumortier, P; Durodié, F; Lombard, G; Nicholls, K

2016-10-01

The analyses illustrated in this manuscript have been performed in order to provide the required data for the amplitude-and-phase calibration of the D-dot voltage probes used in the ITER-like antenna at the Joint European Torus tokamak. Their equivalent electrical circuit has been extracted and analyzed, and it has been compared to the one of voltage probes installed in simple transmission lines. A radio-frequency calibration technique has been formulated and exact mathematical relations have been derived. This technique mixes in an elegant fashion data extracted from measurements and numerical calculations to retrieve the calibration factors. The latter have been compared to previous calibration data with excellent agreement proving the robustness of the proposed radio-frequency calibration technique. In particular, it has been stressed that it is crucial to take into account environmental parasitic effects. A low-frequency calibration technique has been in addition formulated and analyzed in depth. The equivalence between the radio-frequency and low-frequency techniques has been rigorously demonstrated. The radio-frequency calibration technique is preferable in the case of the ITER-like antenna due to uncertainties on the characteristics of the cables connected at the inputs of the voltage probes. A method to extract the effect of a mismatched data acquisition system has been derived for both calibration techniques. Finally it has been outlined that in the case of the ITER-like antenna voltage probes can be in addition used to monitor the currents at the inputs of the antenna.

Nonlinear control of voltage source converters in AC-DC power system.

PubMed

Dash, P K; Nayak, N

2014-07-01

This paper presents the design of a robust nonlinear controller for a parallel AC-DC power system using a Lyapunov function-based sliding mode control (LYPSMC) strategy. The inputs for the proposed control scheme are the DC voltage and reactive power errors at the converter station and the active and reactive power errors at the inverter station of the voltage-source converter-based high voltage direct current transmission (VSC-HVDC) link. The stability and robust tracking of the system parameters are ensured by applying the Lyapunov direct method. Also the gains of the sliding mode control (SMC) are made adaptive using the stability conditions of the Lyapunov function. The proposed control strategy offers invariant stability to a class of systems having modeling uncertainties due to parameter changes and exogenous inputs. Comprehensive computer simulations are carried out to verify the proposed control scheme under several system disturbances like changes in short-circuit ratio, converter parametric changes, and faults on the converter and inverter buses for single generating system connected to the power grid in a single machine infinite-bus AC-DC network and also for a 3-machine two-area power system. Furthermore, a second order super twisting sliding mode control scheme has been presented in this paper that provides a higher degree of nonlinearity than the LYPSMC and damps faster the converter and inverter voltage and power oscillations. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Nitrate removal from pharmaceutical wastewater using microbial electrochemical system supplied through low frequency-low voltage alternating electric current.

PubMed

Hoseinzadeh, Edris; Rezaee, Abbas; Farzadkia, Mahdi

2018-04-01

In this study, a microbial electrochemical system (MES) was designed to evaluate the effects of a low frequency-low voltage alternating electrical current on denitrification efficacy in the presence of ibuprofen as a low biodegradable organic carbon source. Cylindrical carbon cloth and stainless steel mesh electrodes containing a consortium of heterotrophic and autotrophic bacteria were mounted in the wall of the designed laboratory-scale bioreactor. The effects of inlet nitrate concentration (50-800mgL -1 ), retention time (2.5-24h), waveform magnitude (0.1-9.6V p-p ), adjustable direct current voltage added to offset voltage (0.1-4.9V), alternating current frequency (10-60Hz), and waveforms (sinusoidal, square, and ramp) were studied in this work. The results showed that the proposed system removes 800mgL -1 nitrate up to 95% during 6.5h. Optimum conditions were obtained in the 8V p-p using a frequency of 10Hz of a sinusoidal waveform. The morphology studies confirmed bacterial morphology change when applying the alternating current. Dehydrogenase activity of biofilms formed on surface of stainless steel electrodes increased to 15.24μgTFmg biomass cm -2 d. The maximum bacterial activity was obtained at a voltage of 8V p-p . The experimental results revealed that the MES using a low frequency-low voltage alternating electrical current is a promising technique for nitrate removal from pharmaceutical wastewaters in the presence of low biodegradability of carbon sources such as ibuprofen. Copyright © 2017 Elsevier B.V. All rights reserved.

Effects of voltage control in utility interactive dispersed storage and generation systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kirkham, H.; Das, R.

1983-03-15

When a small generator is connected to the distribution system, the voltage at the point of interconnection is determined largely by the system and not the generator. This report examines the effect on the generator, on the load voltage and on the distribution system of a number of different voltage control strategies in the generator. Synchronous generators with three kinds of exciter control are considered, as well as induction generators and dc/ac inverters, with and without capacitor compensation. The effect of varying input power during operation (which may be experienced by generators based on renewable resources) is explored, as wellmore » as the effect of connecting and disconnecting the generator at ten percent of its rated power.« less

Effect of Heat Input on Geometry of Austenitic Stainless Steel Weld Bead on Low Carbon Steel

NASA Astrophysics Data System (ADS)

Saha, Manas Kumar; Hazra, Ritesh; Mondal, Ajit; Das, Santanu

2018-05-01

Among different weld cladding processes, gas metal arc welding (GMAW) cladding becomes a cost effective, user friendly, versatile method for protecting the surface of relatively lower grade structural steels from corrosion and/or erosion wear by depositing high grade stainless steels onto them. The quality of cladding largely depends upon the bead geometry of the weldment deposited. Weld bead geometry parameters, like bead width, reinforcement height, depth of penetration, and ratios like reinforcement form factor (RFF) and penetration shape factor (PSF) determine the quality of the weld bead geometry. Various process parameters of gas metal arc welding like heat input, current, voltage, arc travel speed, mode of metal transfer, etc. influence formation of bead geometry. In the current experimental investigation, austenite stainless steel (316) weld beads are formed on low alloy structural steel (E350) by GMAW using 100% CO2 as the shielding gas. Different combinations of current, voltage and arc travel speed are chosen so that heat input increases from 0.35 to 0.75 kJ/mm. Nine number of weld beads are deposited and replicated twice. The observations show that weld bead width increases linearly with increase in heat input, whereas reinforcement height and depth of penetration do not increase with increase in heat input. Regression analysis is done to establish the relationship between heat input and different geometrical parameters of weld bead. The regression models developed agrees well with the experimental data. Within the domain of the present experiment, it is observed that at higher heat input, the weld bead gets wider having little change in penetration and reinforcement; therefore, higher heat input may be recommended for austenitic stainless steel cladding on low alloy steel.

Observer-based higher order sliding mode control of power factor in three-phase AC/DC converter for hybrid electric vehicle applications

NASA Astrophysics Data System (ADS)

Liu, Jianxing; Laghrouche, Salah; Wack, Maxime

2014-06-01

In this paper, a full-bridge boost power converter topology is studied for power factor control, using output higher order sliding mode control. The AC/DC converters are used for charging the battery and super-capacitor in hybrid electric vehicles from the utility. The proposed control forces the input currents to track the desired values, which can control the output voltage while keeping the power factor close to one. Super-twisting sliding mode observer is employed to estimate the input currents and load resistance only from the measurement of output voltage. Lyapunov analysis shows the asymptotic convergence of the closed-loop system to zero. Multi-rate simulation illustrates the effectiveness and robustness of the proposed controller in the presence of measurement noise.

Ultrasonic input-output for transmitting and receiving longitudinal transducers coupled to same face of isotropic elastic plate

NASA Technical Reports Server (NTRS)

Williams, J. H., Jr.; Karagulle, H.; Lee, S. S.

1982-01-01

The quantitative understanding of ultrasonic nondestructive evaluation parameters such as the stress wave factor were studied. Ultrasonic input/output characteristics for an isotropic elastic plate with transmitting and receiving longitudinal transducers coupled to the same face were analyzed. The asymptotic normal stress is calculated for an isotropic elastic half space subjected to a uniform harmonic normal stress applied to a circular region at the surface. The radiated stress waves are traced within the plate by considering wave reflections at the top and bottom faces. The output voltage amplitude of the receiving transducer is estimated by considering only longitudinal waves. Agreement is found between the output voltage wave packet amplitudes and times of arrival due to multiple reflections of the longitudinal waves.

Device for modular input high-speed multi-channel digitizing of electrical data

DOEpatents

VanDeusen, A.L.; Crist, C.E.

1995-09-26

A multi-channel high-speed digitizer module converts a plurality of analog signals to digital signals (digitizing) and stores the signals in a memory device. The analog input channels are digitized simultaneously at high speed with a relatively large number of on-board memory data points per channel. The module provides an automated calibration based upon a single voltage reference source. Low signal noise at such a high density and sample rate is accomplished by ensuring the A/D converters are clocked at the same point in the noise cycle each time so that synchronous noise sampling occurs. This sampling process, in conjunction with an automated calibration, yields signal noise levels well below the noise level present on the analog reference voltages. 1 fig.

Correspondence between visual and electrical input filters of ON and OFF mouse retinal ganglion cells

NASA Astrophysics Data System (ADS)

Sekhar, S.; Jalligampala, A.; Zrenner, E.; Rathbun, D. L.

2017-08-01

Objective. Over the past two decades retinal prostheses have made major strides in restoring functional vision to patients blinded by diseases such as retinitis pigmentosa. Presently, implants use single pulses to activate the retina. Though this stimulation paradigm has proved beneficial to patients, an unresolved problem is the inability to selectively stimulate the on and off visual pathways. To this end our goal was to test, using white noise, voltage-controlled, cathodic, monophasic pulse stimulation, whether different retinal ganglion cell (RGC) types in the wild type retina have different electrical input filters. This is an important precursor to addressing pathway-selective stimulation. Approach. Using full-field visual flash and electrical and visual Gaussian noise stimulation, combined with the technique of spike-triggered averaging (STA), we calculate the electrical and visual input filters for different types of RGCs (classified as on, off or on-off based on their response to the flash stimuli). Main results. Examining the STAs, we found that the spiking activity of on cells during electrical stimulation correlates with a decrease in the voltage magnitude preceding a spike, while the spiking activity of off cells correlates with an increase in the voltage preceding a spike. No electrical preference was found for on-off cells. Comparing STAs of wild type and rd10 mice revealed narrower electrical STA deflections with shorter latencies in rd10. Significance. This study is the first comparison of visual cell types and their corresponding temporal electrical input filters in the retina. The altered input filters in degenerated rd10 retinas are consistent with photoreceptor stimulation underlying visual type-specific electrical STA shapes in wild type retina. It is therefore conceivable that existing implants could target partially degenerated photoreceptors that have only lost their outer segments, but not somas, to selectively activate the on and off visual pathways.

Monolithic acoustic graphene transistors based on lithium niobate thin film

NASA Astrophysics Data System (ADS)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

The Type-2 Fuzzy Logic Controller-Based Maximum Power Point Tracking Algorithm and the Quadratic Boost Converter for Pv System

NASA Astrophysics Data System (ADS)

Altin, Necmi

2018-05-01

An interval type-2 fuzzy logic controller-based maximum power point tracking algorithm and direct current-direct current (DC-DC) converter topology are proposed for photovoltaic (PV) systems. The proposed maximum power point tracking algorithm is designed based on an interval type-2 fuzzy logic controller that has an ability to handle uncertainties. The change in PV power and the change in PV voltage are determined as inputs of the proposed controller, while the change in duty cycle is determined as the output of the controller. Seven interval type-2 fuzzy sets are determined and used as membership functions for input and output variables. The quadratic boost converter provides high voltage step-up ability without any reduction in performance and stability of the system. The performance of the proposed system is validated through MATLAB/Simulink simulations. It is seen that the proposed system provides high maximum power point tracking speed and accuracy even for fast changing atmospheric conditions and high voltage step-up requirements.

Bi-directional power control system for voltage converter

DOEpatents

Garrigan, Neil Richard; King, Robert Dean; Schwartz, James Edward

1999-01-01

A control system for a voltage converter includes: a power comparator for comparing a power signal on input terminals of the converter with a commanded power signal and producing a power comparison signal; a power regulator for transforming the power comparison signal to a commanded current signal; a current comparator for comparing the commanded current signal with a measured current signal on output terminals of the converter and producing a current comparison signal; a current regulator for transforming the current comparison signal to a pulse width modulator (PWM) duty cycle command signal; and a PWM for using the PWM duty cycle command signal to control electrical switches of the converter. The control system may further include: a command multiplier for converting a voltage signal across the output terminals of the converter to a gain signal having a value between zero (0) and unity (1), and a power multiplier for multiplying the commanded power signal by the gain signal to provide a limited commanded power signal, wherein power comparator compares the limited commanded power signal with the power signal on the input terminals.

Bi-directional power control system for voltage converter

DOEpatents

Garrigan, N.R.; King, R.D.; Schwartz, J.E.

1999-05-11

A control system for a voltage converter includes: a power comparator for comparing a power signal on input terminals of the converter with a commanded power signal and producing a power comparison signal; a power regulator for transforming the power comparison signal to a commanded current signal; a current comparator for comparing the commanded current signal with a measured current signal on output terminals of the converter and producing a current comparison signal; a current regulator for transforming the current comparison signal to a pulse width modulator (PWM) duty cycle command signal; and a PWM for using the PWM duty cycle command signal to control electrical switches of the converter. The control system may further include: a command multiplier for converting a voltage signal across the output terminals of the converter to a gain signal having a value between zero (0) and unity (1), and a power multiplier for multiplying the commanded power signal by the gain signal to provide a limited commanded power signal, wherein power comparator compares the limited commanded power signal with the power signal on the input terminals. 10 figs.

Simulating the Gradually Deteriorating Performance of an RTG

NASA Technical Reports Server (NTRS)

Wood, Eric G.; Ewell, Richard C.; Patel, Jagdish; Hanks, David R.; Lozano, Juan A.; Snyder, G. Jeffrey; Noon, Larry

2008-01-01

Degra (now in version 3) is a computer program that simulates the performance of a radioisotope thermoelectric generator (RTG) over its lifetime. Degra is provided with a graphical user interface that is used to edit input parameters that describe the initial state of the RTG and the time-varying loads and environment to which it will be exposed. Performance is computed by modeling the flows of heat from the radioactive source and through the thermocouples, also allowing for losses, to determine the temperature drop across the thermocouples. This temperature drop is used to determine the open-circuit voltage, electrical resistance, and thermal conductance of the thermocouples. Output power can then be computed by relating the open-circuit voltage and the electrical resistance of the thermocouples to a specified time-varying load voltage. Degra accounts for the gradual deterioration of performance attributable primarily to decay of the radioactive source and secondarily to gradual deterioration of the thermoelectric material. To provide guidance to an RTG designer, given a minimum of input, Degra computes the dimensions, masses, and thermal conductances of important internal structures as well as the overall external dimensions and total mass.