Solid-state semiconductor optical cryocooler based on CdS nanobelts.

PubMed

Li, Dehui; Zhang, Jun; Wang, Xinjiang; Huang, Baoling; Xiong, Qihua

2014-08-13

We demonstrate the laser cooling of silicon-on-insulator (SOI) substrate using CdS nanobelts. The local temperature change of the SOI substrate exactly beneath the CdS nanobelts is deduced from the ratio of the Stokes and anti-Stokes Raman intensities from the Si layer on the top of the SOI substrate. We have achieved a 30 and 20 K net cooling starting from 290 K under a 3.8 mW 514 nm and a 4.4 mW 532 nm pumping, respectively. In contrast, a laser heating effect has been observed pumped by 502 and 488 nm lasers. Theoretical analysis based on the general static heat conduction module in the Ansys program package is conducted, which agrees well with the experimental results. Our investigations demonstrate the laser cooling capability of an external thermal load, suggesting the applications of II-VI semiconductors in all-solid-state optical cryocoolers.

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Effects of substrate voltage on noise characteristics and hole lifetime in SOI metal-oxide-semiconductor field-effect transistor photon detector.

PubMed

Putranto, Dedy Septono Catur; Priambodo, Purnomo Sidi; Hartanto, Djoko; Du, Wei; Satoh, Hiroaki; Ono, Atsushi; Inokawa, Hiroshi

2014-09-08

Low-frequency noise and hole lifetime in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) are analyzed, considering their use in photon detection based on single-hole counting. The noise becomes minimum at around the transition point between front- and back-channel operations when the substrate voltage is varied, and increases largely on both negative and positive sides of the substrate voltage showing peculiar Lorentzian (generation-recombination) noise spectra. Hole lifetime is evaluated by the analysis of drain current histogram at different substrate voltages. It is found that the peaks in the histogram corresponding to the larger number of stored holes become higher as the substrate bias becomes larger. This can be attributed to the prolonged lifetime caused by the higher electric field inside the body of SOI MOSFET. It can be concluded that, once the inversion channel is induced for detection of the photo-generated holes, the small absolute substrate bias is favorable for short lifetime and low noise, leading to high-speed operation.

A novel SOI LDMOS with substrate field plate and variable-k dielectric buried layer

NASA Astrophysics Data System (ADS)

Li, Qi; Wen, Yi; Zhang, Fabi; Li, Haiou; Xiao, Gongli; Chen, Yonghe; Fu, Tao

2018-09-01

A novel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) structure has been proposed. The new structure features a substrate field plate (SFP) and a variable-k dielectric buried layer (VKBL). The SFP and VKBL improve the breakdown voltage by introducing new electric field peaks in the surface electric field distribution. Moreover, the SFP reduces the specific ON-resistance through an enhanced auxiliary depletion effect on the drift region. The simulation results indicate that compared to the conventional SOI LDMOS structure, the breakdown voltage is improved from 118 V to 221 V, the specific ON-resistance is decreased from 7.15 mΩ·cm2 to 3.81 mΩ·cm2, the peak value of surface temperature is declined by 38 K.

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

PubMed

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-08-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

Monolithically Integrated InGaAs Nanowires on 3D Structured Silicon-on-Insulator as a New Platform for Full Optical Links.

PubMed

Kim, Hyunseok; Farrell, Alan C; Senanayake, Pradeep; Lee, Wook-Jae; Huffaker, Diana L

2016-03-09

Monolithically integrated III-V semiconductors on a silicon-on-insulator (SOI) platform can be used as a building block for energy-efficient on-chip optical links. Epitaxial growth of III-V semiconductors on silicon, however, has been challenged by the large mismatches in lattice constants and thermal expansion coefficients between epitaxial layers and silicon substrates. Here, we demonstrate for the first time the monolithic integration of InGaAs nanowires on the SOI platform and its feasibility for photonics and optoelectronic applications. InGaAs nanowires are grown not only on a planar SOI layer but also on a 3D structured SOI layer by catalyst-free metal-organic chemical vapor deposition. The precise positioning of nanowires on 3D structures, including waveguides and gratings, reveals the versatility and practicality of the proposed platform. Photoluminescence measurements exhibit that the composition of ternary InGaAs nanowires grown on the SOI layer has wide tunability covering all telecommunication wavelengths from 1.2 to 1.8 μm. We also show that the emission from an optically pumped single nanowire is effectively coupled and transmitted through an SOI waveguide, explicitly showing that this work lays the foundation for a new platform toward energy-efficient optical links.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

FinFET and UTBB for RF SOI communication systems

NASA Astrophysics Data System (ADS)

Raskin, Jean-Pierre

2016-11-01

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

Carrier-transport mechanism of Er-silicide Schottky contacts to strained-silicon-on-insulator and silicon-on-insulator.

PubMed

Jyothi, I; Janardhanam, V; Kang, Min-Sung; Yun, Hyung-Joong; Lee, Jouhahn; Choi, Chel-Jong

2014-11-01

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates

PubMed Central

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-01-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III–V and II–VI materials. PMID:24046490

Ultra-Thin Monocrystalline Silicon Solar Cell with 12.2% Efficiency Using Silicon-On-Insulator Substrate.

PubMed

Bian, Jian-Tao; Yu, Jian; Duan, Wei-Yuan; Qiu, Yu

2015-04-01

Single side heterojunction silicon solar cells were designed and fabricated using Silicon-On-Insulator (SOI) substrate. The TCAD software was used to simulate the effect of silicon layer thickness, doping concentration and the series resistance. A 10.5 µm thick monocrystalline silicon layer was epitaxially grown on the SOI with boron doping concentration of 2 x 10(16) cm(-3) by thermal CVD. Very high Voc of 678 mV was achieved by applying amorphous silicon heterojunction emitter on the front surface. The single cell efficiency of 12.2% was achieved without any light trapping structures. The rear surface recombination and the series resistance are the main limiting factors for the cell efficiency in addition to the c-Si thickness. By integrating an efficient light trapping scheme and further optimizing fabrication process, higher efficiency of 14.0% is expected for this type of cells. It can be applied to integrated circuits on a monolithic chip to meet the requirements of energy autonomous systems.

Imaging of the native inversion layer in Silicon-On-Insulator wafers via Scanning Surface Photovoltage: Implications for RF device performance

NASA Astrophysics Data System (ADS)

Dahanayaka, Daminda; Wong, Andrew; Kaszuba, Philip; Moszkowicz, Leon; Slinkman, James; IBM SPV Lab Team

2014-03-01

Silicon-On-Insulator (SOI) technology has proved beneficial for RF cell phone technologies, which have equivalent performance to GaAs technologies. However, there is evident parasitic inversion layer under the Buried Oxide (BOX) at the interface with the high resistivity Si substrate. The latter is inferred from capacitance-voltage measurements on MOSCAPs. The inversion layer has adverse effects on RF device performance. We present data which, for the first time, show the extent of the inversion layer in the underlying substrate. This knowledge has driven processing techniques to suppress the inversion.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

NASA Astrophysics Data System (ADS)

Mizutani, Akio; Eto, Yohei; Kikuta, Hisao

2017-12-01

A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting.

PubMed

Du, Wei; Inokawa, Hiroshi; Satoh, Hiroaki; Ono, Atsushi

2011-08-01

In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved. © 2011 Optical Society of America

Formation of SIMOX-SOI structure by high-temperature oxygen implantation

NASA Astrophysics Data System (ADS)

Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

2015-12-01

We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 1017-1018 ions/cm2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

Hybrid Quantum Cascade Lasers on Silicon-on-Sapphire

DTIC Science & Technology

2016-11-23

on-SOS devices mounted on a copper heat sink. The liquid crystal thermal absorber is attached to block mid-IR emission from any sections of the laser...directions. 2. Statement of the problem studied Short-wavelength infrared (SWIR, ~1-3 m) photonics systems based on silicon-on- insulator (SOI...Table 1. Layer type Layer thickness and doping Thickness (nm) Doping (cm-3) InP substrate 350000 Semi- insulating InP buffer layer 2000 2.00E

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

NASA Astrophysics Data System (ADS)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Quantum dots in single electron transistors with ultrathin silicon-on-insulator structures

NASA Astrophysics Data System (ADS)

Ihara, S.; Andreev, A.; Williams, D. A.; Kodera, T.; Oda, S.

2015-07-01

We report on fabrication and transport properties of lithographically defined single quantum dots (QDs) in single electron transistors with ultrathin silicon-on-insulator (SOI) substrate. We observed comparatively large charging energy E C ˜ 20 meV derived from the stability diagram at a temperature of 4.2 K. We also carried out three-dimensional calculations of the capacitance matrix and transport properties through the QD for the real structure geometry and found an excellent quantitative agreement with experiment of the calculated main parameters of stability diagram (charging energy, period of Coulomb oscillations, and asymmetry of the diamonds). The obtained results confirm fabrication of well-defined integrated QDs as designed with ultrathin SOI that makes it possible to achieve relatively large QD charging energies, which is useful for stable and high temperature operation of single electron devices.

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

NASA Technical Reports Server (NTRS)

Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

2005-01-01

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

Electron beam patterning for writing of positively charged gold colloidal nanoparticles

NASA Astrophysics Data System (ADS)

Zafri, Hadar; Azougi, Jonathan; Girshevitz, Olga; Zalevsky, Zeev; Zitoun, David

2018-02-01

Synthesis at the nanoscale has progressed at a very fast pace during the last decades. The main challenge today lies in precise localization to achieve efficient nanofabrication of devices. In the present work, we report on a novel method for the patterning of gold metallic nanoparticles into nanostructures on a silicon-on-insulator (SOI) wafer. The fabrication makes use of relatively accessible equipment, a scanning electron microscope (SEM), and wet chemical synthesis. The electron beam implants electrons into the insulating material, which further anchors the positively charged Au nanoparticles by electrostatic attraction. The novel fabrication method was applied to several substrates useful in microelectronics to add plasmonic particles. The resolution and surface density of the deposition were tuned, respectively, by the electron energy (acceleration voltage) and the dose of electronic irradiation. We easily achieved the smallest written feature of 68 ± 18 nm on SOI, and the technique can be extended to any positively charged nanoparticles, while the resolution is in principle limited by the particle size distribution and the scattering of the electrons in the substrate. [Figure not available: see fulltext.

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

NASA Astrophysics Data System (ADS)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

NASA Astrophysics Data System (ADS)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Strong room temperature electroluminescence from lateral p-SiGe/i-Ge/n-SiGe heterojunction diodes on silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Lin, Guangyang; Yi, Xiaohui; Li, Cheng; Chen, Ningli; Zhang, Lu; Chen, Songyan; Huang, Wei; Wang, Jianyuan; Xiong, Xihuan; Sun, Jiaming

2016-10-01

A lateral p-Si0.05Ge0.95/i-Ge/n-Si0.05Ge0.95 heterojunction light emitting diode on a silicon-on-insulator (SOI) substrate was proposed, which is profitable to achieve higher luminous extraction compared to vertical junctions. Due to the high carrier injection ratio of heterostructures and optical reflection at the SiO2/Si interface of the SOI, strong room temperature electroluminescence (EL) at around 1600 nm from the direct bandgap of i-Ge with 0.30% tensile strain was observed. The EL peak intensity of the lateral heterojunction is enhanced by ˜4 folds with a larger peak energy than that of the vertical Ge p-i-n homojunction, suggesting that the light emitting efficiency of the lateral heterojunction is effectively improved. The EL peak intensity of the lateral heterojunction, which increases quadratically with injection current density, becomes stronger for diodes with a wider i-Ge region. The CMOS compatible fabrication process of the lateral heterojunctions paves the way for the integration of the light source with the Ge metal-oxide-semiconductor field-effect-transistor.

Submicron mapping of strained silicon-on-insulator features induced

NASA Astrophysics Data System (ADS)

Murray, Conal E.; Sankarapandian, M.; Polvino, S. M.; Noyan, I. C.; Lai, B.; Cai, Z.

2007-04-01

Real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction. The quantitative strain mapping indicated that the SOI strain was largest at the SOI/STI interface and decreased as a function of distance from this interface. An out-of-plane residual strain of approximately -31μɛ was observed in the blanket regions of the SOI. A comparison of the depth-averaged strain distributions to the strain profiles calculated from an Eshelby inclusion model indicated an equivalent eigenstrain of -0.55% in the STI regions acting on the SOI features.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes.

PubMed

Zhu, Hao; Li, Haitao; Robertson, Joseph W F; Balijepalli, Arvind; Krylyuk, Sergiy; Davydov, Albert V; Kasianowicz, John J; Suehle, John S; Li, Qiliang

2017-10-27

Novel nanofluidic chemical cells based on self-assembled solid-state SiO 2 nanotubes on silicon-on-insulator (SOI) substrate have been successfully fabricated and characterized. The vertical SiO 2 nanotubes with a smooth cavity are built from Si nanowires which were epitaxially grown on the SOI substrate. The nanotubes have rigid, dry-oxidized SiO 2 walls with precisely controlled nanotube inner diameter, which is very attractive for chemical-/bio-sensing applications. No dispersion/aligning procedures were involved in the nanotube fabrication and integration by using this technology, enabling a clean and smooth chemical cell. Such a robust and well-controlled nanotube is an excellent case of developing functional nanomaterials by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth. These solid, smooth, clean SiO 2 nanotubes and nanofluidic devices are very encouraging and attractive in future bio-medical applications, such as single molecule sensing and DNA sequencing.

Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes

NASA Astrophysics Data System (ADS)

Zhu, Hao; Li, Haitao; Robertson, Joseph W. F.; Balijepalli, Arvind; Krylyuk, Sergiy; Davydov, Albert V.; Kasianowicz, John J.; Suehle, John S.; Li, Qiliang

2017-10-01

Novel nanofluidic chemical cells based on self-assembled solid-state SiO2 nanotubes on silicon-on-insulator (SOI) substrate have been successfully fabricated and characterized. The vertical SiO2 nanotubes with a smooth cavity are built from Si nanowires which were epitaxially grown on the SOI substrate. The nanotubes have rigid, dry-oxidized SiO2 walls with precisely controlled nanotube inner diameter, which is very attractive for chemical-/bio-sensing applications. No dispersion/aligning procedures were involved in the nanotube fabrication and integration by using this technology, enabling a clean and smooth chemical cell. Such a robust and well-controlled nanotube is an excellent case of developing functional nanomaterials by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth. These solid, smooth, clean SiO2 nanotubes and nanofluidic devices are very encouraging and attractive in future bio-medical applications, such as single molecule sensing and DNA sequencing.

Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

NASA Astrophysics Data System (ADS)

Zhang, Runchun; Zhao, Beiji; Huang, Kai; You, Tiangui; Jia, Qi; Lin, Jiajie; Zhang, Shibin; Yan, Youquan; Yi, Ailun; Zhou, Min; Ou, Xin

2018-05-01

Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crowder, M.A.; Sposili, R.S.; Cho, H.S.

Nonhydrogenated, n-channel, low-temperature-processed, single-crystal Si thin-film transistors (TFT`s) have been fabricated on Si thin films prepared via sequential lateral solidification (SLS). The device characteristics of the resulting SLS TFT`s exhibit properties and a level of performance that are superior to polycrystalline Si-based TFT`s and are comparable to similar devices fabricated on silicon-on-insulator (SOI) substrates or bulk-Si wafers. The authors attribute these high-performance device characteristics to the absence of high-angle grain-boundaries within the active channel portion of the TFT`s.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Waveguide-integrated vertical pin photodiodes of Ge fabricated on p+ and n+ Si-on-insulator layers

NASA Astrophysics Data System (ADS)

Ito, Kazuki; Hiraki, Tatsurou; Tsuchizawa, Tai; Ishikawa, Yasuhiko

2017-04-01

Vertical pin structures of Ge photodiodes (PDs) integrated with Si optical waveguides are fabricated by depositing Ge epitaxial layers on Si-on-insulator (SOI) layers, and the performances of n+-Ge/i-Ge/p+-SOI PDs are compared with those of p+-Ge/i-Ge/n+-SOI PDs. Both types of PDs show responsivities as high as 1.0 A/W at 1.55 µm, while the dark leakage current is different, which is consistent with previous reports on free-space PDs formed on bulk Si wafers. The dark current of the p+-Ge/i-Ge/n+-SOI PDs is higher by more than one order of magnitude. Taking into account the activation energies for dark current as well as the dependence on PD area, the dark current of the n+-Ge/i-Ge/p+-SOI PDs is dominated by the thermal generation of carriers via mid-gap defect levels in Ge, while for the p+-Ge/i-Ge/n+-SOI PDs, the dark current is ascribed to not only thermal generation but also other mechanisms such as locally formed conduction paths.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

NASA Astrophysics Data System (ADS)

Lenka, Annada Shankar; Mishra, Sikha; Mishra, Satyaranjan; Bhanja, Urmila; Mishra, Guru Prasad

2017-11-01

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

A Systematic Study of the Effect of Spin-Orbit Interaction on Properties of Tetravalent and Pentavalent Iridate Compounds

NASA Astrophysics Data System (ADS)

Terzic, Jasminka

Previous studies of iridates have shown that an interplay of strong SOI, Coulomb interaction U, Hund's rule coupling and crystalline electric fields result in unexpected insulating states with complex magnetic states. The novel Jeff =1/2 insulating state first observed in Sr2IrO4 is a direct consequence of such an intriguing interplay and is one of the central foci of this dissertation study. The work presented here consists of three projects: (1) Effects of Tb doping on Sr2IrO4 having tetravalent Ir4+ (5d5) ions; (2) Emergence of unexpected magnetic states in double-perovskite (Ba1-xSr x)2YIrO6 with pentavalent Ir5+ (5d4) ions in the presence of strong SOI, and ( 3) The coexistence of a charge and magnetic order in a magnetic dimer chain system, Ba5AlIr2O11, which has both tetravalent Ir4+ (5d5) and pentavalent Ir5+ (5d4) ions. A significant portion of this dissertation will focus on Tb doped Sr 2IrO4. A central finding of this work is that slight Tb doping (3%) readily suppresses the antiferromagnetic state but retains the insulating state, indicating an unusual correlation between the magnetic and insulating states as a result of the presence of the strong SOI. However, SOI is not the only significant phenomenon. The study on the double-perovskite (Ba1-xSrx)2YIrO6 revealed an exotic magnetic ground state, in sharp contrast to the anticipated singlet ground state in the strong SOI limit, raising an urgent question: is SOI as dominant as was initially anticipated in the iridates? Finally, this study turns to a system containing both Ir4+ and Ir5+ ions, Ba5AlIr2O11. This system features dimer chains of two inequivalent octahedra occupied by tetravalent Ir4+ (5d5) and pentavalent Ir 5+ (5d4) ions respectively. Ba5AlIr 2O11 undergoes charge and magnetic order transitions at 210 K and 4.5 K, respectively. SOI-driven physics is a rapidly evolving field with an ever growing list of theoretical proposals which have enjoyed very limited experimental confirmation thus far. This study has revealed a large range of interesting phenomena in the iridates that defy conventional theoretical arguments and that help to fill an experimental void in this field. Keywords: spin-orbit interaction (SOI), iridates, double exchange, Mott insulator, Coulomb interaction, Hund's rule coupling.

Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

NASA Astrophysics Data System (ADS)

Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

2018-05-01

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Nanophotonic applications for silicon-on-insulator (SOI)

NASA Astrophysics Data System (ADS)

de la Houssaye, Paul R.; Russell, Stephen D.; Shimabukuro, Randy L.

2004-07-01

Silicon-on-insulator is a proven technology for very large scale integration of microelectronic devices. The technology also offers the potential for development of nanophotonic devices and the ability to interface such devices to the macroscopic world. This paper will report on fabrication techniques used to form nano-structured silicon wires on an insulating structure that is amenable to interfacing nanostructured sensors with high-performance microelectronic circuitry for practical implementation. Nanostructures formed on silicon-on-sapphire can also exploit the transparent substrate for novel device geometries. This research harnesses the unique properties of a high-quality single crystal film of silicon on sapphire and uses the film thickness as one of the confinement dimensions. Lateral arrays of silicon nanowires were fabricated in the thin (5 to 20 nm) silicon layer and studied. This technique offers simplified contact to individual wires and provides wire surfaces that are more readily accessible for controlled alteration and device designs.

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

Patterning of graphene on silicon-on-insulator waveguides through laser ablation and plasma etching

NASA Astrophysics Data System (ADS)

Van Erps, Jürgen; Ciuk, Tymoteusz; Pasternak, Iwona; Krajewska, Aleksandra; Strupinski, Wlodek; Van Put, Steven; Van Steenberge, Geert; Baert, Kitty; Terryn, Herman; Thienpont, Hugo; Vermeulen, Nathalie

2016-05-01

We present the use of femtosecond laser ablation for the removal of monolayer graphene from silicon-on-insulator (SOI) waveguides, and the use of oxygen plasma etching through a metal mask to peel off graphene from the grating couplers attached to the waveguides. Through Raman spectroscopy and atomic force microscopy, we show that the removal of graphene is successful with minimal damage to the underlying SOI waveguides. Finally, we employ both removal techniques to measure the contribution of graphene to the loss of grating-coupled graphene-covered SOI waveguides using the cut-back method. This loss contribution is measured to be 0.132 dB/μm.

Two-mode division multiplexing in a silicon-on-insulator ring resonator.

PubMed

Dorin, Bryce A; Ye, Winnie N

2014-02-24

Mode-division multiplexing (MDM) is an emerging multiple-input multiple-output method, utilizing multimode waveguides to increase channel numbers. In the past, silicon-on-insulator (SOI) devices have been primarily focused on single-mode waveguides. We present the design and fabrication of a two-mode SOI ring resonator for MDM systems. By optimizing the device parameters, we have ensured that each mode is treated equally within the ring. Using adiabatic Bezier curves in the ring bends, our ring demonstrated a signal-to-crosstalk ratio above 18 dB for both modes at the through and drop ports. We conclude that the ring resonator has the potential for filtering and switching for MDM systems on SOI.

Analysis of Aluminum-Nitride SOI for High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Osman, Mohamed A.; Yu, Zhiping

2000-01-01

We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOSFETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (SiO2). Because the thermal conductivity of AIN is about 100 times that of SiO2, AIN SOI should greatly reduce the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations, and solved with a PDE solver called PROPHET In this work, we compare the performance of AIN-based SOI with that of SiO2-based SOI and conventional MOSFETs. We find that AIN SOI does indeed remove the self-heating penalty of SOL However, several device design trade-offs remain, which our simulations highlight.

The evolution of vacancy-type defects in silicon-on-insulator structures studied by positron annihilation spectroscopy

NASA Astrophysics Data System (ADS)

Coleman, P. G.; Nash, D.; Edwardson, C. J.; Knights, A. P.; Gwilliam, R. M.

2011-07-01

Variable-energy positron annihilation spectroscopy (VEPAS) has been applied to the study of the formation and evolution of vacancy-type defect structures in silicon (Si) and the 1.5 μm thick Si top layer of silicon-on-insulator (SOI) samples. The samples were implanted with 2 MeV Si ions at fluences between 1013 and 1015 cm-2, and probed in the as-implanted state and after annealing for 30 min at temperatures between 350 and 800 °C. In the case of SOI the ions were implanted such that their profile was predominantly in the insulating buried oxide layer, and thus their ability to combine with vacancies in the top Si layer, and that of other interstitials beyond the buried oxide, was effectively negated. No measurable differences in the positron response to the evolution of small clusters of n vacancies (Vn, n ˜ 3) in the top Si layer of the Si and SOI samples were observed after annealing up to 500 °C; at higher temperatures, however, this response persisted in the SOI samples as that in Si decreased toward zero. At 700 and 800 °C the damage in Si was below detectable levels, but the VEPAS response in the top Si layer in the SOI was consistent with the development of nanovoids.

Nano-optical single-photon response mapping of waveguide integrated molybdenum silicide (MoSi) superconducting nanowires.

PubMed

Li, Jian; Kirkwood, Robert A; Baker, Luke J; Bosworth, David; Erotokritou, Kleanthis; Banerjee, Archan; Heath, Robert M; Natarajan, Chandra M; Barber, Zoe H; Sorel, Marc; Hadfield, Robert H

2016-06-27

We present low temperature nano-optical characterization of a silicon-on-insulator (SOI) waveguide integrated SNSPD. The SNSPD is fabricated from an amorphous Mo₈₃Si₁₇ thin film chosen to give excellent substrate conformity. At 350 mK, the SNSPD exhibits a uniform photoresponse under perpendicular illumination, corresponding to a maximum system detection efficiency of approximately 5% at 1550 nm wavelength. Under these conditions 10 Hz dark count rate and 51 ps full width at half maximum (FWHM) timing jitter is observed.

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

NASA Astrophysics Data System (ADS)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

High-speed thin-film transistors on single-crystalline, unstrained- and strained-silicon-based nanomembranes

NASA Astrophysics Data System (ADS)

Yuan, Hao-Chih

This research focuses on developing high-performance single-crystal Si-based nanomembranes and high-frequency thin-film transistors (TFTs) using these nanomembranes on flexible plastic substrates. Unstrained Si or SiGe nanomembranes with thickness of several tens to a couple of hundred nanometers are derived from silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) and are subsequently transferred and integrated with flexible plastic host substrates via a one-step dry printing technique. Biaxial tensile-strained Si membranes that utilize elastic strain-sharing between Si and additionally grown SiGe thin films are also successfully integrated with plastic host substrates and exhibit predicted strain status and negligible density of dislocations. Biaxial tensile strain enhances electron mobility and lowers Schottky contact resistance. As a result, flexible TFTs built on the strained Si-membranes demonstrate much higher electron effective mobility and higher drive current than the unstrained counterpart. The dependence of drive current and transconductance on uniaxial tensile strain introducing by mechanical bending is also discussed. A novel combined "hot-and-cold" TFT fabrication process is developed specifically for realizing a wide spectrum of micro-electronics that can exhibit RF performance and can be integrated on low-temperature plastic substrate. The "hot" process that consists of ion implant and high-temperature annealing for desired doping type, profile, and concentration is realized on the bulk SOI/SGOI substrates followed by the "cold" process that includes room-temperature silicon-monoxide (SiO) deposition as gate dielectric layer to ensure the process compatibility with low-temperature, low-cost plastics. With these developments flexible Si-membrane n-type RF TFTs for analog applications and complementary TFTs for digital applications are demonstrated for the first time. RF TFTs with 1.5-mum channel length have demonstrated record-high f T and fmax values of 2.04 and 7.8 GHz, respectively. A small-signal equivalent circuit model study on the RF TFTs reveals the physics of how device layout affects fT and f max, which paves the way for further performance optimization and realization of integrated circuit on flexible substrate in the future.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Kondo effect with tunable spin-orbit interaction in LaTiO3/CeTiO3/SrTiO3 heterostructure.

PubMed

Ghising, Pramod; Das, Debarchan; Das, Shubhankar; Hossain, Z

2018-07-18

We have fabricated epitaxial films of CeTiO 3 (CTO) on (0 0 1) oriented SrTiO 3 (STO) substrates, which exhibit highly insulating and diamagnetic properties. X-ray photoelectron spectroscopy was used to establish the 3+  valence state of the Ce and Ti ions. Furthermore, we have also fabricated δ (CTO) doped LaTiO 3 (LTO)/SrTiO 3 thin films which exhibit variety of interesting properties including Kondo effect and spin-orbit interaction (SOI) at low temperatures. The SOI shows a non-monotonic behaviour as the thickness of the CTO layer is increased and is reflected in the value of characteristic SOI field ([Formula: see text]) obtained from weak anti-localization fitting. The maximum value of [Formula: see text] is 1.00 T for δ layer thickness of 6 u.c. This non-monotonic behaviour of SOI is attributed to the strong screening of the confining potential at the interface. The screening effect is enhanced by the CTO layer thickness and the dielectric constant of STO which increases at low temperatures. Due to the strong screening, electrons confined at the interface are spread deeper into the STO bulk where it starts to populate the Ti [Formula: see text] subbands; consequently the Fermi level crosses over from [Formula: see text] to the [Formula: see text] subbands. At the crossover region of [Formula: see text] where there is orbital mixing, SOI goes through a maximum.

Method to improve commercial bonded SOI material

DOEpatents

Maris, Humphrey John; Sadana, Devendra Kumar

2000-07-11

A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

On-chip broadband spectral filtering using planar double high-contrast grating reflectors

NASA Astrophysics Data System (ADS)

Horie, Yu; Arbabi, Amir; Faraon, Andrei

2015-02-01

We propose a broadband free-space on-chip spectrometer based on an array of integrated narrowband filters consisting of Fabry-Perot resonators formed by two high-contrast grating (HCG) based reflectors separated by a low-index thin layer with a fixed cavity thickness. Using numerical simulations, broadband tunability of resonance wavelengths was achieved only by changing the in-plane grating parameters such as period or duty cycle of HCGs while the substrate geometry was kept fixed. Experimentally, the HCG reflectors were fabricated on silicon on insulator (SOI) substrates and high reflectivity was measured, fabrication process for the proposed double HCG-based narrowband filter array was developed. The filtering function that can be spanned over a wide range of wavelengths was measured.

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Hung, Chinglin; Takeuchi, Ken

2012-04-01

The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Silicon-On-Insulator (SOI) Devices and Mixed-Signal Circuits for Extreme Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Electronic systems in planetary exploration missions and in aerospace applications are expected to encounter extreme temperatures and wide thermal swings in their operational environments. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of the missions. Electronic parts based on silicon-on-insulator (SOI) technology are known, based on device structure, to provide faster switching, consume less power, and offer better radiation-tolerance compared to their silicon counterparts. They also exhibit reduced current leakage and are often tailored for high temperature operation. However, little is known about their performance at low temperature. The performance of several SOI devices and mixed-signal circuits was determined under extreme temperatures, cold-restart, and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these devices for use in space exploration missions under extreme temperatures. The experimental results obtained on selected SOI devices are presented and discussed in this paper.

Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2018-06-01

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

A photonic crystal waveguide with silicon on insulator in the near-infrared band

NASA Astrophysics Data System (ADS)

Tang, Hai-Xia; Zuo, Yu-Hua; Yu, Jin-Zhong; Wang, Qi-Ming

2007-07-01

A two-dimensional (2D) photonic crystal waveguide in the Γ-K direction with triangular lattice on a silicon-on-insulator (SOI) substrate in the near-infrared band is fabricated by the combination of electron beam lithography and inductively coupled plasma etching. Its transmission characteristics are analysed from the stimulated band diagram by the effective index and the 2D plane wave expansion (PWE) methods. In the experiment, the transmission band edge in a longer wavelength of the photonic crystal waveguide is about 1590 nm, which is in good qualitative agreement with the simulated value. However, there is a disagreement between the experimental and the simulated results when the wavelength ranges from 1607 to 1630 nm, which can be considered as due to the unpolarized source used in the transmission measurement.

Performance analysis of SOI MOSFET with rectangular recessed channel

NASA Astrophysics Data System (ADS)

Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

2016-03-01

In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

NASA Astrophysics Data System (ADS)

Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

2008-04-01

We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

SOI technology for power management in automotive and industrial applications

NASA Astrophysics Data System (ADS)

Stork, Johannes M. C.; Hosey, George P.

2017-02-01

Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

Modeling and experimental investigation of an integrated optical microheater in silicon-on-insulator.

PubMed

Kaushal, Saket; Das, Bijoy Krishna

2016-04-10

A linear piecewise model has been formulated to analyze the performance of a metallic microheater integrated with single-mode waveguides (λ∼1550  nm) in silicon-on-insulator (SOI). The model has been used to evaluate integrated optical microheaters fabricated in a SOI substrate with 2 µm device layer thickness. The Fabry-Perot modulation technique has been used to extract the effective thermo-optic phase shift and response time. The effective thermal power budget of P_eff,π∼500  µW (out of actually consumed power P_π=1.1  mW) for a π phase shift and a switching time of τ∼9  µs, have been recorded for a typical Ti heater stripe of length L_H=50  µm, width W_H=2  µm, and thickness t_H∼150  nm, integrated with a Fabry-Perot waveguide cavity of length ∼20  mm. It has been shown that the performance of a heater improves (in terms of power budget) as the length of a microheater decreases. However, smaller heater size requires higher joule heating to obtain a desired phase shift, which is again found to be dependent on polarization of the guided mode because of thermal stress.

The ZnO-FET Biosensor for Cardiac Troponin I

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md; Nuzaihan, M. N. M.; Gopinath, Subash C. B.; Ruslinda, A. R.; Hashim, U.

2018-03-01

This paper investigates the influence of substrate-gate coupling on the ZnO-FET biosensor’s sensitivity for detection of cardiac troponin I (cTnI), a ‘gold standard’ biomarker for acute myocardial infarction (AMI). The FET-based device with introduction of substrate-gate coupling on p-type silicon-on-insulator (SOI) substrate is fabricated using conventional lithography processes. An n-type zinc oxide (ZnO) thin film deposited via electron-beam evaporator is used as transducer for bridging the source and drain regions. Surface modifications via functionalization with 3-aminopropyltriethoxysilane (APTES) and glutaraldehyde (GA) as chemical linkers, followed by immobilization of cTnI monoclonal antibody (MAb-cTnI) as bio-receptor on the ZnO thin film allow different concentration of cTnI detection with high selectivity. The device’s sensitivity increases up to 9 %·(g/ml)-1 with the increase of the substrate-gate voltage (VSG) up to -10 V at very low limit of detection (LOD) down to 1.6 fg/ml.

Optimized sensitivity of Silicon-on-Insulator (SOI) strip waveguide resonator sensor

PubMed Central

TalebiFard, Sahba; Schmidt, Shon; Shi, Wei; Wu, WenXuan; Jaeger, Nicolas A. F.; Kwok, Ezra; Ratner, Daniel M.; Chrostowski, Lukas

2017-01-01

Evanescent field sensors have shown promise for biological sensing applications. In particular, Silicon-on-Insulator (SOI)-nano-photonic based resonator sensors have many advantages for lab-on-chip diagnostics, including high sensitivity for molecular detection and compatibility with CMOS foundries for high volume manufacturing. We have investigated the optimum design parameters within the fabrication constraints of Multi-Project Wafer (MPW) foundries that result in the highest sensitivity for a resonator sensor. We have demonstrated the optimum waveguide thickness needed to achieve the maximum bulk sensitivity with SOI-based resonator sensors to be 165 nm using the quasi-TM guided mode. The closest thickness offered by MPW foundry services is 150 nm. Therefore, resonators with 150 nm thick silicon waveguides were fabricated resulting in sensitivities as high as 270 nm/RIU, whereas a similar resonator sensor with a 220 nm thick waveguide demonstrated sensitivities of approximately 200 nm/RIU. PMID:28270963

Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

PubMed

Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

2014-11-25

Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

A novel lateral IGBT with a controlled anode for on-off-state loss trade-off improvement

NASA Astrophysics Data System (ADS)

Wensuo, Chen; Bo, Zhang; Jian, Fang; Zhaoji, Li

2011-07-01

A new lateral insulated-gate bipolar transistor with a controlled anode (CA-LIGBT) on silicon-on-insulator (SOI) substrate is reported. Benefiting from both the enhanced conductivity modulation effect and the high resistance controlled electron extracting path, CA-LIGBT has a faster turn-off speed and lower forward drop, and the trade-off between off-state and on-state losses is better than that of state-of-the-art 3-D NCA-LIGBT, which we presented earlier. As the simulation results show, the ratios of figure of merit (FOM) for CA-LIGBT compared to that of 3-D NCA-LIGBT and conventional LIGBT are 1.45: 1 and 59.53: 1, respectively. And, the new devices can be created by using additional silicon direct bonding (SDB). So, from the power efficiency point of view, the proposed CA-LIGBT is a promising device for use in power ICs.

Photosensitive adhesive bonding process of magnetooptic waveguides with Si guiding layer for optical nonreciprocal devices

NASA Astrophysics Data System (ADS)

Choowitsakunlert, Salinee; Takagiwa, Kenji; Kobashigawa, Takuya; Hosoya, Nariaki; Silapunt, Rardchawadee; Yokoi, Hideki

2018-05-01

A photosensitive adhesive bonding process for a magnetooptic waveguide for an optical isolator employing a nonreciprocal guided-radiation mode conversion is investigated at 1.55 µm. The magnetooptic waveguide is a straight rib type, and it is fabricated by bonding the Si guiding layer to a magnetic garnet. In the fabrication process, an adhesive material is diluted to obtain a certain thickness before depositing on a silicon-on-insulator (SOI) substrate. The relationship between the percent dilution ratio and the thickness of the adhesive layer is considered. The smallest gap thickness is found to be 0.66 µm at a dilution ratio of 2%.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

DOE Office of Scientific and Technical Information (OSTI.GOV)

Caër, Charles; Le Roux, Xavier; Cassan, Eric, E-mail: eric.cassan@u-psud.fr

We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics.

Some material structural properties of SOI substrates produced by SDB technology

NASA Astrophysics Data System (ADS)

Hui, Li; Guo-Liang, Sun; Juan, Zhan; Qin-Yi, Tong

1987-10-01

SOI substrates have been produced by silicon direct bonding (SDB) technology. Thermal oxides ranging in thickness from native oxide to 1 μm or even more, on either or both wafers have been bonded successfully. The fracture strength of the SOI layer is 130-200 kg/cm 2 which is similar to the value of intrinsic bulk silicon. Dislocations have been shown to be concentrated on the backsides of the substrate and no additional defects have been developed within 80 μm of the Si-SiO 2 bonding area. Mobility and minority carrier lifetime similar to that of the original bulk silicon have been obtained after annealing.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Electron mobility in the inversion layers of fully depleted SOI films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I.

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished.more » The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.« less

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

DTIC Science & Technology

2016-08-01

APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...mechanism on which to base on-chip nonlinear optical devices compatible with a rapidly growing silicon photonics toolbox.3–9 While silicon on insulator

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

NASA Astrophysics Data System (ADS)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

Very thin, high Ge content Si 0.3Ge 0.7 relaxed buffer grown by MBE on SOI(0 0 1) substrate

NASA Astrophysics Data System (ADS)

Myronov, M.; Shiraki, Y.

2007-04-01

Growth procedure and excellent properties of very thin 240 nm thick, 95% relaxed, high Ge content Si 0.3Ge 0.7 buffer grown on SOI(0 0 1) substrate are demonstrated. All epilayers of the newly developed Si 0.3Ge 0.7/SOI(0 0 1) variable-temperature virtual substrate were grown in a single process by solid-source molecular beam epitaxy. Surface analysis of grown samples revealed smooth, cross-hatch free surface with low root mean square surface roughness of 0.9 nm and low threading dislocations density of 5×10 4 cm -2.

A photonic crystal ring resonator formed by SOI nano-rods.

PubMed

Chiu, Wei-Yu; Huang, Tai-Wei; Wu, Yen-Hsiang; Chan, Yi-Jen; Hou, Chia-Hunag; Chien, Huang Ta; Chen, Chii-Chang

2007-11-12

The design, fabrication and measurement of a silicon-on-insulator (SOI) two-dimensional photonic crystal ring resonator are demonstrated in this study. The structure of the photonic crystal is comprised of silicon nano-rods arranged in a hexagonal lattice on an SOI wafer. The photonic crystal ring resonator allows for the simultaneous separation of light at wavelengths of 1.31 and 1.55mum. The device is fabricated by e-beam lithography. The measurement results confirm that a 1.31mum/1.55mum wavelength ring resonator filter with a nano-rod photonic crystal structure can be realized.

Coupled resonator optical waveguides based on silicon-on-insulator photonic wires

NASA Astrophysics Data System (ADS)

Xia, Fengnian; Sekaric, Lidija; O'Boyle, Martin; Vlasov, Yurii

2006-07-01

Coupled resonator optical waveguides (CROWs) comprised of up to 16 racetrack resonators based on silicon-on-insulator (SOI) photonic wires were fabricated and characterized. The optical properties of the CROWs were simulated using measured single resonator parameters based on a matrix approach. The group delay property of CROWs was also analyzed. The SOI based CROWs consisting of multiple resonators have extremely small footprints and can find applications in optical filtering, dispersion compensation, and optical buffering. Moreover, such CROW structure is a promising candidate for exploration of low light level nonlinear optics due to its resonant nature and compact mode size (˜0.1μm2) in photonic wire.

Visible light laser voltage probing on thinned substrates

DOEpatents

Beutler, Joshua; Clement, John Joseph; Miller, Mary A.; Stevens, Jeffrey; Cole, Jr., Edward I.

2017-03-21

The various technologies presented herein relate to utilizing visible light in conjunction with a thinned structure to enable characterization of operation of one or more features included in an integrated circuit (IC). Short wavelength illumination (e.g., visible light) is applied to thinned samples (e.g., ultra-thinned samples) to achieve a spatial resolution for laser voltage probing (LVP) analysis to be performed on smaller technology node silicon-on-insulator (SOI) and bulk devices. Thinning of a semiconductor material included in the IC (e.g., backside material) can be controlled such that the thinned semiconductor material has sufficient thickness to enable operation of one or more features comprising the IC during LVP investigation.

Silicon/III-V laser with super-compact diffraction grating for WDM applications in electronic-photonic integrated circuits.

PubMed

Wang, Yadong; Wei, Yongqiang; Huang, Yingyan; Tu, Yongming; Ng, Doris; Lee, Cheewei; Zheng, Yunan; Liu, Boyang; Ho, Seng-Tiong

2011-01-31

We have demonstrated a heterogeneously integrated III-V-on-Silicon laser based on an ultra-large-angle super-compact grating (SCG). The SCG enables single-wavelength operation due to its high-spectral-resolution aberration-free design, enabling wavelength division multiplexing (WDM) applications in Electronic-Photonic Integrated Circuits (EPICs). The SCG based Si/III-V laser is realized by fabricating the SCG on silicon-on-insulator (SOI) substrate. Optical gain is provided by electrically pumped heterogeneous integrated III-V material on silicon. Single-wavelength lasing at 1550 nm with an output power of over 2 mW and a lasing threshold of around 150 mA were achieved.

Spin-orbit tuned metal-insulator transitions in single-crystal Sr₂Ir 1–xRh xO₄ (0≤x≤1)

DOE PAGES

Qi, T. F.; Korneta, O. B.; Li, L.; ...

2012-09-06

Sr₂IrO₄ is a magnetic insulator driven by spin-orbit interaction (SOI) whereas the isoelectronic and isostructural Sr₂RhO₄ is a paramagnetic metal. The contrasting ground states have been shown to result from the critical role of the strong SOI in the iridate. Our investigation of structural, transport, magnetic, and thermal properties reveals that substituting 4d Rh⁴⁺ (4d⁵) ions for 5d Ir⁴⁺ (5d⁵) ions in Sr₂IrO₄ directly reduces the SOI and rebalances the competing energies so profoundly that it generates a rich phase diagram for Sr₂Ir 1–xRh xO₄ featuring two major effects: (1) Light Rh doping (0 ≤ x ≤ 0.16) prompts amore » simultaneous and precipitous drop in both the electrical resistivity and the magnetic ordering temperature TC, which is suppressed to zero at x = 0.16 from 240 K at x = 0. (2) However, with heavier Rh doping [0.24 < x < 0.85 (±0.05)] disorder scattering leads to localized states and a return to an insulating state with spin frustration and exotic magnetic behavior that only disappears near x = 1. The intricacy of Sr₂Ir 1–xRh xO₄ is further highlighted by comparison with Sr₂Ir 1–xRu xO₄ where Ru⁴⁺ (4d⁴) drives a direct crossover from the insulating to metallic states.« less

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2016-10-01

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

Magnetic adatoms in two and four terminal graphene nanoribbons: A comparison between their spin polarized transport

NASA Astrophysics Data System (ADS)

Ganguly, Sudin; Basu, Saurabh

2018-04-01

We study the charge and spin transport in two and four terminal graphene nanoribbons (GNR) decorated with random distribution of magnetic adatoms. The inclusion of the magnetic adatoms generates only the z-component of the spin polarized conductance via an exchange bias in the absence of Rashba spin-orbit interaction (SOI), while in presence of Rashba SOI, one is able to create all the three (x, y and z) components. This has important consequences for possible spintronic applications. The charge conductance shows interesting behaviour near the zero of the Fermi energy. Where in presence of magnetic adatoms the familiar plateau at 2e2 / h vanishes, thereby transforming a quantum spin Hall insulating phase to an ordinary insulator. The local charge current and the local spin current provide an intuitive idea on the conductance features of the system. We found that, the local charge current is independent of Rashba SOI, while the three components of the local spin currents are sensitive to Rashba SOI. Moreover the fluctuations of the spin polarized conductance are found to be useful quantities as they show specific trends, that is, they enhance with increasing adatom densities. A two terminal GNR device seems to be better suited for possible spintronic applications.

A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

2008-01-01

A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

Silicon-on-insulator based nanopore cavity arrays for lipid membrane investigation.

PubMed

Buchholz, K; Tinazli, A; Kleefen, A; Dorfner, D; Pedone, D; Rant, U; Tampé, R; Abstreiter, G; Tornow, M

2008-11-05

We present the fabrication and characterization of nanopore microcavities for the investigation of transport processes in suspended lipid membranes. The cavities are situated below the surface of silicon-on-insulator (SOI) substrates. Single cavities and large area arrays were prepared using high resolution electron-beam lithography in combination with reactive ion etching (RIE) and wet chemical sacrificial underetching. The locally separated compartments have a circular shape and allow the enclosure of picoliter volume aqueous solutions. They are sealed at their top by a 250 nm thin Si membrane featuring pores with diameters from 2 µm down to 220 nm. The Si surface exhibits excellent smoothness and homogeneity as verified by AFM analysis. As biophysical test system we deposited lipid membranes by vesicle fusion, and demonstrated their fluid-like properties by fluorescence recovery after photobleaching. As clearly indicated by AFM measurements in aqueous buffer solution, intact lipid membranes successfully spanned the pores. The nanopore cavity arrays have potential applications in diagnostics and pharmaceutical research on transmembrane proteins.

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

NASA Astrophysics Data System (ADS)

Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

2016-11-01

This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

Mach-Zehnder Interferometer Biochemical Sensor Based on Silicon-on-Insulator Rib Waveguide with Large Cross Section

PubMed Central

Yuan, Dengpeng; Dong, Ying; Liu, Yujin; Li, Tianjian

2015-01-01

A high-sensitivity Mach-Zehnder interferometer (MZI) biochemical sensing platform based on Silicon-in-insulator (SOI) rib waveguide with large cross section is proposed in this paper. Based on the analyses of the evanescent field intensity, the mode polarization and cross section dimensions of the SOI rib waveguide are optimized through finite difference method (FDM) simulation. To realize high-resolution MZI read-out configuration based on the SOI rib waveguide, medium-filled trenches are employed and their performances are simulated through two-dimensional finite-difference-time domain (2D-FDTD) method. With the fundamental EH-polarized mode of the SOI rib waveguide with a total rib height of 10 μm, an outside rib height of 5 μm and a rib width of 2.5 μm at the operating wavelength of 1550 nm, when the length of the sensitive window in the MZI configuration is 10 mm, a homogeneous sensitivity of 7296.6%/refractive index unit (RIU) is obtained. Supposing the resolutions of the photoelectric detectors connected to the output ports are 0.2%, the MZI sensor can achieve a detection limit of 2.74 × 10−6 RIU. Due to high coupling efficiency of SOI rib waveguide with large cross section with standard single-mode glass optical fiber, the proposed MZI sensing platform can be conveniently integrated with optical fiber communication systems and (opto-) electronic systems, and therefore has the potential to realize remote sensing, in situ real-time detecting, and possible applications in the internet of things. PMID:26343678

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

NASA Astrophysics Data System (ADS)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Controlled waveguide coupling for photon emission from colloidal PbS quantum dot using tunable microcavity made of optical polymer and silicon

NASA Astrophysics Data System (ADS)

Nozaka, Takahiro; Mukai, Kohki

2016-04-01

A tunable microcavity device composed of optical polymer and Si with a colloidal quantum dot (QD) is proposed as a single-photon source for planar optical circuit. Cavity size is controlled by electrostatic micromachine behavior with the air bridge structure to tune timing of photon injection into optical waveguide from QD. Three-dimensional positioning of a QD in the cavity structure is available using a nanohole on Si processed by scanning probe microscope lithography. We fabricated the prototype microcavity with PbS-QD-mixed polymenthyl methacrylate on a SOI (semiconductor-on-insulator) substrate to show the tunability of cavity size as the shift of emission peak wavelength of QD ensemble.

Methods of producing strain in a semiconductor waveguide and related devices

DOEpatents

Cox, Johathan Albert; Rakich, Peter Thomas

2016-02-16

Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.

A Systematic Transport and Thermodynamic Study of Heavy Transition Metal Oxides with Hexagonal Structure

NASA Astrophysics Data System (ADS)

Butrouna, Kamal

There is no apparent, dominant interaction in heavy transition metal oxides (TMO), especially in 5d-TMO, where all relevant interactions are of comparable energy scales, and therefore strongly compete. In particular, the spin-orbit interaction (SOI) strongly competes with the electron-lattice and on-site Coulomb interaction (U). Therefore, any tool that allows one to tune the relative strengths of SOI and U is expected to offer an opportunity for the discovery and study of novel materials. BaIrO3 is a magnetic insulator driven by SOI, whereas the isostructural BaRuO3 is a paramagnetic metal. The contrasting ground states have been shown to result from the critical role of SOI in the iridate. This dissertation thoroughly examines a wide array of newly observed novel phenomena induced by adjusting the relative strengths of SOI and U via a systematic chemical substitution of the Ru4+(4d 4) ions for Ir4+(5d5) ions in BaIrO3, i.e., in high quality single crystals of BaIr1--x RuxO3(0.0 ≤ x ≤ 1.0). Our investigation of structural, magnetic, transport and thermal properties reveals that Ru substitution directly rebalances the competing energies so profoundly that it generates a rich phase diagram for BaIr 1--xRuxO 3 featuring two major effects: (1) Light Ru doping (0 ≤ x ≤ 0.15) prompts a simultaneous and precipitous drop in both the magnetic ordering temperature TC and the electrical resistivity, which exhibits metal-insulator transition at around TC. (2) Heavier Ru doping (0.41 ≤ x ≤ 0.82) induces a robust metallic and spin frustration state. For comparison and contrast, we also substituted Rh4+(4d 5) ions for Ir4+(5d5) ions in BaIrO3, i.e. in BaIr1--xRhxO 3(0.0 ≤ x ≤ 0.1), where Rh only reduces the SOI, but without altering the band filling. Hence, this system remains tuned at the Mott instability and is very susceptible to disorder scattering which gives rise to Anderson localization. KEYWORDS: spin-orbit interaction, heavy transition metal oxides, barium iridate, metal-insulator transition, magnetic order.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmid, H., E-mail: sih@zurich.ibm.com; Borg, M.; Moselund, K.

2015-06-08

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm{sup 2}/V s, while the alongsidemore » fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at V{sub DS} = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.« less

MEMS based Low Cost Piezoresistive Microcantilever Force Sensor and Sensor Module

PubMed Central

Pandya, H. J.; Kim, Hyun Tae; Roy, Rajarshi; Desai, Jaydev P.

2014-01-01

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in Argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400–1050°C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050°C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 µm in length, 40 µm wide and 1.0 µm thick. A series of force-displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488N/m and 2.7mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen. PMID:24855449

MEMS based Low Cost Piezoresistive Microcantilever Force Sensor and Sensor Module.

PubMed

Pandya, H J; Kim, Hyun Tae; Roy, Rajarshi; Desai, Jaydev P

2014-03-01

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in Argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400-1050°C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050°C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 µm in length, 40 µm wide and 1.0 µm thick. A series of force-displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488N/m and 2.7mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen.

High breakdown voltage and high driving current in a novel silicon-on-insulator MESFET with high- and low-resistance boxes in the drift region

NASA Astrophysics Data System (ADS)

Naderi, Ali; Mohammadi, Hamed

2018-06-01

In this paper a novel silicon-on-insulator metal oxide field effect transistor (SOI-MESFET) with high- and low-resistance boxes (HLRB) is proposed. This structure increases the current and breakdown voltage, simultaneously. The semiconductor at the source side of the channel is doped with higher impurity than the other parts to reduce its resistance and increase the driving current as low-resistance box. An oxide box is implemented at the upper part of the channel from the drain region toward the middle of the channel as the high-resistance box. Inserting a high-resistance box increases the breakdown voltage and improves the RF performance of the device because of its higher tolerable electric field and modification in gate-drain capacitance, respectively. The high-resistance region reduces the current density of the device which is completely compensated by low-resistance box. A 92% increase in breakdown voltage and an 11% improvement in the device current have been obtained. Also, maximum oscillation frequency, unilateral power gain, maximum available gain, maximum stable gain, and maximum output power density are improved by 7%, 35%, 23%, 26%, and 150%, respectively. These results show that the HLRB-SOI-MESFET can be considered as a candidate to replace Conventional SOI-MESFET (C-SOI-MESFET) for high-voltage and high-frequency applications.

A Wide Range Temperature Sensor Using SOI Technology

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Elbuluk, Malik E.; Hammoud, Ahmad

2009-01-01

Silicon-on-insulator (SOI) technology is becoming widely used in integrated circuit chips for its advantages over the conventional silicon counterpart. The decrease in leakage current combined with lower power consumption allows electronics to operate in a broader temperature range. This paper describes the performance of an SOIbased temperature sensor under extreme temperatures and thermal cycling. The sensor comprised of a temperature-to-frequency relaxation oscillator circuit utilizing an SOI precision timer chip. The circuit was evaluated under extreme temperature exposure and thermal cycling between -190 C and +210 C. The results indicate that the sensor performed well over the entire test temperature range and it was able to re-start at extreme temperatures.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

Fabrication and characterization of the Si-photonics-integrated vertical resonant-cavity light-emitting diode

NASA Astrophysics Data System (ADS)

Kong, Duanhua; Kim, Taek; Kim, Sihan; Hong, Hyungi; Shcherbatko, Igor; Park, Youngsoo; Shin, Dongjae; Ha, Kyoung-Ho; Jeong, Gitae

2014-03-01

We designed and fabricated a 1.3-um hybrid vertical Resonant-Cavity Light-Emitting Diode for optical interconnect by using direct III-V wafer bonding on silicon on insulator (SOI). The device included InP based front distributed Bragg reflector (DBR), InGaAlAs based active layer, and SOI-based high-contrast-grating (HCG) as a back reflector. 42-uW continuous wave optical power was achieved at 20mA at room temperature.

Mechanically detected terahertz electron spin resonance using SOI-based thin piezoresistive microcantilevers

NASA Astrophysics Data System (ADS)

Ohmichi, Eiji; Miki, Toshihiro; Horie, Hidekazu; Okamoto, Tsubasa; Takahashi, Hideyuki; Higashi, Yoshinori; Itoh, Shoichi; Ohta, Hitoshi

2018-02-01

We developed piezoresistive microcantilevers for mechanically detected electron spin resonance (ESR) in the millimeter-wave region. In this article, fabrication process and device characterization of our self-sensing microcantilevers are presented. High-frequency ESR measurements of a microcrystal of paramagnetic sample is also demonstrated at multiple frequencies up to 160 GHz at liquid helium temperature. Our fabrication is based on relatively simplified processes with silicon-on-insulator (SOI) wafers and spin-on diffusion doping, thus enabling cost-effective and time-saving cantilever fabrication.

SiNOI and AlGaAs-on-SOI nonlinear circuits for continuum generation in Si photonics

NASA Astrophysics Data System (ADS)

El Dirani, Houssein; Monat, Christelle; Brision, Stéphane; Olivier, Nicolas; Jany, Christophe; Letartre, Xavier; Pu, Minhao; Girouard, Peter D.; Hagedorn Frandsen, Lars; Semenova, Elizaveta; Katsuo Oxenløwe, Leif; Yvind, Kresten; Sciancalepore, Corrado

2018-02-01

In this communication, we report on the design, fabrication, and testing of Silicon Nitride on Insulator (SiNOI) and Aluminum-Gallium-Arsenide (AlGaAs) on silicon-on-insulator (SOI) nonlinear photonic circuits for continuum generation in Silicon (Si) photonics. As recently demonstrated, the generation of frequency continua and supercontinua can be used to overcome the intrinsic limitations of nowadays silicon photonics notably concerning the heterogeneous integration of III-V on SOI lasers for datacom and telecom applications. By using the Kerr nonlinearity of monolithic silicon nitride and heterointegrated GaAs-based alloys on SOI, the generation of tens or even hundreds of new optical frequencies can be obtained in dispersion tailored waveguides, thus providing an all-optical alternative to the heterointegration of hundreds of standalone III-V on Si lasers. In our work, we present paths to energy-efficient continua generation on silicon photonics circuits. Notably, we demonstrate spectral broadening covering the full C-band via Kerrbased self-phase modulation in SiNOI nanowires featuring full process compatibility with Si photonic devices. Moreover, AlGaAs waveguides are heterointegrated on SOI in order to dramatically reduce (x1/10) thresholds in optical parametric oscillation and in the power required for supercontinuum generation under pulsed pumping. The manufacturing techniques allowing the monolithic co-integration of nonlinear functionalities on existing CMOS-compatible Si photonics for both active and passive components will be shown. Experimental evidence based on self-phase modulation show SiNOI and AlGaAs nanowires capable of generating wide-spanning frequency continua in the C-Band. This will pave the way for low-threshold power-efficient Kerr-based comb- and continuum- sources featuring compatibility with Si photonic integrated circuits (Si-PICs).

Thin-film piezoelectric-on-silicon resonators for high-frequency reference oscillator applications.

PubMed

Abdolvand, Reza; Lavasani, Hossein M; Ho, Gavin K; Ayazi, Farrokh

2008-12-01

This paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators. Low-motional-impedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array. Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed. Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient. The lowest reported power consumption is approximately 350 microW for an oscillator operating at approximately 106 MHz. A passive temperature compensation method is also utilized by including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-2.4 ppm/ degrees C) temperature coefficient of frequency is obtained for an 82-MHz oscillator.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Novel detectors for silicon based microdosimetry, their concepts and applications

NASA Astrophysics Data System (ADS)

Rosenfeld, Anatoly B.

2016-02-01

This paper presents an overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for microdosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years. In this paper every generation of CMRP SOI microdosimeters, including their fabrication, design, and electrical and charge collection characterisation are presented. A study of SOI microdosimeters in various radiation fields has demonstrated that under appropriate geometrical scaling, the response of SOI detectors with the well-known geometry of microscopically sensitive volumes will record the energy deposition spectra representative of tissue cells of an equivalent shape. This development of SOI detectors for microdosimetry with increased complexity has improved the definition of microscopic sensitive volume (SV), which is modelling the deposition of ionising energy in a biological cell, that are led from planar to 3D SOI detectors with an array of segmented microscopic 3D SVs. The monolithic ΔE-E silicon telescope, which is an alternative to the SOI silicon microdosimeter, is presented, and as an example, applications of SOI detectors and ΔE-E monolithic telescope for microdosimetery in proton therapy field and equivalent neutron dose measurements out of field are also presented. An SOI microdosimeter "bridge" with 3D SVs can derive the relative biological effectiveness (RBE) in 12C ion radiation therapy that matches the tissue equivalent proportional counter (TEPC) quite well, but with outstanding spatial resolution. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates, and the possibility of integrating the system onto a single device with other types of detectors.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

A proposal for digital electro-optic switches with free-carrier dispersion effect and Goos-Hanchen shift in silicon-on-insulator waveguide corner mirror

NASA Astrophysics Data System (ADS)

Sun, DeGui

2013-09-01

In a silicon-on-insulator (SOI) waveguide corner mirror (WCM) structure, with the quantum process of a frustrated total internal reflection (FTIR) phenomenon and the time delay principle in the two-dimensional potential barrier tunneling process of a mass of particles, we derive an accurate physical model for the Goos-Hanchen (GH) shift of optical guided-mode in the FTIR process, and in principle match the GH shift jumping states with the independent guided-modes. Then, we propose and demonstrate a new regime of 1 × N digital optical switches with a matching state between the free-carrier dispersion (FCD) based refractive index modulation (RIM) of silicon to create a GH shift jumping function of a photonic signal at the reflecting interface and the independent guided-modes in the FTIR process, where a MOS-capacitor type electro-optic modulation regime is proposed and discussed to realize an effective FCD-based RIM. At the critical matching state, i.e., the incident of an optical beam is at the vicinity of Brewster angle in the WCM, a mini-change of refractive index of waveguide material can cause a great jump of GH shift along the FTIR reflecting interface, and further a 1 × N digital optical switching process could be realized. For a 350-500 nm single-mode rib waveguide made on the 220 nm CMOS-compatible SOI substrate and with the FCD effect based RIM of silicon crystal, a concentration variation of 1018-1019 cm-3 has caused a 0.5-2.5 μm GH shift of reflected beam, which is at 2-5 times of a mode-size and hence radically convinces an optical switching function with a 1 × 3-1 × 10 scale.

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

NASA Astrophysics Data System (ADS)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Decoupling of the antiferromagnetic and insulating states in Tb-doped Sr 2IrO 4

DOE PAGES

Wang, J. C.; Aswartham, S.; Ye, Feng; ...

2015-12-08

Sr 2IrO 4 is a spin-orbit coupled insulator with an antiferromagnetic (AFM) transition at T N = 240 K. We report results of a comprehensive study of single-crystal Sr 2Ir 1-xTb xO 4 (0≤x≤0.03). This study found that mere 3% (x=0.03) tetravalent Tb 4+(4f 7) substituting for Ir 4+ (rather than Sr 2+) completely suppresses the long-range collinear AFM transition but retains the insulating state, leading to a phase diagram featuring a decoupling of magnetic interactions and charge gap. The insulating state at x = 0.03 is characterized by an unusually large specific heat at low temperatures and an incommensuratemore » magnetic state having magnetic peaks at (0.95, 0, 0) and (0, 0.95, 0) in the neutron diffraction, suggesting a spiral or spin density wave order. It is apparent that Tb doping effectively changes the relative strength of the SOI and the tetragonal CEF and enhances the Hund’s rule coupling that competes with the SOI, and destabilizes the AFM state. However, the disappearance of the AFM accompanies no metallic state chiefly because an energy level mismatch for the Ir and Tb sites weakens charge carrier hopping and renders a persistent insulating state. Furthermore, this work highlights an unconventional correlation between the AFM and insulating states in which the magnetic transition plays no critical role in the formation of the charge gap in the iridate.« less

Superconductivity bordering Rashba type topological transition

DOE PAGES

Jin, M. L.; Sun, F.; Xing, L. Y.; ...

2017-01-04

Strong spin orbital interaction (SOI) can induce unique quantum phenomena such as topological insulators, the Rashba effect, or p-wave superconductivity. Combining these three quantum phenomena into a single compound has important scientific implications. Here we report experimental observations of consecutive quantum phase transitions from a Rashba type topological trivial phase to topological insulator state then further proceeding to superconductivity in a SOI compound BiTeI tuned via pressures. The electrical resistivity measurement with V shape change signals the transition from a Rashba type topological trivial to a topological insulator phase at 2 GPa, which is caused by an energy gap closemore » then reopen with band inverse. Superconducting transition appears at 8 GPa with a critical temperature T C of 5.3 K. Structure refinements indicate that the consecutive phase transitions are correlated to the changes in the Bi–Te bond and bond angle as function of pressures. As a result, the Hall Effect measurements reveal an intimate relationship between superconductivity and the unusual change in carrier density that points to possible unconventional superconductivity.« less

High Efficiency Photovoltaic and Plasmonic Devices

DTIC Science & Technology

2011-07-01

on Si or SOI substrate along with its band alignment. This elongated mesa forms a strip channel aveguide……………………………….…4 Figure 3 Radiative and...lattice matched GeSn relaxed buffer on Si or SOI substrate along with its band alignment. This elongated mesa forms a strip channel waveguide...Appl. Phys. Lett. 90, 251105 (2007). 8. R. A. Soref and C. H. Perry, J. Appl. Phys. 69, 539 (1991). 9. H. P. L. de Guevara, A. G. Rodriguez , H

Toward athermal silicon-on-insulator (de)multiplexers in the O-band.

PubMed

Hassan, Karim; Sciancalepore, Corrado; Harduin, Julie; Ferrotti, Thomas; Menezo, Sylvie; Ben Bakir, Badhise

2015-06-01

We report on the design, fabrication, and characterization of a 1×4 silicon-on-insulator (SOI) demultiplexer exhibiting a significant reduction of its thermo-optical sensitivity in the O-band. The optical filtering is achieved by cascading several Mach-Zehnder interferometers (MZIs) fabricated on a 300-nm-thick SOI platform. Owing to an asymmetric design of the confinement for each MZIs, we found an athermal criterium that satisfies the spectral requirements. The thermal sensitivity of the structure is analyzed by a semi-analytical model in order to create an athermal multiplexer. Fiber-to-fiber thermo-optical testing reveals a thermal sensitivity of around 17  pm/°C reduced by 75% compared to the standard devices with promising performances for both the crosstalk (15 dB), the insertion losses (4 dB), and absolute lambda registration (<0.25  nm).

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Experimental demonstration of two-dimensional hybrid waveguide-integrated plasmonic crystals on silicon-on-insulator platform

NASA Astrophysics Data System (ADS)

Ren, Guanghui; Yudistira, Didit; Nguyen, Thach G.; Khodasevych, Iryna; Schoenhardt, Steffen; Berean, Kyle J.; Hamm, Joachim M.; Hess, Ortwin; Mitchell, Arnan

2017-07-01

Nanoscale plasmonic structures can offer unique functionality due to extreme sub-wavelength optical confinement, but the realization of complex plasmonic circuits is hampered by high propagation losses. Hybrid approaches can potentially overcome this limitation, but only few practical approaches based on either single or few element arrays of nanoantennas on dielectric nanowire have been experimentally demonstrated. In this paper, we demonstrate a two dimensional hybrid photonic plasmonic crystal interfaced with a standard silicon photonic platform. Off resonance, we observe low loss propagation through our structure, while on resonance we observe strong propagation suppression and intense concentration of light into a dense lattice of nanoscale hot-spots on the surface providing clear evidence of a hybrid photonic plasmonic crystal bandgap. This fully integrated approach is compatible with established silicon-on-insulator (SOI) fabrication techniques and constitutes a significant step toward harnessing plasmonic functionality within SOI photonic circuits.

Effects of heat induced by two-photon absorption and free-carrier absorption in silicon-on-insulator nanowaveguides operating as all-optical wavelength converters.

PubMed

Abdollahi, Siamak; Moravvej-Farshi, Mohammad Kazem

2009-05-01

We propose a new numerical model to analyze heat induced by two-photon absorption and free-carrier absorption, while high intensity optical pulses propagate along silicon-on-insulator (SOI) nanowaveguides (NWGs). Using this model, we demonstrate that such induced heat causes a shift in the amount of wavelength conversion and hence deteriorates the converter output characteristics for pulses in the picosecond regime. The wavelength shift induced by a pulse with maximum input intensity and full width at half-maximum of I(max)=1.5x10(10) W x cm(-2) and T(FWHM)=30 ps, propagating along a SOI NWG with an effective cross-sectional area of a(eff)=0.15 microm(2), is shown to be Delta lambda(s) approximately 8 pm. We also demonstrate that such a shift can be compensated by tuning the pump intensity down by approximately 6.33%.

Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET

NASA Astrophysics Data System (ADS)

Ueda, Daiki; Takeuchi, Kiyoshi; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-04-01

A new circuit model that provides a clear guide on designing a MOS-gated thyristor (MGT) is reported. MGT plays a significant role in achieving a steep subthreshold slope of a PN-body tied silicon-on-insulator (SOI) FET (PNBTFET), which is an SOI MOSFET merged with an MGT. The effects of design parameters on MGT and the proposed equivalent circuit model are examined to determine how to regulate the voltage response of MGT and how to suppress power dissipation. It is demonstrated that MGT with low threshold voltages, small hysteresis widths, and small power dissipation can be designed by tuning design parameters. The temperature dependence of MGT is also examined, and it is confirmed that hysteresis width decreases with the average threshold voltage kept nearly constant as temperature rises. The equivalent circuit model can be conveniently used to design low-power PNBTFET.

Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

NASA Astrophysics Data System (ADS)

Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

2018-04-01

We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

Ultra compact triplexing filters based on SOI nanowire AWGs

NASA Astrophysics Data System (ADS)

Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

2011-04-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

Design, fabrication, and characteristics of microheaters with low consumption power using SDB SOI membrane and trench structures

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang; Choi, Sung-Kyu; Nam, Hoy-Duck

2001-10-01

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro electro mechanical system) applications using SDB and SOI membranes and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10 micrometers thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro- heater was fabricated with Pt-RTD on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280 degree(s)C at input power 0.9 W; for the SOI membrane with 10 trenches, it is 580 degree(s)C due to reduction of the external thermal loss. Consequently, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Guided wave opto-acoustic device

DOEpatents

Jarecki, Jr., Robert L.; Rakich, Peter Thomas; Camacho, Ryan; Shin, Heedeuk; Cox, Jonathan Albert; Qiu, Wenjun; Wang, Zheng

2016-02-23

The various technologies presented herein relate to various hybrid phononic-photonic waveguide structures that can exhibit nonlinear behavior associated with traveling-wave forward stimulated Brillouin scattering (forward-SBS). The various structures can simultaneously guide photons and phonons in a suspended membrane. By utilizing a suspended membrane, a substrate pathway can be eliminated for loss of phonons that suppresses SBS in conventional silicon-on-insulator (SOI) waveguides. Consequently, forward-SBS nonlinear susceptibilities are achievable at about 3000 times greater than achievable with a conventional waveguide system. Owing to the strong phonon-photon coupling achievable with the various embodiments, potential application for the various embodiments presented herein cover a range of radiofrequency (RF) and photonic signal processing applications. Further, the various embodiments presented herein are applicable to applications operating over a wide bandwidth, e.g. 100 MHz to 50 GHz or more.

Optomechanical and photothermal interactions in suspended photonic crystal membranes.

PubMed

Woolf, David; Hui, Pui-Chuen; Iwase, Eiji; Khan, Mughees; Rodriguez, Alejandro W; Deotare, Parag; Bulu, Irfan; Johnson, Steven G; Capasso, Federico; Loncar, Marko

2013-03-25

We present here an optomechanical system fabricated with novel stress management techniques that allow us to suspend an ultrathin defect-free silicon photonic-crystal membrane above a Silicon-on-Insulator (SOI) substrate with a gap that is tunable to below 200 nm. Our devices are able to generate strong attractive and repulsive optical forces over a large surface area with simple in- and out- coupling and feature the strongest repulsive optomechanical coupling in any geometry to date (gOM/2π ≈65 GHz/nm). The interplay between the optomechanical and photo-thermal-mechanical dynamics is explored, and the latter is used to achieve cooling and amplification of the mechanical mode, demonstrating that our platform is well-suited for potential applications in low-power mass, force, and refractive-index sensing as well as optomechanical accelerometry.

Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

NASA Astrophysics Data System (ADS)

Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

2017-10-01

We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

Microelectromechanical Systems (MEMS) Photoacoustic (PA) Detector of Terahertz (THz) Radiation for Chemical Sensing

DTIC Science & Technology

2014-03-01

26 Feb 2014 Ivan Medvedev, PhD (Member) Date iv AFIT-ENG-14-M-58 Abstract In this research effort, a Microelectromechanical...7. Separation by implantation of oxygen (SIMOX) is a process of creating silicon- on-insulator (SOI) wafers. Oxygen ions are implanted into a silicon...wafer. The depth of the insulating layer is dependent upon the power used during ion implantation [14]. .............................. 16  Figure 8

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

NASA Astrophysics Data System (ADS)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Spin transport and accumulation in n{sup +}-Si using Heusler compound Co{sub 2}FeSi/MgO tunnel contacts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishikawa, Mizue, E-mail: mizue.ishikawa@toshiba.co.jp; Sugiyama, Hideyuki; Inokuchi, Tomoaki

2015-08-31

We investigate spin transport and accumulation in n{sup +}-Si using Heusler compound Co{sub 2}FeSi/MgO/Si on insulator (SOI) devices. The magnitudes of the non-local four- and three-terminal Hanle effect signals when using Heusler compound Co{sub 2}FeSi/MgO/SOI devices are larger than when using CoFe/MgO/SOI devices, whereas the preparation methods of MgO layers on SOI are exactly same in both devices. Different bias voltage dependencies on the magnitude of spin accumulation signals are also observed between these devices. Especially, Co{sub 2}FeSi/MgO/SOI devices show large spin accumulation signals compared with CoFe/MgO/SOI devices in the low bias voltage region less than ∼1000 mV in which themore » increase of the spin polarization is expected from the estimation of the density of states in Heusler compound Co{sub 2}FeSi and CoFe under spin extraction conditions. These results indicate that the species of ferromagnetic material definitely affects the magnitude and behavior of the spin signals. The use of highly polarized ferromagnets such as Heusler compounds would be important for improving the spin polarization and the magnitude of spin signals through Si channels.« less

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

NASA Astrophysics Data System (ADS)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

NASA Technical Reports Server (NTRS)

Choi, Sang; King, Glen; Park, Yeonjoon

2009-01-01

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

A MEMS SOI-based piezoresistive fluid flow sensor

NASA Astrophysics Data System (ADS)

Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

2018-02-01

In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

Effect of strain on the electron effective mobility in biaxially strained silicon inversion layers: An experimental and theoretical analysis via atomic force microscopy measurements and Kubo-Greenwood mobility calculations

NASA Astrophysics Data System (ADS)

Bonno, Olivier; Barraud, Sylvain; Mariolle, Denis; Andrieu, François

2008-03-01

Recently, in order to explain the long-channel electron effective mobility at a high sheet carrier density in strained silicon channel transistors, it has been suggested by [M. V. Fischetti, F. Gamiz, and W. Hansch, J. Appl. Phys. 92, 7230 (2002)] that biaxial tensile strain should smooth the Si/SiO2 interface. To address this topic, the roughness properties of biaxial strained silicon-on-insulator (s-SOI) films are investigated by means of atomic force microscopy. Through in-depth statistical analysis of the digitalized surface profiles, the roughness parameters are extracted for unstrained and strained SOI films, with 0.8% biaxial tensile strain. Especially, it is found that strain significantly reduces the roughness amplitude. Then, mobility calculations in SOI and s-SOI inversion layers are performed in the framework of the Kubo-Greenwood formalism. The model accounts for the main scattering mechanisms that are dominant in the high electron density range, namely phonon and surface roughness. Special attention has been paid to the modeling of the latter by accounting for all the contributions of the potential which arise from the deformed rough interface, and by using a multisubband wavelength-dependent screening model. This model is then applied to study the influence of the surface morphology on the mobility in s-SOI inversion layers. In this context, the mobility gain between s-SOI and unstrained SOI layers is found to agree significantly better with experimental data if the strain-induced decrease of the roughness amplitude is taken into account.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

NASA Astrophysics Data System (ADS)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

Optical interconnects based on VCSELs and low-loss silicon photonics

NASA Astrophysics Data System (ADS)

Aalto, Timo; Harjanne, Mikko; Karppinen, Mikko; Cherchi, Matteo; Sitomaniemi, Aila; Ollila, Jyrki; Malacarne, Antonio; Neumeyr, Christian

2018-02-01

Silicon photonics with micron-scale Si waveguides offers most of the benefits of submicron SOI technology while avoiding most of its limitations. In particular, thick silicon-on-insulator (SOI) waveguides offer 0.1 dB/cm propagation loss, polarization independency, broadband single-mode (SM) operation from 1.2 to >4 µm wavelength and ability to transmit high optical powers (>1 W). Here we describe the feasibility of Thick-SOI technology for advanced optical interconnects. With 12 μm SOI waveguides we demonstrate efficient coupling between standard single-mode fibers, vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs), as well as wavelength multiplexing in small footprint. Discrete VCSELs and PDs already support 28 Gb/s on-off keying (OOK), which shows a path towards 50-100 Gb/s bandwidth per wavelength by using more advanced modulation formats like PAM4. Directly modulated VCSELs enable very power-efficient optical interconnects for up to 40 km distance. Furthermore, with 3 μm SOI waveguides we demonstrate extremely dense and low-loss integration of numerous optical functions, such as multiplexers, filters, switches and delay lines. Also polarization independent and athermal operation is demonstrated. The latter is achieved by using short polymer waveguides to compensate for the thermo-optic effect in silicon. New concepts for isolator integration and polarization rotation are also explained.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optofluidic metasurface for lateral flow-through detection of breast cancer biomarker.

PubMed

Wang, Yifei; Ali, Md Azahar; Chow, Edmond K C; Dong, Liang; Lu, Meng

2018-06-01

The rapid growth of point-of-care tests demands for biosensors with high sensitivity and small size. This paper demonstrates an optofluidic metasurface that combines silicon-on-insulator (SOI) nanophotonics and nanofluidics to realize a high-performance, lateral flow-through biosensor. The metasurface is made of a periodic array of silicon nanoposts on an SOI substrate, and functionalized with specific receptor molecules. Bonding of a polydimethylsiloxane slab directly onto the surface results in an ultracompact biosensor, where analyte solutions are restricted to flow only in the space between the nanoposts. No flow exists above the nanoposts. This sensor design overcomes the issue with diffusion-limited detection of many other biosensors. The lateral flow-through feature, in conjunction with high-Q resonance modes associated with optical bound states of the metasurface, offers an improved sensitivity to subtle molecule-bonding induced changes in refractive index. The device exhibits a resonance mode around 1550 nm wavelength and provides an index sensitivity of 720 nm/RIU. Biosensing is conducted to detect the epidermal growth factor receptor 2 (ErbB2), a protein biomarker for early-stage breast cancer screening, by monitoring resonance wavelength shifts in response to specific analyte-ligand binding events at the metasurface. The limit of detection of the device is 0.7 ng mL -1 for ErbB2. Copyright © 2018 Elsevier B.V. All rights reserved.

Electrical Control of Structural and Physical Properties via Strong Spin-Orbit Interactions in Sr2IrO4

NASA Astrophysics Data System (ADS)

Cao, G.; Terzic, J.; Zhao, H. D.; Zheng, H.; De Long, L. E.; Riseborough, Peter S.

2018-01-01

Electrical control of structural and physical properties is a long-sought, but elusive goal of contemporary science and technology. We demonstrate that a combination of strong spin-orbit interactions (SOI) and a canted antiferromagnetic Mott state is sufficient to attain that goal. The antiferromagnetic insulator Sr2IrO4 provides a model system in which strong SOI lock canted Ir magnetic moments to IrO6 octahedra, causing them to rigidly rotate together. A novel coupling between an applied electrical current and the canting angle reduces the Néel temperature and drives a large, nonlinear lattice expansion that closely tracks the magnetization, increases the electron mobility, and precipitates a unique resistive switching effect. Our observations open new avenues for understanding fundamental physics driven by strong SOI in condensed matter, and provide a new paradigm for functional materials and devices.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

NASA Astrophysics Data System (ADS)

Ye, Fan; Xiaorong, Luo; Kun, Zhou; Yuanhang, Fan; Yongheng, Jiang; Qi, Wang; Pei, Wang; Yinchun, Luo; Bo, Zhang

2014-03-01

A low specific on-resistance (Ron,sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron,sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron,sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron,sp by 80% at the same BV.

Optical properties of new wide heterogeneous waveguides with thermo optical shifters.

PubMed

De Leonardis, Francesco; Tsarev, Andrei V; Passaro, Vittorio M

2008-12-22

We present analysis and simulation of novel silicon-on-insulator (SOI) heterogeneous waveguides with thermo-optic phase shifters. New structure design contains a p-n junction on both sides of SOI ridge waveguide with 220 nm x 35 microm silicon core. Strongly mode-dependent optical losses (by additional free charge absorption) provide quasi-singe-mode behavior of wide waveguide with mode size approximately 10 microm. Local heater produces an efficient phase shifting by small temperature increase (DeltaT approximately 2K), switching power (< 40 mW) and switching time (< 10 micros). Mode optical losses are significantly decreased at high heating (DeltaT approximately 120 K).

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

NASA Astrophysics Data System (ADS)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Research on SOI-based micro-resonator devices

NASA Astrophysics Data System (ADS)

Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

2010-10-01

SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of < 400 ps and crosstalk < -23 dB, and > 10 Gbit/s high speed microring modulators.

Dual Interlocked Logic for Single-Event Transient Mitigation

DTIC Science & Technology

2017-03-01

SPICE simulation and fault-injection analysis. Exemplar SPICE simulations have been performed in a 32nm partially- depleted silicon-on-insulator...in this work. The model has been validated at the 32nm SOI technology node with extensive heavy-ion data [7]. For the SPICE simulations, three

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Stopping electric field extension in a modified nanostructure based on SOI technology - A comprehensive numerical study

NASA Astrophysics Data System (ADS)

Anvarifard, Mohammad K.; Orouji, Ali A.

2017-11-01

This article has related a particular knowledge in order to reduce short channel effects (SCEs) in nano-devices based on silicon-on-insulator (SOI) MOSFETs. The device under study has been designed in 22 nm node technology with embedding Si3N4 extra oxide as a stopping layer of electric field and a useful heatsink for transferring generated heat. Two important subjects (DC characteristics and RF characteristics) have been investigated, simultaneously. Stopping electric field extension and enhancement of channel thermal conduction are introduced as an entrance gateway for this work so that improve the electrical characteristics, eventually. The inserted extra oxide made by the Si3N4 material has a vital impact on the modification of the electrical and thermal features in the proposed device. An immense comparison between the proposed SOI and conventional SOI showed that the proposed structure has higher electrical and thermal proficiency than the conventional structure in terms of main parameters such as short channel effects (SCEs), leakage current, floating body effect (FBE), self-heating effect (SHE), voltage gain, ratio of On-current to Off- current, transconductance, output conductance, minimum noise figure and power gain.

Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

NASA Astrophysics Data System (ADS)

Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Zhou, Hang; Liu, Mohan; Wei, Ying; Su, Dandan; Ma, Teng; Lu, Wu; Yu, Xuefeng; Guo, Qi; He, Chengfa

2017-07-01

Effect of total ionizing dose (TID) on single-event upset (SEU) hardness of 130 nm partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) is investigated in this paper. The measurable synergistic effect of TID on SEU sensitivity of 130-nm PD SOI SRAM was observed in our experiment, even though that is far less than micrometer and submicrometer devices. Moreover, SEU cross section after TID irradiation has no dependence on the data pattern that was applied during TID exposure: SEU cross sections are characterized by TID data pattern and its complement data pattern are decreased consistently rather than a preferred state and a nonpreferred state as micrometer and sub-micrometer SRAMs. The memory cell test structure allowing direct measurement of static noise margin (SNM) under standby operation was designed using identical memory cell layout of SRAM. Direct measurement of the memory cell SNM shows that both data sides' SNM is decreased by TID, indicating that SEU cross section of 130-nm PD SOI SRAM will be increased by TID. And, the decreased SNM is caused by threshold shift in memory cell transistors induced by “radiation-induced narrow channel effect”.

An SEU resistant 256K SOI SRAM

NASA Astrophysics Data System (ADS)

Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

1992-12-01

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

NASA Astrophysics Data System (ADS)

Katz, Oded; Malka, Dror

2017-07-01

In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

NASA Astrophysics Data System (ADS)

Fan, Ji; Zhang, Wen Ting; Liu, Jin Quan; Wu, Wen Jie; Zhu, Tao; Tu, Liang Cheng

2015-04-01

We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactive-ion etching, a HAR (˜25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

A High Temperature Silicon Carbide mosfet Power Module With Integrated Silicon-On-Insulator-Based Gate Drive

DOE PAGES

Wang, Zhiqiang; Shi, Xiaojie; Tolbert, Leon M.; ...

2014-04-30

Here we present a board-level integrated silicon carbide (SiC) MOSFET power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200°C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate drivermore » and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225°C.« less

An optical microswitch chip integrated with silicon waveguides and touch-down electrostatic micromirrors

NASA Astrophysics Data System (ADS)

Jin, Young-Hyun; Seo, Kyoung-Sun; Cho, Young-Ho; Lee, Sang-Shin; Song, Ki-Chang; Bu, Jong-Uk

2004-12-01

We present an silicon-on-insulator (SOI) optical microswitch, composed of silicon waveguides and electrostatically actuated gold-coated silicon micromirrors integrated with laser diode (LD) receivers and photo diode (PD) transmitters. For a low switching voltage, we modify the conventional curved electrode microactuator into a new microactuator with touch-down beams. We fabricate the waveguides and the actuated micromirror using the inductively coupled plasma (ICP) etching process of SOI wafers. The fabricated microswitch operates at the switching voltage of 31.7 ± 4 V with the resonant frequency of 6.89 kHz. Compared to the conventional microactuator, the touch-down beam microactuator achieves 77.4% reduction of the switching voltage. We observe the single mode wave propagation through the silicon waveguide with the measured micromirror loss of 4.18 ± 0.25 dB. We discuss a feasible method to achieve the switching voltage lower than 10 V by reducing the residual stress in the insulation layers of touch-down beams to the level of 30 MPa. We also analyze the major source of micromirror loss, thereby presenting design guidelines for low-loss micromirror switches.

Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

PubMed

Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

2016-02-10

We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

Bio-Inspired Micromechanical Directional Acoustic Sensor

NASA Astrophysics Data System (ADS)

Swan, William; Alves, Fabio; Karunasiri, Gamani

Conventional directional sound sensors employ an array of spatially separated microphones and the direction is determined using arrival times and amplitudes. In nature, insects such as the Ormia ochracea fly can determine the direction of sound using a hearing organ much smaller than the wavelength of sound it detects. The fly's eardrums are mechanically coupled, only separated by about 1 mm, and have remarkable directional sensitivity. A micromechanical sensor based on the fly's hearing system was designed and fabricated on a silicon on insulator (SOI) substrate using MEMS technology. The sensor consists of two 1 mm2 wings connected using a bridge and to the substrate using two torsional legs. The dimensions of the sensor and material stiffness determine the frequency response of the sensor. The vibration of the wings in response to incident sound at the bending resonance was measured using a laser vibrometer and found to be about 1 μm/Pa. The electronic response of the sensor to sound was measured using integrated comb finger capacitors and found to be about 25 V/Pa. The fabricated sensors showed good directional sensitivity. In this talk, the design, fabrication and characteristics of the directional sound sensor will be described. Supported by ONR and TDSI.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Broadband non-polarizing beam splitter based on guided mode resonance effect

NASA Astrophysics Data System (ADS)

Ma, Jian-Yong; Xu, Cheng; Qiang, Ying-Huai; Zhu, Ya-Bo

2011-10-01

A broadband non-polarizing beam splitter (NPBS) operating in the telecommunication C+L band is designed by using the guided mode resonance effect of periodic silicon-on-insulator (SOI) elements. It is shown that this double layer SOI structure can provide ~50/50 beam ratio with the maximum divergences between reflection and transmission being less than 8% over the spectrum of 1.4 μm~1.7 μm and 1% in the telecommunication band for both TE and TM polarizations. The physical basis of this broadband non-polarizing property is on the simultaneous excitation of the TE and TM strong modulation waveguide modes near the designed spectrum band. Meanwhile, the electric field distributions for both TE and TM polarizations verify the resonant origin of spectrum in the periodic SOI structure. Furthermore, it is demonstrated with our calculations that the beam splitter proposed here is tolerant to the deviations of incident angle and structure parameters, which make it very easy to be fabricated with current IC technology.

Defect Characterization in SiGe/SOI Epitaxial Semiconductors by Positron Annihilation

PubMed Central

2010-01-01

The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors has been demonstrated in thin multilayer structures of SiGe (50 nm) grown on UTB (ultra-thin body) SOI (silicon-on-insulator). A slow positron beam was used to probe the defect profile. The SiO2/Si interface in the UTB-SOI was well characterized, and a good estimation of its depth has been obtained. The chemical analysis indicates that the interface does not contain defects, but only strongly localized charged centers. In order to promote the relaxation, the samples have been submitted to a post-growth annealing treatment in vacuum. After this treatment, it was possible to observe the modifications of the defect structure of the relaxed film. Chemical analysis of the SiGe layers suggests a prevalent trapping site surrounded by germanium atoms, presumably Si vacancies associated with misfit dislocations and threading dislocations in the SiGe films. PMID:21170391

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Exceptional cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si heterostructures

NASA Astrophysics Data System (ADS)

Chen, Da; Wang, Dadi; Chang, Yongwei; Li, Ya; Ding, Rui; Li, Jiurong; Chen, Xiao; Wang, Gang; Guo, Qinglei

2018-01-01

The cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si structures after thermal annealing was investigated. The crack formation position is found to closely correlate with the thickness of the buried Si0.70Ge0.30 layer. For H-implanted Si containing a buried 3-nm-thick B-doped Si0.70Ge0.30 layer, localized continuous cracking occurs at the interfaces on both sides of the Si0.70Ge0.30 interlayer. Once the thickness of the buried Si0.70Ge0.30 layer increases to 15 and 70 nm, however, a continuous sharp crack is individually observed along the interface between the Si substrate and the B-doped Si0.70Ge0.30 interlayer. We attribute this exceptional cracking behavior to the existence of shear stress on both sides of the buried Si0.70Ge0.30 layer and the subsequent trapping of hydrogen, which leads to a crack in a well-controlled manner. This work may pave the way for high-quality Si or SiGe membrane transfer in a feasible manner, thus expediting its potential applications to ultrathin silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) production.

Full control of the spin-wave damping in a magnetic insulator using spin orbit torque

NASA Astrophysics Data System (ADS)

Klein, Olivier

2015-03-01

The spin-orbit interaction (SOI) has been an interesting and useful addition in the field of spintronics by opening it to non-metallic magnet. It capitalizes on adjoining a strong SOI normal metal next to a thin magnetic layer. The SOI converts a charge current, Jc, into a spin current, Js, with an efficiency parametrized by ΘSH, the spin Hall angle. An important benefit of the SOI is that Jc and Js are linked through a cross-product, allowing a charge current flowing in-plane to produce a spin current flowing out-of-plane. Hence it enables the transfer of spin angular momentum to non-metallic materials and in particular to insulating oxides, which offer improved performance compared to their metallic counterparts. Among all oxides, Yttrium Iron Garnet (YIG) holds a special place for having the lowest known spin-wave (SW) damping factor. Until recently the transmission of spin current through the YIG|Pt interface has been subject to debate. While numerous experiments have reported that Js produced by the excitation of ferromagnetic resonance (FMR) in YIG can cross efficiently the YIG|Pt interface and be converted into Jc in Pt through the inverse spin Hall effect (ISHE), most attempts to observe the reciprocal effect, where Js produced in Pt by the direct spin Hall effect (SHE) is transferred to YIG, resulting in damping compensation, have failed. This has been raising fundamental questions about the reciprocity of the spin transparency of the interface between a metal and a magnetic insulator. In this talk it will be demonstrated that the threshold current for damping compensation can be reached in a 5 μm diameter YIG(20nm)|Pt(7nm) disk. Reduction of both the thickness and lateral size of a YIG-structure were key to reach the microwave generation threshold current, Jc*. The experimental evidence rests upon the measurement of the ferromagnetic resonance linewidth as a function of Idc using a magnetic resonance force microscope (MRFM). It is shwon that the magnetic losses of spin-wave modes existing in the magnetic insulator can be reduced or enhanced by at least a factor of five depending on the polarity and intensity of the in-plane dc current, Idc. Complete compensation of the damping of the fundamental mode by spin-orbit torque is reached for a current density of ~ 3 .1011 A.m-2, in agreement with theoretical predictions. At this critical threshold the MRFM detects a small change of static magnetization, a behavior consistent with the onset of an auto-oscillation regime. This result opens up a new area of research on the electronic control of the damping of YIG-nanostructures.

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Design and implementation of a low-power SOI CMOS receiver

NASA Astrophysics Data System (ADS)

Zencir, Ertan

There is a strong demand for wireless communications in civilian and military applications, and space explorations. This work attempts to implement a low-power, high-performance fully-integrated receiver for deep space communications using Silicon on Insulator (SOI) CMOS technology. Design and implementation of a UHF low-IF receiver front-end in a 0.35-mum SOI CMOS technology are presented. Problems and challenges in implementing a highly integrated receiver at UHF are identified. Low-IF architecture, suitable for low-power design, has been adopted to mitigate the noise at the baseband. Design issues of the receiver building blocks including single-ended and differential LNA's, passive and active mixers, and variable gain/bandwidth complex filters are discussed. The receiver is designed to have a variable conversion gain of more than 100 dB with a 70 dB image rejection and a power dissipation of 45 mW from a 2.5-V supply. Design and measured performance of the LNA's, and the mixer are presented. Measurement results of RF front-end blocks including a single-ended LNA, a differential LNA, and a double-balanced mixer demonstrate the low power realizability of RF front-end circuits in SOI CMOS technology. We also report on the design and simulation of the image-rejecting complex IF filter and the full receiver circuit. Gain, noise, and linearity performance of the receiver components prove the viability of fully integrated low-power receivers in SOI CMOS technology.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Noise performance of 0.35-(mu)m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation

NASA Technical Reports Server (NTRS)

Binkley, D. M.; Hopper, C. E.; Cressler, J. D.; Mojarradi, M. M.; Blalock, B. J.

2004-01-01

This paper presents measured noise for 0.35(mu)m, silicon-on-insulator devices and a micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation. Flicker noise voltage, important for gyros having low frequency output, increases less than 32% after irradiation.

Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

NASA Technical Reports Server (NTRS)

Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

2006-01-01

The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

NASA Astrophysics Data System (ADS)

Qiao, Ming; Wang, Yuru; Li, Yanfei; Zhang, Bo; Li, Zhaoji

2014-11-01

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80 μm, the NBL PSOI LDMOS obtains a high BV of 1243 V which is improved by around 105 V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333 K at a power (P) of 1 mW/μm which is reduced by around 61 K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

Two-way reflector based on two-dimensional sub-wavelength high-index contrast grating on SOI

NASA Astrophysics Data System (ADS)

Kaur, Harpinder; Kumar, Mukesh

2016-05-01

A two-dimensional (2D) high-index contrast grating (HCG) is proposed as a two-way reflector on Silicon-on-insulator (SOI). The proposed reflector provides high reflectivity over two (practically important) sets of angles of incidence- normal (θ = 0 °) and oblique/grazing (θ = 80 ° - 85 ° / 90 °). Analytical model of 2D HCG is presented using improved Fourier modal method. The vertical incidence is useful for application in VCSEL while oblique/grazing incidence can be utilized in high confinement (HCG mirrors based) hollow waveguides and Bragg reflectors. The proposed two-way reflector also exhibits a large reflection bandwidth (around telecom wavelength) which is an advantage for broadband photonic devices.

Silicon-based Coulomb blockade thermometer with Schottky barriers

NASA Astrophysics Data System (ADS)

Tuboltsev, V.; Savin, A.; Rogozin, V. D.; Räisänen, J.

2014-04-01

A hybrid Coulomb blockade thermometer (CBT) in form of an array of intermittent aluminum and silicon islands connected in series via tunnel junctions was fabricated on a thin silicon-on-insulator (SOI) film. Tunnel barriers in the micrometer size junctions were formed by metal-semiconductor Schottky contacts between aluminium electrodes and heavily doped silicon. Differential conductance through the array vs. bias voltage was found to exhibit characteristic features of competing thermal and charging effects enabling absolute temperature measurements over the range of ˜65 to ˜500 mK. The CBT performance implying the primary nature of the thermometer demonstrated for rather trivial architecture attempted in this work paves a route for introduction of Coulomb blockade thermometry into well-developed contemporary SOI technology.

Low-Power SOI CMOS Transceiver

NASA Technical Reports Server (NTRS)

Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

2003-01-01

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Growth of cubic silicon carbide on oxide using polysilicon as a seed layer for micro-electro-mechanical machine applications

NASA Astrophysics Data System (ADS)

Frewin, C. L.; Locke, C.; Wang, J.; Spagnol, P.; Saddow, S. E.

2009-08-01

The growth of highly oriented 3C-SiC directly on an oxide release layer, composed of a 20-nm-thick poly-Si seed layer and a 550-nm-thick thermally deposited oxide on a (1 1 1)Si substrate, was investigated as an alternative to using silicon-on-insulator (SOI) substrates for freestanding SiC films for MEMS applications. The resulting SiC film was characterized by X-ray diffraction (XRD) with the X-ray rocking curve of the (1 1 1) diffraction peak displaying a FWHM of 0.115° (414″), which was better than that for 3C-SiC films grown directly on (1 1 1)Si during the same deposition process. However, the XRD peak amplitude for the 3C-SiC film on the poly-Si seed layer was much less than for the (1 1 1)Si control substrate, due to slight in-plane misorientations in the film. Surprisingly, the film was solely composed of (1 1 1) 3C-SiC grains and possessed no 3C-SiC grains oriented along the <3 1 1> and <1 1 0> directions which were the original directions of the poly-Si seed layer. With this new process, MEMS structures such as cantilevers and membranes can be easily released leaving behind high-quality 3C-SiC structures.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-06-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Performance characteristics of nanocrystalline diamond vacuum field emission transistor array

NASA Astrophysics Data System (ADS)

Hsu, S. H.; Kang, W. P.; Davidson, J. L.; Huang, J. H.; Kerns, D. V.

2012-05-01

Nitrogen-incorporated nanocrystalline diamond (ND) vacuum field emission transistor (VFET) with self-aligned gate is fabricated by mold transfer microfabrication technique in conjunction with chemical vapor deposition (CVD) of nanocrystalline diamond on emitter cavity patterned on silicon-on-insulator (SOI) substrate. The fabricated ND-VFET demonstrates gate-controlled emission current with good signal amplification characteristics. The dc characteristics of the ND-VFET show well-defined cutoff, linear, and saturation regions with low gate turn-on voltage, high anode current, negligible gate intercepted current, and large dc voltage gain. The ac performance of the ND-VFET is measured, and the experimental data are analyzed using a modified small signal circuit model. The experimental results obtained for the ac voltage gain are found to agree with the theoretical model. A higher ac voltage gain is attainable by using a better test setup to eliminate the associated parasitic capacitances. The paper reveals the amplifier characteristics of the ND-VFET for potential applications in vacuum microelectronics.

Integrated programmable photonic filter on the silicon-on-insulator platform.

PubMed

Liao, Shasha; Ding, Yunhong; Peucheret, Christophe; Yang, Ting; Dong, Jianji; Zhang, Xinliang

2014-12-29

We propose and demonstrate a silicon-on-insulator (SOI) on-chip programmable filter based on a four-tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heaters. We further demonstrate the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability for integrating with electronics.

Low-loss silicon-on-insulator shallow-ridge TE and TM waveguides formed using thermal oxidation.

PubMed

Pafchek, R; Tummidi, R; Li, J; Webster, M A; Chen, E; Koch, T L

2009-02-10

A thermal oxidation fabrication technique is employed to form low-loss high-index-contrast silicon shallow-ridge waveguides in silicon-on-insulator (SOI) with maximally tight vertical confinement. Drop-port responses from weakly coupled ring resonators demonstrate propagation losses below 0.36 dB/cm for TE modes. This technique is also combined with "magic width" designs mitigating severe lateral radiation leakage for TM modes to achieve propagation loss values of 0.94 dB/cm. We discuss the fabrication process utilized to form these low-loss waveguides and implications for sensor devices in particular.

Silicon-based optoelectronics: Monolithic integration for WDM

NASA Astrophysics Data System (ADS)

Pearson, Matthew Richard T.

2000-10-01

This thesis details the development of enabling technologies required for inexpensive, monolithic integration of Si-based wavelength division multiplexing (WDM) components and photodetectors. The work involves the design and fabrication of arrayed waveguide grating demultiplexers in silicon-on-insulator (SOI), the development of advanced SiGe photodetectors capable of photodetection at 1.55 mum wavelengths, and the development of a low cost fabrication technique that enables the high volume production of Si-based photonic components. Arrayed waveguide grating (AWG) demultiplexers were designed and fabricated in SOI. The fabrication of AWGs in SOI has been reported in the literature, however there are a number of design issues specific to the SOI material system that can have a large effect on device performance and design, and have not been theoretically examined in earlier work. The SOI AWGs presented in this thesis are the smallest devices of this type reported, and they exhibit performance acceptable for commercial applications. The SiGe photodetectors reported in the literature exhibit extremely low responsivities at wavelengths near 1.55 mum. We present the first use of three dimensional growth modes to enhance the photoresponse of SiGe at 1.55 mum wavelengths. Metal semiconductor-metal (MSM) photodetectors were fabricated using this undulating quantum well structure, and demonstrate the highest responsivities yet reported for a SiGe-based photodetector at 1.55 mum. These detectors were monolithically integrated with low-loss SOI waveguides, enabling integration with nearly any Si-based passive WDM component. The pursuit of inexpensive Si-based photonic components also requires the development of new manufacturing techniques that are more suitable for high volume production. This thesis presents the development of a low cost fabrication technique based on the local oxidation of silicon (LOCOS), a standard processing technique used for Si integrated circuits. This process is developed for both SiGe and SOI waveguides, but is shown to be commercially suitable only for SOI waveguide devices. The technique allows nearly any Si microelectronics fabrication facility to begin manufacturing optical components with minimal change in processing equipment or techniques. These enabling technologies provide the critical elements for inexpensive, monolithic integration in a Si-based system.

Deep Trek High Temperature Electronics Project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bruce Ohme

2007-07-31

This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop high-temperature electronics. Objects of this development included Silicon-on-Insulator (SOI) wafer process development for high temperature, supporting design tools and libraries, and high temperature integrated circuit component development including FPGA, EEPROM, high-resolution A-to-D converter, and a precision amplifier.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Electronic structure of Rh and Ru doped Sr2IrO4

NASA Astrophysics Data System (ADS)

Chikara, Shalinee; Fabbris, Gilberto; Terzic, Jasminka; Qi, Tongfei; Butrouna, Kamal; Veiga, Larissa; Souza Neto, Narcizo; Cao, Gang; Haskel, Daniel

2014-03-01

Sr2IrO4 is a spin-orbit interaction(SOI) assisted insulator. It has been proposed that the weaker SOI in the 4 d -substituted Sr2Ir1-x(Ru, Rh)xO4 closes the insulating gap, rendering it a paramagnetic metal. Rh(4d5) is isoelectronic to Ir(5d5) whereas Ru(4d4) has one less electron in the 4 d -band. The AFM-I/PM-M transition takes place at lower x for Ru than Rh, presumably due to the effect of hole doping. X-ray absorption near edge structure (XANES) and x-ray magnetic circular dichroism (XMCD) measurements at the Ir L2 , 3 edges show that < L . S > is non-zero and independent of x. This is indicative of a strong local 5 d spin orbit interaction that is rather insensitive to the 4 d doping. In contrast, measurements at the L2 , 3 edges of Ru and Rh show < L . S > ~ 0 for all x. The results point to the importance of local 4 d / 5 d - 2 p hybridization as opposed to 4 d - 5 d band formation in the Rh and Ru doped Sr2IrO4.

Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

NASA Astrophysics Data System (ADS)

Hiti, B.; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

2017-10-01

Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1× 1016 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5× 1014 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The results were backed by a numerical simulation of charge collection in an equivalent detector layout.

Single crystal silicon filaments fabricated in SOI: A potential IR source for a microfabricated photometric CO2 sensor

NASA Technical Reports Server (NTRS)

Tu, Juliana; Smith, Rosemary L.

1995-01-01

The objective of this project was to design, fabricate, and test single crystal silicon filaments as potential black body IR sources for a spectrophotometric CO2 sensing microsystem. The design and fabrication of the silicon-on-insulator (SOI) filaments are summarized and figures showing the composite layout of the filament die (which contains four filaments of different lengths -- 500 microns, 1 mm, 1.5 mm and 2 mm -- and equal widths of 15 microns) are presented. The composite includes four mask layers: (1) silicon - defines the filament dimensions and contact pads; (2) release pit - defines the oxide removed from under the filament and hence, the length of the released filament; (3) Pyrex pit - defines the pit etched in the Pyrex cap (not used); and (4) metal - defines a metal pattern on the contact pads or used as a contact hole etch. I/V characteristics testing of the fabricated SOI filaments is described along with the nitride-coating procedures carried out to prevent oxidation and resistance instability.

Transversely coupled Fabry-Perot resonators with Bragg grating reflectors.

PubMed

Saber, Md Ghulam; Wang, Yun; El-Fiky, Eslam; Patel, David; Shahriar, Kh Arif; Alam, Md Samiul; Jacques, Maxime; Xing, Zhenping; Xu, Luhua; Abadía, Nicolás; Plant, David V

2018-01-01

We design and demonstrate Fabry-Perot resonators with transverse coupling using Bragg gratings as reflectors on the silicon-on-insulator (SOI) platform. The effects of tailoring the cavity length and the coupling coefficient of the directional coupler on the spectral characteristics of the device are studied. The fabricated resonators achieved an extinction ratio (ER) of 37.28 dB and a Q-factor of 3356 with an effective cavity length of 110 μm, and an ER of 8.69 dB and a Q-factor of 23642 with a 943 μm effective cavity length. The resonator structure presented here has the highest reported ER on SOI and provides additional degrees of freedom compared to an all-pass ring resonator to tune the spectral characteristics.

Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

NASA Technical Reports Server (NTRS)

Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

2013-01-01

This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

Sensitivity Enhancement in Si Nanophotonic Waveguides Used for Refractive Index Sensing

PubMed Central

Shi, Yaocheng; Ma, Ke; Dai, Daoxin

2016-01-01

A comparative study is given for the sensitivity of several typical Si nanophotonic waveguides, including SOI (silicon-on-insulator) nanowires, nanoslot waveguides, suspended Si nanowires, and nanofibers. The cases for gas sensing (ncl ~ 1.0) and liquid sensing (ncl ~ 1.33) are considered. When using SOI nanowires (with a SiO2 buffer layer), the sensitivity for liquid sensing (S ~ 0.55) is higher than that for gas sensing (S ~ 0.35) due to lower asymmetry in the vertical direction. By using SOI nanoslot waveguides, suspended Si nanowires, and Si nanofibers, one could achieve a higher sensitivity compared to sensing with a free-space beam (S = 1.0). The sensitivity for gas sensing is higher than that for liquid sensing due to the higher index-contrast. The waveguide sensitivity of an optimized suspended Si nanowire for gas sensing is as high as 1.5, which is much higher than that of a SOI nanoslot waveguide. Furthermore, the optimal design has very large tolerance to the core width variation due to the fabrication error (∆w ~ ±50 nm). In contrast, a Si nanofiber could also give a very high sensitivity (e.g., ~1.43) while the fabrication tolerance is very small (i.e., ∆w < ±5 nm). The comparative study shows that suspended Si nanowire is a good choice to achieve ultra-high waveguide sensitivity. PMID:26950132

Sensitivity Enhancement in Si Nanophotonic Waveguides Used for Refractive Index Sensing.

PubMed

Shi, Yaocheng; Ma, Ke; Dai, Daoxin

2016-03-03

A comparative study is given for the sensitivity of several typical Si nanophotonic waveguides, including SOI (silicon-on-insulator) nanowires, nanoslot waveguides, suspended Si nanowires, and nanofibers. The cases for gas sensing (ncl ~ 1.0) and liquid sensing (ncl ~ 1.33) are considered. When using SOI nanowires (with a SiO₂ buffer layer), the sensitivity for liquid sensing (S ~ 0.55) is higher than that for gas sensing (S ~ 0.35) due to lower asymmetry in the vertical direction. By using SOI nanoslot waveguides, suspended Si nanowires, and Si nanofibers, one could achieve a higher sensitivity compared to sensing with a free-space beam (S = 1.0). The sensitivity for gas sensing is higher than that for liquid sensing due to the higher index-contrast. The waveguide sensitivity of an optimized suspended Si nanowire for gas sensing is as high as 1.5, which is much higher than that of a SOI nanoslot waveguide. Furthermore, the optimal design has very large tolerance to the core width variation due to the fabrication error (∆w ~ ±50 nm). In contrast, a Si nanofiber could also give a very high sensitivity (e.g., ~1.43) while the fabrication tolerance is very small (i.e., ∆w < ±5 nm). The comparative study shows that suspended Si nanowire is a good choice to achieve ultra-high waveguide sensitivity.

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

PubMed

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-12-13

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

Exploration of MEMS G-Switches at 100-10,000 G-Levels with Redundancy

DTIC Science & Technology

2014-04-01

Muntz, A.D. Ketsdever, “Kinetic Modeling of Temperature -Driven Flows in Short Microchannels,” International Journal of Thermal Sciences, Vol. 45, No...switches silicon DRIE Unclassified Unclassified Unclassified UU 59 Suhithi Peiris 703-767-4732 CONVERSION...designed. The devices were fabricated on low resistivity (ɘ.01 Ω-cm) silicon on insulator wafers (SOI) using standard micromachining techniques. Fixed

Photonic Hilbert transformers based on laterally apodized integrated waveguide Bragg gratings on a SOI wafer.

PubMed

Bazargani, Hamed Pishvai; Burla, Maurizio; Chrostowski, Lukas; Azaña, José

2016-11-01

We experimentally demonstrate high-performance integer and fractional-order photonic Hilbert transformers based on laterally apodized Bragg gratings in a silicon-on-insulator technology platform. The sub-millimeter-long gratings have been fabricated using single-etch electron beam lithography, and the resulting HT devices offer operation bandwidths approaching the THz range, with time-bandwidth products between 10 and 20.

Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

DTIC Science & Technology

2015-09-17

applications, a tunable pressure sensor and a steerable micromirror . A differential pressure across the mem- brane causes deflection, up or down, which can...0.55µm/psi. A steerable micromirror was realized by selectively heat- ing a single quadrant of a buckled membrane, localized heating results in membrane...124 6.2.1 Micromirror Actuator Optimization . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Summary

Ultrasensitive Silicon Photonic-Crystal Nanobeam Electro-Optical Modulator (Preprint)

DTIC Science & Technology

2013-10-01

and simulation results are presented for an ultralow switching energy, resonator based silicon-on-insulator (SOI) electro-optical modulator. The...joshua.hendrickson@wpafb.af.mil Abstract: Design and simulation results are presented for an ultralow switching energy, resonator based silicon-on...S. Fegadolli, J. E. B. Oliveira, V. R. Almeida, and A. Scherer, “Compact and low power consumption tunable photonic crystal nanobeam cavity,” 21

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

NASA Astrophysics Data System (ADS)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

Enhancement of coupling ratios in SOI based asymmetrical optical directional couplers

NASA Astrophysics Data System (ADS)

Pendam, Nagaraju; Vardhani, Chunduru Parvatha

2017-11-01

A novel design of slab structured asymmetrical optical directional coupler with S-bend waveguides on silicon-on-insulator (SOI) platform has been designed by using R-Soft CAD tool. Beam propagation method (BPM) is used for light propagation analysis. The simulation results of asymmetrical optical directional couplers are reported. We find that the asymmetrical directional coupler has lower coupling ratios and higher extinction ratios with waveguide parameters such as width, wavelength, waveguide spacing, and coupling length. Simulation results designate that the coupling efficiency for transverse electric (TE) and transverse magnetic (TM) modes can reach about more than 95% and extinction ratio about 6 dB when the coupling length is 6 mm for both the polarization modes and insertion loss is 17 dB with same coupling length 6 mm at central wavelength 1550 nm.

Evaluation of Silicon-on-Insulator HTOP-01 Operational Amplifier for Wide Temperature Operation

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Electronics capable of operation under extreme temperatures are required in many of NASA space exploration missions. Aerospace and military applications, as well as some terrestrial industries constitute environments where electronic systems are anticipated to be exposed to extreme temperatures and wide-range thermal swings. Electronics that are able to withstand and operate efficiently in such harsh environments would simplify, if not eliminate, traditional thermal control elements and their associated structures for proper ambient operation. As a result, overall system mass would be reduced, design would be simplified, and reliability would be improved. Electronic parts that are built utilizing silicon-on-insulator (SOI) technology are known to offer better radiation-tolerance compared to their conventional silicon counterparts, provide faster switching, and consume less power. They also exhibit reduced leakage current and, thus, they are often tailored for high temperature operation. These attributes make SOI-based devices suitable for use in harsh environments where extreme temperatures and wide thermal swings are anticipated. A new operational amplifier, based on silicon-on-insulator technology and geared for high temperature well-logging applications, was recently introduced by Honeywell Corporation. This HTOP-01 dual precision operational amplifier is a low power device, operates on a single supply, and has an internal oscillator and an external clocking option [1]. It is rated for operation from -55 C to +225 C with a maximum output current capability of 50 mA. The amplifier chip is designed as a 14-pin, hermetically-sealed device in a ceramic package. Table I shows some of the device manufacturer s specifications.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Optical MEMS platform for low-cost on-chip integration of planar light circuits and optical switching

NASA Astrophysics Data System (ADS)

German, Kristine A.; Kubby, Joel; Chen, Jingkuang; Diehl, James; Feinberg, Kathleen; Gulvin, Peter; Herko, Larry; Jia, Nancy; Lin, Pinyen; Liu, Xueyuan; Ma, Jun; Meyers, John; Nystrom, Peter; Wang, Yao Rong

2004-07-01

Xerox Corporation has developed a technology platform for on-chip integration of latching MEMS optical waveguide switches and Planar Light Circuit (PLC) components using a Silicon On Insulator (SOI) based process. To illustrate the current state of this new technology platform, working prototypes of a Reconfigurable Optical Add/Drop Multiplexer (ROADM) and a l-router will be presented along with details of the integrated latching MEMS optical switches. On-chip integration of optical switches and PLCs can greatly reduce the size, manufacturing cost and operating cost of multi-component optical equipment. It is anticipated that low-cost, low-overhead optical network products will accelerate the migration of functions and services from high-cost long-haul markets to price sensitive markets, including networks for metropolitan areas and fiber to the home. Compared to the more common silica-on-silicon PLC technology, the high index of refraction of silicon waveguides created in the SOI device layer enables miniaturization of optical components, thereby increasing yield and decreasing cost projections. The latching SOI MEMS switches feature moving waveguides, and are advantaged across multiple attributes relative to alternative switching technologies, such as thermal optical switches and polymer switches. The SOI process employed was jointly developed under the auspice of the NIST APT program in partnership with Coventor, Corning IntelliSense Corp., and MicroScan Systems to enable fabrication of a broad range of free space and guided wave MicroOptoElectroMechanical Systems (MOEMS).

Determination of the quasi-TE mode (in-plane) graphene linear absorption coefficient via integration with silicon-on-insulator racetrack cavity resonators.

PubMed

Crowe, Iain F; Clark, Nicholas; Hussein, Siham; Towlson, Brian; Whittaker, Eric; Milosevic, Milan M; Gardes, Frederic Y; Mashanovich, Goran Z; Halsall, Matthew P; Vijayaraghaven, Aravind

2014-07-28

We examine the near-IR light-matter interaction for graphene integrated cavity ring resonators based on silicon-on-insulator (SOI) race-track waveguides. Fitting of the cavity resonances from quasi-TE mode transmission spectra reveal the real part of the effective refractive index for graphene, n(eff) = 2.23 ± 0.02 and linear absorption coefficient, α(gTE) = 0.11 ± 0.01dBμm(-1). The evanescent nature of the guided mode coupling to graphene at resonance depends strongly on the height of the graphene above the cavity, which places limits on the cavity length for optical sensing applications.

Analysis and amelioration about the cross-sensitivity of a high resolution MOEMS accelerometer based on diffraction grating

NASA Astrophysics Data System (ADS)

Lu, Qianbo; Bai, Jian; Wang, Kaiwei; Lou, Shuqi; Jiao, Xufen; Han, Dandan

2016-10-01

Cross-sensitivity is a crucial parameter since it detrimentally affect the performance of an accelerometer, especially for a high resolution accelerometer. In this paper, a suite of analytical and finite-elements-method (FEM) models for characterizing the mechanism and features of the cross-sensitivity of a single-axis MOEMS accelerometer composed of a diffraction grating and a micromachined mechanical sensing chip are presented, which have not been systematically investigated yet. The mechanism and phenomena of the cross-sensitivity of this type MOEMS accelerometer based on diffraction grating differ quite a lot from the traditional ones owing to the identical sensing principle. By analyzing the models, some ameliorations and the modified design are put forward to suppress the cross-sensitivity. The modified design, achieved by double sides etching on a specific double-substrate-layer silicon-on-insulator (SOI) wafer, is validated to have a far smaller cross-sensitivity compared with the design previously reported in the literature. Moreover, this design can suppress the cross-sensitivity dramatically without compromising the acceleration sensitivity and resolution.

Ultra-Sensitive Magnetoresistive Displacement Sensing Device

NASA Technical Reports Server (NTRS)

Olivas, John D. (Inventor); Lairson, Bruce M. (Inventor); Ramesham, Rajeshuni (Inventor)

2003-01-01

An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers. Other approaches include reactive ion etching of silicon on insulator (SOI), or Low Pressure Chemical Vapor Deposition of silicon nitride films over silicon substrates. The device is found to be improved with the use of giant magnetoresistive elements to detect changes in the local magnetic field.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Ultra-low loss fully-etched grating couplers for perfectly vertical coupling compatible with DUV lithography tools

NASA Astrophysics Data System (ADS)

Dabos, G.; Pleros, N.; Tsiokos, D.

2016-03-01

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GC's tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL's outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Polarization beam splitter based on a photonic crystal heterostructure.

PubMed

Schonbrun, E; Wu, Q; Park, W; Yamashita, T; Summers, C J

2006-11-01

The design and characterization of a photonic crystal (PC) polarization beam splitter (PBS) that operates with an extinction ratio of greater than 15 dB for both polarizations are presented. The PBS is fabricated on a silicon-on-insulator (SOI) wafer where the input and output ports consist of 5 mum wide ridge waveguides. A large spectral shift is observed in the dispersion plots of the lowest-order even (TE-like) and odd (TM-like) modes due to the SOI confinement. Because of this shift, the TE-like mode is close to a directional gap at the top of the band, and the TM-like mode is in a low-frequency regime where the dispersion surface is almost isotropic. We show that the TE-like mode has very high reflection at the interface between the two PCs, whereas the TM-like mode exhibits a very high transmission.

Micro - ring resonator with variety of gap width for acid rain sensing application: preliminary study

NASA Astrophysics Data System (ADS)

Mulyanti, B.; Ramza, H.; Pawinanto, R. E.; Rahman, J. A.; Ab-Rahman, M. S.; Putro, W. S.; Hasanah, L.; Pantjawati, A. B.

2017-05-01

The acid rain is an environmental disaster that it will be intimidates human life. The development micro-ring resonator sensor created from SOI (Silicon on insulator) and it used to detect acid rain index. In this study, the LUMERICAL software was used to simulate SOI material micro-ring resonator. The result shows the optimum values of fixed parameters from ring resonator have dependent variable in gap width. The layers under ring resonator with silicone (Si) and wafer layer of silicone material (Si) were added to seen three conditions of capability model. Model - 3 is an additional of bottom layer that gives the significant effect on the factor of quality. The optimum value is a peak value that given by the FSR calculation. FSR = 0, it means that is not shows the light propagation in the ring resonator and none of the light coming out on the bus - line.

Fabrication of optical ring resonators in silicon on insulator

NASA Astrophysics Data System (ADS)

Headley, William R.; Reed, Graham T.; Liu, Ansheng; Cohen, Oded; Hak, D.; Paniccia, Mario J.; Howe, Simon; Huille, Inga

2004-07-01

In an effort to determine low-cost alternatives for components currently used in DWDM, optical ring resonators are currently being investigated. The well-known microfabrication techniques of silicon, coupled with the low propagation loss of single crystal silicon, make SOI an attractive material. Laterally coupled racetrack resonators utilising rib waveguides have been fabricated and preliminary results are discussed. An extinction ratio of 15.9 dB and a finesse of 11 have been measured.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

DTIC Science & Technology

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

Electrode Placement for Active Tuning of Silicon-on-Insulator (SOI) Ring Resonator Structure Clad in Nematic Liquid Crystals

DTIC Science & Technology

2014-08-01

Beer – Lambert law :    0 expI z I z  , (1) where α is the attenuation coefficient expressed as 02 ,k k  (2) and 0 02 /k   , where λ0...notwithstanding any other provision of law , no person shall be subject to any penalty for failing to comply with a collection of information if it

Six-beam homodyne laser Doppler vibrometry based on silicon photonics technology.

PubMed

Li, Yanlu; Zhu, Jinghao; Duperron, Matthieu; O'Brien, Peter; Schüler, Ralf; Aasmul, Soren; de Melis, Mirko; Kersemans, Mathias; Baets, Roel

2018-02-05

This paper describes an integrated six-beam homodyne laser Doppler vibrometry (LDV) system based on a silicon-on-insulator (SOI) full platform technology, with on-chip photo-diodes and phase modulators. Electronics and optics are also implemented around the integrated photonic circuit (PIC) to enable a simultaneous six-beam measurement. Measurement of a propagating guided elastic wave in an aluminum plate (speed ≈ 909 m/s @ 61.5 kHz) is demonstrated.

A Ratiometric Wavelength Measurement Based on a Silicon-on-Insulator Directional Coupler Integrated Device

PubMed Central

Wang, Pengfei; Hatta, Agus Muhamad; Zhao, Haoyu; Zheng, Jie; Farrell, Gerald; Brambilla, Gilberto

2015-01-01

A ratiometric wavelength measurement based on a Silicon-on-Insulator (SOI) integrated device is proposed and designed, which consists of directional couplers acting as two edge filters with opposite spectral responses. The optimal separation distance between two parallel silicon waveguides and the interaction length of the directional coupler are designed to meet the desired spectral response by using local supermodes. The wavelength discrimination ability of the designed ratiometric structure is demonstrated by a beam propagation method numerically and then is verified experimentally. The experimental results have shown a general agreement with the theoretical models. The ratiometric wavelength system demonstrates a resolution of better than 50 pm at a wavelength around 1550 nm with ease of assembly and calibration. PMID:26343668

Astable Oscillator Circuits using Silicon-on-Insulator Timer Chip for Wide Range Temperature Sensing

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Culley, Dennis; Hammoud, Ahmad; Elbuluk, Malik

2008-01-01

Two astable oscillator circuits were constructed using a new silicon-on-insulator (SOI) 555 timer chip for potential use as a temperature sensor in harsh environments encompassing jet engine and space mission applications. The two circuits, which differed slightly in configuration, were evaluated between -190 and 200 C. The output of each circuit was made to produce a stream of rectangular pulses whose frequency was proportional to the sensed temperature. The preliminary results indicated that both circuits performed relatively well over the entire test temperature range. In addition, after the circuits were subjected to limited thermal cycling over the temperature range of -190 to 200 C, the performance of either circuit did not experience any significant change.

Thermo-optic characteristics and switching power limit of slow-light photonic crystal structures on a silicon-on-insulator platform.

PubMed

Chahal, Manjit; Celler, George K; Jaluria, Yogesh; Jiang, Wei

2012-02-13

Employing a semi-analytic approach, we study the influence of key structural and optical parameters on the thermo-optic characteristics of photonic crystal waveguide (PCW) structures on a silicon-on-insulator (SOI) platform. The power consumption and spatial temperature profile of such structures are given as explicit functions of various structural, thermal and optical parameters, offering physical insight not available in finite-element simulations. Agreement with finite-element simulations and experiments is demonstrated. Thermal enhancement of the air-bridge structure is analyzed. The practical limit of thermo-optic switching power in slow light PCWs is discussed, and the scaling with key parameters is analyzed. Optical switching with sub-milliwatt power is shown viable.

Radiation-tolerant microprocessors in Japanese scientific space vehicles: how to maximize the benefits of commercial SOI technologies

NASA Astrophysics Data System (ADS)

Kobayashi, Daisuke; Hirose, Kazuyuki; Saito, Hirobumi

2013-05-01

Development of semiconductor devices not only for harsh radiation environments such as space but also for ground-based applications now faces a major hurdle of radiation problems. Necessary is protecting chips from malfunctions due to sub-nanosecond transient noises induced by radiation. As a protection technique using the silicon-on-insulator structure is often suggested, but the use in fact requires devices and circuits carefully optimized for maximizing its benefits. Mainly describing theoretical and experimental characterization of the transient effects, this paper presents a comprehensive study on radiation responses of commercial silicon-on- insulator technologies, which study results in a space-use low-power system-on-chip with a 100-MIPS RISC-based core.

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Theoretical-Experimental Analysis of the Effects of Grain Boundaries on the Electrical Properties of SOI (Silicon-on-Insulator) MOSFETS.

DTIC Science & Technology

1983-11-01

work on recrystallization of polycrystalline silicon ( polysilicon ) films deposited on silicon-dioxide has demonstrated remarkable improvement in film...quality, and thus has identified another possibly viable 1SO technology for ICs. The polysilicon -on-S10 2 technology not only has the advantages alluded...and consequently higher areal device densities. Virtually all the research to date on polysilicon -on-SiO 2 has concentrated on the

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure

PubMed Central

Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go

2017-01-01

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO2 interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e−rms, low dark current density of 56 pA/cm2 at −35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV. PMID:29295523

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

PubMed

Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2017-12-23

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Photonic bandpass filter characteristics of multimode SOI waveguides integrated with submicron gratings.

PubMed

Sah, Parimal; Das, Bijoy Krishna

2018-03-20

It has been shown that a fundamental mode adiabatically launched into a multimode SOI waveguide with submicron grating offers well-defined flat-top bandpass filter characteristics in transmission. The transmitted spectral bandwidth is controlled by adjusting both waveguide and grating design parameters. The bandwidth is further narrowed down by cascading two gratings with detuned parameters. A semi-analytical model is used to analyze the filter characteristics (1500  nm≤λ≤1650  nm) of the device operating in transverse-electric polarization. The proposed devices were fabricated with an optimized set of design parameters in a SOI substrate with a device layer thickness of 250 nm. The pass bandwidth of waveguide devices integrated with single-stage gratings are measured to be ∼24  nm, whereas the device with two cascaded gratings with slightly detuned periods (ΔΛ=2  nm) exhibits a pass bandwidth down to ∼10  nm.

A Basic Research for the Development and Evaluation of Novel MEMS Digital Accelerometers

DTIC Science & Technology

2013-02-01

that timing differences as measured by the circuit are linearly dependent on the measured capacitance changes. As such, the circuit’s readout is...error in the electronic measurement to refine the technique. An additional capability of the circuit is the ability to observe the impact of cold...low resistivity on (ɘ.01 Ω-cm) silicon on insulator wafers (SOI). The beams are fabricated in a 0.3 cm by 0.3 cm die which is then packaged and wire

SOI layout decomposition for double patterning lithography on high-performance computer platforms

NASA Astrophysics Data System (ADS)

Verstov, Vladimir; Zinchenko, Lyudmila; Makarchuk, Vladimir

2014-12-01

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on 45 nm Nangate Open Cell Library including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; White, Mark; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Electrical characterization of strained and unstrained silicon nanowires with nickel silicide contacts.

PubMed

Habicht, S; Zhao, Q T; Feste, S F; Knoll, L; Trellenkamp, S; Ghyselen, B; Mantl, S

2010-03-12

We present electrical characterization of nickel monosilicide (NiSi) contacts formed on strained and unstrained silicon nanowires (NWs), which were fabricated by top-down processing of initially As(+) implanted and activated strained and unstrained silicon-on-insulator (SOI) substrates. The resistivity of doped Si NWs and the contact resistivity of the NiSi to Si NW contacts are studied as functions of the As(+) ion implantation dose and the cross-sectional area of the wires. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. An increase in resistivity with decreasing cross section of the NWs was observed for all implantation doses. This is ascribed to the occurrence of dopant deactivation. Comparing the silicidation of uniaxially tensile strained and unstrained Si NWs shows no difference in silicidation speed and in contact resistivity between NiSi/Si NW. Contact resistivities as low as 1.2 x 10(-8) Omega cm(-2) were obtained for NiSi contacts to both strained and unstrained Si NWs. Compared to planar contacts, the NiSi/Si NW contact resistivity is two orders of magnitude lower.

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.

2018-05-01

This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included papers on advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.).

Transparent, Flexible Silicon Nanostructured Wire Networks with Seamless Junctions for High-Performance Photodetector Applications.

PubMed

Hossain, Mozakkar; Kumar, Gundam Sandeep; Barimar Prabhava, S N; Sheerin, Emmet D; McCloskey, David; Acharya, Somobrata; Rao, K D M; Boland, John J

2018-05-22

Optically transparent photodetectors are crucial in next-generation optoelectronic applications including smart windows and transparent image sensors. Designing photodetectors with high transparency, photoresponsivity, and robust mechanical flexibility remains a significant challenge, as is managing the inevitable trade-off between high transparency and strong photoresponse. Here we report a scalable method to produce flexible crystalline Si nanostructured wire (NW) networks fabricated from silicon-on-insulator (SOI) with seamless junctions and highly responsive porous Si segments that combine to deliver exceptional performance. These networks show high transparency (∼92% at 550 nm), broadband photodetection (350 to 950 nm) with excellent responsivity (25 A/W), optical response time (0.58 ms), and mechanical flexibility (1000 cycles). Temperature-dependent photocurrent measurements indicate the presence of localized electronic states in the porous Si segments, which play a crucial role in light harvesting and photocarrier generation. The scalable low-cost approach based on SOI has the potential to deliver new classes of flexible optoelectronic devices, including next-generation photodetectors and solar cells.

Tunable filters based on an SOI nano-wire waveguide micro ring resonator

NASA Astrophysics Data System (ADS)

Shuai, Li; Yuanda, Wu; Xiaojie, Yin; Junming, An; Jianguang, Li; Hongjie, Wang; Xiongwei, Hu

2011-08-01

Micro ring resonator (MRR) filters based on a silicon on insulator (SOI) nanowire waveguide are fabricated by electron beam photolithography (EBL) and inductive coupled plasma (ICP) etching technology. The cross-section size of the strip waveguides is 450 × 220 nm2, and the bending radius of the micro ring is around 5 μm. The test results from the tunable filter based on a single ring show that the free spectral range (FSR) is 16.8 nm and the extinction ratio (ER) around the wavelength 1550 nm is 18.1 dB. After thermal tuning, the filter's tuning bandwidth reaches 4.8 nm with a tuning efficiency of 0.12 nm/°C Meanwhile, we fabricated and studied multi-channel filters based on a single ring and a double ring. After measurement, we drew the following conclusions: during the signal transmission of multi-channel filters, crosstalk exists mainly among different transmission channels and are fairly distinct when there are signals input to add ports.

SU-8 microcantilever with an aperture, fluidic channel, and sensing mechanisms for biological and other applications.

PubMed

Gaitas, Angelo; Hower, Robert W

2014-09-15

We describe a method for fabricating an aperture on a fluidic cantilever device using SU-8 as a structural material. The device can ultimately be used for patch clamping, microinjections, fluidic delivery, fluidic deposition, and micromaterial removal. In the first generation of this device, the initial aperture diameter is 10 μ m and is fabricated on a silicon-on-insulator (SOI) wafer that is structurally used to define the aperture. The aperture can be reduced in size through mask design. This self-aligned process allows for patterning on the sharp tip projecting out of the fluidic plane on the cantilever and is batch fabricated, reducing the cost and time for manufacture. The initial mask, SOI device layer thickness, and the width of the base of the tip define the size of the aperture. The SU-8 micromachined cantilever includes an electrode and a force sensing mechanism. The cantilever can be easily integrated with an atomic force microscope or an optical microscope.

Channel add-drop filter based on dual photonic crystal cavities in push-pull mode.

PubMed

Poulton, Christopher V; Zeng, Xiaoge; Wade, Mark T; Popović, Miloš A

2015-09-15

We demonstrate an add-drop filter based on a dual photonic crystal nanobeam cavity system that emulates the operation of a traveling wave resonator, and, thus, provides separation of the through and drop port transmission from the input port. The device is on a 3×3  mm chip fabricated in an advanced microelectronics silicon-on-insulator complementary metal-oxide semiconductor (SOI CMOS) process (IBM 45 nm SOI) without any foundry process modifications. The filter shows 1 dB of insertion loss in the drop port with a 3 dB bandwidth of 64 GHz, and 16 dB extinction in the through port. To the best of our knowledge, this is the first implementation of a port-separating, add-drop filter based on standing wave cavities coupled to conventional waveguides, and demonstrates a performance that suggests potential for photonic crystal devices within optical immersion lithography-based advanced CMOS electronics-photonics integration.

30GHz Ge electro-absorption modulator integrated with 3 μm silicon-on-insulator waveguide.

PubMed

Feng, Ning-Ning; Feng, Dazeng; Liao, Shirong; Wang, Xin; Dong, Po; Liang, Hong; Kung, Cheng-Chih; Qian, Wei; Fong, Joan; Shafiiha, Roshanak; Luo, Ying; Cunningham, Jack; Krishnamoorthy, Ashok V; Asghari, Mehdi

2011-04-11

We demonstrate a compact waveguide-based high-speed Ge electro-absorption (EA) modulator integrated with a single mode 3 µm silicon-on-isolator (SOI) waveguide. The Ge EA modulator is based on a horizontally-oriented p-i-n structure butt-coupled with a deep-etched silicon waveguide, which transitions adiabatically to a shallow-etched single mode large core SOI waveguide. The demonstrated device has a compact active region of 1.0 × 45 µm(2), a total insertion loss of 2.5-5 dB and an extinction ratio of 4-7.5 dB over a wavelength range of 1610-1640 nm with -4V(pp) bias. The estimated Δα/α value is in the range of 2-3.3. The 3 dB bandwidth measurements show that the device is capable of operating at more than 30 GHz. Clear eye-diagram openings at 12.5 Gbps demonstrates large signal modulation at high transmission rate. © 2011 Optical Society of America

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Lasing in silicon–organic hybrid waveguides

PubMed Central

Korn, Dietmar; Lauermann, Matthias; Koeber, Sebastian; Appel, Patrick; Alloatti, Luca; Palmer, Robert; Dumon, Pieter; Freude, Wolfgang; Leuthold, Juerg; Koos, Christian

2016-01-01

Silicon photonics enables large-scale photonic–electronic integration by leveraging highly developed fabrication processes from the microelectronics industry. However, while a rich portfolio of devices has already been demonstrated on the silicon platform, on-chip light sources still remain a key challenge since the indirect bandgap of the material inhibits efficient photon emission and thus impedes lasing. Here we demonstrate a class of infrared lasers that can be fabricated on the silicon-on-insulator (SOI) integration platform. The lasers are based on the silicon–organic hybrid (SOH) integration concept and combine nanophotonic SOI waveguides with dye-doped organic cladding materials that provide optical gain. We demonstrate pulsed room-temperature lasing with on-chip peak output powers of up to 1.1 W at a wavelength of 1,310 nm. The SOH approach enables efficient mass-production of silicon photonic light sources emitting in the near infrared and offers the possibility of tuning the emission wavelength over a wide range by proper choice of dye materials and resonator geometry. PMID:26949229

Strain-Engineered Nanomembrane Substrates for Si/SiGe Heterostructures

NASA Astrophysics Data System (ADS)

Sookchoo, Pornsatit

For Group IV materials, including silicon, germanium, and their alloys, although they are most widely used in the electronics industry, the development of photonic devices is hindered by indirect band gaps and large lattice mismatches. Thus, any heterostructures involving Si and Ge (4.17% lattice mismatch) are subject to plastic relaxation by dislocation formation in the heterolayers. These defects make many devices impossible and at minimum degrade the performance of those that are possible. Fabrication using elastic strain engineering in Si/SiGe nanomembranes (NMs) is an approach that is showing promise to overcome this limitation. A key advantage of such NM substrates over conventional bulk substrates is that they are relaxed elastically and therefore free of dislocations that occur in the conventional fabrication of SiGe substrates, which are transferred to the epilayers and roughen film interfaces. In this thesis, I use the strain engineering of NMs or NM stacks to fabricate substrates for the epitaxial growth of many repeating units of Si/SiGe heterostructure, known as a 'superlattice', by the elastic strain sharing of a few periods of the repeating unit of Si/SiGe heterolayers or a Si/SiGe/Si tri-layer structure. In both cases, the process begins with the epitaxial growth of Si/SiGe heterolayers on silicon-on-insulator (SOI), where each layer thickness is designed to stay below its kinetic critical thickness for the formation of dislocations. The heterostructure NMs are then released by etching of the SiO2 sacrificial layer in hydrofluoric acid. The resulting freestanding NMs are elastically relaxed by the sharing of strain between the heterolayers. The NMs can be bonded in-place to their host substrate or transferred to another host substrate for the subsequent growth of many periods of superlattice film. The magnitude of strain sharing in these freestanding NMs is influenced by their layer thicknesses and layer compositions. As illustrated in this dissertation, strain-engineering of such NMs can provide the enabling basis for improved Group IV optoelectronic devices.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

NASA Technical Reports Server (NTRS)

Chen, Liang-yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

2016-01-01

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

Waveguide embedded plasmon laser with multiplexing and electrical modulation

DOEpatents

Ma, Ren-min; Zhang, Xiang

2017-08-29

This disclosure provides systems, methods, and apparatus related to nanometer scale lasers. In one aspect, a device includes a substrate, a line of metal disposed on the substrate, an insulating material disposed on the line of metal, and a line of semiconductor material disposed on the substrate and the insulating material. The line of semiconductor material overlaying the line of metal, disposed on the insulating material, forms a plasmonic cavity.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

DOE Office of Scientific and Technical Information (OSTI.GOV)

CRESSWELL,M.W.; ALLEN,R.A.; GHOSHTAGORE,R.N.

This paper describes the fabrication and measurement of the linewidths of the reference segments of cross-bridge resistors patterned in (100) Bonded and Etched Back Silicon-on-Insulator (BESOI) material. The critical dimensions (CD) of the reference segments of a selection of the cross-bridge resistor test structures were measured both electrically and by Scanning-Electron Microscopy (SEM) cross-section imaging. The reference-segment features were aligned with <110> directions in the BESOI surface material and had drawn linewidths ranging from 0.35 to 3.0 {micro}m. They were defined by a silicon micro-machining process which results in their sidewalls being atomically-planar and smooth and inclined at 54.737{degree} tomore » the surface (100) plane of the substrate. This (100) implementation may usefully complement the attributes of the previously-reported vertical-sidewall one for selected reference-material applications. For example, the non-orthogonal intersection of the sidewalls and top-surface planes of the reference-segment features may alleviate difficulties encountered with atomic-force microscope measurements. In such applications it has been reported that it may be difficult to maintain probe-tip control at the sharp 90{degree} outside corner of the sidewalls and the upper surface. A second application is refining to-down image-processing algorithms and checking instrument performance. Novel aspects of the (100) SOI implementation that are reported here include the cross-bridge resistor test-structure architecture and details of its fabrication. The long-term goal is to develop a technique for the determination of the absolute dimensions of the trapezoidal cross-sections of the cross-bridge resistors' reference segments, as a prelude to developing them for dimensional reference applications. This is believed to be the first report of electrical CD measurements made on test structures of the cross-bridge resistor type that have been patterned in (100) SOI material. The electrical CD results are compared with cross-section SEM measurements made on the same features.« less

Vacuum-insulated catalytic converter

DOEpatents

Benson, David K.

2001-01-01

A catalytic converter has an inner canister that contains catalyst-coated substrates and an outer canister that encloses an annular, variable vacuum insulation chamber surrounding the inner canister. An annular tank containing phase-change material for heat storage and release is positioned in the variable vacuum insulation chamber a distance spaced part from the inner canister. A reversible hydrogen getter in the variable vacuum insulation chamber, preferably on a surface of the heat storage tank, releases hydrogen into the variable vacuum insulation chamber to conduct heat when the phase-change material is hot and absorbs the hydrogen to limit heat transfer to radiation when the phase-change material is cool. A porous zeolite trap in the inner canister absorbs and retains hydrocarbons from the exhaust gases when the catalyst-coated substrates and zeolite trap are cold and releases the hydrocarbons for reaction on the catalyst-coated substrate when the zeolite trap and catalyst-coated substrate get hot.

Refractory Oxidative-Resistant Ceramic Carbon Insulation

NASA Technical Reports Server (NTRS)

Leiser, Daniel B. (Inventor); Hsu, Ming-Ta S. (Inventor); Chen, Timothy S. (Inventor)

2001-01-01

High-temperature, lightweight, ceramic carbon insulation is prepared by coating or impregnating a porous carbon substrate with a siloxane gel derived from the reaction of an organodialkoxy silane and an organotrialkoxy silane in an acid or base medium in the presence of the carbon substrate. The siloxane gel is subsequently dried on the carbon substrate to form a ceramic carbon precursor. The carbon precursor is pyrolyzed, in an inert atmosphere, to form the ceramic insulation containing carbon, silicon, and oxygen. The carbon insulation is characterized as a porous, fibrous, carbon ceramic tile which is particularly useful as lightweight tiles for spacecraft.

Terahertz Difference-Frequency Quantum Cascade Laser Sources on Silicon

DTIC Science & Technology

2016-12-22

temperature. The introduction of the Cherenkov waveguide scheme in these devices grown on semi- insulating InP substrates enabled generation of tens...room temperature, a factor of 5 improvement over the best reference devices on a native semi- insulating InP substrate. © 2016 Optical Society of America...implementation of the Cherenkov emission scheme [10]. Cherenkov THz DFG-QCLs reported so far use a semi- insulating (SI) InP substrate. SI InP

Investigation of SOI Raman Lasers for Mid-Infrared Gas Sensing

PubMed Central

Passaro, Vittorio M.N.; De Leonardis, Francesco

2009-01-01

In this paper, the investigation and detailed modeling of a cascaded Raman laser, operating in the midwave infrared region, is described. The device is based on silicon-on-insulator optical waveguides and a coupled resonant microcavity. Theoretical results are compared with recent experiments, demonstrating a very good agreement. Design criteria are derived for cascaded Raman lasers working as continuous wave light sources to simultaneously sense two types of gases, namely C2H6 and CO2, at a moderate power level of 130 mW. PMID:22408481

Fast and low power Michelson interferometer thermo-optical switch on SOI.

PubMed

Song, Junfeng; Fang, Q; Tao, S H; Liow, T Y; Yu, M B; Lo, G Q; Kwong, D L

2008-09-29

We designed and fabricated silicon-on-insulator based Michelson interferometer (MI) thermo-optical switches with deep etched trenches for heat-isolation. Switch power was reduced approximately 20% for the switch with deep etched trenches, and the MI saved approximately 50% power than that of the Mach-Zehnder interferometer. 10.6 mW switch power, approximately 42 micros switch time for the MI with deep trenches, 13.14 mW switch power and approximately 34 micros switch time for the MI without deep trenches were achieved.

Local doping of two-dimensional materials

DOEpatents

Wong, Dillon; Velasco, Jr, Jairo; Ju, Long; Kahn, Salman; Lee, Juwon; Germany, Chad E.; Zettl, Alexander K.; Wang, Feng; Crommie, Michael F.

2016-09-20

This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material.

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

DOEpatents

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

NASA Astrophysics Data System (ADS)

Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

2018-05-01

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

NASA Astrophysics Data System (ADS)

Shrestha, Sumeet; Kamehama, Hiroki; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2015-08-01

This paper presents a low-noise wide-dynamic-range pixel design for a high-energy particle detector in astronomical applications. A silicon on insulator (SOI) based detector is used for the detection of wide energy range of high energy particles (mainly for X-ray). The sensor has a thin layer of SOI CMOS readout circuitry and a thick layer of high-resistivity detector vertically stacked in a single chip. Pixel circuits are divided into two parts; signal sensing circuit and event detection circuit. The event detection circuit consisting of a comparator and logic circuits which detect the incidence of high energy particle categorizes the incident photon it into two energy groups using an appropriate energy threshold and generate a two-bit code for an event and energy level. The code for energy level is then used for selection of the gain of the in-pixel amplifier for the detected signal, providing a function of high-dynamic-range signal measurement. The two-bit code for the event and energy level is scanned in the event scanning block and the signals from the hit pixels only are read out. The variable-gain in-pixel amplifier uses a continuous integrator and integration-time control for the variable gain. The proposed design allows the small signal detection and wide dynamic range due to the adaptive gain technique and capability of correlated double sampling (CDS) technique of kTC noise canceling of the charge detector.

Zero-group-velocity acoustic waveguides for high-frequency resonators

NASA Astrophysics Data System (ADS)

Caliendo, C.; Hamidullah, M.

2017-11-01

The propagation of the Lamb-like modes along a silicon-on-insulator (SOI)/AlN thin supported structure was simulated in order to exploit the intrinsic zero group velocity (ZGV) features to design electroacoustic resonators that do not require metal strip gratings or suspended edges to confine the acoustic energy. The ZGV resonant conditions in the SOI/AlN composite plate, i.e. the frequencies where the mode group velocity vanishes while the phase velocity remains finite, were investigated in the frequency range from few hundreds of MHz up to 1900 MHz. Some ZGV points were found that show up mostly in low-order modes. The thermal behaviour of these points was studied in the  -30 to 220 °C temperature range and the temperature coefficients of the ZGV resonant frequencies (TCF) were estimated. The behaviour of the ZGV resonators operating as gas sensors was studied under the hypothesis that the surface of the device is covered with a thin polyisobutylene (PIB) film able to selectively adsorb dichloromethane (CH2Cl2), trichloromethane (CHCl3), carbontetrachloride (CCl4), tetrachloroethylene (C2Cl4), and trichloroethylene (C2HCl3), at atmospheric pressure and room temperature. The sensor sensitivity to gas concentration in air was simulated for the first four ZGV points of the inhomogeneous plate. The feasibility of high-frequency, low TCF electroacoustic micro-resonator based on SOI and piezoelectric thin film technology was demonstrated by the present simulation study.

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

NASA Astrophysics Data System (ADS)

Yan-Hui, Zhang; Jie, Wei; Chao, Yin; Qiao, Tan; Jian-Ping, Liu; Peng-Cheng, Li; Xiao-Rong, Luo

2016-02-01

A uniform doping ultra-thin silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor (LDMOS) with low specific on-resistance (Ron,sp) and high breakdown voltage (BV) is proposed and its mechanism is investigated. The proposed LDMOS features an accumulation-mode extended gate (AG) and back-side etching (BE). The extended gate consists of a P- region and two diodes in series. In the on-state with VGD > 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The Ron,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the Ron,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping (VLD) and the “hot-spot” caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the Ron,sp by 70.2% and increases the BV from 776 V to 818 V. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079).

Fabry-Perot resonators with transverse coupling on SOI using loop mirrors

NASA Astrophysics Data System (ADS)

Saber, Md Ghulam; Abadía, Nicolás; Wang, Yun; Plant, David V.

2018-05-01

A novel integrated transversely coupled Fabry-Perot resonator using loop mirrors as the end reflectors are demonstrated via simulations and experiments on the silicon-on-insulator (SOI) platform. The resonator is formed by connecting two loop mirrors to the two output ports of a directional coupler to form the resonant cavity and utilizing the other two ports as the input and the output. Depending on which two ports of the directional coupler are mirrored, two configurations of the resonator can be achieved. The impacts of varying the cavity length and the coupling coefficient of the directional coupler on the output characteristics of the resonators are analyzed. A Q-factor of 28086 and an extinction ratio of 10.04 dB with an insertion loss of 1.9 dB is achieved experimentally for a 1038 μm cavity length and an extinction ratio of 18.14 dB and a Q-factor of 5120 with an insertion loss of 2.12 dB is obtained for a cavity length of 376 μm. The reported resonator offers additional freedom to tune the spectral characteristics.

Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

NASA Astrophysics Data System (ADS)

Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

2016-09-01

In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

Investigation of AWG demultiplexer based SOI for CWDM application

NASA Astrophysics Data System (ADS)

Juhari, Nurjuliana; Susthitha Menon, P.; Shaari, Sahbudin; Annuar Ehsan, Abang

2017-11-01

9-channel Arrayed Waveguide Grating (AWG) demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM) with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n 3.47) material namely silicon-on-insulator (SOI) with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM) wavelength grid.

A Library of Rad Hard Mixed-Voltage/Mixed-Signal Building Blocks for Integration of Avionics Systems for Deep Space

NASA Technical Reports Server (NTRS)

Mojarradi, M. M.; Blaes, B.; Kolawa, E. A.; Blalock, B. J.; Li, H. W.; Buck, K.; Houge, D.

2001-01-01

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography.

PubMed

Benedikovic, Daniel; Alonso-Ramos, Carlos; Pérez-Galacho, Diego; Guerber, Sylvain; Vakarin, Vladyslav; Marcaud, Guillaume; Le Roux, Xavier; Cassan, Eric; Marris-Morini, Delphine; Cheben, Pavel; Boeuf, Frédéric; Baudot, Charles; Vivien, Laurent

2017-09-01

Grating couplers enable position-friendly interfacing of silicon chips by optical fibers. The conventional coupler designs call upon comparatively complex architectures to afford efficient light coupling to sub-micron silicon-on-insulator (SOI) waveguides. Conversely, the blazing effect in double-etched gratings provides high coupling efficiency with reduced fabrication intricacy. In this Letter, we demonstrate for the first time, to the best of our knowledge, the realization of an ultra-directional L-shaped grating coupler, seamlessly fabricated by using 193 nm deep-ultraviolet (deep-UV) lithography. We also include a subwavelength index engineered waveguide-to-grating transition that provides an eight-fold reduction of the grating reflectivity, down to 1% (-20  dB). A measured coupling efficiency of -2.7  dB (54%) is achieved, with a bandwidth of 62 nm. These results open promising prospects for the implementation of efficient, robust, and cost-effective coupling interfaces for sub-micrometric SOI waveguides, as desired for large-volume applications in silicon photonics.

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

PubMed Central

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-01-01

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

PubMed

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-11-17

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < -17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology.

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

NASA Astrophysics Data System (ADS)

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film.

PubMed

Yebo, Nebiyu A; Lommens, Petra; Hens, Zeger; Baets, Roel

2010-05-24

Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 microm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.

A Plasmonic based Ultracompact Polarization Beam Splitter on Silicon-on-Insulator Waveguides

PubMed Central

Tan, Qilong; Huang, Xuguang; Zhou, Wen; Yang, Kun

2013-01-01

An ultracompact polarization beam splitter (PBS) is designed on silicon-on-insulator (SOI) platform based on the localized surface plasmons (LSPs) excited by particular polarization light. The device uses nanoscale silver cylinders as the polarization selection between two silicon waveguides of a directional coupler. The transverse-magnetic (TM) polarization light excites localized surface plasmons and is coupled into the cross port of the directional coupler with a low insert loss, while the transverse-electric (TE) polarization light is under restriction. The PBS has a coupling layer with 50 nm width and 1.1 μm length supporting broadband operation. The simulation calculations show that 22.06dB and 23.06dB of extinction ratios for the TE and TM polarizations were obtained, together with insertion losses of 0.09dB and 0.40dB. PMID:23856635

High temperature and frequency pressure sensor based on silicon-on-insulator layers

NASA Astrophysics Data System (ADS)

Zhao, Y. L.; Zhao, L. B.; Jiang, Z. D.

2006-03-01

Based on silicon on insulator (SOI) technology, a novel high temperature pressure sensor with high frequency response is designed and fabricated, in which a buried silicon dioxide layer in the silicon material is developed by the separation by implantation of oxygen (SIMOX) technology. This layer can isolate leak currents between the top silicon layer for the detecting circuit and body silicon at a temperature of about 200 °C. In addition, the technology of silicon and glass bonding is used to create a package of the sensor without internal strain. A structural model and test data from the sensor are presented. The experimental results showed that this kind of sensor possesses good static performance in a high temperature environment and high frequency dynamic characteristics, which may satisfy the pressure measurement demands of the oil industry, aviation and space, and so on.

Coherent X-Ray Diffraction Imaging and Characterization of Strain in Silicon-on-Insulator Nanostructures

PubMed Central

Xiong, Gang; Moutanabbir, Oussama; Reiche, Manfred; Harder, Ross; Robinson, Ian

2014-01-01

Coherent X-ray diffraction imaging (CDI) has emerged in the last decade as a promising high resolution lens-less imaging approach for the characterization of various samples. It has made significant technical progress through developments in source, algorithm and imaging methodologies thus enabling important scientific breakthroughs in a broad range of disciplines. In this report, we will introduce the principles of forward scattering CDI and Bragg geometry CDI (BCDI), with an emphasis on the latter. BCDI exploits the ultra-high sensitivity of the diffraction pattern to the distortions of crystalline lattice. Its ability of imaging strain on the nanometer scale in three dimensions is highly novel. We will present the latest progress on the application of BCDI in investigating the strain relaxation behavior in nanoscale patterned strained silicon-on-insulator (sSOI) materials, aiming to understand and engineer strain for the design and implementation of new generation semiconductor devices. PMID:24955950

Electrospinning onto Insulating Substrates by Controlling Surface Wettability and Humidity

NASA Astrophysics Data System (ADS)

Choi, WooSeok; Kim, Geon Hwee; Shin, Jung Hwal; Lim, Geunbae; An, Taechang

2017-11-01

We report a simple method for electrospinning polymers onto flexible, insulating substrates by controlling the wettability of the substrate surface. Water molecules were adsorbed onto the surface of a hydrophilic polymer substrate by increasing the local humidity around the substrate. The adsorbed water was used as the ground electrode for electrospinning. The electrospun fibers were deposited only onto hydrophilic areas of the substrate, allowing for patterning through wettability control. Direct writing of polymer fiber was also possible through near-field electrospinning onto a hydrophilic surface.

Graphene as discharge layer for electron beam lithography on insulating substrate

NASA Astrophysics Data System (ADS)

Liu, Junku; Li, Qunqing; Ren, Mengxin; Zhang, Lihui; Chen, Mo; Fan, Shoushan

2013-09-01

Charging of insulating substrates is a common problem during Electron Beam lithography (EBL), which deflects the beam and distorts the pattern. A homogeneous, electrically conductive, and transparent graphene layer is used as a discharge layer for EBL processes on insulating substrates. The EBL resolution is improved compared with the metal discharge layer. Dense arrays of holes with diameters of 50 nm and gratings with line/space of 50/30 nm are obtained on quartz substrate. The pattern placement errors and proximity effect are suppressed over a large area and high quality complex nanostructures are fabricated using graphene as a conductive layer.

Temperature dependent evolution of wrinkled single-crystal silicon ribbons on shape memory polymers.

PubMed

Wang, Yu; Yu, Kai; Qi, H Jerry; Xiao, Jianliang

2017-10-25

Shape memory polymers (SMPs) can remember two or more distinct shapes, and thus can have a lot of potential applications. This paper presents combined experimental and theoretical studies on the wrinkling of single-crystal Si ribbons on SMPs and the temperature dependent evolution. Using the shape memory effect of heat responsive SMPs, this study provides a method to build wavy forms of single-crystal silicon thin films on top of SMP substrates. Silicon ribbons obtained from a Si-on-insulator (SOI) wafer are released and transferred onto the surface of programmed SMPs. Then such bilayer systems are recovered at different temperatures, yielding well-defined, wavy profiles of Si ribbons. The wavy profiles are shown to evolve with time, and the evolution behavior strongly depends on the recovery temperature. At relatively low recovery temperatures, both wrinkle wavelength and amplitude increase with time as evolution progresses. Finite element analysis (FEA) accounting for the thermomechanical behavior of SMPs is conducted to study the wrinkling of Si ribbons on SMPs, which shows good agreement with experiment. Merging of wrinkles is observed in FEA, which could explain the increase of wrinkle wavelength observed in the experiment. This study can have important implications for smart stretchable electronics, wrinkling mechanics, stimuli-responsive surface engineering, and advanced manufacturing.

Accurate Characterization of Benign and Cancerous Breast Tissues: Aspecific Patient Studies using Piezoresistive Microcantilevers

PubMed Central

PANDYA, HARDIK J.; ROY, RAJARSHI; CHEN, WENJIN; CHEKMAREVA, MARINA A.; FORAN, DAVID J.; DESAI, JAYDEV P.

2014-01-01

Breast cancer is the largest detected cancer amongst women in the US. In this work, our team reports on the development of piezoresistive microcantilevers (PMCs) to investigate their potential use in the accurate detection and characterization of benign and diseased breast tissues by performing indentations on the micro-scale tissue specimens. The PMCs used in these experiments have been fabricated using laboratory-made silicon-on-insulator (SOI) substrate, which significantly reduces the fabrication costs. The PMCs are 260 μm long, 35 μm wide and 2 μm thick with resistivity of order 1.316 X 10−3 Ω-cm obtained by using boron diffusion technique. For indenting the tissue, we utilized 8 μm thick cylindrical SU-8 tip. The PMC was calibrated against a known AFM probe. Breast tissue cores from seven different specimens were indented using PMC to identify benign and cancerous tissue cores. Furthermore, field emission scanning electron microscopy (FE-SEM) of benign and cancerous specimens showed marked differences in the tissue morphology, which further validates our observed experimental data with the PMCs. While these patient aspecific feasibility studies clearly demonstrate the ability to discriminate between benign and cancerous breast tissues, further investigation is necessary to perform automated mechano-phenotyping (classification) of breast cancer: from onset to disease progression. PMID:25128621

Large-scale quantum photonic circuits in silicon

NASA Astrophysics Data System (ADS)

Harris, Nicholas C.; Bunandar, Darius; Pant, Mihir; Steinbrecher, Greg R.; Mower, Jacob; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Englund, Dirk

2016-08-01

Quantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today's classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI) nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3)) of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes. Here, we discuss the SOI nanophotonics platform for quantum photonic circuits with hundreds-to-thousands of optical elements and the associated challenges. We compare SOI to competing technologies in terms of requirements for quantum optical systems. We review recent results on large-scale quantum state evolution circuits and strategies for realizing high-fidelity heralded gates with imperfect, practical systems. Next, we review recent results on silicon photonics-based photon-pair sources and device architectures, and we discuss a path towards large-scale source integration. Finally, we review monolithic integration strategies for single-photon detectors and their essential role in on-chip feed forward operations.

High-contrast grating hollow-core waveguide splitter applied to optical phased array

NASA Astrophysics Data System (ADS)

Zhao, Che; Xue, Ping; Zhang, Hanxing; Chen, Te; Peng, Chao; Hu, Weiwei

2014-11-01

A novel hollow-core (HW) Y-branch waveguide splitter based on high-contrast grating (HCG) is presented. We calculated and designed the HCG-HW splitter using Rigorous Coupled Wave Analysis (RCWA). Finite-different timedomain (FDTD) simulation shows that the splitter has a broad bandwidth and the branching loss is as low as 0.23 dB. Fabrication is accomplished with standard Silicon-On-Insulator (SOI) process. The experimental measurement results indicate its good performance on beam splitting near the central wavelength λ = 1550 nm with a total insertion loss of 7.0 dB.

A process to control light in a micro resonator through a coupling modulation by surface acoustic waves

NASA Astrophysics Data System (ADS)

Fan, Guofang; Li, Yuan; Hu, Chunguang; Lei, Lihua; Guo, Yanchuan

2016-08-01

A novel process to control light through the coupling modulation by surface acoustic wave (SAW) is presented in an optical micro resonator. An optical waveguide modulator of a racetrack resonator on silicon-on-insulator (SOI) technology is took as an example to explore the mechanism. A finite-difference time-domain (FDTD) is developed to simulate the acousto-optical (AO) modulator using the mechanism. An analytical method is presented to verify our proposal. The results show that the process can work well as an optical modulator by SAW.

Low-loss slot waveguides with silicon (111) surfaces realized using anisotropic wet etching

NASA Astrophysics Data System (ADS)

Debnath, Kapil; Khokhar, Ali; Boden, Stuart; Arimoto, Hideo; Oo, Swe; Chong, Harold; Reed, Graham; Saito, Shinichi

2016-11-01

We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI) platform. Waveguides oriented along the (11-2) direction on the Si (110) plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

Catalytic devices

DOEpatents

Liu, Ming; Zhang, Xiang

2018-01-23

This disclosure provides systems, methods, and apparatus related to catalytic devices. In one aspect, a device includes a substrate, an electrically insulating layer disposed on the substrate, a layer of material disposed on the electrically insulating layer, and a catalyst disposed on the layer of material. The substrate comprises an electrically conductive material. The substrate and the layer of material are electrically coupled to one another and configured to have a voltage applied across them.

Effect of the substrate on the insulator-metal transition of vanadium dioxide films

NASA Astrophysics Data System (ADS)

Kovács, György J.; Bürger, Danilo; Skorupa, Ilona; Reuther, Helfried; Heller, René; Schmidt, Heidemarie

2011-03-01

Single-phase vanadium dioxide films grown on (0001) sapphire and (001) silicon substrates show a very different insulator-metal electronic transition. A detailed description of the growth mechanisms and the substrate-film interaction is given, and the characteristics of the electronic transition are described by the morphology and grain boundary structure. (Tri-)epitaxy-stabilized columnar growth of VO2 takes place on the sapphire substrate, whereas on silicon the expected Zone II growth is identified. We have found that in the case of the Si substrate the reasons for the broader hysteresis and the lower switching amplitude are the formation of an amorphous insulating VOx (x > 2.6) phase coexisting with VO2 and the high vanadium vacancy concentration of the VO2. These phenomena are the result of the excess oxygen during the growth and the interaction between the silicon substrate and the growing film.

Thermal stress in flexible interdigital transducers with anisotropic electroactive cellulose substrates

NASA Astrophysics Data System (ADS)

Yoon, Sean J.; Kim, Jung Woong; Kim, Hyun Chan; Kang, Jinmo; Kim, Jaehwan

2017-12-01

Thermal stress in flexible interdigital transducers a reliability concern in the development of flexible devices, which may lead to interface delamination, stress voiding and plastic deformation. In this paper, a mathematical model is presented to investigate the effect of material selections on the thermal stress in interdigital transducers. We modified the linear relationships in the composite materials theory with the effect of high curvature, anisotropic substrate and small substrate thickness. We evaluated the thermal stresses of interdigital transducers, fabricated with various electrodes, insulators and substrate materials for the comparison. The results show that, among various insulators, organic polymer developed the highest stress level while oxide showed the lowest stress level. Aluminium shows a higher stress level and curvature as an electrode than gold. As substrate materials, polyimide and electroactive cellulose show similar stress levels except the opposite sign convention to each other. Polyimide shows positive curvatures while electroactive cellulose shows negative curvatures, which is attributed to the stress and thermal expansion state of the metal/insulator composite. The results show that the insulator is found to be responsible for the confinement across the metal lines while the substrate is responsible for the confinement along the metal lines.

Experimental verification of layout physical verification of silicon photonics

NASA Astrophysics Data System (ADS)

El Shamy, Raghi S.; Swillam, Mohamed A.

2018-02-01

Silicon photonics have been approved as one of the best platforms for dense integration of photonic integrated circuits (PICs) due to the high refractive index contrast among its materials. Silicon on insulator (SOI) is a widespread photonics technology, which support a variety of devices for lots of applications. As the photonics market is growing, the number of components in the PICs increases which increase the need for an automated physical verification (PV) process. This PV process will assure reliable fabrication of the PICs as it will check both the manufacturability and the reliability of the circuit. However, PV process is challenging in the case of PICs as it requires running an exhaustive electromagnetic (EM) simulations. Our group have recently proposed an empirical closed form models for the directional coupler and the waveguide bends based on the SOI technology. The models have shown a very good agreement with both finite element method (FEM) and finite difference time domain (FDTD) solvers. These models save the huge time of the 3D EM simulations and can be easily included in any electronic design automation (EDA) flow as the equations parameters can be easily extracted from the layout. In this paper we present experimental verification for our previously proposed models. SOI directional couplers with different dimensions have been fabricated using electron beam lithography and measured. The results from the measurements of the fabricate devices have been compared to the derived models and show a very good agreement. Also the matching can reach 100% by calibrating certain parameter in the model.

Improving breakdown voltage performance of SOI power device with folded drift region

NASA Astrophysics Data System (ADS)

Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

2016-07-01

A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

Conformally encapsulated multi-electrode arrays with seamless insulation

DOEpatents

Tabada, Phillipe J.; Shah, Kedar G.; Tolosa, Vanessa; Pannu, Satinderall S.; Tooker, Angela; Delima, Terri; Sheth, Heeral; Felix, Sarah

2016-11-22

Thin-film multi-electrode arrays (MEA) having one or more electrically conductive beams conformally encapsulated in a seamless block of electrically insulating material, and methods of fabricating such MEAs using reproducible, microfabrication processes. One or more electrically conductive traces are formed on scaffold material that is subsequently removed to suspend the traces over a substrate by support portions of the trace beam in contact with the substrate. By encapsulating the suspended traces, either individually or together, with a single continuous layer of an electrically insulating material, a seamless block of electrically insulating material is formed that conforms to the shape of the trace beam structure, including any trace backings which provide suspension support. Electrical contacts, electrodes, or leads of the traces are exposed from the encapsulated trace beam structure by removing the substrate.

Whiskerless Schottky diode

NASA Technical Reports Server (NTRS)

Bishop, William L. (Inventor); Mcleod, Kathleen A. (Inventor); Mattauch, Robert J. (Inventor)

1991-01-01

A Schottky diode for millimeter and submillimeter wave applications is comprised of a multi-layered structure including active layers of gallium arsenide on a semi-insulating gallium arsenide substrate with first and second insulating layers of silicon dioxide on the active layers of gallium arsenide. An ohmic contact pad lays on the silicon dioxide layers. An anode is formed in a window which is in and through the silicon dioxide layers. An elongated contact finger extends from the pad to the anode and a trench, preferably a transverse channel or trench of predetermined width, is formed in the active layers of the diode structure under the contact finger. The channel extends through the active layers to or substantially to the interface of the semi-insulating gallium arsenide substrate and the adjacent gallium arsenide layer which constitutes a buffer layer. Such a structure minimizes the effect of the major source of shunt capacitance by interrupting the current path between the conductive layers beneath the anode contact pad and the ohmic contact. Other embodiments of the diode may substitute various insulating or semi-insulating materials for the silicon dioxide, various semi-conductors for the active layers of gallium arsenide, and other materials for the substrate, which may be insulating or semi-insulating.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Electrostatically screened, voltage-controlled electrostatic chuck

DOEpatents

Klebanoff, Leonard Elliott

2001-01-01

Employing an electrostatically screened, voltage-controlled electrostatic chuck particularly suited for holding wafers and masks in sub-atmospheric operations will significantly reduce the likelihood of contaminant deposition on the substrates. The electrostatic chuck includes (1) an insulator block having a outer perimeter and a planar surface adapted to support the substrate and comprising at least one electrode (typically a pair of electrodes that are embedded in the insulator block), (2) a source of voltage that is connected to the at least one electrode, (3) a support base to which the insulator block is attached, and (4) a primary electrostatic shield ring member that is positioned around the outer perimeter of the insulator block. The electrostatic chuck permits control of the voltage of the lithographic substrate; in addition, it provides electrostatic shielding of the stray electric fields issuing from the sides of the electrostatic chuck. The shielding effectively prevents electric fields from wrapping around to the upper or front surface of the substrate, thereby eliminating electrostatic particle deposition.

Wide-Temperature-Range Integrated Operational Amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

2007-01-01

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Heterojunction fully depleted SOI-TFET with oxide/source overlap

NASA Astrophysics Data System (ADS)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

PubMed

Takulapalli, Bharath R

2010-02-23

Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

An active locking mechanism for assembling 3D micro structures

NASA Astrophysics Data System (ADS)

Zhang, Ping; Mayyas, Mohammad; Lee, Woo Ho; Popa, Dan; Shiakolas, Panos; Stephanou, Harry; Chiao, J. C.

2007-01-01

Microassembly is an enabling technology to build 3D microsystems consisting of microparts made of different materials and processes. Multiple microparts can be connected together to construct complicated in-plane and out-of-plane microsystems by using compliant mechanical structures such as micro hinges and snap fasteners. This paper presents design, fabrication, and assembly of an active locking mechanism that provides mechanical and electrical interconnections between mating microparts. The active locking mechanism is composed of thermally actuated Chevron beams and sockets. Assembly by means of an active locking mechanism offers more flexibility in designing microgrippers as it reduces or minimizes mating force, which is one of the main reasons causing fractures in a microgripper during microassembly operation. Microgrippers, microparts, and active locking mechanisms were fabricated on a silicon substrate using the deep reactive ion etching (DRIE) processes with 100-um thick silicon on insulator (SOI) wafers. A precision robotic assembly platform with a dual microscope vision system was used to automate the manipulation and assembly processes of microparts. The assembly sequence includes (1) tether breaking and picking up of a micropart by using an electrothermally actuated microgripper, (2) opening of a socket area for zero-force insertion, (3) a series of translation and rotation of a mating micropart to align it onto the socket, (4) insertion of a micropart into the socket, and (5) deactivation and releasing of locking fingers. As a result, the micropart was held vertically to the substrate and locked by the compliance of Chevron beams. Microparts were successfully assembled using the active locking mechanism and the measured normal angle was 89.2°. This active locking mechanism provides mechanical and electrical interconnections, and it can potentially be used to implement a reconfigurable microrobot that requires complex assembly of multiple links and joints.

High fill-factor micromirror array using a self-aligned vertical comb drive actuator with two rotational axes

NASA Astrophysics Data System (ADS)

Kim, Minsoo; Park, Jae-Hyoung; Jeon, Jin-A.; Yoo, Byung-Wook; Park, I. H.; Kim, Yong-Kweon

2009-03-01

We present a two-axis micromirror array with high fill-factor, using a new fabrication procedure on the full wafer scale. The micromirror comprises a self-aligned vertical comb drive actuator with a mirror plate mounted on it and electrical lines on a bottom substrate. A high-aspect-ratio vertical comb drive was built using a bulk micromachining technique on a silicon-on-insulator (SOI) wafer. The thickness of the torsion spring was adjusted using multiple silicon etching steps to enhance the static angular deflection of the mirrors. To address the array, electrical lines were fabricated on a glass substrate and combined with the comb actuators using an anodic bonding process. The silicon mirror plate was fabricated together with the actuator using a wafer bonding process and segmented at the final release step. The actuator and addressing lines were hidden behind the mirror plate, resulting in a high fill-factor of 84% in an 8 × 8 array of micromirrors, each 340 µm × 340 µm. The fabricated mirror plate has a high-quality optical surface with an average surface roughness (Ra) of 4 nm and a curvature radius of 0.9 m. The static and dynamic responses of the micromirror were characterized by comparing the measured results with the calculated values. The maximum static optical deflection for the outer axis is 4.32° at 60 V, and the maximum inner axis tilting angle is 2.82° at 96 V bias. The torsion resonance frequencies along the outer and inner axes were 1.94 kHz and 0.95 kHz, respectively.

Active control of lateral leakage in thin-ridge SOI waveguide structures

NASA Astrophysics Data System (ADS)

Dalvand, Naser; Nguyen, Thach G.; Tummidi, Ravi S.; Koch, Thomas L.; Mitchell, Arnan

2011-12-01

We report on the design and simulation of a novel Silicon-On-Insulator waveguide structures which when excited with TM guided light, emit TE polarized radiation with controlled radiation characteristics[1]. The structures utilize parallel leaky waveguides of specific separations. The structures are simulated using a full-vector mode-matching approach which allows visualisation of the evolution of the propagating and radiating fields over the length of the waveguide structure. It is shown that radiation can be resonantly enhanced or suppressed in different directions depending on the choice of the phase of the excitation of the waveguide components. Steps toward practical demonstration are identified.

OM300 Direction Drilling Module

DOE Data Explorer

MacGugan, Doug

2013-08-22

OM300 – Geothermal Direction Drilling Navigation Tool: Design and produce a prototype directional drilling navigation tool capable of high temperature operation in geothermal drilling Accuracies of 0.1° Inclination and Tool Face, 0.5° Azimuth Environmental Ruggedness typical of existing oil/gas drilling Multiple Selectable Sensor Ranges High accuracy for navigation, low bandwidth High G-range & bandwidth for Stick-Slip and Chirp detection Selectable serial data communications Reduce cost of drilling in high temperature Geothermal reservoirs Innovative aspects of project Honeywell MEMS* Vibrating Beam Accelerometers (VBA) APS Flux-gate Magnetometers Honeywell Silicon-On-Insulator (SOI) High-temperature electronics Rugged High-temperature capable package and assembly process

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

SOFI/Substrate integrity testing for cryogenic propellant tanks at extreme thermal gradient conditions

NASA Astrophysics Data System (ADS)

Haynes, M.; Fabian, P.

2015-12-01

Liquid propellant tank insulation for space flight requires low weight as well as high insulation factors. Use of Spray-On Foam Insulation (SOFI) is an accepted, cost effective technique for insulating a single wall cryogenic propellant tank and has been used extensively throughout the aerospace industry. Determining the bond integrity of the SOFI to the metallic substrate as well as its ability to withstand the in-service strains, both mechanical and thermal, is critical to the longevity of the insulation. This determination has previously been performed using highly volatile, explosive cryogens, which increases the test costs enormously, as well as greatly increasing the risk to both equipment and personnel. CTD has developed a new test system, based on a previous NASA test that simulates the mechanical and thermal strains associated with filling a large fuel tank with a cryogen. The test enables a relatively small SOFI/substrate sample to be monitored for any deformations, delaminations, or disjunctures during the cooling and mechanical straining process of the substrate, and enables the concurrent application of thermal and physical strains to two specimens at the same time. The thermal strains are applied by cooling the substrate to the desired cryogen temperature (from 4 K to 250 K) while maintaining the outside surface of the SOFI foam at ambient conditions. Multiple temperature monitoring points are exercised to ensure even cooling across the substrate, while at the same time, surface temperatures of the SOFI can be monitored to determine the heat flow. The system also allows for direct measurement of the strains in the substrate during the test. The test system as well as test data from testing at 20 K, for liquid Hydrogen simulation, will be discussed.

Coherent X-ray diffraction imaging and characterization of strain in silicon-on-insulator nanostructures

DOE PAGES

Xiong, Gang; Moutanabbir, Oussama; Reiche, Manfred; ...

2014-12-06

Coherent X-ray diffraction imaging (CDI) has emerged in the last decade as a promising high resolution lens-less imaging approach for the characterization of various samples. It has made significant technical progress through developments in source, algorithm and imaging methodologies thus enabling important scientific breakthroughs in a broad range of disciplines. In this report, we will introduce the principles of forward scattering CDI and Bragg geometry CDI (BCDI), with an emphasis on the latter. BCDI exploits the ultra-high sensitivity of the diffraction pattern to the distortions of crystalline lattice. Its ability of imaging strain on the nanometer scale in three dimensionsmore » is highly novel. In this study, we will present the latest progress on the application of BCDI in investigating the strain relaxation behavior in nanoscale patterned strained silicon-on-insulator (sSOI) materials, aiming to understand and engineer strain for the design and implementation of new generation semiconductor devices.« less

Defect-mediated resonance shift of silicon-on-insulator racetrack resonators.

PubMed

Ackert, J J; Doylend, J K; Logan, D F; Jessop, P E; Vafaei, R; Chrostowski, L; Knights, A P

2011-06-20

We present a study on the effects of inert ion implantation of Silicon-On-Insulator (SOI) racetrack resonators. Selective ion implantation was used to create deep-level defects within a portion of the resonator. The resonant wavelength and round-trip loss were deduced for a range of sequential post-implantation annealing temperatures from 100 to 300 °C. As the devices were annealed there was a concomitant change in the resonance wavelength, consistent with an increase in refractive index following implantation and recovery toward the pre-implanted value. A total shift in resonance wavelength of ~2.9 nm was achieved, equivalent to a 0.02 increase in refractive index. The excess loss upon implantation increased to 301 dB/cm and was reduced to 35 dB/cm following thermal annealing. In addition to providing valuable data for those incorporating defects within resonant structures, we suggest that these results present a method for permanent tuning (or trimming) of ring resonator characteristics.

Coherent X-ray diffraction imaging and characterization of strain in silicon-on-insulator nanostructures.

PubMed

Xiong, Gang; Moutanabbir, Oussama; Reiche, Manfred; Harder, Ross; Robinson, Ian

2014-12-10

Coherent X-ray diffraction imaging (CDI) has emerged in the last decade as a promising high resolution lens-less imaging approach for the characterization of various samples. It has made significant technical progress through developments in source, algorithm and imaging methodologies thus enabling important scientific breakthroughs in a broad range of disciplines. In this report, we will introduce the principles of forward scattering CDI and Bragg geometry CDI (BCDI), with an emphasis on the latter. BCDI exploits the ultra-high sensitivity of the diffraction pattern to the distortions of crystalline lattice. Its ability of imaging strain on the nanometer scale in three dimensions is highly novel. We will present the latest progress on the application of BCDI in investigating the strain relaxation behavior in nanoscale patterned strained silicon-on-insulator (sSOI) materials, aiming to understand and engineer strain for the design and implementation of new generation semiconductor devices. © 2014 The Authors. Published by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Evaluation of a silicon 5 MHz p–n diode actuator with a laterally vibrating extensional mode

NASA Astrophysics Data System (ADS)

Miyazaki, Fumito; Baba, Kazuki; Tanigawa, Hiroshi; Furutsuka, Takashi; Suzuki, Kenichiro

2018-05-01

In this paper, we describe p–n diode actuators that are laterally driven by the force induced in a depletion layer. The previously reported p–n diode actuators have been vertically driven. Because the resonant frequency depends on the thickness of the vibrating plate, the integration of resonators with different frequencies on a chip has been difficult. The resonators in this work are driven laterally by using length-extensional vibration. We have developed a compact model based on an analytical expression, in which p–n diode actuators are driven by the forces induced by the spread of the depletion layer. The deflection generated by the p–n diode actuators was proportional to the ratio of the depletion layer width to the resonator thickness as well as the position of the p–n junction. Good agreement of experimental results with the theory was confirmed by comparing the measured values for silicon p–n diode rectangular-plate actuators fabricated using a silicon-on-insulator (SOI) substrate. The displacement amplitude of the actuators was proportional to the DC bias, while the resonant frequency was independent of the DC bias. The latter characteristic is very different from that of widely used electrostatic actuators. Although the amplitude of the actuator measured in this work was very small, it is expected that the amplitude will increase greatly by increasing the doping of the p–n diode actuators.

MEMS capacitive accelerometer-based middle ear microphone.

PubMed

Young, Darrin J; Zurcher, Mark A; Semaan, Maroun; Megerian, Cliff A; Ko, Wen H

2012-12-01

The design, implementation, and characterization of a microelectromechanical systems (MEMS) capacitive accelerometer-based middle ear microphone are presented in this paper. The microphone is intended for middle ear hearing aids as well as future fully implantable cochlear prosthesis. Human temporal bones acoustic response characterization results are used to derive the accelerometer design requirements. The prototype accelerometer is fabricated in a commercial silicon-on-insulator (SOI) MEMS process. The sensor occupies a sensing area of 1 mm × 1 mm with a chip area of 2 mm × 2.4 mm and is interfaced with a custom-designed low-noise electronic IC chip over a flexible substrate. The packaged sensor unit occupies an area of 2.5 mm × 6.2 mm with a weight of 25 mg. The sensor unit attached to umbo can detect a sound pressure level (SPL) of 60 dB at 500 Hz, 35 dB at 2 kHz, and 57 dB at 8 kHz. An improved sound detection limit of 34-dB SPL at 150 Hz and 24-dB SPL at 500 Hz can be expected by employing start-of-the-art MEMS fabrication technology, which results in an articulation index of approximately 0.76. Further micro/nanofabrication technology advancement is needed to enhance the microphone sensitivity for improved understanding of normal conversational speech.

Polymer Nanofiber Based Reversible Nano-Switch/Sensor Diode (Nanosssd) Device

NASA Technical Reports Server (NTRS)

Theofylaktos, Onoufrios (Inventor); Meador, Michael A. (Inventor); Miranda, Felix A. (Inventor); Pinto, Nicholas (Inventor); Mueller, Carl H. (Inventor); Santos-Perez, Javier (Inventor)

2017-01-01

A nanostructure device is provided and performs dual functions as a nano-switching/sensing device. The nanostructure device includes a doped semiconducting substrate, an insulating layer disposed on the doped semiconducting substrate, an electrode formed on the insulating layer, and at least one polymer nanofiber deposited on the electrode. The at least one polymer nanofiber provides an electrical connection between the electrode and the substrate and is the electroactive element in the device.

Characterizing the structure of topological insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Richardella, Anthony; Kandala, Abhinav; Lee, Joon Sue

2015-08-01

We describe the characterization of structural defects that occur during molecular beam epitaxy of topological insulator thin films on commonly used substrates. Twinned domains are ubiquitous but can be reduced by growth on smooth InP (111)A substrates, depending on details of the oxide desorption. Even with a low density of twins, the lattice mismatch between (Bi, Sb){sub 2}Te{sub 3} and InP can cause tilts in the film with respect to the substrate. We also briefly discuss transport in simultaneously top and back electrically gated devices using SrTiO{sub 3} and the use of capping layers to protect topological insulator films frommore » oxidation and exposure.« less

Direct synthesis of large area graphene on insulating substrate by gallium vapor-assisted chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Murakami, Katsuhisa, E-mail: k.murakami@bk.tsukuba.ac.jp; Hiyama, Takaki; Kuwajima, Tomoya

2015-03-02

A single layer of graphene with dimensions of 20 mm × 20 mm was grown directly on an insulating substrate by chemical vapor deposition using Ga vapor catalysts. The graphene layer showed highly homogeneous crystal quality over a large area on the insulating substrate. The crystal quality of the graphene was measured by Raman spectroscopy and was found to improve with increasing Ga vapor density on the reaction area. High-resolution transmission electron microscopy observations showed that the synthesized graphene had a perfect atomic-scale crystal structure within its grains, which ranged in size from 50 nm to 200 nm.

The Growth of Expitaxial GaAs and GaAlAs on Silicon Substrates by OMVPE

DTIC Science & Technology

1988-08-01

structures have been grown on semi-insulating gallium arsenide substrates, and on high-resistivity silicon substrates using a two stage growth technique...fully in Quarter 9. 2. MATERIALS GROWTH 2.1 DOPING OF GALLIUM ARSENIDE FOR FETs As reported in quarter 7, doping levels for GaAs/SI 4ere found to be a...FET structures on both GaAs and Si substrates. A number of FET layers have been grown to the GAT4 specification on semi-insulating gallium arsenide

Photocapacitive image converter

NASA Technical Reports Server (NTRS)

Miller, W. E.; Sher, A.; Tsuo, Y. H. (Inventor)

1982-01-01

An apparatus for converting a radiant energy image into corresponding electrical signals including an image converter is described. The image converter includes a substrate of semiconductor material, an insulating layer on the front surface of the substrate, and an electrical contact on the back surface of the substrate. A first series of parallel transparent conductive stripes is on the insulating layer with a processing circuit connected to each of the conductive stripes for detecting the modulated voltages generated thereon. In a first embodiment of the invention, a modulated light stripe perpendicular to the conductive stripes scans the image converter. In a second embodiment a second insulating layer is deposited over the conductive stripes and a second series of parallel transparent conductive stripes perpendicular to the first series is on the second insulating layer. A different frequency current signal is applied to each of the second series of conductive stripes and a modulated image is applied to the image converter.

Deeply etched MMI-based components on 4 μm thick SOI for SOA-based optical RAM cell circuits

NASA Astrophysics Data System (ADS)

Cherchi, Matteo; Ylinen, Sami; Harjanne, Mikko; Kapulainen, Markku; Aalto, Timo; Kanellos, George T.; Fitsios, Dimitrios; Pleros, Nikos

2013-02-01

We present novel deeply etched functional components, fabricated by multi-step patterning in the frame of our 4 μm thick Silicon on Insulator (SOI) platform based on singlemode rib-waveguides and on the previously developed rib-tostrip converter. These novel components include Multi-Mode Interference (MMI) splitters with any desired splitting ratio, wavelength sensitive 50/50 splitters with pre-filtering capability, multi-stage Mach-Zehnder Interferometer (MZI) filters for suppression of Amplified Spontaneous Emission (ASE), and MMI resonator filters. These novel building blocks enable functionalities otherwise not achievable on our SOI platform, and make it possible to integrate optical RAM cell layouts, by resorting to our technology for hybrid integration of Semiconductor Optical Amplifiers (SOAs). Typical SOA-based RAM cell layouts require generic splitting ratios, which are not readily achievable by a single MMI splitter. We present here a novel solution to this problem, which is very compact and versatile and suits perfectly our technology. Another useful functional element when using SOAs is the pass-band filter to suppress ASE. We pursued two complimentary approaches: a suitable interleaved cascaded MZI filter, based on a novel suitably designed MMI coupler with pre-filtering capabilities, and a completely novel MMI resonator concept, to achieve larger free spectral ranges and narrower pass-band response. Simulation and design principles are presented and compared to preliminary experimental functional results, together with scaling rules and predictions of achievable RAM cell densities. When combined with our newly developed ultra-small light-turning concept, these new components are expected to pave the way for high integration density of RAM cells.

Current isolating epitaxial buffer layers for high voltage photodiode array

DOEpatents

Morse, Jeffrey D.; Cooper, Gregory A.

2002-01-01

An array of photodiodes in series on a common semi-insulating substrate has a non-conductive buffer layer between the photodiodes and the semi-insulating substrate. The buffer layer reduces current injection leakage between the photodiodes of the array and allows optical energy to be converted to high voltage electrical energy.

A method to restrain the charging effect on an insulating substrate in high energy electron beam lithography

NASA Astrophysics Data System (ADS)

Mingyan, Yu; Shirui, Zhao; Yupeng, Jing; Yunbo, Shi; Baoqin, Chen

2014-12-01

Pattern distortions caused by the charging effect should be reduced while using the electron beam lithography process on an insulating substrate. We have developed a novel process by using the SX AR-PC 5000/90.1 solution as a spin-coated conductive layer, to help to fabricate nanoscale patterns of poly-methyl-methacrylate polymer resist on glass for phased array device application. This method can restrain the influence of the charging effect on the insulating substrate effectively. Experimental results show that the novel process can solve the problems of the distortion of resist patterns and electron beam main field stitching error, thus ensuring the accuracy of the stitching and overlay of the electron beam lithography system. The main characteristic of the novel process is that it is compatible to the multi-layer semiconductor process inside a clean room, and is a green process, quite simple, fast, and low cost. It can also provide a broad scope in the device development on insulating the substrate, such as high density biochips, flexible electronics and liquid crystal display screens.

Method of fabricating high-density hermetic electrical feedthroughs

DOEpatents

Shah, Kedar G.; Pannu, Satinderpall S.; Delima, Terri L.

2015-06-02

A method of fabricating electrical feedthroughs selectively removes substrate material from a first side of an electrically conductive substrate (e.g. a bio-compatible metal) to form an array of electrically conductive posts in a substrate cavity. An electrically insulating material (e.g. a bio-compatible sealing glass) is then flowed to fill the substrate cavity and surround each post, and solidified. The solidified insulating material is then exposed from an opposite second side of the substrate so that each post is electrically isolated from each other as well as the bulk substrate. In this manner a hermetic electrically conductive feedthrough construction is formed having an array of electrical feedthroughs extending between the first and second sides of the substrate from which it was formed.

Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

DOEpatents

Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

2017-03-28

A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

The comprehensive study and the reduction of contact resistivity on the n-InGaAs M-I-S contact system with different inserted insulators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liao, M.-H., E-mail: mhliaoa@ntu.edu.tw; Lien, C.

2015-05-15

Five different kinds of insulators including BaTiO{sub 3}, TiO{sub 2}, Al{sub 2}O{sub 3}, CdO and ZnO on the n-type InGaAs metal-insulator-semiconductor (M-I-S) ohmic contact structure are studied. The effect for the dielectric constant (ε) of inserted insulator and the conduction band offset (CBO) between an insulator and semiconductor substrate is analyzed by a unified M-I-S contact model. Based on the theoretical model and experimental data, we demonstrates that the inserted ZnO insulator with the high electron affinity and the low CBO (∼0.1 eV) to the InGaAs substrate results in ∼10 times contact resistivity reduction, even the ε of ZnO ismore » not pretty high (∼10)« less

Single Versus Multiple Solid Organ Injuries Following Blunt Abdominal Trauma.

PubMed

El-Menyar, Ayman; Abdelrahman, Husham; Al-Hassani, Ammar; Peralta, Ruben; AbdelAziz, Hiba; Latifi, Rifat; Al-Thani, Hassan

2017-11-01

We aimed to describe the pattern of solid organ injuries (SOIs) and analyze the characteristics, management and outcomes based on the multiplicity of SOIs. A retrospective study in a Level 1 trauma center was conducted and included patients admitted with blunt abdominal trauma between 2011 and 2014. Data were analyzed and compared for patients with single versus multiple SOIs. A total of 504 patients with SOIs were identified with a mean age of 28 ± 13 years. The most frequently injured organ was liver (45%) followed by spleen (30%) and kidney (18%). One-fifth of patients had multiple SOIs, of that 87% had two injured organs. Patients with multiple SOIs had higher frequency of head injury and injury severity scores (p < 0.05). The majority of SOIs were treated nonoperatively, whereas operative management was required in a quarter of patients, mostly in patients with multiple SOIs (p = 0.01). Blood transfusion, sepsis and hospital stay were greater in multiple than single SOIs (p < 0.05). The overall mortality was 11% which was comparable between the two groups. In patients with single SOIs, the mortality was significantly higher in those who had pancreatic (28.6%) or hepatic injuries (13%) than the other SOIs. SOIs represent one-tenth of trauma admissions in Qatar. Although liver was the most frequently injured organ, the rate of mortality was higher in pancreatic injury. Patients with multiple SOIs had higher morbidity which required frequent operative management. Further prospective studies are needed to develop management algorithm based on the multiplicity of SOIs.

Graphene Based Reversible Nano-Switch/Sensor Schottky Diode (NANOSSSD) Device

NASA Technical Reports Server (NTRS)

Miranda, Felix A. (Inventor); Theofylaktos, Onoufrios (Inventor); Pinto, Nicholas J. (Inventor); Mueller, Carl H. (Inventor); Santos, Javier (Inventor); Meador, Michael A. (Inventor)

2015-01-01

A nanostructure device is provided and performs dual functions as a nano-switching/sensing device. The nanostructure device includes a doped semiconducting substrate, an insulating layer disposed on the doped semiconducting substrate, an electrode formed on the insulating layer, and at least one layer of graphene formed on the electrode. The at least one layer of graphene provides an electrical connection between the electrode and the substrate and is the electroactive element in the device.

Advanced BCD technology with vertical DMOS based on a semi-insulation structure

NASA Astrophysics Data System (ADS)

Kui, Ma; Xinghua, Fu; Jiexin, Lin; Fashun, Yang

2016-07-01

A new semi-insulation structure in which one isolated island is connected to the substrate was proposed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical device without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabricated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated. Project supported by the National Natural Science Foundation of China (No. 61464002), the Science and Technology Fund of Guizhou Province (No. Qian Ke He J Zi [2014]2066), and the Dr. Fund of Guizhou University (No. Gui Da Ren Ji He Zi (2013)20Hao).

All diamond self-aligned thin film transistor

DOEpatents

Gerbi, Jennifer [Champaign, IL

2008-07-01

A substantially all diamond transistor with an electrically insulating substrate, an electrically conductive diamond layer on the substrate, and a source and a drain contact on the electrically conductive diamond layer. An electrically insulating diamond layer is in contact with the electrically conductive diamond layer, and a gate contact is on the electrically insulating diamond layer. The diamond layers may be homoepitaxial, polycrystalline, nanocrystalline or ultrananocrystalline in various combinations.A method of making a substantially all diamond self-aligned gate transistor is disclosed in which seeding and patterning can be avoided or minimized, if desired.

Note: long-range scanning tunneling microscope for the study of nanostructures on insulating substrates.

PubMed

Molina-Mendoza, Aday J; Rodrigo, José G; Island, Joshua; Burzuri, Enrique; Rubio-Bollinger, Gabino; van der Zant, Herre S J; Agraït, Nicolás

2014-02-01

The scanning tunneling microscope (STM) is a powerful tool for studying the electronic properties at the atomic level, however, it is of relatively small scanning range and the fact that it can only operate on conducting samples prevents its application to study heterogeneous samples consisting of conducting and insulating regions. Here we present a long-range scanning tunneling microscope capable of detecting conducting micro and nanostructures on insulating substrates using a technique based on the capacitance between the tip and the sample and performing STM studies.

Interfacial phonon scattering and transmission loss in > 1 µm thick silicon-on-insulator thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Puqing; Lindsay, Lucas R.; Huang, Xi

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. Here, to better understand the interfacial scattering of phonons and to test the validity of Ziman'smore » theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1–10 μm and a temperature range of 100–300 K. The Si/SiO 2 interface roughness was determined to be 0.11±0.04nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. Finally, we derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.« less

Interfacial phonon scattering and transmission loss in > 1 µm thick silicon-on-insulator thin films

DOE PAGES

Jiang, Puqing; Lindsay, Lucas R.; Huang, Xi; ...

2018-05-17

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. Here, to better understand the interfacial scattering of phonons and to test the validity of Ziman'smore » theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1–10 μm and a temperature range of 100–300 K. The Si/SiO 2 interface roughness was determined to be 0.11±0.04nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. Finally, we derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.« less

System and method for floating-substrate passive voltage contrast

DOEpatents

Jenkins, Mark W [Albuquerque, NM; Cole, Jr., Edward I.; Tangyunyong, Paiboon [Albuquerque, NM; Soden, Jerry M [Placitas, NM; Walraven, Jeremy A [Albuquerque, NM; Pimentel, Alejandro A [Albuquerque, NM

2009-04-28

A passive voltage contrast (PVC) system and method are disclosed for analyzing ICs to locate defects and failure mechanisms. During analysis a device side of a semiconductor die containing the IC is maintained in an electrically-floating condition without any ground electrical connection while a charged particle beam is scanned over the device side. Secondary particle emission from the device side of the IC is detected to form an image of device features, including electrical vias connected to transistor gates or to other structures in the IC. A difference in image contrast allows the defects or failure mechanisms be pinpointed. Varying the scan rate can, in some instances, produce an image reversal to facilitate precisely locating the defects or failure mechanisms in the IC. The system and method are useful for failure analysis of ICs formed on substrates (e.g. bulk semiconductor substrates and SOI substrates) and other types of structures.

A Temperature-Hardened Sensor Interface with a 12-Bit Digital Output Using a Novel Pulse Width Modulation Technique

PubMed Central

Badets, Franck; Nouet, Pascal; Masmoudi, Mohamed

2018-01-01

A fully integrated sensor interface for a wide operational temperature range is presented. It translates the sensor signal into a pulse width modulated (PWM) signal that is then converted into a 12-bit digital output. The sensor interface is based on a pair of injection locked oscillators used to implement a differential time-domain architecture with low sensitivity to temperature variations. A prototype has been fabricated using a 180 nm partially depleted silicon-on-insulator (SOI) technology. Experimental results demonstrate a thermal stability as low as 65 ppm/°C over a large temperature range from −20 °C up to 220 °C. PMID:29621171

Concentric circular focusing reflector realized using high index contrast gratings

NASA Astrophysics Data System (ADS)

Fang, Wenjing; Huang, Yongqing; Fei, Jiarui; Duan, Xiaofeng; Liu, Kai; Ren, Xiaomin

2017-11-01

A non-periodic concentric circular high index contrast grating (CC-HCG) focusing reflector on 500 nm silicon-on-insulator (SOI) platform is fabricated and experimentally demonstrated. The proposed mirror is realized with phase modulation of wave front in a high reflectivity region. The circular structure based HCG focusing reflector has a spot of high concentration at the 10.87 mm with normal incidence for radially polarization, along with the center wavelength set at 1550 nm. The FWHM spot size of the focusing beam decreases to 260 μm, and the intensity increases to 1.26 compared with the incident beam. The focusing efficiency of about 80% is observed at 1550 nm in the experimental measurement.

Micromachined force-balance feedback accelerometer with optical displacement detection

DOEpatents

Nielson, Gregory N.; Langlois, Eric; Baker, Michael; Okandan, Murat; Anderson, Robert

2014-07-22

An accelerometer includes a proof mass and a frame that are formed in a handle layer of a silicon-on-an-insulator (SOI). The proof mass is separated from the frame by a back-side trench that defines a boundary of the proof mass. The accelerometer also includes a reflector coupled to a top surface of the proof mass. An optical detector is located above the reflector at the device side. The accelerometer further includes at least one suspension spring. The suspension spring has a handle anchor that extends downwards from the device side to the handle layer to mechanically support upward and downward movement of the proof mass relative to a top surface of the proof mass.

Surface-micromachined 2D optical scanners with optically flat single-crystalline silicon micromirrors

NASA Astrophysics Data System (ADS)

Su, John G.; Patterson, Pamela R.; Wu, Ming C.

2001-05-01

We have developed a novel wafer-scale single-crystalline silicon micromirror bonding process to fabricate optically flat micromirrors on polysilicon surface-micromachined 2D scanners. The electrostatically actuated 2D scanner has a mirror area of 450 micrometers x 450 micrometers and an optical scan angle of +/- +/-7.5 degree(s). Compared to micromirrors made with a standard polysilicon surface-micromachining process, the radius of curvature of the micromirror has been improved by 1 50 times from 1.8 cm to 265 cm, with surface roughness < 10 nm. Besides, single-crystalline honeycomb micromirrors derived from silicon on insulator (SOI) have been developed to reduce the mass of the bonded mirror.

Substrate composition and moisture in composting source-separated human faeces and food waste.

PubMed

Niwagaba, C; Nalubega, M; Vinnerås, B; Sundberg, C; Jönsson, H

2009-04-14

The composting of a faeces/ash mixture and food waste in relative proportions of 1:0, 1:1 and 1:3 was studied in three successive experiments conducted in Kampala, Uganda in 216 L reactors insulated with 75 mm styrofoam or not insulated. The faeces/ash mixture alone exceeded 50 degrees C for < or = 12 days in insulated reactors, but did not reach or maintain 50 degrees C in non-insulated reactors. Inclusion of food waste kept temperatures above 50 degrees C for over two weeks in insulated reactors except when the substrate was too wet. Escherichia coli and total coliform concentrations decreased below detection in material that exceeded 50 degrees C for at least six days. Enterococcus spp. decreased below detection in material that exceeded 50 degrees C for at least two weeks, but remained detectable after 1.5 months in material that exceeded 50 degrees C for less than two weeks, suggesting that a period of at least two weeks above 50 degrees C, combined with mixing, is needed to achieve sanitation. Initially substrates that were too wet proved a challenge to composting and ways of decreasing substrate moisture should be investigated. The results obtained are applicable to the management of small- to medium-scale composting of faeces/ash and food waste at household and institution levels, e.g. schools and restaurants.

Four-Quadrant Analog Multipliers Using G4-FETs

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Blalock, Benjamin; Christoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

2006-01-01

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

[Study on Strain Detection with Si Based on Bicyclic Cascade Optical Microring Resonator].

PubMed

Tang, Jun; Lei, Long-hai; Zhang, Wei; Zhang, Tian-en; Xue, Chen-yang; Zhang, Wen-dong; Liu, Jun

2016-03-01

Optical micro-ring resonator prepared on Silicon-On-Insulator (SOI) has high sensitivity, small size and low mode volume. Its high sensitivity has been widely applied to the optical information transmission and inertial navigation devices field, while it is rarely applied in the testing of Mechanics. This paper presents a cantilever stress/strain gauge with an optical microring resonator. It is proposed the using of radius change of ring waveguide for the sensing element. When external stress is put on the structure, the radius of the SOI ring waveguide will be subjected to variation, which causes the optical resonant parameters to change. This ultimately leads to a red-shift of resonant spectrum, and shows the excellent characteristics of the structure's stress/strain sensitivity. Designed a bicyclic cascade embedded optical micro-cavity structure, which was prepared by employing MEMS lithography and ICP etching process. The characteristic of stress/strain sensitivity was calculated theoretically. Two values of 0.185 pm x kPa(-1) and 18.04 pm x microstrain(-1) were obtained experimentally, which also was verified by theoretical simulations. Comparing with the single-loop micro-cavity structure, its measuring range and stress sensitivity increased by nearly 50.3%, 10.6%, respectively. This paper provides a new method to develop micro-opto-electromechanical system (MOEMS) sensors.

Compact polarization beam splitter for silicon photonic integrated circuits with a 340-nm-thick silicon core layer.

PubMed

Li, Chenlei; Dai, Daoxin

2017-11-01

A polarization beam splitter (PBS) is proposed and realized for silicon photonic integrated circuits with a 340-nm-thick silicon core layer by introducing an asymmetric directional coupler (ADC), which consists of a silicon-on-insulator (SOI) nanowire and a subwavelength grating (SWG) waveguide. The SWG is introduced to provide an optical waveguide which has much higher birefringence than a regular 340-nm-thick SOI nanowire, so that it is possible to make the phase-matching condition satisfied for TE polarization only in the present design when the waveguide dimensions are optimized. Meanwhile, there is a significant phase mismatching for TM polarization automatically. In this way, the present ADC enables strong polarization selectivity to realize a PBS that separates TE and TM polarizations to the cross and through ports, respectively. The realized PBS has a length of ∼2  μm for the coupling region. For the fabricated PBS, the extinction ratio (ER) is 15-30 dB and the excess loss is 0.2-2.6 dB for TE polarization while the ER is 20-27 dB and the excess loss is 0.3-2.8 dB for TM polarization when operating in the wavelength range of 1520-1580 nm.

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

NASA Astrophysics Data System (ADS)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

Chemical potential fluctuations in topological insulator (Bi0.5Sb0.5)2Te3-films visualized by photocurrent spectroscopy

NASA Astrophysics Data System (ADS)

Kastl, Christoph; Seifert, Paul; He, Xiaoyue; Wu, Kehui; Li, Yongqing; Holleitner, Alexander

2015-06-01

We investigate the photocurrent properties of the topological insulator (Bi0.5Sb0.5)2Te3 on SrTiO3-substrates. We find reproducible, submicron photocurrent patterns generated by long-range chemical potential fluctuations, occurring predominantly at the topological insulator/substrate interface. We fabricate nano-plowed constrictions which comprise single potential fluctuations. Hereby, we can quantify the magnitude of the disorder potential to be in the meV range. The results further suggest a dominating photo-thermoelectric current generated in the surface states in such nanoscale constrictions.

Carbon nanotube nanoelectrode arrays

DOEpatents

Ren, Zhifeng; Lin, Yuehe; Yantasee, Wassana; Liu, Guodong; Lu, Fang; Tu, Yi

2008-11-18

The present invention relates to microelectode arrays (MEAs), and more particularly to carbon nanotube nanoelectrode arrays (CNT-NEAs) for chemical and biological sensing, and methods of use. A nanoelectrode array includes a carbon nanotube material comprising an array of substantially linear carbon nanotubes each having a proximal end and a distal end, the proximal end of the carbon nanotubes are attached to a catalyst substrate material so as to form the array with a pre-determined site density, wherein the carbon nanotubes are aligned with respect to one another within the array; an electrically insulating layer on the surface of the carbon nanotube material, whereby the distal end of the carbon nanotubes extend beyond the electrically insulating layer; a second adhesive electrically insulating layer on the surface of the electrically insulating layer, whereby the distal end of the carbon nanotubes extend beyond the second adhesive electrically insulating layer; and a metal wire attached to the catalyst substrate material.

Growth of Low Defect Density Gallium Nitride (GaN) Films on Novel Tantalum Carbide (TaC) Substrates for Improved Device Performance

DTIC Science & Technology

2009-05-01

2 Figure 2. Schematic of a Schottky diode structure (a) grown on an insulating substrate such as sapphire that requires front side...an on-axis substrate at 1000 °C taken (a) at a high magnification and (b) in a region where micropores were observed. ..........8 Figure 5. The 5 x...is useful for vertical high power devices. It can also be made insulating by growing it in a very pure state, which is useful for lateral high

Post-Deployment Reintegration Experiences of AF Personnel: Implications for Scale Development

DTIC Science & Technology

2006-09-01

peuvent également présenter des avantages, notamment une amélioration aux points de vue suivants : confiance en soi , tolérance à l’égard de soi...notamment une amélioration aux points de vue suivants : confiance en soi , tolérance à l’égard de soi, compréhension politique et compétence militaire... confiance en soi , tolérance à l’égard de soi, compréhension politique et compétence militaire. À ce jour, les études sur l’expérience de réinsertion

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

NASA Astrophysics Data System (ADS)

Tsutsumi, Toshiyuki

2018-06-01

The threshold voltage (V th) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the V th fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad V th distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the V th fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

NASA Astrophysics Data System (ADS)

Maulik, Subhodip; Sarkar, Anirban; Basu, Srismrita; Daniels-Race, Theda

2018-05-01

A facile, cost-effective, voltage-controlled, "single-step" method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

Role of geometric parameters in electrical measurements of insulating thin films deposited on a conductive substrate

NASA Astrophysics Data System (ADS)

Kumar, S.; Gerhardt, R. A.

2012-03-01

The effects of film thickness, electrode size and substrate thickness on the impedance parameters of alternating frequency dielectric measurements of insulating thin films deposited on conductive substrates were studied through parametric finite-element simulations. The quasi-static forms of Maxwell's electromagnetic equations in a time harmonic mode were solved using COMSOL Multiphysics® for several types of 2D models (linear and axisymmetric). The full 2D model deals with a configuration in which the impedance is measured between two surface electrodes on top of a film deposited on a conductive substrate. For the simplified 2D models, the conductive substrate is ignored and the two electrodes are placed on the top and bottom of the film. By comparing the full model and the simplified models, approximations and generalizations are deduced. For highly insulating films, such as the case of insulating SiO2 films on a conducting Si substrate, even the simplified models predict accurate capacitance values at all frequencies. However, the edge effects on the capacitance are found to be significant when the film thickness increases and/or the top electrode contact size decreases. The thickness of the substrate affects predominantly the resistive components of the dielectric response while having no significant effect on the capacitive components. Changing the electrode contact size or the film thickness determines the specific values of the measured resistance or capacitance while the material time constant remains the same, and thus this affects the frequency dependence that is able to be detected. This work highlights the importance of keeping in mind the film thickness and electrode contact size for the correct interpretation of the measured dielectric properties of micro/nanoscale structures that are often investigated using nanoscale capacitance measurements.

Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer

NASA Astrophysics Data System (ADS)

Kim, Hyoung Woo; Seok, Ogyun; Moon, Jeong Hyun; Bahng, Wook; Jo, Jungyol

2017-12-01

4H-SiC lateral double implanted metal-oxide-semiconductor field effect transistors (LDIMOSFET) were fabricated on on-axis semi-insulating SiC substrates without using an epi-layer. The LDIMOSFET adopted a current path layer (CPL), which was formed by ion-implantation. The CPL works as a drift region between gate and drain. By using on-axis semi-insulating substrate and optimized CPL parameters, breakdown voltage (BV) of 1093 V and specific on-resistance (R on,sp) of 89.8 mΩ·cm2 were obtained in devices with 20 µm long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm2·V-1·s-1 and the figure-of-merit (BV2/R on,sp) was 13.3 MW/cm2.

Transparent flexible nanogenerator as self-powered sensor for transportation monitoring

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zhong Lin; Hu, Youfan; Lin, Long

2016-06-14

A traffic sensor includes a flexible substrate having a top surface. A piezoelectric structure extends from the first electrode layer. The piezoelectric structure has a top end. An insulating layer is infused into the piezoelectric structure. A first electrode layer is disposed on top of the insulating layer. A second electrode layer is disposed below the flexible substrate. A packaging layer is disposed around the substrate, the first electrode layer, the piezoelectric structure, the insulating layer and the second electrode layer. In a method of sensing a traffic parameter, a piezoelectric nanostructure-based traffic sensor is applied to a roadway. Anmore » electrical event generated by the piezoelectric nanostructure-based traffic sensor in response to a vehicle interacting with the piezoelectric nanostructure-based traffic sensor is detected. The electrical event is correlated with the traffic parameter.« less

Final Technical Report - 300°C Capable Electronics Platform and Temperature Sensor System For Enhanced Geothermal Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Cheng-Po; Shaddock, David; Sandvik, Peter

2012-11-30

A silicon carbide (SiC) based electronic temperature sensor prototype has been demonstrated to operate at 300°C. We showed continuous operation of 1,000 hours with SiC operational amplifier and surface mounted discreet resistors and capacitors on a ceramic circuit board. This feasibility demonstration is a major milestone in the development of high temperature electronics in general and high temperature geothermal exploration and well management tools in particular. SiC technology offers technical advantages that are not found in competing technologies such as silicon-on-insulator (SOI) at high temperatures of 200°C to 300°C and beyond. The SiC integrated circuits and packaging methods can bemore » used in new product introduction by GE Oil and Gas for high temperature down-hole tools. The existing SiC fabrication facility at GE is sufficient to support the quantities currently demanded by the marketplace, and there are other entities in the United States and other countries capable of ramping up SiC technology manufacturing. The ceramic circuit boards are different from traditional organic-based electronics circuit boards, but the fabrication process is compatible with existing ceramic substrate manufacturing. This project has brought high temperature electronics forward, and brings us closer to commercializing tools that will enable and reduce the cost of enhanced geothermal technology to benefit the public in terms of providing clean renewable energy at lower costs.« less

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Almad

2009-01-01

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Broadband microwave photonic fully tunable filter using a single heterogeneously integrated III-V/SOI-microdisk-based phase shifter.

PubMed

Lloret, Juan; Morthier, Geert; Ramos, Francisco; Sales, Salvador; Van Thourhout, Dries; Spuesens, Thijs; Olivier, Nicolas; Fédéli, Jean-Marc; Capmany, José

2012-05-07

A broadband microwave photonic phase shifter based on a single III-V microdisk resonator heterogeneously integrated on and coupled to a nanophotonic silicon-on-insulator waveguide is reported. The phase shift tunability is accomplished by modifying the effective index through carrier injection. A comprehensive semi-analytical model aiming at predicting its behavior is formulated and confirmed by measurements. Quasi-linear and continuously tunable 2π phase shifts at radiofrequencies greater than 18 GHz are experimentally demonstrated. The phase shifter performance is also evaluated when used as a key element in tunable filtering schemes. Distortion-free and wideband filtering responses with a tuning range of ~100% over the free spectral range are obtained.

Wide-range and fast thermally-tunable silicon photonic microring resonators using the junction field effect.

PubMed

Wang, Xiaoxi; Lentine, Anthony; DeRose, Christopher; Starbuck, Andrew L; Trotter, Douglas; Pomerene, Andrew; Mookherjea, Shayan

2016-10-03

Tunable silicon microring resonators with small, integrated micro-heaters which exhibit a junction field effect were made using a conventional silicon-on-insulator (SOI) photonic foundry fabrication process. The design of the resistive tuning section in the microrings included a "pinched" p-n junction, which limited the current at higher voltages and inhibited damage even when driven by a pre-emphasized voltage waveform. Dual-ring filters were studied for both large (>4.9 THz) and small (850 GHz) free-spectral ranges. Thermal red-shifting was demonstrated with microsecond-scale time constants, e.g., a dual-ring filter was tuned over 25 nm in 0.6 μs 10%-90% transition time, and with efficiency of 3.2 μW/GHz.

Athermal Silicon-on-insulator ring resonators by overlaying a polymer cladding on narrowed waveguides.

PubMed

Teng, Jie; Dumon, Pieter; Bogaerts, Wim; Zhang, Hongbo; Jian, Xigao; Han, Xiuyou; Zhao, Mingshan; Morthier, Geert; Baets, Roel

2009-08-17

Athermal silicon ring resonators are experimentally demonstrated by overlaying a polymer cladding on narrowed silicon wires. The ideal width to achieve athermal condition for the TE mode of 220 nm-height SOI waveguides is found to be around 350 nm. After overlaying a polymer layer, the wavelength temperature dependence of the silicon ring resonator is reduced to less than 5 pm/degrees C, almost eleven times less than that of normal silicon waveguides. The optical loss of a 350-nm bent waveguide (with a radius of 15 microm) is extracted from the ring transmission spectrum. The scattering loss is reduced to an acceptable level of about 50 dB/cm after overlaying a polymer cladding. (c) 2009 Optical Society of America

Low-power silicon-organic hybrid (SOH) modulators for advanced modulation formats.

PubMed

Lauermann, M; Palmer, R; Koeber, S; Schindler, P C; Korn, D; Wahlbrink, T; Bolten, J; Waldow, M; Elder, D L; Dalton, L R; Leuthold, J; Freude, W; Koos, C

2014-12-01

We demonstrate silicon-organic hybrid (SOH) electro-optic modulators that enable quadrature phase-shift keying (QPSK) and 16-state quadrature amplitude modulation (16QAM) with high signal quality and record-low energy consumption. SOH integration combines highly efficient electro-optic organic materials with conventional silicon-on-insulator (SOI) slot waveguides, and allows to overcome the intrinsic limitations of silicon as an optical integration platform. We demonstrate QPSK and 16QAM signaling at symbol rates of 28 GBd with peak-to-peak drive voltages of 0.6 V(pp). For the 16QAM experiment at 112 Gbit/s, we measure a bit-error ratio of 5.1 × 10⁻⁵ and a record-low energy consumption of only 19 fJ/bit.

Dewetting of patterned solid films: Towards a predictive modelling approach

NASA Astrophysics Data System (ADS)

Trautmann, M.; Cheynis, F.; Leroy, F.; Curiotto, S.; Pierre-Louis, O.; Müller, P.

2017-06-01

Owing to its ability to produce an assembly of nanoislands with controllable size and locations, the solid state dewetting of patterned films has recently received great attention. A simple Kinetic Monte Carlo model based on two reduced energetic parameters allows one to reproduce experimental observations of the dewetting morphological evolution of patterned films of Si(001) on SiO2 (or SOI for Silicon-on-Insulator) with various pattern designs. Thus, it is now possible to use KMC to drive further experiments and to optimize the pattern shapes to reach a desired dewetted structure. Comparisons between KMC simulations and dewetting experiments, at least for wire-shaped patterns, show that the prevailing dewetting mechanism depends on the wire width.

Design of CMOS compatible and compact, thermally-compensated electro-optic modulator based on off-axis microring resonator for dense wavelength division multiplexing applications.

PubMed

Haldar, Raktim; Banik, Abhik D; Varshney, Shailendra K

2014-09-22

In this work, we propose and demonstrate the performance of silicon-on-insulator (SOI) off-axis microring resonator (MRR) as electro-optic modulator (EOM). Adding an extra off-axis inner-ring in conventional microring structure provides control to compensate thermal effects on EOM. It is shown that dynamically controlled bias-voltage applied to the outer ring has the potency to quell the thermal effects over a wide range of temperature. Thus, besides the appositely biased conventional microring, off-axis inner microring with pre-emphasized electrical input message signal enables our proposed structure suitable for high data-rate dense wavelength division multiplexing scheme of optical communication within a very compact device size.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Multilayered photonic integration on SOI platform using waveguide-based bridge structure

NASA Astrophysics Data System (ADS)

Majumder, Saikat; Chakraborty, Rajib

2018-06-01

A waveguide based structure on silicon on insulator platform is proposed for vertical integration in photonic integrated circuits. The structure consists of two multimode interference couplers connected by a single mode (SM) section which can act as a bridge over any other underlying device. Two more SM sections acts as input and output of the first and second multimode couplers respectively. Potential application of this structure is in multilayered photonic links. It is shown that the efficiency of the structure can be improved by making some design modifications. The entire simulation is done using effective-index based matrix method. The feature size chosen are comparable to waveguides fabricated previously so as to fabricate the proposed structure easily.

Large-scale fabrication of vertically aligned ZnO nanowire arrays

DOEpatents

Wang, Zhong Lin; Hu, Youfan; Zhang, Yan; Xu, Chen; Zhu, Guang

2014-09-09

A generator includes a substrate, a first electrode layer, a dense plurality of vertically-aligned piezoelectric elongated nanostructures, an insulating layer and a second electrode layer. The substrate has a top surface and the first electrode layer is disposed on the top surface of the substrate. The dense plurality of vertically-aligned piezoelectric elongated nanostructures extends from the first electrode layer. Each of the nanostructures has a top end. The insulating layer is disposed on the top ends of the nanostructures. The second electrode layer is disposed on the non-conductive layer and is spaced apart from the nanostructures.

Refractometry studies of the optical properties of polymer films and the development of polymer coated refractive index sensors

NASA Astrophysics Data System (ADS)

Saunders, John Edward

Sensors for real-time monitoring of environmental contaminants are essential for protecting ecosystems and human health. Refractive index sensing is a non-selective technique that can be used to measure almost any analyte. Miniaturized refractive index sensors, such as silicon-on-insulator (SOI) microring resonators are one possible platform, but require coatings selective to the analytes of interest. A homemade prism refractometer is reported and used to characterize the interactions between polymer films and liquid or vapour-phase analytes. A camera was used to capture both Fresnel reflection and total internal reflection within the prism. For thin-films (d = 10 μm - 100 μm), interference fringes were also observed. Fourier analysis of the interferogram allowed for simultaneous extraction of the average refractive index and film thickness with accuracies of Δn = 1-7 x10-4 and Δd < 3-5%. The refractive indices of 29 common organic solvents as well as aqueous solutions of sodium chloride, sucrose, ethylene glycol, glycerol, and dimethylsulfoxide were measured at λ = 1550 nm. These measurements will be useful for future calibrations of near-infrared refractive index sensors. A mathematical model is presented, where the concentration of analyte adsorbed in a film can be calculated from the refractive index and thickness changes during uptake. This model can be used with Fickian diffusion models to measure the diffusion coefficients through the bulk film and at the film-substrate interface. The diffusion of water and other organic solvents into SU-8 epoxy was explored using refractometry and the diffusion coefficient of water into SU-8 is presented. Exposure of soft baked SU-8 films to acetone, acetonitrile and methanol resulted in rapid delamination. The diffusion of volatile organic compound (VOC) vapours into polydimethylsiloxane and polydimethyl-co-polydiphenylsiloxane polymers was also studied using refractometry. Diffusion and partition coefficients are reported for several analytes. As a model system, polydimethyl-co-diphenylsiloxane films were coated onto SOI microring resonators. After the development of data acquisition software, coated devices were exposed to VOCs and the refractive index response was assessed. More studies with other polymers are required to test the viability of this platform for environmental sensing applications.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

ERIC Educational Resources Information Center

Stock, William A.; DiSalvo, Pamela M.

The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Coexisting charge and magnetic orders in the dimer-chain iridate Ba 5AlIr 2O 11

DOE PAGES

Terzic, J.; Wang, J. C.; Ye, Feng; ...

2015-06-29

In this paper, we have synthesized and studied single-crystal Ba 5AlIr 2O 11 that features dimer chains of two inequivalent octahedra occupied by tetravalent Ir 4+(5d 5) and pentavalent Ir 5+(5d 4) ions, respectively. Ba 5AlIr 2O 11 is a Mott insulator that undergoes a subtle structural phase transition near T S=210K and a magnetic transition at T M=4.5K; the latter transition is surprisingly resistant to applied magnetic fields μ oH≤12T but more sensitive to modest applied pressure (dT M/dp ≈ +0.61K/GPa). All results indicate that the phase transition at T S signals an enhanced charge order that induces electricalmore » dipoles and strong dielectric response near T S. It is clear that the strong covalency and spin-orbit interaction (SOI) suppress double exchange in Ir dimers and stabilize a novel magnetic state that is neither S=3/2 nor J=1/2, but rather lies in an “intermediate” regime between these two states. Finally, the novel behavior of Ba 5AlIr 2O 11 therefore provides unique insights into the physics of SOI along with strong covalency in competition with double-exchange interactions of comparable strength.« less

Low-loss adiabatically-tapered high-contrast gratings for slow-wave modulators on SOI

NASA Astrophysics Data System (ADS)

Sciancalepore, Corrado; Hassan, Karim; Ferrotti, Thomas; Harduin, Julie; Duprez, Hélène; Menezo, Sylvie; Ben Bakir, Badhise

2015-02-01

In this communication, we report about the design, fabrication, and testing of Silicon-based photonic integrated circuits (Si-PICs) including low-loss flat-band slow-light high-contrast-gratings (HCGs) waveguides at 1.31 μm. The light slowdown is achieved in 300-nm-thick silicon-on-insulator (SOI) rib waveguides by patterning adiabatically-tapered highcontrast gratings, capable of providing slow-light propagation with extremely low optical losses, back-scattering, and Fabry-Pérot noise. In detail, the one-dimensional (1-D) grating architecture is capable to provide band-edge group indices ng ~ 25, characterized by overall propagation losses equivalent to those of the index-like propagation regime (~ 1-2 dB/cm). Such photonic band-edge slow-light regime at low propagation losses is made possible by the adiabatic apodization of such 1-D HCGs, thus resulting in a win-win approach where light slow-down regime is reached without additional optical losses penalty. As well as that, a tailored apodization optimized via genetic algorithms allows the flattening of slow-light regime over the wavelength window of interest, therefore suiting well needs for group index stability for modulation purposes and non-linear effects generation. In conclusion, such architectures provide key features suitable for power-efficient high-speed modulators in silicon as well as an extremely low-loss building block for non-linear optics (NLO) which is now available in the Si photonics toolbox.

Improved Starting Materials for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Advanced Microelectronics Technologies for Future Small Satellite Systems

NASA Technical Reports Server (NTRS)

Alkalai, Leon

1999-01-01

Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

A novel nano-sensor based on optomechanical crystal cavity

NASA Astrophysics Data System (ADS)

Zhang, Yeping; Ai, Jie; Ma, Jingfang

2017-10-01

Optical devices based on new sensing principle are widely used in biochemical and medical area. Nowadays, mass sensing based on monitoring the frequency shifts induced by added mass in oscillators is a well-known and widely used technique. It is interesting to note that for nanoscience and nanotechnology applications there is a strong demand for very sensitive mass sensors, being the target a sensor for single molecule detection. The desired mass resolution for very few or even single molecule detection, has to be below the femtogram range. Considering the strong interaction between high co-localized optical mode and mechanical mode in optomechanical crystal (OMC) cavities, we investigate OMC splitnanobeam cavities in silicon operating near at the 1550nm to achieve high optomechanical coupling rate and ultra-small motion mass. Theoretical investigations of the optical and mechanical characteristic for the proposed cavity are carried out. By adjusting the structural parameters, the cavity's effective motion mass below 10fg and mechanical frequency exceed 10GHz. The transmission spectrum of the cavity is sensitive to the sample which located on the center of the cavity. We conducted the fabrication and the characterization of this cavity sensor on the silicon-on-insulator (SOI) chip. By using vertical coupling between the tapered fiber and the SOI chip, we measured the transmission spectrum of the cavity, and verify this cavity is promising for ultimate precision mass sensing and detection.

Toward three-dimensional microelectronic systems: directed self-assembly of silicon microcubes via DNA surface functionalization.

PubMed

Lämmerhardt, Nico; Merzsch, Stephan; Ledig, Johannes; Bora, Achyut; Waag, Andreas; Tornow, Marc; Mischnick, Petra

2013-07-02

The huge and intelligent processing power of three-dimensional (3D) biological "processors" like the human brain with clock speeds of only 0.1 kHz is an extremely fascinating property, which is based on a massively parallel interconnect strategy. Artificial silicon microprocessors are 7 orders of magnitude faster. Nevertheless, they do not show any indication of intelligent processing power, mostly due to their very limited interconnectivity. Massively parallel interconnectivity can only be realized in three dimensions. Three-dimensional artificial processors would therefore be at the root of fabricating artificially intelligent systems. A first step in this direction would be the self-assembly of silicon based building blocks into 3D structures. We report on the self-assembly of such building blocks by molecular recognition, and on the electrical characterization of the formed assemblies. First, planar silicon substrates were functionalized with self-assembling monolayers of 3-aminopropyltrimethoxysilane for coupling of oligonucleotides (single stranded DNA) with glutaric aldehyde. The oligonucleotide immobilization was confirmed and quantified by hybridization with fluorescence-labeled complementary oligonucleotides. After the individual processing steps, the samples were analyzed by contact angle measurements, ellipsometry, atomic force microscopy, and fluorescence microscopy. Patterned DNA-functionalized layers were fabricated by microcontact printing (μCP) and photolithography. Silicon microcubes of 3 μm edge length as model objects for first 3D self-assembly experiments were fabricated out of silicon-on-insulator (SOI) wafers by a combination of reactive ion etching (RIE) and selective wet etching. The microcubes were then surface-functionalized using the same protocol as on planar substrates, and their self-assembly was demonstrated both on patterned silicon surfaces (88% correctly placed cubes), and to cube aggregates by complementary DNA functionalization and hybridization. The yield of formed aggregates was found to be about 44%, with a relative fraction of dimers of some 30%. Finally, the electrical properties of the formed dimers were characterized using probe tips inside a scanning electron microscope.

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate.

PubMed

Lee, Jae-Kyu; Choi, Duck-Kyun

2012-07-01

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Flight Performance of a Functionally Gradient Material, TUFI, on Shuttle Orbiter

NASA Technical Reports Server (NTRS)

Leister, Daniel B.; Stewart, David A.; DiFiore, Robert; Tipton, Bradford; Gordon, Michael P.; Arnold, Jim (Technical Monitor)

2001-01-01

TUFI (Toughened Uni-Piece Fibrous Insulation), a functionally gradient material has been successfully flying on the Shuttle Orbiters in several locations on two insulation substrates over the past few years. TUFI is composed of insulation and a gradated surface treatment. The locations it has flown include the base heat shield where damage had been observed after every flight before its application. It was also applied to the body flap, the bottom of the body flap and around selected windows and doors where damage had been observed in the past. A description of the types of processing used including substrates will be presented and its overall performance will be reviewed.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Frequency mixer having ferromagnetic film

DOEpatents

Khitun, Alexander; Roshchin, Igor V.; Galatsis, Kosmas; Bao, Mingqiang; Wang, Kang L.

2016-03-29

A frequency conversion device, which may include a radiofrequency (RF) mixer device, includes a substrate and a ferromagnetic film disposed over a surface of the substrate. An insulator is disposed over the ferromagnetic film and at least one microstrip antenna is disposed over the insulator. The ferromagnetic film provides a non-linear response to the frequency conversion device. The frequency conversion device may be used for signal mixing and amplification. The frequency conversion device may also be used in data encryption applications.

An AlGaN/GaN high-electron-mobility transistor with an AlN sub-buffer layer

NASA Astrophysics Data System (ADS)

Shealy, J. R.; Kaper, V.; Tilak, V.; Prunty, T.; Smart, J. A.; Green, B.; Eastman, L. F.

2002-04-01

The AlGaN/GaN high-electron-mobility transistor requires a thermally conducting, semi-insulating substrate to achieve the best possible microwave performance. The semi-insulating SiC substrate is currently the best choice for this device technology; however, fringing fields which penetrate the GaN buffer layer at pinch-off introduce significant substrate conduction at modest drain bias if channel electrons are not well confined to the nitride structure. The addition of an insulating AlN sub-buffer on the semi-insulating SiC substrate suppresses this parasitic conduction, which results in dramatic improvements in the AlGaN/GaN transistor performance. A pronounced reduction in both the gate-lag and the gate-leakage current are observed for structures with the AlN sub-buffer layer. These structures operate up to 50 V drain bias under drive, corresponding to a peak voltage of 80 V, for a 0.30 µm gate length device. The devices have achieved high-efficiency operation at 10 GHz (>70% power-added efficiency in class AB mode at 15 V drain bias) and the highest output power density observed thus far (11.2 W mm-1). Large-periphery devices (1.5 mm gate width) deliver 10 W (continuous wave) of maximum saturated output power at 10 GHz. The growth, processing, and performance of these devices are briefly reviewed.

Thin film hydrogen sensor

DOEpatents

Lauf, Robert J.; Hoffheins, Barbara S.; Fleming, Pamela H.

1994-01-01

A hydrogen sensor element comprises an essentially inert, electrically-insulating substrate having a thin-film metallization deposited thereon which forms at least two resistors on the substrate. The metallization comprises a layer of Pd or a Pd alloy for sensing hydrogen and an underlying intermediate metal layer for providing enhanced adhesion of the metallization to the substrate. An essentially inert, electrically insulating, hydrogen impermeable passivation layer covers at least one of the resistors, and at least one of the resistors is left uncovered. The difference in electrical resistances of the covered resistor and the uncovered resistor is related to hydrogen concentration in a gas to which the sensor element is exposed.

Thin film hydrogen sensor

DOEpatents

Lauf, R.J.; Hoffheins, B.S.; Fleming, P.H.

1994-11-22

A hydrogen sensor element comprises an essentially inert, electrically-insulating substrate having a thin-film metallization deposited thereon which forms at least two resistors on the substrate. The metallization comprises a layer of Pd or a Pd alloy for sensing hydrogen and an underlying intermediate metal layer for providing enhanced adhesion of the metallization to the substrate. An essentially inert, electrically insulating, hydrogen impermeable passivation layer covers at least one of the resistors, and at least one of the resistors is left uncovered. The difference in electrical resistances of the covered resistor and the uncovered resistor is related to hydrogen concentration in a gas to which the sensor element is exposed. 6 figs.

Ferroelectricity in epitaxial Y-doped HfO2 thin film integrated on Si substrate

NASA Astrophysics Data System (ADS)

Lee, K.; Lee, T. Y.; Yang, S. M.; Lee, D. H.; Park, J.; Chae, S. C.

2018-05-01

We report on the ferroelectricity of a Y-doped HfO2 thin film epitaxially grown on Si substrate, with an yttria-stabilized zirconia buffer layer pre-deposited on the substrate. Piezoresponse force microscopy results show the ferroelectric domain pattern, implying the existence of ferroelectricity in the epitaxial HfO2 film. The epitaxially stabilized HfO2 film in the form of a metal-ferroelectric-insulator-semiconductor structure exhibits ferroelectric hysteresis with a clear ferroelectric switching current in polarization-voltage measurements. The HfO2 thin film also demonstrates ferroelectric retention comparable to that of current perovskite-based metal-ferroelectric-insulator-semiconductor structures.

A water blown urethane insulation for use in cryogenic environments

NASA Technical Reports Server (NTRS)

Blevins, Elana; Sharpe, Jon

1995-01-01

Thermal Protection Systems (TPS) of NASA's Space Shuttle External Tank include polyurethane and polyisocyanurate modified polyurethane foam insulations. These insulations, currently foamed with CFC 11 blowing agent, serve to maintain cryogenic propellant quality, maintain the external tank structural temperature limits, and minimize the formation of ice and frost that could potentially damage the ceramic insulation on the space shuttle orbiter. During flight the external tank insulations are exposed to mechanical, thermal and acoustical stresses. TPS must pass cryogenic flexure and substrate adhesion tests at -253 C, aerothermal and radiant heating tests at fluxes up to approximately 14 kilowatts per square meter, and thermal conductivity tests at cryogenic and elevated temperatures. Due to environmental concerns, the polyurethane insulation industry and the External Tank Project are tasked with replacing CFC 11. The flight qualification of foam insulations employing HCFC 141b as a foaming agent is currently in progress; HCFC 141b blown insulations are scheduled for production implementation in 1995. Realizing that the second generation HCFC blowing agents are an interim solution, the evaluation of third generation blowing agents with zero ozone depletion potential is underway. NASA's TPS Materials Research Laboratory is evaluating third generation blowing agents in cryogenic insulations for the External Tank; one option being investigated is the use of water as a foaming agent. A dimensionally stable insulation with low friability, good adhesion to cryogenic substrates, and acceptable thermal conductivity has been developed with low viscosity materials that are easily processed in molding applications. The development criteria, statistical experimental approach, and resulting foam properties will be presented.

Method of forming electrical pathways in indium-tin-oxide coatings

DOEpatents

Haynes, T.E.

1996-12-03

An electrical device includes a substrate having an ITO coating thereon, a portion of which is conductive and defines at least one electrical pathway, and the balance of the ITO being insulative. The device is made by the following general steps: a. providing a substrate having a conductive ITO coating on at least one surface thereof; b. rendering a preselected portion of the coating of conductive ITO insulative, leaving the remaining portion of conductive ITO as at least one electrical pathway. 8 figs.

Method of forming electrical pathways in indium-tin-oxide coatings

DOEpatents

Haynes, T.E.

1997-03-04

An electrical device includes a substrate having an ITO coating thereon, a portion of which is conductive and defines at least one electrical pathway, the balance of the ITO being insulative. The device is made by the following general steps: (a) providing a substrate having a conductive ITO coating on at least one surface thereof; (b) rendering a preselected portion of the coating of conductive ITO insulative, leaving the remaining portion of conductive ITO as at least one electrical pathway. 8 figs.

Method of forming electrical pathways in indium-tin-oxide coatings

DOEpatents

Haynes, Tony E.

1996-01-01

An electrical device includes a substrate having an ITO coating thereon, a portion of which is conductive and defines at least one electrical pathway, and the balance of the ITO being insulative. The device is made by the following general steps: a. providing a substrate having a conductive ITO coating on at least one surface thereof; b. rendering a preselected portion of the coating of conductive ITO insulative, leaving the remaining portion of conductive ITO as at least one electrical pathway.

Method of forming electrical pathways in indium-tin-oxide coatings

DOEpatents

Haynes, Tony E.

1997-01-01

An electrical device includes a substrate having an ITO coating thereon, a portion of which is conductive and defines at least one electrical pathway, and the balance of the ITO being insulative. The device is made by the following general steps: a. providing a substrate having a conductive ITO coating on at least one surface thereof; b. rendering a preselected portion of the coating of conductive ITO insulative, leaving the remaining portion of conductive ITO as at least one electrical pathway.

Development of method to characterize emissions from spray polyurethane foam insulation

EPA Science Inventory

This presentation updates symposium participants re EPA progress towards development of SPF insulation emissions characterization methods. The presentation highlights evaluation of experiments investigating emissions after application of SPF to substrates in micro chambers and i...

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.;

The USNA MIDN Microdosimeter Instrument

NASA Technical Reports Server (NTRS)

Pisacane, V. L.; Ziegler, J. F.; Nelson, M. E.; Dolecek, Q.; Heyne, J.; Veade, T.; Rosenfeld, A. B.; Cucinotta, F. A.; Zaider, M.; Dicello, J. F.

2006-01-01

This paper describes the MIcroDosimetry iNstrument (MIDN) mission now under development at the United States Naval Academy. The instrument is manifested to fly on the MidSTAR-1 spacecraft, which is the second spacecraft to be developed and launched by the Academy s faculty and midshipmen. Launch is scheduled for 1 September 2006 on an ATLAS-5 launch vehicle. MIDN is a rugged, portable, low power, low mass, solid-state microdosimeter designed to measure in real time the energy distributions of energy deposited by radiation in microscopic volumes. The MIDN microdosimeter sensor is a reverse-biased silicon p-n junction array in a Silicon-On-Insulator (SOI) configuration. Microdosimetric frequency distributions as a function of lineal energies determine the radiation quality factors in support of radiation risk estimation to humans.

The modeling of MMI structures for signal processing applications

NASA Astrophysics Data System (ADS)

Le, Thanh Trung; Cahill, Laurence W.

2008-02-01

Microring resonators are promising candidates for photonic signal processing applications. However, almost all resonators that have been reported so far use directional couplers or 2×2 multimode interference (MMI) couplers as the coupling element between the ring and the bus waveguides. In this paper, instead of using 2×2 couplers, novel structures for microring resonators based on 3×3 MMI couplers are proposed. The characteristics of the device are derived using the modal propagation method. The device parameters are optimized by using numerical methods. Optical switches and filters using Silicon on Insulator (SOI) then have been designed and analyzed. This device can become a new basic component for further applications in optical signal processing. The paper concludes with some further examples of photonic signal processing circuits based on MMI couplers.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Four-port coupled channel-guide device based on 2D photonic crystal structure

NASA Astrophysics Data System (ADS)

Camargo, Edilson A.; Chong, Harold M. H.; De La Rue, Richard M.

2004-12-01

We have fabricated and measured a four-port coupled channel-waveguide device using W1 channel waveguides oriented along ΓK directions in a two-dimensional (2D) hole-based planar photonic crystal (PhC) based on silicon-on-insulator (SOI) waveguide material, at operation wavelengths around 1550 nm. 2D FDTD simulations and experimental results are shown and compared. The structure has been designed using a mode conversion approach, combined with coupled-mode concepts. The overall length of the photonic crystal structure is typically about 39 μm and the structure has been fabricated using a combination of direct-write electron-beam lithography (EBL) and dry-etch processing. Devices were measured using a tunable laser with end-fire coupling into the planar structure.

Label-free electrical detection of pyrophosphate generated from DNA polymerase reactions on field-effect devices.

PubMed

Credo, Grace M; Su, Xing; Wu, Kai; Elibol, Oguz H; Liu, David J; Reddy, Bobby; Tsai, Ta-Wei; Dorvel, Brian R; Daniels, Jonathan S; Bashir, Rashid; Varma, Madoo

2012-03-21

We introduce a label-free approach for sensing polymerase reactions on deoxyribonucleic acid (DNA) using a chelator-modified silicon-on-insulator field-effect transistor (SOI-FET) that exhibits selective and reversible electrical response to pyrophosphate anions. The chemical modification of the sensor surface was designed to include rolling-circle amplification (RCA) DNA colonies for locally enhanced pyrophosphate (PPi) signal generation and sensors with immobilized chelators for capture and surface-sensitive detection of diffusible reaction by-products. While detecting arrays of enzymatic base incorporation reactions is typically accomplished using optical fluorescence or chemiluminescence techniques, our results suggest that it is possible to develop scalable and portable PPi-specific sensors and platforms for broad biomedical applications such as DNA sequencing and microbe detection using surface-sensitive electrical readout techniques.

Single-crystal-like GdNdO{sub x} thin films on silicon substrates by magnetron sputtering and high-temperature annealing for crystal seed layer application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Ziwei; Xiao, Lei; Liang, Renrong, E-mail: wang-j@tsinghua.edu.cn, E-mail: liangrr@tsinghua.edu.cn

2016-06-15

Single-crystal-like rare earth oxide thin films on silicon (Si) substrates were fabricated by magnetron sputtering and high-temperature annealing processes. A 30-nm-thick high-quality GdNdO{sub x} (GNO) film was deposited using a high-temperature sputtering process at 500°C. A Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} mixture was used as the sputtering target, in which the proportions of Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} were controlled to make the GNO’s lattice parameter match that of the Si substrate. To further improve the quality of the GNO film, a post-deposition annealing process was performed at a temperature of 1000°C. The GNO films exhibitedmore » a strong preferred orientation on the Si substrate. In addition, an Al/GNO/Si capacitor was fabricated to evaluate the dielectric constant and leakage current of the GNO films. It was determined that the single-crystal-like GNO films on the Si substrates have potential for use as an insulator layer for semiconductor-on-insulator and semiconductor/insulator multilayer applications.« less

Concurrent rib and pelvic fractures as an indicator of solid abdominal organ injury.

PubMed

Al-Hassani, Ammar; Afifi, Ibrahim; Abdelrahman, Husham; El-Menyar, Ayman; Almadani, Ammar; Recicar, Jan; Al-Thani, Hassan; Maull, Kimball; Latifi, Rifat

2013-01-01

To study the association of solid organ injuries (SOIs) in patients with concurrent rib and pelvic fractures. Retrospective analysis of prospectively collected data from November 2007 to May 2010. Patients' demographics, mechanism of injury, Injury severity scoring, pelvic fracture, and SOIs were analyzed. Patients with SOIs were compared in rib fractures with and without pelvic fracture. The study included 829 patients (460 with rib fractures ± pelvic fracture and 369 with pelvic fracture alone) with mean age of 35 ± 12.7 years. Motor vehicle crashes (45%) and falls from height (30%) were the most common mechanism of injury. The overall incidence of SOIs in this study was 22% (185/829). Further, 15% of patient with rib fractures had associated pelvic fracture. SOI was predominant in patients with concurrent rib fracture and pelvic fracture compared to ribs or pelvic fractures alone (42% vs. 26% vs. 15%, respectively, p = 0.02). Concurrent multiple rib fractures and pelvic fracture increases the risk of SOI compared to either group alone. Lower RFs and pelvic fracture had higher association for SOI and could be used as an early indicator of the presence of SOIs. Copyright © 2013 Surgical Associates Ltd. Published by Elsevier Ltd. All rights reserved.

Metallization of electronic insulators

DOEpatents

Gottesfeld, Shimshon; Uribe, Francisco A.

1994-01-01

An electroplated element is formed to include an insulating substrate, a conducting polymer polymerized in situ on the substrate, and a metal layer deposited on the conducting polymer. In one application a circuit board is formed by polymerizing pyrrole on an epoxy-fiberglass substrate in a single step process and then electrodepositing a metal over the resulting polypyrrole polymer. No chemical deposition of the metal is required prior to electroplating and the resulting layer of substrate-polymer-metal has excellent adhesion characteristics. The metal deposition is surprisingly smooth and uniform over the relatively high resistance film of polypyrrole. A continuous manufacturing process is obtained by filtering the solution between successive substrates to remove polymer formed in the solution, by maintaining the solution oxidizing potential within selected limits, and by adding a strong oxidant, such as KMnO.sub.4 at periodic intervals to maintain a low sheet resistivity in the resulting conducting polymer film.

Photonic molecules for application in silicon-on-insulator optical sensors

NASA Astrophysics Data System (ADS)

Barea, Luis A. M.; Souza, Mario C. M. M.; Moras, Andre L.; Catellan, Alvaro R. G.; Cirino, Giuseppe A.; Von Zuben, Antonio A. G.; Bassani, Jose W. M.; Frateschi, Newton C.

2018-02-01

Optical sensors based on integrated photonics have experienced impressive advancements in the past few decades and represent one of the main sensing solutions in many areas including environmental sensing and medical diagnostics. In this context, optical microcavities are extensively employed as refractive index (RI) sensors, providing sharp optical resonances that allow the detection of very small variations in the surrounding RI. With increased sensitivity, however, the device is subjected to environmental perturbations that can also change the RI, such as temperature variations, and therefore compromise their reliability. In this work, we present the concept and experimental realization of a photonic sensor based on coupled microcavities or Photonic Molecules (PM) in which only one cavity is exposed to the sensing solution, allowing a differential measurement of the RI change. The device consists of an exposed 5-μm radius microdisk resonator coupled to an external clad microring resonator fabricated on silicon-on-insulator (SOI) platform. This design allows good sensitivity (26 nm/RIU) for transverse electrical mode (TE-mode) in a compact footprint (40 × 40 μm2), representing a good solution for real-life applications in which measurement conditions are not easily controllable.

A Study of the Crystal Structure of Co40Fe40B20 Epitaxial Films on a Bi2Te3 Topological Insulator

NASA Astrophysics Data System (ADS)

Kaveev, A. K.; Suturin, S. M.; Sokolov, N. S.; Kokh, K. A.; Tereshchenko, O. E.

2018-03-01

Laser molecular-beam epitaxy has been used to form Co40Fe40B20 layers on Bi2Te3 topological insulator substrates, and their growth conditions have been studied. The possibility of growing epitaxial ferromagnetic layers on the surface of a topological insulator is demonstrated for the first time. The CoFeB layers have a body-centered cubic crystal structure with the (111) crystal plane parallel to the (0001) plane of Bi2Te3. 3D mapping in the reciprocal space of high-energy electron-diffraction patterns made it possible to determine the epitaxial relationships between the film and the substrate.

Orientation-adjusted anomalous insulator-metal transition in NdNiO3/LaMnO3 bilayers

NASA Astrophysics Data System (ADS)

Pan, S. Y.; Shi, L.; Zhao, J. Y.; Zhou, S. M.; Xu, X. M.

2018-04-01

NdNiO3/LaMnO3 (NNO/LMO) bilayers were epitaxially grown on SrTiO3 (STO) substrates with different orientations by the polymer-assisted deposition technique. A well crystallization quality of the bilayers is confirmed by X-ray diffraction. Two consecutive transitions, an anomalous insulator-metal transition at ˜100 K followed by the typical metal-insulator transition at ˜171 K, are observed in the (001)-oriented NNO/LMO/STO bilayer. The anomalous insulator-metal transition temperature increases to 142 K for the (111)-oriented NNO/LMO/STO bilayer. Meanwhile, the magnetic properties of the NNO/LMO bilayers show an obvious difference with [100] and [111] orientations. Considering the different strain directions and the related oxygen octahedral distortion/rotation, it is suggested that the magnetic changes and the low-temperature anomalous insulator-metal transition in the NNO/LMO bilayers are attributed to the strong interlayer exchange coupling and charge transfer adjusted by the substrate orientation, which can be an effective technique to tune the properties of transition-metal oxide films.

Micromachined peristaltic pump

NASA Technical Reports Server (NTRS)

Hartley, Frank T. (Inventor)

1998-01-01

A micromachined pump including a channel formed in a semiconductor substrate by conventional processes such as chemical etching. A number of insulating barriers are established in the substrate parallel to one another and transverse to the channel. The barriers separate a series of electrically conductive strips. An overlying flexible conductive membrane is applied over the channel and conductive strips with an insulating layer separating the conductive strips from the conductive membrane. Application of a sequential voltage to the series of strips pulls the membrane into the channel portion of each successive strip to achieve a pumping action. A particularly desirable arrangement employs a micromachined push-pull dual channel cavity employing two substrates with a single membrane sandwiched between them.

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

NASA Astrophysics Data System (ADS)

Patil, Ganesh C.; Bonge, Vijaysinh H.; Malode, Mayur M.; Jain, Rahul G.

2016-02-01

In this paper, δ-doped partially insulated junctionless transistor (δ-Pi-OXJLT) has been proposed which shows that, employing highly doped δ-region below the channel not only reduces the off-state leakage current (IOFF) and short channel effects (SCEs) but also reduce the requirements of scaling channel thickness of junctionless transistor (JLT). The comparative analysis of digital and analog circuit performance of proposed δ-Pi-OXJLT, bulk planar (BP) JLT and silicon-on-insulator (SOI) JLT has also been carried out. The digital parameters analyzed in this work are, on-state drive current (ION), IOFF, ION/IOFF ratio, static power dissipation (PSTAT) whereas the analog parameters analyzed includes, transconductance (GM), transconductance generation factor (GM/IDS), intrinsic gain (GMRO) and cut-off frequency (fT) of the devices. In addition, scaling behavior of the devices is studied for various channel lengths by using the parameters such as drain induced barrier lowering (DIBL) and sub-threshold swing (SS). It has been found that, the proposed δ-Pi-OXJLT shows significant reduction in IOFF, DIBL and SS over BPJLT and SOIJLT devices. Further, ION and ION/IOFF ratio in the case of proposed δ-Pi-OXJLT also improves over the BPJLT device. Furthermore, the improvement in analog figures of merit, GM, GM/IDS, GMRO and fT in the case of proposed δ-Pi-OXJLT clearly shows that the proposed δ-Pi-OXJLT is the promising device for mixed signal integrated circuits.

Metal-capped silicon organic micro-ring electro-optical modulator (Conference Presentation)

NASA Astrophysics Data System (ADS)

Zaki, Aya O.; Kirah, Khaled A.; Swillam, Mohamed A.

2017-02-01

An ultra-compact hybrid plasmonic waveguide ring electro-optical modulator is designed to be easily fabricated on silicon on insulator (SOI) substrates using standard silicon photonics technology. The proposed waveguide is based on a buried standard silicon waveguide of height 220 nm topped with polymer and metal. The key advantage of this novel design is that only the silicon layer of the waveguide is structured as a coupled ring resonator. Then, the device is covered with electro-optical polymer and metal in post processes with no need for lithography or accurate mask alignment techniques. The simple fabrication method imposes many design challenges to obtain a resonator of reasonable loaded quality factor and high extinction ratio. Here, the performance of the resonator is optimized in the telecom wavelength range around 1550 nm using 3D FDTD simulations. The design of the coupling junction between the access waveguide and the tightly bent ring is thoroughly studied. The extension of the metal over the coupling region is exploited to make the critical dimension of the design geometry at least 2.5 times larger than conventional plasmonic resonators and the design is thus more robust. In this paper, we demonstrate an electro-optical modulator that offers an insertion loss < 1 dB, a modulation depth of 12 dB for an applied peak to peak voltage of only 2 V and energy consumption of 1.74 fJ/bit. The performance is superior to previously reported hybrid plasmonic ring resonator based modulators while the design shows robustness and low fabrication cost.

New MOEMS based systems appropriate for spectroscopic investigations on agricultural growth and perishable food conditions

NASA Astrophysics Data System (ADS)

Grueger, Heinrich; Schenk, Harald; Heberer, Andreas; Zimmer, Fabian; Scherff, Werner; Kenda, Andreas; Frank, Albert

2005-11-01

Further optimization of the agricultural growth process and quality control of perishable food which can be fruits and vegetables as well as every kind of meat or milk product requires new approaches for the sensitive front end. One possibility is reflectance or fluorescence spectroscopy in a wide wavelength range. By now broad usage is hindered by costs, size and performance of existing systems. MOEMS scanning gratings for spectrometers and translational mirrors for Fourier Transform spectroscopy enable small robust systems working in a range from 200nm to 5μm. Both types use digital signal processors (DSPs) capable to compute the spectra and execute complex evaluation and decision algorithms. The MOEMS chips are realized by anisotropic etching of a silicon on insulator (SOI) substrate. First the backside silicon and buried oxide is removed by a wet process then the front side structure is realized by dry etching. Depending on the bearing springs a silicon plate up to 3 x 3 mm2 wide and typically 30μm thick can be driven resonantly to rotational or translational movement. Combined with additional optical components and appropriate detectors handheld Czerny-Turner or Fourier Transform spectrometers have been realized and tested. Results of first measurements of reflection spectroscopy on model substances have been performed with both system types in the NIR range. Measurements on real objects like tomatoes or apples are intended for a wider wavelength range. Future systems may contain displays and light sources as well as data storage cards or additional interfaces.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

NASA Astrophysics Data System (ADS)

Guichard, Alex Richard

Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores. Investigation of the non-radiative Auger recombination (AR) process suggests that for high carrier densities in excess of 1019 cm-3, the AR lifetime is about 80 ns and decreases with increasing carrier density. This SiNW AR lifetime is slower than the AR process in Si nanocrystals at similar carrier densities, but faster than the radiative process. I also study the light emission and absorption properties of single SiNWs patterned on Silicon-on-insulator (SOI) substrates and find that a large fraction of NWs is optically dead. Moreover, the active, light-emitting nanostructures exhibit PL blinking, a mechanism often seen for individual nanostructure light emitters. These results are essential to evaluating Si nanostructures as a feasible gain or lasing medium. A second potential application for SiNWs is as a building block for low-cost, Si-based photovoltaics (PV). The market for thin-film PV, particularly organic thin-film PV, exists because it offers potential lower cost solutions for solar power versus bulk Si-based PV. However, many thin film technologies, while possessing superior optical absorption properties compared to Si, suffer from poor electronic transport properties. Here, I present a new Si-based PV design that combines the desirable optical properties of highly absorptive organic molecules and the high-mobility electronic properties of crystalline Si. This synergy is achieved by exploiting efficient Forster energy transfer from the light absorbing organic to SiNWs that enable current extraction. The energy transfer radius of a particular dye and bulk Si is found to be roughly 4 nm. Spectroscopic photocurrent experiments were performed on unpatterned SOI wafers as well as SiNWs patterned in SOI substrates and a significant photocurrent increase was seen in samples coated with organics versus uncoated samples. The photocurrent increase is seen in the wavelength range of the dye's absorption band, suggesting absorption of the dye and subsequent energy transfer to the Si plays a role. These results could pave the way for new low-cost, Si-based solar cell designs that leverage the strengths of the Si PV and microelectronics industries.

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

NASA Astrophysics Data System (ADS)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS circuits with 500 nm thick Si, operating around 3.8 µm wavelength. Results on facet coupling and sub-wavelength engineered grating coupler solutions in the mid-IR regime will be compared.

Integrated Optics for Planar imaging and Optical Signal Processing

NASA Astrophysics Data System (ADS)

Song, Qi

Silicon photonics is a subject of growing interest with the potential of delivering planar electro-optical devices with chip scale integration. Silicon-on-insulator (SOI) technology has provided a marvelous platform for photonics industry because of its advantages in integration capability in CMOS circuit and countless nonlinearity applications in optical signal processing. This thesis is focused on the investigation of planar imaging techniques on SOI platform and potential applications in ultra-fast optical signal processing. In the first part, a general review and background introduction about integrated photonics circuit and planar imaging technique are provided. In chapter 2, planar imaging platform is realized by a silicon photodiode on SOI chip. Silicon photodiode on waveguide provides a high numerical aperture for an imaging transceiver pixel. An erbium doped Y2O3 particle is excited by 1550nm Laser and the fluorescent image is obtained with assistance of the scanning system. Fluorescence image is reconstructed by using image de-convolution technique. Under photovoltaic mode, we use an on-chip photodiode and an external PIN photodiode to realize similar resolution as 5μm. In chapter 3, a time stretching technique is developed to a spatial domain to realize a 2D imaging system as an ultrafast imaging tool. The system is evaluated based on theoretical calculation. The experimental results are shown for a verification of system capability to imaging a micron size particle or a finger print. Meanwhile, dynamic information for a moving object is also achieved by correlation algorithm. In chapter 4, the optical leaky wave antenna based on SOI waveguide has been utilized for imaging applications and extensive numerical studied has been conducted. and the theoretical explanation is supported by leaky wave theory. The highly directive radiation has been obtained from the broadside with 15.7 dB directivity and a 3dB beam width of ΔØ 3dB ≈ 1.65° in free space environment when β -1 = 2.409 × 105/m, α=4.576 ×103/m. At the end, electronics beam-steering principle has been studied and the comprehensive model has been built to explain carrier transformation behavior in a PIN junction as individual silicon perturbation. Results show that 1019/cm3 is possible obtained with electron injection mechanism. Although the radiation modulation based on carrier injection of 1019/cm3 gives 0.5dB variation, resonant structure, such as Fabry Perrot Cavity, can be integrated with LOWAs to enhance modulation effect.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.

Insulators obtained by electron cyclotron resonance plasmas on Si or GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Diniz, J.A.; Doi, I.; Swart, J.W

2003-03-15

Silicon oxynitride (SiO{sub x}N{sub y}) and nitride (SiN{sub x}) insulators have been deposited or grown (with or without silane in the gas mixture, respectively) by electron cyclotron resonance (ECR) plasmas on Si and/or GaAs substrates at room temperature (20 deg. C) and low pressures (up to 10 mTorr). Chemical bonding characteristics of the SiO{sub x}N{sub y} and SiN{sub x} films were evaluated using Fourier transform infrared spectrometry (FTIR). The profile measurements determined the film thickness, the deposition (or oxidation) rate and the etch rates in buffered HF (BHF). The refractive indexes and the thicknesses were determined by ellipsometry. The effectivemore » interface charge densities were determined by capacitance-voltage (C-V) measurements. With these processes and analyses, different films were obtained and optimized. Suitable gate insulators for metal-insulator-semiconductor (MIS) devices with low interface charge densities were developed: (a) SiN{sub x} films deposited by ECR-chemical vapor deposition (ECR-PECVD) on GaAs substrates; (b) SiO{sub x}N{sub y} insulators obtained by low-energy molecular nitrogen ion ({sup 28}N{sub 2}{sup +}) implantation (energy of 5 keV and dose of 1x10{sup 15}/cm{sup 2}) in Si substrates prior to high-density O{sub 2} ECR plasma oxidation; and (c) SiO{sub x}N{sub y} insulators grown (without silane in the gas mixture) by O{sub 2}/N{sub 2}/Ar ECR plasma 'oxynitridation'. Furthermore, some SiN{sub x} films also present very good masking characteristics for local oxidation of silicon process.« less

Decadal variations in the strength of ENSO teleconnections with precipitation in the western United States

USGS Publications Warehouse

McCabe, G.J.; Dettinger, M.D.

1999-01-01

Changing patterns of correlations between the historical average June-November Southern Oscillation Index (SOI) and October-March precipitation totals for 84 climate divisions in the western US indicate a large amount of variability in SOI/precipitation relations on decadal time scales. Correlations of western US precipitation with SOI and other indices of tropical El Nino-Southern Oscillation (ENSO) processes were much weaker from 1920 to 1950 than during recent decades. This variability in teleconnections is associated with the character of tropical air-sea interactions as indexed by the number of out-of-phase SOI/tropical sea surface temperature (SST) episodes, and with decadal variability in the North Pacific Ocean as indexed by the Pacific Decadal Oscillation (PDO). ENSO teleconnections with precipitation in the western US are strong when SOI and NINO3 are out-of-phase and PDO is negative. ENSO teleconnections are weak when SOI and NINO3 are weakly correlated and PDO is positive. Decadal modes of tropical and North Pacific Ocean climate variability are important indicators of periods when ENSO indices, like SOI, can be used as reliable predictors of winter precipitation in the US.

Soft-light overhead illumination systems improve laparoscopic task performance.

PubMed

Takai, Akihiro; Takada, Yasutsugu; Motomura, Hideki; Teramukai, Satoshi

2014-02-01

The aim of this study was to evaluate the impact of attached shadow cues for laparoscopic task performance. We developed a soft-light overhead illumination system (SOIS) that produced attached shadows on objects. We compared results using the SOIS with those using a conventional illumination system with regard to laparoscopic experience and laparoscope-to-target distances (LTDs). Forty-two medical students and 23 surgeons participated in the study. A peg transfer task (LTD, 120 mm) for students and surgeons, and a suture removal task (LTD, 30 mm) for students were performed. Illumination systems were randomly assigned to each task. Endpoints were: total number of peg transfers; percentage of peg-dropping errors; and total execution time for suture removal. After the task, participants filled out a questionnaire on their preference for a particular illumination system. Total number of peg transfers was greater with the SOIS for both students and surgeons. Percentage of peg-dropping errors for surgeons was lower with the SOIS. Total execution time for suture removal was shorter with the SOIS. Forty-five participants (69% in total) evaluated the SOIS for easier task performance. The present results confirm that the SOIS improves laparoscopic task performance, regardless of previous laparoscopic experience or LTD.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshizumi, K.; Sasaki, A.; Kohda, M.

We demonstrate gate-controlled switching between persistent spin helix (PSH) state and inverse PSH state, which are detected by quantum interference effect on magneto-conductance. These special symmetric spin states showing weak localization effect give rise to a long spin coherence when the strength of Rashba spin-orbit interaction (SOI) is close to that of Dresselhaus SOI. Furthermore, in the middle of two persistent spin helix states, where the Rashba SOI can be negligible, the bulk Dresselhaus SOI parameter in a modulation doped InGaAs/InAlAs quantum well is determined.

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

PubMed

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

Asymptomatic Hepadnaviral Persistence and Its Consequences in the Woodchuck Model of Occult Hepatitis B Virus Infection

PubMed Central

Mulrooney-Cousins, Patricia M.; Michalak, Tomasz I.

2015-01-01

Woodchuck hepatitis virus (WHV) is molecularly and pathogenically closely related to hepatitis B virus (HBV). Both viruses display tropism towards hepatocytes and cells of the immune system and cause similar liver pathology, where acute hepatitis can progress to chronic hepatitis and to hepatocellular carcinoma (HCC). Two forms of occult hepadnaviral persistence were identified in the woodchuck-WHV model: secondary occult infection (SOI) and primary occult infection (POI). SOI occurs after resolution of a serologically apparent infection with hepatitis or after subclinical serologically evident virus exposure. POI is caused by small amounts of virus and progresses without serological infection markers, but the virus genome and its replication are detectable in the immune system and with time in the liver. SOI can be accompanied by minimal hepatitis, while the hallmark of POI is normal liver morphology. Nonetheless, HCC develops in about 20% of animals with SOI or POI within 3 to 5 years. The virus persists throughout the lifespan in both SOI and POI at serum levels rarely greater than 100 copies/mL, causes hepatitis and HCC when concentrated and administered to virus-naïve woodchucks. SOI is accompanied by virus-specific T and B cell immune responses, while only virus-specific T cells are detected in POI. SOI coincides with protection against reinfection, while POI does not and hepatitis develops after challenge with liver pathogenic doses >1000 virions. Both SOI and POI are associated with virus DNA integration into the liver and the immune system genomes. Overall, SOI and POI are two distinct forms of silent hepadnaviral persistence that share common characteristics. Here, we review findings from the woodchuck model and discuss the relevant observations made in human occult HBV infection (OBI). PMID:26623268

Asymptomatic Hepadnaviral Persistence and Its Consequences in the Woodchuck Model of Occult Hepatitis B Virus Infection.

PubMed

Mulrooney-Cousins, Patricia M; Michalak, Tomasz I

2015-09-28

Woodchuck hepatitis virus (WHV) is molecularly and pathogenically closely related to hepatitis B virus (HBV). Both viruses display tropism towards hepatocytes and cells of the immune system and cause similar liver pathology, where acute hepatitis can progress to chronic hepatitis and to hepatocellular carcinoma (HCC). Two forms of occult hepadnaviral persistence were identified in the woodchuck-WHV model: secondary occult infection (SOI) and primary occult infection (POI). SOI occurs after resolution of a serologically apparent infection with hepatitis or after subclinical serologically evident virus exposure. POI is caused by small amounts of virus and progresses without serological infection markers, but the virus genome and its replication are detectable in the immune system and with time in the liver. SOI can be accompanied by minimal hepatitis, while the hallmark of POI is normal liver morphology. Nonetheless, HCC develops in about 20% of animals with SOI or POI within 3 to 5 years. The virus persists throughout the lifespan in both SOI and POI at serum levels rarely greater than 100 copies/mL, causes hepatitis and HCC when concentrated and administered to virus-naïve woodchucks. SOI is accompanied by virus-specific T and B cell immune responses, while only virus-specific T cells are detected in POI. SOI coincides with protection against reinfection, while POI does not and hepatitis develops after challenge with liver pathogenic doses >1000 virions. Both SOI and POI are associated with virus DNA integration into the liver and the immune system genomes. Overall, SOI and POI are two distinct forms of silent hepadnaviral persistence that share common characteristics. Here, we review findings from the woodchuck model and discuss the relevant observations made in human occult HBV infection (OBI).

ZnO thin-film transistors with a polymeric gate insulator built on a polyethersulfone substrate

NASA Astrophysics Data System (ADS)

Hyung, Gun Woo; Park, Jaehoon; Koo, Ja Ryong; Choi, Kyung Min; Kwon, Sang Jik; Cho, Eou Sik; Kim, Yong Seog; Kim, Young Kwan

2012-03-01

Zinc oxide (ZnO) thin-film transistors (TFTs) with a cross-linked poly(vinyl alcohol) (c-PVA) insulator are fabricated on a polyethersulfone substrate. The ZnO film, formed by atomic layer deposition, shows a polycrystalline hexagonal structure with a band gap energy of about 3.37 eV. The fabricated ZnO TFT exhibits a field-effect mobility of 0.38 cm2/Vs and a threshold voltage of 0.2 V. The hysteresis of the device is mainly caused by trapped electrons at the c-PVA/ZnO interface, whereas the positive threshold voltage shift occurs as a consequence of constant positive gate bias stress after 5000 s due to an electron injection from the ZnO film into the c-PVA insulator.

Wide-Range Temperature Sensors with High-Level Pulse Train Output

NASA Technical Reports Server (NTRS)

Hammoud, Ahmad; Patterson, Richard L.

2009-01-01

Two types of temperature sensors have been developed for wide-range temperature applications. The two sensors measure temperature in the range of -190 to +200 C and utilize a thin-film platinum RTD (resistance temperature detector) as the temperature-sensing element. Other parts used in the fabrication of these sensors include NPO (negative-positive- zero) type ceramic capacitors for timing, thermally-stable film or wirewound resistors, and high-temperature circuit boards and solder. The first type of temperature sensor is a relaxation oscillator circuit using an SOI (silicon-on-insulator) operational amplifier as a comparator. The output is a pulse train with a period that is roughly proportional to the temperature being measured. The voltage level of the pulse train is high-level, for example 10 V. The high-level output makes the sensor less sensitive to noise or electromagnetic interference. The output can be read by a frequency or period meter and then converted into a temperature reading. The second type of temperature sensor is made up of various types of multivibrator circuits using an SOI type 555 timer and the passive components mentioned above. Three configurations have been developed that were based on the technique of charging and discharging a capacitor through a resistive element to create a train of pulses governed by the capacitor-resistor time constant. Both types of sensors, which operated successfully over the wide temperature range, have potential use in extreme temperature environments including jet engines and space exploration missions.

Band gap characterization of ternary BBi1-xNx (0≤x≤1) alloys using modified Becke-Johnson (mBJ) potential

NASA Astrophysics Data System (ADS)

Yalcin, Battal G.

2015-04-01

The semi-local Becke-Johnson (BJ) exchange-correlation potential and its modified form proposed by Tran and Blaha have attracted a lot of interest recently because of the surprisingly accurate band gaps they can deliver for many semiconductors and insulators (e.g., sp semiconductors, noble-gas solids, and transition-metal oxides). The structural and electronic properties of ternary alloys BBi1-xNx (0≤x≤1) in zinc-blende phase have been reported in this study. The results of the studied binary compounds (BN and BBi) and ternary alloys BBi1-xNx structures are presented by means of density functional theory. The exchange and correlation effects are taken into account by using the generalized gradient approximation (GGA) functional of Wu and Cohen (WC) which is an improved form of the most popular Perdew-Burke-Ernzerhof (PBE). For electronic properties the modified Becke-Johnson (mBJ) potential, which is more accurate than standard semi-local LDA and PBE calculations, has been chosen. Geometric optimization has been implemented before the volume optimization calculations for all the studied alloys structure. The obtained equilibrium lattice constants of the studied binary compounds are in coincidence with experimental works. And, the variation of the lattice parameter of ternary alloys BBi1-xNx almost perfectly matches with Vegard's law. The spin-orbit interaction (SOI) has been also considered for structural and electronic calculations and the results are compared to those of non-SOI calculations.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

Strain-controlled electronic properties and magnetorelaxor behaviors in electron-doped CaMnO3 thin films

NASA Astrophysics Data System (ADS)

Xiang, P.-H.; Yamada, H.; Sawa, A.; Akoh, H.

2009-02-01

We have fabricated epitaxial thin films of electron-doped manganite Ca1-xCexMnO3 (CCMO) with 0≤x≤0.08. The transport properties of CCMO films are very sensitive to substrate-controlled epitaxial strain. For the CCMO(x =0.05) film, the metallic transport characteristic is observed only on a nearly lattice-matched NdAlO3 (NAO) substrate, while tensilely and compressively stressed films are insulating. The CCMO(x =0.06) film on the NAO substrate shows a large magnetoresistance characteristic of a magnetorelaxor. This behavior can be explained in terms of the phase separation and the irreversible growth of the metallic domain in antiferromagnetic insulating matrix.

Compact modeling of total ionizing dose and aging effects in MOS technologies

DOE PAGES

Esqueda, Ivan S.; Barnaby, Hugh J.; King, Michael Patrick

2015-06-18

This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimentalmore » I-V characteristics from irradiated devices. The presented approach is suitable for modeling TID and aging effects in advanced MOS devices and ICs.« less

Compact tunable silicon photonic differential-equation solver for general linear time-invariant systems.

PubMed

Wu, Jiayang; Cao, Pan; Hu, Xiaofeng; Jiang, Xinhong; Pan, Ting; Yang, Yuxing; Qiu, Ciyuan; Tremblay, Christine; Su, Yikai

2014-10-20

We propose and experimentally demonstrate an all-optical temporal differential-equation solver that can be used to solve ordinary differential equations (ODEs) characterizing general linear time-invariant (LTI) systems. The photonic device implemented by an add-drop microring resonator (MRR) with two tunable interferometric couplers is monolithically integrated on a silicon-on-insulator (SOI) wafer with a compact footprint of ~60 μm × 120 μm. By thermally tuning the phase shifts along the bus arms of the two interferometric couplers, the proposed device is capable of solving first-order ODEs with two variable coefficients. The operation principle is theoretically analyzed, and system testing of solving ODE with tunable coefficients is carried out for 10-Gb/s optical Gaussian-like pulses. The experimental results verify the effectiveness of the fabricated device as a tunable photonic ODE solver.

Wide-range and fast thermally-tunable silicon photonic microring resonators using the junction field effect

DOE PAGES

Wang, Xiaoxi; Lentine, Anthony; DeRose, Christopher; ...

2016-09-26

Tunable silicon microring resonators with small, integrated micro-heaters which exhibit a junction field effect were made using a conventional silicon-on-insulator (SOI) photonic foundry fabrication process. The design of the resistive tuning section in the microrings included a “pinched” p-n junction, which limited the current at higher voltages and inhibited damage even when driven by a pre-emphasized voltage waveform. Dual-ring filters were studied for both large (>4.9 THz) and small (850 GHz) free-spectral ranges. In conclusion, thermal red-shifting was demonstrated with microsecond-scale time constants, e.g., a dual-ring filter was tuned over 25 nm in 0.6 μs 10%–90% transition time, and withmore » efficiency of 3.2 μW/GHz.« less

Fiber Bragg grating sensor interrogators on chip: challenges and opportunities

NASA Astrophysics Data System (ADS)

Marin, Yisbel; Nannipieri, Tiziano; Oton, Claudio J.; Di Pasquale, Fabrizio

2017-04-01

In this paper we present an overview of the current efforts towards integration of Fiber Bragg Grating (FBG) sensor interrogators. Different photonic integration platforms will be discussed, including monolithic planar lightwave circuit technology, silicon on insulator (SOI), indium phosphide (InP) and gallium arsenide (GaAs) material platforms. Also various possible techniques for wavelength metering and methods for FBG multiplexing will be discussed and compared in terms of resolution, dynamic performance, multiplexing capabilities and reliability. The use of linear filters, array waveguide gratings (AWG) as multiple linear filters and AWG based centroid signal processing techniques will be addressed as well as interrogation techniques based on tunable micro-ring resonators and Mach-Zehnder interferometers (MZI) for phase sensitive detection. The paper will also discuss the challenges and perspectives of photonic integration to address the increasing requirements of several industrial applications.

A comparison of heavy ion induced single event upset susceptibility in unhardened 6T/SRAM and hardened ADE/SRAM

NASA Astrophysics Data System (ADS)

Wang, Bin; Zeng, Chuanbin; Geng, Chao; Liu, Tianqi; Khan, Maaz; Yan, Weiwei; Hou, Mingdong; Ye, Bing; Sun, Youmei; Yin, Yanan; Luo, Jie; Ji, Qinggang; Zhao, Fazhan; Liu, Jie

2017-09-01

Single event upset (SEU) susceptibility of unhardened 6T/SRAM and hardened active delay element (ADE)/SRAM, fabricated with 0.35 μm silicon-on-insulator (SOI) CMOS technology, was investigated at heavy ion accelerator. The mechanisms were revealed by the laser irradiation and resistor-capacitor hardened techniques. Compared with conventional 6T/SRAM, the hardened ADE/SRAM exhibited higher tolerance to heavy ion irradiation, with an increase of about 80% in the LET threshold and a decrease of ∼64% in the limiting upset cross-section. Moreover, different probabilities between 0 → 1 and 1 → 0 transitions were observed, which were attributed to the specific architecture of ADE/SRAM memory cell. Consequently, the radiation-hardened technology can be an attractive alternative to the SEU tolerance of the device-level.

Development of dual-polarization LEKIDs for CMB observations

NASA Astrophysics Data System (ADS)

McCarrick, Heather; Abitbol, Maximilian H.; Ade, Peter A. R.; Barry, Peter; Bryan, Sean; Che, George; Day, Peter; Doyle, Simon; Flanigan, Daniel; Johnson, Bradley R.; Jones, Glenn; LeDuc, Henry G.; Limon, Michele; Mauskopf, Philip; Miller, Amber; Tucker, Carole; Zmuidzinas, Jonas

2016-07-01

We discuss the design considerations and initial measurements from arrays of dual-polarization, lumped-element kinetic inductance detectors (LEKIDs) nominally designed for cosmic microwave background (CMB) studies. The detectors are horn-coupled, and each array element contains two single-polarization LEKIDs, which are made from thin-film aluminum and optimized for a single spectral band centered on 150 GHz. We are developing two array architectures, one based on 160 micron thick silicon wafers and the other based on silicon-on-insulator (SOI) wafers with a 30 micron thick device layer. The 20-element test arrays (40 LEKIDs) are characterized with both a linearly-polarized electronic millimeter wave source and a thermal source. We present initial measurements including the noise spectra, noise-equivalent temperature, and responsivity. We discuss future testing and further design optimizations to be implemented.

Optical modulation in silicon waveguides via charge state control of deep levels.

PubMed

Logan, D F; Jessop, P E; Knights, A P; Wojcik, G; Goebel, A

2009-10-12

The control of defect mediated optical absorption at a wavelength of 1550 nm via charge state manipulation is demonstrated using optical absorption measurements of indium doped Silicon-On-Insulator (SOI) rib waveguides. These measurements introduce the potential for modulation of waveguide transmission by using the local depletion and injection of free-carriers to change deep-level occupancy. The extinction ratio and modulating speed are simulated for a proposed device structure. A 'normally-off' depletion modulator is described with an extinction coefficient limited to 5 dB/cm and switching speeds in excess of 1 GHz. For a carrier injection modulator a fourfold enhancement in extinction ratio is provided relative to free carrier absorption alone. This significant improvement in performance is achieved with negligible increase in driving power but slightly degraded switching speed.

Formation of Fe2SiO4 thin films on Si substrates and influence of substrate to its thermoelectric transport properties

NASA Astrophysics Data System (ADS)

Choi, Jeongyong; Nguyen, Van Quang; Duong, Van Thiet; Shin, Yooleemi; Duong, Anh Tuan; Cho, Sunglae

2018-03-01

Fe2SiO4 thin films have been grown on n-type, p-type and semi-insulating Si(100) substrates by molecular beam epitaxy. When Fe-O thin films were deposited on Si(100) substrate at 300 °C, the film reacted with Si, resulting in a Fe2SiO4 film because of the high reactivity between Fe and Si. The electrical resistance and Seebeck coefficient of Fe2SiO4 thin films grown were different in different doping states. On n-type and p-type Si(100), the electrical resistance decreased suddenly and increased again at 350 and 250 K, respectively, while on semi-insulating Si(100), it exhibited typical semiconducting resistance behavior. We observed similar crossovers at 350 and 250 K in temperature dependent Seebeck coefficients on n-type and p-type Si(100), respectively. These results suggest that the measured electrical and thermoelectric properties originate from Si substrate.

Feature Extraction and Classification of Magnetic and EMI Data, Camp Beale, CA

DTIC Science & Technology

2012-05-01

and non-specialists. However, as part of ESTCP 1004 we are presently working on transitioning our inversion algorithms to an API that will be...10 0 Time (ms) Cell 663 - Target 1965 - Model 1 (SOI) ISO IVS 0.001 0.005 10 0 Time (ms) Cell 1104 - Target 2532 - Model 1 (SOI) ISO IVS...0.0 1 0.005 10 0 Time (ms) Cell 663 - Target 1965 - Model 1 (SOI) ISO IVS 0.0 1 0.005 10 0 Time (ms) Cell 1104 - Target 2532 - Model 1 (SOI

Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

NASA Astrophysics Data System (ADS)

Kang, Sung-Weon; Lyu, Jong-Son; Kang, Jin-Young; Kang, Sang-Won; Lee, Jin-Hyo

1995-06-01

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, approximately 2500 Angstrom) and fully depleted (FD, approximately 800 Angstrom) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES Ilb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to approximately pA and no hump was seen on the drain current curve.

Southern Ocean Climate and Sea Ice Anomalies Associated with the Southern Oscillation.

NASA Astrophysics Data System (ADS)

Kwok, R.; Comiso, J. C.

2002-03-01

The anomalies in the climate and sea ice cover of the Southern Ocean and their relationships with the Southern Oscillation (SO) are investigated using a 17-yr dataset from 1982 to 1998. The polar climate anomalies are correlated with the Southern Oscillation index (SOI) and the composites of these anomalies are examined under the positive (SOI > 0), neutral (0 > SOI > 1), and negative (SOI < 1) phases of SOI. The climate dataset consists of sea level pressure, wind, surface air temperature, and sea surface temperature fields, while the sea ice dataset describes its extent, concentration, motion, and surface temperature. The analysis depicts, for the first time, the spatial variability in the relationship of the above variables with the SOI. The strongest correlation between the SOI and the polar climate anomalies are found in the Bellingshausen, Amundsen, and Ross Seas. The composite fields reveal anomalies that are organized in distinct large-scale spatial patterns with opposing polarities at the two extremes of SOI, and suggest oscillations that are closely linked to the SO. Within these sectors, positive (negative) phases of the SOI are generally associated with lower (higher) sea level pressure, cooler (warmer) surface air temperature, and cooler (warmer) sea surface temperature in these sectors. Associations between these climate anomalies and the behavior of the Antarctic sea ice cover are evident. Recent anomalies in the sea ice cover that are clearly associated with the SOI include the following: the record decrease in the sea ice extent in the Bellingshausen Sea from mid-1988 to early 1991; the relationship between Ross Sea SST and the ENSO signal, and reduced sea ice concentration in the Ross Sea; and the shortening of the ice season in the eastern Ross Sea, Amundsen Sea, far western Weddell Sea and lengthening of the ice season in the western Ross Sea, Bellinghausen Sea, and central Weddell Sea gyre during the period 1988-94. Four ENSO episodes over the last 17 years contributed to a negative mean in the SOI (0.5). In each of these episodes, significant retreats in ice cover of the Bellingshausen and Amundsen Seas were observed showing a unique association of this region of the Antarctic with the Southern Oscillation.

Conical Tungsten Tips as Substrates for the Preparation of Ultramicroelectrodes

PubMed Central

Hermans, Andre; Wightman, R. Mark

2008-01-01

Here we describe a simple method to prepare voltammetric microelectrodes using tungsten wires as a substrate. Tungsten wires have high tensile modulus and enable the fabrication of electrodes that have small dimensions overall while retaining rigidity. In this work, 125 μm tungsten wires with a conical tip were employed. For the preparation of gold or platinum ultramicroelectrodes, commercial tungsten microelectrodes, completely insulated except at the tip, were used as substrates. Following removal of oxides from the exposed tungsten, platinum or gold was electroplated yielding surfaces with an electroactive area of between 1×10−6 cm2 to 2×10−6 cm2. Carbon surfaces on the etched tip of tungsten microwires were prepared by coating with photoresist followed by pyrolysis. The entire electrode was then insulated with Epoxylite except the tip yielding an exposed carbon surface with an area of around 4×10−6 cm2 to 6×10−6 cm2. All three types of ultramicroelectrodes fabricated on the tungsten wire had similar electrochemical behavior to electrodes fabricated from wires or fibers insulated with glass tubes. PMID:17129002

Epitaxy, strain, and composition effects on metal-insulator transition characteristics of SmNiO{sub 3} thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aydogdu, Gulgun H.; Ha, Sieu D.; Viswanath, B.

SmNiO{sub 3} (SNO) thin films were deposited on LaAlO{sub 3} (LAO), SrTiO{sub 3}, SrLaAlO{sub 4}, Si, and Al{sub 2}O{sub 3} (sapphire) substrates by RF magnetron sputtering and studies were conducted to understand how film structure and composition influence the insulator-metal transition properties. It is observed that the compressive strain induces the insulator to metal transition (MIT), while tensile strain suppresses it. In the case of non-epitaxial films, semiconducting behavior is obtained on sapphire over a broad temperature range, while on heavily-doped Si substrate; an MIT is seen in out-of-plane resistance measurement. In addition, thickness dependence on the resistance behavior andmore » nickel oxidation state has been examined for epitaxial SNO films on LAO substrates. Fine control of the MIT by modifications to the mismatch strain and thickness provides insights to enhance the performance and the functionality of these films for emerging electron devices.« less

Use of GC/MS and Microtome Techniques as Methods to Evaluate ODC Free Cleaner Diffusion and Evaporation in Insulation and Phenolic Case Material

NASA Technical Reports Server (NTRS)

Biegert, L. L.

2001-01-01

Because of the 1990 Clean Air Act Amendment (CAAA) many chlorinated solvents used in the aerospace industry are being phased out. Replacement of the ODC (ozone-depleting chemicals) with less volatile, non-ozone depleting cleaners has been extensively studied over the past seven years at Thiokol Propulsion, a Division of Cordant Technologies, Inc. The down selection of ODC replacement cleaners has been based on several factors including the diffusion evaporation of the cleaners in selected substrates. Methodologies were developed to evaluate the cleaner content in substrates. Methods of cutting thin slices of material (microtoming) were combined with GC/MS (gas chromatography/mass spectroscopy) analysis. Substrates evaluated in this study include potential solid rocket motor materials: ASNBR (asbestos-filled nitrile butadiene rubber) and CFEPDM (carbon-filled ethylene propylene dimonomer) insulation and glass (GCP), carbon (CCP) and silica (SCP) cloth phenolic substrates with fibers either parallel (0 deg) or perpendicular (90 deg) to the surface. Residue profiles indicate both cleaner and substrate composition affect the diffusion and subsequent evaporation of the cleaner from the substrate surface.

Metal insulator transitions in perovskite SrIrO{sub 3} thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Biswas, Abhijit; Jeong, Yoon Hee, E-mail: yhj@postech.ac.kr; Kim, Ki-Seok

Understanding of metal insulator transitions in a strongly correlated system, driven by Anderson localization (disorder) and/or Mott localization (correlation), is a long standing problem in condensed matter physics. The prevailing fundamental question would be how these two mechanisms contrive to accomplish emergent anomalous behaviors. Here, we have grown high quality perovskite SrIrO{sub 3} thin films, containing a strong spin orbit coupled 5d element Ir, on various substrates such as GdScO{sub 3} (110), DyScO{sub 3} (110), SrTiO{sub 3} (001), and NdGaO{sub 3} (110) with increasing lattice mismatch, in order to carry out a systematic study on the transport properties. We foundmore » that metal insulator transitions can be induced in this system; by either reducing thickness (on best lattice matched substrate) or changing degree of lattice strain (by lattice mismatch between film and substrates) of films. Surprisingly these two pathways seek two distinct types of metal insulator transitions; the former falls into disorder driven Anderson type whereas the latter turns out to be of unconventional Mott-Anderson type with the interplay of disorder and correlation. More interestingly, in the metallic phases of SrIrO{sub 3}, unusual non-Fermi liquid characteristics emerge in resistivity as Δρ ∝ T{sup ε} with ε evolving from 4/5 to 1 to 3/2 with increasing lattice strain. We discuss theoretical implications of these phenomena to shed light on the metal insulator transitions.« less

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

Helium ion beam induced electron emission from insulating silicon nitride films under charging conditions

NASA Astrophysics Data System (ADS)

Petrov, Yu. V.; Anikeva, A. E.; Vyvenko, O. F.

2018-06-01

Secondary electron emission from thin silicon nitride films of different thicknesses on silicon excited by helium ions with energies from 15 to 35 keV was investigated in the helium ion microscope. Secondary electron yield measured with Everhart-Thornley detector decreased with the irradiation time because of the charging of insulating films tending to zero or reaching a non-zero value for relatively thick or thin films, respectively. The finiteness of secondary electron yield value, which was found to be proportional to electronic energy losses of the helium ion in silicon substrate, can be explained by the electron emission excited from the substrate by the helium ions. The method of measurement of secondary electron energy distribution from insulators was suggested, and secondary electron energy distribution from silicon nitride was obtained.

CCSDS SOIS Subnetwork Services: A First Reference Implementation

NASA Astrophysics Data System (ADS)

Gunes-Lasnet, S.; Notebaert, O.; Farges, P.-Y.; Fowell, S.

2008-08-01

The CCSDS SOIS working groups are developing a range of standards for spacecraft onboard interfaces with the intention of promoting reuse of hardware and software designs across a range of missions while enabling interoperability of onboard systems from diverse sources. The CCSDS SOIS working groups released in June 2007 their red books for both Subnetwork and application support layers. In order to allow the verification of these recommended standards and to pave the way for future implementation onboard spacecrafts, it is essential for these standards to be prototyped on a representative spacecraft platform, to provide valuable feed back to the SOIS working group. A first reference implementation of both Subnetwork and Application Support SOIS services over SpaceWire and Mil-Std-1553 bus is thus being realised by SciSys Ltd and Astrium under an ESA contract.

Rectifying antenna and method of manufacture

NASA Technical Reports Server (NTRS)

Bhansali, Shekhar (Inventor); Buckle, Kenneth (Inventor); Goswami, D. Yogi (Inventor); Stefanakos, Elias (Inventor); Weller, Thomas (Inventor)

2006-01-01

In accordance with the present invention, an aperture rectenna is provided where the substrate is transparent and of sufficient mechanical strength to support the fabricated structure above it. An aperture antenna is deposited on the transparent substrate and a metal-insulator-metal (MIM) diode is constructed on top of the aperture antenna. There is an insulating layer between the aperture antenna metal and the metal ground plane optimized to maximize the collection of incident radiation. The top of the structure is capped with a metal ground plane layer, which also serves as the DC connection points for each rectenna element.

Insulator coating for high temperature alloys method for producing insulator coating for high temperature alloys

DOEpatents

Park, J.H.

1998-06-23

A method for fabricating an electrically insulating coating on a surface is disclosed comprising coating the surface with a metal, and reacting the metal coated surface with a nonmetal so as to create a film on the metal-coated surface. Alternatively, the invention provides for a method for producing a noncorrosive, electrically insulating coating on a surface saturated with a nonmetal comprising supplying a molten fluid, dissolving a metal in the molten fluid to create a mixture, and contacting the mixture with the saturated surface. Lastly, the invention provides an electrically insulative coating comprising an underlying structural substrate coated with an oxide or nitride compound. 2 figs.

Sociosexuality from Argentina to Zimbabwe: a 48-nation study of sex, culture, and strategies of human mating.

PubMed

Schmitt, David P

2005-04-01

The Sociosexual Orientation Inventory (SOI; Simpson & Gangestad 1991) is a self-report measure of individual differences in human mating strategies. Low SOI scores signify that a person is sociosexually restricted, or follows a more monogamous mating strategy. High SOI scores indicate that an individual is unrestricted, or has a more promiscuous mating strategy. As part of the International Sexuality Description Project (ISDP), the SOI was translated from English into 25 additional languages and administered to a total sample of 14,059 people across 48 nations. Responses to the SOI were used to address four main issues. First, the psychometric properties of the SOI were examined in cross-cultural perspective. The SOI possessed adequate reliability and validity both within and across a diverse range of modem cultures. Second, theories concerning the systematic distribution of sociosexuality across cultures were evaluated. Both operational sex ratios and reproductively demanding environments related in evolutionary-predicted ways to national levels of sociosexuality. Third, sex differences in sociosexuality were generally large and demonstrated cross-cultural universality across the 48 nations of the ISDP, confirming several evolutionary theories of human mating. Fourth, sex differences in sociosexuality were significantly larger when reproductive environments were demanding but were reduced to more moderate levels in cultures with more political and economic gender equality. Implications for evolutionary and social role theories of human sexuality are discussed.

Pure gauge spin-orbit couplings

NASA Astrophysics Data System (ADS)

Shikakhwa, M. S.

2017-01-01

Planar systems with a general linear spin-orbit interaction (SOI) that can be cast in the form of a non-Abelian pure gauge field are investigated using the language of non-Abelian gauge field theory. A special class of these fields that, though a 2×2 matrix, are Abelian are seen to emerge and their general form is given. It is shown that the unitary transformation that gauges away these fields induces at the same time a rotation on the wave function about a fixed axis but with a space-dependent angle, both of which being characteristics of the SOI involved. The experimentally important case of equal-strength Rashba and Dresselhaus SOI (R+D SOI) is shown to fall within this special class of Abelian gauge fields, and the phenomenon of persistent spin helix (PSH) that emerges in the presence of this latter SOI in a plane is shown to fit naturally within the general formalism developed. The general formalism is also extended to the case of a particle confined to a ring. It is shown that the Hamiltonian on a ring in the presence of equal-strength R+D SOI is unitarily equivalent to that of a particle subject to only a spin-independent but θ-dependent potential with the unitary transformation relating the two being again the space-dependent rotation operator characteristic of R+D SOI.

Thick film hydrogen sensor

DOEpatents

Hoffheins, Barbara S.; Lauf, Robert J.

1995-01-01

A thick film hydrogen sensor element includes an essentially inert, electrically-insulating substrate having deposited thereon a thick film metallization forming at least two resistors. The metallization is a sintered composition of Pd and a sinterable binder such as glass frit. An essentially inert, electrically insulating, hydrogen impermeable passivation layer covers at least one of the resistors.

Thick film hydrogen sensor

DOEpatents

Hoffheins, B.S.; Lauf, R.J.

1995-09-19

A thick film hydrogen sensor element includes an essentially inert, electrically-insulating substrate having deposited thereon a thick film metallization forming at least two resistors. The metallization is a sintered composition of Pd and a sinterable binder such as glass frit. An essentially inert, electrically insulating, hydrogen impermeable passivation layer covers at least one of the resistors. 8 figs.

Gate-Variable Mid-Infrared Optical Transitions in a (Bi1-xSbx)2Te3 Topological Insulator.

PubMed

Whitney, William S; Brar, Victor W; Ou, Yunbo; Shao, Yinming; Davoyan, Artur R; Basov, D N; He, Ke; Xue, Qi-Kun; Atwater, Harry A

2017-01-11

We report mid-infrared spectroscopy measurements of ultrathin, electrostatically gated (Bi 1-x Sb x ) 2 Te 3 topological insulator films in which we observe several percent modulation of transmittance and reflectance as gating shifts the Fermi level. Infrared transmittance measurements of gated films were enabled by use of an epitaxial lift-off method for large-area transfer of topological insulator films from infrared-absorbing SrTiO 3 growth substrates to thermal oxidized silicon substrates. We combine these optical experiments with transport measurements and angle-resolved photoemission spectroscopy to identify the observed spectral modulation as a gate-driven transfer of spectral weight between both bulk and 2D topological surface channels and interband and intraband channels. We develop a model for the complex permittivity of gated (Bi 1-x Sb x ) 2 Te 3 and find a good match to our experimental data. These results open the path for layered topological insulator materials as a new candidate for tunable, ultrathin infrared optics and highlight the possibility of switching topological optoelectronic phenomena between bulk and spin-polarized surface regimes.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Winokur, P.S.; Devine, R.A.B.

1998-07-28

A method is disclosed for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer. 5 figs.

Imaging prototypical aromatic molecules on insulating surfaces: a review

NASA Astrophysics Data System (ADS)

Hoffmann-Vogel, R.

2018-01-01

Insulating substrates allow for in-plane contacted molecular electronics devices where the molecule is in contact with the insulator. For the development of such devices it is important to understand the interaction of molecules with insulating surfaces. As substrates, ionic crystals such as KBr, KCl, NaCl and CaF2 are discussed. The surface energies of these substrates are small and as a consequence intrinsic properties of the molecules, such as molecule–molecule interaction, become more important relative to interactions with the substrates. As prototypical molecules, three variants of graphene-related molecules are used, pentacene, C60 and PTCDA. Pentacene is a good candidate for molecular electronics applications due to its high charge carrier mobility. It shows mainly an upright standing growth mode and the morphology of the islands is strongly influenced by dewetting. A new second flat-lying phase of the molecule has been observed. Studying the local work function using the Kelvin method reveals details such as line defects in the center of islands. The local work function differences between the upright-standing and flat-lying phase can only be explained by charge transfer that is unusual on ionic crystalline surfaces. C60 nucleation and growth is explained by loosely bound molecules at kink sites as nucleation sites. The stability of C60 islands as a function of magic numbers is investigated. Peculiar island shapes are obtained from unusual dewetting processes already at work during growth, where molecules ‘climb’ to the second molecular layer. PTCDA is a prototypical semiconducting molecule with strong quadrupole moment. It grows in the form of elongated islands where the top and the facets can be molecularly resolved. In this way the precise molecular arrangement in the islands is revealed.

Phase modulation in horizontal metal-insulator-silicon-insulator-metal plasmonic waveguides.

PubMed

Zhu, Shiyang; Lo, G Q; Kwong, D L

2013-04-08

An extremely compact Si phase modulator is proposed and validated, which relies on effective modulation of the real part of modal index of horizontal metal-insulator-Si-insulator-metal plasmonic waveguides by a voltage applied between the metal cover and the Si core. Proof-of-concept devices are fabricated on silicon-on-insulator substrates using standard complementary metal-oxide-semiconductor technology using copper as the metal and thermal silicon dioxide as the insulator. A modulator with a 1-μm-long phase shifter inserted in an asymmetric Si Mach-Zehnder interferometer exhibits 9-dB extinction ratio under a 6-V/10-kHz voltage swing. Numerical simulations suggest that high speed and low driving voltage could be achieved by shortening the distance between the Si core and the n(+)-contact and by using a high-κ dielectric as the insulator, respectively.

Fabrication of Ohmic contact on semi-insulating 4H-SiC substrate by laser thermal annealing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cheng, Yue; Lu, Wu-yue; Wang, Tao

The Ni contact layer was deposited on semi-insulating 4H-SiC substrate by magnetron sputtering. The as-deposited samples were treated by rapid thermal annealing (RTA) and KrF excimer laser thermal annealing (LTA), respectively. The RTA annealed sample is rectifying while the LTA sample is Ohmic. The specific contact resistance (ρ{sub c}) is 1.97 × 10{sup −3} Ω·cm{sup 2}, which was determined by the circular transmission line model. High resolution transmission electron microscopy morphologies and selected area electron diffraction patterns demonstrate that the 3C-SiC transition zone is formed in the near-interface region of the SiC after the as-deposited sample is treated by LTA,more » which is responsible for the Ohmic contact formation in the semi-insulating 4H-SiC.« less

Power module assembly with reduced inductance

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ward, Terence G.; Stancu, Constantin C.; Jaksic, Marko

A power module assembly has a plurality of electrically conducting layers, including a first layer and a third layer. One or more electrically insulating layers are operatively connected to each of the plurality of electrically conducting layers. The electrically insulating layers include a second layer positioned between and configured to electrically isolate the first and the third layers. The first layer is configured to carry a first current flowing in a first direction. The third layer is configured to carry a second current flowing in a second direction opposite to the first direction, thereby reducing an inductance of the assembly.more » The electrically insulating layers may include a fourth layer positioned between and configured to electrically isolate the third layer and a fifth layer. The assembly results in a combined substrate and heat sink structure. The assembly eliminates the requirements for connections between separate substrate and heat sink structures.« less

Geometric confinement effects on the metal-insulator transition temperature and stress relaxation in VO2 thin films grown on silicon

NASA Astrophysics Data System (ADS)

Viswanath, Changhyun Ko, B.; Yang, Zheng; Ramanathan, Shriram

2011-03-01

VO2 undergoes a sharp metal-insulator transition at ˜67 °C with several orders of change in conductivity and optical transmittance. Understanding and control of the properties of vanadium oxide layers grown on technologically relevant substrates such as Si (100) single crystals is therefore of great interest. In this work, we show tunability of metal-insulator transition temperature as well as recoverable stress in VO2 thin films grown on Si substrate by introducing nanoscale atomic layer deposited HfO2 interfacial layers with no degradation in the resistance ratio. For a confined VO2 film, the metal-insulator transition temperature is suppressed by ˜16 °C and the recoverable stress is 150 MPa, compared to 400 MPa for a bare film. These observations are further correlated with in situ variable temperature measurement of stress changes occurring during the phase transition. Structural and microstructural studies on the various samples have been carried out by x ray diffraction and cross-sectional transmission electron microscopy. The strategy of tuning the metal-insulator transition characteristics by nanoscale interfacial dielectrics is of broader relevance in design of programmable materials and integration into solid state devices for electronics.

MEMS-based silicon cantilevers with integrated electrothermal heaters for airborne ultrafine particle sensing

NASA Astrophysics Data System (ADS)

Wasisto, Hutomo Suryo; Merzsch, Stephan; Waag, Andreas; Peiner, Erwin

2013-05-01

The development of low-cost and low-power MEMS-based cantilever sensors for possible application in hand-held airborne ultrafine particle monitors is described in this work. The proposed resonant sensors are realized by silicon bulk micromachining technology with electrothermal excitation, piezoresistive frequency readout, and electrostatic particle collection elements integrated and constructed in the same sensor fabrication process step of boron diffusion. Built-in heating resistor and full Wheatstone bridge are set close to the cantilever clamp end for effective excitation and sensing, respectively, of beam deflection. Meanwhile, the particle collection electrode is located at the cantilever free end. A 300 μm-thick, phosphorus-doped silicon bulk wafer is used instead of silicon-on-insulator (SOI) as the starting material for the sensors to reduce the fabrication costs. To etch and release the cantilevers from the substrate, inductively coupled plasma (ICP) cryogenic dry etching is utilized. By controlling the etching parameters (e.g., temperature, oxygen content, and duration), cantilever structures with thicknesses down to 10 - 20 μm are yielded. In the sensor characterization, the heating resistor is heated and generating thermal waves which induce thermal expansion and further cause mechanical bending strain in the out-of-plane direction. A resonant frequency of 114.08 +/- 0.04 kHz and a quality factor of 1302 +/- 267 are measured in air for a fabricated rectangular cantilever (500x100x13.5 μm3). Owing to its low power consumption of a few milliwatts, this electrothermal cantilever is suitable for replacing the current external piezoelectric stack actuator in the next generation of the miniaturized cantilever-based nanoparticle detector (CANTOR).

Top-down nanofabrication of silicon nanoribbon field effect transistor (Si-NR FET) for carcinoembryonic antigen detection.

PubMed

Bao, Zengtao; Sun, Jialin; Zhao, Xiaoqian; Li, Zengyao; Cui, Songkui; Meng, Qingyang; Zhang, Ye; Wang, Tong; Jiang, Yanfeng

2017-01-01

Sensitive and quantitative detection of tumor markers is highly required in the clinic for cancer diagnosis and consequent treatment. A field-effect transistor-based (FET-based) nanobiosensor emerges with characteristics of being label-free, real-time, having high sensitivity, and providing direct electrical readout for detection of biomarkers. In this paper, a top-down approach is proposed and implemented to fulfill a novel silicon nano-ribbon FET, which acts as biomarker sensor for future clinical application. Compared with the bottom-up approach, a top-down fabrication approach can confine width and length of the silicon FET precisely to control its electrical properties. The silicon nanoribbon (Si-NR) transistor is fabricated on a Silicon-on-Insulator (SOI) substrate by a top-down approach with complementary metal oxide semiconductor (CMOS)-compatible technology. After the preparation, the surface of Si-NR is functionalized with 3-aminopropyltriethoxysilane (APTES). Glutaraldehyde is utilized to bind the amino terminals of APTES and antibody on the surface. Finally, a microfluidic channel is integrated on the top of the device, acting as a flowing channel for the carcinoembryonic antigen (CEA) solution. The Si-NR FET is 120 nm in width and 25 nm in height, with ambipolar electrical characteristics. A logarithmic relationship between the changing ratio of the current and the CEA concentration is measured in the range of 0.1-100 ng/mL. The sensitivity of detection is measured as 10 pg/mL. The top-down fabricated biochip shows feasibility in direct detecting of CEA with the benefits of real-time, low cost, and high sensitivity as a promising biosensor for tumor early diagnosis.

Opportunities of CMOS-MEMS integration through LSI foundry and open facility

NASA Astrophysics Data System (ADS)

Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

2017-06-01

Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

Hole generation associated with intrinsic defects in SOI-based SiGe thin films formed by solid-source molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Satoh, Motoki; Arimoto, Keisuke; Yamanaka, Junji; Sawano, Kentarou; Shiraki, Yasuhiro; Nakagawa, Kiyokazu

2018-04-01

The electronic properties of SiGe on insulator (SGOI) structure are under intense investigation due to its importance as an electronic material. In the previous investigations, a p-type conduction was observed in SGOI even in the absence of extrinsic chemical acceptors, which is a serious problem for device applications. In this paper, the electrical properties of intrinsic-defect-related acceptor states generated during the SGOI formation are reported. It is found that freeze-out is hard to be achieved even at temperatures below 10 K, which indicates that the Fermi level lies near the valence band at low temperatures. With an aim to annihilate these defects, thermal annealing at 1050 °C for 12 h in N2 ambient was carried out. It was found that the thermal treatment is effective in reducing the densities of the acceptor states and in improving the crystalline quality.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line

PubMed Central

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R.

2016-01-01

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth. PMID:27457024

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

NASA Astrophysics Data System (ADS)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Stable and wavelength-tunable silicon-micro-ring-resonator based erbium-doped fiber laser.

PubMed

Yang, L G; Yeh, C H; Wong, C Y; Chow, C W; Tseng, F G; Tsang, H K

2013-02-11

In this work, we propose and demonstrate a stable and wavelength-tunable erbium-doped fiber (EDF) ring laser. Here, a silicon-on-insulator (SOI)-based silicon-micro-ring-resonator (SMRR) is used as the wavelength selective element inside the fiber ring cavity. A uniform period grating coupler (GC) is used to couple between the SMRR and single mode fiber (SMF) and serves also as a polarization dependent element in the cavity. The output lasing wavelength of the proposed fiber laser can be tuned at a tuning step of 2 nm (defined by the free spectral range (FSR) of the SMRR) in a bandwidth of 35.2 nm (1532.00 to 1567.20 nm), which is defined by the gain of the EDF. The optical-signal-to-noise-ratio (OSNR) of each lasing wavelength is larger than 42.0 dB. In addition, the output stabilities of power and wavelength are also discussed.

New dynamic silicon photonic components enabled by MEMS technology

NASA Astrophysics Data System (ADS)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

A four-port vertical-coupling optical interface based on two-dimensional grating coupler

NASA Astrophysics Data System (ADS)

Zhang, Zan; Zhang, Zanyun; Huang, Beiju; Cheng, Chuantong; Gao, Tianxi; Hu, Xiaochuan; Zhang, Lin; Chen, Hongda

2016-10-01

In this work, a fiber-to-chip optical interface with four output ports is proposed. External lights irradiate vertically from single mode fiber to the center of optical interface can be coupled into silicon photonic chips and split into four siliconon- insulator (SOI) waveguides. If the light is circular polarized, the power of light will be equally split into four ports. Meanwhile, all lights travel in the four channel will be converted into TE polarization. The optical interface is based on a two-dimensional grating coupler with carefully designed duty cycle and period. Simulation results show that the coupling efficiency of each port can reach 11.6% so that the total coupling efficiency of the interface is 46.4%. And Lights coupled into four waveguides are all converted into TE polarization. Further, the optical interface has a simple grating structure allowing for easy fabrication.

Optics Communications: Special issue on Polymer Photonics and Its Applications

NASA Astrophysics Data System (ADS)

Zhang, Ziyang; Pitwon, Richard C. A.; Feng, Jing

2016-03-01

In the last decade polymer photonics has witnessed a tremendous boost in research efforts and practical applications. Polymer materials can be engineered to exhibit unique optical and electrical properties. Extremely transparent and reliable passive optical polymers have been made commercially available and paved the ground for the development of various waveguide components. Advancement in the research activities regarding the synthesis of active polymers has enabled devices such as ultra-fast electro-optic modulators, efficient white light emitting diodes, broadband solar cells, flexible displays, and so on. The fabrication technology is not only fast and cost-effective, but also provides flexibility and broad compatibility with other semiconductor processing technologies. Reports show that polymers have been integrated in photonic platforms such as silicon-on-insulator (SOI), III-V semiconductors, and silica PLCs, and vice versa, photonic components made from a multitude of materials have been integrated, in a heterogeneous/hybrid manner, in polymer photonic platforms.

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

PubMed

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

Impact of random discrete dopant in extension induced fluctuation in gate-source/drain underlap FinFET

NASA Astrophysics Data System (ADS)

Wang, Yijiao; Huang, Peng; Xin, Zheng; Zeng, Lang; Liu, Xiaoyan; Du, Gang; Kang, Jinfeng

2014-01-01

In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate-source/drain (G-S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (Vth), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (Ion), and leakage current (Ioff) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and Ion and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

Silicon MEMS bistable electromagnetic vibration energy harvester using double-layer micro-coils

NASA Astrophysics Data System (ADS)

Podder, P.; Constantinou, P.; Mallick, D.; Roy, S.

2015-12-01

This work reports the development of a MEMS bistable electromagnetic vibrational energy harvester (EMVEH) consisting of a silicon-on-insulator (SOI) spiral spring, double layer micro-coils and miniaturized NdFeB magnets. Furthermore, with respect to the spiral silicon spring based VEH, four different square micro-coil topologies with different copper track width and number of turns have been investigated to determine the optimal coil dimensions. The micro-generator with the optimal micro-coil generated 0.68 micro-watt load power over an optimum resistive load at 0.1g acceleration, leading to normalized power density of 3.5 kg.s/m3. At higher accelerations the load power increased, and the vibrating magnet collides with the planar micro-coil producing wider bandwidth. Simulation results show that a substantially wider bandwidth could be achieved in the same device by introducing bistable nonlinearity through a repulsive configuration between the moving and fixed permanent magnets.

Nanopillar arrays on semiconductor membranes as electron emission amplifiers.

PubMed

Qin, Hua; Kim, Hyun-Seok; Blick, Robert H

2008-03-05

A new transmission-type electron multiplier was fabricated from silicon-on-insulator (SOI) material by integrating an array of one-dimensional (1D) silicon nanopillars onto a two-dimensional (2D) silicon membrane. Primary electrons are injected into the nanopillar-membrane (NPM) system from the flat surface of the membrane, while electron emission from the nanopillars is probed by an anode. The secondary electron yield (SEY) from the nanopillars in the current device is found to be about 1.8 times that of the plain silicon membrane. This gain in electron number is slightly enhanced by the electric field applied from the anode. Further optimization of the dimensions of the NPM and an application of field emission promise an even higher gain for detector applications and allow for probing of electronic/mechanical excitations in an NPM system stimulated by incident particles or radiation.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

NASA Astrophysics Data System (ADS)

Harrington, R. C.; Kauppila, J. S.; Warren, K. M.; Chen, Y. P.; Maharrey, J. A.; Haeffner, T. D.; Loveless, T. D.; Bhuva, B. L.; Bounasser, M.; Lilja, K.; Massengill, L. W.

2017-08-01

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

Design and fabrication of hybrid SPP waveguides for ultrahigh-bandwidth low-penalty terabit-scale data transmission.

PubMed

Du, Jing; Wang, Jian

2017-11-27

Here we design and fabricate a hybrid surface plasmon polarities (SPP) waveguide on the silicon-on-insulator (SOI) photonics platform. The designed hybrid SPP waveguide is composed of a metal ridge, an air gap, and a silicon ridge. We simulate the mode characteristics in the structure and design the waveguide with a wide air gap that can simplify the fabrication process and maintain the advantages of the hybrid SPP mode. The performance of ultrahigh-bandwidth data transmission through the proposed waveguide is then investigated using 161 wavelength-division multiplexing (WDM) channels, each carrying a 11.2-Gbit/s orthogonal frequency-division multiplexing (OFDM) 16-ary quadrature amplitude modulation (16-QAM) signal. The bit-error rates (BERs) of all 161 channels are less than 1e-3. The favorable results show the prospect of on-chip optical interconnection using the proposed hybrid SPP waveguide.

Nanotexturing of surfaces to reduce melting point.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Garcia, Ernest J.; Zubia, David; Mireles, Jose

2011-11-01

This investigation examined the use of nano-patterned structures on Silicon-on-Insulator (SOI) material to reduce the bulk material melting point (1414 C). It has been found that sharp-tipped and other similar structures have a propensity to move to the lower energy states of spherical structures and as a result exhibit lower melting points than the bulk material. Such a reduction of the melting point would offer a number of interesting opportunities for bonding in microsystems packaging applications. Nano patterning process capabilities were developed to create the required structures for the investigation. One of the technical challenges of the project was understandingmore » and creating the specialized conditions required to observe the melting and reshaping phenomena. Through systematic experimentation and review of the literature these conditions were determined and used to conduct phase change experiments. Melting temperatures as low as 1030 C were observed.« less

Interface circuit for a multiple-beam tuning-fork gyroscope with high quality factors

NASA Astrophysics Data System (ADS)

Wang, Ren

This research work presents the design, theoretical analysis, fabrication, interface electronics, and experimental results of a Silicon-On-Insulator (SOI) based Multiple-Beam Tuning-Fork Gyroscope (MB-TFG). Based on a numerical model of Thermo-Elastic Damping (TED), a Multiple-Beam Tuning-Fork Structure (MB-TFS) is designed with high Quality factors (Qs) in its two operation modes. A comprehensive theoretical analysis of the MB-TFG design is conducted to relate the design parameters to its operation parameters and further performance parameters. In conjunction with a mask that defines the device through trenches to alleviate severe fabrication effect on anchor loss, a simple one-mask fabrication process is employed to implement this MB-TFG design on SOI wafers. The fabricated MB-TFGs are tested with PCB-level interface electronics and a thorough comparison between the experimental results and a theoretical analysis is conducted to verify the MB-TFG design and accurately interpret the measured performance. The highest measured Qs of the fabricated MB-TFGs in vacuum are 255,000 in the drive-mode and 103,000 in the sense-mode, at a frequency of 15.7kHz. Under a frequency difference of 4Hz between the two modes (operation frequency is 16.8kHz) and a drive-mode vibration amplitude of 3.0um, the measured rate sensitivity is 80mVpp/°/s with an equivalent impedance of 6MQ. The calculated overall rate resolution of this device is 0.37/hrhiElz, while the measured Angle Random Walk (ARW) and bias instability are 6.67°/'vhr and 95°/hr, respectively.

Topological Insulator State in Thin Bismuth Films Subjected to Plane Tensile Strain

NASA Astrophysics Data System (ADS)

Demidov, E. V.; Grabov, V. M.; Komarov, V. A.; Kablukova, N. S.; Krushel'nitskii, A. N.

2018-03-01

The results of experimental examination of galvanomagnetic properties of thin bismuth films subjected to plane tensile strain resulting from the difference in thermal expansion coefficients of the substrate material and bismuth are presented. The resistivity, the magnetoresistance, and the Hall coefficient were studied at temperatures ranging from 5 to 300 K in magnetic fields as strong as 0.65 T. Carrier densities were calculated. A considerable increase in carrier density in films thinner than 30 nm was observed. This suggests that surface states are more prominent in thin bismuth films on mica substrates, while the films themselves may exhibit the properties of a topological insulator.

Buffer Layer Doping Concentration Measurement Using VT-VSUB Characteristics of GaN HEMT with p-GaN Substrate Layer

NASA Astrophysics Data System (ADS)

Hu, Cheng-Yu; Nakatani, Katsutoshi; Kawai, Hiroji; Ao, Jin-Ping; Ohno, Yasuo

To improve the high voltage performance of AlGaN/GaN heterojunction field effect transistors (HFETs), we have fabricated AlGaN/GaN HFETs with p-GaN epi-layer on sapphire substrate with an ohmic contact to the p-GaN (p-sub HFET). Substrate bias dependent threshold voltage variation (VT-VSUB) was used to directly determine the doping concentration profile in the buffer layer. This VT-VSUB method was developed from Si MOSFET. For HFETs, the insulator is formed by epitaxially grown and heterogeneous semiconductor layer while for Si MOSFETs the insulator is amorphous SiO2. Except that HFETs have higher channel mobility due to the epitaxial insulator/semiconductor interface, HFETs and Si MOSFETs are basically the same in the respect of device physics. Based on these considerations, the feasibility of this VT-VSUB method for AlGaN/GaN HFETs was discussed. In the end, the buffer layer doping concentration was measured to be 2 × 1017cm-3, p-type, which is well consistent with the Mg concentration obtained from secondary ion mass spectroscopy (SIMS) measurement.

Improved metal-insulator-transition characteristics of ultrathin VO2 epitaxial films by optimized surface preparation of rutile TiO2 substrates

NASA Astrophysics Data System (ADS)

Martens, Koen; Aetukuri, Nagaphani; Jeong, Jaewoo; Samant, Mahesh G.; Parkin, Stuart S. P.

2014-02-01

Key to the growth of epitaxial, atomically thin films is the preparation of the substrates on which they are deposited. Here, we report the growth of atomically smooth, ultrathin films of VO2 (001), only ˜2 nm thick, which exhibit pronounced metal-insulator transitions, with a change in resistivity of ˜500 times, at a temperature that is close to that of films five times thicker. These films were prepared by pulsed laser deposition on single crystalline TiO2(001) substrates that were treated by dipping in acetone, HCl and HF in successive order, followed by an anneal at 700-750 °C in flowing oxygen. This pretreatment removes surface contaminants, TiO2 defects, and provides a terraced, atomically smooth surface.

Hybrid aerogel rigid ceramic fiber insulation and method of producing same

NASA Technical Reports Server (NTRS)

Barney, Andrea O. (Inventor); Heng, Vann (Inventor); Oka, Kris Shigeko (Inventor); Santos, Maryann (Inventor); Zinn, Alfred A. (Inventor); Droege, Michael (Inventor)

2004-01-01

A hybrid insulation material comprises of porous ceramic substrate material impregnated with nanoporous material and method of making the same is the topic of this invention. The porous substrate material has bulk density ranging from 6 to 20 lb/ft.sup.3 and is composed of about 60 to 80 wt % silica (SiO.sub.2) 20 to 40 wt % alumina (Al.sub.2 O.sub.3) fibers, and with about 0.1 to 1.0 wt % boron-containing constituent as the sintering agent. The nanoporous material has density ranging from 1.0 to 10 lb/ft.sup.3 and is either fully or partially impregnated into the substrate to block the pores, resulting in substantial reduction in conduction via radiation and convention. The nanoporous material used to impregnate the fiber substrate is preferably formed from a precursor of alkoxysilane, alcohol, water, and an acid or base catalyst for silica aerogels, and from a precursor of aluminum alkoxide, alcohol, water, and an acid or base catalyst for alumina aerogels.

Organic thin film transistor with a simplified planar structure

NASA Astrophysics Data System (ADS)

Zhang, Lei; Yu, Jungsheng; Zhong, Jian; Jiang, Yadong

2009-05-01

Organic thin film transistor (OTFT) with a simplified planar structure is described. The gate electrode and the source/drain electrodes of OTFT are processed in one planar structure. And these three electrodes are deposited on the glass substrate by DC sputtering technology using Cr/Ni target. Then the electrode layouts of different width length ratio are made by photolithography technology at the same time. Only one step of deposition and one step of photolithography is needed while conventional process takes at least two steps of deposition and two steps of photolithography. Metal is first prepared on the other side of glass substrate and electrode is formed by photolithography. Then source/drain electrode is prepared by deposition and photolithography on the side with the insulation layer. Compared to conventional process of OTFTs, the process in this work is simplified. After three electrodes prepared, the insulation layer is made by spin coating method. The organic material of polyimide is used as the insulation layer. A small molecular material of pentacene is evaporated on the insulation layer using vacuum deposition as the active layer. The process of OTFTs needs only three steps totally. A semi-auto probe stage is used to connect the three electrodes and the probe of the test instrument. A charge carrier mobility of 0.3 cm2 /V s, is obtained from OTFTs on glass substrates with and on/off current ratio of 105. The OTFTs with the planar structure using simplified process can simplify the device process and reduce the fabrication cost.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Effects of spin-orbit coupling and many-body correlations in STM transport through copper phthalocyanine.

PubMed

Siegert, Benjamin; Donarini, Andrea; Grifoni, Milena

2015-01-01

The interplay of exchange correlations and spin-orbit interaction (SOI) on the many-body spectrum of a copper phtalocyanine (CuPc) molecule and their signatures in transport are investigated. We first derive a minimal model Hamiltonian in a basis of frontier orbitals that is able to reproduce experimentally observed singlet-triplet splittings. In a second step SOI effects are included perturbatively. Major consequences of the SOI are the splitting of former degenerate levels and a magnetic anisotropy, which can be captured by an effective low-energy spin Hamiltonian. We show that scanning tunneling microscopy-based magnetoconductance measurements can yield clear signatures of both these SOI-induced effects.

Development of the Stress of Immigration Survey (SOIS): a Field Test among Mexican Immigrant Women

PubMed Central

Sternberg, Rosa Maria; Nápoles, Anna Maria; Gregorich, Steven; Paul, Steven; Lee, Kathryn A.; Stewart, Anita L.

2016-01-01

The Stress of Immigration Survey (SOIS) is a screening tool used to assess immigration-related stress. The mixed methods approach included concept development, pretesting, field-testing, and psychometric evaluation in a sample of 131 low-income women of Mexican descent. The 21-item SOIS screens for stress related to language; immigrant status; work issues; yearning for family and home country; and cultural dissonance. Mean scores ranged from 3.6 to 4.4 (1-5 scale, higher is more stress). Cronbach's alphas >.80 for all sub-scales. The SOIS may be a useful screening tool for detecting high levels of immigration-related stress in low-income Mexican immigrant women. PMID:26605954

SiGe-on-insulator fabricated via germanium condensation following high-fluence Ge+ ion implantation

NASA Astrophysics Data System (ADS)

Anthony, R.; Haddara, Y. M.; Crowe, I. F.; Knights, A. P.

2017-08-01

Germanium condensation is demonstrated using a two-step wet oxidation of germanium implanted Silicon-On-Insulator (SOI). Samples of 220 nm thick SOI are implanted with a nominal fluence of 5 × 1016 cm-2 Ge+ at an energy of 33 keV. Primary post-implantation wet oxidation is performed initially at 870 °C for 70 min, with the aim of capping the sample without causing significant dose loss via Ge evaporation through the sample surface. This is followed by a secondary higher temperature wet oxidation at either 900 °C, 1000 °C, or 1080 °C. The germanium retained dose and concentration profile, and the oxide thickness is examined after primary oxidation, and various secondary oxidation times, using Rutherford backscattering analysis. A mixed SiGe oxide is observed to form during the primary oxidation followed by a pure silicon oxide after higher temperature secondary oxidation. The peak germanium concentration, which varies with secondary oxidation condition, is found to range from 43 at. % to 95 at. %, while the FWHM of the Ge profile varies from 13 to 5 nm, respectively. It is also observed that both the diffusion of germanium and the rate of oxidation are enhanced at 870 and 900 °C compared to equilibrium expectations. Transmission electron microscopy of a representative sample with secondary oxidation at 1080 °C for 20 min shows that the SiGe layer is crystalline in nature and seeded from the underlying silicon. Raman spectroscopy is used to determine residual strain in the SiGe region following secondary oxidation. The strain is compressive in nature and increases with Ge concentration to a maximum of approximately 1% in the samples probed. In order to elucidate the physical mechanisms, which govern the implantation-condensation process, we fit the experimental profiles of the samples with a model that uses a modified segregation boundary condition; a modified linear rate constant for the oxidation; and an enhanced diffusion coefficient of germanium where the enhancement is inversely proportional to the temperature and decays with increasing time. Comparison of the modeled and experimental results shows reasonable agreement and allows conclusions to be made regarding the dominant physical mechanisms, despite the semi-empirical nature of the model used.

Influence of design variables on radiation hardness of silicon MINP solar cells

NASA Technical Reports Server (NTRS)

Anderson, W. A.; Solaun, S.; Rao, B. B.; Banerjee, S.

1985-01-01

Metal-insulator-N/P silicon (MINP) solar cells were fabricated using different substrate resistivity values, different N-layer designs, and different I-layer designs. A shallow junction into an 0.3 ohm-cm substrate gave best efficiency whereas a deeper junction into a 1 to 4 ohm-cm substrate gave improved radiation hardness. I-layer design variation did little to influence radiation hardness.

Synthesis of ultrathin polymer insulating layers by initiated chemical vapour deposition for low-power soft electronics.

PubMed

Moon, Hanul; Seong, Hyejeong; Shin, Woo Cheol; Park, Won-Tae; Kim, Mincheol; Lee, Seungwon; Bong, Jae Hoon; Noh, Yong-Young; Cho, Byung Jin; Yoo, Seunghyup; Im, Sung Gap

2015-06-01

Insulating layers based on oxides and nitrides provide high capacitance, low leakage, high breakdown field and resistance to electrical stresses when used in electronic devices based on rigid substrates. However, their typically high process temperatures and brittleness make it difficult to achieve similar performance in flexible or organic electronics. Here, we show that poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3) prepared via a one-step, solvent-free technique called initiated chemical vapour deposition (iCVD) is a versatile polymeric insulating layer that meets a wide range of requirements for next-generation electronic devices. Highly uniform and pure ultrathin films of pV3D3 with excellent insulating properties, a large energy gap (>8 eV), tunnelling-limited leakage characteristics and resistance to a tensile strain of up to 4% are demonstrated. The low process temperature, surface-growth character, and solvent-free nature of the iCVD process enable pV3D3 to be grown conformally on plastic substrates to yield flexible field-effect transistors as well as on a variety of channel layers, including organics, oxides, and graphene.

Micropatterning of poly(dimethylsiloxane) using a photoresist lift-off technique for selective electrical insulation of microelectrode arrays

PubMed Central

Park, Jaewon; Kim, Hyun Soo; Han, Arum

2009-01-01

A poly(dimethylsiloxane) (PDMS) patterning method based on a photoresist lift-off technique to make an electrical insulation layer with selective openings is presented. The method enables creating PDMS patterns with small features and various thicknesses without any limitation in the designs and without the need for complicated processes or expensive equipments. Patterned PDMS layers were created by spin-coating liquid phase PDMS on top of a substrate having sacrificial photoresist patterns, followed by a photoresist lift-off process. The thickness of the patterned PDMS layers could be accurately controlled (6.5–24 µm) by adjusting processing parameters such as PDMS spin-coating speeds, PDMS dilution ratios, and sacrificial photoresist thicknesses. PDMS features as small as 15 µm were successfully patterned and the effects of each processing parameter on the final patterns were investigated. Electrical resistance tests between adjacent electrodes with and without the insulation layer showed that the patterned PDMS layer functions properly as an electrical insulation layer. Biocompatibility of the patterned PDMS layer was confirmed by culturing primary neuron cells on top of the layer for up to two weeks. An extensive neuronal network was successfully formed, showing that this PDMS patterning method can be applied to various biosensing microdevices. The utility of this fabrication method was further demonstrated by successfully creating a patterned electrical insulation layer on flexible substrates containing multi-electrode arrays. PMID:19946385

Substrate-mediated strain effect on the role of thermal heating and electric field on metal-insulator transition in vanadium dioxide nanobeams.

PubMed

Kim, Min-Woo; Jung, Wan-Gil; Hyun-Cho; Bae, Tae-Sung; Chang, Sung-Jin; Jang, Ja-Soon; Hong, Woong-Ki; Kim, Bong-Joong

2015-06-04

Single-crystalline vanadium dioxide (VO2) nanostructures have recently attracted great attention because of their single domain metal-insulator transition (MIT) nature that differs from a bulk sample. The VO2 nanostructures can also provide new opportunities to explore, understand, and ultimately engineer MIT properties for applications of novel functional devices. Importantly, the MIT properties of the VO2 nanostructures are significantly affected by stoichiometry, doping, size effect, defects, and in particular, strain. Here, we report the effect of substrate-mediated strain on the correlative role of thermal heating and electric field on the MIT in the VO2 nanobeams by altering the strength of the substrate attachment. Our study may provide helpful information on controlling the properties of VO2 nanobeam for the device applications by changing temperature and voltage with a properly engineered strain.

Substrate-mediated strain effect on the role of thermal heating and electric field on metal-insulator transition in vanadium dioxide nanobeams

PubMed Central

Kim, Min-Woo; Jung, Wan-Gil; Hyun-Cho; Bae, Tae-Sung; Chang, Sung-Jin; Jang, Ja-Soon; Hong, Woong-Ki; Kim, Bong-Joong

2015-01-01

Single-crystalline vanadium dioxide (VO2) nanostructures have recently attracted great attention because of their single domain metal-insulator transition (MIT) nature that differs from a bulk sample. The VO2 nanostructures can also provide new opportunities to explore, understand, and ultimately engineer MIT properties for applications of novel functional devices. Importantly, the MIT properties of the VO2 nanostructures are significantly affected by stoichiometry, doping, size effect, defects, and in particular, strain. Here, we report the effect of substrate-mediated strain on the correlative role of thermal heating and electric field on the MIT in the VO2 nanobeams by altering the strength of the substrate attachment. Our study may provide helpful information on controlling the properties of VO2 nanobeam for the device applications by changing temperature and voltage with a properly engineered strain. PMID:26040637