Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

NASA Technical Reports Server (NTRS)

Leonard, Regis F. (Editor); Bhasin, Kul B. (Editor)

1991-01-01

Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure.

A framework for scalable parameter estimation of gene circuit models using structural information.

PubMed

Kuwahara, Hiroyuki; Fan, Ming; Wang, Suojin; Gao, Xin

2013-07-01

Systematic and scalable parameter estimation is a key to construct complex gene regulatory models and to ultimately facilitate an integrative systems biology approach to quantitatively understand the molecular mechanisms underpinning gene regulation. Here, we report a novel framework for efficient and scalable parameter estimation that focuses specifically on modeling of gene circuits. Exploiting the structure commonly found in gene circuit models, this framework decomposes a system of coupled rate equations into individual ones and efficiently integrates them separately to reconstruct the mean time evolution of the gene products. The accuracy of the parameter estimates is refined by iteratively increasing the accuracy of numerical integration using the model structure. As a case study, we applied our framework to four gene circuit models with complex dynamics based on three synthetic datasets and one time series microarray data set. We compared our framework to three state-of-the-art parameter estimation methods and found that our approach consistently generated higher quality parameter solutions efficiently. Although many general-purpose parameter estimation methods have been applied for modeling of gene circuits, our results suggest that the use of more tailored approaches to use domain-specific information may be a key to reverse engineering of complex biological systems. http://sfb.kaust.edu.sa/Pages/Software.aspx. Supplementary data are available at Bioinformatics online.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Slow-wave propagation on monolithic microwave integrated circuits with layered and non-layered structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tzuang, C.K.C.

1986-01-01

Various MMIC (monolithic microwave integrated circuit) planar waveguides have shown possible existence of a slow-wave propagation. In many practical applications of these slow-wave circuits, the semiconductor devices have nonuniform material properties that may affect the slow-wave propagation. In the first part of the dissertation, the effects of the nonuniform material properties are studied by a finite-element method. In addition, the transient pulse excitations of these slow-wave circuits also have great theoretical and practical interests. In the second part, the time-domain analysis of a slow-wave coplanar waveguide is presented.

Comprehensive photonics-electronics convergent simulation and its application to high-speed electronic circuit integration on a Si/Ge photonic chip

NASA Astrophysics Data System (ADS)

Takeda, Kotaro; Honda, Kentaro; Takeya, Tsutomu; Okazaki, Kota; Hiraki, Tatsurou; Tsuchizawa, Tai; Nishi, Hidetaka; Kou, Rai; Fukuda, Hiroshi; Usui, Mitsuo; Nosaka, Hideyuki; Yamamoto, Tsuyoshi; Yamada, Koji

2015-01-01

We developed a design technique for a photonics-electronics convergence system by using an equivalent circuit of optical devices in an electrical circuit simulator. We used the transfer matrix method to calculate the response of an optical device. This method used physical parameters and dimensions of optical devices as calculation parameters to design a device in the electrical circuit simulator. It also used an intermediate frequency to express the wavelength dependence of optical devices. By using both techniques, we simulated bit error rates and eye diagrams of optical and electrical integrated circuits and calculated influences of device structure change and wavelength shift penalty.

Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

2006-09-01

A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

PubMed

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

Conception et realisation d'un echantillonneur de grande vitesse en technologie HIGFET (transistor a effet de champ avec heterostructure et grille isolee)

NASA Astrophysics Data System (ADS)

Tazlauanu, Mihai

The research work reported in this thesis details a new fabrication technology for high speed integrated circuits in the broadest sense, including original contributions to device modeling, circuit simulation, integrated circuit design, wafer fabrication, micro-physical and electrical characterization, process flow and final device testing as part of an electrical system. The primary building block of this technology is the heterostructure insulated gate field effect transistor, HIGFET. We used an InP/InGaAs epitaxial heterostructure to ensure a high charge carrier mobility and hence obtain a higher operating frequency than that currently possible for silicon devices. We designed and built integrated circuits with two system architectures. The first architecture integrates the clock signal generator with the sample and hold circuitry on the InP die, while the second is a hybrid architecture of an InP sample and hold assembled with an external clock signal generator made with ECL circuits on GaAs. To generate the clock signals on the same die with the sample and hold circuits, we developed a digital circuit family based on an original inverter, appropriate for depletion mode NMOS technology. We used this circuit to design buffer amplifiers and ring oscillators. Four mask sets produced in a Cadence environment, have permitted the fabrication of test and working devices. Each new mask generation has reflected the previous achievements and has implemented new structures and circuit techniques. The fabrication technology has undergone successive modifications and refinements to optimize device manufacturing. Particular attention has been paid to the technological robustness. The plasma enhanced etching process (RIE) had been used for an exhaustive study for the statistical simulation of the technological steps. Electrical measurements, performed on the experimental samples, have permitted the modeling of the devices, technological processing to be adjusted and circuit design improved. Electrical measurements performed on dedicated test structures, during the fabrication cycle, allowed the identification and correction of some technological problems (ohmic contacts, current leakage, interconnection integrity, and thermal instabilities). Feedback corrections were validated by dedicated experiments with the experimental effort optimized by statistical techniques (factorial fractional design). (Abstract shortened by UMI.)

Very high speed integrated circuits - Into the second generation. V - The issues of standardization and technology insertion

NASA Astrophysics Data System (ADS)

Martin, J.

1982-04-01

It is shown that the fulfillment of very high speed integrated circuit (VHSIC) device development goals entails the restructuring of military electronics acquisition policy, standardization which produces the maximum number of systems and subsystems by means of the minimum number of flexible, broad-purpose, high-power semiconductors, and especially the standardization of bus structures incorporating a priorization system. It is expected that the Design Specification Handbook currently under preparation by the VHSIC program office of the DOD will make the design of such systems a task whose complexity is comparable to that of present integrated circuit electronics.

FIBER AND INTEGRATED OPTICS: Photodetector waveguide structures made of epitaxial InGaAs films and intended for integrated circuits manufactured from III-V semiconductor compounds

NASA Astrophysics Data System (ADS)

Shmal'ko, A. V.; Lamekin, V. F.; Smirnov, V. L.; Polyantsev, A. S.; Kogan, Yu I.; Babushkina, T. S.; Kuntsevich, T. S.; Peshkovskaya, O. G.

1990-08-01

Photodetector waveguide structures made of epitaxial InxGa1 - xAs solid-solution films were developed and investigated. These structures were intended for optical integrated circuits manufactured from III-V semiconductor compounds for operation in the wavelength range 1.0-1.5 μm. Two types of photodetector waveguide p-i-n structures were developed. They consisted of a composite waveguide and tunnel-coupled waveguides, respectively. A study was made of structural parameters, responsivity, spectral and time characteristics, and dark currents in photodetectors made of the waveguide structures. This investigation was carried out in the wavelength range 1.0-1.3 μm. The maximum spectral responsivity of one of the types of the waveguide photodetector was ~ 0.5 ± 0.1 A/W and the dark current did not exceed 10 - 7-10 - 8 A.

Silicon nitride tri-layer vertical Y-junction and 3D couplers with arbitrary splitting ratio for photonic integrated circuits.

PubMed

Shang, Kuanping; Pathak, Shibnath; Liu, Guangyao; Feng, Shaoqi; Li, Siwei; Lai, Weicheng; Yoo, S J B

2017-05-01

We designed and demonstrated a tri-layer Si₃N₄/SiO₂ photonic integrated circuit capable of vertical interlayer coupling with arbitrary splitting ratios. Based on this multilayer photonic integrated circuit platform with each layer thicknesses of 150 nm, 50 nm, and 150 nm, we designed and simulated the vertical Y-junctions and 3D couplers with arbitrary power splitting ratios between 1:10 and 10:1 and with negligible(< -50 dB) reflection. Based on the design, we fabricated and demonstrated tri-layer vertical Y-junctions with the splitting ratios of 1:1 and 3:2 with excess optical losses of 0.230 dB. Further, we fabricated and demonstrated the 1 × 3 3D couplers with the splitting ratio of 1:1:4 for symmetric structures and variable splitting ratio for asymmetric structures.

Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

NASA Technical Reports Server (NTRS)

Alt, Shannon

2016-01-01

Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Barfknecht, Andrew T. (Inventor); Garcia, Graham A. (Inventor); Russell, Stephen D. (Inventor); Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Nanoelectronics from the bottom up.

PubMed

Lu, Wei; Lieber, Charles M

2007-11-01

Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

Integrated circuit package with lead structure and method of preparing the same

NASA Technical Reports Server (NTRS)

Kennedy, B. W. (Inventor)

1973-01-01

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Integration of a photonic crystal polarization beam splitter and waveguide bend.

PubMed

Zheng, Wanhua; Xing, Mingxin; Ren, Gang; Johnson, Steven G; Zhou, Wenjun; Chen, Wei; Chen, Lianghui

2009-05-11

In this work, we present the design of an integrated photonic-crystal polarization beam splitter (PC-PBS) and a low-loss photonic-crystal 60 degrees waveguide bend. Firstly, the modal properties of the PC-PBS and the mechanism of the low-loss waveguide bend are investigated by the two-dimensional finite-difference time-domain (FDTD) method, and then the integration of the two devices is studied. It shows that, although the individual devices perform well separately, the performance of the integrated circuit is poor due to the multi-mode property of the PC-PBS. By introducing deformed airhole structures, a single-mode PC-PBS is proposed, which significantly enhance the performance of the circuit with the extinction ratios remaining above 20 dB for both transverse-electric (TE) and transverse-magnetic (TM) polarizations. Both the specific result and the general idea of integration design are promising in the photonic crystal integrated circuits in the future.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

A simple structure wavelet transform circuit employing function link neural networks and SI filters

NASA Astrophysics Data System (ADS)

Mu, Li; Yigang, He

2016-12-01

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1985-06-24

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, David B.

1987-01-01

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, David B.

1989-01-01

In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1985-08-23

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Planarization of metal films for multilevel interconnects

DOEpatents

Tuckerman, D.B.

1989-03-21

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

SEMICONDUCTOR INTEGRATED CIRCUITS: A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

NASA Astrophysics Data System (ADS)

Jizhi, Liu; Xingbi, Chen

2009-12-01

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

Monolithic FET structures for high-power control component applications

NASA Astrophysics Data System (ADS)

Shifrin, Mitchell B.; Katzin, Peter J.; Ayasli, Yalcin

1989-12-01

A monolithic FET switch is described that can be integrated with other monolithic functions or used as a discrete component in a microwave integrated circuit structure. This device increases the power-handling capability of the conventional single FET switch by an order of magnitude. It does this by overcoming the breakdown voltage limitation of the FET device. The design, fabrication, and performance of two high-power control components using these circuits are described as examples of the implementation of this technology. They are an L-band terminated single-pole, single-throw (SPST) switch and an L-band limiter).

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

NASA Technical Reports Server (NTRS)

Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

1991-01-01

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

An assessment of the impact of the Department of Defense very high speed integrated circuit program

NASA Astrophysics Data System (ADS)

1982-01-01

The technical and economic effects of the Department of Defense's (DoD) development program for very-high-speed integrated circuits (VHSIC) are examined. The probable effects of this program on the domestic aspects and international position of the integrated-circuit (IC) industry as they relate to the interests of the general public and the DoD are considered. The report presents a review of the unique DoD needs that motivate VHSIC research and development; an estimate of the degree of which these needs are likely to be met by the VHSIC program; a discussion of the effects of the program's demands for manpower, materials, and design and processing technologies; the problems connected with the program's technology export controls; and an assessment of the impact of the program on the structure of the U.S. integrated-circuit industry, its continued development and production of civilian consumer products, and its international competitive position.

Rolled-up inductor structure for a radiofrequency integrated circuit (RFIC)

DOEpatents

Li, Xiuling; Huang, Wen; Ferreira, Placid M.; Yu, Xin

2015-12-29

A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure.

Rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC)

DOEpatents

Li, Xiuling; Huang, Wen

2015-04-28

A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.

Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Gallium Arsenide Monolithic Optoelectronic Circuits

NASA Astrophysics Data System (ADS)

Bar-Chaim, N.; Katz, J.; Margalit, S.; Ury, I.; Wilt, D.; Yariv, A.

1981-07-01

The optical properties of GaAs make it a very useful material for the fabrication of optical emitters and detectors. GaAs also possesses electronic properties which allow the fabrication of high speed electronic devices which are superior to conventional silicon devices. Monolithic optoelectronic circuits are formed by the integration of optical and electronic devices on a single GaAs substrate. Integration of many devices is most easily accomplished on a semi-insulating (SI) sub-strate. Several laser structures have been fabricated on SI GaAs substrates. Some of these lasers have been integrated with Gunn diodes and with metal semiconductor field effect transistors (MESFETs). An integrated optical repeater has been demonstrated in which MESFETs are used for optical detection and electronic amplification, and a laser is used to regenerate the optical signal. Monolithic optoelectronic circuits have also been constructed on conducting substrates. A heterojunction bipolar transistor driver has been integrated with a laser on an n-type GaAs substrate.

Effective algorithm for routing integral structures with twolayer switching

NASA Astrophysics Data System (ADS)

Nazarov, A. V.; Shakhnov, V. A.; Vlasov, A. I.; Novikov, A. N.

2018-05-01

The paper presents an algorithm for routing switching objects such as large-scale integrated circuits (LSICs) with two layers of metallization, embossed printed circuit boards, microboards with pairs of wiring layers on each side, and other similar constructs. The algorithm allows eliminating the effect of mutual blocking of routes in the classical wave algorithm by implementing a special circuit of digital wave motion in two layers of metallization, allowing direct intersections of all circuit conductors in a combined layer. However, information about the belonging of the topology elements to the circuits is sufficient for layering and minimizing the number of contact holes. In addition, the paper presents a specific example which shows that, in contrast to the known routing algorithms using a wave model, just one byte of memory per discrete of the work field is sufficient to implement the proposed algorithm.

Design techniques for low-voltage analog integrated circuits

NASA Astrophysics Data System (ADS)

Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

2017-08-01

In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Photonic crystal ring resonator based optical filters for photonic integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, S., E-mail: mail2robinson@gmail.com

In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which ismore » highly suitable of photonic integrated circuits.« less

Tomography experiment of an integrated circuit specimen using 3 MeV electrons in the transmission electron microscope.

PubMed

Zhang, Hai-Bo; Zhang, Xiang-Liang; Wang, Yong; Takaoka, Akio

2007-01-01

The possibility of utilizing high-energy electron tomography to characterize the micron-scale three dimensional (3D) structures of integrated circuits has been demonstrated experimentally. First, electron transmission through a tilted SiO(2) film was measured with an ultrahigh-voltage electron microscope (ultra-HVEM) and analyzed from the point of view of elastic scattering of electrons, showing that linear attenuation of the logarithmic electron transmission still holds valid for effective specimen thicknesses up to 5 microm under 2 MV accelerating voltages. Electron tomography of a micron-order thick integrated circuit specimen including the Cu/via interconnect was then tried with 3 MeV electrons in the ultra-HVEM. Serial projection images of the specimen tilted at different angles over the range of +/-90 degrees were acquired, and 3D reconstruction was performed with the images by means of the IMOD software package. Consequently, the 3D structures of the Cu lines, via and void, were revealed by cross sections and surface rendering.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Digital circuits using universal logic gates

NASA Technical Reports Server (NTRS)

Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)

2004-01-01

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Integrating DNA strand-displacement circuitry with DNA tile self-assembly

PubMed Central

Zhang, David Yu; Hariadi, Rizal F.; Choi, Harry M.T.; Winfree, Erik

2013-01-01

DNA nanotechnology has emerged as a reliable and programmable way of controlling matter at the nanoscale through the specificity of Watson–Crick base pairing, allowing both complex self-assembled structures with nanometer precision and complex reaction networks implementing digital and analog behaviors. Here we show how two well-developed frameworks, DNA tile self-assembly and DNA strand-displacement circuits, can be systematically integrated to provide programmable kinetic control of self-assembly. We demonstrate the triggered and catalytic isothermal self-assembly of DNA nanotubes over 10 μm long from precursor DNA double-crossover tiles activated by an upstream DNA catalyst network. Integrating more sophisticated control circuits and tile systems could enable precise spatial and temporal organization of dynamic molecular structures. PMID:23756381

A novel high performance ESD power clamp circuit with a small area

NASA Astrophysics Data System (ADS)

Zhaonian, Yang; Hongxia, Liu; Li, Li; Qingqing, Zhuo

2012-09-01

A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10 ns RC time constant for a 0.18-μm process is proposed. A diode-connected NMOSFET is used to maintain a long delay time and save area. The special structure overcomes other shortcomings in this clamp circuit. Under fast power-up events, the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events, the special structure can keep the clamp MOSFET thoroughly off. Under a falsely triggered event, the special structure can turn off the clamp MOSFET in a short time. The clamp circuit can also reject the power supply noise effectively. Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up, maintains a 1.2 μs delay time and a 2.14 μs turn-off time, and reduces to about 70% of the RC time constant. It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.

Equivalent circuit modeling of a piezo-patch energy harvester on a thin plate with AC-DC conversion

NASA Astrophysics Data System (ADS)

Bayik, B.; Aghakhani, A.; Basdogan, I.; Erturk, A.

2016-05-01

As an alternative to beam-like structures, piezoelectric patch-based energy harvesters attached to thin plates can be readily integrated to plate-like structures in automotive, marine, and aerospace applications, in order to directly exploit structural vibration modes of the host system without mass loading and volumetric occupancy of cantilever attachments. In this paper, a multi-mode equivalent circuit model of a piezo-patch energy harvester integrated to a thin plate is developed and coupled with a standard AC-DC conversion circuit. Equivalent circuit parameters are obtained in two different ways: (1) from the modal analysis solution of a distributed-parameter analytical model and (2) from the finite-element numerical model of the harvester by accounting for two-way coupling. After the analytical modeling effort, multi-mode equivalent circuit representation of the harvester is obtained via electronic circuit simulation software SPICE. Using the SPICE software, electromechanical response of the piezoelectric energy harvester connected to linear and nonlinear circuit elements are computed. Simulation results are validated for the standard AC-AC and AC-DC configurations. For the AC input-AC output problem, voltage frequency response functions are calculated for various resistive loads, and they show excellent agreement with modal analysis-based analytical closed-form solution and with the finite-element model. For the standard ideal AC input-DC output case, a full-wave rectifier and a smoothing capacitor are added to the harvester circuit for conversion of the AC voltage to a stable DC voltage, which is also validated against an existing solution by treating the single-mode plate dynamics as a single-degree-of-freedom system.

System-on-Chip Considerations for Heterogeneous Integration of CMOS and Fluidic Bio-Interfaces.

PubMed

Datta-Chaudhuri, Timir; Smela, Elisabeth; Abshire, Pamela A

2016-12-01

CMOS chips are increasingly used for direct sensing and interfacing with fluidic and biological systems. While many biosensing systems have successfully combined CMOS chips for readout and signal processing with passive sensing arrays, systems that co-locate sensing with active circuits on a single chip offer significant advantages in size and performance but increase the complexity of multi-domain design and heterogeneous integration. This emerging class of lab-on-CMOS systems also poses distinct and vexing technical challenges that arise from the disparate requirements of biosensors and integrated circuits (ICs). Modeling these systems must address not only circuit design, but also the behavior of biological components on the surface of the IC and any physical structures. Existing tools do not support the cross-domain simulation of heterogeneous lab-on-CMOS systems, so we recommend a two-step modeling approach: using circuit simulation to inform physics-based simulation, and vice versa. We review the primary lab-on-CMOS implementation challenges and discuss practical approaches to overcome them. Issues include new versions of classical challenges in system-on-chip integration, such as thermal effects, floor-planning, and signal coupling, as well as new challenges that are specifically attributable to biological and fluidic domains, such as electrochemical effects, non-standard packaging, surface treatments, sterilization, microfabrication of surface structures, and microfluidic integration. We describe these concerns as they arise in lab-on-CMOS systems and discuss solutions that have been experimentally demonstrated.

Planarization of metal films for multilevel interconnects by pulsed laser heating

DOEpatents

Tuckerman, David B.

1987-01-01

In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

Flexible micro flow sensor for micro aerial vehicles

NASA Astrophysics Data System (ADS)

Zhu, Rong; Que, Ruiyi; Liu, Peng

2017-12-01

This article summarizes our studies on micro flow sensors fabricated on a flexible polyimide circuit board by a low-cost hybrid process of thin-film deposition and circuit printing. The micro flow sensor has merits of flexibility, structural simplicity, easy integrability with circuits, and good sensing performance. The sensor, which adheres to an object surface, can detect the surface flow around the object. In our study, we install the fabricated micro flow sensors on micro aerial vehicles (MAVs) to detect the surface flow variation around the aircraft wing and deduce the aerodynamic parameters of the MAVs in flight. Wind tunnel experiments using the sensors integrated with the MAVs are also conducted.

Multiple piezo-patch energy harvesters integrated to a thin plate with AC-DC conversion: analytical modeling and numerical validation

NASA Astrophysics Data System (ADS)

Aghakhani, Amirreza; Basdogan, Ipek; Erturk, Alper

2016-04-01

Plate-like components are widely used in numerous automotive, marine, and aerospace applications where they can be employed as host structures for vibration based energy harvesting. Piezoelectric patch harvesters can be easily attached to these structures to convert the vibrational energy to the electrical energy. Power output investigations of these harvesters require accurate models for energy harvesting performance evaluation and optimization. Equivalent circuit modeling of the cantilever-based vibration energy harvesters for estimation of electrical response has been proposed in recent years. However, equivalent circuit formulation and analytical modeling of multiple piezo-patch energy harvesters integrated to thin plates including nonlinear circuits has not been studied. In this study, equivalent circuit model of multiple parallel piezoelectric patch harvesters together with a resistive load is built in electronic circuit simulation software SPICE and voltage frequency response functions (FRFs) are validated using the analytical distributedparameter model. Analytical formulation of the piezoelectric patches in parallel configuration for the DC voltage output is derived while the patches are connected to a standard AC-DC circuit. The analytic model is based on the equivalent load impedance approach for piezoelectric capacitance and AC-DC circuit elements. The analytic results are validated numerically via SPICE simulations. Finally, DC power outputs of the harvesters are computed and compared with the peak power amplitudes in the AC output case.

Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

PubMed

Cai, Jinguang; Lv, Chao; Watanabe, Akira

2018-01-10

Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

Integrated logic circuits using single-atom transistors

PubMed Central

Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.

2011-01-01

Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

The tapered slot antenna - A new integrated element for millimeter-wave applications

NASA Technical Reports Server (NTRS)

Yngvesson, K. Sigfrid; Kim, Young-Sik; Korzeniowski, T. L.; Kollberg, Erik L.; Johansson, Joakim F.

1989-01-01

Tapered slot antennas (TSAs) with a number of potential applications as single elements and focal-plane arrays are discussed. TSAs are fabricated with photolithographic techniques and integrated in either hybrid or MMIC circuits with receiver or transmitter components. They offer considerably narrower beams than other integrated antenna elements and have high aperture efficiency and packing density as array elements. Both the circuit and radiation properties of TSAs are reviewed. Topics covered include: antenna beamwidth, directivity, and gain of single-element TSAs; their beam shape and the effect of different taper shapes; and the input impedance and the effects of using thick dielectrics. These characteristics are also given for TSA arrays, as are the circuit properties of the array elements. Different array structures and their applications are also described.

Flip-flop resolving time test circuit

NASA Technical Reports Server (NTRS)

Rosenberger, F.; Chaney, T. J.

1982-01-01

Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.

Toolbox for the design of LiNbO3-based passive and active integrated quantum circuits

NASA Astrophysics Data System (ADS)

Sharapova, P. R.; Luo, K. H.; Herrmann, H.; Reichelt, M.; Meier, T.; Silberhorn, C.

2017-12-01

We present and discuss perspectives of current developments on advanced quantum optical circuits monolithically integrated in the lithium niobate platform. A set of basic components comprising photon pair sources based on parametric down conversion (PDC), passive routing elements and active electro-optically controllable switches and polarisation converters are building blocks of a toolbox which is the basis for a broad range of diverse quantum circuits. We review the state-of-the-art of these components and provide models that properly describe their performance in quantum circuits. As an example for applications of these models we discuss design issues for a circuit providing on-chip two-photon interference. The circuit comprises a PDC section for photon pair generation followed by an actively controllable modified mach-Zehnder structure for observing Hong-Ou-Mandel interference. The performance of such a chip is simulated theoretically by taking even imperfections of the properties of the individual components into account.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

NASA Astrophysics Data System (ADS)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Self-contained sub-millimeter wave rectifying antenna integrated circuit

NASA Technical Reports Server (NTRS)

Siegel, Peter H. (Inventor)

2004-01-01

The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

Transferrable monolithic III-nitride photonic circuit for multifunctional optoelectronics

NASA Astrophysics Data System (ADS)

Shi, Zheng; Gao, Xumin; Yuan, Jialei; Zhang, Shuai; Jiang, Yan; Zhang, Fenghua; Jiang, Yuan; Zhu, Hongbo; Wang, Yongjin

2017-12-01

A monolithic III-nitride photonic circuit with integrated functionalities was implemented by integrating multiple components with different functions into a single chip. In particular, the III-nitride-on-silicon platform is used as it integrates a transmitter, a waveguide, and a receiver into a suspended III-nitride membrane via a wafer-level procedure. Here, a 0.8-mm-diameter suspended device architecture is directly transferred from silicon to a foreign substrate by mechanically breaking the support beams. The transferred InGaN/GaN multiple-quantum-well diode (MQW-diode) exhibits a turn-on voltage of 2.8 V with a dominant electroluminescence peak at 453 nm. The transmitter and receiver share an identical InGaN/GaN MQW structure, and the integrated photonic circuit inherently works for on-chip power monitoring and in-plane visible light communication. The wire-bonded monolithic photonic circuit on glass experimentally demonstrates in-plane data transmission at 120 Mb/s, paving the way for diverse applications in intelligent displays, in-plane light communication, flexible optical sensors, and wearable III-nitride optoelectronics.

Segregated cholinergic transmission modulates dopamine neurons integrated in distinct functional circuits.

PubMed

Dautan, Daniel; Souza, Albert S; Huerta-Ocampo, Icnelia; Valencia, Miguel; Assous, Maxime; Witten, Ilana B; Deisseroth, Karl; Tepper, James M; Bolam, J Paul; Gerdjikov, Todor V; Mena-Segovia, Juan

2016-08-01

Dopamine neurons in the ventral tegmental area (VTA) receive cholinergic innervation from brainstem structures that are associated with either movement or reward. Whereas cholinergic neurons of the pedunculopontine nucleus (PPN) carry an associative/motor signal, those of the laterodorsal tegmental nucleus (LDT) convey limbic information. We used optogenetics and in vivo juxtacellular recording and labeling to examine the influence of brainstem cholinergic innervation of distinct neuronal subpopulations in the VTA. We found that LDT cholinergic axons selectively enhanced the bursting activity of mesolimbic dopamine neurons that were excited by aversive stimulation. In contrast, PPN cholinergic axons activated and changed the discharge properties of VTA neurons that were integrated in distinct functional circuits and were inhibited by aversive stimulation. Although both structures conveyed a reinforcing signal, they had opposite roles in locomotion. Our results demonstrate that two modes of cholinergic transmission operate in the VTA and segregate the neurons involved in different reward circuits.

Organic membrane photonic integrated circuits (OMPICs).

PubMed

Amemiya, Tomohiro; Kanazawa, Toru; Hiratani, Takuo; Inoue, Daisuke; Gu, Zhichen; Yamasaki, Satoshi; Urakami, Tatsuhiro; Arai, Shigehisa

2017-08-07

We propose the concept of organic membrane photonic integrated circuits (OMPICs), which incorporate various functions needed for optical signal processing into a flexible organic membrane. We describe the structure of several devices used within the proposed OMPICs (e.g., transmission lines, I/O couplers, phase shifters, photodetectors, modulators), and theoretically investigate their characteristics. We then present a method of fabricating the photonic devices monolithically in an organic membrane and demonstrate the operation of transmission lines and I/O couplers, the most basic elements of OMPICs.

Additive manufacturing of hybrid circuits

DOE PAGES

Bell, Nelson S.; Sarobol, Pylin; Cook, Adam; ...

2016-03-26

There is a rising interest in developing functional electronics using additively manufactured components. Considerations in materials selection and pathways to forming hybrid circuits and devices must demonstrate useful electronic function; must enable integration; and must complement the complex shape, low cost, high volume, and high functionality of structural but generally electronically passive additively manufactured components. This article reviews several emerging technologies being used in industry and research/development to provide integration advantages of fabricating multilayer hybrid circuits or devices. First, we review a maskless, noncontact, direct write (DW) technology that excels in the deposition of metallic colloid inks for electrical interconnects.more » Second, we review a complementary technology, aerosol deposition (AD), which excels in the deposition of metallic and ceramic powder as consolidated, thick conformal coatings and is additionally patternable through masking. As a result, we show examples of hybrid circuits/devices integrated beyond 2-D planes, using combinations of DW or AD processes and conventional, established processes.« less

The Electric Circuit as a System: A New Approach.

ERIC Educational Resources Information Center

Hartel, H.

1982-01-01

Traditionally, the terms "current,""voltage," and "resistance" are introduced in a linear sequence according to structure of the discipline and based on measurement operations. A new approach is discussed, the terms being introduced simultaneously in a qualitative way, using the system aspect of the electric circuit as an integrative base.…

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

NASA Astrophysics Data System (ADS)

Yashin, A. A.

1985-04-01

A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

Design, Simulation and Characteristics Research of the Interface Circuit based on nano-polysilicon thin films pressure sensor

NASA Astrophysics Data System (ADS)

Zhao, Xiaosong; Zhao, Xiaofeng; Yin, Liang

2018-03-01

This paper presents a interface circuit for nano-polysilicon thin films pressure sensor. The interface circuit includes consist of instrument amplifier and Analog-to-Digital converter (ADC). The instrumentation amplifier with a high common mode rejection ratio (CMRR) is implemented by three stages current feedback structure. At the same time, in order to satisfy the high precision requirements of pressure sensor measure system, the 1/f noise corner of 26.5 mHz can be achieved through chopping technology at a noise density of 38.2 nV/sqrt(Hz).Ripple introduced by chopping technology adopt continuous ripple reduce circuit (RRL), which achieves the output ripple level is lower than noise. The ADC achieves 16 bits significant digit by adopting sigma-delta modulator with fourth-order single-bit structure and digital decimation filter, and finally achieves high precision integrated pressure sensor interface circuit.

Multiplier Architecture for Coding Circuits

NASA Technical Reports Server (NTRS)

Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.

1986-01-01

Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.

Experimental Verification of Guided-Wave Lumped Circuits Using Waveguide Metamaterials

NASA Astrophysics Data System (ADS)

Li, Yue; Zhang, Zhijun

2018-04-01

Through the construction and characterization in microwave frequencies, we experimentally demonstrate our recently developed theory of waveguide lumped circuits, i.e., waveguide metatronics [Sci. Adv. 2, e1501790 (2016), 10.1126/sciadv.1501790], as a method to design subwavelength-scaled analog circuits. In the paradigm of waveguide metatronics, numbers of lumped inductors and capacitors are easily integrated functionally inside the waveguide, which is an irreplaceable transmission line in millimeter-wave and terahertz systems with the advantages of low radiation loss and low crosstalk. An example of multiple-ordered metatronic filters with layered structures is fabricated utilizing the technique of substrate integrated waveguides, which can be easily constructed by the printed-circuit-board process. The materials used in the construction are also typical microwave materials with positive permittivity, low loss, and negligible dispersion, imitating the plasmonic materials with negative permittivity in the optical domain. The results verify the theory of waveguide metatronics, which provides an efficient platform of functional lumped circuit design for guided-wave processing.

Numerical investigation of a tunable band-pass plasmonic filter with a hollow-core ring resonator

NASA Astrophysics Data System (ADS)

Setayesh, Amir; Mirnaziry, S. Reza; Sadegh Abrishamian, Mohammad

2011-03-01

In this study, a compact nanoscale plasmonic filter which consists of two metal-insulator-metal (MIM) waveguides coupled to each other by a rectangular ring resonator is presented and investigated numerically. The propagating modes of surface plasmon polaritons (SPPs) are studied in this structure. By replacing a portion of the ring core with air, while the outer dimensions of the structure are kept constant, we illustrate the possibility of the redshift of resonant wavelengths in order to tune the resonance modes. This feature is useful for integrated circuits in which we have limitations on the outer dimensions of the filter structure and it is not possible to enlarge the dimension of the ring resonator to reach longer resonant wavelengths. The corresponding results are illustrated by the 2D finite-difference time-domain (FDTD) method. The proposed structure has potential applications in plasmonic integrated circuits and can be simply fabricated.

Roughness measurements on coupling structures for optical interconnections integrated on a printed circuit board

NASA Astrophysics Data System (ADS)

Hendrickx, Nina; Van Erps, Jürgen; Suyal, Himanshu; Taghizadeh, Mohammad; Thienpont, Hugo; Van Daele, Peter

2006-04-01

In this paper, laser ablation (at UGent), deep proton writing (at VUB) and laser direct writing (at HWU) are presented as versatile technologies that can be used for the fabrication of coupling structures for optical interconnections integrated on a printed circuit board (PCB). The optical layer, a highly cross-linked acrylate based polymer, is applied on an FR4 substrate. Both laser ablation and laser direct writing are used for the definition of arrays of multimode optical waveguides, which guide the light in the plane of the optical layer. In order to couple light vertically in/out of the plane of the optical waveguides, coupling structures have to be integrated into the optical layer. Out-of-plane turning mirrors, that deflect the light beam over 90°, are used for this purpose. The surface roughness and angle of three mirror configurations are evaluated: a laser ablated one that is integrated into the optical waveguide, a laser direct written one that is also directly written onto the waveguide and a DPW insert that is plugged into a cavity into the waveguiding layer.

On-clip high frequency reliability and failure test structures

DOEpatents

Snyder, Eric S.; Campbell, David V.

1997-01-01

Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer.

Unexplained Obstruction of an Integrated Cardiotomy Filter During Cardiopulmonary Bypass.

PubMed

Alwardt, Cory M; Wilson, Donald S; Pajaro, Octavio E

2017-03-01

Cardiopulmonary bypass (CPB) is considered relatively safe in most cases, yet is not complication free. We present a case of an integrated cardiotomy filter obstruction during CPB, requiring circuit reconfiguration. Approximately an hour after uneventful initiation of CPB the integrated cardiotomy filter became obstructed over several minutes, requiring circuit reconfiguration using an external cardiotomy filter to maintain functionality. Following reconfiguration, CPB was maintained with a fully functional circuit allowing safe patient support throughout the remainder of CPB. Postoperatively, there was no sign of thrombus or mechanical obstruction of the filter, which was sent to the manufacturer for analysis. The cause of the obstruction was unclear even after chemical analysis, visual inspection, and a review of all techniques and products to which the patient was exposed. The patient had a generally routine hospital stay, with no signs or symptoms related to the incident. To our knowledge, this is the first report describing an obstructed integrated cardiotomy filter. An appropriate readiness plan for such an incident includes proper venting of the filter chamber, a method for detecting an obstruction, and a plan for circuit reconfiguration. This case illustrates the need for a formal reporting structure for incidents or "near miss" incidents during CPB.

A tale of two species: Neural integration in zebrafish and monkeys.

PubMed

Joshua, M; Lisberger, S G

2015-06-18

Selection of a model organism creates tension between competing constraints. The recent explosion of modern molecular techniques has revolutionized the analysis of neural systems in organisms that are amenable to genetic techniques. Yet, the non-human primate remains the gold-standard for the analysis of the neural basis of behavior, and as a bridge to the operation of the human brain. The challenge is to generalize across species in a way that exposes the operation of circuits as well as the relationship of circuits to behavior. Eye movements provide an opportunity to cross the bridge from mechanism to behavior through research on diverse species. Here, we review experiments and computational studies on a circuit function called "neural integration" that occurs in the brainstems of larval zebrafish, primates, and species "in between". We show that analysis of circuit structure using modern molecular and imaging approaches in zebrafish has remarkable explanatory power for details of the responses of integrator neurons in the monkey. The combination of research from the two species has led to a much stronger hypothesis for the implementation of the neural integrator than could have been achieved using either species alone. Copyright © 2014 IBRO. Published by Elsevier Ltd. All rights reserved.

Low-dielectric constant insulators for future integrated circuits and packages.

PubMed

Kohl, Paul A

2011-01-01

Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

Neural CMOS-integrated circuit and its application to data classification.

PubMed

Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

2012-05-01

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

Advanced 3-V semiconductor technology assessment

NASA Technical Reports Server (NTRS)

Nowogrodzki, M.

1983-01-01

Components required for extensions of currently planned space communications systems are discussed for large antennas, crosslink systems, single sideband systems, Aerostat systems, and digital signal processing. Systems using advanced modulation concepts and new concepts in communications satellites are included. The current status and trends in materials technology are examined with emphasis on bulk growth of semi-insulating GaAs and InP, epitaxial growth, and ion implantation. Microwave solid state discrete active devices, multigigabit rate GaAs digital integrated circuits, microwave integrated circuits, and the exploratory development of GaInAs devices, heterojunction devices, and quasi-ballistic devices is considered. Competing technologies such as RF power generation, filter structures, and microwave circuit fabrication are discussed. The fundamental limits of semiconductor devices and problems in implementation are explored.

Superconducting Multilayer High-Density Flexible Printed Circuit Board for Very High Thermal Resistance Interconnections

NASA Astrophysics Data System (ADS)

de la Broïse, Xavier; Le Coguie, Alain; Sauvageot, Jean-Luc; Pigot, Claude; Coppolani, Xavier; Moreau, Vincent; d'Hollosy, Samuel; Knarosovski, Timur; Engel, Andreas

2018-05-01

We have successively developed two superconducting flexible PCBs for cryogenic applications. The first one is monolayer, includes 552 tracks (10 µm wide, 20 µm spacing), and receives 24 wire-bonded integrated circuits. The second one is multilayer, with one track layer between two shielding layers interconnected by microvias, includes 37 tracks, and can be interconnected at both ends by wire bonding or by connectors. The first cold measurements have been performed and show good performances. The novelty of these products is, for the first one, the association of superconducting materials with very narrow pitch and bonded integrated circuits and, for the second one, the introduction of a superconducting multilayer structure interconnected by vias which is, to our knowledge, a world-first.

Gigahertz flexible graphene transistors for microwave integrated circuits.

PubMed

Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

2014-08-26

Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bell, Nelson S.; Sarobol, Pylin; Cook, Adam

There is a rising interest in developing functional electronics using additively manufactured components. Considerations in materials selection and pathways to forming hybrid circuits and devices must demonstrate useful electronic function; must enable integration; and must complement the complex shape, low cost, high volume, and high functionality of structural but generally electronically passive additively manufactured components. This article reviews several emerging technologies being used in industry and research/development to provide integration advantages of fabricating multilayer hybrid circuits or devices. First, we review a maskless, noncontact, direct write (DW) technology that excels in the deposition of metallic colloid inks for electrical interconnects.more » Second, we review a complementary technology, aerosol deposition (AD), which excels in the deposition of metallic and ceramic powder as consolidated, thick conformal coatings and is additionally patternable through masking. As a result, we show examples of hybrid circuits/devices integrated beyond 2-D planes, using combinations of DW or AD processes and conventional, established processes.« less

Design of a cross-connected charge pump for energy harvesting systems

NASA Astrophysics Data System (ADS)

Eguchi, K.; Fujisaki, H.; Asadi, F.; Oota, I.

2018-03-01

For energy harvesting systems, a novel charge pump with cross-connected structure is proposed in this paper. Owing to the cross-connected structure, the proposed charge pump can offer the output voltage to the output load at every phase. Furthermore, the proposed charge pump can reduce the number of circuit stages from the conventional charge pump. For above-mentioned reasons, the proposed charge pump can realize not only smaller internal resistance but also smaller output capacitance than the conventional charge pump. The theoretical analysis and simulation program with integrated circuit emphasis (SPICE) simulation demonstrate that the proposed charge pump outperforms the conventional charge pump in the point of power efficiency and circuit speed.

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

1995-01-01

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Integrating anatomy and function for zebrafish circuit analysis.

PubMed

Arrenberg, Aristides B; Driever, Wolfgang

2013-01-01

Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function.

Soldering Tool for Integrated Circuits

NASA Technical Reports Server (NTRS)

Takahashi, Ted H.

1987-01-01

Many connections soldered simultaneously in confined spaces. Improved soldering tool bonds integrated circuits onto printed-circuit boards. Intended especially for use with so-called "leadless-carrier" integrated circuits.

On-clip high frequency reliability and failure test structures

DOEpatents

Snyder, E.S.; Campbell, D.V.

1997-04-29

Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer. 22 figs.

The Topographical Mapping in Drosophila Central Complex Network and Its Signal Routing

PubMed Central

Chang, Po-Yen; Su, Ta-Shun; Shih, Chi-Tin; Lo, Chung-Chuan

2017-01-01

Neural networks regulate brain functions by routing signals. Therefore, investigating the detailed organization of a neural circuit at the cellular levels is a crucial step toward understanding the neural mechanisms of brain functions. To study how a complicated neural circuit is organized, we analyzed recently published data on the neural circuit of the Drosophila central complex, a brain structure associated with a variety of functions including sensory integration and coordination of locomotion. We discovered that, except for a small number of “atypical” neuron types, the network structure formed by the identified 194 neuron types can be described by only a few simple mathematical rules. Specifically, the topological mapping formed by these neurons can be reconstructed by applying a generation matrix on a small set of initial neurons. By analyzing how information flows propagate with or without the atypical neurons, we found that while the general pattern of signal propagation in the central complex follows the simple topological mapping formed by the “typical” neurons, some atypical neurons can substantially re-route the signal pathways, implying specific roles of these neurons in sensory signal integration. The present study provides insights into the organization principle and signal integration in the central complex. PMID:28443014

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Analysis of photonic spot profile converter and bridge structure on SOI platform for horizontal and vertical integration

NASA Astrophysics Data System (ADS)

Majumder, Saikat; Jha, Amit Kr.; Biswas, Aishik; Banerjee, Debasmita; Ganguly, Dipankar; Chakraborty, Rajib

2017-08-01

Horizontal spot size converter required for horizontal light coupling and vertical bridge structure required for vertical integration are designed on high index contrast SOI platform in order to form more compact integrated photonic circuits. Both the structures are based on the concept of multimode interference. The spot size converter can be realized by successive integration of multimode interference structures with reducing dimension on horizontal plane, whereas the optical bridge structure consists of a number of vertical multimode interference structure connected by single mode sections. The spot size converter can be modified to a spot profile converter when the final single mode waveguide is replaced by a slot waveguide. Analysis have shown that by using three multimode sections in a spot size converter, an Gaussian input having spot diameter of 2.51 μm can be converted to a spot diameter of 0.25 μm. If the output single mode section is replaced by a slot waveguide, this input profile can be converted to a flat top profile of width 50 nm. Similarly, vertical displacement of 8μm is possible by using a combination of two multimode sections and three single mode sections in the vertical bridge structure. The analyses of these two structures are carried out for both TE and TM modes at 1550 nm wavelength using the semi analytical matrix method which is simple and fast in computation time and memory. This work shows that the matrix method is equally applicable for analysis of horizontally as well as vertically integrated photonic circuit.

Nonlinear interface between the piezoelectric harvesting structure and the modulating circuit of an energy harvester with a real storage battery.

PubMed

Hu, Yuantai; Xue, Huan; Hu, Ting; Hu, Hongping

2008-01-01

This paper studies the performance of an energy harvester with a piezoelectric bimorph (PB) and a real electrochemical battery (ECB), both are connected as an integrated system through a rectified dc-dc converter (DDC). A vibrating PB can scavenge energy from the operating environment by the electromechanical coupling. A DDC can effectively match the optimal output voltage of the harvesting structure to the battery voltage. To raise the output power density of PB, a synchronized switch harvesting inductor (SSHI) is used in parallel with the harvesting structure to reverse the voltage through charge transfer between the output electrodes at the transition moments from closed-to open-circuit. Voltage reversal results in earlier arrival of rectifier conduction because the output voltage phases of any two adjacent closed-circuit states are just opposite each other. In principle, a PB is with a smaller, flexural stiffness under closed-circuit condition than under open-circuit condition. Thus, the PB subjected to longer closed-circuit condition will be easier to be accelerated. A larger flexural velocity makes the PB to deflect with larger amplitude, which implies that more mechanical energy will be converted into an electric one. Nonlinear interface between the vibrating PB and the modulating circuit is analyzed in detail, and the effects of SSHI and DDC on the charging efficiency of the storage battery are researched numerically. It was found that the introduction of a DDC in the modulating circuit and an SSHI in the harvesting structure can raise the charging efficiency by several times.

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2011-01-01

A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

19 CFR 10.14 - Fabricated components subject to the exemption.

Code of Federal Regulations, 2010 CFR

2010-04-01

... assembled, such as transistors, diodes, integrated circuits, machinery parts, or precut parts of wearing..., or integrated circuit wafers containing individual integrated circuit dice which have been scribed or... resulted in a substantial transformation of the foreign copper ingots. Example 2. An integrated circuit...

Optogenetic interrogation of neural circuits: technology for probing mammalian brain structures

PubMed Central

Zhang, Feng; Gradinaru, Viviana; Adamantidis, Antoine R; Durand, Remy; Airan, Raag D; de Lecea, Luis; Deisseroth, Karl

2015-01-01

Elucidation of the neural substrates underlying complex animal behaviors depends on precise activity control tools, as well as compatible readout methods. Recent developments in optogenetics have addressed this need, opening up new possibilities for systems neuroscience. Interrogation of even deep neural circuits can be conducted by directly probing the necessity and sufficiency of defined circuit elements with millisecond-scale, cell type-specific optical perturbations, coupled with suitable readouts such as electrophysiology, optical circuit dynamics measures and freely moving behavior in mammals. Here we collect in detail our strategies for delivering microbial opsin genes to deep mammalian brain structures in vivo, along with protocols for integrating the resulting optical control with compatible readouts (electrophysiological, optical and behavioral). The procedures described here, from initial virus preparation to systems-level functional readout, can be completed within 4–5 weeks. Together, these methods may help in providing circuit-level insight into the dynamics underlying complex mammalian behaviors in health and disease. PMID:20203662

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

HDL to verification logic translator

NASA Technical Reports Server (NTRS)

Gambles, J. W.; Windley, P. J.

1992-01-01

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

A novel integrated structure with a radial displacement sensor and a permanent magnet biased radial magnetic bearing.

PubMed

Sun, Jinji; Zhang, Yin

2014-01-24

In this paper, a novel integrated structure is proposed in order to reduce the axial length of the high speed of a magnetically suspended motor (HSMSM) to ensure the maximum speed, which combines radial displacement sensor probes and the permanent magnet biased radial magnetic bearing in HSMSM. The sensor probes are integrated in the magnetic bearing, and the sensor preamplifiers are placed in the control system of the HSMSM, separate from the sensor probes. The proposed integrated structure can save space in HSMSMs, improve the working frequency, reduce the influence of temperature on the sensor circuit, and improve the stability of HSMSMs.

Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

DTIC Science & Technology

2016-04-01

with Al top electrodes and Cu bottom electrodes. ................... 9 Figure 4. SPICE netlist structure...memory elements play a part in logic gate. 4.4.2 Simulation SPICE Simulation Program for Integrated Circuits Emphasis ( SPICE ) is a general-purpose...analog circuit simulator that was developed at the Electronics Research Laboratory of the University of California, Berkeley [6]. In 1975, SPICE

IIIV/Si Nanoscale Lasers and Their Integration with Silicon Photonics

NASA Astrophysics Data System (ADS)

Bondarenko, Olesya

The rapidly evolving global information infrastructure requires ever faster data transfer within computer networks and stations. Integrated chip scale photonics can pave the way to accelerated signal manipulation and boost bandwidth capacity of optical interconnects in a compact and ergonomic arrangement. A key building block for integrated photonic circuits is an on-chip laser. In this dissertation we explore ways to reduce the physical footprint of semiconductor lasers and make them suitable for high density integration on silicon, a standard material platform for today's integrated circuits. We demonstrated the first room temperature metalo-dielectric nanolaser, sub-wavelength in all three dimensions. Next, we demonstrated a nanolaser on silicon, showing the feasibility of its integration with this platform. We also designed and realized an ultracompact feedback laser with edge-emitting structure, amenable for in-plane coupling with a standard silicon waveguide. Finally, we discuss the challenges and propose solutions for improvement of the device performance and practicality.

Hierarchical hybrid control of manipulators: Artificial intelligence in large scale integrated circuits

NASA Technical Reports Server (NTRS)

Greene, P. H.

1972-01-01

Both in practical engineering and in control of muscular systems, low level subsystems automatically provide crude approximations to the proper response. Through low level tuning of these approximations, the proper response variant can emerge from standardized high level commands. Such systems are expressly suited to emerging large scale integrated circuit technology. A computer, using symbolic descriptions of subsystem responses, can select and shape responses of low level digital or analog microcircuits. A mathematical theory that reveals significant informational units in this style of control and software for realizing such information structures are formulated.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oda, H., E-mail: h-oda@photon.chitose.ac.jp; Yamanaka, A.; Ozaki, N.

The development of small sized laser operating above room temperature is important in the realization of optical integrated circuits. Recently, micro-lasers consisting of photonic crystals (PhCs) and whispering gallery mode cavities have been demonstrated. Optically pumped laser devices could be easily designed using photonic crystal-slab waveguides (PhC-WGs) with an air-bridge type structure. In this study, we observe lasing at 1.3μm from two-photon pumped InAs-quantum-dots embedded GaAs PhC-WGs above room temperature. This type of compact laser shows promise as a new light source in ultra-compact photonics integrated circuits.

Integrated Avalanche Photodiode arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Harmon, Eric S.

2017-04-18

The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed.

Integrated avalanche photodiode arrays

DOEpatents

Harmon, Eric S.

2015-07-07

The present disclosure includes devices for detecting photons, including avalanche photon detectors, arrays of such detectors, and circuits including such arrays. In some aspects, the detectors and arrays include a virtual beveled edge mesa structure surrounded by resistive material damaged by ion implantation and having side wall profiles that taper inwardly towards the top of the mesa structures, or towards the direction from which the ion implantation occurred. Other aspects are directed to masking and multiple implantation and/or annealing steps. Furthermore, methods for fabricating and using such devices, circuits and arrays are disclosed.

Fully 3D-Integrated Pixel Detectors for X-Rays

DOE PAGES

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul; ...

2016-01-01

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

Arrays of Carbon Nanotubes as RF Filters in Waveguides

NASA Technical Reports Server (NTRS)

Hoppe, Daniel; Hunt, Brian; Hoenk, Michael; Noca, Flavio; Xu, Jimmy

2003-01-01

Brushlike arrays of carbon nanotubes embedded in microstrip waveguides provide highly efficient (high-Q) mechanical resonators that will enable ultraminiature radio-frequency (RF) integrated circuits. In its basic form, this invention is an RF filter based on a carbon nanotube array embedded in a microstrip (or coplanar) waveguide, as shown in Figure 1. In addition, arrays of these nanotube-based RF filters can be used as an RF filter bank. Applications of this new nanotube array device include a variety of communications and signal-processing technologies. High-Q resonators are essential for stable, low-noise communications, and radar applications. Mechanical oscillators can exhibit orders of magnitude higher Qs than electronic resonant circuits, which are limited by resistive losses. This has motivated the development of a variety of mechanical resonators, including bulk acoustic wave (BAW) resonators, surface acoustic wave (SAW) resonators, and Si and SiC micromachined resonators (known as microelectromechanical systems or MEMS). There is also a strong push to extend the resonant frequencies of these oscillators into the GHz regime of state-of-the-art electronics. Unfortunately, the BAW and SAW devices tend to be large and are not easily integrated into electronic circuits. MEMS structures have been integrated into circuits, but efforts to extend MEMS resonant frequencies into the GHz regime have been difficult because of scaling problems with the capacitively-coupled drive and readout. In contrast, the proposed devices would be much smaller and hence could be more readily incorporated into advanced RF (more specifically, microwave) integrated circuits.

Heat pipe with embedded wick structure

DOEpatents

Adkins, Douglas Ray; Shen, David S.; Tuck, Melanie R.; Palmer, David W.; Grafe, V. Gerald

1998-01-01

A heat pipe has an embedded wick structure that maximizes capillary pumping capability. Heat from attached devices such as integrated circuits evaporates working fluid in the heat pipe. The vapor cools and condenses on a heat dissipation surface. The condensate collects in the wick structure, where capillary pumping returns the fluid to high heat areas.

Heat pipe with embedded wick structure

DOEpatents

Adkins, D.R.; Shen, D.S.; Tuck, M.R.; Palmer, D.W.; Grafe, V.G.

1998-06-23

A heat pipe has an embedded wick structure that maximizes capillary pumping capability. Heat from attached devices such as integrated circuits evaporates working fluid in the heat pipe. The vapor cools and condenses on a heat dissipation surface. The condensate collects in the wick structure, where capillary pumping returns the fluid to high heat areas. 7 figs.

Heat pipe with embedded wick structure

DOEpatents

Adkins, Douglas Ray; Shen, David S.; Tuck, Melanie R.; Palmer, David W.; Grafe, V. Gerald

1999-01-01

A heat pipe has an embedded wick structure that maximizes capillary pumping capability. Heat from attached devices such as integrated circuits evaporates working fluid in the heat pipe. The vapor cools and condenses on a heat dissipation surface. The condensate collects in the wick structure, where capillary pumping returns the fluid to high heat areas.

Halbach array-based design and simulation of disc coreless permanen-magnet integrated starter generator

NASA Astrophysics Data System (ADS)

Li, Y. B.; Yang, Z. X.; Chen, W.; He, Q. Y.

2017-11-01

The functional performance, such as magnetic flux leakage, power density and efficiency, is related to the structural characteristics and design technique for the disc permanent magnet synchronous generators (PMSGs). Halbach array theory-based magnetic circuit structure is developed, and Maxwell3D simulation analysis approach of PMSG is proposed in this paper for integrated starter generator (ISG). The magnetization direction of adjacent permanent magnet is organized in difference of 45 degrees for focusing air gap side, and improving the performance of the generator. The magnetic field distribution and functional performance in load and/or unload conditions are simulated by Maxwell3D module. The proposed approach is verified by simulation analysis, the air gap flux density is 0.66T, and the phase voltage curve has the characteristics of a preferable sinusoidal wave and the voltage amplitude 335V can meet the design requirements while the disc coreless PMSG is operating at rated speed. And the developed magnetic circuit structure can be used for engineering design of the disc coreless PMSG to the integrated starter generator.

Interlocked DNA nanostructures controlled by a reversible logic circuit.

PubMed

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-09-17

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems.

Interlocked DNA nanostructures controlled by a reversible logic circuit

PubMed Central

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-01-01

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

NASA Astrophysics Data System (ADS)

Kawamoto, Kazunori; Mizuno, Shoji; Abe, Hirofumi; Higuchi, Yasushi; Ishihara, Hideaki; Fukumoto, Harutsugu; Watanabe, Takamoto; Fujino, Seiji; Shirakawa, Isao

2001-04-01

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

A tale of two species: neural integration in zebrafish and monkeys

PubMed Central

Joshua, Mati; Lisberger, Stephen G.

2014-01-01

Selection of a model organism creates a tension between competing constraints. The recent explosion of modern molecular techniques has revolutionized the analysis of neural systems in organisms that are amenable to genetic techniques. Yet, the non-human primate remains the gold-standard for the analysis of the neural basis of behavior, and as a bridge to the operation of the human brain. The challenge is to generalize across species in a way that exposes the operation of circuits as well as the relationship of circuits to behavior. Eye movements provide an opportunity to cross the bridge from mechanism to behavior through research on diverse species. Here, we review experiments and computational studies on a circuit function called “neural integration” that occurs in the brainstems of larval zebrafish, non-human primates, and species “in between”. We show that analysis of circuit structure using modern molecular and imaging approaches in zebrafish has remarkable explanatory power for the details of the responses of integrator neurons in the monkey. The combination of research from the two species has led to a much stronger hypothesis for the implementation of the neural integrator than could have been achieved using either species alone. PMID:24797331

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

DTIC Science & Technology

2015-10-13

transistors. There are several reasons for this gigantic disparity: insufficient funding and lack of profit-driven investments in superconductor ...Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers,” IEEE Trans. Appl. Supercond., vol...vol. 25, No. 3, 1301704, June 2015. [7] V. Ambegaokar and A. Baratoff, “Tunneling between superconductors ,” Phys. Rev. Lett., vol. 10, no. 11, pp

Integrated Circuit For Simulation Of Neural Network

NASA Technical Reports Server (NTRS)

Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

1988-01-01

Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

NASA Technical Reports Server (NTRS)

1975-01-01

Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

High-performance integrated pick-up circuit for SPAD arrays in time-correlated single photon counting

NASA Astrophysics Data System (ADS)

Acconcia, Giulia; Cominelli, Alessandro; Peronio, Pietro; Rech, Ivan; Ghioni, Massimo

2017-05-01

The analysis of optical signals by means of Single Photon Avalanche Diodes (SPADs) has been subject to a widespread interest in recent years. The development of multichannel high-performance Time Correlated Single Photon Counting (TCSPC) acquisition systems has undergone a fast trend. Concerning the detector performance, best in class results have been obtained resorting to custom technologies leading also to a strong dependence of the detector timing jitter from the threshold used to determine the onset of the photogenerated current flow. In this scenario, the avalanche current pick-up circuit plays a key role in determining the timing performance of the TCSPC acquisition system, especially with a large array of SPAD detectors because of electrical crosstalk issues. We developed a new current pick-up circuit based on a transimpedance amplifier structure able to extract the timing information from a 50-μm-diameter custom technology SPAD with a state-of-art timing jitter as low as 32ps and suitable to be exploited with SPAD arrays. In this paper we discuss the key features of this structure and we present a new version of the pick-up circuit that also provides quenching capabilities in order to minimize the number of interconnections required, an aspect that becomes more and more crucial in densely integrated systems.

Microwave processed NiMg ferrite: Studies on structural and magnetic properties

NASA Astrophysics Data System (ADS)

Chandra Babu Naidu, K.; Madhuri, W.

2016-12-01

Ferrites are magnetic semiconductors realizing an important role in electrical and electronic circuits where electrical and magnetic property coupling is required. Though ferrite materials are known for a long time, there is a large scope in the improvement of their properties (vice sintering and frequency dependence of electrical and magnetic properties) with the current technological trends. Forth coming technology is aimed at miniaturization and smart gadgets, electrical components like inductors and transformers cannot be included in integrated circuits. These components are incorporated into the circuit as surface mount devices whose fabrication involves low temperature co-firing of ceramics and microwave monolithic integrated circuits technologies. These technologies demand low temperature sinter-ability of ferrites. This article presents low temperature microwave sintered Ni-Mg ferrites of general chemical formula Ni1-xMgxFe2O4 (x=0, 0.2, 0.4, 0.5, 0.6, 0.8, 1) for potential applications as transformer core materials. The series of ferrites are characterized using X-ray diffractometer, scanning electron microscopy, Fourier transform infrared and vibrating sample magnetometer for investigating structural, morphological and magnetic properties respectively. The initial permeability is studied with magnesium content, temperature and frequency in the temperature range of 308 K-873 K and 42 Hz-5 MHz.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Digital design using selection operations

NASA Technical Reports Server (NTRS)

Miles, Lowell H. (Inventor); Whitaker, Sterling R. (Inventor); Cameron, Eric G. (Inventor)

2004-01-01

A digital integrated circuit chip is designed by identifying a logical structure to be implemented. This logical structure is represented in terms of a logical operations, at least 5% of which include selection operations. A determination is made of logic cells that correspond to an implementation of these logical operations.

Programmable resistive-switch nanowire transistor logic circuits.

PubMed

Shim, Wooyoung; Yao, Jun; Lieber, Charles M

2014-09-10

Programmable logic arrays (PLA) constitute a promising architecture for developing increasingly complex and functional circuits through nanocomputers from nanoscale building blocks. Here we report a novel one-dimensional PLA element that incorporates resistive switch gate structures on a semiconductor nanowire and show that multiple elements can be integrated to realize functional PLAs. In our PLA element, the gate coupling to the nanowire transistor can be modulated by the memory state of the resistive switch to yield programmable active (transistor) or inactive (resistor) states within a well-defined logic window. Multiple PLA nanowire elements were integrated and programmed to yield a working 2-to-4 demultiplexer with long-term retention. The well-defined, controllable logic window and long-term retention of our new one-dimensional PLA element provide a promising route for building increasingly complex circuits with nanoscale building blocks.

Energy structure of MHD flow coupling with outer resistance circuit

NASA Astrophysics Data System (ADS)

Huang, Z. Y.; Liu, Y. J.; Chen, Y. Q.; Peng, Z. L.

2015-08-01

Energy structure of MHD flow coupling with outer resistance circuit is studied to illuminate qualitatively and quantitatively the energy relation of this basic MHD flow system with energy input and output. Energy structure are analytically derived based on the Navier-Stocks equations for two-dimensional fully-developed flow and generalized Ohm's Law. The influences of applied magnetic field, Hall parameter and conductivity on energy structure are discussed based on the analytical results. Associated energies in MHD flow are deduced and validated by energy conservation. These results reveal that energy structure consists of two sub structures: electrical energy structure and internal energy structure. Energy structure and its sub structures provide an integrated theoretical energy path of the MHD system. Applied magnetic field and conductivity decrease the input energy, dissipation by fluid viscosity and internal energy but increase the ratio of electrical energy to input energy, while Hall parameter has the opposite effects. These are caused by their different effects on Bulk velocity, velocity profiles, voltage and current in outer circuit. Understanding energy structure helps MHD application designers to actively adjust the allocation of different parts of energy so that it is more reasonable and desirable.

Automatic visual inspection system for microelectronics

NASA Technical Reports Server (NTRS)

Micka, E. Z. (Inventor)

1975-01-01

A system for automatically inspecting an integrated circuit was developed. A device for shining a scanning narrow light beam at an integrated circuit to be inspected and another light beam at an accepted integrated circuit was included. A pair of photodetectors that receive light reflected from these integrated circuits, and a comparing system compares the outputs of the photodetectors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

STICAP: A linear circuit analysis program with stiff systems capability. Volume 1: Theory manual. [network analysis

NASA Technical Reports Server (NTRS)

Cooke, C. H.

1975-01-01

STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.

Packaging system with cleaning channel and method of making the same

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fang, Lu

A packaging structure and method for surface mount integrated circuits reduces electrochemical migration (ECM) problems by including one or more cleaning channels to effectively and efficiently remove flux residue that may otherwise remain lodged in gaps between the surface mount package and the printed circuit board. A cleaning channel may be formed along a bottom surface of the surface mount package (i.e., the surface facing the printed circuit board), or along a portion of a top surface of the printed circuit board. In either case, the inclusion of a cleaning channel enlarges the gap between the bottom surface of themore » surface mount package and the printed circuit board and creates a path for contaminants to be flushed out during a cleaning process.« less

Laser Integration on Silicon Photonic Circuits Through Transfer Printing

DTIC Science & Technology

2017-03-10

AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...TYPE Final 3. DATES COVERED (From - To) 15 Sep 2015 to 14 Sep 2016 4. TITLE AND SUBTITLE Laser integration on silicon photonic circuits through...parallel integration of III-V lasers on silicon photonic integrated circuits. The report discusses the technological process that has been developed as

Multilayered photonic integration on SOI platform using waveguide-based bridge structure

NASA Astrophysics Data System (ADS)

Majumder, Saikat; Chakraborty, Rajib

2018-06-01

A waveguide based structure on silicon on insulator platform is proposed for vertical integration in photonic integrated circuits. The structure consists of two multimode interference couplers connected by a single mode (SM) section which can act as a bridge over any other underlying device. Two more SM sections acts as input and output of the first and second multimode couplers respectively. Potential application of this structure is in multilayered photonic links. It is shown that the efficiency of the structure can be improved by making some design modifications. The entire simulation is done using effective-index based matrix method. The feature size chosen are comparable to waveguides fabricated previously so as to fabricate the proposed structure easily.

A Novel Integrated Structure with a Radial Displacement Sensor and a Permanent Magnet Biased Radial Magnetic Bearing

PubMed Central

Sun, Jinji; Zhang, Yin

2014-01-01

In this paper, a novel integrated structure is proposed in order to reduce the axial length of the high speed of a magnetically suspended motor (HSMSM) to ensure the maximum speed, which combines radial displacement sensor probes and the permanent magnet biased radial magnetic bearing in HSMSM. The sensor probes are integrated in the magnetic bearing, and the sensor preamplifiers are placed in the control system of the HSMSM, separate from the sensor probes. The proposed integrated structure can save space in HSMSMs, improve the working frequency, reduce the influence of temperature on the sensor circuit, and improve the stability of HSMSMs. PMID:24469351

Rad-Hard Structured ASIC Body of Knowledge

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

A periodic piezoelectric smart structure with the integrated passive/active vibration-reduction performances

NASA Astrophysics Data System (ADS)

Wang, Yuxi; Niu, Shengkai; Hu, Yuantai

2017-06-01

The paper proposes a new piezoelectric smart structure with the integrated passive/active vibration-reduction performances, which is made of a series of periodic structural units. Every structural unit is made of two layers, one is an array of piezoelectric bimorphs (PBs) and one is an array of metal beams (MBs), both are connected as a whole by a metal plate. Analyses show that such a periodic smart structure possesses two aspects of vibration-reduction performance: one comes from its phonon crystal characteristics which can isolate those vibrations with the driving frequency inside the band gap(s). The other one comes from the electromechanical conversion of bent PBs, which is actively aimed at those vibrations with the driving frequency outside the band gap(s). By adjusting external inductance, the equivalent circuit of the proposed structure can be forced into parallel resonance such that most of the vibration energy is converted into electrical energy for dissipation by a resistance. Thus, an external circuit under the parallel resonance state is equivalent to a strong damping to the interrelated vibrating structure, which is just the action mechanism of the active vibration reduction performance of the proposed smart structure.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Artificial Muscle (AM) Cilia Array for Underwater Systems

DTIC Science & Technology

2016-12-15

structures, including cilia-like structures. Specifically, a custom 3D printer was created that utilizes custom-made Nafion filament for 30 printing of custom... printing ) of IPMC material to create custom-shaped AM structures, including cilia-like structures. Various custom-shaped AM structures were fabricated via...integrating square cross-section IPMC actuators with a printed circuit board power delivery system. IV. Concise Accomplishments Performance

Graphene radio frequency receiver integrated circuit.

PubMed

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Graphene radio frequency receiver integrated circuit

NASA Astrophysics Data System (ADS)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A.; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm2 area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

PubMed

Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

2015-02-01

An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

Monolithically integrated bacteriorhodopsin/semiconductor opto-electronic integrated circuit for a bio-photoreceiver.

PubMed

Xu, J; Bhattacharya, P; Váró, G

2004-03-15

The light-sensitive protein, bacteriorhodopsin (BR), is monolithically integrated with an InP-based amplifier circuit to realize a novel opto-electronic integrated circuit (OEIC) which performs as a high-speed photoreceiver. The circuit is realized by epitaxial growth of the field-effect transistors, currently used semiconductor device and circuit fabrication techniques, and selective area BR electro-deposition. The integrated photoreceiver has a responsivity of 175 V/W and linear photoresponse, with a dynamic range of 16 dB, with 594 nm photoexcitation. The dynamics of the photochemical cycle of BR has also been modeled and a proposed equivalent circuit simulates the measured BR photoresponse with good agreement.

Mode-locked laser with pulse interleavers in a monolithic photonic integrated circuit for millimeter wave and terahertz carrier generation.

PubMed

Lo, Mu-Chieh; Guzmán, Robinson; Gordón, Carlos; Carpintero, Guillermo

2017-04-15

This Letter presents a photonics-based millimeter wave and terahertz frequency synthesizer using a monolithic InP photonic integrated circuit composed of a mode-locked laser (MLL) and two pulse interleaver stages to multiply the repetition rate frequency. The MLL is a multiple colliding pulse MLL producing an 80 GHz repetition rate pulse train. Through two consecutive monolithic pulse interleaver structures, each doubling the repetition rate, we demonstrate the achievement of 160 and 320 GHz. The fabrication was done on a multi-project wafer run of a generic InP photonic technology platform.

Graphene-based plasmonic photodetector for photonic integrated circuits.

PubMed

Kim, Jin Tae; Yu, Young-Jun; Choi, Hongkyw; Choi, Choon-Gi

2014-01-13

We developed a planar-type graphene-based plasmonic photodetector (PD) for the development of all-graphene photonic-integrated-circuits (PICs). By configuring the graphene plasmonic waveguide and PD structure all-in-one, the proposed graphene PD detects horizontally incident light. The photocurrent profile with opposite polarity is the maximum at graphene-electrode interfaces due to a Schottky-like barrier effect at the interface. The photocurrent amplitude increases with an increase of the graphene-metal interface length. Obtaining time constants of less than 39.7 ms for the time response, we concluded that the proposed graphene PD could be exploited further for application in all graphene-based PICs.

Open Circuit Resonant Sensors for Composite Damage Detection and Diagnosis

NASA Technical Reports Server (NTRS)

Mielnik, John J., Jr.

2011-01-01

Under the Integrated Vehicle Health Management (IVHM) program work was begun to investigate the feasibility of sensor systems for detecting and diagnosing damage to aircraft composite structures and materials. Specific interest for this study was in damage initiated by environmental storm hazards and the direct effect of lightning strikes on the material structures of a composite aircraft in flight. A series of open circuit resonant sensors was designed, fabricated, characterized, and determined to be a potentially viable means for damage detection and diagnosis of composite materials. The results of this research and development effort are documented in this report.

Fast Faraday Cup With High Bandwidth

DOEpatents

Deibele, Craig E [Knoxville, TN

2006-03-14

A circuit card stripline Fast Faraday cup quantitatively measures the picosecond time structure of a charged particle beam. The stripline configuration maintains signal integrity, and stitching of the stripline increases the bandwidth. A calibration procedure ensures the measurement of the absolute charge and time structure of the charged particle beam.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Grzegorz W.; Gabriella, Carini; Enquist, Paul

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch,more » yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e - rms and a conversion gain of 69.5 μV/e - with 2.6 e - rms and 2.7 μV/e - rms pixel-to-pixel variations, respectively, were measured.« less

Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Hyun S.; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

2007-05-01

We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing and then storing, transporting, processing, switching, routing and distributing optical signals that have been collected by means of sensors. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate sensors and other micro/ nano-scale photonic devices. Here, in our study, we focus on the sensors based on the micro-ring structures. We designed bio-sensors using silicon based micro-ring resonator. We investigate the characteristics such as sensitivity and selectivity (or quality factor) of micro-ring resonator for their use in bio-sensing application. We performed simulation studies on the quality factor of micro-ring resonators by varying the radius of the ring resonators and the separation between adjacent waveguides. We introduce the effective coupling coefficient as a realistic value to describe the strength of the coupling in micro-ring resonators.

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

Design of integrated laser initiator

NASA Astrophysics Data System (ADS)

Cao, Chunqiang; He, Aifeng; Jing, Bo; Ma, Yue

2018-03-01

This paper analyzes the design principle of integrated laser detonator, introduces the design method of integrated laser Detonators. Based on the integrated laser detonator, structure, laser energy -exchange device, circuit design and the energetic material properties and the charge parameters, developed a high level of integration Antistatic ability Small size of the integrated laser prototype Detonator. The laser detonator prototype antistatic ability of 25 kV. The research of this paper can solve the key design of laser detonator miniaturization and integration of weapons and equipment, satisfy the electromagnetic safety and micro weapons development of explosive demand.

Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-12-09

Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.

Capacitive micromachined ultrasonic transducers for medical imaging and therapy.

PubMed

Khuri-Yakub, Butrus T; Oralkan, Omer

2011-05-01

Capacitive micromachined ultrasonic transducers (CMUTs) have been subject to extensive research for the last two decades. Although they were initially developed for air-coupled applications, today their main application space is medical imaging and therapy. This paper first presents a brief description of CMUTs, their basic structure, and operating principles. Our progression of developing several generations of fabrication processes is discussed with an emphasis on the advantages and disadvantages of each process. Monolithic and hybrid approaches for integrating CMUTs with supporting integrated circuits are surveyed. Several prototype transducer arrays with integrated frontend electronic circuits we developed and their use for 2-D and 3-D, anatomical and functional imaging, and ablative therapies are described. The presented results prove the CMUT as a MEMS technology for many medical diagnostic and therapeutic applications.

Capacitive micromachined ultrasonic transducers for medical imaging and therapy

PubMed Central

Khuri-Yakub, Butrus T.; Oralkan, Ömer

2011-01-01

Capacitive micromachined ultrasonic transducers (CMUTs) have been subject to extensive research for the last two decades. Although they were initially developed for air-coupled applications, today their main application space is medical imaging and therapy. This paper first presents a brief description of CMUTs, their basic structure, and operating principles. Our progression of developing several generations of fabrication processes is discussed with an emphasis on the advantages and disadvantages of each process. Monolithic and hybrid approaches for integrating CMUTs with supporting integrated circuits are surveyed. Several prototype transducer arrays with integrated frontend electronic circuits we developed and their use for 2-D and 3-D, anatomical and functional imaging, and ablative therapies are described. The presented results prove the CMUT as a MEMS technology for many medical diagnostic and therapeutic applications. PMID:21860542

Electro-optical Probing Of Terahertz Integrated Circuits

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

1990-01-01

Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

NASA Astrophysics Data System (ADS)

Bahl, Inder J.

Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

Antenna-coupled Superconducting Bolometers for Observations of the Cosmic Microwave Background Polarization

NASA Astrophysics Data System (ADS)

Myers, Michael James

We describe the development of a novel millimeter-wave cryogenic detector. The device integrates a planar antenna, superconducting transmission line, bandpass filter, and bolometer onto a single silicon wafer. The bolometer uses a superconducting Transition-Edge Sensor (TES) thermistor, which provides substantial advantages over conventional semiconductor bolometers. The detector chip is fabricated using standard micro-fabrication techniques. This highly-integrated detector architecture is particularly well-suited for use in the de- velopment of polarization-sensitive cryogenic receivers with thousands of pixels. Such receivers are needed to meet the sensitivity requirements of next-generation cosmic microwave background polarization experiments. The design, fabrication, and testing of prototype array pixels are described. Preliminary considerations for a full array design are also discussed. A set of on-chip millimeter-wave test structures were developed to help understand the performance of our millimeter-wave microstrip circuits. These test structures produce a calibrated transmission measurement for an arbitrary two-port circuit using optical techniques, rather than a network analyzer. Some results of fabricated test structures are presented.

Wide-band polarization controller for Si photonic integrated circuits.

PubMed

Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

2016-12-15

A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

Large Scale Integrated Circuits for Military Applications.

DTIC Science & Technology

1977-05-01

economic incentive for riarrowing this gap is examined, y (U)^wo"categories of cost are analyzed: the direct life cycle cost of the integrated circuit...dependence of these costs on the physical charac- teristics of the integrated circuits is discussed. (U) The economic and physical characteristics of... economic incentive for narrowing this gap is examined. Two categories of cost are analyzed: the direct life cycle cost of the integrated circuit

Novel electrochemical nickel metallization in silicon impedance engineering for mixed-signal system-on-chip crosstalk isolation

NASA Astrophysics Data System (ADS)

Zhang, Xi

One of the major challenges for single chip radio frequency integrated circuits (RFIC's) built on Si is the RE crosstalk through the Si substrate. Noise from switching transient in digital circuits can be transmitted through Si substrate and degrades the performance of analog circuit elements. A highly conductive moat or Faraday cage type structure of through-the-wafer thickness in the Si substrate was demonstrated to be effective in shielding electromagnetic interference thereby reducing RE cross-talk in high performance mixed signal integrated circuits. Such a structure incorporated into the p- Si substrate was realized by electroless Ni metallization over selected regions with ultra-high-aspect-ratio macropores that was etched electrochemically in p- Si substrates. The metallization process was conducted by immersing the macroporous Si sample in an alkaline aqueous solution containing Ni2+ without a reducing agent. It was found that working at slightly elevated temperature, Ni 2+ was rapidly reduced and deposited in the macropores. During the wet chemical process, conformal metallization on the pore wall was achieved. The entire porous Si skeleton was gradually replaced by Ni along the extended duration of immersion. In a p-/p+ epi Si substrate used for high performance digital CMOS, the suppression of crosstalk by the arrayed metallic Ni via structure fabricated from the front p side was significant that the crosstalk went down to the noise floor of the conventional measurement instruments. The process and mechanism of forming such a Ni structure over the original Si were studied. Theoretical computation relevant to the process was carried out to show a good consistency with the experiments.

Low-loss terahertz ribbon waveguides.

PubMed

Yeh, Cavour; Shimabukuro, Fred; Siegel, Peter H

2005-10-01

The submillimeter wave or terahertz (THz) band (1 mm-100 microm) is one of the last unexplored frontiers in the electromagnetic spectrum. A major stumbling block hampering instrument deployment in this frequency regime is the lack of a low-loss guiding structure equivalent to the optical fiber that is so prevalent at the visible wavelengths. The presence of strong inherent vibrational absorption bands in solids and the high skin-depth losses of conductors make the traditional microstripline circuits, conventional dielectric lines, or metallic waveguides, which are common at microwave frequencies, much too lossy to be used in the THz bands. Even the modern surface plasmon polariton waveguides are much too lossy for long-distance transmission in the THz bands. We describe a concept for overcoming this drawback and describe a new family of ultra-low-loss ribbon-based guide structures and matching components for propagating single-mode THz signals. For straight runs this ribbon-based waveguide can provide an attenuation constant that is more than 100 times less than that of a conventional dielectric or metallic waveguide. Problems dealing with efficient coupling of power into and out of the ribbon guide, achieving low-loss bends and branches, and forming THz circuit elements are discussed in detail. One notes that active circuit elements can be integrated directly onto the ribbon structure (when it is made with semiconductor material) and that the absence of metallic structures in the ribbon guide provides the possibility of high-power carrying capability. It thus appears that this ribbon-based dielectric waveguide and associated components can be used as fundamental building blocks for a new generation of ultra-high-speed electronic integrated circuits or THz interconnects.

Integrated circuits, and design and manufacture thereof

DOEpatents

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistor

NASA Technical Reports Server (NTRS)

Halsor, J. L.; Lin, H. C.

1974-01-01

Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.

Heterojunction-Internal-Photoemission Infrared Detectors

NASA Technical Reports Server (NTRS)

Maserjian, Joseph

1991-01-01

New type of photodetector adds options for design of imaging devices. Heterojunction-internal-photoemission (HIP) infrared photodetectors proposed for incorporation into planar arrays in imaging devices required to function well at wavelengths from 8 to 17 micrometers and at temperatures above 65 K. Photoexcited electrons cross energy barrier at heterojunction and swept toward collection layer. Array of such detectors made by etching mesa structures. HIP layers stacked to increase quantum efficiency. Also built into integrated circuits including silicon multiplexer/readout circuits.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

PubMed

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Label-Free Direct Electronic Detection of Biomolecules with Amorphous Silicon Nanostructures

PubMed Central

Lund, John; Mehta, Ranjana; Parviz, Babak A.

2007-01-01

We present the fabrication and characterization of a nano-scale sensor made of amorphous silicon for the label-free, electronic detection of three classes of biologically important molecules: ions, oligonucleotides, and proteins. The sensor structure has an active element which is a 50 nm wide amorphous silicon semicircle and has a total footprint of less than 4 μm2. We demonstrate the functionalization of the sensor with receptor molecules and the electronic detection of three targets: H+ ions, short single-stranded DNAs, and streptavidin. The sensor is able to reliably distinguish single base-pair mismatches in 12 base long strands of DNA and monitor the introduction and identification of straptavidin in real-time. The versatile sensor structure can be readily functionalized with a wide range of receptor molecules and is suitable for integration with high-speed electronic circuits as a post-process on an integrated circuit chip. PMID:17292148

Thermal stress cycling of GaAs solar cells

NASA Technical Reports Server (NTRS)

Janousek, B. K.; Francis, R. W.; Wendt, J. P.

1985-01-01

A thermal cycling experiment was performed on GaAs solar cells to establish the electrical and structural integrity of these cells under the temperature conditions of a simulated low-Earth orbit of 3-year duration. Thirty single junction GaAs cells were obtained and tests were performed to establish the beginning-of-life characteristics of these cells. The tests consisted of cell I-V power output curves, from which were obtained short-circuit current, open circuit voltage, fill factor, and cell efficiency, and optical micrographs, spectral response, and ion microprobe mass analysis (IMMA) depth profiles on both the front surfaces and the front metallic contacts of the cells. Following 5,000 thermal cycles, the performance of the cells was reexamined in addition to any factors which might contribute to performance degradation. It is established that, after 5,000 thermal cycles, the cells retain their power output with no loss of structural integrity or change in physical appearance.

Surface-micromachined and high-aspect ratio electrostatic actuators for aeronautic and space applications: design and lifetime considerations

NASA Astrophysics Data System (ADS)

Vescovo, P.; Joseph, E.; Bourbon, G.; Le Moal, P.; Minotti, P.; Hibert, C.; Pont, G.

2003-09-01

This paper focuses on recent advances in the field of MEMS-based actuators and distributed microelectromechanical systems (MEMS). IC-processed actuators (e.g. actuators that are machined using integrated circuit batch processes) are expected to open a wide range of industrial applications on the near term. The most promising investigations deal with high-aspect ratio electric field driven microactuators suitable for use in numerous technical fields such as aeronautics and space industry. Because the silicon micromachining technology have the potential to integrate both mechanical components and control circuits within a single process, MEMS-based active control of microscopic and macroscopic structures appears to be one of the most promising challenges for the next decade. As a first step towards new generations of MEMS-based smart structures, recent investigations dealing with silicon mechanisms involving MEMS-based actuators are briefly discussed in this paper.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology.

PubMed

Zhao, Hong-Quan; Kasai, Seiya; Shiratori, Yuta; Hashizume, Tamotsu

2009-06-17

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.

Experimental demonstration of two-dimensional hybrid waveguide-integrated plasmonic crystals on silicon-on-insulator platform

NASA Astrophysics Data System (ADS)

Ren, Guanghui; Yudistira, Didit; Nguyen, Thach G.; Khodasevych, Iryna; Schoenhardt, Steffen; Berean, Kyle J.; Hamm, Joachim M.; Hess, Ortwin; Mitchell, Arnan

2017-07-01

Nanoscale plasmonic structures can offer unique functionality due to extreme sub-wavelength optical confinement, but the realization of complex plasmonic circuits is hampered by high propagation losses. Hybrid approaches can potentially overcome this limitation, but only few practical approaches based on either single or few element arrays of nanoantennas on dielectric nanowire have been experimentally demonstrated. In this paper, we demonstrate a two dimensional hybrid photonic plasmonic crystal interfaced with a standard silicon photonic platform. Off resonance, we observe low loss propagation through our structure, while on resonance we observe strong propagation suppression and intense concentration of light into a dense lattice of nanoscale hot-spots on the surface providing clear evidence of a hybrid photonic plasmonic crystal bandgap. This fully integrated approach is compatible with established silicon-on-insulator (SOI) fabrication techniques and constitutes a significant step toward harnessing plasmonic functionality within SOI photonic circuits.

Y-junctions based on circular depressed-cladding waveguides fabricated with femtosecond pulses in Nd:YAG crystal: A route to integrate complex photonic circuits in crystals

NASA Astrophysics Data System (ADS)

Ajates, Javier G.; Romero, Carolina; Castillo, Gabriel R.; Chen, Feng; Vázquez de Aldana, Javier R.

2017-10-01

We have designed and fabricated photonic structures such as, Y-junctions (one of the basic building blocks for construction any integrated photonic devices) and Mach-Zehnder interferometers, based on circular depressed-cladding waveguides by direct femtosecond laser irradiation in Nd:YAG crystal. The waveguides were optically characterized at 633 nm, showing nearly mono-modal behaviour for the selected waveguide radius (9 μm). The effect of the splitting angle in the Y structures was investigated finding a good preservation of the modal profiles up to more than 2°, with 1 dB of additional losses in comparison with straight waveguides. The dependence with polarization of these splitters keeps in a reasonable low level. Our designs pave the way for the fabrication of arbitrarily complex 3D photonic circuits in crystals with cladding waveguides.

Reusable vibration resistant integrated circuit mounting socket

DOEpatents

Evans, Craig N.

1995-01-01

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

PubMed

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Macromodels of digital integrated circuits for program packages of circuit engineering design

NASA Astrophysics Data System (ADS)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Integrated coherent matter wave circuits

DOE PAGES

Ryu, C.; Boshier, M. G.

2015-09-21

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Cerebro-cerebellar circuits in autism spectrum disorder.

PubMed

D'Mello, Anila M; Stoodley, Catherine J

2015-01-01

The cerebellum is one of the most consistent sites of abnormality in autism spectrum disorder (ASD) and cerebellar damage is associated with an increased risk of ASD symptoms, suggesting that cerebellar dysfunction may play a crucial role in the etiology of ASD. The cerebellum forms multiple closed-loop circuits with cerebral cortical regions that underpin movement, language, and social processing. Through these circuits, cerebellar dysfunction could impact the core ASD symptoms of social and communication deficits and repetitive and stereotyped behaviors. The emerging topography of sensorimotor, cognitive, and affective subregions in the cerebellum provides a new framework for interpreting the significance of regional cerebellar findings in ASD and their relationship to broader cerebro-cerebellar circuits. Further, recent research supports the idea that the integrity of cerebro-cerebellar loops might be important for early cortical development; disruptions in specific cerebro-cerebellar loops in ASD might impede the specialization of cortical regions involved in motor control, language, and social interaction, leading to impairments in these domains. Consistent with this concept, structural, and functional differences in sensorimotor regions of the cerebellum and sensorimotor cerebro-cerebellar circuits are associated with deficits in motor control and increased repetitive and stereotyped behaviors in ASD. Further, communication and social impairments are associated with atypical activation and structure in cerebro-cerebellar loops underpinning language and social cognition. Finally, there is converging evidence from structural, functional, and connectivity neuroimaging studies that cerebellar right Crus I/II abnormalities are related to more severe ASD impairments in all domains. We propose that cerebellar abnormalities may disrupt optimization of both structure and function in specific cerebro-cerebellar circuits in ASD.

Cerebro-cerebellar circuits in autism spectrum disorder

PubMed Central

D'Mello, Anila M.; Stoodley, Catherine J.

2015-01-01

The cerebellum is one of the most consistent sites of abnormality in autism spectrum disorder (ASD) and cerebellar damage is associated with an increased risk of ASD symptoms, suggesting that cerebellar dysfunction may play a crucial role in the etiology of ASD. The cerebellum forms multiple closed-loop circuits with cerebral cortical regions that underpin movement, language, and social processing. Through these circuits, cerebellar dysfunction could impact the core ASD symptoms of social and communication deficits and repetitive and stereotyped behaviors. The emerging topography of sensorimotor, cognitive, and affective subregions in the cerebellum provides a new framework for interpreting the significance of regional cerebellar findings in ASD and their relationship to broader cerebro-cerebellar circuits. Further, recent research supports the idea that the integrity of cerebro-cerebellar loops might be important for early cortical development; disruptions in specific cerebro-cerebellar loops in ASD might impede the specialization of cortical regions involved in motor control, language, and social interaction, leading to impairments in these domains. Consistent with this concept, structural, and functional differences in sensorimotor regions of the cerebellum and sensorimotor cerebro-cerebellar circuits are associated with deficits in motor control and increased repetitive and stereotyped behaviors in ASD. Further, communication and social impairments are associated with atypical activation and structure in cerebro-cerebellar loops underpinning language and social cognition. Finally, there is converging evidence from structural, functional, and connectivity neuroimaging studies that cerebellar right Crus I/II abnormalities are related to more severe ASD impairments in all domains. We propose that cerebellar abnormalities may disrupt optimization of both structure and function in specific cerebro-cerebellar circuits in ASD. PMID:26594140

Neuronal Circuitry Mechanisms Regulating Adult Mammalian Neurogenesis

PubMed Central

Song, Juan; Olsen, Reid H.J.; Sun, Jiaqi; Ming, Guo-li; Song, Hongjun

2017-01-01

The adult mammalian brain is a dynamic structure, capable of remodeling in response to various physiological and pathological stimuli. One dramatic example of brain plasticity is the birth and subsequent integration of newborn neurons into the existing circuitry. This process, termed adult neurogenesis, recapitulates neural developmental events in two specialized adult brain regions: the lateral ventricles of the forebrain. Recent studies have begun to delineate how the existing neuronal circuits influence the dynamic process of adult neurogenesis, from activation of quiescent neural stem cells (NSCs) to the integration and survival of newborn neurons. Here, we review recent progress toward understanding the circuit-based regulation of adult neurogenesis in the hippocampus and olfactory bulb. PMID:27143698

Integrated optical circuits for numerical computation

NASA Technical Reports Server (NTRS)

Verber, C. M.; Kenan, R. P.

1983-01-01

The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

Stochastic simulation and robust design optimization of integrated photonic filters

NASA Astrophysics Data System (ADS)

Weng, Tsui-Wei; Melati, Daniele; Melloni, Andrea; Daniel, Luca

2017-01-01

Manufacturing variations are becoming an unavoidable issue in modern fabrication processes; therefore, it is crucial to be able to include stochastic uncertainties in the design phase. In this paper, integrated photonic coupled ring resonator filters are considered as an example of significant interest. The sparsity structure in photonic circuits is exploited to construct a sparse combined generalized polynomial chaos model, which is then used to analyze related statistics and perform robust design optimization. Simulation results show that the optimized circuits are more robust to fabrication process variations and achieve a reduction of 11%-35% in the mean square errors of the 3 dB bandwidth compared to unoptimized nominal designs.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

PubMed

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

PubMed

Kwon, Jimin; Takeda, Yasunori; Fukuda, Kenjiro; Cho, Kilwon; Tokito, Shizuo; Jung, Sungjune

2016-11-22

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Nanowires and nanoribbons as subwavelength optical waveguides and their use as components in photonic circuits and devices

DOEpatents

Yang, Peidong; Law, Matt; Sirbuly, Donald J.; Johnson, Justin C.; Saykally, Richard; Fan, Rong; Tao, Andrea

2012-10-02

Nanoribbons and nanowires having diameters less than the wavelength of light are used in the formation and operation of optical circuits and devices. Such nanostructures function as subwavelength optical waveguides which form a fundamental building block for optical integration. The extraordinary length, flexibility and strength of these structures enable their manipulation on surfaces, including the precise positioning and optical linking of nanoribbon/wire waveguides and other nanoribbon/wire elements to form optical networks and devices. In addition, such structures provide for waveguiding in liquids, enabling them to further be used in other applications such as optical probes and sensors.

An analog silicon retina with multichip configuration.

PubMed

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

A grid amplifier

NASA Technical Reports Server (NTRS)

Kim, Moonil; Weikle, Robert M., II; Hacker, Jonathan B.; Delisio, Michael P.; Rutledge, David B.; Rosenberg, James J.; Smith, R. P.

1991-01-01

A 50-MESFET grid amplifier is reported that has a gain of 11 dB at 3.3 GHz. The grid isolates the input from the output by using vertical polarization for the input beam and horizontal polarization for the transmitted output beam. The grid unit cell is a two-MESFET differential amplifier. A simple calibration procedure allows the gain to be calculated from a relative power measurement. This grid is a hybrid circuit, but the structure is suitable for fabrication as a monolithic wafer-scale integrated circuit, particularly at millimeter wavelengths.

Microprocessor-based integration of microfluidic control for the implementation of automated sensor monitoring and multithreaded optimization algorithms.

PubMed

Ezra, Elishai; Maor, Idan; Bavli, Danny; Shalom, Itai; Levy, Gahl; Prill, Sebastian; Jaeger, Magnus S; Nahmias, Yaakov

2015-08-01

Microfluidic applications range from combinatorial synthesis to high throughput screening, with platforms integrating analog perfusion components, digitally controlled micro-valves and a range of sensors that demand a variety of communication protocols. Currently, discrete control units are used to regulate and monitor each component, resulting in scattered control interfaces that limit data integration and synchronization. Here, we present a microprocessor-based control unit, utilizing the MS Gadgeteer open framework that integrates all aspects of microfluidics through a high-current electronic circuit that supports and synchronizes digital and analog signals for perfusion components, pressure elements, and arbitrary sensor communication protocols using a plug-and-play interface. The control unit supports an integrated touch screen and TCP/IP interface that provides local and remote control of flow and data acquisition. To establish the ability of our control unit to integrate and synchronize complex microfluidic circuits we developed an equi-pressure combinatorial mixer. We demonstrate the generation of complex perfusion sequences, allowing the automated sampling, washing, and calibrating of an electrochemical lactate sensor continuously monitoring hepatocyte viability following exposure to the pesticide rotenone. Importantly, integration of an optical sensor allowed us to implement automated optimization protocols that require different computational challenges including: prioritized data structures in a genetic algorithm, distributed computational efforts in multiple-hill climbing searches and real-time realization of probabilistic models in simulated annealing. Our system offers a comprehensive solution for establishing optimization protocols and perfusion sequences in complex microfluidic circuits.

Differential transimpedance amplifier circuit for correlated differential amplification

DOEpatents

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Non-invasive Brain Stimulation: Probing Intracortical Circuits and Improving Cognition in the Aging Brain

PubMed Central

Gomes-Osman, Joyce; Indahlastari, Aprinda; Fried, Peter J.; Cabral, Danylo L. F.; Rice, Jordyn; Nissim, Nicole R.; Aksu, Serkan; McLaren, Molly E.; Woods, Adam J.

2018-01-01

The impact of cognitive aging on brain function and structure is complex, and the relationship between aging-related structural changes and cognitive function are not fully understood. Physiological and pathological changes to the aging brain are highly variable, making it difficult to estimate a cognitive trajectory with which to monitor the conversion to cognitive decline. Beyond the information on the structural and functional consequences of cognitive aging gained from brain imaging and neuropsychological studies, non-invasive brain stimulation techniques such as transcranial magnetic stimulation (TMS) and transcranial direct current stimulation (tDCS) can enable stimulation of the human brain in vivo, offering useful insights into the functional integrity of intracortical circuits using electrophysiology and neuromodulation. TMS measurements can be used to identify and monitor changes in cortical reactivity, the integrity of inhibitory and excitatory intracortical circuits, the mechanisms of long-term potentiation (LTP)/depression-like plasticity and central cholinergic function. Repetitive TMS and tDCS can be used to modulate neuronal excitability and enhance cortical function, and thus offer a potential means to slow or reverse cognitive decline. This review will summarize and critically appraise relevant literature regarding the use of TMS and tDCS to probe cortical areas affected by the aging brain, and as potential therapeutic tools to improve cognitive function in the aging population. Challenges arising from intra-individual differences, limited reproducibility, and methodological differences will be discussed.

Improving depiction of temporal bone anatomy with low-radiation dose CT by an integrated circuit detector in pediatric patients: a preliminary study.

PubMed

He, Jingzhen; Zu, Yuliang; Wang, Qing; Ma, Xiangxing

2014-12-01

The purpose of this study was to determine the performance of low-dose computed tomography (CT) scanning with integrated circuit (IC) detector in defining fine structures of temporal bone in children by comparing with the conventional detector. The study was performed with the approval of our institutional review board and the patients' anonymity was maintained. A total of 86 children<3 years of age underwent imaging of temporal bone with low-dose CT (80 kV/150 mAs) equipped with either IC detector or conventional discrete circuit (DC) detector. The image noise was measured for quantitative analysis. Thirty-five structures of temporal bone were further assessed and rated by 2 radiologists for qualitative analysis. κ Statistics were performed to determine the agreement reached between the 2 radiologists on each image. Mann-Whitney U test was used to determine the difference in image quality between the 2 detector systems. Objective analysis showed that the image noise was significantly lower (P<0.001) with the IC detector than with the DC detector. The κ values for qualitative assessment of the 35 fine anatomical structures revealed high interobserver agreement. The delineation for 30 of the 35 landmarks (86%) with the IC detector was superior to that with the conventional DC detector (P<0.05) although there were no differences in the delineation of the remaining 5 structures (P>0.05). The low-dose CT images acquired with the IC detector provide better depiction of fine osseous structures of temporal bone than that with the conventional DC detector.

A way to improve dose rate laser simulation adequacy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Skorobogatov, P.K.; Nikiforov, A.Y.; Demidov, A.A.

1998-12-01

A method for improving laser simulation of dose rate radiation in silicon IC`s (Integrated Circuit) is analyzed based on the application of noncoherent laser radiation. Experimental validation was performed using test structures with up to 90% surface metallization coverage.

MMIC devices for active phased array antennas

NASA Technical Reports Server (NTRS)

Mittra, R.

1986-01-01

The use of finlines for microwave monolithic integrated circuit application in the 20 to 40 GHz frequency range. Other wave guiding structures, are also examined from a comparative point of view and some sonclusions are drawn on the basis of the results.

A photonic circuit for complementary frequency shifting, in-phase quadrature/single sideband modulation and frequency multiplication: analysis and integration feasibility

NASA Astrophysics Data System (ADS)

Hasan, Mehedi; Hu, Jianqi; Nikkhah, Hamdam; Hall, Trevor

2017-08-01

A novel photonic integrated circuit architecture for implementing orthogonal frequency division multiplexing by means of photonic generation of phase-correlated sub-carriers is proposed. The circuit can also be used for implementing complex modulation, frequency up-conversion of the electrical signal to the optical domain and frequency multiplication. The principles of operation of the circuit are expounded using transmission matrices and the predictions of the analysis are verified by computer simulation using an industry-standard software tool. Non-ideal scenarios that may affect the correct function of the circuit are taken into consideration and quantified. The discussion of integration feasibility is illustrated by a photonic integrated circuit that has been fabricated using 'library' components and which features most of the elements of the proposed circuit architecture. The circuit is found to be practical and may be fabricated in any material platform that offers a linear electro-optic modulator such as organic or ferroelectric thin films hybridized with silicon photonics.

GaAs Optoelectronic Integrated-Circuit Neurons

NASA Technical Reports Server (NTRS)

Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

1992-01-01

Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

DTIC Science & Technology

1993-02-10

new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

Semicustom integrated circuits and the standard transistor array radix (STAR)

NASA Technical Reports Server (NTRS)

Edge, T. M.

1977-01-01

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

Equivalent circuit models for interpreting impedance perturbation spectroscopy data

NASA Astrophysics Data System (ADS)

Smith, R. Lowell

2004-07-01

As in-situ structural integrity monitoring disciplines mature, there is a growing need to process sensor/actuator data efficiently in real time. Although smaller, faster embedded processors will contribute to this, it is also important to develop straightforward, robust methods to reduce the overall computational burden for practical applications of interest. This paper addresses the use of equivalent circuit modeling techniques for inferring structure attributes monitored using impedance perturbation spectroscopy. In pioneering work about ten years ago significant progress was associated with the development of simple impedance models derived from the piezoelectric equations. Using mathematical modeling tools currently available from research in ultrasonics and impedance spectroscopy is expected to provide additional synergistic benefits. For purposes of structural health monitoring the objective is to use impedance spectroscopy data to infer the physical condition of structures to which small piezoelectric actuators are bonded. Features of interest include stiffness changes, mass loading, and damping or mechanical losses. Equivalent circuit models are typically simple enough to facilitate the development of practical analytical models of the actuator-structure interaction. This type of parametric structure model allows raw impedance/admittance data to be interpreted optimally using standard multiple, nonlinear regression analysis. One potential long-term outcome is the possibility of cataloging measured viscoelastic properties of the mechanical subsystems of interest as simple lists of attributes and their statistical uncertainties, whose evolution can be followed in time. Equivalent circuit models are well suited for addressing calibration and self-consistency issues such as temperature corrections, Poisson mode coupling, and distributed relaxation processes.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-17

... Integrated Circuit Semiconductor Chips and Products Containing the Same; Notice of a Commission Determination... certain large scale integrated circuit semiconductor chips and products containing same by reason of... existence of a domestic industry. The Commission's notice of investigation named several respondents...

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-03-29

... INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and... Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on... Commission's electronic docket (EDIS) at http://edis.usitc.gov , and will be available for inspection during...

77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-06

... INTERNATIONAL TRADE COMMISSION [Docket No. 2899] Certain Integrated Circuit Packages Provided With... complaint entitled Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and..., telephone (202) 205-2000. The public version of the complaint can be accessed on the Commission's electronic...

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

PubMed

Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

2008-02-01

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

Integrating a Silicon Solar Cell with a Triboelectric Nanogenerator via a Mutual Electrode for Harvesting Energy from Sunlight and Raindrops.

PubMed

Liu, Yuqiang; Sun, Na; Liu, Jiawei; Wen, Zhen; Sun, Xuhui; Lee, Shuit-Tong; Sun, Baoquan

2018-03-27

Solar cells, as promising devices for converting light into electricity, have a dramatically reduced performance on rainy days. Here, an energy harvesting structure that integrates a solar cell and a triboelectric nanogenerator (TENG) device is built to realize power generation from both sunlight and raindrops. A heterojunction silicon (Si) solar cell is integrated with a TENG by a mutual electrode of a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) film. Regarding the solar cell, imprinted PEDOT:PSS is used to reduce light reflection, which leads to an enhanced short-circuit current density. A single-electrode-mode water-drop TENG on the solar cell is built by combining imprinted polydimethylsiloxane (PDMS) as a triboelectric material combined with a PEDOT:PSS layer as an electrode. The increasing contact area between the imprinted PDMS and water drops greatly improves the output of the TENG with a peak short-circuit current of ∼33.0 nA and a peak open-circuit voltage of ∼2.14 V, respectively. The hybrid energy harvesting system integrated electrode configuration can combine the advantages of high current level of a solar cell and high voltage of a TENG device, promising an efficient approach to collect energy from the environment in different weather conditions.

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

PubMed Central

Vidor, Fábio F.; Meyers, Thorsten; Hilleringmann, Ulrich

2016-01-01

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates. PMID:28335282

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications.

PubMed

Vidor, Fábio F; Meyers, Thorsten; Hilleringmann, Ulrich

2016-08-23

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high- k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the I ON / I OFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V / V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

Impurity engineering of Czochralski silicon used for ultra large-scaled-integrated circuits

NASA Astrophysics Data System (ADS)

Yang, Deren; Chen, Jiahe; Ma, Xiangyang; Que, Duanlin

2009-01-01

Impurities in Czochralski silicon (Cz-Si) used for ultra large-scaled-integrated (ULSI) circuits have been believed to deteriorate the performance of devices. In this paper, a review of the recent processes from our investigation on internal gettering in Cz-Si wafers which were doped with nitrogen, germanium and/or high content of carbon is presented. It has been suggested that those impurities enhance oxygen precipitation, and create both denser bulk microdefects and enough denuded zone with the desirable width, which is benefit of the internal gettering of metal contamination. Based on the experimental facts, a potential mechanism of impurity doping on the internal gettering structure is interpreted and, a new concept of 'impurity engineering' for Cz-Si used for ULSI is proposed.

Integrated circuit test-port architecture and method and apparatus of test-port generation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Teifel, John

A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. Themore » computer then completes the generation of the RTL code.« less

Curvilinear electronics formed using silicon membrane circuits and elastomeric transfer elements.

PubMed

Ko, Heung Cho; Shin, Gunchul; Wang, Shuodao; Stoykovich, Mark P; Lee, Jeong Won; Kim, Dong-Hun; Ha, Jeong Sook; Huang, Yonggang; Hwang, Keh-Chih; Rogers, John A

2009-12-01

Materials and methods to achieve electronics intimately integrated on the surfaces of substrates with complex, curvilinear shapes are described. The approach exploits silicon membranes in circuit mesh structures that can be deformed in controlled ways using thin, elastomeric films. Experimental and theoretical studies of the micromechanics of such curvilinear electronics demonstrate the underlying concepts. Electrical measurements illustrate the high yields that can be obtained. The results represent significant experimental and theoretical advances over recently reported concepts for creating hemispherical photodetectors in electronic eye cameras and for using printable silicon nanoribbons/membranes in flexible electronics. The results might provide practical routes to the integration of high performance electronics with biological tissues and other systems of interest for new applications.

A three-dimensional integrated nanogenerator for effectively harvesting sound energy from the environment

NASA Astrophysics Data System (ADS)

Liu, Jinmei; Cui, Nuanyang; Gu, Long; Chen, Xiaobo; Bai, Suo; Zheng, Youbin; Hu, Caixia; Qin, Yong

2016-02-01

An integrated triboelectric nanogenerator (ITNG) with a three-dimensional structure benefiting sound propagation and adsorption is demonstrated to more effectively harvest sound energy with improved output performance. With different multifunctional integrated layers working harmonically, it could generate a short-circuit current up to 2.1 mA, an open-circuit voltage up to 232 V and the maximum charging rate can reach 453 μC s-1 for a 1 mF capacitor, which are 4.6 times, 2.6 times and 7.4 times the highest reported values, respectively. Further study shows that the ITNG works well under sound in a wide range of sound intensity levels (SILs) and frequencies, and its output is sensitive to the SIL and frequency of the sound, which reveals that the ITNG can act as a self-powered active sensor for real-time noise surveillance and health care. Moreover, this generator can be used to directly power the Fe(OH)3 sol electrophoresis and shows great potential as a wireless power supply in the electrochemical industry.An integrated triboelectric nanogenerator (ITNG) with a three-dimensional structure benefiting sound propagation and adsorption is demonstrated to more effectively harvest sound energy with improved output performance. With different multifunctional integrated layers working harmonically, it could generate a short-circuit current up to 2.1 mA, an open-circuit voltage up to 232 V and the maximum charging rate can reach 453 μC s-1 for a 1 mF capacitor, which are 4.6 times, 2.6 times and 7.4 times the highest reported values, respectively. Further study shows that the ITNG works well under sound in a wide range of sound intensity levels (SILs) and frequencies, and its output is sensitive to the SIL and frequency of the sound, which reveals that the ITNG can act as a self-powered active sensor for real-time noise surveillance and health care. Moreover, this generator can be used to directly power the Fe(OH)3 sol electrophoresis and shows great potential as a wireless power supply in the electrochemical industry. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr09087c

Hippocampal-medial prefrontal circuit supports memory updating during learning and post-encoding rest

PubMed Central

Schlichting, Margaret L.; Preston, Alison R.

2015-01-01

Learning occurs in the context of existing memories. Encountering new information that relates to prior knowledge may trigger integration, whereby established memories are updated to incorporate new content. Here, we provide a critical test of recent theories suggesting hippocampal (HPC) and medial prefrontal (MPFC) involvement in integration, both during and immediately following encoding. Human participants with established memories for a set of initial (AB) associations underwent fMRI scanning during passive rest and encoding of new related (BC) and unrelated (XY) pairs. We show that HPC-MPFC functional coupling during learning was more predictive of trial-by-trial memory for associations related to prior knowledge relative to unrelated associations. Moreover, the degree to which HPC-MPFC functional coupling was enhanced following overlapping encoding was related to memory integration behavior across participants. We observed a dissociation between anterior and posterior MPFC, with integration signatures during post-encoding rest specifically in the posterior subregion. These results highlight the persistence of integration signatures into post-encoding periods, indicating continued processing of interrelated memories during rest. We also interrogated the coherence of white matter tracts to assess the hypothesis that integration behavior would be related to the integrity of the underlying anatomical pathways. Consistent with our predictions, more coherent HPC-MPFC white matter structure was associated with better performance across participants. This HPC-MPFC circuit also interacted with content-sensitive visual cortex during learning and rest, consistent with reinstatement of prior knowledge to enable updating. These results show that the HPC-MPFC circuit supports on- and offline integration of new content into memory. PMID:26608407

Photonic emitters and circuits based on colloidal quantum dot composites

NASA Astrophysics Data System (ADS)

Menon, Vinod M.; Husaini, Saima; Valappil, Nikesh; Luberto, Matthew

2009-02-01

We discuss our work on light emitters and photonic circuits realized using colloidal quantum dot composites. Specifically we will report our recent work on flexible microcavity laser, microdisk emitters and integrated active - passive waveguides. The entire microcavity laser structure was realized using spin coating and consisted of an all-polymer distributed Bragg reflector with a poly-vinyl carbazole cavity layer embedded with InGaP/ZnS colloidal quantum dots. These microcavities can be peeled off the substrate yielding a flexible structure that can conform to any shape and whose emission spectra can be mechanically tuned. The microdisk emitters and the integrated waveguide structures were realized using soft lithography and photo-lithography, respectively and were fabricated using a composite consisting of quantum dots embedded in SU8 matrix. Finally, we will discuss the effect of the host matrix on the optical properties of the quantum dots using results of steady-state and time-resolved luminescence measurements. In addition to their specific functionalities, these novel device demonstrations and their development present a low cost alternative to the traditional photonic device fabrication techniques.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

CMOS compatible IR sensors by cytochrome c protein

NASA Astrophysics Data System (ADS)

Liao, Chien-Jen; Su, Guo-Dung

2013-09-01

In recent years, due to the progression of the semiconductor industrial, the uncooled Infrared sensor - microbolometer has opened the opportunity for achieving low cost infrared imaging systems for both military and commercial applications. Therefore, various fabrication processes and different materials based microbolometer have been developed sequentially. The cytochrome c (protein) thin film has be reported high temperature coefficient of resistance (TCR), which is related to the performance of microbolometer directly. Hence the superior TCR value will increase the performance of microbolometer. In this paper, we introduced a novel fabrication process using aluminum which is compatible with the Taiwan Semiconductor Manufacture Company (TSMC) D35 2P4M process as the main structure material, which benefits the device to integrate with readout integrated circuit (ROIC).The aluminum split structure is suspended by sacrificial layer utilizing the standard photolithography technology and chemical etching. The height and thickness of the structure are already considered. Besides, cytochrome c solutions were ink-jetted onto the aluminum structure by using the inkjet printer, applying precise control of the Infrared absorbing layer. In measurement, incident Infrared radiation can be detected and later the heat can be transmitted to adjacent pads to readout the signal. This approach applies an inexpensive and simple fabrication process and makes the device suitable for integration. In addition, the performance can be further improved with low noise readout circuits.

Propagation of eigenmodes and transfer functions in waveguide WDM structures

NASA Astrophysics Data System (ADS)

Mashkov, Vladimir A.; Francoeur, S.; Geuss, U.; Neiser, K.; Temkin, Henryk

1998-02-01

A method of propagation functions and transfer amplitudes suitable for the design of integrated optical circuits is presented. The method is based on vectorial formulation of electrodynamics: the distributions and propagation of electromagnetic fields in optical circuits is described by equivalent surface sources. This approach permits a division of complex optical waveguide structures into sets of primitive blocks and to separately calculate the transfer function and the transfer amplitude for each block. The transfer amplitude of the entire optical system is represented by a convolution of transfer amplitudes of its primitive blocks. The eigenvalues and eigenfunctions of arbitrary waveguide structure are obtained in the WKB approximation and compared with other methods. The general approach is illustrated with the transfer amplitude calculations for Dragone's star coupler and router.

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits.

PubMed

Khuri-Yakub, B T; Oralkan, Omer; Nikoozadeh, Amin; Wygant, Ira O; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O'Donnell, Matthew; Truong, Uyen; Sahn, David J

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Oscillatory integration windows in neurons

PubMed Central

Gupta, Nitin; Singh, Swikriti Saran; Stopfer, Mark

2016-01-01

Oscillatory synchrony among neurons occurs in many species and brain areas, and has been proposed to help neural circuits process information. One hypothesis states that oscillatory input creates cyclic integration windows: specific times in each oscillatory cycle when postsynaptic neurons become especially responsive to inputs. With paired local field potential (LFP) and intracellular recordings and controlled stimulus manipulations we directly test this idea in the locust olfactory system. We find that inputs arriving in Kenyon cells (KCs) sum most effectively in a preferred window of the oscillation cycle. With a computational model, we show that the non-uniform structure of noise in the membrane potential helps mediate this process. Further experiments performed in vivo demonstrate that integration windows can form in the absence of inhibition and at a broad range of oscillation frequencies. Our results reveal how a fundamental coincidence-detection mechanism in a neural circuit functions to decode temporally organized spiking. PMID:27976720

75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-05-05

... Integrated Circuit Semiconductor Chips and Products Containing Same; Notice of Investigation AGENCY: U.S... of certain large scale integrated circuit semiconductor chips and products containing same by reason... alleges that an industry in the United States exists as required by subsection (a)(2) of section 337. The...

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-04

... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... that there exists a domestic industry with respect to each of the asserted patents. The complaint named...

Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system

NASA Astrophysics Data System (ADS)

Liu, Yang; Wang, Sheng; Liu, Huaping; Peng, Lian-Mao

2017-06-01

Single material-based monolithic optoelectronic integration with complementary metal oxide semiconductor-compatible signal processing circuits is one of the most pursued approaches in the post-Moore era to realize rapid data communication and functional diversification in a limited three-dimensional space. Here, we report an electrically driven carbon nanotube-based on-chip three-dimensional optoelectronic integrated circuit. We demonstrate that photovoltaic receivers, electrically driven transmitters and on-chip electronic circuits can all be fabricated using carbon nanotubes via a complementary metal oxide semiconductor-compatible low-temperature process, providing a seamless integration platform for realizing monolithic three-dimensional optoelectronic integrated circuits with diversified functionality such as the heterogeneous AND gates. These circuits can be vertically scaled down to sub-30 nm and operates in photovoltaic mode at room temperature. Parallel optical communication between functional layers, for example, bottom-layer digital circuits and top-layer memory, has been demonstrated by mapping data using a 2 × 2 transmitter/receiver array, which could be extended as the next generation energy-efficient signal processing paradigm.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Multichannel, Active Low-Pass Filters

NASA Technical Reports Server (NTRS)

Lev, James J.

1989-01-01

Multichannel integrated circuits cascaded to obtain matched characteristics. Gain and phase characteristics of channels of multichannel, multistage, active, low-pass filter matched by making filter of cascaded multichannel integrated-circuit operational amplifiers. Concept takes advantage of inherent equality of electrical characteristics of nominally-identical circuit elements made on same integrated-circuit chip. Characteristics of channels vary identically with changes in temperature. If additional matched channels needed, chips containing more than two operational amplifiers apiece (e.g., commercial quad operational amplifliers) used. Concept applicable to variety of equipment requiring matched gain and phase in multiple channels - radar, test instruments, communication circuits, and equipment for electronic countermeasures.

The use of test structures for reliability prediction and process control of integrated circuits and photovoltaics

NASA Astrophysics Data System (ADS)

Trachtenberg, I.

How a reliability model might be developed with new data from accelerated stress testing, failure mechanisms, process control monitoring, and test structure evaluations is illustrated. The effects of the acceleration of temperature on operating life is discussed. Test structures that will further accelerate the failure rate are discussed. Corrosion testing is addressed. The uncoated structure is encapsulated in a variety of mold compounds and subjected to pressure-cooker testing.

Structural Covariance of the Prefrontal-Amygdala Pathways Associated with Heart Rate Variability.

PubMed

Wei, Luqing; Chen, Hong; Wu, Guo-Rong

2018-01-01

The neurovisceral integration model has shown a key role of the amygdala in neural circuits underlying heart rate variability (HRV) modulation, and suggested that reciprocal connections from amygdala to brain regions centered on the central autonomic network (CAN) are associated with HRV. To provide neuroanatomical evidence for these theoretical perspectives, the current study used covariance analysis of MRI-based gray matter volume (GMV) to map structural covariance network of the amygdala, and then determined whether the interregional structural correlations related to individual differences in HRV. The results showed that covariance patterns of the amygdala encompassed large portions of cortical (e.g., prefrontal, cingulate, and insula) and subcortical (e.g., striatum, hippocampus, and midbrain) regions, lending evidence from structural covariance analysis to the notion that the amygdala was a pivotal node in neural pathways for HRV modulation. Importantly, participants with higher resting HRV showed increased covariance of amygdala to dorsal medial prefrontal cortex and anterior cingulate cortex (dmPFC/dACC) extending into adjacent medial motor regions [i.e., pre-supplementary motor area (pre-SMA)/SMA], demonstrating structural covariance of the prefrontal-amygdala pathways implicated in HRV, and also implying that resting HRV may reflect the function of neural circuits underlying cognitive regulation of emotion as well as facilitation of adaptive behaviors to emotion. Our results, thus, provide anatomical substrates for the neurovisceral integration model that resting HRV may index an integrative neural network which effectively organizes emotional, cognitive, physiological and behavioral responses in the service of goal-directed behavior and adaptability.

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

NASA Technical Reports Server (NTRS)

Olson, E. M.

1986-01-01

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1993-12-31

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components.« less

Reusable vibration resistant integrated circuit mounting socket

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evans, C.N.

1995-08-29

This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuitmore » lead can be removed from the socket without damage either to the lead or to the socket components. 11 figs.« less

Novel Spiral-Like Electrode Structure Design for Realization of Two Modes of Energy Harvesting.

PubMed

Chen, Lin; Guo, Hengyu; Xia, Xiaona; Liu, Guanlin; Shi, Haofei; Wang, Mingjun; Xi, Yi; Hu, Chenguo

2015-08-05

A planar spiral-like electrodes (PSE) based triboelectric generator has been designed for harvesting rotary mechanical energy to translate into electricity. The performance of the PSE-triboelectric generator with different cycles of spiral-like electrode strip at different rotating speeds is investigated, which demonstrates the open-circuit voltage and short-circuit current of 470 V and 9.0 μA at rotating speed of 500 r/min with three cycles. In addition, a novel coaxially integrated multilayered PSE-triboelectric generator is built, which can enhance the output of the power effectively. The short-circuit current, the open-circuit voltage, and output power reach to 41.55 μA, 500 V, and 11.73 mW, respectively, at rotating speed of 700 r/min. The output power of the multilayered PSE-triboelectric generator can drive 200 LEDs connected in antiparallel and charge a 110 μF commercial capacitor to 6 V in 23 s. Besides, due to the spiral-like electrode structure, the PSE-generator can work simultaneously in the modes of triboelectricity and electromagnetic induced electricity by sticking a small magnet on the rotating disk. The electromagnetic induced output power reaches to 21 μW at a loading resistance of 2 Ω at a rotating rate of 200 r/min. The spiral-like electrode structure not only broadens the electrode structure design but also adds a new function to the electrode.

670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Schlecht, Erich T.; Lee, Choonsup; Lin, Robert H.; Gill, John J.; Mehdi, Imran; Sin, Seth; Deal, William; Loi, Kwok K.; Nam, Peta;

Memory formation orchestrates the wiring of adult-born hippocampal neurons into brain circuits.

PubMed

Petsophonsakul, Petnoi; Richetin, Kevin; Andraini, Trinovita; Roybon, Laurent; Rampon, Claire

2017-08-01

During memory formation, structural rearrangements of dendritic spines provide a mean to durably modulate synaptic connectivity within neuronal networks. New neurons generated throughout the adult life in the dentate gyrus of the hippocampus contribute to learning and memory. As these neurons become incorporated into the network, they generate huge numbers of new connections that modify hippocampal circuitry and functioning. However, it is yet unclear as to how the dynamic process of memory formation influences their synaptic integration into neuronal circuits. New memories are established according to a multistep process during which new information is first acquired and then consolidated to form a stable memory trace. Upon recall, memory is transiently destabilized and vulnerable to modification. Using contextual fear conditioning, we found that learning was associated with an acceleration of dendritic spines formation of adult-born neurons, and that spine connectivity becomes strengthened after memory consolidation. Moreover, we observed that afferent connectivity onto adult-born neurons is enhanced after memory retrieval, while extinction training induces a change of spine shapes. Together, these findings reveal that the neuronal activity supporting memory processes strongly influences the structural dendritic integration of adult-born neurons into pre-existing neuronal circuits. Such change of afferent connectivity is likely to impact the overall wiring of hippocampal network, and consequently, to regulate hippocampal function.

A monolithic lead sulfide-silicon MOS integrated-circuit structure

NASA Technical Reports Server (NTRS)

Jhabvala, M. D.; Barrett, J. R.

1982-01-01

A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Technical Reports Server (NTRS)

Jones, C. W. (Editor)

1985-01-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Study of Ni Metallization in Macroporous Si Using Wet Chemistry for Radio Frequency Cross-Talk Isolation in Mixed Signal Integrated Circuits

PubMed Central

Zhang, Xi; Xu, Chengkun; Chong, Kyuchul; Tu, King-Ning; Xie, Ya-Hong

2011-01-01

A highly conductive moat or Faraday cage of through-the-wafer thickness in Si substrate was proposed to be effective in shielding electromagnetic interference thereby reducing radio frequency (RF) cross-talk in high performance mixed signal integrated circuits. Such a structure was realized by metallization of selected ultra-high-aspect-ratio macroporous regions that were electrochemically etched in p− Si substrates. The metallization process was conducted by means of wet chemistry in an alkaline aqueous solution containing Ni2+ without reducing agent. It is found that at elevated temperature during immersion, Ni2+ was rapidly reduced and deposited into macroporous Si and a conformal metallization of the macropore sidewalls was obtained in a way that the entire porous Si framework was converted to Ni. A conductive moat was as a result incorporated into p− Si substrate. The experimentally measured reduction of crosstalk in this structure is 5~18 dB at frequencies up to 35 GHz. PMID:28879960

Study of Ni Metallization in Macroporous Si Using Wet Chemistry for Radio Frequency Cross-Talk Isolation in Mixed Signal Integrated Circuits.

PubMed

Zhang, Xi; Xu, Chengkun; Chong, Kyuchul; Tu, King-Ning; Xie, Ya-Hong

2011-05-25

A highly conductive moat or Faraday cage of through-the-wafer thickness in Si substrate was proposed to be effective in shielding electromagnetic interference thereby reducing radio frequency (RF) cross-talk in high performance mixed signal integrated circuits. Such a structure was realized by metallization of selected ultra-high-aspect-ratio macroporous regions that were electrochemically etched in p - Si substrates. The metallization process was conducted by means of wet chemistry in an alkaline aqueous solution containing Ni 2+ without reducing agent. It is found that at elevated temperature during immersion, Ni 2+ was rapidly reduced and deposited into macroporous Si and a conformal metallization of the macropore sidewalls was obtained in a way that the entire porous Si framework was converted to Ni. A conductive moat was as a result incorporated into p - Si substrate. The experimentally measured reduction of crosstalk in this structure is 5~18 dB at frequencies up to 35 GHz.

Brain/MINDS: brain-mapping project in Japan

PubMed Central

Okano, Hideyuki; Miyawaki, Atsushi; Kasai, Kiyoto

2015-01-01

There is an emerging interest in brain-mapping projects in countries across the world, including the USA, Europe, Australia and China. In 2014, Japan started a brain-mapping project called Brain Mapping by Integrated Neurotechnologies for Disease Studies (Brain/MINDS). Brain/MINDS aims to map the structure and function of neuronal circuits to ultimately understand the vast complexity of the human brain, and takes advantage of a unique non-human primate animal model, the common marmoset (Callithrix jacchus). In Brain/MINDS, the RIKEN Brain Science Institute acts as a central institute. The objectives of Brain/MINDS can be categorized into the following three major subject areas: (i) structure and functional mapping of a non-human primate brain (the marmoset brain); (ii) development of innovative neurotechnologies for brain mapping; and (iii) human brain mapping; and clinical research. Brain/MINDS researchers are highly motivated to identify the neuronal circuits responsible for the phenotype of neurological and psychiatric disorders, and to understand the development of these devastating disorders through the integration of these three subject areas. PMID:25823872

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

NASA Astrophysics Data System (ADS)

Jones, C. W.

1985-12-01

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

PubMed

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Fiber-Optic Distribution Of Pulsed Power To Multiple Sensors

NASA Technical Reports Server (NTRS)

Kirkham, Harold

1996-01-01

Optoelectronic systems designed according to time-sharing scheme distribute optical power to multiple integrated-circuit-based sensors in fiber-optic networks. Networks combine flexibility of electronic sensing circuits with advantage of electrical isolation afforded by use of optical fibers instead of electrical conductors to transmit both signals and power. Fiber optics resist corrosion and immune to electromagnetic interference. Sensor networks of this type useful in variety of applications; for example, in monitoring strains in aircraft, buildings, and bridges, and in monitoring and controlling shapes of flexible structures.

Olfactory Cued Learning Paradigm.

PubMed

Liu, Gary; McClard, Cynthia K; Tepe, Burak; Swanson, Jessica; Pekarek, Brandon; Panneerselvam, Sugi; Arenkiel, Benjamin R

2017-05-05

Sensory stimulation leads to structural changes within the CNS (Central Nervous System), thus providing the fundamental mechanism for learning and memory. The olfactory circuit offers a unique model for studying experience-dependent plasticity, partly due to a continuous supply of integrating adult born neurons. Our lab has recently implemented an olfactory cued learning paradigm in which specific odor pairs are coupled to either a reward or punishment to study downstream circuit changes. The following protocol outlines the basic set up for our learning paradigm. Here, we describe the equipment setup, programming of software, and method of behavioral training.

Characterization of quantum well structures using a photocathode electron microscope

NASA Technical Reports Server (NTRS)

Spencer, Michael G.; Scott, Craig J.

1989-01-01

Present day integrated circuits pose a challenge to conventional electronic and mechanical test methods. Feature sizes in the submicron and nanometric regime require radical approaches in order to facilitate electrical contact to circuits and devices being tested. In addition, microwave operating frequencies require careful attention to distributed effects when considering the electrical signal paths within and external to the device under test. An alternative testing approach which combines the best of electrical and optical time domain testing is presented, namely photocathode electron microscope quantitative voltage contrast (PEMQVC).

Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

PubMed Central

Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

2010-01-01

Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

Rectifying the output of vibrational piezoelectric energy harvester using quantum dots

NASA Astrophysics Data System (ADS)

Li, Lijie

2017-03-01

Piezoelectric energy harvester scavenges mechanical vibrations and generates electricity. Researchers have strived to optimize the electromechanical structures and to design necessary external power management circuits, aiming to deliver high power and rectified outputs ready for serving as batteries. Complex deformation of the mechanical structure results in charges with opposite polarities appearing on same surface, leading to current loss in the attached metal electrode. External power management circuits such as rectifiers comprise diodes that consume power and have undesirable forward bias. To address the above issues, we devise a novel integrated piezoelectric energy harvesting device that is structured by stacking a layer of quantum dots (QDs) and a layer of piezoelectric material. We find that the QD can rectify electrical charges generated from the piezoelectric material because of its adaptable conductance to the electrochemical potentials of both sides of the QDs layer, so that electrical current causing energy loss on the same surface of the piezoelectric material can be minimized. The QDs layer has the potential to replace external rectification circuits providing a much more compact and less power-consumption solution.

Simple photometer circuits using modular electronic components

NASA Technical Reports Server (NTRS)

Wampler, J. E.

1975-01-01

Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

LEC GaAs for integrated circuit applications

NASA Technical Reports Server (NTRS)

Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

1984-01-01

Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

NASA Technical Reports Server (NTRS)

Johnston, Allan H.; Rax, Bernard G.

2006-01-01

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

Ka-band to L-band frequency down-conversion based on III-V-on-silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Van Gasse, K.; Wang, Z.; Uvin, S.; De Deckere, B.; Mariën, J.; Thomassen, L.; Roelkens, G.

2017-12-01

In this work, we present the design, simulation and characterization of a frequency down-converter based on III-V-on-silicon photonic integrated circuit technology. We first demonstrate the concept using commercial discrete components, after which we demonstrate frequency conversion using an integrated mode-locked laser and integrated modulator. In our experiments, five channels in the Ka-band (27.5-30 GHz) with 500 MHz bandwidth are down-converted to the L-band (1.5 GHz). The breadboard demonstration shows a conversion efficiency of - 20 dB and a flat response over the 500 MHz bandwidth. The simulation of a fully integrated circuit indicates that a positive conversion gain can be obtained on a millimeter-sized photonic integrated circuit.

Microwave GaAs Integrated Circuits On Quartz Substrates

NASA Technical Reports Server (NTRS)

Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

1994-01-01

Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

Geometric dependence of the parasitic components and thermal properties of HEMTs

NASA Astrophysics Data System (ADS)

Vun, Peter V.; Parker, Anthony E.; Mahon, Simon J.; Fattorini, Anthony

2007-12-01

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

NASA Technical Reports Server (NTRS)

1983-01-01

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

A comparison of hardware description languages. [describing digital systems structure and behavior to a computer

NASA Technical Reports Server (NTRS)

Shiva, S. G.

1978-01-01

Several high level languages which evolved over the past few years for describing and simulating the structure and behavior of digital systems, on digital computers are assessed. The characteristics of the four prominent languages (CDL, DDL, AHPL, ISP) are summarized. A criterion for selecting a suitable hardware description language for use in an automatic integrated circuit design environment is provided.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

PubMed

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

PubMed

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

A lumped parameter mathematical model for simulation of subsonic wind tunnels

NASA Technical Reports Server (NTRS)

Krosel, S. M.; Cole, G. L.; Bruton, W. M.; Szuch, J. R.

1986-01-01

Equations for a lumped parameter mathematical model of a subsonic wind tunnel circuit are presented. The equation state variables are internal energy, density, and mass flow rate. The circuit model is structured to allow for integration and analysis of tunnel subsystem models which provide functions such as control of altitude pressure and temperature. Thus the model provides a useful tool for investigating the transient behavior of the tunnel and control requirements. The model was applied to the proposed NASA Lewis Altitude Wind Tunnel (AWT) circuit and included transfer function representations of the tunnel supply/exhaust air and refrigeration subsystems. Both steady state and frequency response data are presented for the circuit model indicating the type of results and accuracy that can be expected from the model. Transient data for closed loop control of the tunnel and its subsystems are also presented, demonstrating the model's use as a control analysis tool.

Technical Reliability Studies. EOS/ESD Technology Abstracts

DTIC Science & Technology

1982-01-01

RESISTANT BIPOLAR TRANSISTOR DESIGN AND ITS APPLICATIONS TO LINEAR INTEGRATED CIRCUITS 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR 15786 SOME...T.M. 16476 STATIC DISCHARGE MODELING TECHNIQUES FOR EVALUATION OF INTEGRATED (FET) CIRCUIT DESTRUCTION 16145 MODULE ELECTAOSTATIC DISCHARGE SIMULATOR...PLASTIC LSI CIRCUITS PRklE, L.A., II 16145 MODULE ELECTROSTATIC DISCHARGE SIMULATOR PRICE, R.D. 13455 EVALUATION OF PLASTIC LSI CIRCUITS PSHAENICH, A

Silicon millimetre-wave integrated-circuit (SIMMWIC) SPST switch

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-10-01

The first silicon millimetre-wave integrated circuit (SIMMWIC) has been successfully fabricated. This circuit is a monolithic SPST switch with a 3 dB bandwidth of 20 percent and a minimum isolation of 21.6 dB across the band (centre frequency is 36.75 GHz). This monolithic circuit is a low-cost reproducible building block for all millimetre-wave control applications.

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

DTIC Science & Technology

2015-12-24

Signal to Noise Ratio SPICE Simulation Program with Integrated Circuit Emphasis TIFF Tagged Image File Format USC University of Southern California xvii...sources can create errors in digital circuits. These effects can be simulated using Simulation Program with Integrated Circuit Emphasis ( SPICE ) or...compute summary statistics. 4.1 Circuit Simulations Noisy analog circuits can be simulated in SPICE or Cadence SpectreTM software via noisy voltage

Nanophotonic integrated circuits from nanoresonators grown on silicon.

PubMed

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ryu, C.; Boshier, M. G.

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through theirmore » electric polarizability. Moreover, the source of coherent matter waves is a Bose–Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry.« less

Integrated testing system FiTest for diagnosis of PCBA

NASA Astrophysics Data System (ADS)

Bogdan, Arkadiusz; Lesniak, Adam

2016-12-01

This article presents the innovative integrated testing system FiTest for automatic, quick inspection of printed circuit board assemblies (PCBA) manufactured in Surface Mount Technology (SMT). Integration of Automatic Optical Inspection (AOI), In-Circuit Tests (ICT) and Functional Circuit Tests (FCT) resulted in universal hardware platform for testing variety of electronic circuits. The platform provides increased test coverage, decreased level of false calls and optimization of test duration. The platform is equipped with powerful algorithms performing tests in a stable and repetitive way and providing effective management of diagnosis.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

NASA Astrophysics Data System (ADS)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Analog integrated circuits design for processing physiological signals.

PubMed

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

InP-based three-dimensional photonic integrated circuits

NASA Astrophysics Data System (ADS)

Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

2001-10-01

Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure. This additional beam routing flexibility allows significant size reduction and process simplification without sacrificing device performance. This innovative 3-D PIC technology platform can be easily extended to create surface-emitting lasers integrated with power monitoring detectors, micro-lenses, external modulators, amplifiers, and other passive and active components. Such added functionality can produce cost--effective solutions for the highest-end laser transmitters required for datacom and short range telecom networks, as well as fiber channels and other cost and performance sensitive applications. We present results for 1310 nm photonic IC surface-emitting laser transmitters operating at 2.5 Gbps without active thermal electric cooling.

Single Crystal Diffractometry

NASA Astrophysics Data System (ADS)

Arndt, U. W.; Willis, B. T. M.

2009-06-01

Preface; Acknowledgements; Part I. Introduction; Part II. Diffraction Geometry; Part III. The Design of Diffractometers; Part IV. Detectors; Part V. Electronic Circuits; Part VI. The Production of the Primary Beam (X-rays); Part VII. The Production of the Primary Beam (Neutrons); Part VIII. The Background; Part IX. Systematic Errors in Measuring Relative Integrated Intensities; Part X. Procedure for Measuring Integrated Intensities; Part XI. Derivation and Accuracy of Structure Factors; Part XII. Computer Programs and On-line Control; Appendix; References; Index.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

PubMed

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor)

1988-01-01

A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

The Effects of Space Radiation on Linear Integrated Circuit

NASA Technical Reports Server (NTRS)

Johnston, A.

2000-01-01

Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

35 GHz integrated circuit rectifying antenna with 33 percent efficiency

NASA Technical Reports Server (NTRS)

Yoo, T.-W.; Chang, K.

1991-01-01

A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

A megahertz-frequency tunable piecewise-linear electromechanical resonator realized via nonlinear feedback

NASA Astrophysics Data System (ADS)

Bajaj, Nikhil; Chiu, George T.-C.; Rhoads, Jeffrey F.

2018-07-01

Vibration-based sensing modalities traditionally have relied upon monitoring small shifts in natural frequency in order to detect structural changes (such as those in mass or stiffness). In contrast, bifurcation-based sensing schemes rely on the detection of a qualitative change in the behavior of a system as a parameter is varied. This can produce easy-to-detect changes in response amplitude with high sensitivity to structural change, but requires resonant devices with specific dynamic behavior which is not always easily reproduced. Desirable behavior for such devices can be produced reliably via nonlinear feedback circuitry, but has in past efforts been largely limited to sub-MHz operation, partially due to the time delay limitations present in certain nonlinear feedback circuits, such as multipliers. This work demonstrates the design and implementation of a piecewise-linear resonator realized via diode- and integrated circuit-based feedback electronics and a quartz crystal resonator. The proposed system is fabricated and characterized, and the creation and selective placement of the bifurcation points of the overall electromechanical system is demonstrated by tuning the circuit gains. The demonstrated circuit operates at 16 MHz. Preliminary modeling and analysis is presented that qualitatively agrees with the experimentally-observed behavior.

Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

PubMed

Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

2015-06-01

Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

Silicon photonic integrated circuit for fast and precise dual-comb distance metrology.

PubMed

Weimann, C; Lauermann, M; Hoeller, F; Freude, W; Koos, C

2017-11-27

We demonstrate an optical distance sensor integrated on a silicon photonic chip with a footprint of well below 1 mm 2 . The integrated system comprises a heterodyne receiver structure with tunable power splitting ratio and on-chip photodetectors. The functionality of the device is demonstrated in a synthetic-wavelength interferometry experiment using frequency combs as optical sources. We obtain accurate and fast distance measurements with an unambiguity range of 3.75 mm, a root-mean-square error of 3.4 µm and acquisition times of 14 µs.

Structural Covariance of the Prefrontal-Amygdala Pathways Associated with Heart Rate Variability

PubMed Central

Wei, Luqing; Chen, Hong; Wu, Guo-Rong

2018-01-01

The neurovisceral integration model has shown a key role of the amygdala in neural circuits underlying heart rate variability (HRV) modulation, and suggested that reciprocal connections from amygdala to brain regions centered on the central autonomic network (CAN) are associated with HRV. To provide neuroanatomical evidence for these theoretical perspectives, the current study used covariance analysis of MRI-based gray matter volume (GMV) to map structural covariance network of the amygdala, and then determined whether the interregional structural correlations related to individual differences in HRV. The results showed that covariance patterns of the amygdala encompassed large portions of cortical (e.g., prefrontal, cingulate, and insula) and subcortical (e.g., striatum, hippocampus, and midbrain) regions, lending evidence from structural covariance analysis to the notion that the amygdala was a pivotal node in neural pathways for HRV modulation. Importantly, participants with higher resting HRV showed increased covariance of amygdala to dorsal medial prefrontal cortex and anterior cingulate cortex (dmPFC/dACC) extending into adjacent medial motor regions [i.e., pre-supplementary motor area (pre-SMA)/SMA], demonstrating structural covariance of the prefrontal-amygdala pathways implicated in HRV, and also implying that resting HRV may reflect the function of neural circuits underlying cognitive regulation of emotion as well as facilitation of adaptive behaviors to emotion. Our results, thus, provide anatomical substrates for the neurovisceral integration model that resting HRV may index an integrative neural network which effectively organizes emotional, cognitive, physiological and behavioral responses in the service of goal-directed behavior and adaptability. PMID:29545744

Adaptive neuro fuzzy inference system-based power estimation method for CMOS VLSI circuits

NASA Astrophysics Data System (ADS)

Vellingiri, Govindaraj; Jayabalan, Ramesh

2018-03-01

Recent advancements in very large scale integration (VLSI) technologies have made it feasible to integrate millions of transistors on a single chip. This greatly increases the circuit complexity and hence there is a growing need for less-tedious and low-cost power estimation techniques. The proposed work employs Back-Propagation Neural Network (BPNN) and Adaptive Neuro Fuzzy Inference System (ANFIS), which are capable of estimating the power precisely for the complementary metal oxide semiconductor (CMOS) VLSI circuits, without requiring any knowledge on circuit structure and interconnections. The ANFIS to power estimation application is relatively new. Power estimation using ANFIS is carried out by creating initial FIS modes using hybrid optimisation and back-propagation (BP) techniques employing constant and linear methods. It is inferred that ANFIS with the hybrid optimisation technique employing the linear method produces better results in terms of testing error that varies from 0% to 0.86% when compared to BPNN as it takes the initial fuzzy model and tunes it by means of a hybrid technique combining gradient descent BP and mean least-squares optimisation algorithms. ANFIS is the best suited for power estimation application with a low RMSE of 0.0002075 and a high coefficient of determination (R) of 0.99961.

The Development of an IMU Integrated Clothes for Postural Monitoring Using Conductive Yarn and Interconnecting Technology.

PubMed

Kang, Sung-Won; Choi, Hyeob; Park, Hyung-Il; Choi, Byoung-Gun; Im, Hyobin; Shin, Dongjun; Jung, Young-Giu; Lee, Jun-Young; Park, Hong-Won; Park, Sukyung; Roh, Jung-Sim

2017-11-07

Spinal disease is a common yet important condition that occurs because of inappropriate posture. Prevention could be achieved by continuous posture monitoring, but most measurement systems cannot be used in daily life due to factors such as burdensome wires and large sensing modules. To improve upon these weaknesses, we developed comfortable "smart wear" for posture measurement using conductive yarn for circuit patterning and a flexible printed circuit board (FPCB) for interconnections. The conductive yarn was made by twisting polyester yarn and metal filaments, and the resistance per unit length was about 0.05 Ω/cm. An embroidered circuit was made using the conductive yarn, which showed increased yield strength and uniform electrical resistance per unit length. Circuit networks of sensors and FPCBs for interconnection were integrated into clothes using a computer numerical control (CNC) embroidery process. The system was calibrated and verified by comparing the values measured by the smart wear with those measured by a motion capture camera system. Six subjects performed fixed movements and free computer work, and, with this system, we were able to measure the anterior/posterior direction tilt angle with an error of less than 4°. The smart wear does not have excessive wires, and its structure will be optimized for better posture estimation in a later study.

Genetic programs constructed from layered logic gates in single cells

PubMed Central

Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.

2014-01-01

Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931

Development of analog watch with minute repeater

NASA Astrophysics Data System (ADS)

Okigami, Tomio; Aoyama, Shigeru; Osa, Takashi; Igarashi, Kiyotaka; Ikegami, Tomomi

A complementary metal oxide semiconductor with large scale integration was developed for an electronic minute repeater. It is equipped with the synthetic struck sound circuit to generate natural struck sound necessary for the minute repeater. This circuit consists of an envelope curve drawing circuit, frequency mixer, polyphonic mixer, and booster circuit made by using analog circuit technology. This large scale integration is a single chip microcomputer with motor drivers and input ports in addition to the synthetic struck sound circuit, and it is possible to make an electronic system of minute repeater at a very low cost in comparison with the conventional type.

Multidisciplinary System Reliability Analysis

NASA Technical Reports Server (NTRS)

Mahadevan, Sankaran; Han, Song; Chamis, Christos C. (Technical Monitor)

2001-01-01

The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code, developed under the leadership of NASA Glenn Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multidisciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.

Multi-Disciplinary System Reliability Analysis

NASA Technical Reports Server (NTRS)

Mahadevan, Sankaran; Han, Song

1997-01-01

The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code developed under the leadership of NASA Lewis Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multi-disciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

PubMed Central

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively. PMID:22294897

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Cobalt oxide nanosheet and CNT micro carbon monoxide sensor integrated with readout circuit on chip.

PubMed

Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

2010-01-01

The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

High-Tc superconductor coplanar waveguide filter

NASA Technical Reports Server (NTRS)

Chew, Wilbert; Bajuk, Louis J.; Cooley, Thomas W.; Foote, Marc C.; Hunt, Brian D.; Rascoe, Daniel L.; Riley, A. L.

1991-01-01

Coplanar waveguide (CPW) low-pass filters made of YBa2Cu3O(7-delta) (YBCO) on LaAlO3 substrates, with dimensions suited for integrated circuits, were fabricated and packaged. A complete filter gives a true idea of the advantages and difficulties in replacing thin-film metal with a high-temperature superconductor in a practical circuit. Measured insertion losses in liquid nitrogen were superior to the loss of a similar thin-film copper filter throughout the 0- to 9.5-GHz passband. These results demonstrate the performance of fully patterned YBCO in a practical CPW structure after sealing in a hermetic package.

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

PubMed Central

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

2017-01-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

PubMed

Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

2017-08-01

This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

Power system with an integrated lubrication circuit

DOEpatents

Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

2009-11-10

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

High-resolution non-destructive three-dimensional imaging of integrated circuits

NASA Astrophysics Data System (ADS)

Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H. R.; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

2017-03-01

Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

High-resolution non-destructive three-dimensional imaging of integrated circuits.

PubMed

Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H R; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

2017-03-15

Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography-a high-resolution coherent diffractive imaging technique-can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

Experimental characterization of a bi-dimensional array of negative capacitance piezo-patches for vibroacoustic control

NASA Astrophysics Data System (ADS)

Tateo, F.; Collet, M.; Ouisse, M.; Ichchou, M. N.; Cunefare, K. A.

2013-04-01

A recent technological revolution in the fields of integrated MEMS has finally rendered possible the mechanical integration of active smart materials, electronics and power supply systems for the next generation of smart composite structures. Using a bi-dimensional array of electromechanical transducers, composed by piezo-patches connected to a synthetic negative capacitance, it is possible to modify the dynamics of the underlying structure. In this study, we present an application of the Floquet-Bloch theorem for vibroacoustic power flow optimization, by means of distributed shunted piezoelectric material. In the context of periodically distributed damped 2D mechanical systems, this numerical approach allows one to compute the multi-modal waves dispersion curves into the entire first Brillouin zone. This approach also permits optimization of the piezoelectric shunting electrical impedance, which controls energy diffusion into the proposed semi-active distributed set of cells. Furthermore, we present experimental evidence that proves the effectiveness of the proposed control method. The experiment requires a rectangular metallic plate equipped with seventy-five piezo-patches, controlled independently by electronic circuits. More specifically, the out-of-plane displacements and the averaged kinetic energy of the controlled plate are compared in two different cases (open-circuit and controlled circuit). The resulting data clearly show how this proposed technique is able to damp and selectively reflect the incident waves.

Low-power integrated-circuit driver for ferrite-memory word lines

NASA Technical Reports Server (NTRS)

Katz, S.

1970-01-01

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

NASA Technical Reports Server (NTRS)

Seaward, R. C.

1967-01-01

Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-10-04

... Circuit Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... public record for this investigation may be viewed on the Commission's electronic docket (EDIS) at http... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

Multi-lead heat sink

DOEpatents

Roose, L.D.

1984-07-03

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again. 4 figs.

Multi-lead heat sink

DOEpatents

Roose, Lars D.

1984-01-01

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Multi-lead heat sink

DOEpatents

Roose, L.D.

1982-08-25

The disclosure relates to a heat sink used to protect integrated circuits from the heat resulting from soldering them to circuit boards. A tubular housing contains a slidable member which engages somewhat inwardly extending connecting rods, each of which is rotatably attached at one end to the bottom of the housing. The other end of each rod is fastened to an expandable coil spring loop. As the member is pushed downward in the housing, its bottom edge engages and forces outward the connecting rods, thereby expanding the spring so that it will fit over an integrated circuit. After the device is in place, the member is slid upward and the spring contracts about the leads of the integrated circuit. Soldering is now conducted and the spring absorbs excess heat therefrom to protect the integrated circuit. The placement steps are repeated in reverse order to remove the heat sink for use again.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

NASA Astrophysics Data System (ADS)

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-02-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design.

Intrinsic modulation of pulse-coupled integrate-and-fire neurons

NASA Astrophysics Data System (ADS)

Coombes, S.; Lord, G. J.

1997-11-01

Intrinsic neuromodulation is observed in sensory and neuromuscular circuits and in biological central pattern generators. We model a simple neuronal circuit with a system of two pulse-coupled integrate-and-fire neurons and explore the parameter regimes for periodic firing behavior. The inclusion of biologically realistic features shows that the speed and onset of neuronal response plays a crucial role in determining the firing phase for periodic rhythms. We explore the neurophysiological function of distributed delays arising from both the synaptic transmission process and dendritic structure as well as discrete delays associated with axonal communication delays. Bifurcation and stability diagrams are constructed with a mixture of simple analysis, numerical continuation and the Kuramoto phase-reduction technique. Moreover, we show that, for asynchronous behavior, the strength of electrical synapses can control the firing rate of the system.

The integrated design and archive of space-borne signal processing and compression coding

NASA Astrophysics Data System (ADS)

He, Qiang-min; Su, Hao-hang; Wu, Wen-bo

2017-10-01

With the increasing demand of users for the extraction of remote sensing image information, it is very urgent to significantly enhance the whole system's imaging quality and imaging ability by using the integrated design to achieve its compact structure, light quality and higher attitude maneuver ability. At this present stage, the remote sensing camera's video signal processing unit and image compression and coding unit are distributed in different devices. The volume, weight and consumption of these two units is relatively large, which unable to meet the requirements of the high mobility remote sensing camera. This paper according to the high mobility remote sensing camera's technical requirements, designs a kind of space-borne integrated signal processing and compression circuit by researching a variety of technologies, such as the high speed and high density analog-digital mixed PCB design, the embedded DSP technology and the image compression technology based on the special-purpose chips. This circuit lays a solid foundation for the research of the high mobility remote sensing camera.

Magnetic-free non-reciprocity based on staggered commutation

PubMed Central

Reiskarimian, Negar; Krishnaswamy, Harish

2016-01-01

Lorentz reciprocity is a fundamental characteristic of the vast majority of electronic and photonic structures. However, non-reciprocal components such as isolators, circulators and gyrators enable new applications ranging from radio frequencies to optical frequencies, including full-duplex wireless communication and on-chip all-optical information processing. Such components today dominantly rely on the phenomenon of Faraday rotation in magneto-optic materials. However, they are typically bulky, expensive and not suitable for insertion in a conventional integrated circuit. Here we demonstrate magnetic-free linear passive non-reciprocity based on the concept of staggered commutation. Commutation is a form of parametric modulation with very high modulation ratio. We observe that staggered commutation enables time-reversal symmetry breaking within very small dimensions (λ/1,250 × λ/1,250 in our device), resulting in a miniature radio-frequency circulator that exhibits reduced implementation complexity, very low loss, strong non-reciprocity, significantly enhanced linearity and real-time reconfigurability, and is integrated in a conventional complementary metal–oxide–semiconductor integrated circuit for the first time. PMID:27079524

DOE Office of Scientific and Technical Information (OSTI.GOV)

Oler, Kiri J.; Miller, Carl H.

In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

A Real Time Controller For Applications In Smart Structures

NASA Astrophysics Data System (ADS)

Ahrens, Christian P.; Claus, Richard O.

1990-02-01

Research in smart structures, especially the area of vibration suppression, has warranted the investigation of advanced computing environments. Real time PC computing power has limited development of high order control algorithms. This paper presents a simple Real Time Embedded Control System (RTECS) in an application of Intelligent Structure Monitoring by way of modal domain sensing for vibration control. It is compared to a PC AT based system for overall functionality and speed. The system employs a novel Reduced Instruction Set Computer (RISC) microcontroller capable of 15 million instructions per second (MIPS) continuous performance and burst rates of 40 MIPS. Advanced Complimentary Metal Oxide Semiconductor (CMOS) circuits are integrated on a single 100 mm by 160 mm printed circuit board requiring only 1 Watt of power. An operating system written in Forth provides high speed operation and short development cycles. The system allows for implementation of Input/Output (I/O) intensive algorithms and provides capability for advanced system development.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Betavoltaic effect in titanium dioxide nanotube arrays under build-in potential difference

NASA Astrophysics Data System (ADS)

Zhang, Qiang; Chen, Ranbin; San, Haisheng; Liu, Guohua; Wang, Kaiying

2015-05-01

We report the fabrication of sandwich-type metal/TiO2 nanotube (TNT) array/metal structures as well as their betavoltaic effects under build-in voltage through contact potential difference. The sandwiched structure is integrated by immobilized TNT arrays on Ti foil with radioisotope 63Ni planar source on Ni substrate (Ni-63Ni/TNT array/Ti). Under irradiation of the 63Ni source with activity of 8 mCi, the structure (TNT diameter ∼ 130 nm, length ∼ 11 μm) presents optimum energy conversion efficiency of 7.30% with open-circuit voltage of 1.54 V and short-circuit current of 12.43 nA. The TNT arrays exhibit a highly potential for developing betavoltaic batteries due to its wide band gap and nanotube array configuration. The TNT-betavoltaic concept offers a facile solution for micro/nano electronics with high efficiency and long life-time instead of conventional planar junction-type batteries.

Noise and linearity optimization methods for a 1.9GHz low noise amplifier.

PubMed

Guo, Wei; Huang, Da-Quan

2003-01-01

Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

NASA Technical Reports Server (NTRS)

Ponchak, George E.

2002-01-01

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

System-level integrated circuit (SLIC) development for phased array antenna applications

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Raquet, C. A.

1991-01-01

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

Free-world microelectronic manufacturing equipment

NASA Astrophysics Data System (ADS)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

Chemical sensors fabricated by a photonic integrated circuit foundry

NASA Astrophysics Data System (ADS)

Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

2018-02-01

We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

Hybrid stretchable circuits on silicone substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk; Liu, Q.

When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

An Electronics Course Emphasizing Circuit Design

ERIC Educational Resources Information Center

Bergeson, Haven E.

1975-01-01

Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

SFG synthesis of general high-order all-pass and all-pole current transfer functions using CFTAs.

PubMed

Tangsrirat, Worapong

2014-01-01

An approach of using the signal flow graph (SFG) technique to synthesize general high-order all-pass and all-pole current transfer functions with current follower transconductance amplifiers (CFTAs) and grounded capacitors has been presented. For general nth-order systems, the realized all-pass structure contains at most n + 1 CFTAs and n grounded capacitors, while the all-pole lowpass circuit requires only n CFTAs and n grounded capacitors. The resulting circuits obtained from the synthesis procedure are resistor-less structures and especially suitable for integration. They also exhibit low-input and high-output impedances and also convenient electronic controllability through the g m-value of the CFTA. Simulation results using real transistor model parameters ALA400 are also included to confirm the theory.

SFG Synthesis of General High-Order All-Pass and All-Pole Current Transfer Functions Using CFTAs

PubMed Central

Tangsrirat, Worapong

2014-01-01

An approach of using the signal flow graph (SFG) technique to synthesize general high-order all-pass and all-pole current transfer functions with current follower transconductance amplifiers (CFTAs) and grounded capacitors has been presented. For general nth-order systems, the realized all-pass structure contains at most n + 1 CFTAs and n grounded capacitors, while the all-pole lowpass circuit requires only n CFTAs and n grounded capacitors. The resulting circuits obtained from the synthesis procedure are resistor-less structures and especially suitable for integration. They also exhibit low-input and high-output impedances and also convenient electronic controllability through the g m-value of the CFTA. Simulation results using real transistor model parameters ALA400 are also included to confirm the theory. PMID:24688375

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

PubMed

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.

Arbitrary-Shaped Graphene-Based Planar Sandwich Supercapacitors on One Substrate with Enhanced Flexibility and Integration.

PubMed

Zheng, Shuanghao; Tang, Xingyan; Wu, Zhong-Shuai; Tan, Yuan-Zhi; Wang, Sen; Sun, Chenglin; Cheng, Hui-Ming; Bao, Xinhe

2017-02-28

The emerging smart power source-unitized electronics represent an utmost innovative paradigm requiring dramatic alteration from materials to device assembly and integration. However, traditional power sources with huge bottlenecks on the design and performance cannot keep pace with the revolutionized progress of shape-confirmable integrated circuits. Here, we demonstrate a versatile printable technology to fabricate arbitrary-shaped, printable graphene-based planar sandwich supercapacitors based on the layer-structured film of electrochemically exfoliated graphene as two electrodes and nanosized graphene oxide (lateral size of 100 nm) as a separator on one substrate. These monolithic planar supercapacitors not only possess arbitrary shapes, e.g., rectangle, hollow-square, "A" letter, "1" and "2" numbers, circle, and junction-wire shape, but also exhibit outstanding performance (∼280 F cm -3 ), excellent flexibility (no capacitance degradation under different bending states), and applicable scalability, which are far beyond those achieved by conventional technologies. More notably, such planar supercapacitors with superior integration can be readily interconnected in parallel and series, without use of metal interconnects and contacts, to modulate the output current and voltage of modular power sources for designable integrated circuits in various shapes and sizes.

Advanced Packaging for VLSI/VHSIC (Very Large Scale Integrated Circuits/Very High Speed Integrated Circuits) Applications: Electrical, Thermal, and Mechanical Considerations - An IR&D Report.

DTIC Science & Technology

1987-11-01

developed that can be used by circuit engineers to extract the maximum performance from the devices on various board technologies including multilayer ceramic...Design guidelines have been developed that can be used by circuit engineers to extract the maxi- mum performance from the devices on various board...25 Attenuation and Dispersion Effects ......................................... 27 Skin Effect

Integrated-Circuit Pseudorandom-Number Generator

NASA Technical Reports Server (NTRS)

Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

1992-01-01

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

Long life assurance study for manned spacecraft long life hardware. Volume 2: Long life assurance studies of EEE parts and packaging

NASA Technical Reports Server (NTRS)

1972-01-01

Guidelines for the design, development, and fabrication of electronic components and circuits for use in spacecraft construction are presented. The subjects discussed involve quality control procedures and test methodology for the following subjects: (1) monolithic integrated circuits, (2) hybrid integrated circuits, (3) transistors, (4) diodes, (5) tantalum capacitors, (6) electromechanical relays, (7) switches and circuit breakers, and (8) electronic packaging.

Asymmetric Memory Circuit Would Resist Soft Errors

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Perlman, Marvin

1990-01-01

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Radiation damage in MOS integrated circuits, Part 1

NASA Technical Reports Server (NTRS)

Danchenko, V.

1971-01-01

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Projecting light beams with 3D waveguide arrays

NASA Astrophysics Data System (ADS)

Crespi, Andrea; Bragheri, Francesca

2017-01-01

Free-space light beams with complex intensity patterns, or non-trivial phase structure, are demanded in diverse fields, ranging from classical and quantum optical communications, to manipulation and imaging of microparticles and cells. Static or dynamic spatial light modulators, acting on the phase or intensity of an incoming light wave, are the conventional choices to produce beams with such non-trivial characteristics. However, interfacing these devices with optical fibers or integrated optical circuits often requires difficult alignment or cumbersome optical setups. Here we explore theoretically and with numerical simulations the potentialities of directly using the output of engineered three-dimensional waveguide arrays, illuminated with linearly polarized light, to project light beams with peculiar structures. We investigate through a collection of illustrative configurations the far field distribution, showing the possibility to achieve orbital angular momentum, or to produce elaborate intensity or phase patterns with several singularity points. We also simulate the propagation of the projected beam, showing the possibility to concentrate light. We note that these devices should be at reach of current technology, thus perspectives are open for the generation of complex free-space optical beams from integrated waveguide circuits.

The multi-instrumentalist hippocampus. Comment on "The quartet theory of human emotions: An integrative and neurofunctional model" by S. Koelsch et al.

NASA Astrophysics Data System (ADS)

Strange, Bryan A.; Yebra, Mar

2015-06-01

Characterizing the neural circuitry of emotion is important not only from a basic science perspective, but also for understanding how these circuits may malfunction in psychiatric disease. A fundamental question for affective neuroscience is whether there are specialised neuroanatomical areas, or "modules", dedicated to the processing of emotional stimuli. In their review, Koelsch and colleagues [1] argue for the existence of a quartet of neuroanatomically distinct cerebral systems involved in the generation of a specific class of affects. Intriguingly, all four systems (brainstem-, diencephalon-, hippocampus-, and orbitofrontal-centred) comprise brain areas whose role in emotional processing is in addition to mediating other specific aspects of cognition. One member of the quartet in which this is particularly apparent is the hippocampus, a structure known to be critical for episodic memory and navigation. If areas involved in emotion also mediate other brain functions, this raises an issue of whether these multiple functions are executed by segregated circuits within each structure - i.e., a "module" for emotion residing in a sub-division of a brain structure - or whether these circuits are superimposed.

Integrated Electrode Arrays for Neuro-Prosthetic Implants

NASA Technical Reports Server (NTRS)

Brandon, Erik; Mojarradi, Mohammede

2003-01-01

Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.

Silicon Carbide Integrated Circuit Chip

NASA Image and Video Library

2015-02-17

A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

Controlling system for smart hyper-spectral imaging array based on liquid-crystal Fabry-Perot device

NASA Astrophysics Data System (ADS)

Jiang, Xue; Chen, Xin; Rong, Xin; Liu, Kan; Zhang, Xinyu; Ji, An; Xie, Changsheng

2011-11-01

A research for developing a kind of smart spectral imaging detection technique based on the electrically tunable liquidcrystal (LC) FP structure is launched. It has some advantages of low cost, highly compact integration, perfuming wavelength selection without moving any micro-mirror of FP device, and the higher reliability and stability. The controlling system for hyper-spectral imaging array based on LC-FP device includes mainly a MSP430F5438 as its core. Considering the characteristics of LC-FP device, the controlling system can provide a driving signal of 1-10 kHz and 0- 30Vrms for the device in a static driving mode. This paper introduces the hardware designing of the control system in detail. It presents an overall hardware solutions including: (1) the MSP430 controlling circuit, and (2) the operational amplifier circuit, and (3) the power supply circuit, and (4) the AD conversion circuit. The techniques for the realization of special high speed digital circuits, which is necessary for the PCB employed, is also discussed.

Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

PubMed

Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

2005-12-01

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

Testbed Experiment for SPIDER: A Photonic Integrated Circuit-based Interferometric imaging system

NASA Astrophysics Data System (ADS)

Badham, K.; Duncan, A.; Kendrick, R. L.; Wuchenich, D.; Ogden, C.; Chriqui, G.; Thurman, S. T.; Su, T.; Lai, W.; Chun, J.; Li, S.; Liu, G.; Yoo, S. J. B.

The Lockheed Martin Advanced Technology Center (LM ATC) and the University of California at Davis (UC Davis) are developing an electro-optical (EO) imaging sensor called SPIDER (Segmented Planar Imaging Detector for Electro-optical Reconnaissance) that seeks to provide a 10x to 100x size, weight, and power (SWaP) reduction alternative to the traditional bulky optical telescope and focal-plane detector array. The substantial reductions in SWaP would reduce cost and/or provide higher resolution by enabling a larger-aperture imager in a constrained volume. Our SPIDER imager replaces the traditional optical telescope and digital focal plane detector array with a densely packed interferometer array based on emerging photonic integrated circuit (PIC) technologies that samples the object being imaged in the Fourier domain (i.e., spatial frequency domain), and then reconstructs an image. Our approach replaces the large optics and structures required by a conventional telescope with PICs that are accommodated by standard lithographic fabrication techniques (e.g., complementary metal-oxide-semiconductor (CMOS) fabrication). The standard EO payload integration and test process that involves precision alignment and test of optical components to form a diffraction limited telescope is, therefore, replaced by in-process integration and test as part of the PIC fabrication, which substantially reduces associated schedule and cost. In this paper we describe the photonic integrated circuit design and the testbed used to create the first images of extended scenes. We summarize the image reconstruction steps and present the final images. We also describe our next generation PIC design for a larger (16x area, 4x field of view) image.

n-B-pi-p Superlattice Infrared Detector

NASA Technical Reports Server (NTRS)

Ting, David Z.; Bandara, Sumith V.; Hill, Cory J.; Gunapala, Sarath D.

2011-01-01

A specially designed barrier (B) is inserted at the n-pi junction [where most GR (generation-recombination) processes take place] in the standard n-pi-p structure to substantially reduce generation-recombination dark currents. The resulting n-Bpi- p structure also has reduced tunneling dark currents, thereby solving some of the limitations to which current type II strained layer superlattice infrared detectors are prone. This innovation is compatible with common read-out integrated circuits (ROICs).

Electronic Switch Arrays for Managing Microbattery Arrays

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Alahmad, Mahmoud; Sukumar, Vinesh; Zghoul, Fadi; Buck, Kevin; Hess, Herbert; Li, Harry; Cox, David

2008-01-01

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Inkjet printed circuits based on ambipolar and p-type carbon nanotube thin-film transistors

PubMed Central

Kim, Bongjun; Geier, Michael L.; Hersam, Mark C.; Dodabalapur, Ananth

2017-01-01

Ambipolar and p-type single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) are reliably integrated into various complementary-like circuits on the same substrate by inkjet printing. We describe the fabrication and characteristics of inverters, ring oscillators, and NAND gates based on complementary-like circuits fabricated with such TFTs as building blocks. We also show that complementary-like circuits have potential use as chemical sensors in ambient conditions since changes to the TFT characteristics of the p-channel TFTs in the circuit alter the overall operating characteristics of the circuit. The use of circuits rather than individual devices as sensors integrates sensing and signal processing functions, thereby simplifying overall system design. PMID:28145438

Multidisciplinary analysis and design of printed wiring boards

NASA Astrophysics Data System (ADS)

Fulton, Robert E.; Hughes, Joseph L.; Scott, Waymond R., Jr.; Umeagukwu, Charles; Yeh, Chao-Pin

1991-04-01

Modern printed wiring board design depends on electronic prototyping using computer-based simulation and design tools. Existing electrical computer-aided design (ECAD) tools emphasize circuit connectivity with only rudimentary analysis capabilities. This paper describes a prototype integrated PWB design environment denoted Thermal Structural Electromagnetic Testability (TSET) being developed at Georgia Tech in collaboration with companies in the electronics industry. TSET provides design guidance based on enhanced electrical and mechanical CAD capabilities including electromagnetic modeling testability analysis thermal management and solid mechanics analysis. TSET development is based on a strong analytical and theoretical science base and incorporates an integrated information framework and a common database design based on a systematic structured methodology.

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

PubMed

Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

2010-01-01

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e(-) for the simple integration CMS and 75 dB and 2.2 e(-) for the folding integration CMS, respectively, are obtained.

Computer aided design of monolithic microwave and millimeter wave integrated circuits and subsystems

NASA Astrophysics Data System (ADS)

Ku, Walter H.

1989-05-01

The objectives of this research are to develop analytical and computer aided design techniques for monolithic microwave and millimeter wave integrated circuits (MMIC and MIMIC) and subsystems and to design and fabricate those ICs. Emphasis was placed on heterojunction-based devices, especially the High Electron Mobility Transition (HEMT), for both low noise and medium power microwave and millimeter wave applications. Circuits to be considered include monolithic low noise amplifiers, power amplifiers, and distributed and feedback amplifiers. Interactive computer aided design programs were developed, which include large signal models of InP MISFETs and InGaAs HEMTs. Further, a new unconstrained optimization algorithm POSM was developed and implemented in the general Analysis and Design program for Integrated Circuit (ADIC) for assistance in the design of largesignal nonlinear circuits.

Development, Integration and Testing of Automated Triggering Circuit for Hybrid DC Circuit Breaker

NASA Astrophysics Data System (ADS)

Kanabar, Deven; Roy, Swati; Dodiya, Chiragkumar; Pradhan, Subrata

2017-04-01

A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed.

Hybrid integrated biological-solid-state system powered with adenosine triphosphate.

PubMed

Roseman, Jared M; Lin, Jianxun; Ramakrishnan, Siddharth; Rosenstein, Jacob K; Shepard, Kenneth L

2015-12-07

There is enormous potential in combining the capabilities of the biological and the solid state to create hybrid engineered systems. While there have been recent efforts to harness power from naturally occurring potentials in living systems in plants and animals to power complementary metal-oxide-semiconductor integrated circuits, here we report the first successful effort to isolate the energetics of an electrogenic ion pump in an engineered in vitro environment to power such an artificial system. An integrated circuit is powered by adenosine triphosphate through the action of Na(+)/K(+) adenosine triphosphatases in an integrated in vitro lipid bilayer membrane. The ion pumps (active in the membrane at numbers exceeding 2 × 10(6) mm(-2)) are able to sustain a short-circuit current of 32.6 pA mm(-2) and an open-circuit voltage of 78 mV, providing for a maximum power transfer of 1.27 pW mm(-2) from a single bilayer. Two series-stacked bilayers provide a voltage sufficient to operate an integrated circuit with a conversion efficiency of chemical to electrical energy of 14.9%.

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits.

PubMed

Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein

2011-08-26

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, A.D.; Haigh, R.E.; Hugenberg, K.F.

1995-09-26

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place. 7 figs.

Triggerable electro-optic amplitude modulator bias stabilizer for integrated optical devices

DOEpatents

Conder, Alan D.; Haigh, Ronald E.; Hugenberg, Keith F.

1995-01-01

An improved Mach-Zehnder integrated optical electro-optic modulator is achieved by application and incorporation of a DC bias box containing a laser synchronized trigger circuit, a DC ramp and hold circuit, a modulator transfer function negative peak detector circuit, and an adjustable delay circuit. The DC bias box ramps the DC bias along the transfer function curve to any desired phase or point of operation at which point the RF modulation takes place.

Cost optimization in low volume VLSI circuits

NASA Technical Reports Server (NTRS)

Cook, K. B., Jr.; Kerns, D. V., Jr.

1982-01-01

The relationship of integrated circuit (IC) cost to electronic system cost is developed using models for integrated circuit cost which are based on design/fabrication approach. Emphasis is on understanding the relationship between cost and volume for custom circuits suitable for NASA applications. In this report, reliability is a major consideration in the models developed. Results are given for several typical IC designs using off the shelf, full custom, and semicustom IC's with single and double level metallization.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, X.

1996-12-17

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window. 5 figs.

Gated integrator with signal baseline subtraction

DOEpatents

Wang, Xucheng

1996-01-01

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

PubMed

Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

2016-02-08

Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-08

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Silica Integrated Optical Circuits Based on Glass Photosensitivity

NASA Technical Reports Server (NTRS)

Abushagur, Mustafa A. G.

1999-01-01

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

Nanoscale integration is the next frontier for nanotechnology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Picraux, Samuel T

2009-01-01

Nanoscale integration of materials and structures is the next critical step to exploit the promise of nanomaterials. Many novel and fascinating properties have been revealed for nanostructured materials. But if nanotechnology is to live up to its promise we must incorporate these nanoscale building blocks into functional systems that connect to the micro- and macroscale world. To do this we will inevitably need to understand and exploit the resulting combined unique properties of these integrated nanosystems. Much science waits to be discovered in the process. Nanoscale integration extends from the synthesis and fabrication of individual nanoscale building blocks, to themore » assembly of these building blocks into composite structures, and finally to the formation of complex functional systems. As illustrated in Figure 1, the building blocks may be homogeneous or heterogeneous, the composite materials may be nanocomposite or patterned structures, and the functional systems will involve additional combinations of materials. Nanoscale integration involves assembling diverse nanoscale materials across length scales to design and achieve new properties and functionality. At each stage size-dependent properties, the influence of surfaces in close proximity, and a multitude of interfaces all come into play. Whether the final system involves coherent electrons in a quantum computing approach, the combined flow of phonons and electrons for a high efficiency thermoelectric micro-generator, or a molecular recognition structure for bio-sensing, the combined effects of size, surface, and interface will be critical. In essence, one wants to combine the novel functions available through nanoscale science to achieve unique multi-functionalities not available in bulk materials. Perhaps the best-known example of integration is that of combining electronic components together into very large scale integrated circuits (VLSI). The integrated circuit has revolutionized electronics in many ways, from exploiting field-effect transistor devices and low power complementary logic to enable the electronic watch and hand calculator in the 1970's, to today's microprocessors and memories with billions of devices and a computational power not imagined a few decades ago. The manipulation of charges on a chip, the new concepts in combining devices for logic functions, and the new approaches to computation, information processing, and imaging have all emerged from Kilby and Noyce's simple concept of integrating devices on a single chip. Moving from hard to soft materials, a second more recent example of integration is the DNA microarray. These microarrays, with up to millions of elements in a planar array that can be optically read out, can simultaneously measure the expression of 10's of thousands of genes to study the effects of disease and treatment, or screen for single nucleotide polymorphisms for uses ranging from forensics to predisposition to disease. While still at an early stage, microarrays have revolutionized biosciences by providing the means to interrogate the complex genetic control of biological functions. Just as integrated circuits and microarrays have led to completely new functionalities and performance, the integration of nanoscale materials and structures is anticipated to lead to new performance and enable the design of new functionalities not previously envisioned. The fundamental questions underlying integration go beyond just complex fabrication or the engineering of known solutions; they lead to new discoveries and new science. The scientific challenges around nanoscale integration necessitate the development of new knowledge that is central to the advance of nanotechnology. To move forward one must address key science questions that arise in nanoscience integration and go beyond a single system or materials area. New science and discoveries especially await around three questions. How does one: (1) Control energy transfer and other interactions across interfaces and over mUltiple length scales? (2) Understand and control the interactions between nanoscale building blocks to assemble specific integrated structures? (3) Design and exploit interactions within assembled structures to achieve new properties and specific functionalities? These high level questions can serve to drive research, and to advance understanding of the complex phenomena and multifunctionality that may emerge from integration. For example, in photonics there is considerable effort to understand and control the response of nanoscale conducting structures on dielectrics, to allow one to localize, manipulate, and control electromagnetic energy in integrated systems such as in the field known as metamaterials. Essential to this area is a fundamental understanding of energy transfer across multiple length scales (question 1 above).« less

Neuropeptide Signaling Networks and Brain Circuit Plasticity.

PubMed

McClard, Cynthia K; Arenkiel, Benjamin R

2018-01-01

The brain is a remarkable network of circuits dedicated to sensory integration, perception, and response. The computational power of the brain is estimated to dwarf that of most modern supercomputers, but perhaps its most fascinating capability is to structurally refine itself in response to experience. In the language of computers, the brain is loaded with programs that encode when and how to alter its own hardware. This programmed "plasticity" is a critical mechanism by which the brain shapes behavior to adapt to changing environments. The expansive array of molecular commands that help execute this programming is beginning to emerge. Notably, several neuropeptide transmitters, previously best characterized for their roles in hypothalamic endocrine regulation, have increasingly been recognized for mediating activity-dependent refinement of local brain circuits. Here, we discuss recent discoveries that reveal how local signaling by corticotropin-releasing hormone reshapes mouse olfactory bulb circuits in response to activity and further explore how other local neuropeptide networks may function toward similar ends.

Entropy Flow Through Near-Critical Quantum Junctions

NASA Astrophysics Data System (ADS)

Friedan, Daniel

2017-05-01

This is the continuation of Friedan (J Stat Phys, 2017. doi: 10.1007/s10955-017-1752-8). Elementary formulas are derived for the flow of entropy through a circuit junction in a near-critical quantum circuit close to equilibrium, based on the structure of the energy-momentum tensor at the junction. The entropic admittance of a near-critical junction in a bulk-critical circuit is expressed in terms of commutators of the chiral entropy currents. The entropic admittance at low frequency, divided by the frequency, gives the change of the junction entropy with temperature—the entropic "capacitance". As an example, and as a check on the formalism, the entropic admittance is calculated explicitly for junctions in bulk-critical quantum Ising circuits (free fermions, massless in the bulk), in terms of the reflection matrix of the junction. The half-bit of information capacity per end of critical Ising wire is re-derived by integrating the entropic "capacitance" with respect to temperature, from T=0 to T=∞.

Sleep Drive Is Encoded by Neural Plastic Changes in a Dedicated Circuit.

PubMed

Liu, Sha; Liu, Qili; Tabuchi, Masashi; Wu, Mark N

2016-06-02

Prolonged wakefulness leads to an increased pressure for sleep, but how this homeostatic drive is generated and subsequently persists is unclear. Here, from a neural circuit screen in Drosophila, we identify a subset of ellipsoid body (EB) neurons whose activation generates sleep drive. Patch-clamp analysis indicates these EB neurons are highly sensitive to sleep loss, switching from spiking to burst-firing modes. Functional imaging and translational profiling experiments reveal that elevated sleep need triggers reversible increases in cytosolic Ca(2+) levels, NMDA receptor expression, and structural markers of synaptic strength, suggesting these EB neurons undergo "sleep-need"-dependent plasticity. Strikingly, the synaptic plasticity of these EB neurons is both necessary and sufficient for generating sleep drive, indicating that sleep pressure is encoded by plastic changes within this circuit. These studies define an integrator circuit for sleep homeostasis and provide a mechanism explaining the generation and persistence of sleep drive. Copyright © 2016 Elsevier Inc. All rights reserved.

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

ERIC Educational Resources Information Center

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Exchange circuits for FASTBUS slaves

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bratskii, A.A.; Matseev, M.Y.; Rybakov, V.G.

1985-09-01

This paper describes general-purpose circuits for FASTBUS interfacing of the functional part of a slave device. The circuits contain buffered receivers and transmitters, addressrecognition and data-transfer logic, and the required control/status registers. The described circuits are implemented with series-K500 integrated circuits.

In situ fabricated 3D micro-lenses for photonic integrated circuits.

PubMed

Thomas, R; Li, J; Ladak, Sam; Barrow, D; Smowton, P M

2018-05-14

Aspheric astigmatic polymer micro-lenses were fabricated directly onto photonic integrated circuits using two-photon lithography. We observed a 12.6 dB improvement in the free space coupling efficiency between integrated ridge laser pairs with micro-lenses to those without.

Multipurpose instrumentation cable provides integral thermocouple circuit

NASA Technical Reports Server (NTRS)

Zellner, G.

1967-01-01

Multipurpose cable with an integral thermocouple circuit measures strain, vibration, pressure, throughout a wide temperature range. This cable reduces bulky and complex circuitry by eliminating separate thermocouples for each transducer.

Microstructures in striato-thalamo-orbitofrontal circuit in methamphetamine users.

PubMed

Li, Yadi; Dong, Haibo; Li, Feng; Wang, Gaoyan; Zhou, Wenhua; Yu, Rongbin; Zhang, Lingjun

2017-11-01

Background Striato-thalamo-orbitofrontal (STO) circuit plays a key role in the development of drug addiction. Few studies have investigated its microstructural abnormalities in methamphetamine (MA) users. Purpose To evaluate the microstructural changes and relevant clinical relevance of the STO circuit in MA users using diffusion tensor imaging (DTI). Material and Methods Twenty-eight MA users and 28 age-matched normal volunteers were enrolled. 3T magnetic resonance imaging (MRI) was employed to obtain structural T1-weighted (T1W) imaging and diffusion-tensor imaging (DTI) data. Freesurfer software was used for automated segmentation of the bilateral nucleus accumbens (NAc), thalami, and orbitofrontal cortex (OFC). Four DTI measures maps, fractional anisotropy (FA), mean diffusivity (MD), axial diffusion (AD), and radial diffusion (RD) were generated and non-linearly co-registered to structural space. Comparisons of DTI measures of the STO circuit were carried out between MA and controls using repeated measures analysis of variance. Correlation analyses were performed between STO circuit DTI measures and clinical characteristics. Results The MA group had significant FA reduction in the bilateral NAc, OFC, and right thalamus ( P < 0.05). Lower left OFC FA and right NAc FA/AD were associated with longer duration of MA use. Lower right OFC FA was associated with younger age at first MA use. Higher FA and lower MD/RD in the thalamus, as well as higher left OFC RD, were associated with increased psychiatric symptoms. Conclusion The STO circuit has reduced microstructural integrity in MA users. Microstructural changes in the thalamus may compensate for dysfunction in functionally connected cortices, which needs further investigation.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2006-12-12

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Multi-channel detector readout method and integrated circuit

DOEpatents

Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

2004-05-18

An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

Investigation for connecting waveguide in off-planar integrated circuits.

PubMed

Lin, Jie; Feng, Zhifang

2017-09-01

The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

Development of computer informational system of diagnostics integrated optical materials, elements, and devices

NASA Astrophysics Data System (ADS)

Volosovitch, Anatoly E.; Konopaltseva, Lyudmila I.

1995-11-01

Well-known methods of optical diagnostics, database for their storage, as well as expert system (ES) for their development are analyzed. A computer informational system is developed, which is based on a hybrid ES built on modern DBMS. As an example, the structural and constructive circuits of the hybrid integrated-optical devices based on laser diodes, diffusion waveguides, geodetic lenses, package-free linear photodiode arrays, etc. are presented. The features of methods and test results as well as the advanced directions of works related to the hybrid integrated-optical devices in the field of metrology are discussed.

Optical Isolator Utilizing Surface Plasmons

PubMed Central

Zayets, Vadym; Saito, Hidekazu; Ando, Koji; Yuasa, Shinji

2012-01-01

Feasibility of usage of surface plasmons in a new design of an integrated optical isolator has been studied. In the case of surface plasmons propagating at a boundary between a transition metal and a double-layer dielectric, there is a significant difference of optical loss for surface plasmons propagating in opposite directions. Utilizing this structure, it is feasible to fabricate a competitive plasmonic isolator, which benefits from a broad wavelength operational bandwidth and a good technological compatibility for integration into the Photonic Integrated Circuits (PIC). The linear dispersion relation was derived for plasmons propagating in a multilayer magneto-optical slab. PMID:28817012

Effects of /spl gamma/-rays on JFET devices and circuits fabricated in a detector-compatible Process

NASA Astrophysics Data System (ADS)

Betta, G. F. D.; Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.; Traversi, G.

2003-12-01

This work is concerned with the effects of /spl gamma/-rays on the static, signal and noise characteristics of JFET-based circuits belonging to a fabrication technology made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy. Such a process has been tuned with the aim of monolithically integrating the readout electronics on the same highly resistive substrate as multielectrode silicon detectors. The radiation tolerance of some test structures, including single devices and charge sensitive amplifiers, was studied in view of low-noise applications in industrial and medical imaging, X- and /spl gamma/-ray astronomy and high energy physics experiments. This paper intends to fill the gap in the study of gamma radiation effects on JFET devices and circuits belonging to detector-compatible technologies.

Estimation method of state-of-charge for lithium-ion battery used in hybrid electric vehicles based on variable structure extended kalman filter

NASA Astrophysics Data System (ADS)

Sun, Yong; Ma, Zilin; Tang, Gongyou; Chen, Zheng; Zhang, Nong

2016-07-01

Since the main power source of hybrid electric vehicle(HEV) is supplied by the power battery, the predicted performance of power battery, especially the state-of-charge(SOC) estimation has attracted great attention in the area of HEV. However, the value of SOC estimation could not be greatly precise so that the running performance of HEV is greatly affected. A variable structure extended kalman filter(VSEKF)-based estimation method, which could be used to analyze the SOC of lithium-ion battery in the fixed driving condition, is presented. First, the general lower-order battery equivalent circuit model(GLM), which includes column accumulation model, open circuit voltage model and the SOC output model, is established, and the off-line and online model parameters are calculated with hybrid pulse power characteristics(HPPC) test data. Next, a VSEKF estimation method of SOC, which integrates the ampere-hour(Ah) integration method and the extended Kalman filter(EKF) method, is executed with different adaptive weighting coefficients, which are determined according to the different values of open-circuit voltage obtained in the corresponding charging or discharging processes. According to the experimental analysis, the faster convergence speed and more accurate simulating results could be obtained using the VSEKF method in the running performance of HEV. The error rate of SOC estimation with the VSEKF method is focused in the range of 5% to 10% comparing with the range of 20% to 30% using the EKF method and the Ah integration method. In Summary, the accuracy of the SOC estimation in the lithium-ion battery cell and the pack of lithium-ion battery system, which is obtained utilizing the VSEKF method has been significantly improved comparing with the Ah integration method and the EKF method. The VSEKF method utilizing in the SOC estimation in the lithium-ion pack of HEV can be widely used in practical driving conditions.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Characteristics of High-Resolution Hemoglobin Measurement Microchip Integrated with Signal Processing Circuit

NASA Astrophysics Data System (ADS)

Noda, Toshihiko; Takao, Hidekuni; Ashiki, Mitsuaki; Ebi, Hiroyuki; Sawada, Kazuaki; Ishida, Makoto

2004-04-01

In this study, a microchip for measurement of hemoglobin in human blood has been proposed, fabricated and evaluated. The measurement principle of hemoglobin is based on the “cyanmethemoglobin method” that calculates the cyanmethemoglobin concentration by absorption photometry. A glass/silicon/silicon structure was used for the microchip. The middle silicon layer includes flow channels, and 45° mirrors formed at each end of the flow channels. Photodiodes and metal oxide semiconductor (MOS) integrated circuits were fabricated on the bottom silicon layer. The performance of the microchip for hemoglobin measurement was evaluated using a solution of red food color instead of a real blood sample. The fabricated microchip exhibited a similar performance to a nonminiaturized absorption cell which has the same optical path length. Signal processing output varied with solution concentration from 5.32 V to 5.55 V with very high stability due to differential signal processing.

Quantum electromechanics on silicon nitride nanomembranes

PubMed Central

Fink, J. M.; Kalaee, M.; Pitanti, A.; Norte, R.; Heinzle, L.; Davanço, M.; Srinivasan, K.; Painter, O.

2016-01-01

Radiation pressure has recently been used to effectively couple the quantum motion of mechanical elements to the fields of optical or microwave light. Integration of all three degrees of freedom—mechanical, optical and microwave—would enable a quantum interconnect between microwave and optical quantum systems. We present a platform based on silicon nitride nanomembranes for integrating superconducting microwave circuits with planar acoustic and optical devices such as phononic and photonic crystals. Using planar capacitors with vacuum gaps of 60 nm and spiral inductor coils of micron pitch we realize microwave resonant circuits with large electromechanical coupling to planar acoustic structures of nanoscale dimensions and femtoFarad motional capacitance. Using this enhanced coupling, we demonstrate microwave backaction cooling of the 4.48 MHz mechanical resonance of a nanobeam to an occupancy as low as 0.32. These results indicate the viability of silicon nitride nanomembranes as an all-in-one substrate for quantum electro-opto-mechanical experiments. PMID:27484751

The spatial structure of a nonlinear receptive field.

PubMed

Schwartz, Gregory W; Okawa, Haruhisa; Dunn, Felice A; Morgan, Josh L; Kerschensteiner, Daniel; Wong, Rachel O; Rieke, Fred

2012-11-01

Understanding a sensory system implies the ability to predict responses to a variety of inputs from a common model. In the retina, this includes predicting how the integration of signals across visual space shapes the outputs of retinal ganglion cells. Existing models of this process generalize poorly to predict responses to new stimuli. This failure arises in part from properties of the ganglion cell response that are not well captured by standard receptive-field mapping techniques: nonlinear spatial integration and fine-scale heterogeneities in spatial sampling. Here we characterize a ganglion cell's spatial receptive field using a mechanistic model based on measurements of the physiological properties and connectivity of only the primary excitatory circuitry of the retina. The resulting simplified circuit model successfully predicts ganglion-cell responses to a variety of spatial patterns and thus provides a direct correspondence between circuit connectivity and retinal output.

Infrared transparent graphene heater for silicon photonic integrated circuits.

PubMed

Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

2016-04-18

Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

PubMed

Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

2017-07-12

Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

Quantum electromechanics on silicon nitride nanomembranes.

PubMed

Fink, J M; Kalaee, M; Pitanti, A; Norte, R; Heinzle, L; Davanço, M; Srinivasan, K; Painter, O

2016-08-03

Radiation pressure has recently been used to effectively couple the quantum motion of mechanical elements to the fields of optical or microwave light. Integration of all three degrees of freedom-mechanical, optical and microwave-would enable a quantum interconnect between microwave and optical quantum systems. We present a platform based on silicon nitride nanomembranes for integrating superconducting microwave circuits with planar acoustic and optical devices such as phononic and photonic crystals. Using planar capacitors with vacuum gaps of 60 nm and spiral inductor coils of micron pitch we realize microwave resonant circuits with large electromechanical coupling to planar acoustic structures of nanoscale dimensions and femtoFarad motional capacitance. Using this enhanced coupling, we demonstrate microwave backaction cooling of the 4.48 MHz mechanical resonance of a nanobeam to an occupancy as low as 0.32. These results indicate the viability of silicon nitride nanomembranes as an all-in-one substrate for quantum electro-opto-mechanical experiments.

Fault tolerant system based on IDDQ testing

NASA Astrophysics Data System (ADS)

Guibane, Badi; Hamdi, Belgacem; Mtibaa, Abdellatif; Bensalem, Brahim

2018-06-01

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.

Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

PubMed

LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

2014-06-02

We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Kron-Branin modelling of ultra-short pulsed signal microelectrode

NASA Astrophysics Data System (ADS)

Xu, Zhifei; Ravelo, Blaise; Liu, Yang; Zhao, Lu; Delaroche, Fabien; Vurpillot, Francois

2018-06-01

An uncommon circuit modelling of microelectrode for ultra-short signal propagation is developed. The proposed model is based on the Tensorial Analysis of Network (TAN) using the Kron-Branin (KB) formalism. The systemic graph topology equivalent to the considered structure problem is established by assuming as unknown variables the branch currents. The TAN mathematical solution is determined after the KB characteristic matrix identification. The TAN can integrate various structure physical parameters. As proof of concept, via hole ended microelectrodes implemented on Kapton substrate were designed, fabricated and tested. The 0.1-MHz-to-6-GHz S-parameter KB model, simulation and measurement are in good agreement. In addition, time-domain analyses with nanosecond duration pulse signals were carried out to predict the microelectrode signal integrity. The modelled microstrip electrode is usually integrated in the atom probe tomography. The proposed unfamiliar KB method is particularly beneficial with respect to the computation speed and adaptability to various structures.

Function does not follow form in gene regulatory circuits.

PubMed

Payne, Joshua L; Wagner, Andreas

2015-08-20

Gene regulatory circuits are to the cell what arithmetic logic units are to the chip: fundamental components of information processing that map an input onto an output. Gene regulatory circuits come in many different forms, distinct structural configurations that determine who regulates whom. Studies that have focused on the gene expression patterns (functions) of circuits with a given structure (form) have examined just a few structures or gene expression patterns. Here, we use a computational model to exhaustively characterize the gene expression patterns of nearly 17 million three-gene circuits in order to systematically explore the relationship between circuit form and function. Three main conclusions emerge. First, function does not follow form. A circuit of any one structure can have between twelve and nearly thirty thousand distinct gene expression patterns. Second, and conversely, form does not follow function. Most gene expression patterns can be realized by more than one circuit structure. And third, multifunctionality severely constrains circuit form. The number of circuit structures able to drive multiple gene expression patterns decreases rapidly with the number of these patterns. These results indicate that it is generally not possible to infer circuit function from circuit form, or vice versa.

Pyruvate dehydrogenase complex and nicotinamide nucleotide transhydrogenase constitute an energy consuming redox circuit

PubMed Central

Fisher-Wellman, Kelsey H.; Lin, Chien-Te; Ryan, Terence E.; Reese, Lauren R.; Gilliam, Laura A. A.; Cathey, Brook L.; Lark, Daniel S.; Smith, Cody D.; Muoio, Deborah M.; Neufer, P. Darrell

2015-01-01

SUMMARY Cellular proteins rely on reversible redox reactions to establish and maintain biological structure and function. How redox catabolic (NAD+:NADH) and anabolic (NADP+:NADPH) processes integrate during metabolism to maintain cellular redox homeostasis however is unknown. The present work identifies a continuously cycling, mitochondrial membrane potential-dependent redox circuit between the pyruvate dehydrogenase complex (PDHC) and nicotinamide nucleotide transhydrogenase (NNT). PDHC is shown to produce H2O2 in relation to reducing pressure within the complex. The H2O2 produced however is effectively masked by a continuously cycling redox circuit that links, via glutathione/thioredoxin, to NNT, which catalyzes the regeneration of NADPH from NADH at the expense of the mitochondrial membrane potential. The net effect is an automatic fine tuning of NNT-mediated energy expenditure to metabolic balance at the level of PDHC. In mitochondria, genetic or pharmacological disruptions in the PDHC-NNT redox circuit negate counterbalance changes in energy expenditure. At the whole animal level, mice lacking functional NNT (C57BL/6J) are characterized by lower energy expenditure rates, consistent with their well known susceptibility to diet-induced obesity. These findings suggest the integration of redox sensing of metabolic balance with compensatory changes in energy expenditure provides a potential mechanism by which cellular redox homeostasis is maintained and body weight is defended during periods of positive and negative energy balance. PMID:25643703

The Development of an IMU Integrated Clothes for Postural Monitoring Using Conductive Yarn and Interconnecting Technology

PubMed Central

Kang, Sung-Won; Park, Hyung-Il; Choi, Byoung-Gun; Shin, Dongjun; Jung, Young-Giu; Lee, Jun-Young; Park, Hong-Won; Park, Sukyung

2017-01-01

Spinal disease is a common yet important condition that occurs because of inappropriate posture. Prevention could be achieved by continuous posture monitoring, but most measurement systems cannot be used in daily life due to factors such as burdensome wires and large sensing modules. To improve upon these weaknesses, we developed comfortable “smart wear” for posture measurement using conductive yarn for circuit patterning and a flexible printed circuit board (FPCB) for interconnections. The conductive yarn was made by twisting polyester yarn and metal filaments, and the resistance per unit length was about 0.05 Ω/cm. An embroidered circuit was made using the conductive yarn, which showed increased yield strength and uniform electrical resistance per unit length. Circuit networks of sensors and FPCBs for interconnection were integrated into clothes using a computer numerical control (CNC) embroidery process. The system was calibrated and verified by comparing the values measured by the smart wear with those measured by a motion capture camera system. Six subjects performed fixed movements and free computer work, and, with this system, we were able to measure the anterior/posterior direction tilt angle with an error of less than 4°. The smart wear does not have excessive wires, and its structure will be optimized for better posture estimation in a later study. PMID:29112125

Pyruvate dehydrogenase complex and nicotinamide nucleotide transhydrogenase constitute an energy-consuming redox circuit.

PubMed

Fisher-Wellman, Kelsey H; Lin, Chien-Te; Ryan, Terence E; Reese, Lauren R; Gilliam, Laura A A; Cathey, Brook L; Lark, Daniel S; Smith, Cody D; Muoio, Deborah M; Neufer, P Darrell

2015-04-15

Cellular proteins rely on reversible redox reactions to establish and maintain biological structure and function. How redox catabolic (NAD+/NADH) and anabolic (NADP+/NADPH) processes integrate during metabolism to maintain cellular redox homoeostasis, however, is unknown. The present work identifies a continuously cycling mitochondrial membrane potential (ΔΨm)-dependent redox circuit between the pyruvate dehydrogenase complex (PDHC) and nicotinamide nucleotide transhydrogenase (NNT). PDHC is shown to produce H2O2 in relation to reducing pressure within the complex. The H2O2 produced, however, is effectively masked by a continuously cycling redox circuit that links, via glutathione/thioredoxin, to NNT, which catalyses the regeneration of NADPH from NADH at the expense of ΔΨm. The net effect is an automatic fine-tuning of NNT-mediated energy expenditure to metabolic balance at the level of PDHC. In mitochondria, genetic or pharmacological disruptions in the PDHC-NNT redox circuit negate counterbalance changes in energy expenditure. At the whole animal level, mice lacking functional NNT (C57BL/6J) are characterized by lower energy-expenditure rates, consistent with their well-known susceptibility to diet-induced obesity. These findings suggest the integration of redox sensing of metabolic balance with compensatory changes in energy expenditure provides a potential mechanism by which cellular redox homoeostasis is maintained and body weight is defended during periods of positive and negative energy balance.

Front-end ASICs for high-energy astrophysics in space

NASA Astrophysics Data System (ADS)

Gevin, O.; Limousin, O.; Meuris, A.

2016-07-01

In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a major role in the noise performances of the detection systems. The geometry of a sensor is therefore critical and drives the ASIC design. The second part of the paper takes the geometry of the detector as a story line to explore different kinds of ASIC structures and architectures. From the simple single-channel ASIC for CCDs to the most advanced 3D ASIC prototypes used to build dead-zone free imaging systems, the paper reports on different families of circuits for spectro-imaging systems. It emphasizes a variety of designer choices, all around the word, in different space missions.

Roadmap evolution: from NTRS to ITRS, from ITRS 2.0 to IRDS

NASA Astrophysics Data System (ADS)

Gargini, Paolo A.

2017-10-01

The semiconductor industry benefitted from roadmap guidance since the mid-60s. The roadmap anticipated and outlined the main needs of the semiconductor industry for years to come and identified future challenges and possible solutions. Making transistor smaller by means of advanced lithographic technologies enabled both increased integration levels and improved IC performance. The roadmap methodology allowed the removal of multiple "red brick walls". The NTRS and the ITRS constituted primarily a "bottom up" approach as standard microprocessors and memories where introduced at a blistering pace barely allowing time for system houses to integrate them in their products. The 1998 ITRS provided the vision that triggered research, development and manufacturing communities to develop a completely new transistor structure in addition to replacing aluminum interconnects with a more advanced technology. The advent of Foundries and Fabless companies transformed the electronics industry into a "top down" driven industry in the past 15 years. The ITRS adjusted to this new ecosystem and morphed into the International Roadmap for Devices and Systems (IRDS) sponsored by IEEE. The IRDS is addressing the requirements and needs of the renewed electronics industry. Furthermore, by the middle of the next decade the ability to layout integrated circuits in a 2D geometry grid will reach fundamental physical limits and the aggressive conversion to 3D architecture for integrated circuit must be pursued across the board as an avenue to continuously increasing transistor count and improving performance. EUV technology is finally approaching the manufacturing stage but with the advent of 3D monolithically integrated heterogeneous circuits approaching in the not-toodistant future should the semiconductor industry concentrate its resources on the next lithographic technology generation in order to enhance resolution or on providing a smooth transition to the new revolutionary 3D architecture of integrated circuits? It is essential for the whole semiconductor industry to come together and make fundamental choices leading to a cooperative and synchronized allocation of adequate resources to produce viable solutions that once introduced in a timely manner into manufacturing will enable the continuation of the growth of the electronic industry at a pace comparable or exceeding historical trends.

Electrochemical planarization

DOEpatents

Bernhardt, A.F.; Contolini, R.J.

1993-10-26

In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer. 12 figures.

Applications of Computer Graphics in Engineering

NASA Technical Reports Server (NTRS)

1975-01-01

Various applications of interactive computer graphics to the following areas of science and engineering were described: design and analysis of structures, configuration geometry, animation, flutter analysis, design and manufacturing, aircraft design and integration, wind tunnel data analysis, architecture and construction, flight simulation, hydrodynamics, curve and surface fitting, gas turbine engine design, analysis, and manufacturing, packaging of printed circuit boards, spacecraft design.

A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

NASA Astrophysics Data System (ADS)

Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

2014-06-01

This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

Multislice imaging of integrated circuits by precession X-ray ptychography.

PubMed

Shimomura, Kei; Hirose, Makoto; Takahashi, Yukio

2018-01-01

A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wide Q range and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

PubMed

He, Li; Li, Mo

2014-05-01

The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

Smart Power: New power integrated circuit technologies and their applications

NASA Astrophysics Data System (ADS)

Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

1992-05-01

Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

The Management of Cognitive Load During Complex Cognitive Skill Acquisition by Means of Computer-Simulated Problem Solving

ERIC Educational Resources Information Center

Kester, Liesbeth; Kirschner, Paul A.; van Merrienboer, Jeroen J.G.

2005-01-01

This study compared the effects of two information presentation formats on learning to solve problems in electrical circuits. In one condition, the split-source format, information relating to procedural aspects of the functioning of an electrical circuit was not integrated in a circuit diagram, while information in the integrated format condition…

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

NASA Astrophysics Data System (ADS)

Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

2017-06-01

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

Time-lapse imaging reveals highly dynamic structural maturation of postnatally born dentate granule cells in organotypic entorhino-hippocampal slice cultures

PubMed Central

Radic, Tijana; Jungenitz, Tassilo; Singer, Mathias; Beining, Marcel; Cuntz, Hermann; Vlachos, Andreas; Deller, Thomas; Schwarzacher, Stephan W.

2017-01-01

Neurogenesis of hippocampal granule cells (GCs) persists throughout mammalian life and is important for learning and memory. How newborn GCs differentiate and mature into an existing circuit during this time period is not yet fully understood. We established a method to visualize postnatally generated GCs in organotypic entorhino-hippocampal slice cultures (OTCs) using retroviral (RV) GFP-labeling and performed time-lapse imaging to study their morphological development in vitro. Using anterograde tracing we could, furthermore, demonstrate that the postnatally generated GCs in OTCs, similar to adult born GCs, grow into an existing entorhino-dentate circuitry. RV-labeled GCs were identified and individual cells were followed for up to four weeks post injection. Postnatally born GCs exhibited highly dynamic structural changes, including dendritic growth spurts but also retraction of dendrites and phases of dendritic stabilization. In contrast, older, presumably prenatally born GCs labeled with an adeno-associated virus (AAV), were far less dynamic. We propose that the high degree of structural flexibility seen in our preparations is necessary for the integration of newborn granule cells into an already existing neuronal circuit of the dentate gyrus in which they have to compete for entorhinal input with cells generated and integrated earlier. PMID:28256620

GaAs VLSI technology and circuit elements for DSP

NASA Astrophysics Data System (ADS)

Mikkelson, James M.

1990-10-01

Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs

Cascade photonic integrated circuit architecture for electro-optic in-phase quadrature/single sideband modulation or frequency conversion.

PubMed

Hasan, Mehedi; Hall, Trevor

2015-11-01

A photonic integrated circuit architecture for implementing frequency upconversion is proposed. The circuit consists of a 1×2 splitter and 2×1 combiner interconnected by two stages of differentially driven phase modulators having 2×2 multimode interference coupler between the stages. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. The intrinsic conversion efficiency of the proposed design is improved by 6 dB over the alternative functionally equivalent circuit based on dual parallel Mach-Zehnder modulators known in the prior art. A two-tone analysis is presented to study the linearity of the proposed circuit, and a comparison is provided over the alternative. The proposed circuit is suitable for integration in any platform that offers linear electro-optic phase modulation such as LiNbO(3), silicon, III-V, or hybrid technology.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

PubMed Central

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Dual-function photonic integrated circuit for frequency octo-tupling or single-side-band modulation.

PubMed

Hasan, Mehedi; Maldonado-Basilio, Ramón; Hall, Trevor J

2015-06-01

A dual-function photonic integrated circuit for microwave photonic applications is proposed. The circuit consists of four linear electro-optic phase modulators connected optically in parallel within a generalized Mach-Zehnder interferometer architecture. The photonic circuit is arranged to have two separate output ports. A first port provides frequency up-conversion of a microwave signal from the electrical to the optical domain; equivalently single-side-band modulation. A second port provides tunable millimeter wave carriers by frequency octo-tupling of an appropriate amplitude RF carrier. The circuit exploits the intrinsic relative phases between the ports of multi-mode interference couplers to provide substantially all the static optical phases needed. The operation of the proposed dual-function photonic integrated circuit is verified by computer simulations. The performance of the frequency octo-tupling and up-conversion functions is analyzed in terms of the electrical signal to harmonic distortion ratio and the optical single side band to unwanted harmonics ratio, respectively.

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, David M.

1996-01-01

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit.

Compensated gain control circuit for buck regulator command charge circuit

DOEpatents

Barrett, D.M.

1996-11-05

A buck regulator command charge circuit includes a compensated-gain control signal for compensating for changes in the component values in order to achieve optimal voltage regulation. The compensated-gain control circuit includes an automatic-gain control circuit for generating a variable-gain control signal. The automatic-gain control circuit is formed of a precision rectifier circuit, a filter network, an error amplifier, and an integrator circuit. 5 figs.

Controllability of structural brain networks

NASA Astrophysics Data System (ADS)

Gu, Shi; Pasqualetti, Fabio; Cieslak, Matthew; Telesford, Qawi K.; Yu, Alfred B.; Kahn, Ari E.; Medaglia, John D.; Vettel, Jean M.; Miller, Michael B.; Grafton, Scott T.; Bassett, Danielle S.

2015-10-01

Cognitive function is driven by dynamic interactions between large-scale neural circuits or networks, enabling behaviour. However, fundamental principles constraining these dynamic network processes have remained elusive. Here we use tools from control and network theories to offer a mechanistic explanation for how the brain moves between cognitive states drawn from the network organization of white matter microstructure. Our results suggest that densely connected areas, particularly in the default mode system, facilitate the movement of the brain to many easily reachable states. Weakly connected areas, particularly in cognitive control systems, facilitate the movement of the brain to difficult-to-reach states. Areas located on the boundary between network communities, particularly in attentional control systems, facilitate the integration or segregation of diverse cognitive systems. Our results suggest that structural network differences between cognitive circuits dictate their distinct roles in controlling trajectories of brain network function.

An integrated circuit switch

NASA Technical Reports Server (NTRS)

Bonin, E. L.

1969-01-01

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

Chemical etching for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1981-01-01

Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

Multiple network interface core apparatus and method

DOEpatents

Underwood, Keith D [Albuquerque, NM; Hemmert, Karl Scott [Albuquerque, NM

2011-04-26

A network interface controller and network interface control method comprising providing a single integrated circuit as a network interface controller and employing a plurality of network interface cores on the single integrated circuit.

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

NASA Astrophysics Data System (ADS)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

Functional Laser Trimming Of Thin Film Resistors On Silicon ICs

NASA Astrophysics Data System (ADS)

Mueller, Michael J.; Mickanin, Wes

1986-07-01

Modern Laser Wafer Trimming (LWT) technology achieves exceptional analog circuit performance and precision while maintain-ing the advantages of high production throughput and yield. Microprocessor-driven instrumentation has both emphasized the role of data conversion circuits and demanded sophisticated signal conditioning functions. Advanced analog semiconductor circuits with bandwidths over 1 GHz, and high precision, trimmable, thin-film resistors meet many of todays emerging circuit requirements. Critical to meeting these requirements are optimum choices of laser characteristics, proper materials, trimming process control, accurate modeling of trimmed resistor performance, and appropriate circuit design. Once limited exclusively to hand-crafted, custom integrated circuits, designs are now available in semi-custom circuit configurations. These are similar to those provided for digital designs and supported by computer-aided design (CAD) tools. Integrated with fully automated measurement and trimming systems, these quality circuits can now be produced in quantity to meet the requirements of communications, instrumentation, and signal processing markets.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Hybrid Integration of Solid-State Quantum Emitters on a Silicon Photonic Chip.

PubMed

Kim, Je-Hyung; Aghaeimeibodi, Shahriar; Richardson, Christopher J K; Leavitt, Richard P; Englund, Dirk; Waks, Edo

2017-12-13

Scalable quantum photonic systems require efficient single photon sources coupled to integrated photonic devices. Solid-state quantum emitters can generate single photons with high efficiency, while silicon photonic circuits can manipulate them in an integrated device structure. Combining these two material platforms could, therefore, significantly increase the complexity of integrated quantum photonic devices. Here, we demonstrate hybrid integration of solid-state quantum emitters to a silicon photonic device. We develop a pick-and-place technique that can position epitaxially grown InAs/InP quantum dots emitting at telecom wavelengths on a silicon photonic chip deterministically with nanoscale precision. We employ an adiabatic tapering approach to transfer the emission from the quantum dots to the waveguide with high efficiency. We also incorporate an on-chip silicon-photonic beamsplitter to perform a Hanbury-Brown and Twiss measurement. Our approach could enable integration of precharacterized III-V quantum photonic devices into large-scale photonic structures to enable complex devices composed of many emitters and photons.

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

PubMed

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Computationally Efficient Modeling and Simulation of Large Scale Systems

NASA Technical Reports Server (NTRS)

Jain, Jitesh (Inventor); Koh, Cheng-Kok (Inventor); Balakrishnan, Vankataramanan (Inventor); Cauley, Stephen F (Inventor); Li, Hong (Inventor)

2014-01-01

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

NASA Technical Reports Server (NTRS)

Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

1981-01-01

Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

Flexible integration of free-standing nanowires into silicon photonics.

PubMed

Chen, Bigeng; Wu, Hao; Xin, Chenguang; Dai, Daoxin; Tong, Limin

2017-06-14

Silicon photonics has been developed successfully with a top-down fabrication technique to enable large-scale photonic integrated circuits with high reproducibility, but is limited intrinsically by the material capability for active or nonlinear applications. On the other hand, free-standing nanowires synthesized via a bottom-up growth present great material diversity and structural uniformity, but precisely assembling free-standing nanowires for on-demand photonic functionality remains a great challenge. Here we report hybrid integration of free-standing nanowires into silicon photonics with high flexibility by coupling free-standing nanowires onto target silicon waveguides that are simultaneously used for precise positioning. Coupling efficiency between a free-standing nanowire and a silicon waveguide is up to ~97% in the telecommunication band. A hybrid nonlinear-free-standing nanowires-silicon waveguides Mach-Zehnder interferometer and a racetrack resonator for significantly enhanced optical modulation are experimentally demonstrated, as well as hybrid active-free-standing nanowires-silicon waveguides circuits for light generation. These results suggest an alternative approach to flexible multifunctional on-chip nanophotonic devices.Precisely assembling free-standing nanowires for on-demand photonic functionality remains a challenge. Here, Chen et al. integrate free-standing nanowires into silicon waveguides and show all-optical modulation and light generation on silicon photonic chips.

When more is less: Feedback effects in perceptual category learning ☆

PubMed Central

Maddox, W. Todd; Love, Bradley C.; Glass, Brian D.; Filoteo, J. Vincent

2008-01-01

Rule-based and information-integration category learning were compared under minimal and full feedback conditions. Rule-based category structures are those for which the optimal rule is verbalizable. Information-integration category structures are those for which the optimal rule is not verbalizable. With minimal feedback subjects are told whether their response was correct or incorrect, but are not informed of the correct category assignment. With full feedback subjects are informed of the correctness of their response and are also informed of the correct category assignment. An examination of the distinct neural circuits that subserve rule-based and information-integration category learning leads to the counterintuitive prediction that full feedback should facilitate rule-based learning but should also hinder information-integration learning. This prediction was supported in the experiment reported below. The implications of these results for theories of learning are discussed. PMID:18455155

PUZZLE - A program for computer-aided design of printed circuit artwork

NASA Technical Reports Server (NTRS)

Harrell, D. A. W.; Zane, R.

1971-01-01

Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.

Open-loop digital frequency multiplier

NASA Technical Reports Server (NTRS)

Moore, R. C.

1977-01-01

Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.

Integrated circuit cooled turbine blade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.

A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channelmore » connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.« less

Magnetophoretic circuits for digital control of single particles and cells

NASA Astrophysics Data System (ADS)

Lim, Byeonghwa; Reddy, Venu; Hu, Xinghao; Kim, Kunwoo; Jadhav, Mital; Abedini-Nassab, Roozbeh; Noh, Young-Woock; Lim, Yong Taik; Yellen, Benjamin B.; Kim, Cheolgi

2014-05-01

The ability to manipulate small fluid droplets, colloidal particles and single cells with the precision and parallelization of modern-day computer hardware has profound applications for biochemical detection, gene sequencing, chemical synthesis and highly parallel analysis of single cells. Drawing inspiration from general circuit theory and magnetic bubble technology, here we demonstrate a class of integrated circuits for executing sequential and parallel, timed operations on an ensemble of single particles and cells. The integrated circuits are constructed from lithographically defined, overlaid patterns of magnetic film and current lines. The magnetic patterns passively control particles similar to electrical conductors, diodes and capacitors. The current lines actively switch particles between different tracks similar to gated electrical transistors. When combined into arrays and driven by a rotating magnetic field clock, these integrated circuits have general multiplexing properties and enable the precise control of magnetizable objects.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

PubMed

Shulaker, Max Marcel; Van Rethy, Jelle; Wu, Tony F; Liyanage, Luckshitha Suriyasena; Wei, Hai; Li, Zuanyi; Pop, Eric; Gielen, Georges; Wong, H-S Philip; Mitra, Subhasish

2014-04-22

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

System and method for interfacing large-area electronics with integrated circuit devices

DOEpatents

Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

2016-07-12

A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lashin, A. V., E-mail: LashinAV@lhp.ru; Kozyrev, A. V.

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.;

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

PubMed

Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

2016-10-12

Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS 2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS 2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Waveguide design, modeling, and optimization: from photonic nanodevices to integrated photonic circuits

NASA Astrophysics Data System (ADS)

Bordovsky, Michal; Catrysse, Peter; Dods, Steven; Freitas, Marcio; Klein, Jackson; Kotacka, Libor; Tzolov, Velko; Uzunov, Ivan M.; Zhang, Jiazong

2004-05-01

We present the state of the art for commercial design and simulation software in the 'front end' of photonic circuit design. One recent advance is to extend the flexibility of the software by using more than one numerical technique on the same optical circuit. There are a number of popular and proven techniques for analysis of photonic devices. Examples of these techniques include the Beam Propagation Method (BPM), the Coupled Mode Theory (CMT), and the Finite Difference Time Domain (FDTD) method. For larger photonic circuits, it may not be practical to analyze the whole circuit by any one of these methods alone, but often some smaller part of the circuit lends itself to at least one of these standard techniques. Later the whole problem can be analyzed on a unified platform. This kind of approach can enable analysis for cases that would otherwise be cumbersome, or even impossible. We demonstrate solutions for more complex structures ranging from the sub-component layout, through the entire device characterization, to the mask layout and its editing. We also present recent advances in the above well established techniques. This includes the analysis of nano-particles, metals, and non-linear materials by FDTD, photonic crystal design and analysis, and improved models for high concentration Er/Yb co-doped glass waveguide amplifiers.

Computer Simulation of Microwave Devices

NASA Technical Reports Server (NTRS)

Kory, Carol L.

1997-01-01

The accurate simulation of cold-test results including dispersion, on-axis beam interaction impedance, and attenuation of a helix traveling-wave tube (TWT) slow-wave circuit using the three-dimensional code MAFIA (Maxwell's Equations Solved by the Finite Integration Algorithm) was demonstrated for the first time. Obtaining these results is a critical step in the design of TWT's. A well-established procedure to acquire these parameters is to actually build and test a model or a scale model of the circuit. However, this procedure is time-consuming and expensive, and it limits freedom to examine new variations to the basic circuit. These limitations make the need for computational methods crucial since they can lower costs, reduce tube development time, and lessen limitations on novel designs. Computer simulation has been used to accurately obtain cold-test parameters for several slow-wave circuits. Although the helix slow-wave circuit remains the mainstay of the TWT industry because of its exceptionally wide bandwidth, until recently it has been impossible to accurately analyze a helical TWT using its exact dimensions because of the complexity of its geometrical structure. A new computer modeling technique developed at the NASA Lewis Research Center overcomes these difficulties. The MAFIA three-dimensional mesh for a C-band helix slow-wave circuit is shown.

Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

PubMed

Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

2016-06-22

We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals.

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

NASA Technical Reports Server (NTRS)

Taylor, B.

1990-01-01

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

A three-dimensional integrated nanogenerator for effectively harvesting sound energy from the environment.

PubMed

Liu, Jinmei; Cui, Nuanyang; Gu, Long; Chen, Xiaobo; Bai, Suo; Zheng, Youbin; Hu, Caixia; Qin, Yong

2016-03-07

An integrated triboelectric nanogenerator (ITNG) with a three-dimensional structure benefiting sound propagation and adsorption is demonstrated to more effectively harvest sound energy with improved output performance. With different multifunctional integrated layers working harmonically, it could generate a short-circuit current up to 2.1 mA, an open-circuit voltage up to 232 V and the maximum charging rate can reach 453 μC s(-1) for a 1 mF capacitor, which are 4.6 times, 2.6 times and 7.4 times the highest reported values, respectively. Further study shows that the ITNG works well under sound in a wide range of sound intensity levels (SILs) and frequencies, and its output is sensitive to the SIL and frequency of the sound, which reveals that the ITNG can act as a self-powered active sensor for real-time noise surveillance and health care. Moreover, this generator can be used to directly power the Fe(OH)3 sol electrophoresis and shows great potential as a wireless power supply in the electrochemical industry.

Maturation of Cortico-Subcortical Structural Networks-Segregation and Overlap of Medial Temporal and Fronto-Striatal Systems in Development.

PubMed

Walhovd, Kristine B; Tamnes, Christian K; Bjørnerud, Atle; Due-Tønnessen, Paulina; Holland, Dominic; Dale, Anders M; Fjell, Anders M

2015-07-01

The brain consists of partly segregated neural circuits within which structural convergence and functional integration occurs during development. The relationship of structural cortical and subcortical maturation is largely unknown. We aimed to study volumetric development of the hippocampus and basal ganglia (caudate, putamen, pallidum, accumbens) in relation to volume changes throughout the cortex. Longitudinal MRI data were obtained across a mean interval of 2.6 years in 85 participants with an age range of 8-19 years at study start. Left and right subcortical changes were related to cortical change vertex-wise in the ipsilateral hemisphere with general linear models with age, sex, interval between scans, and mean cortical volume change as covariates. Hippocampal-cortical change relationships centered on parts of the Papez circuit, including entorhinal, parahippocampal, and isthmus cingulate areas, and lateral temporal, insular, and orbitofrontal cortices in the left hemisphere. Basal ganglia-cortical change relationships were observed in mostly nonoverlapping and more anterior cortical areas, all including the anterior cingulate. Other patterns were unique to specific basal ganglia structures, including pre-, post-, and paracentral patterns relating to putamen change. In conclusion, patterns of cortico-subcortical development as assessed by morphometric analyses in part map out segregated neural circuits at the macrostructural level. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

Monolithic optical integrated control circuitry for GaAs MMIC-based phased arrays

NASA Technical Reports Server (NTRS)

Bhasin, K. B.; Ponchak, G. E.; Kascak, T. J.

1985-01-01

Gallium arsenide (GaAs) monolithic microwave integrated circuits (MMIC's) show promise in phased-array antenna applications for future space communications systems. Their efficient usage will depend on the control of amplitude and phase signals for each MMIC element in the phased array and in the low-loss radiofrequency feed. For a phased array contining several MMIC elements a complex system is required to control and feed each element. The characteristics of GaAs MMIC's for 20/30-GHz phased-array systems are discussed. The optical/MMIC interface and the desired characteristics of optical integrated circuits (OIC's) for such an interface are described. Anticipated fabrication considerations for eventual full monolithic integration of optical integrated circuits with MMIC's on a GaAs substrate are presented.

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

NASA Astrophysics Data System (ADS)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Mixed Signal Learning by Spike Correlation Propagation in Feedback Inhibitory Circuits

PubMed Central

Hiratani, Naoki; Fukai, Tomoki

2015-01-01

The brain can learn and detect mixed input signals masked by various types of noise, and spike-timing-dependent plasticity (STDP) is the candidate synaptic level mechanism. Because sensory inputs typically have spike correlation, and local circuits have dense feedback connections, input spikes cause the propagation of spike correlation in lateral circuits; however, it is largely unknown how this secondary correlation generated by lateral circuits influences learning processes through STDP, or whether it is beneficial to achieve efficient spike-based learning from uncertain stimuli. To explore the answers to these questions, we construct models of feedforward networks with lateral inhibitory circuits and study how propagated correlation influences STDP learning, and what kind of learning algorithm such circuits achieve. We derive analytical conditions at which neurons detect minor signals with STDP, and show that depending on the origin of the noise, different correlation timescales are useful for learning. In particular, we show that non-precise spike correlation is beneficial for learning in the presence of cross-talk noise. We also show that by considering excitatory and inhibitory STDP at lateral connections, the circuit can acquire a lateral structure optimal for signal detection. In addition, we demonstrate that the model performs blind source separation in a manner similar to the sequential sampling approximation of the Bayesian independent component analysis algorithm. Our results provide a basic understanding of STDP learning in feedback circuits by integrating analyses from both dynamical systems and information theory. PMID:25910189

An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

ERIC Educational Resources Information Center

Muyskens, Mark A.

1997-01-01

Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

Magnet-wire wrapping tool for integrated circuits

NASA Technical Reports Server (NTRS)

Takahashi, T. H.

1972-01-01

Wire-dispensing tool which resembles mechanical pencil is used to wrap magnet wire around integrated circuit terminals uniformly and securely without damaging insulative coating on wire. Tool is hand-held and easily manipulated to execute wire wrapping movements.

A zirconium dioxide ammonia microsensor integrated with a readout circuit manufactured using the 0.18 μm CMOS process.

PubMed

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-03-15

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Dendritic nonlinearities are tuned for efficient spike-based computations in cortical circuits.

PubMed

Ujfalussy, Balázs B; Makara, Judit K; Branco, Tiago; Lengyel, Máté

2015-12-24

Cortical neurons integrate thousands of synaptic inputs in their dendrites in highly nonlinear ways. It is unknown how these dendritic nonlinearities in individual cells contribute to computations at the level of neural circuits. Here, we show that dendritic nonlinearities are critical for the efficient integration of synaptic inputs in circuits performing analog computations with spiking neurons. We developed a theory that formalizes how a neuron's dendritic nonlinearity that is optimal for integrating synaptic inputs depends on the statistics of its presynaptic activity patterns. Based on their in vivo preynaptic population statistics (firing rates, membrane potential fluctuations, and correlations due to ensemble dynamics), our theory accurately predicted the responses of two different types of cortical pyramidal cells to patterned stimulation by two-photon glutamate uncaging. These results reveal a new computational principle underlying dendritic integration in cortical neurons by suggesting a functional link between cellular and systems--level properties of cortical circuits.

A real-time spectrum acquisition system design based on quantum dots-quantum well detector

NASA Astrophysics Data System (ADS)

Zhang, S. H.; Guo, F. M.

2016-01-01

In this paper, we studied the structure characteristics of quantum dots-quantum well photodetector with response wavelength range from 400 nm to 1000 nm. It has the characteristics of high sensitivity, low dark current and the high conductance gain. According to the properties of the quantum dots-quantum well photodetectors, we designed a new type of capacitive transimpedence amplifier (CTIA) readout circuit structure with the advantages of adjustable gain, wide bandwidth and high driving ability. We have implemented the chip packaging between CTIA-CDS structure readout circuit and quantum dots detector and tested the readout response characteristics. According to the timing signals requirements of our readout circuit, we designed a real-time spectral data acquisition system based on FPGA and ARM. Parallel processing mode of programmable devices makes the system has high sensitivity and high transmission rate. In addition, we realized blind pixel compensation and smoothing filter algorithm processing to the real time spectrum data by using C++. Through the fluorescence spectrum measurement of carbon quantum dots and the signal acquisition system and computer software system to realize the collection of the spectrum signal processing and analysis, we verified the excellent characteristics of detector. It meets the design requirements of quantum dot spectrum acquisition system with the characteristics of short integration time, real-time and portability.

Maternal buffering beyond glucocorticoids: impact of early life stress on corticolimbic circuits that control infant responses to novelty

PubMed Central

Howell, Brittany R.; McMurray, Matthew S.; Guzman, Dora B.; Nair, Govind; Shi, Yundi; McCormack, Kai M.; Hu, Xiaoping; Styner, Martin A.; Sanchez, Mar M.

2017-01-01

Maternal presence has a potent buffering effect on infant fear and stress responses in primates. We previously reported that maternal presence is not effective in buffering the endocrine stress response in infant rhesus monkeys reared by maltreating mothers. We have also reported that maltreating mothers show low maternal responsiveness and permissiveness/secure-base behavior. Although still not understood, it is possible that this maternal buffering effect is mediated, at least partially, through deactivation of amygdala response circuits when mothers are present. Here we studied rhesus monkey infants that differed in the quality of early maternal care to investigate how this early experience modulated maternal buffering effects on behavioral responses to novelty during the weaning period. We also examined the relationship between these behavioral responses and structural connectivity in one of the underlying regulatory neural circuits: amygdala-prefrontal pathways. Our findings suggest that infant exploration in a novel situation is predicted by maternal responsiveness and structural integrity of amygdala-prefrontal white matter depending on maternal presence (positive relationships when mother is absent). These results provide evidence that maternal buffering of infant behavioral inhibition is dependent on the quality of maternal care and structural connectivity of neural pathways that are sensitive to early life stress. PMID:27295326

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beammore » Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF{sub 2}) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF{sub 2} detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented.« less

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

NASA Astrophysics Data System (ADS)

Dickson, T. O.; Lacroix, M.-A.; Boret, S.; Gloria, D.; Beerkens, R.; Voinigescu, S. P.

2005-01-01

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S21 of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 μm × 30 μm) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.

Activity-Induced Remodeling of Olfactory Bulb Microcircuits Revealed by Monosynaptic Tracing

PubMed Central

Arenkiel, Benjamin R.; Hasegawa, Hiroshi; Yi, Jason J.; Larsen, Rylan S.; Wallace, Michael L.; Philpot, Benjamin D.; Wang, Fan; Ehlers, Michael D.

2011-01-01

The continued addition of new neurons to mature olfactory circuits represents a remarkable mode of cellular and structural brain plasticity. However, the anatomical configuration of newly established circuits, the types and numbers of neurons that form new synaptic connections, and the effect of sensory experience on synaptic connectivity in the olfactory bulb remain poorly understood. Using in vivo electroporation and monosynaptic tracing, we show that postnatal-born granule cells form synaptic connections with centrifugal inputs and mitral/tufted cells in the mouse olfactory bulb. In addition, newly born granule cells receive extensive input from local inhibitory short axon cells, a poorly understood cell population. The connectivity of short axon cells shows clustered organization, and their synaptic input onto newborn granule cells dramatically and selectively expands with odor stimulation. Our findings suggest that sensory experience promotes the synaptic integration of new neurons into cell type-specific olfactory circuits. PMID:22216277

Emergence of binocular functional properties in a monocular neural circuit

PubMed Central

Ramdya, Pavan; Engert, Florian

2010-01-01

Sensory circuits frequently integrate converging inputs while maintaining precise functional relationships between them. For example, in mammals with stereopsis, neurons at the first stages of binocular visual processing show a close alignment of receptive-field properties for each eye. Still, basic questions about the global wiring mechanisms that enable this functional alignment remain unanswered, including whether the addition of a second retinal input to an otherwise monocular neural circuit is sufficient for the emergence of these binocular properties. We addressed this question by inducing a de novo binocular retinal projection to the larval zebrafish optic tectum and examining recipient neuronal populations using in vivo two-photon calcium imaging. Notably, neurons in rewired tecta were predominantly binocular and showed matching direction selectivity for each eye. We found that a model based on local inhibitory circuitry that computes direction selectivity using the topographic structure of both retinal inputs can account for the emergence of this binocular feature. PMID:19160507

Reduction of radiation loss at small-radius bend using spoof surface plasmon polariton transmission line

NASA Astrophysics Data System (ADS)

Tang, Wen Xuan; Zhang, Hao Chi; Liu, Jun Feng; Xu, Jie; Cui, Tie Jun

2017-01-01

Spoof surface plasmon polariton (SPP) has been realized at low frequencies through corrugated metallic structures. As two-dimensional application, the ultrathin SPP transmission lines (TLs) have been proposed with great potentials for microwave compact circuits due to the strong field confinement and enhancement, as well as controllable dispersive properties. In this paper, we examine the radiation loss at small-radius bend, which may cause severe crosstalk in highly-integrated circuits or systems, for the SPP TLs. We theoretically analyze that the SPP TL has essential merit of low radiation loss, and show better performance of SPP TL than the conventional microstrip line through numerical simulations and experiments. Both simulated and measured results demonstrate that the new type of transmission line can efficiently suppress the radiation loss at small-radius bend, and hence reduce the crosstalk in circuits and systems.

Flagellar region 3b supports strong expression of integrated DNA and the highest chromosomal integration efficiency of the Escherichia coli flagellar regions.

PubMed

Juhas, Mario; Ajioka, James W

2015-07-01

The Gram-negative bacterium Escherichia coli is routinely used as the chassis for a variety of biotechnology and synthetic biology applications. Identification and analysis of reliable chromosomal integration and expression target loci is crucial for E. coli engineering. Chromosomal loci differ significantly in their ability to support integration and expression of the integrated genetic circuits. In this study, we investigate E. coli K12 MG1655 flagellar regions 2 and 3b. Integration of the genetic circuit into seven and nine highly conserved genes of the flagellar regions 2 (motA, motB, flhD, flhE, cheW, cheY and cheZ) and 3b (fliE, F, G, J, K, L, M, P, R), respectively, showed significant variation in their ability to support chromosomal integration and expression of the integrated genetic circuit. While not reducing the growth of the engineered strains, the integrations into all 16 target sites led to the loss of motility. In addition to high expression, the flagellar region 3b supports the highest efficiency of integration of all E. coli K12 MG1655 flagellar regions and is therefore potentially the most suitable for the integration of synthetic genetic circuits. © 2015 The Authors. Microbial Biotechnology published by John Wiley & Sons Ltd and Society for Applied Microbiology.

Characterization of Novel Thin-Films and Structures for Integrated Circuit and Photovoltaic Applications

NASA Astrophysics Data System (ADS)

Zhao, Zhao

Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer is employed. The electrical and structural characterization of hole transfer layers (HTLs) in OSCs reveals MoO3 is the compatible HTL for TAgT anode. In the end, the reactive ink printed Ag film for solar cell contact application is studied by characterizing its electromigration lifetime. A percolative model is proposed and validated for predicting the resistivity and lifetime of printed Ag thin films containing porous structure.

RF Energy Interaction With Electro-Optic Materials (Single Investigator Award Proposed to Address Research Topic Area 6.4. Electromagnetics and RF Circuit Integration)

DTIC Science & Technology

2015-12-27

demonstration vehicles. Test and measurement of fabricated structures will be conducted to experimentally quantify RF and optical performance. Measurement...the development of coupled RF and optical structures. Both the graduate student and the undergraduate student were trained in conducting precision...research conducted for this project. The journal paper citations are: 1. L. Chen, J. Nagy, and R. M. Reano, "Patterned ion-sliced lithium niobate for

Radiation and Temperature Hard Multi-Pixel Avalanche Photodiodes

NASA Technical Reports Server (NTRS)

Bensaoula, Abdelhak (Inventor); Starikov, David (Inventor); Pillai, Rajeev (Inventor)

2017-01-01

The structure and method of fabricating a radiation and temperature hard avalanche photodiode with integrated radiation and temperature hard readout circuit, comprising a substrate, an avalanche region, an absorption region, and a plurality of Ohmic contacts are presented. The present disclosure provides for tuning of spectral sensitivity and high device efficiency, resulting in photon counting capability with decreased crosstalk and reduced dark current.

Comparison between two photovoltaic module models based on transistors

NASA Astrophysics Data System (ADS)

Saint-Eve, Frédéric; Sawicki, Jean-Paul; Petit, Pierre; Maufay, Fabrice; Aillerie, Michel

2018-05-01

The main objective of this paper is to verify the possibility to reduce to a simple electronic circuit with very few components the behavior simulation of an un-shaded photovoltaic (PV) module. Particularly, two models based on well-tried elementary structures, i.e., the Darlington structure in first model and the voltage regulation with programmable Zener diode in the second are analyzed. Specifications extracted from the behavior of a real I-V characteristic of a panel are considered and the principal electrical variables are deduced. The two models are expected to match with open circuit voltage, maximum power point (MPP) and short circuit current, without forgetting realistic current slopes on the both sides of MPP. The robustness is mentioned when irradiance varies and is considered as an additional fundamental property. For both models, two simulations are done to identify influence of some parameters. In the first model, a parameter allowing to adjust current slope on left side of MPP proves to be also important for the calculation of open circuit voltage. Besides this model does not authorize an entirely adjustment of I-V characteristic and MPP moves significantly away from real value when irradiance increases. On the contrary, the second model seems to have only qualities: open circuit voltage is easy to calculate, current slopes are realistic and there is perhaps a good robustness when irradiance variations are simulated by adjusting short circuit current of PV module. We have shown that these two simplified models are expected to make reliable and easier simulations of complex PV architecture integrating many different devices like PV modules or other renewable energy sources and storage capacities coupled in parallel association.

Vacuum Microelectronic Field Emission Array Devices for Microwave Amplification.

NASA Astrophysics Data System (ADS)

Mancusi, Joseph Edward

This dissertation presents the design, analysis, and measurement of vacuum microelectronic devices which use field emission to extract an electron current from arrays of silicon cones. The arrays of regularly-spaced silicon cones, the field emission cathodes or emitters, are fabricated with an integrated gate electrode which controls the electric field at the tip of the cone, and thus the electron current. An anode or collector electrode is placed above the array to collect the emission current. These arrays, which are fabricated in a standard silicon processing facility, are developed for use as high power microwave amplifiers. Field emission has been studied extensively since it was first characterized in 1928, however due to the large electric fields required practical field emission devices are difficult to make. With the development of the semiconductor industry came the development of fabrication equipment and techniques which allow for the manufacture of the precision micron-scale structures necessary for practical field emission devices. The active region of a field emission device is a vacuum, therefore the electron travel is ballistic. This analysis of field emission devices includes electric field and electron emission modeling, development of a device equivalent circuit, analysis of the parameters in the equivalent circuit, and device testing. Variations in device structure are taken into account using a statistical model based upon device measurements. Measurements of silicon field emitter arrays at DC and RF are presented and analyzed. In this dissertation, the equivalent circuit is developed from the analysis of the device structure. The circuit parameters are calculated from geometrical considerations and material properties, or are determined from device measurements. It is necessary to include the emitter resistance in the equivalent circuit model since relatively high resistivity silicon wafers are used. As is demonstrated, the circuit model accurately predicts the magnitude of the emission current at a number of typical bias current levels when the device is operating at frequencies within the range of 10 MHz to 1 GHz. At low frequencies and at high frequencies within this range, certain parameters are negligible, and simplifications may be made in the equivalent circuit model.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Waveshaping electronic circuit

NASA Technical Reports Server (NTRS)

Harper, T. P.

1971-01-01

Circuit provides output signal with sinusoidal function in response to bipolar transition of input signal. Instantaneous transition shapes into linear rate of change and linear rate of change shapes into sinusoidal rate of change. Circuit contains only active components; therefore, compatibility with integrated circuit techniques is assured.

Monolithic 3D CMOS Using Layered Semiconductors.

PubMed

Sachid, Angada B; Tosun, Mahmut; Desai, Sujay B; Hsu, Ching-Yi; Lien, Der-Hsien; Madhvapathy, Surabhi R; Chen, Yu-Ze; Hettick, Mark; Kang, Jeong Seuk; Zeng, Yuping; He, Jr-Hau; Chang, Edward Yi; Chueh, Yu-Lun; Javey, Ali; Hu, Chenming

2016-04-06

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study of Piezoelectric Vibration Energy Harvester with non-linear conditioning circuit using an integrated model

NASA Astrophysics Data System (ADS)

Manzoor, Ali; Rafique, Sajid; Usman Iftikhar, Muhammad; Mahmood Ul Hassan, Khalid; Nasir, Ali

2017-08-01

Piezoelectric vibration energy harvester (PVEH) consists of a cantilever bimorph with piezoelectric layers pasted on its top and bottom, which can harvest power from vibrations and feed to low power wireless sensor nodes through some power conditioning circuit. In this paper, a non-linear conditioning circuit, consisting of a full-bridge rectifier followed by a buck-boost converter, is employed to investigate the issues of electrical side of the energy harvesting system. An integrated mathematical model of complete electromechanical system has been developed. Previously, researchers have studied PVEH with sophisticated piezo-beam models but employed simplistic linear circuits, such as resistor, as electrical load. In contrast, other researchers have worked on more complex non-linear circuits but with over-simplified piezo-beam models. Such models neglect different aspects of the system which result from complex interactions of its electrical and mechanical subsystems. In this work, authors have integrated the distributed parameter-based model of piezo-beam presented in literature with a real world non-linear electrical load. Then, the developed integrated model is employed to analyse the stability of complete energy harvesting system. This work provides a more realistic and useful electromechanical model having realistic non-linear electrical load unlike the simplistic linear circuit elements employed by many researchers.

Interface For MIL-STD-1553B Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Osborn, Stephen H.; Sullender, Craig C.

1993-01-01

Electronic control-logic subsystem acts as interface between microcontroller and MIL-STD-1553B data bus. Subsystem made of relatively small number of integrated circuits. Advantages include low power, few integrated-circuit chips, and little need for control signals.

Package Holds Five Monolithic Microwave Integrated Circuits

NASA Technical Reports Server (NTRS)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

NASA Astrophysics Data System (ADS)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

Robust Hybrid Finite Element Methods for Antennas and Microwave Circuits

NASA Technical Reports Server (NTRS)

Gong, J.; Volakis, John L.

1996-01-01

One of the primary goals in this dissertation is concerned with the development of robust hybrid finite element-boundary integral (FE-BI) techniques for modeling and design of conformal antennas of arbitrary shape. Both the finite element and integral equation methods will be first overviewed in this chapter with an emphasis on recently developed hybrid FE-BI methodologies for antennas, microwave and millimeter wave applications. The structure of the dissertation is then outlined. We conclude the chapter with discussions of certain fundamental concepts and methods in electromagnetics, which are important to this study.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Packaging Of Control Circuits In A Robot Arm

NASA Technical Reports Server (NTRS)

Kast, William

1994-01-01

Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

NASA Technical Reports Server (NTRS)

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Nonlinear system analysis in bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T. F.; Whalen, J. J.

1980-01-01

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

Capacitive charge generation apparatus and method for testing circuits

DOEpatents

Cole, E.I. Jr.; Peterson, K.A.; Barton, D.L.

1998-07-14

An electron beam apparatus and method for testing a circuit are disclosed. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 {micro}m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits. 7 figs.

Capacitive charge generation apparatus and method for testing circuits

DOEpatents

Cole, Jr., Edward I.; Peterson, Kenneth A.; Barton, Daniel L.

1998-01-01

An electron beam apparatus and method for testing a circuit. The electron beam apparatus comprises an electron beam incident on an outer surface of an insulating layer overlying one or more electrical conductors of the circuit for generating a time varying or alternating current electrical potential on the surface; and a measurement unit connected to the circuit for measuring an electrical signal capacitively coupled to the electrical conductors to identify and map a conduction state of each of the electrical conductors, with or without an electrical bias signal being applied to the circuit. The electron beam apparatus can further include a secondary electron detector for forming a secondary electron image for registration with a map of the conduction state of the electrical conductors. The apparatus and method are useful for failure analysis or qualification testing to determine the presence of any open-circuits or short-circuits, and to verify the continuity or integrity of electrical conductors buried below an insulating layer thickness of 1-100 .mu.m or more without damaging or breaking down the insulating layer. The types of electrical circuits that can be tested include integrated circuits, multi-chip modules, printed circuit boards and flexible printed circuits.

High stability amplifier

NASA Technical Reports Server (NTRS)

Adams, W. A.; Reinhardt, V. S. (Inventor)

1983-01-01

An electrical RF signal amplifier for providing high temperature stability and RF isolation and comprised of an integrated circuit voltage regulator, a single transistor, and an integrated circuit operational amplifier mounted on a circuit board such that passive circuit elements are located on side of the circuit board while the active circuit elements are located on the other side is described. The active circuit elements are embedded in a common heat sink so that a common temperature reference is provided for changes in ambient temperature. The single transistor and operational amplifier are connected together to form a feedback amplifier powered from the voltage regulator with transistor implementing primarily the desired signal gain while the operational amplifier implements signal isolation. Further RF isolation is provided by the voltage regulator which inhibits cross-talk from other like amplifiers powered from a common power supply. Input and output terminals consisting of coaxial connectors are located on the sides of a housing in which all the circuit components and heat sink are located.

Two integrator loop quadrature oscillators: A review.

PubMed

Soliman, Ahmed M

2013-01-01

A review of the two integrator loop oscillator circuits providing two quadrature sinusoidal output voltages is given. All the circuits considered employ the minimum number of capacitors namely two except one circuit which uses three capacitors. The circuits considered are classified to four different classes. The first class includes floating capacitors and floating resistors and the active building blocks realizing these circuits are the Op Amp or the OTRA. The second class employs grounded capacitors and includes floating resistors and the active building blocks realizing these circuits are the DCVC or the unity gain cells or the CFOA. The third class employs grounded capacitors and grounded resistors and the active building blocks realizing these circuits are the CCII. The fourth class employs grounded capacitors and no resistors and the active building blocks realizing these circuits are the TA. Transformation methods showing the generation of different classes from each other is given in details and this is one of the main objectives of this paper.

Hybrid UV Imager Containing Face-Up AlGaN/GaN Photodiodes

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata

2005-01-01

A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.

On-chip continuous-variable quantum entanglement

NASA Astrophysics Data System (ADS)

Masada, Genta; Furusawa, Akira

2016-09-01

Entanglement is an essential feature of quantum theory and the core of the majority of quantum information science and technologies. Quantum computing is one of the most important fruits of quantum entanglement and requires not only a bipartite entangled state but also more complicated multipartite entanglement. In previous experimental works to demonstrate various entanglement-based quantum information processing, light has been extensively used. Experiments utilizing such a complicated state need highly complex optical circuits to propagate optical beams and a high level of spatial interference between different light beams to generate quantum entanglement or to efficiently perform balanced homodyne measurement. Current experiments have been performed in conventional free-space optics with large numbers of optical components and a relatively large-sized optical setup. Therefore, they are limited in stability and scalability. Integrated photonics offer new tools and additional capabilities for manipulating light in quantum information technology. Owing to integrated waveguide circuits, it is possible to stabilize and miniaturize complex optical circuits and achieve high interference of light beams. The integrated circuits have been firstly developed for discrete-variable systems and then applied to continuous-variable systems. In this article, we review the currently developed scheme for generation and verification of continuous-variable quantum entanglement such as Einstein-Podolsky-Rosen beams using a photonic chip where waveguide circuits are integrated. This includes balanced homodyne measurement of a squeezed state of light. As a simple example, we also review an experiment for generating discrete-variable quantum entanglement using integrated waveguide circuits.

Method for Evaluating the Corrosion Resistance of Aluminum Metallization of Integrated Circuits under Multifactorial Influence

NASA Astrophysics Data System (ADS)

Kolomiets, V. I.

2018-03-01

The influence of complex influence of climatic factors (temperature, humidity) and electric mode (supply voltage) on the corrosion resistance of metallization of integrated circuits has been considered. The regression dependence of the average time of trouble-free operation t on the mentioned factors has been established in the form of a modified Arrhenius equation that is adequate in a wide range of factor values and is suitable for selecting accelerated test modes. A technique for evaluating the corrosion resistance of aluminum metallization of depressurized CMOS integrated circuits has been proposed.

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

DOEpatents

Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

1995-01-01

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

DOEpatents

Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

1995-11-07

A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

A SPICE2 Model for the M732 Analog Timer Integrated Circuit.

DTIC Science & Technology

1982-06-01

I AD-All? 019 ARMY ARMAMENT RESEARCH AND DEVELOPMENT C01MAND DOVER-ETC F/ S 1/ I A SPICES MODEL FOR THE M739 ANALOG TIMER INTEGRATED CIRCUIT. (U) I...JUN $I .J P TOBAK UNCLASSIFIED AR ID-20Di S I-AD-E06 3 NL ADI- A SPICE2 MODEL FOR THE M3 ANALOG TIMR INTERNATED CIRCIT, JOHN P. TOMA DTIC JUNE 1992 13...ARrIID-TR-82001 -;AZ/ 4 " 4. TITLE (and Subtitle) S . TYPE OF REPORT & PERIOD COVERED A SPICE2 MODEL FOR THE M732 ANALOG TIMER Final INTEGRATED CIRCUIT

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

PubMed

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

PubMed

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Radome Positioner for the RFSS (Radio Frequency Simulation System).

DTIC Science & Technology

1978-02-27

its associated circuits contained on the Motorola M68MM01A-I micro- module (See Drawing 64). This board contains the 6800 microprocessor. Ik bytes of...D 00 1~ 0 41 + C.) ) -44 208 g. Small encoder diameter achieved by using integrated circuit modules . h. Stainless steel case. U...to the 30 integrated circuits which actually comprise the heart of the-microcomputer. This dramatic reduction in parts count re- sults in a similar

Modelling of double air-bridged structured inductor implemented by a GaAs integrated passive device manufacturing process

NASA Astrophysics Data System (ADS)

Li, Yang; Yao, Zhao; Zhang, Chun-Wei; Fu, Xiao-Qian; Li, Zhi-Ming; Li, Nian-Qiang; Wang, Cong

2017-05-01

In order to provide excellent performance and show the development of a complicated structure in a module and system, this paper presents a double air-bridge-structured symmetrical differential inductor based on integrated passive device technology. Corresponding to the proposed complicated structure, a new manufacturing process fabricated on a high-resistivity GaAs substrate is described in detail. Frequency-independent physical models are presented with lump elements and the results of skin effect-based measurements. Finally, some key features of the inductor are compared; good agreement between the measurements and modeled circuit fully verifies the validity of the proposed modeling approach. Meanwhile, we also present a comparison of different coil turns for inductor performance. The proposed work can provide a good solution for the design, fabrication, modeling, and practical application of radio-frequency modules and systems.

Integrated Circuits in the Introductory Electronics Laboratory

ERIC Educational Resources Information Center

English, Thomas C.; Lind, David A.

1973-01-01

Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

Chemical vapor deposition for automatic processing of integrated circuits

NASA Technical Reports Server (NTRS)

Kennedy, B. W.

1980-01-01

Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-06

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-648] Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing Same; Notice of Commission Decision To Dismiss the Investigation as Moot AGENCY: U.S. International Trade Commission. ACTION: Notice. SUMMARY...

Optoelectronic Integrated Circuits For Neural Networks

NASA Technical Reports Server (NTRS)

Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

1990-01-01

Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

A Program in Semiconductor Processing.

ERIC Educational Resources Information Center

McConica, Carol M.

1984-01-01

A graduate program at Colorado State University which focuses on integrated circuit processing is described. The program utilizes courses from several departments while allowing students to apply chemical engineering techniques to an integrated circuit fabrication research topic. Information on employment of chemical engineers by electronics…

AIN-Based Packaging for SiC High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Savrun, Ender

2004-01-01

Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

PubMed

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Readout circuit with novel background suppression for long wavelength infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Xie, L.; Xia, X. J.; Zhou, Y. F.; Wen, Y.; Sun, W. F.; Shi, L. X.

2011-02-01

In this article, a novel pixel readout circuit using a switched-capacitor integrator mode background suppression technique is presented for long wavelength infrared focal plane arrays. This circuit can improve dynamic range and signal-to-noise ratio by suppressing the large background current during integration. Compared with other background suppression techniques, the new background suppression technique is less sensitive to the process mismatch and has no additional shot noise. The proposed circuit is theoretically analysed and simulated while taking into account the non-ideal characteristics. The result shows that the background suppression non-uniformity is ultra-low even for a large process mismatch. The background suppression non-uniformity of the proposed circuit can also remain very small with technology scaling.

V-band integrated quadriphase modulator

NASA Technical Reports Server (NTRS)

Grote, A.; Chang, K.

1983-01-01

A V-band integrated circuit quadriphase shift keyed modulator/exciter for space communications systems was developed. Intersatellite communications systems require direct modulation at 60 GHz to enhance signal processing capability. For most systems, particularly space applications, small and lightweight components are essential to alleviate severe system design constraints. Thus to achieve wideband, high data rate systems, direct modulation techniques at millimeter waves using solid state integrated circuit technology are an integral part of the overall technology developments.

Industrial Electronics II for ICT. Student's Manual.

ERIC Educational Resources Information Center

Snider, Bob

This student manual contains the following six units for classroom and laboratory experiences in high school industrial electronics: (1) introduction and review of DC and AC circuits; (2) semiconductors; (3) integrated circuits; (4) digital basics; (5) complex digital circuits; and (6) computer circuits. The units include unit objectives, specific…