Science.gov

Sample records for integrated electronic circuits

  1. ELECTRONIC INTEGRATING CIRCUIT

    DOEpatents

    Englemann, R.H.

    1963-08-20

    An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

  2. Integrated Circuits in the Introductory Electronics Laboratory

    ERIC Educational Resources Information Center

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  3. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  4. Neuromorphic opto-electronic integrated circuits for optical signal processing

    NASA Astrophysics Data System (ADS)

    Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

    2014-08-01

    The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

  5. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  6. System and method for interfacing large-area electronics with integrated circuit devices

    DOEpatents

    Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

    2016-07-12

    A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

  7. Active parallel redundancy for electronic integrator-type control circuits

    NASA Technical Reports Server (NTRS)

    Peterson, R. A.

    1971-01-01

    Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

  8. Plasmonic and electronic device-based integrated circuits and their characteristics

    NASA Astrophysics Data System (ADS)

    Sakai, H.; Okahisa, S.; Nakayama, Y.; Nakayama, K.; Fukuhara, M.; Kimura, Y.; Ishii, Y.; Fukuda, M.

    2016-11-01

    This paper presents a plasmonic circuit that has been monolithically integrated with electronic devices on a silicon substrate and then discusses the concept behind this circuit. To form the proposed circuit, two plasmonic waveguides and a detector are integrated with metal-oxide-semiconductor field-effect transistors (MOSFETs) on the substrate. In the circuit, intensity signals or coherent plasmonic signals are generated by coherent light at an operating wavelength at which silicon is transparent, and these signals propagate along the waveguides before they are converted into electrical signals by the detector. These electrical intensity and coherent signals then drive the MOSFETs during both DC and AC operation. The measured performances of the devices indicate that surface plasmon polaritons propagate on the metal surface at the speed of light and drive the electronic devices without any absorption in the silicon.

  9. Photonic Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Merritt, Scott; Krainak, Michael

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  10. Efficient computer-aided failure analysis of integrated circuits using scanning electron microscopy

    NASA Astrophysics Data System (ADS)

    Propst, R. H.; Oxford, W. V.

    1985-12-01

    A working, operational system for computer-aided failure analysis of integrated circuits using a scanning electron microscope (SEM) is described. Statistical data analysis and image-processing algorithms are applied to digitized SEM image data. Faults are automatically identified and characterized at the single transistor level. Data-storage requirements for locating and characterizing semiconductor device failures are evaluated. A working, operational methods is presented which minimizes these requirements, increases throughput, and permits a high degree of automation.

  11. SEM analysis of ionizing radiation effects in linear integrated circuits. [Scanning Electron Microscope

    NASA Technical Reports Server (NTRS)

    Stanley, A. G.; Gauthier, M. K.

    1977-01-01

    A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

  12. Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

    PubMed

    Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

    2010-02-21

    Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

  13. Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

    PubMed

    Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

    2010-02-21

    Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings. PMID:20126694

  14. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

    PubMed Central

    Iovan, Adrian; Fischer, Marco; Lo Conte, Roberto

    2012-01-01

    Summary Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths. PMID:23365801

  15. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices.

    PubMed

    Iovan, Adrian; Fischer, Marco; Lo Conte, Roberto; Korenivski, Vladislav

    2012-01-01

    Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  16. Electronic control circuits: A compilation

    NASA Technical Reports Server (NTRS)

    1973-01-01

    A compilation of technical R and D information on circuits and modular subassemblies is presented as a part of a technology utilization program. Fundamental design principles and applications are given. Electronic control circuits discussed include: anti-noise circuit; ground protection device for bioinstrumentation; temperature compensation for operational amplifiers; hybrid gatling capacitor; automatic signal range control; integrated clock-switching control; and precision voltage tolerance detector.

  17. An Electronics Course Emphasizing Circuit Design

    ERIC Educational Resources Information Center

    Bergeson, Haven E.

    1975-01-01

    Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

  18. The use of fault tolerant and testable high performance integrated circuits for improved military electronic system availability

    NASA Astrophysics Data System (ADS)

    Bart, J. J.

    1985-08-01

    The rapid evolution of high performance Very Large Scale Integrated Circuits (VLSICs) has resulted in accelerated opportunities for improving the operational performance of military electronic systems. In addition, the microelectronics technology base also holds the promise of providing improvements in the operational availability, survivability and logistics supportability of these complex systems. The basics for these advances lies in the ability to design microelectronics based systems which are much more fault tolerant and more easily testable than those which have been developed to date. The current activities in the design of testable/fault tolerant integrated circuits are reviewed and areas for future emphasis are suggested.

  19. Polymorphic Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian

    2004-01-01

    Polymorphic electronics is a nascent technological discipline that involves, among other things, designing the same circuit to perform different analog and/or digital functions under different conditions. For example, a circuit can be designed to function as an OR gate or an AND gate, depending on the temperature (see figure). Polymorphic electronics can also be considered a subset of polytronics, which is a broader technological discipline in which optical and possibly other information- processing systems could also be designed to perform multiple functions. Polytronics is an outgrowth of evolvable hardware (EHW). The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles. To recapitulate: The essence of EHW is to design, construct, and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by computational simulation (in which case the evolution is said to be extrinsic), tested in real hardware (in which case the evolution is said to be intrinsic), or tested in random sequences of computational simulation and real hardware (in which case the evolution is said to be mixtrinsic).

  20. Monolithic microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Pucel, R. A.

    Monolithic microwave integrated circuits (MMICs), a new microwave technology which is expected to exert a profound influence on microwave circuit designs for future military systems as well as for the commercial and consumer markets, is discussed. The book contains an historical discussion followed by a comprehensive review presenting the current status in the field. The general topics of the volume are: design considerations, materials and processing considerations, monolithic circuit applications, and CAD, measurement, and packaging techniques. All phases of MMIC technology are covered, from design to testing.

  1. ELECTRONIC PHASE CONTROL CIRCUIT

    DOEpatents

    Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

    1959-04-21

    An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

  2. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1990-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  3. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1988-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  4. Bioluminescent bioreporter integrated circuit

    DOEpatents

    Simpson, Michael L.; Sayler, Gary S.; Paulus, Michael J.

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  5. ELECTRONIC TRIGGER CIRCUIT

    DOEpatents

    Russell, J.A.G.

    1958-01-01

    An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

  6. ELECTRONIC MULTIPLIER CIRCUIT

    DOEpatents

    Thomas, R.E.

    1959-08-25

    An electronic multiplier circuit is described in which an output voltage having an amplitude proportional to the product or quotient of the input signals is accomplished in a novel manner which facilitates simplicity of circuit construction and a high degree of accuracy in accomplishing the multiplying and dividing function. The circuit broadly comprises a multiplier tube in which the plate current is proportional to the voltage applied to a first control grid multiplied by the difference between voltage applied to a second control grid and the voltage applied to the first control grid. Means are provided to apply a first signal to be multiplied to the first control grid together with means for applying the sum of the first signal to be multiplied and a second signal to be multiplied to the second control grid whereby the plate current of the multiplier tube is proportional to the product of the first and second signals to be multiplied.

  7. Design automation for integrated circuits

    NASA Astrophysics Data System (ADS)

    Newell, S. B.; de Geus, A. J.; Rohrer, R. A.

    1983-04-01

    Consideration is given to the development status of the use of computers in automated integrated circuit design methods, which promise the minimization of both design time and design error incidence. Integrated circuit design encompasses two major tasks: error specification, in which the goal is a logic diagram that accurately represents the desired electronic function, and physical specification, in which the goal is an exact description of the physical locations of all circuit elements and their interconnections on the chip. Design automation not only saves money by reducing design and fabrication time, but also helps the community of systems and logic designers to work more innovatively. Attention is given to established design automation methodologies, programmable logic arrays, and design shortcuts.

  8. Integrated Circuit Immunity

    NASA Technical Reports Server (NTRS)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  9. Monolithic Optoelectronic Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

    1990-01-01

    Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

  10. Graphene radio frequency receiver integrated circuit.

    PubMed

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  11. Electron and optical beam testing of integrated circuits using CIVA, LIVA, and LECIVA

    SciTech Connect

    Cole, E.I. Jr.

    1995-09-01

    Charge-Induced Voltage Alteration (CIVA), Light-Induced Voltage Alteration, (LIVA), and Low Energy CIVA (LECIVA) are three new failure analysis imaging techniques developed to quickly localize defects on ICs. All three techniques utilize the voltage fluctuations of a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA yield rapid localization of open interconnections on ICs. LIVA allows quick localization of open-circuited and damaged semiconductor junctions. LIVA can also be used to image transistor logic states and can be performed from the backside of ICs with an infrared laser source. The physics of signal generation for each technique and examples of their use in failure analysis are described.

  12. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  13. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  14. ELECTRONIC PULSE SCALING CIRCUITS

    DOEpatents

    Cooke-Yarborough, E.H.

    1958-11-18

    Electronic pulse scaling circults of the klnd comprlsing a serles of bi- stable elements connected ln sequence, usually in the form of a rlng so as to be cycllcally repetitive at the highest scallng factor, are described. The scaling circuit comprises a ring system of bi-stable elements each arranged on turn-off to cause, a succeeding element of the ring to be turned-on, and one being arranged on turn-off to cause a further element of the ring to be turned-on. In addition, separate means are provided for applying a turn-off pulse to all the elements simultaneously, and for resetting the elements to a starting condition at the end of each cycle.

  15. Modular electron transfer circuits for synthetic biology

    PubMed Central

    Agapakis, Christina M

    2010-01-01

    Electron transfer is central to a wide range of essential metabolic pathways, from photosynthesis to fermentation. The evolutionary diversity and conservation of proteins that transfer electrons makes these pathways a valuable platform for engineered metabolic circuits in synthetic biology. Rational engineering of electron transfer pathways containing hydrogenases has the potential to lead to industrial scale production of hydrogen as an alternative source of clean fuel and experimental assays for understanding the complex interactions of multiple electron transfer proteins in vivo. We designed and implemented a synthetic hydrogen metabolism circuit in Escherichia coli that creates an electron transfer pathway both orthogonal to and integrated within existing metabolism. The design of such modular electron transfer circuits allows for facile characterization of in vivo system parameters with applications toward further engineering for alternative energy production. PMID:21468209

  16. Thermally controlled coupling of a rolled-up microtube integrated with a waveguide on a silicon electronic-photonic integrated circuit.

    PubMed

    Zhong, Qiuhang; Tian, Zhaobing; Veerasubramanian, Venkat; Dastjerdi, M Hadi Tavakoli; Mi, Zetian; Plant, David V

    2014-05-01

    We report on the first experimental demonstration of the thermal control of coupling strength between a rolled-up microtube and a waveguide on a silicon electronic-photonic integrated circuit. The microtubes are fabricated by selectively releasing a coherently strained GaAs/InGaAs heterostructure bilayer. The fabricated microtubes are then integrated with silicon waveguides using an abruptly tapered fiber probe. By tuning the gap between the microtube and the waveguide using localized heaters, the microtube-waveguide evanescent coupling is effectively controlled. With heating, the extinction ratio of a microtube whispering-gallery mode changes over an 18 dB range, while the resonant wavelength remains approximately unchanged. Utilizing this dynamic thermal tuning effect, we realize coupling modulation of the microtube integrated with the silicon waveguide at 2 kHz with a heater voltage swing of 0-6 V.

  17. Progress in organic integrated circuit manufacture

    NASA Astrophysics Data System (ADS)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  18. CADAT integrated circuit mask analysis

    NASA Technical Reports Server (NTRS)

    1981-01-01

    CADAT System Mask Analysis Program (MAPS2) is automated software tool for analyzing integrated-circuit mask design. Included in MAPS2 functions are artwork verification, device identification, nodal analysis, capacitance calculation, and logic equation generation.

  19. Scaling of graphene integrated circuits.

    PubMed

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-01

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing. PMID:25873359

  20. Military Curricula for Vocational & Technical Education. Basic Electricity and Electronics. CANTRAC A-100-0010. Module 34: Linear Integrated Circuits. Study Booklet.

    ERIC Educational Resources Information Center

    Chief of Naval Education and Training Support, Pensacola, FL.

    This individualized learning module on linear integrated circuits is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Two lessons are included in…

  1. Variational integrators for electric circuits

    SciTech Connect

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  2. Displacement Damage in Bipolar Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  3. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  4. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  5. Optoelectronic integrated circuits

    NASA Astrophysics Data System (ADS)

    Forrest, Stephen R.

    1987-11-01

    The technology development requirements of several generic photonic systems for advanced optoelectronic ICs are currently being met by the fabrication of highly functional integrated transmitters, receivers, modulators, and arrays of such devices. Attention is presently given to illustrative examples of each of these, as well as of other 'archetypal' ICs. It is noted that the materials-growth techniques employed in optoelectronic IC structures constitute the foundation of their development hierarchy; the primary pacer of development progress is therefore the rapidity of advancements in epitaxial materials-growth technology.

  6. Integrated Circuit Stellar Magnitude Simulator

    ERIC Educational Resources Information Center

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  7. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  8. MOS integrated circuit fault modeling

    NASA Technical Reports Server (NTRS)

    Sievers, M.

    1985-01-01

    Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

  9. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  10. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  11. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  12. Bioluminescent bioreporter integrated circuits (BBICs)

    NASA Astrophysics Data System (ADS)

    Simpson, Michael L.; Sayler, Gary S.; Nivens, David; Ripp, Steve; Paulus, Michael J.; Jellison, Gerald E.

    1998-07-01

    As the workhorse of the integrated circuit (IC) industry, the capabilities of CMOS have been expanded well beyond the original applications. The full spectrum of analog circuits from switched-capacitor filters to microwave circuit blocks, and from general-purpose operational amplifiers to sub- nanosecond analog timing circuits for nuclear physics experiments have been implemented in CMOS. This technology has also made in-roads into the growing area of monolithic sensors with devices such as active-pixel sensors and other electro-optical detection devices. While many of the processes used for MEMS fabrication are not compatible with the CMOS IC process, depositing a sensor material onto a previously fabricated CMOS circuit can create a very useful category of sensors. In this work we report a chemical sensor composed of bioluminescent bioreporters (genetically engineered bacteria) deposited onto a micro-luminometer fabricated in a standard CMOS IC process. The bioreporter used for this work emitted 490-nm light when exposed to toluene. This luminescence was detected by the micro- luminometer giving an indication of the concentration of toluene. Other bioluminescent bioreporters sensitive to explosives, mercury, and other organic chemicals and heavy metals have been reported. These could be incorporated (individually or in combination) with the micro-luminometer reported here to form a variety of chemical sensors.

  13. Prospects For Quantum Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Bate, R. T.; Frazier, G. A.; Frensley, W. R.; Lee, J. W.; Reed, M. A.

    1987-08-01

    Recent progress in research on resonant tunneling diodes, and on lateral quantization effects in quantum wells renews hope for the development of active unipolar heterojunction devices which incorporate no depletion layers, and hence can be extremely compact in both vertical and lateral dimensions. If such devices meeting the fundamental requirements for ultrahigh density integrated circuits can be developed, and if revolutionary chip architectures which overcome current interconnection limitations can be devised, then a new generation of integrated circuits approaching the ultimate limits of functional density and functional throughput may eventually ensue. Although many of the most challenging problems in this scenario have not yet been addressed, progress is being made in the areas of fabrication and characterization of resonant tunneling devices, simulation of such devices using quantum transport theory, and simulation of nearest-neighbor connected (two-dimensional cellular automaton) architectures. This paper reviews the progress in these areas at Texas Instruments, and discusses the prospects for the future.

  14. Integrated circuits, and design and manufacture thereof

    DOEpatents

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  15. Simple photometer circuits using modular electronic components

    NASA Technical Reports Server (NTRS)

    Wampler, J. E.

    1975-01-01

    Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

  16. Removing Bonded Integrated Circuits From Boards

    NASA Technical Reports Server (NTRS)

    Rice, John T.

    1989-01-01

    Small resistance heater makes it easier, faster, and cheaper to remove integrated circuit from hybrid-circuit board, package, or other substrate for rework. Heater, located directly in polymeric bond interface or on substrate under integrated-circuit chip, energized when necessary to remove chip. Heat generated softens adhesive or solder that bonds chip to substrate. Chip then lifted easily from substrate.

  17. Tunable resonant structures for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Ptasinski, Joanna Nina

    Photonics is an evolving field allowing for optical devices to be made cost effectively using standard semiconductor fabrication techniques, which in turn enables integration with microelectronic chips. Chip scale photonics will play an increasing role in the future of communications as the demand for bandwidth and reduced power consumption per bit continues to grow. Tunable optical circuit components are one of the essential technologies in the development of photonic analogues for classical electronic devices, where tunable photonic resonant structures allow for altering of their electromagnetic spectrum and find applications in optical switching, filtering, buffering, lasers and biosensors. The scope of this work is focused on tunable resonant structures for photonic integrated circuits. Specifically, this work demonstrates active tuning of silicon photonic resonant structures using the properties of dye doped nematic liquid crystals, temperature stabilization of silicon photonics using the passive properties of liquid crystals, and the effects of low density plasma enhanced chemical vapor deposition (PECVD) claddings on ring resonator device performance.

  18. Electronic circuits: A compilation. [for electronic equipment in telecommunication

    NASA Technical Reports Server (NTRS)

    1976-01-01

    A compilation containing articles on newly developed electronic circuits and systems is presented. It is divided into two sections: (1) section 1 on circuits and techniques of particular interest in communications technology, and (2) section 2 on circuits designed for a variety of specific applications. The latest patent information available is also given. Circuit diagrams are shown.

  19. Automatic generation of signal processing integrated circuits

    SciTech Connect

    Pope, S.P.

    1985-01-01

    A system for the automated design of signal processing integrated circuits is described in this thesis. The system is based on a library of circuit cells, and a software package that can configure the cells into complete integrated circuits. The architecture of the cell library is optimized for low and medium bandwidth digital signal processing applications. Circuits designed with the system use a multiprocessor architecture. Input to the system is a design file written in a specialized programming language. Software emulation from the design file is used to verify performance. A two-pass silicon compiler is used to translate the design file into a mask-level description of an integrated circuit. A major goal of the project is to make the system useable by those with little or no formal training in integrated circuits. A second goal is to reduce the time and cost associated with performing an integrated circuit design, while still producing designs which are reasonably efficient in their use of the technology. Development of the system was guided by basic research on appropriate architectures and circuit constructs for signal processors. As part of this research an integrated circuit was designed which performs speech analysis and synthesis. This vocoder circuit is intended for use in low-bit-rate digital speech transmission systems.

  20. Electronic switches and control circuits: A compilation

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The innovations in this updated series of compilations dealing with electronic technology represents a carefully selected collection of items on electronic switches and control circuits. Most of the items are based on well-known circuit design concepts that have been simplified or refined to meet NASA's demanding requirement for reliability, simplicity, fail-safe characteristics, and the capability of withstanding environmental extremes.

  1. Nanophotonic integrated circuits from nanoresonators grown on silicon

    NASA Astrophysics Data System (ADS)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D.; Li, Kun; Chang-Hasnain, Connie

    2014-07-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore’s law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  2. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    PubMed

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-01-01

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  3. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  4. Thermionic integrated circuit program: Final report

    SciTech Connect

    Wilde, D.K.; Lynn, D.K.; Hamilton, D.

    1988-05-01

    This report describes the development of an operational amplifier using radiation hardened Thermionic Integrated Circuits (TICs). The report is written as a tutorial to cover all aspects of the fabrication process and circuit development as well as the process and circuit modifications required to meet the integration requirements of the operational amplifier. Recent experimental results are discussed in which both devices and test circuit data are compared to theoretical computer code predictions. The development of compatible high-temperature thin-film resistors is also presented. Because the project is being terminated prior to the completion of the amplifier, suggestions are made for additional advance development.

  5. Electronic circuits for communications systems: A compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    The compilation of electronic circuits for communications systems is divided into thirteen basic categories, each representing an area of circuit design and application. The compilation items are moderately complex and, as such, would appeal to the applications engineer. However, the rationale for the selection criteria was tailored so that the circuits would reflect fundamental design principles and applications, with an additional requirement for simplicity whenever possible.

  6. Oxide bipolar electronics: materials, devices and circuits

    NASA Astrophysics Data System (ADS)

    Grundmann, Marius; Klüpfel, Fabian; Karsthof, Robert; Schlupp, Peter; Schein, Friedrich-Leonhard; Splith, Daniel; Yang, Chang; Bitter, Sofie; von Wenckstern, Holger

    2016-06-01

    We present the history of, and the latest progress in, the field of bipolar oxide thin film devices. As such we consider primarily pn-junctions in which at least one of the materials is a metal oxide semiconductor. A wide range of n-type and p-type oxides has been explored for the formation of such bipolar diodes. Since most oxide semiconductors are unipolar, challenges and opportunities exist with regard to the formation of heterojunction diodes and band lineups. Recently, various approaches have led to devices with high rectification, namely p-type ZnCo2O4 and NiO on n-type ZnO and amorphous zinc-tin-oxide. Subsequent bipolar devices and applications such as photodetectors, solar cells, junction field-effect transistors and integrated circuits like inverters and ring oscillators are discussed. The tremendous progress shows that bipolar oxide electronics has evolved from the exploration of various materials and heterostructures to the demonstration of functioning integrated circuits. Therefore a viable, facile and high performance technology is ready for further exploitation and performance optimization.

  7. Analog VLSI neural network integrated circuits

    NASA Astrophysics Data System (ADS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-12-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  8. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  9. Integrated-Circuit Pseudorandom-Number Generator

    NASA Technical Reports Server (NTRS)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  10. Reverse engineering of integrated circuits

    DOEpatents

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  11. Widefield subsurface microscopy of integrated circuits.

    PubMed

    Köklü, Fatih Hakan; Quesnel, Justin I; Vamivakas, Anthony N; Ippolito, Stephen B; Goldberg, Bennett B; Unlü, M Selim

    2008-06-23

    We apply the numerical aperture increasing lens technique to widefield subsurface imaging of silicon integrated circuits. We demonstrate lateral and longitudinal resolutions well beyond the limits of conventional backside imaging. With a simple infrared widefield microscope (lambda(0) = 1.2 microm), we demonstrate a lateral spatial resolution of 0.26 microm (0.22 lambda(0)) and a longitudinal resolution of 1.24 microm (1.03 lambda(0)) for backside imaging through the silicon substrate of an integrated circuit. We present a spatial resolution comparison between widefield and confocal microscopy, which are essential in integrated circuit analysis for emission and excitation microscopy, respectively.

  12. Reusable vibration resistant integrated circuit mounting socket

    SciTech Connect

    Evans, C.N.

    1993-12-31

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  13. Reusable vibration resistant integrated circuit mounting socket

    DOEpatents

    Evans, Craig N.

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  14. Electron Beam/Optical Hybrid Lithography For The Production Of Gallium Arsenide Monolithic Microwave Integrated Circuits (Mimics)

    NASA Astrophysics Data System (ADS)

    Nagarajan, Rao M.; Rask, Steven D.

    1988-06-01

    A hybrid lithography technique is described in which selected levels are fabricated by high resolution direct write electron beam lithography and all other levels are fabricated optically. This technique permits subhalf micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. The goal is to improve throughput and reduce overall cost of fabricating MIMIC GaAS chips without compromising device performance. The lithography equipment used for these experiments is the Cambridge Electron beam vector scan system EBMF 6.4 capable of achieving ultra high current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The optical aligner is a Karl Suss Contact aligner. The flexibility of the Cambridge electron beam system is matched to the less flexible Karl Suss contact aligner. The lithography related factors, such as image placement, exposure and process related analyses, which influence overlay, pattern quality and performance, are discussed. A process chip containing 3.2768mm fields in an eleven by eleven array was used for alignment evaluation on a 3" semi-insulating GaAS wafer. Each test chip contained five optical verniers and four Prometrix registration marks per field along with metal bumps for alignment marks. The process parameters for these chips are identical to those of HEMT/epi-MESFET ohmic contact and gate layer processes. These layers were used to evaluate the overlay accuracy because of their critical alignment and dimensional control requirements. Two cases were examined: (1) Electron beam written gate layers aligned to optically imaged ohmic contact layers and (2) Electron beam written gate layers aligned to electron beam written ohmic contact layers. The effect of substrate charging by the electron beam is also investigated. The resulting peak overlay error accuracies are: (1) Electron

  15. Chain Of Test Contacts For Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo

    1989-01-01

    Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

  16. Gallium arsenide digital integrated circuits - A systems perspective

    NASA Astrophysics Data System (ADS)

    Kanopoulos, Nick

    The characteristics of GaAs electronic components and their integration into digital circuits are examined in an introduction for graduate engineering students. Chapters are devoted to GaAs components, GaAs logic-gate design, GaAs logic circuits, GaAs digital-IC design principles, packaging, high-speed testing and design for testability, and GaAs insertion into system design. Diagrams, drawings, and exercises for each chapter are included.

  17. Optical XOR circuit using combined technology of photonics and electronics

    NASA Astrophysics Data System (ADS)

    Takiguchi, Koichi

    2013-12-01

    I propose and demonstrate a novel and simple optical exclusive OR circuit for binary signals, which is composed of a balanced photo-detector and a Mach-Zehnder intensity modulator. Two input optical signals into the photo-detector produce an electrical signal to drive the modulator. The modulator outputs an optical exclusive OR signal of the two input optical signals. I report the configuration, operating principle, and primary experimental results using 10 Gbit/s binary signals to demonstrate that the exclusive OR circuit operates properly. The proposed simple circuit is suitable for the future hybrid integration of photonics and electronics.

  18. Zipper Connectors for Flexible Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Barnes, Kevin N.

    2003-01-01

    Devices that look and function much like conventional zippers on clothing have been proposed as connectors for flexible electronic circuits. Heretofore, flexible electronic circuits have commonly included rigid connectors like those of conventional rigid electronic circuits. The proposed zipper connectors would make it possible to connect and disconnect flexible circuits quickly and easily. Moreover, the flexibility of zipper connectors would make them more (relative to rigid connectors) compatible with flexible circuits, so that the advantages of flexible circuitry could be realized more fully. Like a conventional zipper, a zipper according to the proposal would include teeth anchored on flexible tapes, a slider with a loosely attached clasp, a box at one end of the rows of mating teeth, and stops at the opposite ends. The tapes would be made of a plastic or other dielectric material. On each of the two mating sides of the zipper, metal teeth would alternate with dielectric (plastic) teeth, there being two metal teeth for each plastic one. When the zipper was closed, each metal tooth from one side would be in mechanical and electrical contact with a designated metal tooth from the other side, and these mating metal teeth would be electrically insulated from the next pair of mating metal teeth by an intervening plastic tooth. The metal teeth would be soldered or crimped to copper tabs. Wires or other conductors connected to electronic circuits would be soldered or crimped to the ends of the tabs opposite the teeth.

  19. Handbook of microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Hoffmann, Reinmut K.

    The design and operation of ICs for use in the 0.5-20-GHz range are described in an introductory and reference work for industrial engineers. Chapters are devoted to an overview of microwave IC (MIC) technology, general stripline characteristics, microwave transmission line (MTL) parameters for microstrips with isotropic dielectric substrates, higher-order modes on a microstrip, the effects of metallic enclosure on MTL transmission parameters, losses in microstrips, the measurement of MTL parameters, and MTLs on anisotropic dielectric substrates. Consideration is given to coupled microstrips on dielectric substrates, microstrip discontinuities, radiation from microstrip circuits, MTL variations, coplanar MTLs, slotlines, and spurious modes in MTL circuits. Diagrams, drawings, graphs, and a glossary of symbols are provided.

  20. Maximum Temperature Detection System for Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  1. Solution methods for very highly integrated circuits.

    SciTech Connect

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator

  2. Integrated logic circuits using single-atom transistors.

    PubMed

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  3. Printed organic thin-film transistor-based integrated circuits

    NASA Astrophysics Data System (ADS)

    Mandal, Saumen; Noh, Yong-Young

    2015-06-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted.

  4. Modular packaging technique for combining integrated circuits and discrete components

    NASA Technical Reports Server (NTRS)

    Lacchia, J. F.

    1969-01-01

    Technique for packaging electronic modules interconnects integrated circuits and discrete components by means of beryllium-copper strips in a molded diallyphthalate tray. Simple girder-like construction provides ease of assembly, high rigidity, excellent vibration resistance, and good heat dissipation characteristics.

  5. Chemical vapor deposition for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1980-01-01

    Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

  6. How will photonic integrated circuits develop?

    NASA Astrophysics Data System (ADS)

    Haney, Michael W.

    2013-02-01

    This paper explores issues associated with Photonic Integrated Circuit (PIC) research and development - with an overall goal of initiating a discussion of how PIC technology should develop and eventually be deployed with high impact. Significant research and development programs have focused on PICs for routing and switching, and computer interconnects. Most recently, the application domain of PICs has diversified greatly, and now includes analog signal processing, remote sensing, biological and chemical sensing, neural interfacing, and solar cells. A key feature of PIC technology growth has been the exploitation of high-density fabrication and packaging technology originally developed for the Silicon IC industry. PIC foundry services are emerging - and there has been a natural attempt to ascribe a "Moore's Law" to PIC scaling. Analogies to Silicon electronic scaling, however, should be used with caution. PIC complexity scaling may be driven more by the ability to access the degrees-of-freedom offered by PIC-based optical domain signal processing, rather than increasing device count. Specific examples of PIC research in chip-scale computer interconnects and integrated micro-concentrators for solar cells are highlighted.

  7. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  8. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  9. Radiation damage in MOS integrated circuits, Part 1

    NASA Technical Reports Server (NTRS)

    Danchenko, V.

    1971-01-01

    Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

  10. Self-integration of nanowires into circuits via guided growth

    PubMed Central

    Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

    2013-01-01

    The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom–up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel “self-integration” of NWs into electronic circuits and functional systems based on guided growth. PMID:23904485

  11. 3D circuit integration for Vertex and other detectors

    SciTech Connect

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  12. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  13. Laboratory experiments in integrated circuit fabrication

    NASA Technical Reports Server (NTRS)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-01-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  14. Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

    NASA Technical Reports Server (NTRS)

    Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

    1995-01-01

    Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

  15. Mathematical Modeling of Electronic Devices and Circuits

    NASA Astrophysics Data System (ADS)

    Singh, B. P.; Singh, Meena; Roy, Sanjay Kumar

    2010-11-01

    The necessity of modeling lies in the nature of technology and its advancement. The modeling minimizes time and cost of the process involved. The mathematical model provides an insight into the behavior of the physical system that reduces the problem to its essential characteristics. The floating admittance matrix (FAM) approach is an elegant method of mathematical modeling of electronic devices and circuits.

  16. General Electronics Technician: Semiconductor Devices and Circuits.

    ERIC Educational Resources Information Center

    Hilley, Robert

    These instructional materials include a teacher's guide designed to assist instructors in organizing and presenting an introductory course in general electronics focusing on semiconductor devices and circuits and a student guide. The materials are based on the curriculum-alignment concept of first stating the objectives, developing instructional…

  17. Microwave integrated circuit for Josephson voltage standards

    NASA Technical Reports Server (NTRS)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  18. A CCD integrated circuit for transient recorders

    NASA Technical Reports Server (NTRS)

    Balch, J. W.; Mcconaghy, C. F.

    1976-01-01

    A 50 MHz CCD integrated circuit is described that was developed for use in transient analog signal recorders to sample and time expand transient signals. The integrated circuit achieves an effective 200 MHz sample rate by using four 32 stage peristaltic CCDs to sample the transient signal four times each clock period. Dual frequency, 4 phi clocking is used to sample and time expand the sampled data. The output signals of the four CCDs are multiplexed on chip into a single low frequency output data line. When operated with 50 MHz/165 KHz 4 phi clocks, this circuit has a 200 MHz sample rate, a record length of 640 nanoseconds, a time expansion factor of 303, and overall signal to noise ratio of 40:1. The signal to noise ratio is limited by fixed pattern noise of the four CCDs.

  19. Package Holds Five Monolithic Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  20. Healing Voids In Interconnections In Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

    1989-01-01

    Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

  1. Bioluminescent bioreporter integrated circuit detection methods

    DOEpatents

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  2. Integrated Circuit Failure Analysis Hypertext Help System

    1995-02-23

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  3. An analog integrated-circuit vocal tract.

    PubMed

    Keng Hoong Wee; Turicchia, L; Sarpeshkar, R

    2008-12-01

    We present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 muW analog vocal tract chip includes a 16-stage cascade of two-port pi-elements that forms a tunable transmission line, electronically variable impedances, and a current source as the glottal source. A nonlinear resistor models laminar and turbulent flow in the vocal tract. The measured SNR at the output of the analog vocal tract is 64, 66, and 63 dB for the first three formant resonances of a vocal tract with uniform cross-sectional area. The analog vocal tract can be used with auditory processors in a feedback speech locked loop-analogous to a phase locked loop-to implement speech recognition that is potentially robust in noise. Our use of a physiological model of the human vocal tract enables the analog vocal tract chip to synthesize speech signals of interest, using articulatory parameters that are intrinsically compact and linearly interpolatable. PMID:23853134

  4. SEU In An Advanced Bipolar Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.; Secrest, Elaine C.; Berndt, Dale F.

    1989-01-01

    Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

  5. Integrated-Circuit Active Digital Filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1986-01-01

    Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

  6. Development of 3D integrated circuits for HEP

    SciTech Connect

    Yarema, R.; /Fermilab

    2006-09-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

  7. Applying analog integrated circuits for HERO protection

    NASA Technical Reports Server (NTRS)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  8. Development of beam lead RF integrated circuits

    NASA Technical Reports Server (NTRS)

    Kline, A. J.; Kermode, A. W.

    1975-01-01

    This paper describes the design and development of a set of multifunction VHF/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical test results and the distribution of test parameters are presented. A unique carrier for beam-lead devices is described, and the need for such a device is discussed. The application of the carrier to device screening, burn-in and drift measurements is discussed together with the incentives for providing these capabilities. An overview of the integration of the devices into the spacecraft radio is given and candidate assembly processes are discussed. The technology impact of this approach upon future spacecraft radio systems is qualitatively examined.

  9. Integrated Circuit For Simulation Of Neural Network

    NASA Technical Reports Server (NTRS)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  10. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  11. Accessibility of applications specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Strip, D. R.

    1986-03-01

    Applications specific integrated circuits (ASICs) open new design opportunities in Sandia component applications. ASICs can be used to overcome many of the constraints that reduce system functionality in Sandia systems. Key constraints in our environment are power consumption, volume, weight, speed, and radiation-hardness. In addition, use of ASICs may reduce the costs of system design, acquisition, and life-cycle maintenance. Design tools for integrated circuits are rapidly simplifying the design of integrated circuits. Just as high level computer languages enabled applications-oriented computer users to take control of their own code development after assembly coding had limited the practicality of user design, in ICC design tools and approaches are enabling the applications-oriented user to design an ASIC with modest training and in a short time period. In order to demonstrate the state of the design systems, we have selected a representative application and, without any formal training or experience in IC design, have designed and fabricated an ASIC. This report details the steps that were followed and the time they took. It is important to emphasize that this project was the first chip designed start-to-finish on the Mentor design stations in Organization 2110; therefore most of the problems encountered were typical of a first pass through a new system. Most of the problems were quickly wrung out by the CAD tools staff; future users of the system should not expect to have the problems recur.

  12. Progress in radiation immune thermionic integrated circuits

    SciTech Connect

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  13. Power system with an integrated lubrication circuit

    DOEpatents

    Hoff, Brian D.; Akasam, Sivaprasad; Algrain, Marcelo C.; Johnson, Kris W.; Lane, William H.

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  14. Radio-Frequency Electronics, Circuits and Applications

    NASA Astrophysics Data System (ADS)

    Hagen, Jon B.

    This accessible and comprehensive book provides an introduction to the basic concepts and key circuits of radio frequency systems, covering fundamental principles which apply to all radio devices, from wireless data transceivers on semiconductor chips to high-power broadcast transmitters. Topics covered include filters, amplifiers, oscillators, modulators, low-noise amplifiers, phase-locked loops, and transformers. Applications of radio frequency systems are described in such areas as communications, radio and television broadcasting, radar, and radio astronomy. The book contains many exercises, and assumes only a knowledge of elementary electronics and circuit analysis. It will be an ideal textbook for advanced undergraduate and graduate courses in electrical engineering, as well as an invaluable reference for researchers and professional engineers in this area, or for those moving into the field of wireless communications.

  15. Construction and Analysis of Electronic circuits

    NASA Technical Reports Server (NTRS)

    Thomas, Ashley N.

    2004-01-01

    The Aviation Environmental Technical Branch produces many various types of aeronautical research that benefits the NASA mission for space exploration and in turn, produces new technology for our nation. One of the present goals of the Aviation Environmental Technical Branch is to create better engines for airplanes by testing supersonic jet propulsion and safe fuel combustion. During the summer of 2004, I was hired by Vincent Sattenvhite Chief executive of the Aviation Environmental Technical Branch to Assist Yves Lamothe with a fuel igniter circuit. Yves Lamothe is an electrical engineer who is currently working on safe fuel combustion testing. This testing is planned to determine the minimum ignition energy for fuel and air vapors of current and alternative fuels under simulated flight conditions. An air temperature bath will provide simulated flight profile temperatures and the heat fluxes to the test chamber. I was assigned with Yves to help complete the igniter circuit which consists of a 36k voltage supply an oscilloscope, and a high voltage transistor switch. During my tenure in the L.E.C.I.R.P. program I studied the basics of electricity and circuitry along with two other projects that I completed. In the beginning of my internship, I devote all of my time to research the aspects of circuitry so that I would be prepared for the projects that I was assigned to do. I read about lessons on; the basic physical concepts of electronics, Electrical units, Basic dc circuits, direct current circuit analysis, resistance and cell batteries, various types of magnetism , Alternating current basics, inductance, and power supplies. I received work sheets and math equations from my Mentor so that I could be able to apply these concepts into my work. After I complete my studies, I went on to construct a LED chaser circuit which displays a series of light patterns using a 555 timer. I incorporated a switch and motion detector into the circuit to create basic alarm system

  16. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    SciTech Connect

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  17. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  18. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, Edward H.; Tuckerman, David B.

    1991-01-01

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

  19. An optoelectronic integrated device including a laser and its driving circuit

    NASA Astrophysics Data System (ADS)

    Matsueda, H.; Tanaka, T. P.; Nakano, H.

    1984-10-01

    A monolithic optoelectronic integrated circuit (OEIC) including a laser diode, photomonitor and driving and detecting circuits has been fabricated on a semi-insulating GaAs substrate. The OEIC has a horizontal integrating structure which is suitable for realizing high-density multifunctional devices. The fabricating process and the static and dynamic characteristics of the optical and electronic elements are described. The preliminary results of the cooperative operation of the laser and its driving circuit are also presented.

  20. An integrator circuit in cerebellar cortex.

    PubMed

    Maex, Reinoud; Steuber, Volker

    2013-09-01

    The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low (< 1 per s) and high rates (> 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant.

  1. Organic printed photonics: From microring lasers to integrated circuits

    PubMed Central

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-01-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  2. Towards quantum thermodynamics in electronic circuits

    NASA Astrophysics Data System (ADS)

    Pekola, Jukka P.

    2015-02-01

    Electronic circuits operating at sub-kelvin temperatures are attractive candidates for studying classical and quantum thermodynamics: their temperature can be controlled and measured locally with exquisite precision, and they allow experiments with large statistical samples. The availability and rapid development of devices such as quantum dots, single-electron boxes and superconducting qubits only enhance their appeal. But although these systems provide fertile ground for studying heat transport, entropy production and work in the context of quantum mechanics, the field remains in its infancy experimentally. Here, we review some recent experiments on quantum heat transport, fluctuation relations and implementations of Maxwell's demon, revealing the rich physics yet to be fully probed in these systems.

  3. Study of Contact Resistances in Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Lambe, J.; Suszko, S. F.

    1985-01-01

    Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.

  4. Automatic Parametric Testing Of Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Jennings, Glenn A.; Pina, Cesar A.

    1989-01-01

    Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

  5. Tool For Tinning Integrated-Circuit Leads

    NASA Technical Reports Server (NTRS)

    Prosser, Gregory N.

    1988-01-01

    As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

  6. Integrated-Circuit Broadband Infrared Sources

    NASA Technical Reports Server (NTRS)

    Lamb, G.; Jhabvala, M.; Burgess, A.

    1989-01-01

    Microscopic devices consume less power, run hotter, and are more reliable. Simple, compact, lightweight, rapidly-responding reference sources of broadband infrared radiation made available by integrated-circuit technology. Intended primarily for use in calibration of remote-sensing infrared instruments, devices eventually replace conventional infrared sources. New devices also replace present generation of miniature infrared sources. Self-passivating nature of poly-crystalline silicon adds to reliability of devices. Maximum operating temperature is 1,000 K, and power dissipation is only one-fourth that of prior devices.

  7. 3D packaging for integrated circuit systems

    SciTech Connect

    Chu, D.; Palmer, D.W.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  8. The Very High Speed Integrated Circuit Program

    NASA Astrophysics Data System (ADS)

    Thornton, C. G.

    The DOD's Very High Speed Integrated Circuits (VHSIC) Program was established in order to gain and maintain a lead over adversaries in the military field of high density signal processing microelectronic subsystems. The advantages anticipated for VHSIC systems include order-of-magnitude reductions in signal processor size, weight and power requirements, as well as improvements in system performance capabilities, reliability, logistics support, and radiation hardness. VHSIC will be applied to systems involved in communications, intelligence, surveillance, target acquisition, and missile guidance and control.

  9. Accelerating functional verification of an integrated circuit

    SciTech Connect

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  10. Electro-optical Probing Of Terahertz Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

    1990-01-01

    Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

  11. Electronic circuit for measuring series connected electrochemical cell voltages

    DOEpatents

    Ashtiani, Cyrus N.; Stuart, Thomas A.

    2000-01-01

    An electronic circuit for measuring voltage signals in an energy storage device is disclosed. The electronic circuit includes a plurality of energy storage cells forming the energy storage device. A voltage divider circuit is connected to at least one of the energy storage cells. A current regulating circuit is provided for regulating the current through the voltage divider circuit. A voltage measurement node is associated with the voltage divider circuit for producing a voltage signal which is proportional to the voltage across the energy storage cell.

  12. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    NASA Technical Reports Server (NTRS)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  13. Electronic Components and Circuits for Extreme Temperature Environments

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad; Dickman, John E.; Gerber, Scott

    2003-01-01

    Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with

  14. Technologies for highly parallel optoelectronic integrated circuits

    SciTech Connect

    Lear, K.L.

    1994-10-01

    While summarily reviewing the range of optoelectronic integrated circuits (OEICs), this paper emphasizes technology for highly parallel optical interconnections. Market volume and integration suitability considerations highlight board-to-board interconnects within systems as an initial insertion point for large OEIC production. The large channel count of these intrasystem interconnects necessitates two-dimensional laser transmitter and photoreceiver arrays. Surface normal optoelectronic components are promoted as a basis for OEICs in this application. An example system is discussed that uses vertical cavity surface emitting lasers for optical buses between layers of stacked multichip modules. Another potentially important application for highly parallel OEICs is optical routing or packet switching, and examples of such systems based on smart pixels are presented.

  15. Flexible Microstrip Circuits for Superconducting Electronics

    NASA Technical Reports Server (NTRS)

    Chervenak, James; Mateo, Jennette

    2013-01-01

    Flexible circuits with superconducting wiring atop polyimide thin films are being studied to connect large numbers of wires between stages in cryogenic apparatus with low heat load. The feasibility of a full microstrip process, consisting of two layers of superconducting material separated by a thin dielectric layer on 5 mil (approximately 0.13 mm) Kapton sheets, where manageable residual stress remains in the polyimide film after processing, has been demonstrated. The goal is a 2-mil (approximately 0.051-mm) process using spin-on polyimide to take advantage of the smoother polyimide surface for achieving highquality metal films. Integration of microstrip wiring with this polyimide film may require high-temperature bakes to relax the stress in the polyimide film between metallization steps.

  16. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  17. Monolithic microwave integrated circuit water vapor radiometer

    NASA Technical Reports Server (NTRS)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  18. Test results of a 90 MHZ integrated circuit sixteen channel analog pipeline for SSC detector calorimetry

    SciTech Connect

    Kleinfelder, S.A.; Levi, M.; Milgrome, O.

    1990-10-01

    A sixteen channel analog transient recorder with 128 cells per channel has been fabricated as an integrated circuit and tested at speeds of up to 90 MHz. The circuit uses a switched capacitor array technology to achieve a simultaneous read and write capability and twelve bit dynamic range. The high performance of this part should satisfy the demanding electronics requirements of calorimeter detectors at the SSC. The circuit parameters and test results are presented. 2 refs., 3 figs., 1 tab.

  19. W88 integrated circuit shelf life program

    SciTech Connect

    Soden, J.M.; Anderson, R.E.

    1998-01-01

    The W88 Integrated Circuit Shelf Life Program was created to monitor the long term performance, reliability characteristics, and technological status of representative WR ICs manufactured by the Allied Signal Albuquerque Microelectronics Operation (AMO) and by Harris Semiconductor Custom Integrated Circuits Division. Six types of ICs were used. A total of 272 ICs entered two storage temperature environments. Electrical testing and destructive physical analysis were completed in 1995. During each year of the program, the ICs were electrically tested and samples were selected for destructive physical analysis (DPA). ICs that failed electrical tests or DPA criteria were analyzed. Fifteen electrical failures occurred, with two dominant failure modes: electrical overstress (EOS) damage involving the production test programs and electrostatic discharge (ESD) damage during analysis. Because of the extensive handling required during multi-year programs like this, it is not unusual for EOS and ESD failures to occur even though handling and testing precautions are taken. The clustering of the electrical test failures in a small subset of the test operations supports the conclusion that the test operation itself was responsible for many of the failures and is suspected to be responsible for the others. Analysis of the electrical data for the good ICs found no significant degradation trends caused by the storage environments. Forty-six ICs were selected for DPA with findings primarily in two areas: wire bonding and die processing. The wire bonding and die processing findings are not surprising since these technology conditions had been documented during manufacturing and were determined to present acceptable risk. The current reliability assessment of the W88 stockpile assemblies employing these and related ICs is reinforced by the results of this shelf life program. Data from this program will aid future investigation of 4/3 micron or MNOS IC technology failure modes.

  20. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    PubMed

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-01

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  1. Integrated photo-responsive metal oxide semiconductor circuit

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzban D. (Inventor); Dargo, David R. (Inventor); Lyons, John C. (Inventor)

    1987-01-01

    An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

  2. Advances in integrated photonic circuits for packet-switched interconnection

    NASA Astrophysics Data System (ADS)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  3. Method for analyzing radiation sensitivity of integrated circuits

    NASA Technical Reports Server (NTRS)

    Gauthier, M. K.; Stanley, A. G. (Inventor)

    1979-01-01

    A method for analyzing the radiation sensitivity of an integrated circuit is described to determine the components. The application of a narrow radiation beam to portions of the circuit is considered. The circuit is operated under normal bias conditions during the application of radiation in a dosage that is likely to cause malfunction of at least some transistors, while the circuit is monitored for failure of the irradiated transistor. When a radiation sensitive transistor is found, then the radiation beam is further narrowed and, using a fresh integrated circuit, a very narrow beam is applied to different parts of the transistor, such as its junctions, to locate the points of greatest sensitivity.

  4. Ge/Si Integrated Circuit For Infrared Imaging

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.

    1990-01-01

    Proposed integrated circuit consists of focal-plane array of metal/germanium Schottky-barrier photodetectors on same chip with silicon-based circuits that processes signals from photodetectors. Made compatible with underlying silicon-based circuitry by growing germanium epitaxially on silicon circuit wafers. Metal deposited in ultrahigh vacuum immediately after growth of germanium. Combination of described techniques results in high-resolution infrared-imaging circuits of superior performance.

  5. Energy-efficient neuron, synapse and STDP integrated circuits.

    PubMed

    Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

    2012-06-01

    Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively. PMID:23853146

  6. An application of carbon nanotubes for integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Coiffic, J. C.; Foa Torres, L. E.; Le Poche, H.; Fayolle, M.; Roche, S.; Maitrejean, S.; Roualdes, S.; Ayral, A.

    2008-08-01

    Integrated circuits fabrication is soon reaching strong limitations. Help could come from using carbon nanotubes as conducting wires for interconnects. Although this solution was proposed six years ago, researchers still come up with many obstacles such as localization, low temperature growth on copper, contacting and reproducibility. The integration processes exposed here intend to meet the industrial requirements. Two approaches are then possibly followed. Either using densely packed single wall (SWCNT) (or very tiny multiwall) nanotubes, or filling up the whole interconnect diameter with a single large multiwall (MWCNT) nanotube. In this work, we focus on the integration of multiwall vertical interconnects. Densely packed MWCNTs are grown in via holes by CVD. Alternatively, we have developed a method to obtain a single large nanofibre grown by PECVD (MWCNF) in each via hole. Electrical measurements are performed on CVD and PECVD grown carbon nanotubes. The role of electron-phonon interaction in these devices is also briefly discussed.

  7. Electronic circuit provides automatic level control for liquid nitrogen traps

    NASA Technical Reports Server (NTRS)

    Turvy, R. R.

    1968-01-01

    Electronic circuit, based on the principle of increased thermistor resistance corresponding to decreases in temperature provides an automatic level control for liquid nitrogen cold traps. The electronically controlled apparatus is practically service-free, requiring only occasional reliability checks.

  8. Connector and electronic circuit assembly for improved wet insulation resistance

    DOEpatents

    Reese, Jason A.; Teli, Samar R.; Keenihan, James R.; Langmaid, Joseph A.; Maak, Kevin D.; Mills, Michael E.; Plum, Timothy C.; Ramesh, Narayan

    2016-07-19

    The present invention is premised upon a connector and electronic circuit assembly (130) at least partially encased in a polymeric frame (200). The assembly including at least: a connector housing (230); at least one electrical connector (330); at least one electronic circuit component (430); and at least one barrier element (530).

  9. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  10. Predicting the reliability of electronic circuits.

    SciTech Connect

    Loescher, Douglas H.

    2004-06-01

    Procedures to predict the reliability of electrical circuits are discussed. Three cases are introduced and discussed. In Case 1, an analyst predicts the probability of any failure in the intended relations between circuit inputs and circuit outputs. In Case 2, an analyst predicts the probability that specified unintended outputs would occur. In Case 3, an analyst considers coupling between circuits. Logic models are given for the three cases, and sources of failure probabilities of components are mentioned. Methods of analysis are given, software tools are mentioned, and recommendations for presentation and review of results are discussed.

  11. Hybrid Integration of Graphene Analog and Silicon Complementary Metal-Oxide-Semiconductor Digital Circuits.

    PubMed

    Hong, Seul Ki; Kim, Choong Sun; Hwang, Wan Sik; Cho, Byung Jin

    2016-07-26

    We demonstrate a hybrid integration of a graphene-based analog circuit and a silicon-based digital circuit in order to exploit the strengths of both graphene and silicon devices. This mixed signal circuit integration was achieved using a three-dimensional (3-D) integration technique where a graphene FET multimode phase shifter is fabricated on top of a silicon complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) ring oscillator. The process integration scheme presented here is compatible with the conventional silicon CMOS process, and thus the graphene circuit can successfully be integrated on current semiconductor technology platforms for various applications. This 3-D integration technique allows us to take advantage of graphene's excellent inherent properties and the maturity of current silicon CMOS technology for future electronics. PMID:27403730

  12. GaAs Optoelectronic Integrated-Circuit Neurons

    NASA Technical Reports Server (NTRS)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  13. Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment

    NASA Technical Reports Server (NTRS)

    Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

    1998-01-01

    Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

  14. Securing Health Sensing Using Integrated Circuit Metric

    PubMed Central

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  15. Securing health sensing using integrated circuit metric.

    PubMed

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-10-20

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  16. Mixed signal custom integrated circuit development for physics instrumentation

    SciTech Connect

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S.

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  17. Development of superconducting bonding for multilayer microwave integrated quantum circuits

    NASA Astrophysics Data System (ADS)

    Brecht, Teresa; Axline, Christopher; Chu, Yiwen; Pfaff, Wolfgang; Frunzio, Luigi; Devoret, Michel; Schoelkopf, Robert

    Future quantum computers are likely to take the shape of multilayer microwave integrated quantum circuits. The proposed physical architecture retains the superb coherence of 3D structures while achieving superior scalability and compatibility with planar circuitry and integrated readout electronics. This hardware platform utilizes known techniques of bulk etching in silicon wafers and requires metallic bonding of superconducting materials. Superconducting wafer bonding is a crucial tool in need of development. Whether micromachined in wafers or traditionally machined in bulk metal, 3D cavities typically posses a seam where two parts meet. Ideally, this seam consists of a perfect superconducting bond. Pursuing this goal, we have developed a new understanding of seams as a loss mechanism that is applicable to 3D cavities in general. We present quality factor measurements of both 3D cavities and 2D stripline resonators to study the losses of superconducting bonds.

  18. Fractal Electronic Circuits Assembled From Nanoclusters

    NASA Astrophysics Data System (ADS)

    Fairbanks, M. S.; McCarthy, D.; Taylor, R. P.; Brown, S. A.

    2009-07-01

    Many patterns in nature can be described using fractal geometry. The effect of this fractal character is an array of properties that can include high internal connectivity, high dispersivity, and enhanced surface area to volume ratios. These properties are often desirable in applications and, consequently, fractal geometry is increasingly employed in technologies ranging from antenna to storm barriers. In this paper, we explore the application of fractal geometry to electrical circuits, inspired by the pervasive fractal structure of neurons in the brain. We show that, under appropriate growth conditions, nanoclusters of Sb form into islands on atomically flat substrates via a process close to diffusion-limited aggregation (DLA), establishing fractal islands that will form the basis of our fractal circuits. We perform fractal analysis of the islands to determine the spatial scaling properties (characterized by the fractal dimension, D) of the proposed circuits and demonstrate how varying growth conditions can affect D. We discuss fabrication approaches for establishing electrical contact to the fractal islands. Finally, we present fractal circuit simulations, which show that the fractal character of the circuit translates into novel, non-linear conduction properties determined by the circuit's D value.

  19. Chapter 12: Trapped Electrons as Electrical (Quantum) Circuits

    NASA Astrophysics Data System (ADS)

    Verdú, José

    2014-01-01

    In this chapter, we present a detailed model of the equivalent electric circuit of a single trapped particle in a coplanar-waveguide (CPW) Penning trap. The CPW-trap, which is essentially a section of coplanar-waveguide transmission-line, is designed to make it compatible with circuit-quantum electrodynamic architectures. This will enable a single trapped electron, or geonium atom, as a potential building block of microwave quantum circuits. The model of the trapped electron as an electric circuit was first introduced by Hans Dehmelt in the 1960s. It is essential for the description of the electronic detection using resonant tank circuits. It is also the basis for the description of the interaction of a geonium atom with other distant quantum systems through electrical (microwave) signals.

  20. Fixture aids soldering of electronic components on circuit board

    NASA Technical Reports Server (NTRS)

    Ross, M. H.

    1966-01-01

    Spring clamp fixture holds small electronic components in a desired position while they are being soldered on a circuit board. The spring clamp is clipped on the edge of the circuit board and an adjustable spring-steel boom holds components against the board. The felt pad at the end of the boom is replaced with different attachments for other holding tasks.

  1. Electronic circuit detects left ventricular ejection events in cardiovascular system

    NASA Technical Reports Server (NTRS)

    Gebben, V. D.; Webb, J. A., Jr.

    1972-01-01

    Electronic circuit processes arterial blood pressure waveform to produce discrete signals that coincide with beginning and end of left ventricular ejection. Output signals provide timing signals for computers that monitor cardiovascular systems. Circuit operates reliably for heart rates between 50 and 200 beats per minute.

  2. Basic structures of integrated photonic circuits for smart biosensor applications

    NASA Astrophysics Data System (ADS)

    Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

    2013-05-01

    The breadth of opportunities for applied technologies for optical sensors ranges from environmental and biochemical control, medical diagnostics to process regulation. Thus the specified usage of the optical sensor system requires a particular design and functionalization. Especially biochemical sensors incorporate electronic and photonic devices for the detection of harmful substances e.g. in drinking water. Here we present recent developments in the integration of a Si-based light emitting device (LED) [1-3, 8] into a photonic circuit for an optical waveguide-based biodetection system. This concept includes the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, in the photonic system circuit. First approaches involve simulations of Si3N4/SiO2-waveguides with the finite element method (FEM) and their fabrication by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). In addition, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish a basis for optimized Si-based LED waveguide butt-coupling with adequate coupling efficiency, low attenuation loss and a high optical power throughput.

  3. Investigation of radiation effects on semiconductor devices and integrated circuits

    NASA Astrophysics Data System (ADS)

    Shanfield, Zef; Srour, Joseph R.; Moriwaki, Melvin; Kitazaki, Kerry S.; Hartmann, Robert A.

    1988-09-01

    Results of a study of radiation effects on electronic materials, devices, and integrated circuits are presented in this report. Emphasis was placed on determining the underlying mechanisms responsible for observed radiation effects with a view toward gaining understanding of value in the development of radiation-hardened devices. Measurements and analyses were made of the effects of single energetic neutrons and protons on silicon integrated circuits. In addition, a detailed description is given of the effects of radiation-induced displacement damage on device depletion regions. Single event upset studies included charge collection and transient current measurements on Si and GaAs devices following a single alpha-particle strike. The angular dependence of charge funneling was also investigated. The mechanisms of ionizing radiation effects on Si MOS devices were explored in detail using the thermally stimulated current technique and other measurement approaches. Data obtained by several techniques show that use of the radiation-induced shift of the capacitance-voltage curve at midgap is not generally valid for determining oxide trapped charge.

  4. High performance protection circuit for power electronics applications

    SciTech Connect

    Tudoran, Cristian D. Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  5. High performance protection circuit for power electronics applications

    NASA Astrophysics Data System (ADS)

    Tudoran, Cristian D.; Dǎdârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-01

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a "sensor" or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  6. Computer programs: Electronic circuit design criteria: A compilation

    NASA Technical Reports Server (NTRS)

    1973-01-01

    A Technology Utilization Program for the dissemination of information on technological developments which have potential utility outside the aerospace community is presented. The 21 items reported herein describe programs that are applicable to electronic circuit design procedures.

  7. 35 GHz integrated circuit rectifying antenna with 33 percent efficiency

    NASA Technical Reports Server (NTRS)

    Yoo, T.-W.; Chang, K.

    1991-01-01

    A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

  8. The Effects of Space Radiation on Linear Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Johnston, A.

    2000-01-01

    Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

  9. Stable Polyurethane Coatings for Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Morris, D. E.

    1983-01-01

    Alkane-based polyurethanes resist deterioration while maintaining good dielectric properties. Weight loss after prolonged immersion in hot water far less for alkane-based polyurethanes than for more common ether based polyurethanes, at any given oxygen content. Major uses of polyurethanes are as connector potting materials and conformal coatings for printed circuit boards.

  10. Radiation-hardened transistor and integrated circuit

    DOEpatents

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  11. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  12. Integrated prepulse circuits for efficient excitation of gas lasers

    NASA Technical Reports Server (NTRS)

    Rothe, Dietmar E. (Inventor)

    1990-01-01

    Efficient impedance-matched gas laser excitation circuits integrally employ prepulse power generators. Magnetic switches are employed to both generate the prepulse and switch the prepulse onto the laser electrodes.

  13. Implantable intracranial pressure telemeter using custom integrated circuits

    NASA Astrophysics Data System (ADS)

    Leung, A. M. P.

    1981-10-01

    The design, fabrication, and evaluation of an implantable intracranial pressure (ICP) telemetry transmitter is described. Data transmission is accomplished by means of a radio frequency (RF) link. A silicon piezoresistive pressure transducer is used. Electrostatic bonding of this transducer onto a tubular glass support provides long-term stability, stress isolation and a hermetic package. Pressure baseline stability of better than 2 mm Hg/month has been achieved. Pulse code modulation is employed in the pressure channel to assure accurate data transmission. Low duty cycle pulse powering technique lowers the power consumption of the telemeter to only 0.3 mW. The complexity of the electronics is reduced by the use of a custom integrated circuit (PM2) which is a 40-pin bipolar device measuring 150 mil x 150 mil. It contains 75 NPN transistors, 26 PNP transistors, 45 base resistors (480 K total) and 16 pinch resistors (560 K total). The operating characteristics of the telemeter are described.

  14. Addressable-Matrix Integrated-Circuit Test Structure

    NASA Technical Reports Server (NTRS)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  15. W-band, 20 W microstrip integrated circuit combiner

    NASA Astrophysics Data System (ADS)

    Yen, Y. E.; Hayashibara, G.; Yen, P.; Ngan, Y. C.; Yen, H. C.

    1987-04-01

    A W-band, 20 W, short-pulse microstrip integrated circuit (MIC) power combiner was developed, adopting an integrated circuit design approach in conjunction with a versatile modulator to achieve small size, low cost, and high performance. The combiner consists of two high power IMPATT oscillators and a low-loss ratrace ring hybrid circuit. Using a high power diode in a well-matched circuit, an individual MIC IMPATT oscillator delivered 12.5 W with less than 1.5 dB degradation from rated waveguide power. The insertion loss of the ratrace ring circuit is 0.75 dB. A circulator is not required. Furthermore, well balanced amplitude and phase relationships ensure that the combined power emerges only at the output port. The combiner efficiency exceeds 80 percent. The DC-to-RF conversion efficiency is about 3 percent. The pulsewidth and pulse repetition rate are 40 ns and 80 kHz, respectively.

  16. Digital pixel readout integrated circuit architectures for LWIR

    NASA Astrophysics Data System (ADS)

    Shafique, Atia; Yazici, Melik; Kayahan, Huseyin; Ceylan, Omer; Gurbuz, Yasar

    2015-06-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented. It can achieve extreme charge handling capacity of 2.04Ge- with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed.

  17. Integrated Circuit Failure Analysis Expert System

    1995-10-03

    The software assists a failure analyst performing failure anaysis on intergrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  18. Circuit-level input integration in bacterial gene regulation.

    PubMed

    Espinar, Lorena; Dies, Marta; Cagatay, Tolga; Süel, Gürol M; Garcia-Ojalvo, Jordi

    2013-04-23

    Gene regulatory circuits can receive multiple simultaneous inputs, which can enter the system through different locations. It is thus necessary to establish how these genetic circuits integrate multiple inputs as a function of their relative entry points. Here, we use the dynamic circuit regulating competence for DNA uptake in Bacillus subtilis as a model system to investigate this issue. Specifically, we map the response of single cells in vivo to a combination of (i) a chemical signal controlling the constitutive expression of key competence genes, and (ii) a genetic perturbation in the form of copy number variation of one of these genes, which mimics the level of stress signals sensed by the bacteria. Quantitative time-lapse fluorescence microscopy shows that a variety of dynamical behaviors can be reached by the combination of the two inputs. Additionally, the integration depends strongly on the relative locations where the two perturbations enter the circuit. Specifically, when the two inputs act upon different circuit elements, their integration generates novel dynamical behavior, whereas inputs affecting the same element do not. An in silico bidimensional bifurcation analysis of a mathematical model of the circuit offers good quantitative agreement with the experimental observations, and sheds light on the dynamical mechanisms leading to the different integrated responses exhibited by the gene regulatory circuit.

  19. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, E.I. Jr.

    1996-06-04

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs. 5 figs.

  20. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, Jr., Edward I.

    1996-01-01

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

  1. Microwave GaAs Integrated Circuits On Quartz Substrates

    NASA Technical Reports Server (NTRS)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  2. High density electronic circuit and process for making

    DOEpatents

    Morgan, William P.

    1999-01-01

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

  3. High density electronic circuit and process for making

    DOEpatents

    Morgan, W.P.

    1999-06-29

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

  4. Innovative devices for integrated circuits - A design perspective

    NASA Astrophysics Data System (ADS)

    Schmitt-Landsiedel, D.; Werner, C.

    2009-04-01

    MOS devices go 3D, new quantum effect devices appear in the research labs. This paper discusses the impact of various innovative device architectures on circuit design. Examples of circuits with FinFETs or Multi-Gate-FETs are shown and their performance is compared with classically scaled CMOS circuits both for digital and analog applications. As an example for novel quantum effect devices beyond CMOS we discuss circuits with Tunneling Field Effect Transistors and their combination with classical MOSFETs and MuGFETs. Finally the potential of more substantial paradigm changes in circuit design will be exploited for the example of magnetic quantum cellular automata using a novel integrated magnetic field clocking scheme.

  5. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  6. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  7. Sub-Half Micrometer Gate Lift-Off By Three Layer Resist Process Via Electron Beam Lithography For Gallium Arsenide Monolithic Microwave Integrated Circuits (MIMICs)

    NASA Astrophysics Data System (ADS)

    Nagarajan, Rao M.; Rask, Steven D.; King, Michael R.; Yard, Thomas K.

    1988-06-01

    A three layer resist process for gate lift-oft on Gallium Arsenide MIMICs by electron Dean and optical lithographies are described. The electron beam lithography process consists of Poly (Dimethyl Glutarimide) PMGI as tne planarizing layer, a Plasma Enhanced Chemical Vapour Deposition silicon nitride (SiN) as an intermediate barrier layer and Poly (Methyl methacrylate), PMMA, as the top imaging layer. The PivimA is exposed by Cambridge Electron beam system EBMF 6.4 at 20kev and developed in Methyl Ethyl Ketone/Iso Propyl Alcohol. The pattern is then transferred to the SiN layer by cF4/o2 plasma etcning. The SiN layer is then used as the mask to transfer the pattern to the PMGI layer by 02 kteactive Ion Etching until tne GaAS is exposed. The various processing parameters are optimized to obtain lip or overnang suitable for lift-off with 0.20μm gate dimension. After the GaAS has been recessed (to reduce the parasitic source resistance), a thick 9000Å Ti/Pt/Au gate metal is evaporated and the unwanted gate metal is lifted oft using PMGI stripper. To use the three layer resist process in optical litnograpny, the MG.'. planarizing layer and PECVD SiN layer is used along with optical pnotoresist AZ1450J as a top imaging layer. inc sofcbake, uV exposure dose (436 nm) and development time for AZ145UJ are optimized to obtain 0.5μm to 1.0μm gate dimensions. The etch parameters for the pattern transfer to SiN and tnen to PMGI layers are same as in tne above process. The process levels such as mesa, source/drain, contact and metal levels for GaAs mlivilt,s are defined by UV lithography (Karl Suss contact aligner) using single layer pnotoresist. A nign overlay accuracy is obtained by use of gold metal Dumps as registration marks for aligning tne electron Dean exposed gate to optically exposed source/drain channel. Thus a higher tnrougnput and better linewidtn control are obtained using electron beam/optical lithography tecnniques. This approach is currently used to

  8. Monolithic microwave integrated circuits: Technology and design

    NASA Astrophysics Data System (ADS)

    Goyal, Ravender

    Theoretical and practical aspects of MMIC design are examined in a textbook intended for a senior or graduate engineering laboratory course. The individual chapters are contributed by specialists and cover fundamental MMIC characteristics and applications, the theory of microwave transmission, MMIC material and manufacturing technology, device modeling, amplifier design, nonlinear and control circuits, the TV-receive-only chip as a typical MMIC-based subsystem, design automation tools, on-wafer testing, MMIC packaging, and MMIC reliability. Extensive diagrams, drawings, graphs, photographs, and tables of numerical data are provided.

  9. Simulation of proton-induced energy deposition in integrated circuits

    NASA Technical Reports Server (NTRS)

    Fernald, Kenneth W.; Kerns, Sherra E.

    1988-01-01

    A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

  10. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    PubMed

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

  11. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    PubMed Central

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  12. Direct Desktop Printed-Circuits-on-Paper Flexible Electronics

    PubMed Central

    Zheng, Yi; He, Zhizhu; Gao, Yunxia; Liu, Jing

    2013-01-01

    There currently lacks of a way to directly write out electronics, just like printing pictures on paper by an office printer. Here we show a desktop printing of flexible circuits on paper via developing liquid metal ink and related working mechanisms. Through modifying adhesion of the ink, overcoming its high surface tension by dispensing machine and designing a brush like porous pinhead for printing alloy and identifying matched substrate materials among different papers, the slightly oxidized alloy ink was demonstrated to be flexibly printed on coated paper, which could compose various functional electronics and the concept of Printed-Circuits-on-Paper was thus presented. Further, RTV silicone rubber was adopted as isolating inks and packaging material to guarantee the functional stability of the circuit, which suggests an approach for printing 3D hybrid electro-mechanical device. The present work paved the way for a low cost and easygoing method in directly printing paper electronics.

  13. Direct Desktop Printed-Circuits-on-Paper Flexible Electronics

    NASA Astrophysics Data System (ADS)

    Zheng, Yi; He, Zhizhu; Gao, Yunxia; Liu, Jing

    2013-05-01

    There currently lacks of a way to directly write out electronics, just like printing pictures on paper by an office printer. Here we show a desktop printing of flexible circuits on paper via developing liquid metal ink and related working mechanisms. Through modifying adhesion of the ink, overcoming its high surface tension by dispensing machine and designing a brush like porous pinhead for printing alloy and identifying matched substrate materials among different papers, the slightly oxidized alloy ink was demonstrated to be flexibly printed on coated paper, which could compose various functional electronics and the concept of Printed-Circuits-on-Paper was thus presented. Further, RTV silicone rubber was adopted as isolating inks and packaging material to guarantee the functional stability of the circuit, which suggests an approach for printing 3D hybrid electro-mechanical device. The present work paved the way for a low cost and easygoing method in directly printing paper electronics.

  14. Integrated circuit narrowband dielectric filters for D-band

    NASA Astrophysics Data System (ADS)

    Morgan, G. B.; Singh, D.

    1987-06-01

    Dielectrics offer the highest Q-factor for integrated circuit resonators. In the D-band, low-order modes, with higher Q than the fundamental, are worthwhile, despite mode competition and slightly increased area. A 2-pole bandpass filter with a bandwidth of about 1.5 percent at 127 GHz is described. Insertion loss and return loss data are presented. Mode resonances and circuit substrates are also discussed.

  15. Development of integrated thermionic circuits for high-temperature applications

    NASA Technical Reports Server (NTRS)

    Mccormick, J. B.; Wilde, D.; Depp, S.; Hamilton, D. J.; Kerwin, W.; Derouin, C.; Roybal, L.; Wooley, R.

    1981-01-01

    Integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 C are studied. A set of practical design and performance equations is demonstrated. Experimental results are discussed in which both devices and simple circuits were successfully operated in 5000 C environments for extended periods. It is suggested that ITC's may become an important technology for high temperature instrumentation and control systems in geothermal and other high temperature environments.

  16. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  17. Development of integrated thermionic circuits for high-temperature applications

    SciTech Connect

    McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.

    1981-01-01

    This report describes a class of microminiature, thin film devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500/sup 0/C. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time (greater than 11,000 hours).

  18. Development of thermionic integrated circuits for applications in hostile environments

    SciTech Connect

    McCormik, J.B.; Lynn, D.K.; Wilde, D.; Cowan, R.; Hamilton, D.J.; Kerwin, W.; Dooley, R.

    1984-04-10

    This report describes a class of devices known as thermionic integrated circuits (TICs) that are capable of extended operation in ambient temperatures up to 500/sup 0/C and in high radiation environments. The evolution of the TIC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500/sup 0/C environments for extended periods of time.

  19. Single Event Transients in Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  20. Development of wide range charge integration application specified integrated circuit for photo-sensor

    NASA Astrophysics Data System (ADS)

    Katayose, Yusaku; Ikeda, Hirokazu; Tanaka, Manobu; Shibata, Makio

    2013-01-01

    A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10-4 fC/pF.

  1. Fuzzy classifier for fault diagnosis in analog electronic circuits.

    PubMed

    Kumar, Ashwani; Singh, A P

    2013-11-01

    Many studies have presented different approaches for the fault diagnosis with fault models having ± 50% variation in the component values in analog electronic circuits. There is still a need of the approaches which provide the fault diagnosis with the variation in the component value below ± 50%. A new single and multiple fault diagnosis technique for soft faults in analog electronic circuit using fuzzy classifier has been proposed in this paper. This technique uses the simulation before test (SBT) approach by analyzing the frequency response of the analog circuit under faulty and fault free conditions. Three signature parameters peak gain, frequency and phase associated with peak gain, of the frequency response of the analog circuit are observed and extracted such that they give unique values for faulty and fault free configuration of the circuit. The single and double fault models with the component variations from ± 10% to ± 50% are considered. The fuzzy classifier along the classification of faults gives the estimated component value under faulty and faultfree conditions. The proposed method is validated using simulated data and the real time data for a benchmark analog circuit. The comparative analysis is also presented for both the validations.

  2. Pseudo-fermions in an Electronic Loss-Gain Circuit

    NASA Astrophysics Data System (ADS)

    Bagarello, F.; Pantano, G.

    2013-12-01

    In some recent papers a loss-gain electronic circuit has been introduced and analyzed within the context of PT-quantum mechanics. In this paper we show that this circuit can be analyzed using the formalism of the so-called pseudo-fermions. In particular we discuss the time behavior of the circuit, and we construct two biorthogonal bases associated to the Liouville matrix used in the treatment of the dynamics. We relate these bases to and , and we also show that a self-adjoint Liouville-like operator could be introduced in the game. Finally, we describe the time evolution of the circuit in an Heisenberg-like representation, driven by a non self-adjoint Hamiltonian.

  3. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  4. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    NASA Technical Reports Server (NTRS)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  5. Circulators for microwave and millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Schloemann, Ernst F.

    1988-02-01

    The requirements for circulators for use in combination with microwave and millimeter-wave integrated circuits are reviewed, with special emphasis on modules for phased-array antennas. Recent advances in broadbanding and in miniaturization are summarized. Novel types of circulators that are fabricated by attaching a ferrite disc and a suitable coupling structure to the surface of a dielectric or semiconductor substrate ('quasi-monolithic' integration) are described. Methods for achieving complete monolithic integration are also discussed.

  6. Control of electrostatic damage to electronic circuits

    SciTech Connect

    Kirk, W.J. Jr.

    1980-03-01

    Static is caused by the flow of materials and people within an environment. The static voltages generated by these movements can degrade or destroy many solid state devices currently being used in sophisticated electronic equipment. Discharge of static voltages through these sensitive devices during assembly operations can lead to a nonfunctional assembly fabricated from parts which previously were acceptable or to later failure of an assembly which was functional after fabrication. Sources of electrostatic charges, equipment and methods for minimizing the generation of electrostatic voltages during the production, assembly and packaging of solid state electronic equipment, and the sensitivity of solid state devices to electrostatic damage are discussed. It is concluded that static awareness is the key to an effective electrostatic damage (ESD) control program, and that production facilities must incorporate electrostatic protection facilities, materials, and processes so that workers can concentrate on producing a high-quality product without having to be overly concerned about ESD procedures. (LCL)

  7. The Induction of Chaos in Electronic Circuits Final Report-October 1, 2001

    SciTech Connect

    R.M.Wheat, Jr.

    2003-04-01

    This project, now known by the name ''Chaos in Electronic Circuits,'' was originally tasked as a two-year project to examine various ''fault'' or ''non-normal'' operational states of common electronic circuits with some focus on determining the feasibility of exploiting these states. Efforts over the two-year duration of this project have been dominated by the study of the chaotic behavior of electronic circuits. These efforts have included setting up laboratory space and hardware for conducting laboratory tests and experiments, acquiring and developing computer simulation and analysis capabilities, conducting literature surveys, developing test circuitry and computer models to exercise and test our capabilities, and experimenting with and studying the use of RF injection as a means of inducing chaotic behavior in electronics. An extensive array of nonlinear time series analysis tools have been developed and integrated into a package named ''After Acquisition'' (AA), including capabilities such as Delayed Coordinate Embedding Mapping (DCEM), Time Resolved (3-D) Fourier Transform, and several other phase space re-creation methods. Many computer models have been developed for Spice and for the ATP (Alternative Transients Program), modeling the several working circuits that have been developed for use in the laboratory. And finally, methods of induction of chaos in electronic circuits have been explored.

  8. Thermally-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  9. Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

    NASA Astrophysics Data System (ADS)

    Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

    2015-03-01

    This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

  10. Integrated Circuit Chip Improves Network Efficiency

    NASA Technical Reports Server (NTRS)

    2008-01-01

    Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating

  11. Shape determination and placement algorithms for hierarchical integrated circuit layout

    NASA Astrophysics Data System (ADS)

    Slutz, E. A.

    Algorithms for the automatic layout of integrated circuits are presented. The algorithms use a hierarchical decomposition of the circuit structure. Since this reduces the complexity of the design, it is an aid to the designer as well as the means of making possible the automated approach to layout. The layout method consists of two phases: a top-down phase during which the shapes of the components at each level are determined, followed by a bottomup phase where a final placement and routing for each level is computed. The data structure used to model the chip surface is central to the algorithms. This data structure is presented along with the alternative structures. Four basic operations of adding components, deleting components, sizing, and building the structure for a given placement are described. A file format for capturing integrated circuit design information is also described.

  12. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  13. Multimode waveguide components for millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Bhooshan, S.; Mittra, R.

    1980-01-01

    In this paper, we report the results of an investigation of multimode, planar dielectric waveguides for integrated circuit application at millimeter wavelengths. Two multimode devices have been fabricated and tested using the inverted strip guide (ISG), and a comparison between the theoretical and experimental results is given.

  14. An integrated circuit/packet switched videoconferencing system

    SciTech Connect

    Kippenhan, H.A. Jr.; Lidinsky, W.P.; Roediger, G.A.; Watts, T.A.

    1995-11-01

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible videoconferencing system for use by high energy physics collaborations and others wishing to use videoconferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of videoconferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEP`s needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Videoconferencing Using PAckets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched videoconferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet videoconferencing interface. Augmentation is centered in another subsystem called MSB (Multiport multisession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system.

  15. Performance of digital integrated circuit technologies at very high temperatures

    SciTech Connect

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  16. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    DOEpatents

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  17. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1988-04-20

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

  18. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1989-09-12

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  19. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, David R.

    1989-01-01

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  20. Life cycle cost model for very high speed integrated circuits

    NASA Astrophysics Data System (ADS)

    Long, E. A.

    1984-09-01

    The Very High Speed Integrated Circuit (VHSIC) technology program is forecast to have a profound impact on performance, reliability, and cost of future avionics systems. An important question is: how do VHSIC design fabrication and support concepts impact life cycle cost (LCC) of a host system? To answer this question, an insertion model representative of future avionics systems is selected and LCCs are obtained for various chip designs and layout configurations which implement this model. This thesis then examines five factors affecting VHSIC chips with respect to LCC of a digital synthetic aperture radar processor. These factors are: (1) chip technology and design; (2) fabrication yields; (3) substrate type; (4) the degree to which computer-aided-design (CAD) methods are used; and (5) maintenance level. Of these factors, the greatest impact to LCC is chip fabrication yields. The least effect on LCC is the degree to which CAD methods are used. The remaining factors fall between these two. Originator-supplied keywords include: semiconductors, microcircuits and Chips(Electronics).

  1. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  2. Flexible circuits with integrated switches for robotic shape sensing

    NASA Astrophysics Data System (ADS)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  3. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    NASA Technical Reports Server (NTRS)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  4. Modeling of single-event upset in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  5. Quantum dot rolled-up microtube optoelectronic integrated circuit.

    PubMed

    Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

    2013-05-15

    A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively.

  6. Fast symbolic layout translocation for custom VLSI integrated circuits

    SciTech Connect

    Eichenberger, P.A.

    1986-01-01

    Symbolic layout tools have enormous potential for easing the task of custom integrated circuit layout by allowing the designer to work at a higher level of abstraction, hiding some of the complexity of full custom design. Unfortunately, the practicality of symbolic layout tools has been limited for several reasons. Most important, the CPU resources required to compute a full-size integrated circuit from a symbolic description are prohibitively large; this problem has been avoided either by restricting the range of applicability to a narrow class of integrated circuits, or by using a simpler translation algorithm, which reduces the quality of the output. Other problems include: producing poor quality layouts, insufficient user control of the generated output, and inability to cooperate with other layout tools. These problems make symbolic design of complete chips difficult. This thesis presents an approach to the symbolic layout problems that produces high-quality layout for an arbitrary circuit without requiring excessive CPU time. The key to this approach includes the use of hierarchy to improve CPU time, the use of wire-length minimization to improve quality, a good balance between optimization of the layout and optimization of CPU time, and a smooth transition over varying degrees of automation. The result has been a symbolic layout tool that has been successfully used to lay out several chips from a design-rule-independent input.

  7. Conductus makes high-T sub c integrated circuit

    SciTech Connect

    Not Available

    1991-01-01

    This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step.

  8. Highly integrated electronics for the star TPC

    SciTech Connect

    Arthur, A.A.; Bieser, F.; Hearn, W.; Kleinfelder, S.; Merrick, T.; Millaud, J.; Noggle, T.; Rai, G.; Ritter, H.G.; Wieman, H.

    1991-12-31

    The concept for the STAR TPC front-end electronics is presented and the progress toward the development of a fully integrated solution is described. It is the goal of the R+D program to develop the complete electronics chain for the STAR central TPC detector at RHIC. It is obvious that solutions chosen e.g. for ALEPH are not adequate for the 150000 channels that need to be instrumented for readout. It will be necessary to perform all the signal processing, digitization and multiplexing directly on the detector in order to reduce per channel cost and the amount of cabling necessary to read out the information. We follow the approach chosen by the EOS TPC project, where the readout electronics on the detector consists of an integrated preamplifier, a hybrid shaping amplifier, an integrated switched capacitor array and a highly multiplexed ADC. The STAR electronics will be further integrated so that approximately 16 channels of the preamplifier, the shaper, the analog store and the ADC will be contained in two integrated circuits located directly on the pad plane.

  9. Millimeter-wave and terahertz integrated circuit antennas

    NASA Astrophysics Data System (ADS)

    Rebeiz, Gabriel M.

    1992-11-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  10. Millimeter-wave and terahertz integrated circuit antennas

    NASA Technical Reports Server (NTRS)

    Rebeiz, Gabriel M.

    1992-01-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  11. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    SciTech Connect

    Arefin, Md Shamsul Redoute, Jean-Michel; Rasit Yuce, Mehmet; Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  12. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  13. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, Anthony F.; Malba, Vincent

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  14. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  15. Full Wave Simulation of Integrated Circuits Using Hybrid Numerical Methods

    NASA Astrophysics Data System (ADS)

    Tan, Jilin

    Transmission lines play an important role in digital electronics, and in microwave and millimeter-wave circuits. Analysis, modeling, and design of transmission lines are critical to the development of the circuitry in the chip, subsystem, and system levels. In the past several decays, at the EM modeling level, the quasi-static approximation has been widely used due to its great simplicity. As the clock rates increase, the inter-connect effects such as signal delay, distortion, dispersion, reflection, and crosstalk, limit the performance of microwave systems. Meanwhile, the quasi-static approach loses its validity for some complex system structures. Since the successful system design of the PCB, MCM, and the chip packaging, rely very much on the computer aided EM level modeling and simulation, many new methods have been developed, such as the full wave approach, to guarantee the successful design. Many difficulties exist in the rigorous EM level analysis. Some of these include the difficulties in describing the behavior of the conductors with finite thickness and finite conductivity, the field singularity, and the arbitrary multilayered multi-transmission lines structures. This dissertation concentrates on the full wave study of the multi-conductor transmission lines with finite conductivity and finite thickness buried in an arbitrary lossy multilayered environment. Two general approaches have been developed. The first one is the integral equation method in which the dyadic Green's function for arbitrary layered media has been correctly formulated and has been tested both analytically and numerically. By applying this method, the double layered high dielectric permitivitty problem and the heavy dielectrical lossy problem in multilayered media in the CMOS circuit design have been solved. The second approach is the edge element method. In this study, the correct functional for the two dimensional propagation problem has been successfully constructed in a rigorous way

  16. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-06

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... United States after importation of certain semiconductor integrated circuits using tungsten...

  17. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  18. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  19. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  20. Curvilinear electronics formed using silicon membrane circuits and elastomeric transfer elements.

    PubMed

    Ko, Heung Cho; Shin, Gunchul; Wang, Shuodao; Stoykovich, Mark P; Lee, Jeong Won; Kim, Dong-Hun; Ha, Jeong Sook; Huang, Yonggang; Hwang, Keh-Chih; Rogers, John A

    2009-12-01

    Materials and methods to achieve electronics intimately integrated on the surfaces of substrates with complex, curvilinear shapes are described. The approach exploits silicon membranes in circuit mesh structures that can be deformed in controlled ways using thin, elastomeric films. Experimental and theoretical studies of the micromechanics of such curvilinear electronics demonstrate the underlying concepts. Electrical measurements illustrate the high yields that can be obtained. The results represent significant experimental and theoretical advances over recently reported concepts for creating hemispherical photodetectors in electronic eye cameras and for using printable silicon nanoribbons/membranes in flexible electronics. The results might provide practical routes to the integration of high performance electronics with biological tissues and other systems of interest for new applications.

  1. Extended life testing evaluation of complementary MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Brosnan, T. E.

    1972-01-01

    The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

  2. Image guide couplers used in millimeter wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Qi, Lanfen; Xu, Liqun; Luo, Ye

    1988-12-01

    The odd-even mode principle and the effective dielectric constant method are used to explore the dispersion and coupling characteristics of coupled image guides. The design for an image guide directional coupler is discussed. It is suggested that 3-dB and 10-dB couplers in Ka band can be used to provide millimeter wave integrated circuits with flat coupling, mechanical stability, and low losses.

  3. Aperture efficiency of integrated-circuit horn antennas

    NASA Technical Reports Server (NTRS)

    Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

    1991-01-01

    The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

  4. Monolithic microwave integrated circuit technology for advanced space communication

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Romanofsky, Robert R.

    1988-01-01

    Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

  5. A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

    NASA Astrophysics Data System (ADS)

    Smith, Michael John Sebastian

    Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

  6. Controlling Photons, Qubits and their Interactions in Superconducting Electronic Circuits

    NASA Astrophysics Data System (ADS)

    Wallraff, Andreas

    2009-03-01

    A combination of ideas from atomic physics, quantum optics and solid state physics allows us to investigate the fundamental interaction of matter and light on the level of single quanta in electronic circuits. In an approach known as circuit quantum electrodynamics, we coherently couple individual photons stored in a high quality microwave frequency resonator to a fully controllable superconducting two-level system (qubit) realized in a macroscopic electronic circuit [1]. In particular, we have recently observed the simultaneous interaction of one, two and three photons with a single qubit. In these experiments, we have probed the quantum nonlinearity of the qubit/light interaction governed by the Jaynes-Cummings hamiltonian, clearly demonstrating the quantization of the radiation field in the on-chip cavity. We have also performed quantum optics experiments with no photons at all. In this situation, i.e. in pure vacuum, we have resolved the renormalization of the qubit transition frequency - known as the Lamb shift - due to its non-resonant interaction with the cavity vacuum fluctuations [3].[4pt] [1] A. Wallraff et al., Nature (London) 431, 162 (2004)[0pt] [2] J. Fink et al., Nature (London) 454, 315 (2008)[0pt] [3] A. Fragner et al., Science 322, 1357 (2008)

  7. Serpentine and corduroy circuits to enhance the stretchablity of a stretchable electronic device

    SciTech Connect

    Maghribi, Mariam N.; Krulevitch, Peter A.; Wilson, Thomas S.; Hamilton, Julie K.; Park, Christina

    2011-01-18

    A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.

  8. Serpentine and corduroy circuits to enhance the stretchability of a stretchable electronic device

    SciTech Connect

    Maghribi, Mariam N.; Krulevitch, Peter A.; Wilson, Thomas S.; Hamilton, Julie K. , Park; Christina

    2007-09-04

    A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.

  9. Photonic-integrated circuit for continuous-wave THz generation.

    PubMed

    Theurer, Michael; Göbel, Thorsten; Stanze, Dennis; Troppenz, Ute; Soares, Francisco; Grote, Norbert; Schell, Martin

    2013-10-01

    We demonstrate a photonic-integrated circuit for continuous-wave (cw) terahertz (THz) generation. By comprising two lasers and an optical phase modulator on a single chip, the full control of the THz signal is enabled via a unique bidirectional operation technique. Integrated heaters allow for continuous tuning of the THz frequency over 570 GHz. Applied to a coherent cw THz photomixing system operated at 1.5 μm optical wavelength, we reach a signal-to-noise ratio of 44 dB at 1.25 THz, which is identical to the performance of a standard system based on discrete components.

  10. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    SciTech Connect

    Rath, P.; Ummethala, S.; Pernice, W. H. P.; Diewald, S.; Lewes-Malandrakis, G.; Brink, D.; Heidrich, N.; Nebel, C.

    2014-12-22

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions.

  11. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    PubMed

    Hall, Trevor J; Hasan, Mehedi

    2016-04-01

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  12. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    PubMed

    Hall, Trevor J; Hasan, Mehedi

    2016-04-01

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical. PMID:27137048

  13. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    PubMed Central

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-01-01

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

  14. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    PubMed

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-01-01

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

  15. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    PubMed

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-06-18

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  16. Design and status of the RF-digitizer integrated circuit

    NASA Technical Reports Server (NTRS)

    Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

    1991-01-01

    An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

  17. Integrating anatomy and function for zebrafish circuit analysis.

    PubMed

    Arrenberg, Aristides B; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function.

  18. Integrating anatomy and function for zebrafish circuit analysis

    PubMed Central

    Arrenberg, Aristides B.; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties—e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function. PMID:23630469

  19. InP-based three-dimensional photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  20. Ultraviolet illumination thermoreflectance for the temperature mapping of integrated circuits.

    PubMed

    Tessier, Gilles; Holé, Stéphane; Fournier, Danièle

    2003-06-01

    Noncontact optical methods such as thermoreflectance, which measure temperature-induced optical reflectivity changes, are particularly suitable for obtaining high-resolution temperature mappings on integrated circuits. Unfortunately, the coefficient linking the variations of temperature and reflectivity depends on the nature of the material and can be modified when optical interferences occur in the Si3N4-based encapsulation layers protecting the circuits. We show that taking advantage of the deep UV absorption of encapsulation layers yields temperature mapping that is independent of the underlying materials. A single calibration is therefore enough to yield the temperature on any point of the uniform and thermally thin encapsulation layer. This simplification and its potential for high resolution should make UV thermoreflectance more attractive to the semiconductor industry.

  1. Mnemonic Functions for Nonlinear Dendritic Integration in Hippocampal Pyramidal Circuits.

    PubMed

    Kaifosh, Patrick; Losonczy, Attila

    2016-05-01

    We present a model for neural circuit mechanisms underlying hippocampal memory. Central to this model are nonlinear interactions between anatomically and functionally segregated inputs onto dendrites of pyramidal cells in hippocampal areas CA3 and CA1. We study the consequences of such interactions using model neurons in which somatic burst-firing and synaptic plasticity are controlled by conjunctive processing of these separately integrated input pathways. We find that nonlinear dendritic input processing enhances the model's capacity to store and retrieve large numbers of similar memories. During memory encoding, CA3 stores heavily decorrelated engrams to prevent interference between similar memories, while CA1 pairs these engrams with information-rich memory representations that will later provide meaningful output signals during memory recall. While maintaining mathematical tractability, this model brings theoretical study of memory operations closer to the hippocampal circuit's anatomical and physiological properties, thus providing a framework for future experimental and theoretical study of hippocampal function. PMID:27146266

  2. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

    2000-01-01

    We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

  3. Tomonaga–Luttinger physics in electronic quantum circuits

    PubMed Central

    Jezouin, S.; Albert, M.; Parmentier, F. D.; Anthore, A.; Gennser, U.; Cavanna, A.; Safi, I.; Pierre, F.

    2013-01-01

    In one-dimensional conductors, interactions result in correlated electronic systems. At low energy, a hallmark signature of the so-called Tomonaga–Luttinger liquids is the universal conductance curve predicted in presence of an impurity. A seemingly different topic is the quantum laws of electricity, when distinct quantum conductors are assembled in a circuit. In particular, the conductances are suppressed at low energy, a phenomenon called dynamical Coulomb blockade. Here we investigate the conductance of mesoscopic circuits constituted by a short single-channel quantum conductor in series with a resistance, and demonstrate a proposed link to Tomonaga–Luttinger physics. We reformulate and establish experimentally a recently derived phenomenological expression for the conductance using a wide range of circuits, including carbon nanotube data obtained elsewhere. By confronting both conductance data and phenomenological expression with the universal Tomonaga–Luttinger conductance curve, we demonstrate experimentally the predicted mapping between dynamical Coulomb blockade and the transport across a Tomonaga–Luttinger liquid with an impurity. PMID:23653214

  4. Tomonaga-Luttinger physics in electronic quantum circuits.

    PubMed

    Jezouin, S; Albert, M; Parmentier, F D; Anthore, A; Gennser, U; Cavanna, A; Safi, I; Pierre, F

    2013-01-01

    In one-dimensional conductors, interactions result in correlated electronic systems. At low energy, a hallmark signature of the so-called Tomonaga-Luttinger liquids is the universal conductance curve predicted in presence of an impurity. A seemingly different topic is the quantum laws of electricity, when distinct quantum conductors are assembled in a circuit. In particular, the conductances are suppressed at low energy, a phenomenon called dynamical Coulomb blockade. Here we investigate the conductance of mesoscopic circuits constituted by a short single-channel quantum conductor in series with a resistance, and demonstrate a proposed link to Tomonaga-Luttinger physics. We reformulate and establish experimentally a recently derived phenomenological expression for the conductance using a wide range of circuits, including carbon nanotube data obtained elsewhere. By confronting both conductance data and phenomenological expression with the universal Tomonaga-Luttinger conductance curve, we demonstrate experimentally the predicted mapping between dynamical Coulomb blockade and the transport across a Tomonaga-Luttinger liquid with an impurity.

  5. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    PubMed Central

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

  6. Implantable neurotechnologies: a review of integrated circuit neural amplifiers

    PubMed Central

    Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

  7. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    PubMed

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  8. Scalability issues in evolutionary synthesis of electronic circuits: lessons learned and challenges ahead

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.

    2003-01-01

    This paper describes scalability issues of evolutionary-driven automatic synthesis of electronic circuits. The article begins by reviewing the concepts of circuit evolution and discussing the limitations of this technique when trying to achieve more complex systems.

  9. SiGe/Si Monolithically Integrated Amplifier Circuits

    NASA Technical Reports Server (NTRS)

    Katehi, Linda P. B.; Bhattacharya, Pallab

    1998-01-01

    With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

  10. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    1995-01-01

    An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

  11. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, E.I. Jr.; Soden, J.M.

    1995-07-04

    An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

  12. Universal nondestructive mm-wave integrated circuit test fixture

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert R. (Inventor); Shalkhauser, Kurt A. (Inventor)

    1990-01-01

    Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

  13. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

    1997-01-01

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

  14. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  15. Cycles of self-pulsations in a photonic integrated circuit.

    PubMed

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  16. Stainless Steel NaK Circuit Integration and Fill Submission

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

  17. Mechanical Designs for Inorganic Stretchable Circuits in Soft Electronics

    PubMed Central

    Wang, Shuodao; Huang, Yonggang; Rogers, John A.

    2016-01-01

    Mechanical concepts and designs in inorganic circuits for different levels of stretchability are reviewed in this paper, through discussions of the underlying mechanics and material theories, fabrication procedures for the constituent microscale/nanoscale devices, and experimental characterization. All of the designs reported here adopt heterogeneous structures of rigid and brittle inorganic materials on soft and elastic elastomeric substrates, with mechanical design layouts that isolate large deformations to the elastomer, thereby avoiding potentially destructive plastic strains in the brittle materials. The overall stiffnesses of the electronics, their stretchability, and curvilinear shapes can be designed to match the mechanical properties of biological tissues. The result is a class of soft stretchable electronic systems that are compatible with traditional high-performance inorganic semiconductor technologies. These systems afford promising options for applications in portable biomedical and health-monitoring devices. Mechanics theories and modeling play a key role in understanding the underlining physics and optimization of these systems. PMID:27668126

  18. Mechanical Designs for Inorganic Stretchable Circuits in Soft Electronics

    PubMed Central

    Wang, Shuodao; Huang, Yonggang; Rogers, John A.

    2016-01-01

    Mechanical concepts and designs in inorganic circuits for different levels of stretchability are reviewed in this paper, through discussions of the underlying mechanics and material theories, fabrication procedures for the constituent microscale/nanoscale devices, and experimental characterization. All of the designs reported here adopt heterogeneous structures of rigid and brittle inorganic materials on soft and elastic elastomeric substrates, with mechanical design layouts that isolate large deformations to the elastomer, thereby avoiding potentially destructive plastic strains in the brittle materials. The overall stiffnesses of the electronics, their stretchability, and curvilinear shapes can be designed to match the mechanical properties of biological tissues. The result is a class of soft stretchable electronic systems that are compatible with traditional high-performance inorganic semiconductor technologies. These systems afford promising options for applications in portable biomedical and health-monitoring devices. Mechanics theories and modeling play a key role in understanding the underlining physics and optimization of these systems.

  19. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  20. Heavy-ion induced single-event upset in integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1991-01-01

    The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

  1. Electron tunneling infrared sensor module with integrated control circuitry

    NASA Technical Reports Server (NTRS)

    Boyadzhyan-Sevak, Vardkes V. (Inventor)

    2001-01-01

    In an integrated electron tunneling sensor, an automatic tunneling control circuit varies a high voltage bias applied to the sensor deflection electrode in response to changes in sensor output to maintain the proper gap between the sensor tip and membrane. The control circuit ensures stable tunneling activity in the presence of large signals and other disturbances to the sensor. Output signals from the module may be derived from the amplified sensor output. The integrated sensor module is particularly well adapted for use in blood glucose measurement and monitoring system.

  2. Compact electronic soma and synapse circuits fabricated using a low temperature approach

    NASA Astrophysics Data System (ADS)

    Subramaniam, Anand

    Digital circuits using the von Neumann architecture and complementary metal-oxide-semiconductor (CMOS) electronic devices dominate large-scale processing systems today and are extremely efficient at performing well-defined operations. However, these systems are less efficient at tasks which involve processing large amounts of imprecise information originating from the surrounding environment, such as pattern recognition and outcome prediction. The human brain is the best processor of such information sets, and consists of a large number of primitive elements (1010 neurons and 1014 synapses). Neuromorphic systems are a class of circuits that draw inspiration from the extremely parallel architecture of the brain. A major goal is thus to develop neuromorphic circuits using a large-area, low-power, and highly dense approach. The major focus of this work is the fabrication of a compact circuit which can implement a biologically realistic synaptic learning rule using low-temperature materials. Ambipolar nanocrystalline-silicon (nc-Si) thin-film transistors (TFTs) are selected as basic building blocks of spiking soma circuits. These TFTs are fabricated at the nanoscale using a CMOS-compatible fabrication process at a maximum temperature of 250 °C. High-κ gate dielectrics are incorporated to achieve lower subthreshold swings and threshold voltages. Soma circuits which consist of a few nc-Si TFTs and capacitors are fabricated and shown to display spiking behavior similar to biological neurons. Electronic synapses are fabricated using Au nanoparticle (NP) memory devices based on nc-Si TFTs and TiN/HfO2/TiN memristors. These are then integrated with the soma circuit to achieve an action potential pair-based learning rule, namely spike-timing-dependent plasticity (STDP). The STDP rule is experimentally demonstrated for the first time using simple rectangular voltage pulses alone. The soma circuits are shown to be capable of driving a significant number of synapses in a large

  3. Electron flux and microbial community in microbial fuel cells (open-circuit and closed-circuit modes) and fermentation.

    PubMed

    Yu, Jaecheul; Park, Youghyun; Lee, Taeho

    2015-07-01

    A closed-circuit microbial fuel cell (C-MFC) was operated to investigate the electron flux under fed-batch mode, and the results were compared to those of open-circuit MFC (O-MFC) and a fermentation reactor (F-reactor). The current was the largest electron sink (52.7% of influent SCOD) in C-MFC, whereas biomass and methane gas were the most significant electron sinks in O-MFC and F-reactor. Interestingly, some of the unknown sink may have accumulated in the electrode of O-MFC. Principal component analysis based on gradient gel electrophoresis profiles showed that the microbial communities were significantly affected by the growth conditions and the presence of electrode, regardless of the circuit connection. Therefore, the electrode and circuit mode might help to control the amount of biomass and enhance the MFC performance.

  4. Electronics. Module 4: Circuit Construction Techniques. Instructor's Guide.

    ERIC Educational Resources Information Center

    Slack, Don

    This guide contains instructor's materials for a three-unit secondary school course on circuit construction techniques. The units are breadboarding circuits, solder/desolder circuits, and printed circuit board repair. The document begins with advice on its use and a cross-referenced table of instructional materials that show which materials in the…

  5. Integrated circuit amplifiers for multi-electrode intracortical recording.

    PubMed

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  6. Development of optical packet and circuit integrated ring network testbed.

    PubMed

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated.

  7. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    NASA Astrophysics Data System (ADS)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  8. Data Mining Approaches for Modeling Complex Electronic Circuit Design Activities

    SciTech Connect

    Kwon, Yongjin; Omitaomu, Olufemi A; Wang, Gi-Nam

    2008-01-01

    A printed circuit board (PCB) is an essential part of modern electronic circuits. It is made of a flat panel of insulating materials with patterned copper foils that act as electric pathways for various components such as ICs, diodes, capacitors, resistors, and coils. The size of PCBs has been shrinking over the years, while the number of components mounted on these boards has increased considerably. This trend makes the design and fabrication of PCBs ever more difficult. At the beginning of design cycles, it is important to estimate the time to complete the steps required accurately, based on many factors such as the required parts, approximate board size and shape, and a rough sketch of schematics. Current approach uses multiple linear regression (MLR) technique for time and cost estimations. However, the need for accurate predictive models continues to grow as the technology becomes more advanced. In this paper, we analyze a large volume of historical PCB design data, extract some important variables, and develop predictive models based on the extracted variables using a data mining approach. The data mining approach uses an adaptive support vector regression (ASVR) technique; the benchmark model used is the MLR technique currently being used in the industry. The strengths of SVR for this data include its ability to represent data in high-dimensional space through kernel functions. The computational results show that a data mining approach is a better prediction technique for this data. Our approach reduces computation time and enhances the practical applications of the SVR technique.

  9. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    PubMed

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line. PMID:27134304

  10. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    PubMed

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  11. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs

    PubMed Central

    Reagor, James A.; Holt, David W.

    2016-01-01

    Abstract: Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line. PMID:27134304

  12. Long-wavelength photonic integrated circuits and avalanche photodetectors

    NASA Astrophysics Data System (ADS)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  13. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q.; Enquist, P.M.

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  14. Photonic integrated circuit for all-optical millimeter-wave signal generation

    SciTech Connect

    Vawter, G.A.; Mar, A.; Zolper, J.; Hietala, V.

    1997-03-01

    Generation of millimeter-wave electronic signals and power is required for high-frequency communication links, RADAR, remote sensing and other applications. However, in the 30 to 300 GHz mm-wave regime, signal sources are bulky and inefficient. All-optical generation of mm-wave signals promises to improve efficiency to as much as 30 to 50 percent with output power as high as 100 mW. All of this may be achieved while taking advantage of the benefits of monolithic integration to reduce the overall size to that of a single semiconductor chip only a fraction of a square centimeter in size. This report summarizes the development of the first monolithically integrated all-optical mm-wave signal generator ever built. The design integrates a mode-locked semiconductor ring diode laser with an optical amplifier and high-speed photodetector into a single optical integrated circuit. Frequency generation is demonstrated at 30, 60 and 90 Ghz.

  15. Directly Writing Resistor, Inductor and Capacitor to Composite Functional Circuits: A Super-Simple Way for Alternative Electronics

    PubMed Central

    Gao, Yunxia; Li, Haiyan; Liu, Jing

    2013-01-01

    Background The current strategies for making electronic devices are generally time, water, material and energy consuming. Here, the direct writing of composite functional circuits through comprehensive use of GaIn10-based liquid metal inks and matching material is proposed and investigated, which is a rather easy going and cost effective electronics fabrication way compared with the conventional approaches. Methods Owing to its excellent adhesion and electrical properties, the liquid metal ink was demonstrated as a generalist in directly making various basic electronic components such as planar resistor, inductor and capacitor or their combination and thus composing circuits with expected electrical functions. For a precise control of the geometric sizes of the writing, a mask with a designed pattern was employed and demonstrated. Mechanisms for justifying the chemical components of the inks and the magnitudes of the target electronic elements so as to compose various practical circuits were disclosed. Results Fundamental tests on the electrical components including capacitor and inductor directly written on paper with working time up to 48 h and elevated temperature demonstrated their good stability and potential widespread adaptability especially when used in some high frequency circuits. As the first proof-of-concept experiment, a typical functional oscillating circuit including an integrated chip of 74HC04 with a supply voltage of 5 V, a capacitor of 10 nF and two resistors of 5 kΩ and 1 kΩ respectively was directly composed on paper through integrating specific electrical elements together, which presented an oscillation frequency of 8.8 kHz. Conclusions The present method significantly extends the roles of the metal ink in recent works serving as only a single electrical conductor or interconnecting wires. It opens the way for directly writing out complex functional circuits or devices on different substrates. Such circuit composition strategy has

  16. Student use of model-based reasoning when troubleshooting an electronic circuit

    NASA Astrophysics Data System (ADS)

    Lewandowski, Heather; Stetzer, Mackenzie; van de Bogart, Kevin; Dounas-Frazer, Dimitri

    2016-03-01

    Troubleshooting systems is an integral part of experimental physics in both research and educational settings. Accordingly, ability to troubleshoot is an important learning goal for undergraduate physics lab courses. We investigate students' model-based reasoning on a troubleshooting task using data collected in think-aloud interviews during which pairs of students from two institutions attempted to diagnose and repair a malfunctioning circuit. Our analysis scheme was informed by the Experimental Modeling Framework, which describes physicists' use of mathematical and conceptual models when reasoning about experimental systems. We show that system and subsystem models were crucial for the evaluation of repairs to the circuit and played an important role in some troubleshooting strategies. Finally, drawing on data from interviews with electronics instructors from a broad range of institution types, we outline recommendations for model-based approaches to teaching and learning troubleshooting skills.

  17. E-Learning System for Experiments Involving Construction of Practical Electronic Circuits

    ERIC Educational Resources Information Center

    Takemura, Atsushi

    2013-01-01

    This paper proposes a novel e-learning system for technical experiments involving the construction of practical electronic circuits; this system would meet the various demands of individual experimenters. This mixed mode is beneficial for practical use in that an experimenter who does not have sufficient circuit components for circuit making can…

  18. Investigation of failure mechanisms in integrated vacuum circuits

    NASA Technical Reports Server (NTRS)

    Rosengreen, A.

    1972-01-01

    The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

  19. Single event soft error in advanced integrated circuit

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Suge, Yue; Xinyuan, Zhao; Shijin, Lu; Qiang, Bian; Liang, Wang; Yongshu, Sun

    2015-11-01

    As technology feature size decreases, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) cause serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.

  20. Minimizing the area required for time constants in integrated circuits

    NASA Technical Reports Server (NTRS)

    Lyons, J. C.

    1972-01-01

    When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

  1. Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

    PubMed

    Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

    2005-09-01

    This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB.

  2. An Electronics Course: Part II--Some of the Circuits.

    ERIC Educational Resources Information Center

    James, Frank

    1981-01-01

    Describes and illustrates the following electric circuits suitable for student construction: basic circuit, dimmer, multivibrators, amplifiers, schmitt trigger, op-amplifier, radio reception, transmitter, sound effects generators, intercoms, and laboratory amplifier. (SK)

  3. Integrated circuit for processing a low-frequency signal from a seismic detector

    SciTech Connect

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A. Fedorov, R. A.

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  4. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  5. Monolithic microwave integrated circuit devices for active array antennas

    NASA Technical Reports Server (NTRS)

    Mittra, R.

    1984-01-01

    Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

  6. Photonic integrated circuits unveil crisis-induced intermittency.

    PubMed

    Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

    2016-09-19

    We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics. PMID:27661954

  7. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  8. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  9. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  10. Wireless Neural Recording With Single Low-Power Integrated Circuit

    PubMed Central

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  11. Apparatus and method for defect testing of integrated circuits

    SciTech Connect

    Cole, E.I. Jr.; Soden, J.M.

    2000-02-29

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  12. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

  13. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built.

  14. Uncertain behaviours of integrated circuits improve computational performance

    PubMed Central

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  15. Funneling single photons into ridge-waveguide photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Fattah poor, S.; Midolo, L.; Li, L. H.; Linfield, E. H.; Schouwenberg, J. F. P.; Xia, T.; van Otten, F. W. M.; Hoang, T. B.; Fiore, A.

    2013-02-01

    The generation, manipulation and detection of single photons enable quantum communication, simulation and potentially computing protocols. However scaling to several qubits requires the integration of these functionalities in a single chip. A promising approach to the integration of single-photon sources in a chip is the use of single quantum dots embedded in photonic crystal waveguides or cavities. To this aim, efficient coupling of the emission from single quantum dots in photonic crystal cavities to low-loss ridge-waveguide (RWG) circuits is needed. This is usually hampered by the large mode mismatch between the two systems. In this work the emission of a photonic crystal (PhC) cavity realized on a GaAs/AlGaAs membrane and pumped by quantum dots has been effectively coupled and transferred through a long RWG (~1mm). By continuous tapering in both horizontal and vertical direction, transmission values (fiber-in, fiber-out) around 0.16 and 0.08% for RWG and coupled PhC waveguide-RWG have been achieved, respectively. This corresponds to about 2.8% coupling efficiency between the center of the PhC waveguide and the single-mode output fiber, a value much higher than what is achieved by top collection. It further shows that around 70% of the light in the PhC waveguide is coupled to the RWG. The emission from quantum dots in the cavity has been clearly identified by exciting from the top and collecting the photoluminescence from the cleaved facet of the device 1mm away from the cavity which enables the efficient coupling of single photons to RWG and detector circuits.

  16. Integrated electronics for peripheral nerve recording and signal processing.

    PubMed

    Limnuson, Kanokwan; Tyler, Dustin J; Mohseni, Pedram

    2009-01-01

    This paper describes the integrated circuit implementation of an electronic system for peripheral nerve recording and signal processing. Specifically, the system aims to record and condition neural activity from the phrenic nerve as a good indicator for breathing, and generate a stimulus trigger signal for a laryngeal pacemaker device to reanimate a paralyzed muscle with electrical stimulation paced with respiration. The 2.2 x 2.2-mm(2) integrated circuit is fabricated using the AMI 1.5 microm 2P/2M n-well CMOS process, and consumes 1 mW from +/-1.5 V. System architecture, circuit design, simulation results, and measurement data in benchtop experiments are presented.

  17. Organic–Inorganic Eu3+/Tb3+ codoped hybrid films for temperature mapping in integrated circuits

    PubMed Central

    Brites, Carlos D. S.; Lima, Patrícia P.; Silva, Nuno J. O.; Millán, Angel; Amaral, Vitor S.; Palacio, Fernando; Carlos, Luís D.

    2013-01-01

    The continuous decrease on the geometric size of electronic devices and integrated circuits generates higher local power densities and localized heating problems that cannot be characterized by conventional thermographic techniques. Here, a self-referencing intensity-based molecular thermometer involving a di-ureasil organic-inorganic hybrid thin film co-doped with Eu3+ and Tb3+ tris (β-diketonate) chelates is used to obtain the temperature map of a FR4 printed wiring board with spatio-temporal resolutions of 0.42 μm/4.8 ms. PMID:24790938

  18. Low-dielectric constant insulators for future integrated circuits and packages.

    PubMed

    Kohl, Paul A

    2011-01-01

    Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

  19. Organic-Inorganic Eu(3+)/Tb(3+) codoped hybrid films for temperature mapping in integrated circuits.

    PubMed

    Brites, Carlos D S; Lima, Patrícia P; Silva, Nuno J O; Millán, Angel; Amaral, Vitor S; Palacio, Fernando; Carlos, Luís D

    2013-01-01

    The continuous decrease on the geometric size of electronic devices and integrated circuits generates higher local power densities and localized heating problems that cannot be characterized by conventional thermographic techniques. Here, a self-referencing intensity-based molecular thermometer involving a di-ureasil organic-inorganic hybrid thin film co-doped with Eu(3+) and Tb(3+) tris (β-diketonate) chelates is used to obtain the temperature map of a FR4 printed wiring board with spatio-temporal resolutions of 0.42 μm/4.8 ms. PMID:24790938

  20. A kind of integrated method discuss of fOG signal processing circuit

    NASA Astrophysics Data System (ADS)

    Lu, Jun; Pan, Xin; Ying, Jiaju; Liu, Jie

    2014-12-01

    In view of the circuit miniaturization need in project application of fiber optic gyroscope(FOG), a new integrated technical scheme adopting system in package(SIP) for signal processing circuit of FOG was put forward. At first, the principle on signal processing circuit of FOG was analyzed, and the technical scheme adopting SIP based on low-temperature co-fired substrate technology was presented according to circuit characteristic and actual condition. Secondly, under the prerequisite of the concept introduction of SIP and LTCC, the SIP prototype of signal processing circuit of FOG was trialed produced,and it passed through the debug test. This SIP modular is an overall circuit complete integrated the signal processing circuit of FOG, and only a potentiometer and EPROM do not case outside. The testing results indicate that SIP is a kind of feasible scheme that carries out miniaturization for signal processing circuit of FOG.

  1. Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

    NASA Technical Reports Server (NTRS)

    Johnston, Allan H.; Rax, Bernard G.

    2006-01-01

    This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

  2. Fundamentals handbook of electrical and computer engineering. Volume 1 Circuits fields and electronics

    NASA Astrophysics Data System (ADS)

    Chang, S. S. L.

    State of the art technology in circuits, fields, and electronics is discussed. The principles and applications of these technologies to industry, digital processing, microwave semiconductors, and computer-aided design are explained. Important concepts and methodologies in mathematics and physics are reviewed, and basic engineering sciences and associated design methods are dealt with, including: circuit theory and the design of magnetic circuits and active filter synthesis; digital signal processing, including FIR and IIR digital filter design; transmission lines, electromagnetic wave propagation and surface acoustic wave devices. Also considered are: electronics technologies, including power electronics, microwave semiconductors, GaAs devices, and magnetic bubble memories; digital circuits and logic design.

  3. Stretchable electronics: materials, architectures and integrations

    NASA Astrophysics Data System (ADS)

    Ahn, Jong-Hyun; Je, Jung Ho

    2012-03-01

    Stretchable electronics, i.e. elastic electronics that can be bent and stretched, is a new, emerging class of electronics, based on building electronic circuits or devices on stretchable substrates. The potential applications range from fully conformable, stretchable, skin sensors for robotic devices, wearable electronic devices, to flesh-like biodevices. One of the challenges in the development of stretchable electronics is to retain full functionality under high external strains in stretching. In this paper, we review a few approaches recently developed for stretchable electronics and highlight recent research efforts on multi-directional writing for stretchable, three-dimensional structures.

  4. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    NASA Astrophysics Data System (ADS)

    Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-01

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  5. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  6. Fabrication of Planar Gradiometers by Using Superconducting Integrated Circuit Technology

    NASA Astrophysics Data System (ADS)

    Maezawa, Masaaki; Ying, Liliang; Gorwadkar, Sucheta; Zhang, Guofeng; Wang, Hai; Kong, Xiangyan; Wang, Zhen; Xie, Xiaoming

    We present fabrication technology for planar-type superconducting quantum interference devices (SQUIDs) comprising trilayer Nb/AlOx/Nb Josephson junctions and thin-film pick-up coils integrated on a single chip. A well-established superconducting integrated circuit technology that was originally developed for digital applications has been modified for developing SQUID fabrication processes with high reliability and controllability. Combination of two photolithography techniques, a high-resolution stepper and a large-shot-area mask aligner, has been introduced to fabricate fine-scale patterns such as 2-μm-square junctions and large-scale patterns such as 10-mm-square pick-up coils with a 2.5- or 3.0-cm baseline on the same chip. We successfully fabricated planar gradiometers and confirmed the operation with typical modulation amplitude of 50 μV, achieving gradient field resolutions as small as 3.5 fT/Hz1/2cm.

  7. SDN architecture for optical packet and circuit integrated networks

    NASA Astrophysics Data System (ADS)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  8. Evolutionary Technique for Automated Synthesis of Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

    2007-01-01

    An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

  9. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    NASA Astrophysics Data System (ADS)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0–30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  10. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-23

    ..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43. The... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same...

  11. Paper-based silver-nanowire electronic circuits with outstanding electrical conductivity and extreme bending stability.

    PubMed

    Huang, Gui-Wen; Xiao, Hong-Mei; Fu, Shao-Yun

    2014-08-01

    Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated.

  12. Ion-beam apparatus and method for analyzing and controlling integrated circuits

    DOEpatents

    Campbell, A.N.; Soden, J.M.

    1998-12-01

    An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

  13. Ion-beam apparatus and method for analyzing and controlling integrated circuits

    DOEpatents

    Campbell, Ann N.; Soden, Jerry M.

    1998-01-01

    An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

  14. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Islam, Syed K; Blalock, Benjamin J

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  15. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    NASA Astrophysics Data System (ADS)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  16. Design structure for in-system redundant array repair in integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  17. Design and Implementation of Study Support System for Electronic Circuits with Observable V-I Characteristics

    NASA Astrophysics Data System (ADS)

    Ohchi, Masashi; Yoshitomi, Takashi; Akagi, Keita; Sasaki, Shinichi; Furukawa, Tatsuya

    We have designed and implemented the “Virtual Laboratory” on the computer systems. Some of the implemented systems are Web-based learning environments where server/client model and Java technologies are adopted. The subject of electronic circuits is the most essential one in the department of electrical and electronic engineering. However, it is a difficult subject for students to understand the basic therory, technical term and electronic circuits design. In this paper, we will describe the study support system for the electronic circuits with observable V-I characteristics using Java.

  18. Development of Remote Measurement System for Studying Electronic Circuits on Web Browser

    NASA Astrophysics Data System (ADS)

    Yoshitomi, Takashi; Ohchi, Masashi; Sasaki, Shinichi; Furukawa, Tatsuya

    We have designed and implemented the “Virtual Laboratory” systems on the computer systems. Some of the implemented systems are Web-based learning environments where a server/client model is adopted. The subject of electronic circuits is the most essential one in the departments of electrical and electronic engineering. However, it is a difficult subject for students to understand the basic therory, technical term and electronic circuit design. In this paper, we will describe the remote measurement system for the learning support of electronic circuits using RTLinux.

  19. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    NASA Technical Reports Server (NTRS)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  20. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A; Tolbert, Leon M; Blalock, Benjamin; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  1. Paper-based silver-nanowire electronic circuits with outstanding electrical conductivity and extreme bending stability

    NASA Astrophysics Data System (ADS)

    Huang, Gui-Wen; Xiao, Hong-Mei; Fu, Shao-Yun

    2014-07-01

    Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated.Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated. Electronic supplementary information (ESI) available: Video of rolling tests; video of the PFP circuit used as flexible cable in a cell phone; video of the application of the circuit as a RFID tag; a detailed method for synthesizing silver nanowires; details of the PFP technique; folding tests for the circuits; air humidity test for the circuit. See DOI: 10.1039/c4nr00846d

  2. The spectral-domain approach for microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Jansen, R. H.

    1985-10-01

    A survey is given of the so-called spectral-domain approach, an analytical and numerical technique particularly suited for the solution of boundary-value problems in microwave and millimeter-wave integrated circuits. The mathematical formulation of the analytical part of this approach is described in a generalized notation for two- and three-dimensional strip- and slot-type fields. In a similar way, the numerical part of the technique is treated, keeping always in touch with the mathematical and physical background, as well as with the respective microwave applications. A discussion of different specific aspects of the approach is presented, and outlines are provided of the peculiarities of shielded-, covered-, and open-type problems. A brief review of the progress achieved in the last decade (1975-1984) follows. The survey closes with considerations on numerical efficiency, demonstrating that spectral-domain computations can by speeded up remarkably by analytical preprocessing. The presented material is based on ten years of active involvement by the author in the field and reveals a variety of contributions by West German researchers previously not known to the international microwave community.

  3. Scheduling revisited workstations in integrated-circuit fabrication

    NASA Technical Reports Server (NTRS)

    Kline, Paul J.

    1992-01-01

    The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

  4. Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

    PubMed Central

    Roham, Masoud; Halpern, Jeffrey M.; Martin, Heidi B.; Chiel, Hillel J.

    2015-01-01

    An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order ΔΣ modulator (ΔΣM) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 μm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of ~250 fA, ~1.5 pA, ~4.5 pA, and ~17 pA were achieved for input currents in the range of ±5, ±37, ±150, and ±600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 μM wirelessly over a transmission distance of ~0.5 m in flow injection analysis experiments. PMID:18990633

  5. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

    PubMed Central

    Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

    2010-01-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

  6. Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

    NASA Astrophysics Data System (ADS)

    Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

    2000-03-01

    Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this

  7. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

    PubMed Central

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

    2008-01-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  8. Towards Evolving Electronic Circuits for Autonomous Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

    2000-01-01

    The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

  9. Variable Time Base Integrator Circuit for Buffet Signal Measurements

    NASA Technical Reports Server (NTRS)

    Batts, Colossie N.

    1973-01-01

    A measurement circuit to obtain buffet data from wind tunnel models wherein a signal proportional to the average RMS value of buffet data is produced for subsequent recording. Feedback means are employed to suppress the D.C. portion of signals developed by the strain gages during dynamic testing. Automatic recording of gain settings of amplifiers employed in the circuit is also provided.

  10. Mimicking the biological neural system using electronic logic circuits

    NASA Astrophysics Data System (ADS)

    Kirikera, Goutham R.; Shinde, Vishal; Kang, Inpil; Schulz, Mark J.; Shanov, Vesselin; Datta, Saurabh; Hurd, Doug; Westheider, Bo; Sundaresan, Mannur; Ghoshal, Anindya

    2004-07-01

    Detecting and locating cracks in structural components and joints that have high feature densities is a challenging problem in the field of Structural Health Monitoring. There have been advances in piezoelectric sensors, actuators, wave propagation, MEMS, and optical fiber sensors. However, few sensor-signal processing techniques have been applied to the monitoring of joints and complex structural geometries. This is in part because maintaining and analyzing a large amount of data obtained from a large number of sensors that may be needed to monitor joints for cracks is difficult. Reliable low cost assessment of the health of structures is crucial to maintain operational availability and productivity, reduce maintenance cost, and prevent catastrophic failure of large structures such as wind turbines, aircraft, and civil infrastructure. Recently, there have also been advances in development of simple passive techniques for health monitoring including a technique based on mimicking the biological neural system using electronic logic circuits. This technique aids in reducing the required number of data acquisition channels by a factor of ten or more and is able to predict the location of a crack within a rectangular grid or within an arbitrarily arranged network of continuous sensors or neurons. The current paper shows results obtained by implementing this method on an aluminum plate and joint. The plates were tested using simulated acoustic emissions and also loading via an MTS machine. The testing indicates that the neural system can monitor complex joints and detect acoustic emissions due to propagating cracks. High sensitivity of the neural system is needed, and further sensor development and testing on different types of joints is required. Also indicated is that sensor geometry, sensor location, signal filtering, and logic parameters of the neural system will be specific to the particular type of joint (material, thickness, geometry) being monitored. Also, a

  11. Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1984-01-01

    Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

  12. Open foundry platform for high-performance electronic-photonic integration.

    PubMed

    Orcutt, Jason S; Moss, Benjamin; Sun, Chen; Leu, Jonathan; Georgas, Michael; Shainline, Jeffrey; Zgraggen, Eugen; Li, Hanqing; Sun, Jie; Weaver, Matthew; Urošević, Stevan; Popović, Miloš; Ram, Rajeev J; Stojanović, Vladimir

    2012-05-21

    This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.

  13. Electronic bidirectional valve circuit prevents crossover distortion and threshold effect

    NASA Technical Reports Server (NTRS)

    Kernick, A.

    1966-01-01

    Four-terminal network forms a bidirectional valve which will switch or alternate an ac signal without crossover distortion or threshold effect. In this network, an isolated control signal is sufficient for circuit turn-on.

  14. An electronic circuit that detects left ventricular ejection events by processing the arterial pressure waveform

    NASA Technical Reports Server (NTRS)

    Gebben, V. D.; Webb, J. A., Jr.

    1972-01-01

    An electronic circuit for processing arterial blood pressure waveform signals is described. The circuit detects blood pressure as the heart pumps blood through the aortic valve and the pressure distribution caused by aortic valve closure. From these measurements, timing signals for use in measuring the left ventricular ejection time is determined, and signals are provided for computer monitoring of the cardiovascular system. Illustrations are given of the circuit and pressure waveforms.

  15. From The Lab to The Fab: Transistors to Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.

    2003-09-01

    Transistor action was experimentally observed by John Bardeen and Walter Brattain in n-type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold-plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point-contact semiconductor amplifier, often referred to as the point-contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point-contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. The a priori tuning of the point-contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to "burnout" were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p-n junction (bulk) transistors began replacing the point-contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore's Law in setting the parameters by which the IC industry's growth was monitored will be discussed.

  16. Electrothermal Analysis of Three-Dimensional Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Harris, Theodore Robert

    2011-12-01

    Transient electro-thermal simulation of a three dimensional integrated circuit (3DIC) is reported that uses a cell-based simulation to provide a selected transistor thermal profile while providing advantages of hierarchical simulation. Due to CPU and memory limitations, full transistor electro-thermal simulations on a useful scale are not possible. Standard cells are considered on a per-instance basis and modeled with electro-thermal macro-models developed in a multi-physics simulator. Simulations are compared favorably to measurements for a token-generating 3DIC clocking at a maximum of 1 GHz. The 3DIC, which is composed of 9 by 3 layers of repetitive frequency multipliers and dividers, was fabricated with the Massachusetts Institute of Technology Lincoln Laboratory (MITLL) 3DIC process. Measurements indicated a linear rise in temperature of the active areas over a range of applied background ambient temperatures. An average of 7.5 K change in temperature was measured across dense areas of circuitry. For thermal simulation, the physical characteristics of the 3DIC were extracted from flattened OpenAccess layout files. Material parameters, connections, and geometries were considered in order to create a more physically accurate resistive thermal mesh. Physical thermal networks extracted with resolutions of 10 mum and 5 mum connect thermal terminals of the electrothermal macromodel cell elements to active layers yielding temporal and spatial simulated dynamic thermal results in three dimensions. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.

  17. Bridge Circuits: One Topic in the Modular Course in Electronics Instrumentation.

    ERIC Educational Resources Information Center

    Aldridge, Bill G.; Stringer, Gene A.

    This learning module is intended to illustrate the functioning and uses of bridge circuits. The discussion and laboratory procedures suggested in the module presume familiarity with basic concepts of electronics such as voltage, current, resistance, capacitance, inductance, phase, and knowledge of such skills as breadboarding circuits from…

  18. Virtual Instrument Systems in Reality (VISIR) for Remote Wiring and Measurement of Electronic Circuits on Breadboard

    ERIC Educational Resources Information Center

    Tawfik, M.; Sancristobal, E.; Martin, S.; Gil, R.; Diaz, G.; Colmenar, A.; Peire, J.; Castro, M.; Nilsson, K.; Zackrisson, J.; Hakansson, L.; Gustavsson, I.

    2013-01-01

    This paper reports on a state-of-the-art remote laboratory project called Virtual Instrument Systems in Reality (VISIR). VISIR allows wiring and measuring of electronic circuits remotely on a virtual workbench that replicates physical circuit breadboards. The wiring mechanism is developed by means of a relay switching matrix connected to a PCI…

  19. CIRCUS--A digital computer program for transient analysis of electronic circuits

    NASA Technical Reports Server (NTRS)

    Moore, W. T.; Steinbert, L. L.

    1968-01-01

    Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

  20. Heterodyne lock-in thermal coupling measurements in integrated circuits: Applications to test and characterization.

    PubMed

    Altet, J; Aldrete-Vidrio, E; Mateo, D; Salhi, A; Grauby, S; Claeys, W; Dilhaire, S; Perpiñà, X; Jordà, X

    2009-02-01

    Heterodyne strategies can be used to characterize thermal coupling in integrated circuits when the electrical bandwidth of the dissipating circuit is beyond the bandwidth of the thermal coupling mechanism. From the characterization of the thermal coupling, two possible applications are described: extraction of characteristics of the dissipating circuit (the determination of the center frequency of a low-noise amplifier) and the extraction of the thermal coupling transfer function. PMID:19256677

  1. Equivalent circuit modeling of losses and dispersion in single and coupled lines for microwave and millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Tripathi, Vijai K.; Hill, Achim

    1988-02-01

    Losses and dispersion in open inhomogeneous guided-wave structures such as microstrips and other planar structures at microwave and millimeter-wave frequencies and in MMICs (monolithic microwave integrated circuits) have been modeled with circuits consisting of ideal lumped elements and lossless TEM (transverse electromagnetic) lines. It is shown that, given a propagation structure for which numerical techniques to compute the propagation characteristics are available, an equivalent circuit whose terminal frequency and time-domain properties are the same as the structure can be synthesized. This is accomplished by equating the network functions of the given single or coupled line multiport with that of the model and extracting all the parameters of the equivalent circuit model by using standard parameters identification procedures. This model is valid over a desired frequency range and can be used to help design both analog and digital circuits consisting of these structures and other active and passive elements utilizing standard CAD (computer-aided design) programs. To validate the accuracy and usefulness of the models, results for a mismatched 50-ohm line in alumina and a high-impedance MMIC line stub are included.

  2. Monolithic integrated resonant tunneling diode and heterostructure junction field effect transistor circuits

    NASA Astrophysics Data System (ADS)

    Yen, J. C.; Zhang, Q.; Mondry, M. J.; Chavarkar, P. M.; Hu, E. L.; Long, S. I.; Mishra, U. K.

    1996-10-01

    We have developed a simple technology for monolithic integration of resonant tunneling diodes (RTDs) and heterostructure junction-modulated field effect transistors (HJFETs). We have achieved good device performance with this technology: HJFETs had transconductances of 290 mS/mm and current densities of 310 mA/mm for a 1.5 μm gate length; RTDs had room temperature peak to valley ratios greater than 20:1 with current densities of 42 kA/cm 2. With this technology, we have demonstrated a monolithically integrated RTD + HJFET state holding circuit that can serve as a building block circuit for self-timed logic units. This circuit is resistor-free and operates at room temperature. The state holding circuit showed large noise margins of 1.21 V and 0.71 V, respectively, for input low and input high, for a 1.7 V input voltage swing. We have examined the transient response of the circuit and investigated the effect of circuit design parameters on propagation delay. We identify the RTD valley current as the limiting factor on propagation delay. We discuss the suitability of RTD + HJFET circuits such as our state holding circuit for highly dense integrated circuits.

  3. Method for producing a hybridization of detector array and integrated circuit for readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

    1993-01-01

    A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

  4. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    PubMed

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

  5. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    PubMed

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler. PMID:27464079

  6. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    ERIC Educational Resources Information Center

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  7. Compact grating structure for application to filters and resonators in monolithic microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Wang, Te-Hui; Itoh, Tatsuo

    1987-12-01

    Possible high-Q circuits based on a low-loss crosstie-overlay slow-wave structure are proposed for monolithic microwave integrated circuits (MMICs). Various configurations and results for slow-wave factors are presented. This structure is used for construction of a frequency-selective reflector with a compact size. The effect of conductor loss is considered.

  8. Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

    NASA Technical Reports Server (NTRS)

    Seaward, R. C.

    1967-01-01

    Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

  9. Low-power integrated-circuit driver for ferrite-memory word lines

    NASA Technical Reports Server (NTRS)

    Katz, S.

    1970-01-01

    Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

  10. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator.

    PubMed

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  11. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

    PubMed Central

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  12. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    NASA Technical Reports Server (NTRS)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  13. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    NASA Technical Reports Server (NTRS)

    Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

    2000-01-01

    Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

  14. An Educational Laboratory for Digital Control and Rapid Prototyping of Power Electronic Circuits

    ERIC Educational Resources Information Center

    Choi, Sanghun; Saeedifard, M.

    2012-01-01

    This paper describes a new educational power electronics laboratory that was developed primarily to reinforce experimentally the fundamental concepts presented in a power electronics course. The developed laboratory combines theoretical design, simulation studies, digital control, fabrication, and verification of power-electronic circuits based on…

  15. A new pixel level digital read out integrated circuits for ultraviolet imaging sensors

    NASA Astrophysics Data System (ADS)

    Xu, Bin; Lan, Tian-yi; Yuan, Yong-gang; Li, Xiang-yang

    2014-11-01

    The ultraviolet imaging sensors consist of two important parts: the array of detectors and the read out integrated circuits. Along with the demand for the fine resolution, large input dynamic range and high integration degree of the imaging sensors, the functions of read out integrated circuits are becoming more and more important. The on chip analog to digital conversion is the main directions of research on this area. In this paper, we presented a new digital read out integrated circuits for ultraviolet imaging sensors. The proposed circuits have an analog to digital converter in each pixel, which enable the parallel analog to digital conversion of the whole pixel array. The developed circuits have a 50um×50um pixel area with a 128×128 size, and are designed in a 0.35um four metal double poly mixed signal CMOS process. The simulation results show that the designed analog to digital converter has an accuracy of 0.2mV and can achieve the dynamic range of 88dB. The proposed circuits realize the low noise and high speed digital output of read out integrated circuits for ultraviolet imaging sensors.

  16. RNA Signal Amplifier Circuit with Integrated Fluorescence Output

    PubMed Central

    2015-01-01

    We designed an in vitro signal amplification circuit that takes a short RNA input that catalytically activates the Spinach RNA aptamer to produce a fluorescent output. The circuit consists of three RNA strands: an internally blocked Spinach aptamer, a fuel strand, and an input strand (catalyst), as well as the Spinach aptamer ligand 3,5-difluoro-4-hydroxylbenzylidene imidazolinone (DFHBI). The input strand initially displaces the internal inhibitory strand to activate the fluorescent aptamer while exposing a toehold to which the fuel strand can bind to further displace and recycle the input strand. Under a favorable condition, one input strand was able to activate up to five molecules of the internally blocked Spinach aptamer in 185 min at 30 °C. The simple RNA circuit reported here serves as a model for catalytic activation of arbitrary RNA effectors by chemical triggers. PMID:25354355

  17. RNA signal amplifier circuit with integrated fluorescence output.

    PubMed

    Akter, Farhima; Yokobayashi, Yohei

    2015-05-15

    We designed an in vitro signal amplification circuit that takes a short RNA input that catalytically activates the Spinach RNA aptamer to produce a fluorescent output. The circuit consists of three RNA strands: an internally blocked Spinach aptamer, a fuel strand, and an input strand (catalyst), as well as the Spinach aptamer ligand 3,5-difluoro-4-hydroxylbenzylidene imidazolinone (DFHBI). The input strand initially displaces the internal inhibitory strand to activate the fluorescent aptamer while exposing a toehold to which the fuel strand can bind to further displace and recycle the input strand. Under a favorable condition, one input strand was able to activate up to five molecules of the internally blocked Spinach aptamer in 185 min at 30 °C. The simple RNA circuit reported here serves as a model for catalytic activation of arbitrary RNA effectors by chemical triggers.

  18. The development of an uncommitted integrated circuit for combined digital and analogue applications

    NASA Astrophysics Data System (ADS)

    Kemp, A. J.

    1982-06-01

    An uncommmited integrated circuit is a standardized integrated circuit needing only a fraction of the normal processing steps to program it for a required application. The result is a reduction in the time, money and knowledge required to develop an integrated circuit. The development and industrialization of an uncommitted circuit for combined digital and analog applications are described. Integrated Injection Logic (I2L) is used to realize digital functions, and standard analog techniques, based on a bipolar process, are used to realize analog functions. A novel architecture, as well as the use of three masks to realize a required interconnection pattern, results in a very high efficiency in terms of the number of components that was used.

  19. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    ERIC Educational Resources Information Center

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  20. A review of the technology and process on integrated circuits failure analysis applied in communications products

    NASA Astrophysics Data System (ADS)

    Ming, Zhimao; Ling, Xiaodong; Bai, Xiaoshu; Zong, Bo

    2016-02-01

    The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

  1. INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

    PubMed

    Sholom, S; McKeever, S W S

    2016-09-01

    In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. PMID:26516131

  2. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    PubMed

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

  3. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    NASA Astrophysics Data System (ADS)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  4. Thermoelectric devices and diamond films for temperature control of high density electronic circuits

    NASA Astrophysics Data System (ADS)

    Vandersande, Jan W.; Ewell, Richard; Fleurial, Jean-Pierre; Lyon, Hylan B.

    1994-08-01

    The increased speeds of integrated circuits is accompanied by increased power levels and the need to package the IC chips very close together. Combined, these spell very high power densities and severe thermal problems at the package level. Conventional packaging materials have difficulty dealing with these thermal management problems. However, it is possible to combine both active and passive cooling by using thin film bismuth-telluride thermoelectric coolers (microcoolers) and diamond substrates for the temperature control of these high density electronic circuits. The highest power components would be mounted directly onto thin film thermoelectric elements, which would maintain the temperature of these components from a few degrees to tens of degrees below that of the diamond substrate. This allows these components to operate within their required temperature range, effectively manage temperature spikes and junction temperatures, and increase clockspeed. To optimize the design of the thermoelectric cooler and operate at maximum efficiency, diamond films acting as thermal lenses would also be used to spread the heat from the small power device to the larger coolers. In those instances where the devices are all operating above ambient temperature, high thermal conductivity diamond films alone are sufficient to cool these devices, by effectively conducting the heat throughout the board.

  5. Integrated-Circuit Controller For Brushless dc Motor

    NASA Technical Reports Server (NTRS)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  6. V-band low-noise integrated circuit receiver. [for space communication systems

    NASA Technical Reports Server (NTRS)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-01-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  7. Integrating Electronics and Microfluidics on Paper.

    PubMed

    Hamedi, Mahiar M; Ainla, Alar; Güder, Firat; Christodouleas, Dionysios C; Fernández-Abedul, M Teresa; Whitesides, George M

    2016-07-01

    Paper microfluidics and printed electronics have developed independently, and are incompatible in many aspects. Monolithic integration of microfluidics and electronics on paper is demonstrated. This integration makes it possible to print 2D and 3D fluidic, electrofluidic, and electrical components on paper, and to fabricate devices using them.

  8. SEMICONDUCTOR INTEGRATED CIRCUITS: Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

    NASA Astrophysics Data System (ADS)

    Tao, Liang; Xinzhang, Jia; Junfeng, Chen

    2009-11-01

    Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

  9. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  10. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    PubMed

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials. PMID:27322134

  11. Process development of beam-lead silicon-gate COS/MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Baptiste, B.; Boesenberg, W.

    1974-01-01

    Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

  12. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    PubMed

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits. PMID:19940239

  13. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits

    PubMed Central

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M.

    2009-01-01

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (Vout) versus input (Vin) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of ≈45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits. PMID:19940239

  14. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  15. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    SciTech Connect

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  16. Nonpolymer new organic film for local insulation in laser-direct-writing circuit restructuring for large-scale integrated circuits

    NASA Astrophysics Data System (ADS)

    Seki, Y.; Morishige, Y.; Wamme, N.; Ohnishi, Y.; Kishida, S.

    1993-06-01

    A new nonpolymer organic material, hexaacetate p-methylcalix [6] arene (hereafter referred to as MC6AOAc), has been successfully applied to the localized insulator for large-scale integration (LSI) circuit restructuring. A conductive line, necessary for the restructuring, was written on the MC6AOAc film by laser chemical vapor deposition with no damage to the film. The leakage current through the film was kept within the permissible limit. The unnecessary part of the film for LSI testing was easily removed by an ethanol rinse without damage to the interconnection, in a self-aligned manner, with the written line as a mask. This technology extends the usability of the LSI circuit restructuring.

  17. Buffer direct injection readout integrated circuit design for dual band infrared focal plane array detector

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Tang, Shiang-Feng; Lin, Wen-Jen

    2013-05-01

    This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 μm. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

  18. Unipolar complementary circuits using double electron layer tunneling transistors

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Blount, M.A.; Reno, J.L.; Hafich, M.J.

    1999-01-01

    We demonstrate unipolar complementary circuits consisting of a pair of resonant tunneling transistors based on the gate control of two-dimensional{endash}two-dimensional interlayer tunneling, where a single transistor{emdash}in addition to exhibiting a well-defined negative-differential resistance{emdash}can be operated with either positive or negative transconductance. Details of the device operation are analyzed in terms of the quantum capacitance effect and bandbending in a double quantum well structure, and show good agreement with experiment. Application of resonant tunneling complementary logic is discussed by demonstrating complementary static random access memory using two devices connected in series. {copyright} {ital 1999 American Institute of Physics.}

  19. Unipolar Complementary Circuits Using Double Electron Layer Tunneling Tansistors

    SciTech Connect

    Blount, M.A.; Hafich, M.J.; Moon, J.S.; Reno, J.L.; Simmons, J.A.

    1998-10-19

    We demonstrate unipolar complementary circuits consisting of a pair of resonant tunneling transistors based on the gate control of 2D-2D interlayer tunneling, where a single transistor - in addition to exhibiting a welldefined negative-differential-resistance can be operated with either positive or negative transconductance. Details of the device operation are analyzed in terms of the quantum capacitance effect and band-bending in a double quantum well structure, and show good agreement with experiment. Application of resonant tunneling complementary logic is discussed by demonstrating complementary static random access memory using two devices connected in series.

  20. Si-based light emitter in an integrated photonic circuit for smart biosensor applications

    NASA Astrophysics Data System (ADS)

    Germer, S.; Cherkouk, C.; Rebohle, L.; Helm, M.; Skorupa, W.

    2013-05-01

    The motivation for integrated Silicon-based optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here we present initial results in the integration and butt-coupling of a Si-based light emitting device (LED) [1-3] to a waveguide into a photonic circuit. Our first approach deals with the design, fabrication and characterization of the dielectric high contrast waveguide as an important component, beside the LED, for the development of a Si-based biodetection system. In this work we demonstrate design examples of Si3N4/SiO2-waveguides, which were calculated using MATLAB, the effective index method (EIM) and the finite element method (FEM), with a 0.45μm thick and 0.7μm wide core which shows a high confinement factor of ~74% and coupling efficiency of ~66% at 1.55μm, respectively. The fabrication was done by plasma enhanced chemical vapour deposition (PECVD), optical lithography and reactive ion etching (RIE). Additionally, we characterized the deposited layers via ellipsometry and the etched structures by scanning electron microscopy (SEM). The obtained results establish principles for Si-based LED butt-coupling to a powerful optical waveguide-based interconnect with effective light absorption and an adequate coupling efficiency.

  1. Fault detection monitor circuit provides ''self-heal capability'' in electronic modules - A concept

    NASA Technical Reports Server (NTRS)

    Kennedy, J. J.

    1970-01-01

    Self-checking technique detects defective solid state modules used in electronic test and checkout instrumentation. A ten bit register provides failure monitor and indication for 1023 comparator circuits, and the automatic fault-isolation capability permits the electronic subsystems to be repaired by replacing the defective module.

  2. Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

    PubMed

    Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

    2013-08-21

    For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge

  3. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  4. Basic Study on the Radio Frequency Characteristics of the Transmission Lines Employing Periodically Perforated Ground Metal on GaAs Monolithic Microwave Integrated Circuit and Their Equivalent Ciruits

    NASA Astrophysics Data System (ADS)

    Yun, Young; Ju, Jeong-Gab; Kim, Hong Seung

    2011-01-01

    In this work, basic characteristics of transmission line employing periodically perforated ground metal (PPGM) were investigated using theoretical and experimental analysis. Concretely, bandwidth and impedance were investigated using theoretical analysis, and wavelength and effective permittivity were extracted from experimental results. In addition, insertion loss and isolation characteristics were investigated using equivalent circuit analysis. For simplification of design process, equivalent circuits for the PPGM cell were extracted, and all circuit parameters were expressed by closed-form equation. Above results indicate that the transmission line employing PPGM is a promising candidate for a development of matching and passive elements on monolithic microwave integrated circuit (MMIC) including wireless communication circuit and compound semiconducting devices such as high electron mobility transistor (HEMT), diamond field effect transistor (FET) and light emitting diode (LED).

  5. In vivo silicon-based flexible radio frequency integrated circuits monolithically encapsulated with biocompatible liquid crystal polymers.

    PubMed

    Hwang, Geon-Tae; Im, Donggu; Lee, Sung Eun; Lee, Jooseok; Koo, Min; Park, So Young; Kim, Seungjun; Yang, Kyounghoon; Kim, Sung June; Lee, Kwyro; Lee, Keon Jae

    2013-05-28

    Biointegrated electronics have been investigated for various healthcare applications which can introduce biomedical systems into the human body. Silicon-based semiconductors perform significant roles of nerve stimulation, signal analysis, and wireless communication in implantable electronics. However, the current large-scale integration (LSI) chips have limitations in in vivo devices due to their rigid and bulky properties. This paper describes in vivo ultrathin silicon-based liquid crystal polymer (LCP) monolithically encapsulated flexible radio frequency integrated circuits (RFICs) for medical wireless communication. The mechanical stability of the LCP encapsulation is supported by finite element analysis simulation. In vivo electrical reliability and bioaffinity of the LCP monoencapsulated RFIC devices are confirmed in rats. In vitro accelerated soak tests are performed with Arrhenius method to estimate the lifetime of LCP monoencapsulated RFICs in a live body. The work could provide an approach to flexible LSI in biointegrated electronics such as an artificial retina and wireless body sensor networks.

  6. A terahertz monolithic integrated resonant tunneling diode oscillator and mixer circuit

    NASA Astrophysics Data System (ADS)

    Diebold, Sebastian; Tsuruda, Kazuisao; Kim, Jae-Young; Mukai, Toshikazu; Fujita, Masayuki; Nagatsuma, Tadao

    2016-04-01

    In this paper, we demonstrate the monolithic integration of two resonant tunneling diodes (RTD) to make a THz mixer circuit. The circuit uses two RTDs, which are integrated in one carrier substrate. The RTDs are biased independently. The fist RTD operates as an oscillator and provides the local oscillator signal for the second RTD operating as a mixer. The measurements demonstrate that a monolithic integration of several RTDs in one substrate is feasible. This offers new possibilities for RTD based wireless communication and sensing systems.

  7. Evolutionary Technique for Automated Synthesis of Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

    2003-01-01

    A method for evolving a circuit comprising configuring a plurality of transistors using a plurality of reconfigurable switches so that each of the plurality of transistors has a terminal coupled to a terminal of another of the plurality of transistors that is controllable by a single reconfigurable switch. The plurality of reconfigurable switches being controlled in response to a chromosome pattern. The plurality of reconfigurable switches may be controlled using an annealing function. As such, the plurality of reconfigurable switches may be controlled by selecting qualitative values for the plurality of reconfigurable switches in response to the chromosomal pattern, selecting initial quantitative values for the selected qualitative values, and morphing the initial quantitative values. Typically, subsequent quantitative values will be selected more divergent than the initial quantitative values. The morphing process may continue to partially or to completely polarize the quantitative values.

  8. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-02-04

    ... December 24, 2008, based on a complaint filed by Qimonda AG of Munich, Germany (``Qimonda''). 73 FR 79165... COMMISSION In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice... importation, and sale within the United States after importation of certain semiconductor integrated...

  9. External electro-optic probing of millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

    1989-01-01

    An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

  10. The single-event effect evaluation technology for nano integrated circuits

    NASA Astrophysics Data System (ADS)

    Hongchao, Zheng; Yuanfu, Zhao; Suge, Yue; Long, Fan; Shougang, Du; Maoxin, Chen; Chunqing, Yu

    2015-11-01

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally.

  11. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    PubMed

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-01

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  12. A circuit method to integrate metamaterial and graphene in absorber design

    NASA Astrophysics Data System (ADS)

    Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

    2014-10-01

    We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

  13. Electronic switching circuit uses complementary non-linear components

    NASA Technical Reports Server (NTRS)

    Zucker, O. S.

    1972-01-01

    Inherent switching properties of saturable inductors and storage diodes are combined to perform large variety of electronic functions, such as pulse shaping, gating, and multiplexing. Passive elements replace active switching devices in generation of complex waveforms.

  14. Ultrafast electron transport across nano gaps in nanowire circuits

    SciTech Connect

    Potma, Eric O.

    2015-07-31

    In this Program we aim for a closer look at electron transfer through single molecules. To achieve this, we use ultrafast laser pulses to time stamp an electron tunneling event in a molecule that is connected between two metallic electrodes, while reading out the electron current. A key aspect of this project is the use of metallic substrates with plasmonic activity to efficiently manipulate the tunneling probability. The first Phase of this program is concerned with developing highly sensitive tools for the ultrafast optical manipulation of tethered molecules through the evanescent surface field of plasmonic substrates. The second Phase of the program aims to use these tools for exercising control over the electron tunneling probability.

  15. Quantitative coherent diffractive imaging of an integrated circuit at a spatial resolution of 20 nm

    NASA Astrophysics Data System (ADS)

    Abbey, Brian; Williams, Garth J.; Pfeifer, Mark A.; Clark, Jesse N.; Putkunz, Corey T.; Torrance, Angela; McNulty, Ian; Levin, T. M.; Peele, Andrew G.; Nugent, Keith A.

    2008-11-01

    The complex transmission function of an integrated circuit is reconstructed at 20 nm spatial resolution using coherent diffractive imaging. A quantitative map is made of the exit surface wave emerging from void defects within the circuit interconnect. Assuming a known index of refraction for the substrate allows the volume of these voids to be estimated from the phase retardation in this region. Sample scanning and tomography of extended objects using coherent diffractive imaging is demonstrated.

  16. Design of beam steering electronic circuits for medical applications

    NASA Astrophysics Data System (ADS)

    Safar, Mohammad A. A. A.

    This thesis deals with the theory and design of a hemispherical antenna array circuit that is capable to operate in the intermediate zones. By doing that, this array can be used in Hyperthermia Treatment for Brain Cancer in which the aim is to noninvasively focus the fields at microwave frequencies to the location of the tumor cells in the brain. Another possible application of the array is to offer an alternative means of sustaining Deep Brain Stimulation other than using the traditional (surgical) approach. The new noninvasive technique is accomplished by the use of a hemispherical antenna array placed on the human's head. The array uses a new beamforming technique that achieves 3 dimensional beamforming or focusing of the magnetic field of antennas to desired points in the brain to achieve either cell death by temperature rise (Hyperthermia Application) or to cause brain stimulation and hopefully alleviate the affects of Parkinson's Disease (Deep Brain Stimulation). The main obstacle in this design was that the far field approximation that is usually used when designing antenna arrays does not apply in this case since the hemispherical array is in close proximity to where the magnetic field is desired to be focused. The antenna array problem is approached as a boundary-valued problem with the human head being modeled as a three layered hemisphere. The exact expressions for electromagnetic fields are derived. Health issues such as electric field exposure and specific absorption rate (SAR) are considered. After developing the main antenna and beamforming theory, a neural network is designed to accomplish the beamforming technique used. The radio-frequency (RF) transmitter was designed to transmit the fields at a frequency of 1.8 GHz. The antenna array can also be used as a receiver. The antenna and beamforming theory is presented. A new reception technique is shown which enables the array to receive multiple magnetic field sources from within the hemispherical

  17. Electronics box having internal circuit cards interconnected to external connectors sans motherboard

    NASA Technical Reports Server (NTRS)

    Hockett, John E. (Inventor)

    2005-01-01

    An electronics chassis box includes a pair of opposing sidewalls, a pair of opposing end walls, a bottom surface, a top cover, and ring connectors assemblies mounted in selective ones of the walls of the electronic box. Boss members extend from the bottom surface at different heights upon which circuit cards are mounted in spatial relationship to each other. A flex interconnect substantially reduces and generally eliminates the need of a motherboard by interconnecting the circuit cards to one another and to external connectors mounted within the ring connector assemblies.

  18. DCal: A custom integrated circuit for calorimetry at the International Linear Collider

    SciTech Connect

    Hoff, James R.; Mekkaoui, Abderrazek; Yarema, Ray; Drake, Gary; Repond, Jose; /Argonne

    2005-10-01

    A research and development collaboration has been started with the goal of producing a prototype hadron calorimeter section for the purpose of proving the Particle Flow Algorithm concept for the International Linear Collider. Given the unique requirements of a Particle Flow Algorithm calorimeter, custom readout electronics must be developed to service these detectors. This paper introduces the DCal or Digital Calorimetry Chip, a custom integrated circuit developed in a 0.25um CMOS process specifically for this International Linear Collider project. The DCal is capable of handling 64 channels, producing a 1-bit Digital-to-Analog conversion of the input (i.e. hit/no hit). It maintains a 24-bit timestamp and is capable of operating either in an externally triggered mode or in a self-triggered mode. Moreover, it is capable of operating either with or without a pipeline delay. Finally, in order to permit the testing of different calorimeter technologies, its analog front end is capable of servicing Particle Flow Algorithm calorimeters made from either Resistive Plate Chambers or Gaseous Electron Multipliers.

  19. Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

    NASA Astrophysics Data System (ADS)

    Dickerson, Samuel J.; Noyola, Arnaldo J.; Levitan, Steven P.; Chiarulli, Donald M.

    2007-01-01

    In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer, which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology, we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack. We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with macro-scale optical techniques.

  20. Differential transimpedance amplifier circuit for correlated differential amplification

    DOEpatents

    Gresham, Christopher A.; Denton, M. Bonner; Sperline, Roger P.

    2008-07-22

    A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

  1. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  2. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  3. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-08

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  4. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-29

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  5. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2007-12-18

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  6. Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

    PubMed

    Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

    2015-06-01

    Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

  7. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    NASA Astrophysics Data System (ADS)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  8. Integrated silicon and silicon nitride photonic circuits on flexible substrates.

    PubMed

    Chen, Yu; Li, Mo

    2014-06-15

    Flexible integrated photonic devices based on crystalline materials on plastic substrates have a promising potential in many unconventional applications. In this Letter, we demonstrate a fully integrated photonic system including ring resonators and grating couplers, based on both crystalline silicon and silicon nitride, on flexible plastic substrate by using the stamping-transfer method. A high yield has been achieved by a simple, yet reliable transfer method without significant performance degradation.

  9. A photon position sensor consisting of single-electron circuits.

    PubMed

    Kikombo, Andrew Kilinga; Tabe, Michiharu; Amemiya, Yoshihito

    2009-10-01

    This paper proposes a solid-state sensor that can detect the position of incident photons with a high spatial resolution. The sensor consists of a two-dimensional array of single-electron oscillators, each coupled to its neighbors through coupling capacitors. An incident photon triggers an excitatory circular wave of electron tunneling in the oscillator array. The wave propagates in all directions to reach the periphery of the array. By measuring the arrival time of the wave at the periphery, we can know the position of the incident photon. The tunneling wave's generation, propagation, arrival at the array periphery, and the determination of incident photon positions are demonstrated with the results of Monte Carlo based computer simulations.

  10. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  11. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

    1995-11-07

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

  12. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

    1995-01-01

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

  13. Design of a low noise and high accuracy readout integrated circuit for infrared detectors

    NASA Astrophysics Data System (ADS)

    Yang, Dong; Zhou, Hang-yu; Wang, Jian

    2011-08-01

    In this paper, a low noise and high accuracy readout integrated circuit (ROIC) for Infrared detectors is presented. The circuit is made up of capacitor trans-impedance amplifier (CTIA) and correlation double sampling (CDS) circuit. First, the accuracy, and injection efficiency of the CTIA structure which is used to convert the photo-current into voltage are fully discussed. The readout accuracy of weak current signal can be obviously improved by the using of CTIA. Then, the CDS structure with offset calibration technique is used to reduce the fixed pattern noise (FPN) of CTIA. Thus, the signal to noise ratio (SNR) of the designed readout circuit is improved. By utilizing the above two techniques, the influence of noise on this circuit was greatly reduced and the precision of the ROIC was improved. Besides, the design of amplifier in CTIA is discussed in more detail, which will bring about important effect on performance of the whole circuit. Simulation results at Cadence Spectre demonstrated that the readout circuit had reached the requirement of application. The final chip was fabricated with Chartered 0.35um standard CMOS process. Testing results show that the linearity of CTIA is 99%, and that the readout accuracy is 10-bit, while the detecting current varies from 10pA to 10nA. Furthermore, the infrared image is shown in this paper, which means that the ROIC has a good performance at the practical application.

  14. An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

    1991-01-01

    Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

  15. Readout integrated circuit for microbolometer with an analog non-uniformity correction

    NASA Astrophysics Data System (ADS)

    Hwang, C. H.; Woo, D. H.; Lee, Y. S.; Lee, H. C.

    2005-10-01

    We have developed a microbolometer readout integrated circuit (ROIC) that corrects the non-uniformity in analog operation and acts in both normal mode and edge detection mode. A capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. Generally, when fabricating microbolometer focal plane arrays (FPAs), offset-error and gain-error in the inter-microbolometer are induced by fabrication error. They are shown as fixed pattern noise (FPN) in the infrared image. In the present study, a circuit correcting the offset-error and the gain-error in the normal mode by controlling the bias and the integration capacitance of the CTIA is proposed. This circuit does not require an additional DSP chip, and the non-uniformity is corrected before the analog to digital conversion (ADC). Thus, it can utilize 3-4 bits lower ADC compared to the conventional readout circuit. In the edge detection mode, after correcting the gain-error in two adjacent pixels, edge detection can be realized by subtracting their signal without the DSP. We have designed the suggested circuit to output a 10bit level effective infrared signal using 0.35um 2-poly 3-metal CMOS technology.

  16. Integrated low power digital gyro control electronics

    NASA Technical Reports Server (NTRS)

    M'Closkey, Robert (Inventor); Challoner, A. Dorian (Inventor); Grayver, Eugene (Inventor); Hayworth, Ken J. (Inventor)

    2005-01-01

    Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

  17. Detection of orbital angular momentum using a photonic integrated circuit

    PubMed Central

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916

  18. Detection of orbital angular momentum using a photonic integrated circuit.

    PubMed

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-20

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  19. Detection of orbital angular momentum using a photonic integrated circuit

    NASA Astrophysics Data System (ADS)

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  20. Detection of orbital angular momentum using a photonic integrated circuit.

    PubMed

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916

  1. An improved electrical and thermal model of a microbolometer for electronic circuit simulation

    NASA Astrophysics Data System (ADS)

    Würfel, D.; Vogt, H.

    2012-09-01

    The need for uncooled infrared focal plane arrays (IRFPA) for imaging systems has increased since the beginning of the nineties. Examples for the application of IRFPAs are thermography, pedestrian detection for automotives, fire fighting, and infrared spectroscopy. It is very important to have a correct electro-optical model for the simulation of the microbolometer during the development of the readout integrated circuit (ROIC) used for IRFPAs. The microbolometer as the sensing element absorbs infrared radiation which leads to a change of its temperature due to a very good thermal insulation. In conjunction with a high temperature coefficient of resistance (TCR) of the sensing material (typical vanadium oxide or amorphous silicon) this temperature change results in a change of the electrical resistance. During readout, electrical power is dissipated in the microbolometer, which increases the temperature continuously. The standard model for the electro-optical simulation of a microbolometer includes the radiation emitted by an observed blackbody, radiation emitted by the substrate, radiation emitted by the microbolometer itself to the surrounding, a heat loss through the legs which connect the microbolometer electrically and mechanically to the substrate, and the electrical power dissipation during readout of the microbolometer (Wood, 1997). The improved model presented in this paper takes a closer look on additional radiation effects in a real IR camera system, for example the radiation emitted by the casing and the lens. The proposed model will consider that some parts of the radiation that is reflected from the casing and the substrate is also absorbed by the microbolometer. Finally, the proposed model will include that some fraction of the radiation is transmitted through the microbolometer at first and then absorbed after the reflection at the surface of the substrate. Compared to the standard model temperature and resistance of the microbolometer can be

  2. Electronically Tunable Differential Integrator: Linear Voltage Controlled Quadrature Oscillator.

    PubMed

    Nandi, Rabindranath; Pattanayak, Sandhya; Venkateswaran, Palaniandavar; Das, Sagarika

    2015-01-01

    A new electronically tunable differential integrator (ETDI) and its extension to voltage controlled quadrature oscillator (VCQO) design with linear tuning law are proposed; the active building block is a composite current feedback amplifier with recent multiplication mode current conveyor (MMCC) element. Recently utilization of two different kinds of active devices to form a composite building block is being considered since it yields a superior functional element suitable for improved quality circuit design. The integrator time constant (τ) and the oscillation frequency (ω o ) are tunable by the control voltage (V) of the MMCC block. Analysis indicates negligible phase error (θ e ) for the integrator and low active ω o -sensitivity relative to the device parasitic capacitances. Satisfactory experimental verifications on electronic tunability of some wave shaping applications by the integrator and a double-integrator feedback loop (DIFL) based sinusoid oscillator with linear f o variation range of 60 KHz~1.8 MHz at low THD of 2.1% are verified by both simulation and hardware tests. PMID:27347537

  3. Analog integrated circuits for the Lotka-Volterra competitive neural networks.

    PubMed

    Asai, T; Ohtani, M; Yonezu, H

    1999-01-01

    A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV IC's agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches.

  4. A UVLO Circuit in SiC Compatible with Power MOSFET Integration (pending entry)

    SciTech Connect

    Ericson, Milton Nance; Frank, Steven Shane; Glover, Dr. Michael; Britton, Charles; Francis, Dr. Matt; Mantooth, Alan; Marlino, Laura D; Mcnutt, Tyler; Mudholkar, Dr. Mihir; Shepherd, Dr. Paul; Whitaker, Mr. Bret; Barkley, Dr. Adam; Lotstetter, Alex

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data show the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  5. A UVLO Circuit in SiC Compatible with Power MOSFET Integration

    SciTech Connect

    Glover, Michael; Shepherd, Paul; Francis, Matt; Mudholkar, Dr. Mihir; Mantooth, Alan; Ericson, Milton Nance; Frank, Steven; Britton Jr, Charles L; Marlino, Laura D; Mcnutt, Tyler; Barkley, Dr. Adam; Whitaker, Mr. Bret; Lostetter, Dr. Alex

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data shows the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  6. The stabilized supralinear network: A unifying circuit motif underlying multi-input integration in sensory cortex

    PubMed Central

    Rubin, Daniel B.; Van Hooser, Stephen D.; Miller, Kenneth D.

    2014-01-01

    Summary Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression: modulatory contextual stimuli suppress responses to driving stimuli; (2) “normalization”: responses to multiple driving stimuli add sublinearly. These properties depend on input strength: for weak driving stimuli, contextual influences more weakly suppress or facilitate and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties including the above emerge robustly from four properties of cortical circuitry: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions. PMID:25611511

  7. Electronic Components Subsystems and Equipment: a Compilation

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Developments in electronic components, subsystems, and equipment are summarized. Topics discussed include integrated circuit components and techniques, circuit components and techniques, and cables and connectors.

  8. Exploitation of Unintentional Information Leakage from Integrated Circuits

    ERIC Educational Resources Information Center

    Cobb, William E.

    2011-01-01

    The information leakage of electronic devices, especially those used in cryptographic or other vital applications, represents a serious practical threat to secure systems. While physical implementation attacks have evolved rapidly over the last decade, relatively little work has been done to allow system designers to effectively counter the…

  9. Design of integrated readout circuit with enhanced capacitance mechanism for dual-band infrared detector

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Shiu, Shiuan-Shuo; Liu, Yi-Ting; Tang, Shiang-Feng; Lin, Wen-Jen

    2011-10-01

    This study proposes a solution for an excessive dark current by a sharing capacitor, which avoids output signal distortion due to integration voltage saturation. Integration capacitance can be changed by adding a switch in the pixel circuit, which will increase the capacitance by two times the original. This circuit also provides output functions of either single-band or dual-band by switching to different sensor. This integrated readout circuit design adopts the TSMC 0.35um 2P4M CMOS 5V process, run on a 5V power supply and operated at a 3MHz clock rate. The dual-band pixel circuit uses an interlace structure, the pixel circuit areas of the two wavelengths are both 30um x 30um. The mid-wave and long-wave sensor currents are from 1nA to 2nA and 6nA to 8nA, respectively, and output swing is 2.8V.

  10. Electronic Device of Didactic and Electrometric Interest for the Study of RLC Circuits.

    ERIC Educational Resources Information Center

    Rodriguez, Angel L. Perez; And Others

    1979-01-01

    Presents a method of studying RLC circuits with the help of the oscilloscope in the XYZ mode, complemented by an electronic device which generates a marker-trace on the screen and which is used to measure frequencies without the need of a reference point on the screen. (Author/GA)

  11. Method For Making Electronic Circuits Having Nial And Ni3al Substrates

    DOEpatents

    Deevi, Seetharama C.; Sikka, Vinod K.

    2001-01-30

    A method for making electronic circuit component having improved mechanical properties and thermal conductivity comprises steps of providing NiAl and/or Ni.sub.3 Al, and forming an alumina layer thereupon prior to applying the conductive elements. Additional layers of copper-aluminum alloy or copper further improve mechanical strength and thermal conductivity.

  12. Using Laboratory Experiments and Circuit Simulation IT Tools in an Undergraduate Course in Analog Electronics

    ERIC Educational Resources Information Center

    Baltzis, Konstantinos B.; Koukias, Konstantinos D.

    2009-01-01

    Laboratory-based courses play a significant role in engineering education. Given the role of electronics in engineering and technology, laboratory experiments and circuit simulation IT tools are used in their teaching in several academic institutions. This paper discusses the characteristics and benefits of both methods. The content and structure…

  13. Electronic circuits having NiAl and Ni.sub.3 Al substrates

    DOEpatents

    Deevi, Seetharama C.; Sikka, Vinod K.

    1999-01-01

    An electronic circuit component having improved mechanical properties and thermal conductivity comprises NiAl and/or Ni.sub.3 Al, upon which an alumina layer is formed prior to applying the conductive elements. Additional layers of copper-aluminum alloy or copper further improve mechanical strength and thermal conductivity.

  14. Dissecting neural circuits for multisensory integration and crossmodal processing

    PubMed Central

    Yau, Jeffrey M.; DeAngelis, Gregory C.; Angelaki, Dora E.

    2015-01-01

    We rely on rich and complex sensory information to perceive and understand our environment. Our multisensory experience of the world depends on the brain's remarkable ability to combine signals across sensory systems. Behavioural, neurophysiological and neuroimaging experiments have established principles of multisensory integration and candidate neural mechanisms. Here we review how targeted manipulation of neural activity using invasive and non-invasive neuromodulation techniques have advanced our understanding of multisensory processing. Neuromodulation studies have provided detailed characterizations of brain networks causally involved in multisensory integration. Despite substantial progress, important questions regarding multisensory networks remain unanswered. Critically, experimental approaches will need to be combined with theory in order to understand how distributed activity across multisensory networks collectively supports perception. PMID:26240418

  15. Tunable quantum interference in a 3D integrated circuit.

    PubMed

    Chaboyer, Zachary; Meany, Thomas; Helt, L G; Withford, Michael J; Steel, M J

    2015-04-27

    Integrated photonics promises solutions to questions of stability, complexity, and size in quantum optics. Advances in tunable and non-planar integrated platforms, such as laser-inscribed photonics, continue to bring the realisation of quantum advantages in computation and metrology ever closer, perhaps most easily seen in multi-path interferometry. Here we demonstrate control of two-photon interference in a chip-scale 3D multi-path interferometer, showing a reduced periodicity and enhanced visibility compared to single photon measurements. Observed non-classical visibilities are widely tunable, and explained well by theoretical predictions based on classical measurements. With these predictions we extract Fisher information approaching a theoretical maximum. Our results open a path to quantum enhanced phase measurements.

  16. Recursive multiport schemes for implementing quantum algorithms with photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tabia, Gelo Noel M.

    2016-01-01

    We present recursive multiport schemes for implementing quantum Fourier transforms and the inversion step in Grover's algorithm on an integrated linear optics device. In particular, each scheme shows how to execute a quantum operation on 2 d modes using a pair of circuits for the same operation on d modes. The circuits operate on path-encoded qudits and realize d -dimensional unitary transformations on these states using linear optical networks with O (d2) optical elements. To evaluate the schemes against realistic errors, we ran simulations of proof-of-principle experiments using a simple fabrication model of silicon-based photonic integrated devices that employ directional couplers and thermo-optic modulators for beam splitters and phase shifters, respectively. We find that high-fidelity performance is achievable with our multiport circuits for 2-qubit and 3-qubit quantum Fourier transforms, and for quantum search on four-item and eight-item databases.

  17. Design of readout integrated circuit structure for single and dual band infrared detector with variable integration time

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Shiu, Shiuan-Shuo; Liu, Yi-Ting; Tang, Shiang-Feng; Lin, Wen-Jen

    2011-08-01

    This paper proposes two kinds of readout integrated circuits for column and row interlaced dual-band infrared detectors. The experiments were simulated using TSMC 0.35μm Mixed Signal 2P4M CMOS process and operated at 3MHz clock rate. The pixel dimensions for two kinds of readout integrated circuits were also 30×30μm. The mid-wave and long-wave sense current was set from 1nA to 2nA and 6nA to 8nA, respectively. We designed a 40x16 array for the columns interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 4.68kFPS. The total power consumption was less than 17.6mW. We also designed a 20x32 array for the row interlace readout circuit. The output voltage swing was 2.8V. The frame rate was 2.67kFPS. The total power consumption was less than 11.4mW. The power consumption increased when the column interlace frame rate reached the row interlace frame rate. The row interlace can decrease the layout area by sharing the column stage circuit, but the frame rate will drop to half of the single band frame rate.

  18. Photonic integrated circuit as a picosecond pulse timing discriminator.

    PubMed

    Lowery, Arthur James; Zhuang, Leimeng

    2016-04-18

    We report the first experimental demonstration of a compact on-chip optical pulse timing discriminator that is able to provide an output voltage proportional to the relative timing of two 60-ps input pulses on separate paths. The output voltage is intrinsically low-pass-filtered, so the discriminator forms an interface between high-speed optics and low-speed electronics. Potential applications include timing synchronization of multiple pulse trains as a precursor for optical time-division multiplexing, and compact rangefinders with millimeter dimensions.

  19. Photonic integrated circuit as a picosecond pulse timing discriminator.

    PubMed

    Lowery, Arthur James; Zhuang, Leimeng

    2016-04-18

    We report the first experimental demonstration of a compact on-chip optical pulse timing discriminator that is able to provide an output voltage proportional to the relative timing of two 60-ps input pulses on separate paths. The output voltage is intrinsically low-pass-filtered, so the discriminator forms an interface between high-speed optics and low-speed electronics. Potential applications include timing synchronization of multiple pulse trains as a precursor for optical time-division multiplexing, and compact rangefinders with millimeter dimensions. PMID:27137311

  20. Collective behaviours: from biochemical kinetics to electronic circuits.

    PubMed

    Agliari, Elena; Barra, Adriano; Burioni, Raffaella; Di Biasio, Aldo; Uguzzoni, Guido

    2013-12-10

    In this work we aim to highlight a close analogy between cooperative behaviors in chemical kinetics and cybernetics; this is realized by using a common language for their description, that is mean-field statistical mechanics. First, we perform a one-to-one mapping between paradigmatic behaviors in chemical kinetics (i.e., non-cooperative, cooperative, ultra-sensitive, anti-cooperative) and in mean-field statistical mechanics (i.e., paramagnetic, high and low temperature ferromagnetic, anti-ferromagnetic). Interestingly, the statistical mechanics approach allows a unified, broad theory for all scenarios and, in particular, Michaelis-Menten, Hill and Adair equations are consistently recovered. This framework is then tested against experimental biological data with an overall excellent agreement. One step forward, we consistently read the whole mapping from a cybernetic perspective, highlighting deep structural analogies between the above-mentioned kinetics and fundamental bricks in electronics (i.e. operational amplifiers, flashes, flip-flops), so to build a clear bridge linking biochemical kinetics and cybernetics.

  1. Collective behaviours: from biochemical kinetics to electronic circuits

    NASA Astrophysics Data System (ADS)

    Agliari, Elena; Barra, Adriano; Burioni, Raffaella; di Biasio, Aldo; Uguzzoni, Guido

    2013-12-01

    In this work we aim to highlight a close analogy between cooperative behaviors in chemical kinetics and cybernetics; this is realized by using a common language for their description, that is mean-field statistical mechanics. First, we perform a one-to-one mapping between paradigmatic behaviors in chemical kinetics (i.e., non-cooperative, cooperative, ultra-sensitive, anti-cooperative) and in mean-field statistical mechanics (i.e., paramagnetic, high and low temperature ferromagnetic, anti-ferromagnetic). Interestingly, the statistical mechanics approach allows a unified, broad theory for all scenarios and, in particular, Michaelis-Menten, Hill and Adair equations are consistently recovered. This framework is then tested against experimental biological data with an overall excellent agreement. One step forward, we consistently read the whole mapping from a cybernetic perspective, highlighting deep structural analogies between the above-mentioned kinetics and fundamental bricks in electronics (i.e. operational amplifiers, flashes, flip-flops), so to build a clear bridge linking biochemical kinetics and cybernetics.

  2. 75 FR 16837 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-02

    ... violations of section 337 based upon the importation into the United States, the sale for importation, and the sale within the United States after importation of certain integrated circuits, chipsets, and... an industry in the United States exists as required by subsection (a)(2) of section 337....

  3. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products... With Multiple Heat-Conducting Paths and Products Containing Same, DN 2899; the Commission is soliciting... multiple heat-conducting paths and products containing same. The complaint names as respondents...

  4. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-06-10

    ... Freescale Semiconductor, Inc. of Austin Texas. 75 FR 16837 (Mar. 29, 2010). The complaint alleged violations... Televisions, Media Players, and Cameras; Notice of Commission Determination Not To Review a Final... integrated circuits, chipsets, and products containing same including televisions, media players, and...

  5. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-20

    ... COMMISSION Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice of... Determination and Recommended Determination on Remedy and Bonding in the above-captioned investigation. The Commission is soliciting comments on public interest issues raised by the recommended relief, specifically...

  6. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-09

    ...'') of Tokyo, Japan. 76 FR 58041 (Sept. 19, 2011). The complaint alleges violations of section 337 of the... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof,...

  7. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR......

  8. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    ERIC Educational Resources Information Center

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  9. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-02-14

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR...

  10. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-07

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products Containing Same including Televisions, DN 2860; the Commission is soliciting comments on any public interest issues raised by the...

  11. Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

    NASA Technical Reports Server (NTRS)

    Slaughter, D. W.

    1977-01-01

    A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

  12. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    PubMed

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  13. The Hybrid Integrated Circuit of the ALICE Inner Tracking System upgrade

    NASA Astrophysics Data System (ADS)

    Fiorenza, G.; Manzari, V.; Pastore, C.; Valentino, V.

    2016-01-01

    The upgrade of the Inner Tracking System scheduled during the second long shutdown is an important milestone of the ALICE upgrade and it will provide a high improvement of its performances. In this contribution the smallest operator unit of the detector, the Hybrid Integrated Circuits, is presented.

  14. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    PubMed Central

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  15. Ultraprecise phase manipulation in integrated photonic quantum circuits with generalized directional couplers

    SciTech Connect

    Heilmann, R.; Keil, R.; Gräfe, M.; Nolte, S.; Szameit, A.

    2014-08-11

    We present an innovative approach for ultra-precise phase manipulation in integrated photonic quantum circuits. To this end, we employ generalized directional couplers that utilize a detuning of the propagation constant in optical waveguides by the overlap of adjacent waveguide modes. We demonstrate our findings in experiments with classical as well as quantum light.

  16. Stress-induced voiding study in integrated circuit interconnects

    NASA Astrophysics Data System (ADS)

    Hou, Yuejin; Tan, Cher Ming

    2008-07-01

    An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

  17. Experimentally verified inductance extraction and parameter study for superconductive integrated circuit wires crossing ground plane holes

    NASA Astrophysics Data System (ADS)

    Fourie, Coenrad J.; Wetzstein, Olaf; Kunert, Juergen; Toepfer, Hannes; Meyer, Hans-Georg

    2013-01-01

    As the complexity of rapid single flux quantum (RSFQ) circuits increases, both current and power consumption of the circuits become important design criteria. Various new concepts such as inductive biasing for energy efficient RSFQ circuits and inductively coupled RSFQ cells for current recycling have been proposed to overcome increasingly severe design problems. Both of these techniques use ground plane holes to increase the inductance or coupling factor of superconducting integrated circuit wires. New design tools are consequently required to handle the new topographies. One important issue in such circuit design is the accurate calculation of networks of inductances even in the presence of finite holes in the ground plane. We show how a fast network extraction method using InductEx, which is a pre- and post-processor for the magnetoquasistatic field solver FastHenry, is used to calculate the inductances of a set of SQUIDs (superconducting quantum interference devices) with ground plane holes of different sizes. The results are compared to measurements of physical structures fabricated with the IPHT Jena 1 kA cm-2 RSFQ niobium process to verify accuracy. We then do a parameter study and derive empirical equations for fast and useful estimation of the inductance of wires surrounded by ground plane holes. We also investigate practical circuits and show excellent accuracy.

  18. Development of high-performance printed organic field-effect transistors and integrated circuits.

    PubMed

    Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

    2015-10-28

    Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

  19. Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

    DOEpatents

    Bellofatto, Ralph E.; Ellavsky, Matthew R.; Gara, Alan G.; Giampapa, Mark E.; Gooding, Thomas M.; Haring, Rudolf A.; Hehenberger, Lance G.; Ohmacht, Martin

    2012-03-20

    An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

  20. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip.

    PubMed

    Li, Xuelian; Zang, Jianfeng; Liu, Yingshuai; Lu, Zhisong; Li, Qing; Li, Chang Ming

    2013-04-10

    An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

  1. A Broadband Polyvinylidene Difluoride-Based Hydrophone with Integrated Readout Circuit for Intravascular Photoacoustic Imaging.

    PubMed

    Daeichin, Verya; Chen, Chao; Ding, Qing; Wu, Min; Beurskens, Robert; Springeling, Geert; Noothout, Emile; Verweij, Martin D; van Dongen, Koen W A; Bosch, Johan G; van der Steen, Antonius F W; de Jong, Nico; Pertijs, Michiel; van Soest, Gijs

    2016-05-01

    Intravascular photoacoustic (IVPA) imaging can visualize the coronary atherosclerotic plaque composition on the basis of the optical absorption contrast. Most of the photoacoustic (PA) energy of human coronary plaque lipids was found to lie in the frequency band between 2 and 15 MHz requiring a very broadband transducer, especially if a combination with intravascular ultrasound is desired. We have developed a broadband polyvinylidene difluoride (PVDF) transducer (0.6 × 0.6 mm, 52 μm thick) with integrated electronics to match the low capacitance of such a small polyvinylidene difluoride element (<5 pF/mm(2)) with the high capacitive load of the long cable (∼100 pF/m). The new readout circuit provides an output voltage with a sensitivity of about 3.8 μV/Pa at 2.25 MHz. Its response is flat within 10 dB in the range 2 to 15 MHz. The root mean square (rms) output noise level is 259 μV over the entire bandwidth (1-20 MHz), resulting in a minimum detectable pressure of 30 Pa at 2.25 MHz.

  2. Massively Parallel, Molecular Analysis Platform Developed Using a CMOS Integrated Circuit With Biological Nanopores

    PubMed Central

    Roever, Stefan

    2012-01-01

    A massively parallel, low cost molecular analysis platform will dramatically change the nature of protein, molecular and genomics research, DNA sequencing, and ultimately, molecular diagnostics. An integrated circuit (IC) with 264 sensors was fabricated using standard CMOS semiconductor processing technology. Each of these sensors is individually controlled with precision analog circuitry and is capable of single molecule measurements. Under electronic and software control, the IC was used to demonstrate the feasibility of creating and detecting lipid bilayers and biological nanopores using wild type α-hemolysin. The ability to dynamically create bilayers over each of the sensors will greatly accelerate pore development and pore mutation analysis. In addition, the noise performance of the IC was measured to be 30fA(rms). With this noise performance, single base detection of DNA was demonstrated using α-hemolysin. The data shows that a single molecule, electrical detection platform using biological nanopores can be operationalized and can ultimately scale to millions of sensors. Such a massively parallel platform will revolutionize molecular analysis and will completely change the field of molecular diagnostics in the future.

  3. Laser dynamics: The system dynamics and network theory of optoelectronic integrated circuit design

    NASA Astrophysics Data System (ADS)

    Tarng, Tom Shinming-T. K.

    Laser dynamics is the system dynamics, communication and network theory for the design of opto-electronic integrated circuit (OEIC). Combining the optical network theory and optical communication theory, the system analysis and design for the OEIC fundamental building blocks is considered. These building blocks include the direct current modulation, inject light modulation, wideband filter, super-gain optical amplifier, E/O and O/O optical bistability and current-controlled optical oscillator. Based on the rate equations, the phase diagram and phase portrait analysis is applied to the theoretical studies and numerical simulation. The OEIC system design methodologies are developed for the OEIC design. Stimulating-field-dependent rate equations are used to model the line-width narrowing/broadening mechanism for the CW mode and frequency chirp of semiconductor lasers. The momentary spectra are carrier-density-dependent. Furthermore, the phase portrait analysis and the nonlinear refractive index is used to simulate the single mode frequency chirp. The average spectra of chaos, period doubling, period pulsing, multi-loops and analog modulation are generated and analyzed. The bifurcation-chirp design chart with modulation depth and modulation frequency as parameters is provided for design purpose.

  4. A Broadband Polyvinylidene Difluoride-Based Hydrophone with Integrated Readout Circuit for Intravascular Photoacoustic Imaging.

    PubMed

    Daeichin, Verya; Chen, Chao; Ding, Qing; Wu, Min; Beurskens, Robert; Springeling, Geert; Noothout, Emile; Verweij, Martin D; van Dongen, Koen W A; Bosch, Johan G; van der Steen, Antonius F W; de Jong, Nico; Pertijs, Michiel; van Soest, Gijs

    2016-05-01

    Intravascular photoacoustic (IVPA) imaging can visualize the coronary atherosclerotic plaque composition on the basis of the optical absorption contrast. Most of the photoacoustic (PA) energy of human coronary plaque lipids was found to lie in the frequency band between 2 and 15 MHz requiring a very broadband transducer, especially if a combination with intravascular ultrasound is desired. We have developed a broadband polyvinylidene difluoride (PVDF) transducer (0.6 × 0.6 mm, 52 μm thick) with integrated electronics to match the low capacitance of such a small polyvinylidene difluoride element (<5 pF/mm(2)) with the high capacitive load of the long cable (∼100 pF/m). The new readout circuit provides an output voltage with a sensitivity of about 3.8 μV/Pa at 2.25 MHz. Its response is flat within 10 dB in the range 2 to 15 MHz. The root mean square (rms) output noise level is 259 μV over the entire bandwidth (1-20 MHz), resulting in a minimum detectable pressure of 30 Pa at 2.25 MHz. PMID:26856788

  5. Power Management Integrated Circuit for Indoor Photovoltaic Energy Harvesting System

    NASA Astrophysics Data System (ADS)

    Jain, Vipul

    In today's world, power dissipation is a main concern for battery operated mobile devices. Key design decisions are being governed by power rather than area/delay because power requirements are growing more stringent every year. Hence, a hybrid power management system is proposed, which uses both a solar panel to harvest energy from indoor lighting and a battery to power the load. The system tracks the maximum power point of the solar panel and regulates the battery and microcontroller output load voltages through the use of an on-chip switched-capacitor DC-DC converter. System performance is verified through simulation at the 180nm technology node and is made to be integrated on-chip with 0.25 second startup time, 79% efficiency, --8/+14% ripple on the load, an average 1micro A of quiescent current (3.7micro W of power) and total on-chip area of 1.8mm2 .

  6. Towards Photonic-Plasmonic Integrated Circuits: Study and Fabrication Of Electrically-Pumped Plasmonic Nano-Laser

    NASA Astrophysics Data System (ADS)

    Hseih, Chunhan Michael

    For the next generation of optical communication, Photonic Integrated Circuits (PIC) and optoelectronic integrated circuits has been of great interest because of the possibility of integrating multiple optical components and electronics together to give high performance opto-electronic system on a small chip that can be produced cost-effectively. Integrated semiconductor laser, as the main light source for generating signals in optical communications, is one of the most important function on a photonic integrated circuit. In the recent advancements in nanophotonics, strong confinement of light in strongly-guiding optical waveguide structure comparing to conventional structures, has been used to improve certain performances of on-chip semiconductor lasers and miniaturize the laser device sizes. However, compared to electronics, even with use of nanophotonic device technology, optoelectronic device footprints are still relatively large due to the diffraction limit of light, which poses a limit on the sizes of optoelectronic devices. Plasmonic photonic device area has been an intensive field of research that utilizes plamonic photonic waveguides to confine light smaller than the diffraction limit through the effect of surface plasmon polariton, a coupling between photons and plasmon along a metal-dielectric interface. In this dissertation, an electrically pumped Plasmonic nanolaser has been designed using 2D-FDTD simulation. The nanolaser has the potential of lasing utilizing achievable optical gain in the typical compound (group III-V) semiconductor materials. The laser electrical pumping structure is compatible with device integration on silicon photonics platform utilizing silicon-on-insulator (SOI) substrate. Electrically pumped thin film based laser structure is shown to be realizable with the use of TCO material as transparent electrodes on the waveguide cladding. Indium oxide (In2O3) and Zinc-Indium-Tin-Oxide (ZITO) deposited by ion-beam-assisted deposition

  7. Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

    NASA Technical Reports Server (NTRS)

    1972-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

  8. Electronic Circuit Experiments and SPICE Simulation of Double Covering Bifurcation of 2-Torus Quasi-Periodic Flow in Phase-Locked Loop Circuit

    NASA Astrophysics Data System (ADS)

    Kamiyama, Kyohei; Endo, Tetsuro; Imai, Isao; Komuro, Motomasa

    2016-06-01

    Double covering (DC) bifurcation of a 2-torus quasi-periodic flow in a phase-locked loop circuit was experimentally investigated using an electronic circuit and via SPICE simulation; in the circuit, the input radio-frequency signal was frequency modulated by the sum of two asynchronous sinusoidal baseband signals. We observed both DC and period-doubling bifurcations of a discrete map on two Poincaré sections, which were realized by changing the sample timing from one baseband sinusoidal signal to the other. The results confirm the DC bifurcation of the original flow.

  9. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    NASA Technical Reports Server (NTRS)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  10. Enhancing and inhibiting stimulated Brillouin scattering in photonic integrated circuits

    PubMed Central

    Merklein, Moritz; Kabakova, Irina V.; Büttner, Thomas F. S.; Choi, Duk-Yong; Luther-Davies, Barry; Madden, Stephen J.; Eggleton, Benjamin J.

    2015-01-01

    On-chip nonlinear optics is a thriving research field, which creates transformative opportunities for manipulating classical or quantum signals in small-footprint integrated devices. Since the length scales are short, nonlinear interactions need to be enhanced by exploiting materials with large nonlinearity in combination with high-Q resonators or slow-light structures. This, however, often results in simultaneous enhancement of competing nonlinear processes, which limit the efficiency and can cause signal distortion. Here, we exploit the frequency dependence of the optical density-of-states near the edge of a photonic bandgap to selectively enhance or inhibit nonlinear interactions on a chip. We demonstrate this concept for one of the strongest nonlinear effects, stimulated Brillouin scattering using a narrow-band one-dimensional photonic bandgap structure: a Bragg grating. The stimulated Brillouin scattering enhancement enables the generation of a 15-line Brillouin frequency comb. In the inhibition case, we achieve stimulated Brillouin scattering free operation at a power level twice the threshold. PMID:25736909

  11. Enhancing and inhibiting stimulated Brillouin scattering in photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Merklein, Moritz; Kabakova, Irina V.; Büttner, Thomas F. S.; Choi, Duk-Yong; Luther-Davies, Barry; Madden, Stephen J.; Eggleton, Benjamin J.

    2015-03-01

    On-chip nonlinear optics is a thriving research field, which creates transformative opportunities for manipulating classical or quantum signals in small-footprint integrated devices. Since the length scales are short, nonlinear interactions need to be enhanced by exploiting materials with large nonlinearity in combination with high-Q resonators or slow-light structures. This, however, often results in simultaneous enhancement of competing nonlinear processes, which limit the efficiency and can cause signal distortion. Here, we exploit the frequency dependence of the optical density-of-states near the edge of a photonic bandgap to selectively enhance or inhibit nonlinear interactions on a chip. We demonstrate this concept for one of the strongest nonlinear effects, stimulated Brillouin scattering using a narrow-band one-dimensional photonic bandgap structure: a Bragg grating. The stimulated Brillouin scattering enhancement enables the generation of a 15-line Brillouin frequency comb. In the inhibition case, we achieve stimulated Brillouin scattering free operation at a power level twice the threshold.

  12. SEMICONDUCTOR DEVICES: A novel high voltage start up circuit for an integrated switched mode power supply

    NASA Astrophysics Data System (ADS)

    Hao, Hu; Xingbi, Chen

    2010-09-01

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.

  13. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    PubMed

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented.

  14. Escherichia coli Flagellar Genes as Target Sites for Integration and Expression of Genetic Circuits

    PubMed Central

    Juhas, Mario; Evans, Lewis D. B.; Frost, Joe; Davenport, Peter W.; Yarkoni, Orr; Fraser, Gillian M.; Ajioka, James W.

    2014-01-01

    E. coli is a model platform for engineering microbes, so genetic circuit design and analysis will be greatly facilitated by simple and effective approaches to introduce genetic constructs into the E. coli chromosome at well-characterised loci. We combined the Red recombinase system of bacteriophage λ and Isothermal Gibson Assembly for rapid integration of novel DNA constructs into the E. coli chromosome. We identified the flagellar region as a promising region for integration and expression of genetic circuits. We characterised integration and expression at four candidate loci, fliD, fliS, fliT, and fliY, of the E. coli flagellar region 3a. The integration efficiency and expression from the four integrations varied considerably. Integration into fliD and fliS significantly decreased motility, while integration into fliT and fliY had only a minor effect on the motility. None of the integrations had negative effects on the growth of the bacteria. Overall, we found that fliT was the most suitable integration site. PMID:25350000

  15. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  16. Silicon-on-insulator-based high-voltage, high-temperature integrated circuit gate driver for silicon carbide-based power field effect transistors

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Blalock, Benjamin J; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  17. Integrating Electronic Information Sources into the Curriculum.

    ERIC Educational Resources Information Center

    Buchanan, Lori E.; And Others

    Integrating the use of technology-based library resources into the curriculum is necessary for students to acquire vital information-seeking skills. Learning to select and use electronic information sources found on CD-ROM, mainframe computers, and via the Internet enables students to function better in today's information society. This paper…

  18. Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Abraham, Billion; Widodo, Arif; Chen, Poki

    2016-06-01

    In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

  19. Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.

    PubMed

    Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

    2014-01-13

    Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use. PMID:24514964

  20. Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.

    PubMed

    Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

    2014-01-13

    Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use.