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Sample records for integrated electronic circuits

  1. ELECTRONIC INTEGRATING CIRCUIT

    DOEpatents

    Englemann, R.H.

    1963-08-20

    An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

  2. Integrated Circuits in the Introductory Electronics Laboratory

    ERIC Educational Resources Information Center

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  3. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  4. Linear integrated circuits

    NASA Astrophysics Data System (ADS)

    Young, T.

    This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.

  5. Advances in the modeling of single electron transistors for the design of integrated circuit.

    PubMed

    Chi, Yaqing; Sui, Bingcai; Yi, Xun; Fang, Liang; Zhou, Hailiang

    2010-09-01

    Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.

  6. System and method for interfacing large-area electronics with integrated circuit devices

    DOEpatents

    Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

    2016-07-12

    A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

  7. Thermionic integrated circuits

    SciTech Connect

    MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.

    1986-01-01

    Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

  8. Active parallel redundancy for electronic integrator-type control circuits

    NASA Technical Reports Server (NTRS)

    Peterson, R. A.

    1971-01-01

    Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

  9. Plasmonic and electronic device-based integrated circuits and their characteristics

    NASA Astrophysics Data System (ADS)

    Sakai, H.; Okahisa, S.; Nakayama, Y.; Nakayama, K.; Fukuhara, M.; Kimura, Y.; Ishii, Y.; Fukuda, M.

    2016-11-01

    This paper presents a plasmonic circuit that has been monolithically integrated with electronic devices on a silicon substrate and then discusses the concept behind this circuit. To form the proposed circuit, two plasmonic waveguides and a detector are integrated with metal-oxide-semiconductor field-effect transistors (MOSFETs) on the substrate. In the circuit, intensity signals or coherent plasmonic signals are generated by coherent light at an operating wavelength at which silicon is transparent, and these signals propagate along the waveguides before they are converted into electrical signals by the detector. These electrical intensity and coherent signals then drive the MOSFETs during both DC and AC operation. The measured performances of the devices indicate that surface plasmon polaritons propagate on the metal surface at the speed of light and drive the electronic devices without any absorption in the silicon.

  10. Electromagnetic Interactions in High-Speed Integrated Electronic Circuits

    DTIC Science & Technology

    1989-03-31

    Sommerfeld integrals using the fast Fourier transform ," Nat. Radio Science (USNC/URSI) Meeting, University of Colorado, Boulder, CO, digest p. 73, Jan...p. 180, Jan. 1989. 3 [12] B. Drachman, M. Cloud, and D. Nyquist, "Accurate evaluation of Sommerfeld integrals using the fast Fourier transform ," to...leads to the transform -domain Hertz potential maintained by currents immersed in the tri-layered environment. The space-domain electric field is recovered

  11. Photonic Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Merritt, Scott; Krainak, Michael

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  12. Electronic control circuits: A compilation

    NASA Technical Reports Server (NTRS)

    1973-01-01

    A compilation of technical R and D information on circuits and modular subassemblies is presented as a part of a technology utilization program. Fundamental design principles and applications are given. Electronic control circuits discussed include: anti-noise circuit; ground protection device for bioinstrumentation; temperature compensation for operational amplifiers; hybrid gatling capacitor; automatic signal range control; integrated clock-switching control; and precision voltage tolerance detector.

  13. Photonic analog-to-digital conversion with electronic-photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Kärtner, F. X.; Amatya, R.; Araghchini, M.; Birge, J.; Byun, H.; Chen, J.; Dahlem, M.; DiLello, N. A.; Gan, F.; Holzwarth, C. W.; Hoyt, J. L.; Ippen, E. P.; Khilo, A.; Kim, J.; Kim, M.; Motamedi, A.; Orcutt, J. S.; Park, M.; Perrott, M.; Popović, M. A.; Ram, R. J.; Smith, H. I.; Zhou, G. R.; Spector, S. J.; Lyszczarz, T. M.; Geis, M. W.; Lennon, D. M.; Yoon, J. U.; Grein, M. E.; Schulein, R. T.

    2008-02-01

    Photonic Analog-to-Digital Conversion (ADC) has a long history. The premise is that the superior noise performance of femtosecond lasers working at optical frequencies enables us to overcome the bottleneck set by jitter and bandwidth of electronic systems and components. We discuss and demonstrate strategies and devices that enable the implementation of photonic ADC systems with emerging electronic-photonic integrated circuits based on silicon photonics. Devices include 2-GHz repetition rate low noise femtosecond fiber lasers, Si-Modulators with up to 20 GHz modulation speed, 20 channel SiN-filter banks, and Ge-photodetectors. Results towards a 40GSa/sec sampling system with 8bits resolution are presented.

  14. An Electronics Course Emphasizing Circuit Design

    ERIC Educational Resources Information Center

    Bergeson, Haven E.

    1975-01-01

    Describes a one-quarter introductory electronics course in which the students use a variety of inexpensive integrated circuits to design and construct a large number of useful circuits. Presents the subject matter of the course in three parts: linear circuits, digital circuits, and more complex circuits. (GS)

  15. Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

    DTIC Science & Technology

    1993-02-10

    new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

  16. Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices

    NASA Astrophysics Data System (ADS)

    Vanhoestenberghe, A.; Donaldson, N.

    2013-06-01

    Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

  17. ELECTRONIC PHASE CONTROL CIRCUIT

    DOEpatents

    Salisbury, J.D.; Klein, W.W.; Hansen, C.F.

    1959-04-21

    An electronic circuit is described for controlling the phase of radio frequency energy applied to a multicavity linear accelerator. In one application of the circuit two cavities are excited from a single radio frequency source, with one cavity directly coupled to the source and the other cavity coupled through a delay line of special construction. A phase detector provides a bipolar d-c output signal proportional to the difference in phase between the voltage in the two cavities. This d-c signal controls a bias supply which provides a d-c output for varying the capacitnce of voltage sensitive capacitors in the delay line. The over-all operation of the circuit is completely electronic, overcoming the time response limitations of the electromechanical control systems, and the relative phase relationship of the radio frequency voltages in the two caviiies is continuously controlled to effect particle acceleration.

  18. Monolithic microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Pucel, R. A.

    Monolithic microwave integrated circuits (MMICs), a new microwave technology which is expected to exert a profound influence on microwave circuit designs for future military systems as well as for the commercial and consumer markets, is discussed. The book contains an historical discussion followed by a comprehensive review presenting the current status in the field. The general topics of the volume are: design considerations, materials and processing considerations, monolithic circuit applications, and CAD, measurement, and packaging techniques. All phases of MMIC technology are covered, from design to testing.

  19. Basic Mechanisms of Radiation Effects on Electronic Materials, Devices, and Integrated Circuits

    DTIC Science & Technology

    1982-08-01

    such changes on de’ ice properties. To gain detailed insight regarding the effects that occur when an integrated circuit is placed in a radiation...the interaction produces energetic free elec- trons. The energy range in which photoelectr~ ic collisions dominate depends on the atomic number Z of...neutron energy dependent, as discussed in Sec- ticn 3.0, this makes it difficult to compare directly results obtained by workers using different radiation

  20. ELECTRONIC TRIGGER CIRCUIT

    DOEpatents

    Russell, J.A.G.

    1958-01-01

    An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

  1. ELECTRONIC MULTIPLIER CIRCUIT

    DOEpatents

    Thomas, R.E.

    1959-08-25

    An electronic multiplier circuit is described in which an output voltage having an amplitude proportional to the product or quotient of the input signals is accomplished in a novel manner which facilitates simplicity of circuit construction and a high degree of accuracy in accomplishing the multiplying and dividing function. The circuit broadly comprises a multiplier tube in which the plate current is proportional to the voltage applied to a first control grid multiplied by the difference between voltage applied to a second control grid and the voltage applied to the first control grid. Means are provided to apply a first signal to be multiplied to the first control grid together with means for applying the sum of the first signal to be multiplied and a second signal to be multiplied to the second control grid whereby the plate current of the multiplier tube is proportional to the product of the first and second signals to be multiplied.

  2. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1990-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  3. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1988-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  4. Bioluminescent bioreporter integrated circuit

    DOEpatents

    Simpson, Michael L.; Sayler, Gary S.; Paulus, Michael J.

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  5. Integrated Circuit Immunity

    NASA Technical Reports Server (NTRS)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  6. Monolithic Optoelectronic Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

    1990-01-01

    Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

  7. Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

    2017-02-01

    Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

  8. Graphene radio frequency receiver integrated circuit.

    PubMed

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  9. Digital integrated circuits

    NASA Astrophysics Data System (ADS)

    Polasek, P.; Halamik, J.

    1984-05-01

    The term semicustom designed integrated circuits denotes integrated circuits of an all purpose character in which the production of chips is completed by using one to three custom design stencil type exposure masks. This involves in most cases interconnecting masks that are used to devise the circuit function desired by the customer. Silicon plates with an all purpose gate matrix are produced up to the interconnection level and can be kept at this phase in storage, after which a customer's specific demands can be met very expediently. All purpose logic fields containing 200 logic gates on a chip and an all purpose chip to be expanded to 1,000 logic gates are discussed. The technology facilitates the devising of fast gates with a delay of approximately 5 ns and power dissipation of 1 mW. In assembly it will be possible to make use of the entire assortment of the currently used casings with 16, 18, 20, 24, 28 and 40 outlets. In addition to the development of the mentioned technology, a general methodology for design of the mentioned gate fields is currently under way.

  10. Silicon/III-V laser with super-compact diffraction grating for WDM applications in electronic-photonic integrated circuits.

    PubMed

    Wang, Yadong; Wei, Yongqiang; Huang, Yingyan; Tu, Yongming; Ng, Doris; Lee, Cheewei; Zheng, Yunan; Liu, Boyang; Ho, Seng-Tiong

    2011-01-31

    We have demonstrated a heterogeneously integrated III-V-on-Silicon laser based on an ultra-large-angle super-compact grating (SCG). The SCG enables single-wavelength operation due to its high-spectral-resolution aberration-free design, enabling wavelength division multiplexing (WDM) applications in Electronic-Photonic Integrated Circuits (EPICs). The SCG based Si/III-V laser is realized by fabricating the SCG on silicon-on-insulator (SOI) substrate. Optical gain is provided by electrically pumped heterogeneous integrated III-V material on silicon. Single-wavelength lasing at 1550 nm with an output power of over 2 mW and a lasing threshold of around 150 mA were achieved.

  11. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  12. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  13. ELECTRONIC PULSE SCALING CIRCUITS

    DOEpatents

    Cooke-Yarborough, E.H.

    1958-11-18

    Electronic pulse scaling circults of the klnd comprlsing a serles of bi- stable elements connected ln sequence, usually in the form of a rlng so as to be cycllcally repetitive at the highest scallng factor, are described. The scaling circuit comprises a ring system of bi-stable elements each arranged on turn-off to cause, a succeeding element of the ring to be turned-on, and one being arranged on turn-off to cause a further element of the ring to be turned-on. In addition, separate means are provided for applying a turn-off pulse to all the elements simultaneously, and for resetting the elements to a starting condition at the end of each cycle.

  14. Monolithic Lumped Element Integrated Circuit (M2LEIC) Transistors.

    DTIC Science & Technology

    INTEGRATED CIRCUITS, *MONOLITHIC STRUCTURES(ELECTRONICS), *TRANSISTORS, CHIPS(ELECTRONICS), FABRICATION, EPITAXIAL GROWTH, ULTRAHIGH FREQUENCY, POLYSILICONS, PHOTOLITHOGRAPHY, RADIOFREQUENCY POWER, IMPEDANCE MATCHING .

  15. Integrated Circuit Computer Analysis.

    DTIC Science & Technology

    information on this topic. The most important findings were the method used to identify combinational circuits ( Quine - McCluskey algorithm) and a clearly...defined set of limits on the problem of identifying sequential circuits. Since the Quine - McCluskey algorithm works only for combinational circuits, an

  16. Parallelism in integrated fluidic circuits

    NASA Astrophysics Data System (ADS)

    Bousse, Luc J.; Kopf-Sill, Anne R.; Parce, J. W.

    1998-04-01

    Many research groups around the world are working on integrated microfluidics. The goal of these projects is to automate and integrate the handling of liquid samples and reagents for measurement and assay procedures in chemistry and biology. Ultimately, it is hoped that this will lead to a revolution in chemical and biological procedures similar to that caused in electronics by the invention of the integrated circuit. The optimal size scale of channels for liquid flow is determined by basic constraints to be somewhere between 10 and 100 micrometers . In larger channels, mixing by diffusion takes too long; in smaller channels, the number of molecules present is so low it makes detection difficult. At Caliper, we are making fluidic systems in glass chips with channels in this size range, based on electroosmotic flow, and fluorescence detection. One application of this technology is rapid assays for drug screening, such as enzyme assays and binding assays. A further challenge in this area is to perform multiple functions on a chip in parallel, without a large increase in the number of inputs and outputs. A first step in this direction is a fluidic serial-to-parallel converter. Fluidic circuits will be shown with the ability to distribute an incoming serial sample stream to multiple parallel channels.

  17. Modular electron transfer circuits for synthetic biology

    PubMed Central

    Agapakis, Christina M

    2010-01-01

    Electron transfer is central to a wide range of essential metabolic pathways, from photosynthesis to fermentation. The evolutionary diversity and conservation of proteins that transfer electrons makes these pathways a valuable platform for engineered metabolic circuits in synthetic biology. Rational engineering of electron transfer pathways containing hydrogenases has the potential to lead to industrial scale production of hydrogen as an alternative source of clean fuel and experimental assays for understanding the complex interactions of multiple electron transfer proteins in vivo. We designed and implemented a synthetic hydrogen metabolism circuit in Escherichia coli that creates an electron transfer pathway both orthogonal to and integrated within existing metabolism. The design of such modular electron transfer circuits allows for facile characterization of in vivo system parameters with applications toward further engineering for alternative energy production. PMID:21468209

  18. Thermally controlled coupling of a rolled-up microtube integrated with a waveguide on a silicon electronic-photonic integrated circuit.

    PubMed

    Zhong, Qiuhang; Tian, Zhaobing; Veerasubramanian, Venkat; Dastjerdi, M Hadi Tavakoli; Mi, Zetian; Plant, David V

    2014-05-01

    We report on the first experimental demonstration of the thermal control of coupling strength between a rolled-up microtube and a waveguide on a silicon electronic-photonic integrated circuit. The microtubes are fabricated by selectively releasing a coherently strained GaAs/InGaAs heterostructure bilayer. The fabricated microtubes are then integrated with silicon waveguides using an abruptly tapered fiber probe. By tuning the gap between the microtube and the waveguide using localized heaters, the microtube-waveguide evanescent coupling is effectively controlled. With heating, the extinction ratio of a microtube whispering-gallery mode changes over an 18 dB range, while the resonant wavelength remains approximately unchanged. Utilizing this dynamic thermal tuning effect, we realize coupling modulation of the microtube integrated with the silicon waveguide at 2 kHz with a heater voltage swing of 0-6 V.

  19. Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design

    DTIC Science & Technology

    2012-10-01

    Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design by John E. Penn ARL-TR-6237 October 2012...Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design John E. Penn Sensors and Electron Devices Directorate, ARL...TITLE AND SUBTITLE Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c

  20. Scaling of graphene integrated circuits

    NASA Astrophysics Data System (ADS)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A.; Pop, Eric; Sordan, Roman

    2015-04-01

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing. Electronic supplementary information (ESI) available: Discussions on the cutoff frequency fT, the maximum frequency of oscillation fmax, and the intrinsic gate delay CV/I. See DOI: 10.1039/c5nr01126d

  1. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

    PubMed

    De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm(2) area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  2. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    NASA Astrophysics Data System (ADS)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  3. Progress in organic integrated circuit manufacture

    NASA Astrophysics Data System (ADS)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  4. Military Curricula for Vocational & Technical Education. Basic Electricity and Electronics. CANTRAC A-100-0010. Module 34: Linear Integrated Circuits. Study Booklet.

    ERIC Educational Resources Information Center

    Chief of Naval Education and Training Support, Pensacola, FL.

    This individualized learning module on linear integrated circuits is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Two lessons are included in…

  5. Variational integrators for electric circuits

    SciTech Connect

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  6. Displacement Damage in Bipolar Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  7. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  8. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2010-01-01

    The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

  9. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  10. Integrated Circuit Stellar Magnitude Simulator

    ERIC Educational Resources Information Center

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  11. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  12. MOS integrated circuit fault modeling

    NASA Technical Reports Server (NTRS)

    Sievers, M.

    1985-01-01

    Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

  13. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  14. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  15. Microfluidic photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

    2008-11-01

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled twodimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1- 10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments.

  16. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  17. Integrated circuits, and design and manufacture thereof

    DOEpatents

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  18. Simple photometer circuits using modular electronic components

    NASA Technical Reports Server (NTRS)

    Wampler, J. E.

    1975-01-01

    Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

  19. Integrated acoustooptic circuits and applications.

    PubMed

    Tsai, C S

    1992-01-01

    The recent development of titanium-indiffusion proton-exchange (TIPE) microlenses and lens arrays has made possible the construction of a variety of single- and multichannel integrated acoustooptic (AO) and acoustooptic-electrooptic (EO) circuits in LiNbO(3) channel-planar waveguides 0.1x1.0x2.0 cm(3) in size. These hybrid AO and AO-EO circuits can be fabricated through compatible and well-established technologies. The most recent realization of ion-milled microlenses and lens arrays together with the recent development of gigahertz AO Bragg modulators and EO Bragg modulator arrays have also paved the way for construction of similar but monolithic AO and AO-EO GaAs/GaAlAs waveguides of comparable size. Both types of integrated AO and AO-EO circuits suggest versatile applications in communications signal processing, and computing. Efficient and simultaneous excitation of the channel waveguide array using an ion-milled planar microlens array has facilitated the demonstration of some of these applications.

  20. Removing Bonded Integrated Circuits From Boards

    NASA Technical Reports Server (NTRS)

    Rice, John T.

    1989-01-01

    Small resistance heater makes it easier, faster, and cheaper to remove integrated circuit from hybrid-circuit board, package, or other substrate for rework. Heater, located directly in polymeric bond interface or on substrate under integrated-circuit chip, energized when necessary to remove chip. Heat generated softens adhesive or solder that bonds chip to substrate. Chip then lifted easily from substrate.

  1. Electronic test and calibration circuits, a compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    A wide variety of simple test calibration circuits are compiled for the engineer and laboratory technician. The majority of circuits were found inexpensive to assemble. Testing electronic devices and components, instrument and system test, calibration and reference circuits, and simple test procedures are presented.

  2. Silicon photonic devices for optoelectronic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tien, Ming-Chun

    Electronic and photonic integrated circuits use optics to overcome bottlenecks of microelectronics in bandwidth and power consumption. Silicon photonic devices such as optical modulators, filters, switches, and photodetectors have being developed for integration with electronics based on existing complementary metal-oxide-semiconductor (CMOS) circuits. An important building block of photonic devices is the optical microresonator. On-chip whispering-gallery-mode optical resonators such as microdisks, microtoroids, and microrings have very small footprint, and thus are suitable for large scale integration. Micro-electro-mechanical system (MEMS) technology enables dynamic control and tuning of optical functions. In this dissertation, microring resonators with tunable power coupling ratio using MEMS electrostatic actuators are demonstrated. The fabrication is compatible with CMOS. By changing the physical gap spacing between the waveguide coupler and the microring, the quality factor of the microring can be tuned from 16,300 to 88,400. Moreover, we have demonstrated optical switches and tunable optical add-drop filters with an optical bandwidth of 10 GHz and an extinction ratio of 20 dB. Potentially, electronic control circuits can also be integrated. To realize photonic integrated circuits on silicon, electrically-pumped silicon lasers are desirable. However, because of the indirect bandgap, silicon is a poor material for light emission compared with direct-bandgap III-V compound semiconductors. Heterogeneous integration of III-V semiconductor lasers on silicon is an alternative to provide on-chip light sources. Using a room-temperature, post-CMOS optofluidic assembly technique, we have experimentally demonstrated an InGaAsP microdisk laser integrated with silicon waveguides. Pre-fabricated InGaAsP microdisk lasers were fluidically assembled and aligned to the silicon waveguides on silicon-on-insulator (SOI) with lithographic alignment accuracy. The assembled

  3. Electronic circuits: A compilation. [for electronic equipment in telecommunication

    NASA Technical Reports Server (NTRS)

    1976-01-01

    A compilation containing articles on newly developed electronic circuits and systems is presented. It is divided into two sections: (1) section 1 on circuits and techniques of particular interest in communications technology, and (2) section 2 on circuits designed for a variety of specific applications. The latest patent information available is also given. Circuit diagrams are shown.

  4. Electronic switches and control circuits: A compilation

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The innovations in this updated series of compilations dealing with electronic technology represents a carefully selected collection of items on electronic switches and control circuits. Most of the items are based on well-known circuit design concepts that have been simplified or refined to meet NASA's demanding requirement for reliability, simplicity, fail-safe characteristics, and the capability of withstanding environmental extremes.

  5. Fabrication process of superconducting integrated circuits with submicron Nb/AlOx/Nb junctions using electron-beam direct writing technique

    NASA Astrophysics Data System (ADS)

    Aoyagi, Masahiro; Nakagawa, Hiroshi

    1997-07-01

    For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

  6. Isolation of Battery Chargers Integrated Into Printed Circuit Boards

    SciTech Connect

    Sullivan, James S.

    2013-11-21

    Present test procedures developed by the Federal Government (10 CFR Part 430 “Energy Conservation Program for Consumer Products”) to measure the energy consumption of battery chargers provide no method for the isolation of input power for battery chargers that have been integrated into printed circuit boards internal to electronic equipment. This prevents the measurement of Standby and Off Mode energy consumption. As a result, the energy consumption of battery chargers integrated into the printed circuit board cannot be measured.

  7. Control of exciton fluxes in an excitonic integrated circuit.

    PubMed

    High, Alex A; Novitskaya, Ekaterina E; Butov, Leonid V; Hanson, Micah; Gossard, Arthur C

    2008-07-11

    Efficient signal communication uses photons. Signal processing, however, uses an optically inactive medium, electrons. Therefore, an interconnection between electronic signal processing and optical communication is required at the integrated circuit level. We demonstrated control of exciton fluxes in an excitonic integrated circuit. The circuit consists of three exciton optoelectronic transistors and performs operations with exciton fluxes, such as directional switching and merging. Photons transform into excitons at the circuit input, and the excitons transform into photons at the circuit output. The exciton flux from the input to the output is controlled by a pattern of the electrode voltages. The direct coupling of photons, used in communication, to excitons, used as the device-operation medium, may lead to the development of efficient exciton-based optoelectronic devices.

  8. Electronic circuits for communications systems: A compilation

    NASA Technical Reports Server (NTRS)

    1972-01-01

    The compilation of electronic circuits for communications systems is divided into thirteen basic categories, each representing an area of circuit design and application. The compilation items are moderately complex and, as such, would appeal to the applications engineer. However, the rationale for the selection criteria was tailored so that the circuits would reflect fundamental design principles and applications, with an additional requirement for simplicity whenever possible.

  9. Oxide bipolar electronics: materials, devices and circuits

    NASA Astrophysics Data System (ADS)

    Grundmann, Marius; Klüpfel, Fabian; Karsthof, Robert; Schlupp, Peter; Schein, Friedrich-Leonhard; Splith, Daniel; Yang, Chang; Bitter, Sofie; von Wenckstern, Holger

    2016-06-01

    We present the history of, and the latest progress in, the field of bipolar oxide thin film devices. As such we consider primarily pn-junctions in which at least one of the materials is a metal oxide semiconductor. A wide range of n-type and p-type oxides has been explored for the formation of such bipolar diodes. Since most oxide semiconductors are unipolar, challenges and opportunities exist with regard to the formation of heterojunction diodes and band lineups. Recently, various approaches have led to devices with high rectification, namely p-type ZnCo2O4 and NiO on n-type ZnO and amorphous zinc-tin-oxide. Subsequent bipolar devices and applications such as photodetectors, solar cells, junction field-effect transistors and integrated circuits like inverters and ring oscillators are discussed. The tremendous progress shows that bipolar oxide electronics has evolved from the exploration of various materials and heterostructures to the demonstration of functioning integrated circuits. Therefore a viable, facile and high performance technology is ready for further exploitation and performance optimization.

  10. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  11. Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers - 2nd Pass Correction

    DTIC Science & Technology

    2013-09-01

    Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers—2nd Pass Correction by John E. Penn ARL-TN-0580 September 2013...September 2013 Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers—2nd Pass Correction John E. Penn Sensors and Electron...COVERED (From - To) 4. TITLE AND SUBTITLE Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers–2nd Pass Correction 5a. CONTRACT NUMBER

  12. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  13. Integrated-Circuit Pseudorandom-Number Generator

    NASA Technical Reports Server (NTRS)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  14. Reusable vibration resistant integrated circuit mounting socket

    DOEpatents

    Evans, Craig N.

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  15. Reusable vibration resistant integrated circuit mounting socket

    SciTech Connect

    Evans, C.N.

    1993-12-31

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  16. Reverse engineering of integrated circuits

    DOEpatents

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  17. Maxwell's demons realized in electronic circuits

    NASA Astrophysics Data System (ADS)

    Koski, Jonne V.; Pekola, Jukka P.

    2016-12-01

    We review recent progress in making the former gedanken experiments of Maxwell's demon [1] into real experiments in a lab. In particular, we focus on realizations based on single-electron tunneling in electronic circuits. We first present how stochastic thermodynamics can be investigated in these circuits. Next we review recent experiments on an electron-based Szilard engine. Finally, we report on experiments on single-electron tunneling-based cooling, overviewing the recent realization of a Coulomb gap refrigerator, as well as an autonomous Maxwell's demon.

  18. Electron Beam/Optical Hybrid Lithography For The Production Of Gallium Arsenide Monolithic Microwave Integrated Circuits (Mimics)

    NASA Astrophysics Data System (ADS)

    Nagarajan, Rao M.; Rask, Steven D.

    1988-06-01

    A hybrid lithography technique is described in which selected levels are fabricated by high resolution direct write electron beam lithography and all other levels are fabricated optically. This technique permits subhalf micron geometries and the site-by-site alignment for each field written by electron beam lithography while still maintaining the high throughput possible with optical lithography. The goal is to improve throughput and reduce overall cost of fabricating MIMIC GaAS chips without compromising device performance. The lithography equipment used for these experiments is the Cambridge Electron beam vector scan system EBMF 6.4 capable of achieving ultra high current densities with a beam of circular cross section and a gaussian intensity profile operated at 20 kev. The optical aligner is a Karl Suss Contact aligner. The flexibility of the Cambridge electron beam system is matched to the less flexible Karl Suss contact aligner. The lithography related factors, such as image placement, exposure and process related analyses, which influence overlay, pattern quality and performance, are discussed. A process chip containing 3.2768mm fields in an eleven by eleven array was used for alignment evaluation on a 3" semi-insulating GaAS wafer. Each test chip contained five optical verniers and four Prometrix registration marks per field along with metal bumps for alignment marks. The process parameters for these chips are identical to those of HEMT/epi-MESFET ohmic contact and gate layer processes. These layers were used to evaluate the overlay accuracy because of their critical alignment and dimensional control requirements. Two cases were examined: (1) Electron beam written gate layers aligned to optically imaged ohmic contact layers and (2) Electron beam written gate layers aligned to electron beam written ohmic contact layers. The effect of substrate charging by the electron beam is also investigated. The resulting peak overlay error accuracies are: (1) Electron

  19. Integrated electronic detection of biomolecules.

    PubMed

    Parviz, Babak A

    2006-09-01

    Electronics offers several unique opportunities for the detection and characterization of biomolecules such as oligonucleotides and proteins. Solid-state microfabrication technology, similar to that used to make integrated circuits, can be employed to make integrated electronic sensing systems that are capable of simultaneously detecting multiple molecules. Here, we review some of the capabilities afforded by electronics for rapid and sensitive detection of biomolecules and discuss a recent demonstration of a multi-marker electronic sensing system for detection of uropathogens in clinical samples.

  20. Research in computer simulation of integrated circuits

    NASA Astrophysics Data System (ADS)

    Newton, A. R.; Pdederson, D. O.

    1983-07-01

    The performance of the new LSI simulator CLASSIE is evaluated on several circuits with a few hundred to over one thousand semiconductor devices. A more accurate run time prediction formula has been found to be appropriate for circuit simulators. The design decisions for optimal performance under the constraints of the hardware (CRAY-1) are presented. Vector computers have an increased potential for fast, accurate simulation at the transistor level of Large-Scale-Integrated Circuits. Design considerations for a new circuit simulator are developed based on the specifics of the vector computer architecture and of LSI circuits. The simulation of Large-Scale-Integrated (LSI) circuits requires very long run time on conventional circuit analysis programs such as SPICE2 and super-mini computers. A new simulator for LSI circuits, CLASSIE, which takes advantage of circuit hierarchy and repetitiveness, and array processors capable of high-speed floating-point computation are a promising combination. While a large number of powerful design verfication tools have been developed for IC design at the transistor and logic gate levels, there are very few silicon-oriented tools for architectural design and evaluation.

  1. RF lockout circuit for electronic locking system

    NASA Astrophysics Data System (ADS)

    Becker, Earl M., Jr.; Miller, Allen

    1991-02-01

    An electronics lockout circuit was invented that includes an antenna adapted to receive radio frequency signals from a transmitter, and a radio frequency detector circuit which converts the radio frequency signals into a first direct current voltage indicative of the relative strength of the field resulting from the radio frequency signals. The first direct current voltage is supplied to a trigger circuit which compares this direct current voltage to an adjustable direct current reference voltage. This provides a second direct current voltage at the output whenever the amplitude of the first direct current voltage exceeds the amplitude of the reference voltage provided by the comparator circuit. This is supplied to a disconnect relay circuit which, upon receiving a signal from the electronic control unit of an electronic combination lock during the time period at which the second direct current voltage is present, isolates the door strike coil of a security door from the electronic control unit. This prevents signals falsely generated by the electronic control unit because of radio frequency signals in the vicinity of the electronic control unit energizing the door strike coil and accidentally opening a security door.

  2. Chain Of Test Contacts For Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo

    1989-01-01

    Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

  3. Zipper Connectors for Flexible Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Barnes, Kevin N.

    2003-01-01

    Devices that look and function much like conventional zippers on clothing have been proposed as connectors for flexible electronic circuits. Heretofore, flexible electronic circuits have commonly included rigid connectors like those of conventional rigid electronic circuits. The proposed zipper connectors would make it possible to connect and disconnect flexible circuits quickly and easily. Moreover, the flexibility of zipper connectors would make them more (relative to rigid connectors) compatible with flexible circuits, so that the advantages of flexible circuitry could be realized more fully. Like a conventional zipper, a zipper according to the proposal would include teeth anchored on flexible tapes, a slider with a loosely attached clasp, a box at one end of the rows of mating teeth, and stops at the opposite ends. The tapes would be made of a plastic or other dielectric material. On each of the two mating sides of the zipper, metal teeth would alternate with dielectric (plastic) teeth, there being two metal teeth for each plastic one. When the zipper was closed, each metal tooth from one side would be in mechanical and electrical contact with a designated metal tooth from the other side, and these mating metal teeth would be electrically insulated from the next pair of mating metal teeth by an intervening plastic tooth. The metal teeth would be soldered or crimped to copper tabs. Wires or other conductors connected to electronic circuits would be soldered or crimped to the ends of the tabs opposite the teeth.

  4. Radiation Effects in 3D Integrated SOl SRAM Circuits

    DTIC Science & Technology

    2011-08-23

    Comparing Neutrons and Protons Data Monoenergetic neutrons and protons are used to characterize single event effects in electronics circuits, and are...for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross-section...fabricating circuits for space applications. singIe event effects, SOl, fully depleted, 3D integration, neutron , protons, upset cross-section U U U U SAR

  5. Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene

    NASA Astrophysics Data System (ADS)

    Amani, Matin; Burke, Robert A.; Proie, Robert M.; Dubey, Madan

    2015-03-01

    Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >107 and field effect mobilities as high as 16.4 cm2 V-1 s-1. Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W-1. Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322-1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform.

  6. Self-integration of nanowires into circuits via guided growth.

    PubMed

    Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

    2013-09-17

    The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom-up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel "self-integration" of NWs into electronic circuits and functional systems based on guided growth.

  7. Handbook of microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Hoffmann, Reinmut K.

    The design and operation of ICs for use in the 0.5-20-GHz range are described in an introductory and reference work for industrial engineers. Chapters are devoted to an overview of microwave IC (MIC) technology, general stripline characteristics, microwave transmission line (MTL) parameters for microstrips with isotropic dielectric substrates, higher-order modes on a microstrip, the effects of metallic enclosure on MTL transmission parameters, losses in microstrips, the measurement of MTL parameters, and MTLs on anisotropic dielectric substrates. Consideration is given to coupled microstrips on dielectric substrates, microstrip discontinuities, radiation from microstrip circuits, MTL variations, coplanar MTLs, slotlines, and spurious modes in MTL circuits. Diagrams, drawings, graphs, and a glossary of symbols are provided.

  8. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B.; Bowman, Douglas R.

    1990-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  9. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  10. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B.; Bowman, Douglas R.

    1989-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  11. Integrated logic circuits using single-atom transistors.

    PubMed

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch.

  12. Maximum Temperature Detection System for Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  13. Solution methods for very highly integrated circuits.

    SciTech Connect

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator

  14. Layout techniques for integrated circuits

    SciTech Connect

    Tsay, C.Y.

    1986-01-01

    Several techniques are presented for solving circuit-layout problems. In particular, a channel-placement algorithm is first introduced to reduce the channel density (d) so that a channel router can complete the routing requirements in fewer tracks. A 4-layer channel-routing model is then formulated so that a general channel routing problem (CRP) with cyclic conflicts and long critical paths can be completed with d/2. Finally, the 4-layer, 2-dimensional switchbox routing problem needed to enhance the channel routing in general circuit layout is investigated from the graph-theoretical viewpoint. The channel-placement technique consists of two phases. Using the principle of decomposition, the initial placement phase effectively reduces the complexity of the problem and, therefore, improves the efficiency of the second phase, which is called the iterative improvement placement. The main feature of this phase is its hill-climbing ability to avoid being trapped at local minima. The combination of these two phases leads to an efficient technique for standard cell placement. To utilize multi-layer technology, a new 4-layer channel routing model is introduced to minimize the channel width of more-generalized CRP's. The 2-dimensional switchbox routing problem is transformed to an equivalent graph-theoretical problem.

  15. Printed organic thin-film transistor-based integrated circuits

    NASA Astrophysics Data System (ADS)

    Mandal, Saumen; Noh, Yong-Young

    2015-06-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted.

  16. Modular packaging technique for combining integrated circuits and discrete components

    NASA Technical Reports Server (NTRS)

    Lacchia, J. F.

    1969-01-01

    Technique for packaging electronic modules interconnects integrated circuits and discrete components by means of beryllium-copper strips in a molded diallyphthalate tray. Simple girder-like construction provides ease of assembly, high rigidity, excellent vibration resistance, and good heat dissipation characteristics.

  17. Chemical vapor deposition for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1980-01-01

    Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

  18. General Electronics Technician: Semiconductor Devices and Circuits.

    ERIC Educational Resources Information Center

    Hilley, Robert

    These instructional materials include a teacher's guide designed to assist instructors in organizing and presenting an introductory course in general electronics focusing on semiconductor devices and circuits and a student guide. The materials are based on the curriculum-alignment concept of first stating the objectives, developing instructional…

  19. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  20. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  1. Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

    NASA Technical Reports Server (NTRS)

    Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

    1995-01-01

    Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

  2. Laboratory experiments in integrated circuit fabrication

    NASA Technical Reports Server (NTRS)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-01-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  3. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  4. Microwave integrated circuit for Josephson voltage standards

    NASA Technical Reports Server (NTRS)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  5. Exciton-polariton integrated circuits

    NASA Astrophysics Data System (ADS)

    Liew, T. C. H.; Kavokin, A. V.; Ostatnický, T.; Kaliteevski, M.; Shelykh, I. A.; Abram, R. A.

    2010-07-01

    We show that logical signals encoded in bistable states in semiconductor microcavities can be generated and controlled electronically by exploiting the electrical sensitivity of Tamm-plasmon-exciton-polariton modes. The signals can be transported along polariton neurons, created with a patterned metal surface. Using the Gross-Pitaevskii equations, we simulate an electrically controlled transistor and find that high repetition rates (10 GHz) are possible.

  6. Enhancements to - and Submillimetre - Integrated Circuit Receivers.

    NASA Astrophysics Data System (ADS)

    Veidt, Bruce George

    1995-01-01

    An important area of radio astronomy instrumentation is the development of sensitive receivers at millimetre - and submillimetre-wavelengths. Over the last decade, there has been steady progress in advancing the technology from using receivers based on mechanically machined waveguides and horn antennas to transmission lines and antennas fabricated using integrated circuit techniques. The motivation has been to simplify the fabrication of the receivers through the use of photolithography and etching. It is hoped that this will eventually lead to the development of focal plane arrays, which have many elements placed side-by-side forming a radio camera. The first part of this thesis addresses one of the problems with the integrated circuit technology, namely the fixed nature of the circuits, by examining one type of electrically-adjustable tuning. In those experiments, the bias voltage was modulated across the active device so as to change its tuning. Unfortunately the tuning effect was severely limited by the electrical nonlinearity of the device. Another part of this thesis builds upon the integrated nature of modern receivers by adding what, up until now, has been an external component: the Josephson effect suppression electromagnet. This technique will allow the receiving elements to be much simpler and smaller than would otherwise be the case. Finally, the last part of this thesis examines another method of constructing antennas and transmission lines using integrated circuit techniques. This work shows the feasibility of integrating a waveguide fabricated with integrated circuit technology with a diagonal horn antenna. This technique will provide another option for receiver designers.

  7. Package Holds Five Monolithic Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  8. Designing Test Chips for Custom Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Griswold, T. W.; Pina, C. A.; Timoc, C. C.

    1985-01-01

    Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

  9. Integrated Circuit Failure Analysis Hypertext Help System

    SciTech Connect

    Henderson, Christopher L.; Barton, Daniel L.; Campbell, Ann N.; Cole, Edward I; Mikawa, Russell E.; Peterson, Kenneth A.; Rife, James L.; Soden, Jerry M.

    1995-02-23

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  10. Heat-Transfer Microstructures for Integrated Circuits

    DTIC Science & Technology

    2007-11-02

    fatigue failure curves for silicon mounted on molybdenum or copper (from Lang et a[ [75]). Microcapillary thermal interface concept. a) Tunnels...Coolant Figure of Merit Complementary Metal-Oxide-Semiconductor Emitter- Coupled Logic Integrated Circuit Metal-Oxide-Semiconductor Median Time to...nominally independent devices; for example, electromagnetic coupling (crosstalk) between adjacent long, parallel wires on an IC, especially when a ground

  11. Bioluminescent bioreporter integrated circuit detection methods

    SciTech Connect

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  12. Optoelectronic Integrated Circuits For Neural Networks

    NASA Technical Reports Server (NTRS)

    Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

    1990-01-01

    Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

  13. All-ion-implantation process for integrated circuits

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1979-01-01

    Simpler than diffusion fabrication, ion bombardment produces complementary-metal-oxide-semiconductor / silicon-on-sapphire (CMOS/SOS) circuits that are one-third faster. Ion implantation simplifies the integrated circuit fabrication procedure and produces circuits with uniform characteristics.

  14. SEU In An Advanced Bipolar Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.; Secrest, Elaine C.; Berndt, Dale F.

    1989-01-01

    Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

  15. Integrated-Circuit Active Digital Filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1986-01-01

    Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

  16. Development of 3D integrated circuits for HEP

    SciTech Connect

    Yarema, R.; /Fermilab

    2006-09-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

  17. Applying analog integrated circuits for HERO protection

    NASA Technical Reports Server (NTRS)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  18. Photonic circuits integrated with CMOS compatible photodetectors

    NASA Astrophysics Data System (ADS)

    Cristea, Dana; Craciunoiu, F.; Modreanu, M.; Caldararu, M.; Cernica, I.

    2001-06-01

    This paper presents the integration of photodetectors and photonic circuits (waveguides and interferometers, coupling elements and chemo-optical transducing layer) on one silicon chip. Different materials: silicon, doped or undoped silica, SiO xN y, polymers, and different technologies: LPCVD, APCVD, sol-gel, spinning, micromachining have been used to realize the photonic and micromechanical components and the transducers. Also, MOS compatible processes have been used for optoelectronic circuits. The attention was focused on the matching of all the involved technologies, to allow the monolithic integration of all components, and also on the design and fabrication of special structures of photodetectors. Two types of high responsivity photodetectors, a photo-FET and a bipolar NPN phototransistor, with modified structures that allow the optical coupling to the waveguides have been designed and experimented. An original 3-D model was developed for the system: opto-FET-coupler-waveguide. A test circuit for sensor applications was experimented. All the components of the test circuits, photodetectors, waveguides, couplers, were obtained using CMOS-compatible processes. The aim of our research activity was to obtain microsensors with optical read-out.

  19. Integrated Circuit Radar And Radiometric Sensors

    NASA Astrophysics Data System (ADS)

    Seashore, C. R.

    1985-10-01

    The use of integrated circuit techniques for millimeter wave transducers has now moved from a research curiosity to an engineering discipline. Microstrip is the preferred transmission media to demonstrate a wide variety of RF component functions. For applications involving precision weapon systems, a soft substrate is preferred since it provides lower cost, improved survivability, and functional versatility when compared with the traditional hard candidates such as quartz. The MESFET is rapidly emerging as a key building block for monolithic supercomponents up to a frequency of approximately 40 GHz. Both planar and conformal antennas are being developed again based on a soft substrate with photolithographic processing. The marriage of planar integrated circuit transceivers with thin, planar antennas is providing a new generation of low cost, producible and miniature millimeter wave transducers for demanding systems requirements.

  20. Development of beam lead RF integrated circuits

    NASA Technical Reports Server (NTRS)

    Kline, A. J.; Kermode, A. W.

    1975-01-01

    This paper describes the design and development of a set of multifunction VHF/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical test results and the distribution of test parameters are presented. A unique carrier for beam-lead devices is described, and the need for such a device is discussed. The application of the carrier to device screening, burn-in and drift measurements is discussed together with the incentives for providing these capabilities. An overview of the integration of the devices into the spacecraft radio is given and candidate assembly processes are discussed. The technology impact of this approach upon future spacecraft radio systems is qualitatively examined.

  1. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  2. Integrated Circuit For Simulation Of Neural Network

    NASA Technical Reports Server (NTRS)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  3. Construction and Analysis of Electronic circuits

    NASA Technical Reports Server (NTRS)

    Thomas, Ashley N.

    2004-01-01

    The Aviation Environmental Technical Branch produces many various types of aeronautical research that benefits the NASA mission for space exploration and in turn, produces new technology for our nation. One of the present goals of the Aviation Environmental Technical Branch is to create better engines for airplanes by testing supersonic jet propulsion and safe fuel combustion. During the summer of 2004, I was hired by Vincent Sattenvhite Chief executive of the Aviation Environmental Technical Branch to Assist Yves Lamothe with a fuel igniter circuit. Yves Lamothe is an electrical engineer who is currently working on safe fuel combustion testing. This testing is planned to determine the minimum ignition energy for fuel and air vapors of current and alternative fuels under simulated flight conditions. An air temperature bath will provide simulated flight profile temperatures and the heat fluxes to the test chamber. I was assigned with Yves to help complete the igniter circuit which consists of a 36k voltage supply an oscilloscope, and a high voltage transistor switch. During my tenure in the L.E.C.I.R.P. program I studied the basics of electricity and circuitry along with two other projects that I completed. In the beginning of my internship, I devote all of my time to research the aspects of circuitry so that I would be prepared for the projects that I was assigned to do. I read about lessons on; the basic physical concepts of electronics, Electrical units, Basic dc circuits, direct current circuit analysis, resistance and cell batteries, various types of magnetism , Alternating current basics, inductance, and power supplies. I received work sheets and math equations from my Mentor so that I could be able to apply these concepts into my work. After I complete my studies, I went on to construct a LED chaser circuit which displays a series of light patterns using a 555 timer. I incorporated a switch and motion detector into the circuit to create basic alarm system

  4. Progress in radiation immune thermionic integrated circuits

    SciTech Connect

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  5. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-19

    ... COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice... 1930, as amended, 19 U.S.C. 1337, on behalf of Renesas Electronics Corporation of Japan and 511... certain digital televisions containing integrated circuit devices and components thereof by reason...

  6. Power system with an integrated lubrication circuit

    SciTech Connect

    Hoff, Brian D.; Akasam, Sivaprasad; Algrain, Marcelo C.; Johnson, Kris W.; Lane, William H.

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  7. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  8. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, Edward H.; Tuckerman, David B.

    1991-01-01

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

  9. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    SciTech Connect

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  10. Towards quantum thermodynamics in electronic circuits

    NASA Astrophysics Data System (ADS)

    Pekola, Jukka P.

    2015-02-01

    Electronic circuits operating at sub-kelvin temperatures are attractive candidates for studying classical and quantum thermodynamics: their temperature can be controlled and measured locally with exquisite precision, and they allow experiments with large statistical samples. The availability and rapid development of devices such as quantum dots, single-electron boxes and superconducting qubits only enhance their appeal. But although these systems provide fertile ground for studying heat transport, entropy production and work in the context of quantum mechanics, the field remains in its infancy experimentally. Here, we review some recent experiments on quantum heat transport, fluctuation relations and implementations of Maxwell's demon, revealing the rich physics yet to be fully probed in these systems.

  11. An integrator circuit in cerebellar cortex.

    PubMed

    Maex, Reinoud; Steuber, Volker

    2013-09-01

    The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low (< 1 per s) and high rates (> 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant.

  12. LASER APPLICATIONS AND OTHER TOPICS IN QUANTUM ELECTRONICS: Laser-induced extreme UV radiation sources for manufacturing next-generation integrated circuits

    NASA Astrophysics Data System (ADS)

    Borisov, V. M.; Vinokhodov, A. Yu; Ivanov, A. S.; Kiryukhin, Yu B.; Mishchenko, V. A.; Prokof'ev, A. V.; Khristoforov, O. B.

    2009-10-01

    The development of high-power discharge sources emitting in the 13.5±0.135-nm spectral band is of current interest because they are promising for applications in industrial EUV (extreme ultraviolet) lithography for manufacturing integrated circuits according to technological precision standards of 22 nm and smaller. The parameters of EUV sources based on a laser-induced discharge in tin vapours between rotating disc electrodes are investigated. The properties of the discharge initiation by laser radiation at different wavelengths are established and the laser pulse parameters providing the maximum energy characteristics of the EUV source are determined. The EUV source developed in the study emits an average power of 276 W in the 13.5±0.135-nm spectral band on conversion to the solid angle 2π sr in the stationary regime at a pulse repetition rate of 3000 Hz.

  13. Organic printed photonics: From microring lasers to integrated circuits.

    PubMed

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  14. Organic printed photonics: From microring lasers to integrated circuits

    PubMed Central

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-01-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  15. Electronic circuit for measuring series connected electrochemical cell voltages

    DOEpatents

    Ashtiani, Cyrus N.; Stuart, Thomas A.

    2000-01-01

    An electronic circuit for measuring voltage signals in an energy storage device is disclosed. The electronic circuit includes a plurality of energy storage cells forming the energy storage device. A voltage divider circuit is connected to at least one of the energy storage cells. A current regulating circuit is provided for regulating the current through the voltage divider circuit. A voltage measurement node is associated with the voltage divider circuit for producing a voltage signal which is proportional to the voltage across the energy storage cell.

  16. Electronic Components and Circuits for Extreme Temperature Environments

    NASA Technical Reports Server (NTRS)

    Patterson, Richard L.; Hammoud, Ahmad; Dickman, John E.; Gerber, Scott

    2003-01-01

    Planetary exploration missions and deep space probes require electrical power management and control systems that are capable of efficient and reliable operation in very low temperature environments. Presently, spacecraft operating in the cold environment of deep space carry a large number of radioisotope heating units in order to maintain the surrounding temperature of the on-board electronics at approximately 20 C. Electronics capable of operation at cryogenic temperatures will not only tolerate the hostile environment of deep space but also reduce system size and weight by eliminating or reducing the radioisotope heating units and their associate structures; thereby reducing system development as well as launch costs. In addition, power electronic circuits designed for operation at low temperatures are expected to result in more efficient systems than those at room temperature. This improvement results from better behavior and tolerance in the electrical and thermal properties of semiconductor and dielectric materials at low temperatures. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical components, circuits, and systems suitable for applications in the aerospace environment and deep space exploration missions. Research is being conducted on devices and systems for reliable use down to cryogenic temperatures. Some of the commercial-off-the-shelf as well as developed components that are being characterized include switching devices, resistors, magnetics, and capacitors. Semiconductor devices and integrated circuits including digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being investigated for potential use in low temperature applications. An overview of the NASA Glenn Research Center Low Temperature Electronic Program will be presented in this paper. A description of the low temperature test facilities along with

  17. Integrated circuit tester using interferometric imaging

    SciTech Connect

    Donaldson, W.R.; Michaels, E.M.R.; Akowuah, K.

    1997-04-01

    An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a number of physical phenomena including dopants in the material such as those used to form device structures, heating due to the flow of electrical currents, and changes in carrier concentration due to injection. These variations have both static and dynamic components. The dynamic components are associated with the normal device operation and are the most interesting. To separate the components, the device is first imaged in a quiescent state, and then a second image is taken after the device enters a known voltage state. Differences between the two images determine where the local index of refraction has changed and by how much. A third image taken with the reference arm of the interferometer blocked, allows device structures to be associated with particular changes in the index of refraction. Activation of the voltage state is synchronized with the pulsed illumination source, and the time delay between the application of the voltage and the laser probe pulse allows us to take a series of images that map the time evolution of the interferogram. This technique offers an exciting new diagnostic for semiconductor integrated circuits. The technique is noninvasive and compatible with high-speed operation of integrated circuits. The picosecond resolution enables us to either characterize specific logic states or watch an individual device turn on. This imaging technique is sensitive to all of the index of refraction changes that can be associated with IC`s. These include heating due to current flowing through narrow wires and charge injection into the depletion region of a transistor.

  18. Electro-optical Probing Of Terahertz Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

    1990-01-01

    Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

  19. Accelerating functional verification of an integrated circuit

    SciTech Connect

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  20. Tool For Tinning Integrated-Circuit Leads

    NASA Technical Reports Server (NTRS)

    Prosser, Gregory N.

    1988-01-01

    As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

  1. Integrated-Circuit Broadband Infrared Sources

    NASA Technical Reports Server (NTRS)

    Lamb, G.; Jhabvala, M.; Burgess, A.

    1989-01-01

    Microscopic devices consume less power, run hotter, and are more reliable. Simple, compact, lightweight, rapidly-responding reference sources of broadband infrared radiation made available by integrated-circuit technology. Intended primarily for use in calibration of remote-sensing infrared instruments, devices eventually replace conventional infrared sources. New devices also replace present generation of miniature infrared sources. Self-passivating nature of poly-crystalline silicon adds to reliability of devices. Maximum operating temperature is 1,000 K, and power dissipation is only one-fourth that of prior devices.

  2. An integrated circuit floating point accumulator

    NASA Technical Reports Server (NTRS)

    Goldsmith, T. C.

    1977-01-01

    Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

  3. 3D packaging for integrated circuit systems

    SciTech Connect

    Chu, D.; Palmer, D.W.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  4. Testing Fixture For Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert; Shalkhauser, Kurt

    1989-01-01

    Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

  5. Automatic Parametric Testing Of Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Jennings, Glenn A.; Pina, Cesar A.

    1989-01-01

    Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

  6. Computer Aided Engineering of Semiconductor Integrated Circuits

    DTIC Science & Technology

    1976-04-01

    transistor opera tion; (4) theoretical invest! jations of carrifr mobli *!;y *"« inversion layer of an MOSFET; (5) mathematical investigations for high...satisfactory greLnt «Lh experiment. In time, the rapid groWth of se.r- oonduotor integrated circuit (IC, technology created ^ ^ °n" £or which this theory was...and Technology of Semiconductor Devices, John Wiley and Sons, Inc., N.Y. (1967). [2] S. K. Ghandi, The Theory and Practice of

  7. GaAs microwave devices and circuits with submicron electron-beam defined features

    NASA Technical Reports Server (NTRS)

    Wisseman, W. R.; Macksey, H. M.; Brehm, G. E.; Saunier, P.

    1983-01-01

    This paper describes the fabrication and application of GaAs FET's, both as discrete microwave devices and as the key active components in monolithic microwave integrated circuits. The performance of these devices and circuits is discussed for frequencies ranging from 3 to 25 GHz. The crucial fabrication step is the formation of the submicron gate by electron-beam lithography.

  8. Flexible Microstrip Circuits for Superconducting Electronics

    NASA Technical Reports Server (NTRS)

    Chervenak, James; Mateo, Jennette

    2013-01-01

    Flexible circuits with superconducting wiring atop polyimide thin films are being studied to connect large numbers of wires between stages in cryogenic apparatus with low heat load. The feasibility of a full microstrip process, consisting of two layers of superconducting material separated by a thin dielectric layer on 5 mil (approximately 0.13 mm) Kapton sheets, where manageable residual stress remains in the polyimide film after processing, has been demonstrated. The goal is a 2-mil (approximately 0.051-mm) process using spin-on polyimide to take advantage of the smoother polyimide surface for achieving highquality metal films. Integration of microstrip wiring with this polyimide film may require high-temperature bakes to relax the stress in the polyimide film between metallization steps.

  9. The design of PLC circuits based on power electronics topology

    NASA Astrophysics Data System (ADS)

    Sun, Qi; Ouyang, Mingsan

    2011-10-01

    The paper presents a new design method and power lines communication circuit consolidates their power and data in a single bus. This method is based on power electronic topology and can export new application circuit. Our-the bus's principle are briefly introduced. Buck-by considering the circuit transmission line, the characteristics of the steady-state circuit influence and dynamic switch characteristics are analyzed. The validity of this method is verified by the experiment results.

  10. Diamond heat sinks for electronic circuits

    NASA Astrophysics Data System (ADS)

    Li, Chou H.

    During the interim stage of this Phase 1 R and D, a useful metallizing procedure for bulk diamond has been developed, with natural diamond chips, granules, and polished wafers from two vendors. Small-scale statistical experiments were designed and executed by systematically varying several material and processing variables including: metallizing and brazing compositions, processing temperature and time, ambient control, and other procedural changes. Under selected combinations of these variables, metallizing of these diamond samples was achieved. Surface wetting appears to be excellent. The metallized surfaces were brazed or soldered to metal for future heat sink uses in high-power electronic circuits. These results clearly demonstrate the proof of the principle that is our main objective in Phase 1. The remainder of the Phase 1 work will be directed to metallizing and brazing polished diamond wafers to metal (copper and/or Kovar) substrates; detailed sample characterization including scanning electron microscopy (SEM), microstructural and microprobing analyses; thermal conductance measurements of mounted diamond wafers; and analyzing all results for the final report.

  11. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  12. Next-generation integrated microfluidic circuits.

    PubMed

    Mosadegh, Bobak; Bersano-Begey, Tommaso; Park, Joong Yull; Burns, Mark A; Takayama, Shuichi

    2011-09-07

    This mini-review provides a brief overview of recent devices that use networks of elastomeric valves to minimize or eliminate the need for interconnections between microfluidic chips and external instruction lines that send flow control signals. Conventional microfluidic control mechanisms convey instruction signals in a parallel manner such that the number of instruction lines must increase as the number of independently operated valves increases. The devices described here circumvent this "tyranny of microfluidic interconnects" by the serial encoding of information to enable instruction of an arbitrary number of independent valves with a set number of control lines, or by the microfluidic circuit-embedded encoding of instructions to eliminate control lines altogether. Because the parallel instruction chips are the most historical and straightforward to design, they are still the most commonly used approach today. As requirements for instruction complexity, chip-to-chip communication, and real-time on-chip feedback flow control arise, the next generation of integrated microfluidic circuits will need to incorporate these latest interconnect flow control approaches.

  13. Test Diagnostics of RF Effects in Integrated Circuits

    DTIC Science & Technology

    1990-02-01

    RADC-TR-89-355 Final Technical Report February 1990AD-A219 737 TEST DIAGNOSTICS OF RF EFFECTS IN INTEGRATED CIRCUITS Martin Marietta Space Systems...DIAGNOSTICS OF RF EFFECTS IN INTEGRATED CIRCUITS 12 PERSONAL AUTHOR(S) David D. Wilson, Stan Epshtein, Mark G. Rossi, Christine L. Proffitt 13a. TYPE...presents "he results of an effort to measure the RF upset susceptibilities of CMOS and low power Schottky integrated circuits and to demonstrate a

  14. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    PubMed

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-05

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  15. Photonic integrated circuits: new challenges for lithography

    NASA Astrophysics Data System (ADS)

    Bolten, Jens; Wahlbrink, Thorsten; Prinzen, Andreas; Porschatis, Caroline; Lerch, Holger; Giesecke, Anna Lena

    2016-10-01

    In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today's low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

  16. Monolithic microwave integrated circuit water vapor radiometer

    NASA Technical Reports Server (NTRS)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  17. Post irradiation effects (PIE) in integrated circuits

    NASA Technical Reports Server (NTRS)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  18. Integrated photo-responsive metal oxide semiconductor circuit

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzban D. (Inventor); Dargo, David R. (Inventor); Lyons, John C. (Inventor)

    1987-01-01

    An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

  19. W88 integrated circuit shelf life program

    SciTech Connect

    Soden, J.M.; Anderson, R.E.

    1998-01-01

    The W88 Integrated Circuit Shelf Life Program was created to monitor the long term performance, reliability characteristics, and technological status of representative WR ICs manufactured by the Allied Signal Albuquerque Microelectronics Operation (AMO) and by Harris Semiconductor Custom Integrated Circuits Division. Six types of ICs were used. A total of 272 ICs entered two storage temperature environments. Electrical testing and destructive physical analysis were completed in 1995. During each year of the program, the ICs were electrically tested and samples were selected for destructive physical analysis (DPA). ICs that failed electrical tests or DPA criteria were analyzed. Fifteen electrical failures occurred, with two dominant failure modes: electrical overstress (EOS) damage involving the production test programs and electrostatic discharge (ESD) damage during analysis. Because of the extensive handling required during multi-year programs like this, it is not unusual for EOS and ESD failures to occur even though handling and testing precautions are taken. The clustering of the electrical test failures in a small subset of the test operations supports the conclusion that the test operation itself was responsible for many of the failures and is suspected to be responsible for the others. Analysis of the electrical data for the good ICs found no significant degradation trends caused by the storage environments. Forty-six ICs were selected for DPA with findings primarily in two areas: wire bonding and die processing. The wire bonding and die processing findings are not surprising since these technology conditions had been documented during manufacturing and were determined to present acceptable risk. The current reliability assessment of the W88 stockpile assemblies employing these and related ICs is reinforced by the results of this shelf life program. Data from this program will aid future investigation of 4/3 micron or MNOS IC technology failure modes.

  20. Electronic circuit provides automatic level control for liquid nitrogen traps

    NASA Technical Reports Server (NTRS)

    Turvy, R. R.

    1968-01-01

    Electronic circuit, based on the principle of increased thermistor resistance corresponding to decreases in temperature provides an automatic level control for liquid nitrogen cold traps. The electronically controlled apparatus is practically service-free, requiring only occasional reliability checks.

  1. Connector and electronic circuit assembly for improved wet insulation resistance

    SciTech Connect

    Reese, Jason A.; Teli, Samar R.; Keenihan, James R.; Langmaid, Joseph A.; Maak, Kevin D.; Mills, Michael E.; Plum, Timothy C.; Ramesh, Narayan

    2016-07-19

    The present invention is premised upon a connector and electronic circuit assembly (130) at least partially encased in a polymeric frame (200). The assembly including at least: a connector housing (230); at least one electrical connector (330); at least one electronic circuit component (430); and at least one barrier element (530).

  2. Ge/Si Integrated Circuit For Infrared Imaging

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.

    1990-01-01

    Proposed integrated circuit consists of focal-plane array of metal/germanium Schottky-barrier photodetectors on same chip with silicon-based circuits that processes signals from photodetectors. Made compatible with underlying silicon-based circuitry by growing germanium epitaxially on silicon circuit wafers. Metal deposited in ultrahigh vacuum immediately after growth of germanium. Combination of described techniques results in high-resolution infrared-imaging circuits of superior performance.

  3. Predicting the reliability of electronic circuits.

    SciTech Connect

    Loescher, Douglas H.

    2004-06-01

    Procedures to predict the reliability of electrical circuits are discussed. Three cases are introduced and discussed. In Case 1, an analyst predicts the probability of any failure in the intended relations between circuit inputs and circuit outputs. In Case 2, an analyst predicts the probability that specified unintended outputs would occur. In Case 3, an analyst considers coupling between circuits. Logic models are given for the three cases, and sources of failure probabilities of components are mentioned. Methods of analysis are given, software tools are mentioned, and recommendations for presentation and review of results are discussed.

  4. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  5. Integrated circuit for SAW and MEMS sensors

    NASA Astrophysics Data System (ADS)

    Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

    2001-11-01

    The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

  6. GaAs Optoelectronic Integrated-Circuit Neurons

    NASA Technical Reports Server (NTRS)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  7. Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment

    NASA Technical Reports Server (NTRS)

    Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

    1998-01-01

    Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

  8. Securing health sensing using integrated circuit metric.

    PubMed

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-10-20

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  9. Optical Integrated Circuits Theory and Design

    NASA Astrophysics Data System (ADS)

    Li, Xiangshan

    1995-01-01

    The first part of this work describes the main theory required for the analysis and design of optical integrated circuits which have the purpose of processing light signals carried on fiber optic cables. For ease of fabrication it is advantageous to design the light processing channels in a planar geometry. The analysis of the resulting dielectric structures requires computations of both the propagation constants of the modes of the structures and the inherent energy losses resulting from the geometry of the light guiding channels. The latter losses have two primary sources, (1) radiation losses due to leakage out of the guiding channels into the supporting substrates, and (2) curvature losses due to the necessary bending of the guiding channels required to separate the light signals. The results of this work is a computer program for the design of a computer generated CAD lithographic mask that can be used to fabricate a multiple channel waveguiding structure capable of dividing an input light signal into a set number of output channels carrying designated fractions of the input energy. In the last part of this thesis we then apply the theory developed in first part to the design of a TE -TM polarization splitter. The resulting design represents an improvement over previous design suggested by other groups, and makes it possible to obtain a nearly 100% separation between the two orthogonal polarization states of the fields in a waveguide. All of the work of this thesis has potential applications in the construction of the superhighway.

  10. Securing Health Sensing Using Integrated Circuit Metric

    PubMed Central

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  11. Ultraviolet integrated photonic circuits (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Fanto, Michael L.; Steidle, Jeffrey A.; Lu, Tsung-Ju; Preble, Stefan F.; Englund, Dirk R.; Tison, Christopher C.; Smith, Amos M.; Howland, Gregory A.; Soderberg, Kathy-Anne; Alsing, Paul M.

    2016-10-01

    Quantum information processing relies on the fundamental property of quantum interference, where the quality of the interference directly correlates to the indistinguishability of the interacting particles. The creation of these indistinguishable particles, photons in this case, has conventionally been accomplished with nonlinear crystals and optical filters to remove spectral distinguishability, albeit sacrificing the number of photons. This research describes the use of an integrated aluminum nitride microring resonator circuit to selectively generate photon pairs at the narrow cavity transmissions, thereby producing spectrally indistinguishable photons. These spectrally indistinguishable photons can then be routed through optical waveguide circuitry, concatenated interferometers, to manipulate and entangle the photons into the desired quantum states. Photon sources and circuitry are only two of the three required pieces of the puzzle. The final piece which this research is aimed at interfacing with are trapped ion quantum memories, based on trapped Ytterbium ions. These ions serve as very long lived and stable quantum memories with storage times on the order of 10's of minutes, compared with photonic quantum memories which are limited to 10-6 to 10-3 seconds. The caveat with trapped ions is the interaction wavelength of the photons is 369.5nm and therefore the goal of this research is to develop entangled photon sources and circuitry in that wavelength regime to interact directly with the trapped ions and bypass the need for frequency conversion.

  12. Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

    DTIC Science & Technology

    2016-03-01

    monolithic microwave integrated circuits (MMICs) are essential for compact hand-held satellite communications systems that provide instant, secure data...of approximately 30 to 45 GHz, monolithic microwave integrated circuits (MMICs) are essential for compact hand- held satellite communications (SATCOM...6- × 50-µm HEMT cell using measured data and based on load pull data (8, 16, 24, and 32 GHz) measured at ARL. Simple one-stage designs with a single

  13. Magnetic imaging of moat-guarded superconducting electronic circuits

    NASA Astrophysics Data System (ADS)

    Jeffery, Mark; Van Duzer, T.; Kirtley, J. R.; Ketchen, M. B.

    1995-09-01

    Superconducting electronic circuits surrounded by various configurations of holes in the superconducting ground plane have been imaged using a high resolution scanning superconducting quantum interference device (SQUID) microscope. These data demonstrate that in the weak field limit continuous moats trap flux more effectively to protect the circuits than small holes in the same configuration.

  14. Modular electron transfer circuits for synthetic biology: insulation of an engineered biohydrogen pathway.

    PubMed

    Agapakis, Christina M; Silver, Pamela A

    2010-01-01

    Electron transfer is central to a wide range of essential metabolic pathways, from photosynthesis to fermentation. The evolutionary diversity and conservation of proteins that transfer electrons makes these pathways a valuable platform for engineered metabolic circuits in synthetic biology. Rational engineering of electron transfer pathways containing hydrogenases has the potential to lead to industrial scale production of hydrogen as an alternative source of clean fuel and experimental assays for understanding the complex interactions of multiple electron transfer proteins in vivo. We designed and implemented a synthetic hydrogen metabolism circuit in Escherichia coli that creates an electron transfer pathway both orthogonal to and integrated within existing metabolism. The design of such modular electron transfer circuits allows for facile characterization of in vivo system parameters with applications toward further engineering for alternative energy production.

  15. High performance protection circuit for power electronics applications

    SciTech Connect

    Tudoran, Cristian D. Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  16. Germanium on silicon to enable integrated photonic circuits

    NASA Astrophysics Data System (ADS)

    Hopkins, F. Kenneth; Walsh, Kevin M.; Benken, Alexander; Jones, John; Averett, Kent; Diggs, Darnell E.; Tan, Loon-Seng; Mou, Shin; Grote, James G.

    2013-09-01

    Electronic circuits alone cannot fully meet future requirements for speed, size, and weight of many sensor systems, such as digital radar technology and as a result, interest in integrated photonic circuits (IPCs) and the hybridization of electronics with photonics is growing. However, many IPC components such as photodetectors are not presently ideal, but germanium has many advantages to enable higher performance designs that can be better incorporated into an IPC. For example, Ge photodetectors offer an enormous responsivity to laser wavelengths near 1.55μm at high frequencies to 40GHz, and they can be easily fabricated as part of a planar silicon processing schedule. At the same time, germanium has enormous potential for enabling 1.55 micron lasers on silicon and for enhancing the performance of silicon modulators. Our new effort has begun by studying the deposition of germanium on silicon and beginning to develop methods for processing these films. In initial experiments comparing several common chemical solutions for selective etching under patterned positive photoresist, it was found that hydrogen peroxide (H2O2) at or below room temperature (20 C) produced the sharpest patterns in the Ge films; H2O2 at a higher temperature (50 C) resulted in the greatest lateral etching.

  17. Stable Polyurethane Coatings for Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Morris, D. E.

    1983-01-01

    Alkane-based polyurethanes resist deterioration while maintaining good dielectric properties. Weight loss after prolonged immersion in hot water far less for alkane-based polyurethanes than for more common ether based polyurethanes, at any given oxygen content. Major uses of polyurethanes are as connector potting materials and conformal coatings for printed circuit boards.

  18. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products.... International Trade Commission has received a complaint entitled Certain Integrated Circuit Packages Provided... sale within the United States after importation of certain integrated circuit packages provided...

  19. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-07

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Receipt... Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products... importation of certain integrated circuits, chipsets, and products containing same including televisions....

  20. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-13

    ... COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of... within the United States after importation of certain radio frequency integrated circuits and devices... after importation of certain radio frequency integrated circuits and devices containing same...

  1. 76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-14

    ... COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions by reason of infringement... integrated circuits, chipsets, and products containing same including televisions that infringe one or...

  2. The Effects of Space Radiation on Linear Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Johnston, A.

    2000-01-01

    Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

  3. 35 GHz integrated circuit rectifying antenna with 33 percent efficiency

    NASA Technical Reports Server (NTRS)

    Yoo, T.-W.; Chang, K.

    1991-01-01

    A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

  4. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  5. Chemical etching for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1981-01-01

    Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

  6. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-23

    ... Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products Containing the Same... certain large scale integrated circuit semiconductor chips and products containing same by reason...

  7. Vertically integrated circuit development at Fermilab for detectors

    NASA Astrophysics Data System (ADS)

    Yarema, R.; Deptuch, G.; Hoff, J.; Khalid, F.; Lipton, R.; Shenai, A.; Trimpl, M.; Zimmerman, T.

    2013-01-01

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  8. Radiation-hardened transistor and integrated circuit

    DOEpatents

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  9. Addressable-Matrix Integrated-Circuit Test Structure

    NASA Technical Reports Server (NTRS)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  10. Analog integrated circuits design for processing physiological signals.

    PubMed

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  11. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, Jr., Edward I.

    1996-01-01

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

  12. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, E.I. Jr.

    1996-06-04

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs. 5 figs.

  13. Secondary Side CMOS Feedback Control Integrated Circuit

    DTIC Science & Technology

    1990-06-01

    Temperature ( Celc ~us) Figure 5.1: Experimental Temperature Dependence cf Untrimmed Bandgap Circuit 104 1. I I ’ - ’ 0 0.9 . -0-0 Ouput Voit -ge ---.o M...Schlecht and L.F. Casey, "Comparison of the Square-Wave and Quasi- Resonant Topologies," IEEE PESC Record, 1987, pp. 124-134. 132

  14. Processing of Image Data by Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Armstrong, R. W.

    1985-01-01

    Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.

  15. Laser rapid prototyping of photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Levy, Miguel; Scarmozzino, Robert; Osgood, Richard M., Jr.

    1994-07-01

    In this paper, we will describe our work at Columbia in developing a laser prototyping system, in conjunction with computer simulation, to design, fabricate, and test novel waveguide circuits. The system is also useful for manufacturing small-run circuit designs. The fundamental technique uses a laser-induced photoelectrochemical process for etching GaAs and other III-V compounds. The technique is maskless and discretionary. The computer-controlled apparatus can be programmed with any desired circuit pattern, and prototype waveguide circuits can be produced within a day. The waveguides and passive components produced with this technique include linear waveguides, tapered waveguides, abrupt and smoothly curved bends, Y-branches, asymmetric splitters, directional couplers, and optical delay lines. The passive devices are single-mode and low-loss. The technique also has the ability to vary the effective index of refraction along the device by grading the etch depth. In addition to passive devices, we have recently shown that active switching components can be prototyped by combining passive structures with laser-patterned metal electrodes. These electrodes are produced masklessly using standard metal deposition techniques coupled with laser- patterning of photoresist. In addition, metal can be deposited directly using laser-induced selective metallorgainic CVD.

  16. Hybrid and monolithic integration of planar lightwave circuits (PLCs)

    NASA Astrophysics Data System (ADS)

    Chen, Ray T.

    2008-02-01

    In this paper, we review the status of monolithic and hybrid integration of planar lightwave circuits (PLCs). Building blocks needed for system integration based on polymeric materials, III-V semiconductor materials, LiNbO 3 and SOI on Silicon are summarized with pros and cons. Due to the maturity of silicon CMOS technology, silicon becomes the platform of choice for optical application specific integrated circuits (OASICs). However, the indirect bandgap of silicon makes the formation of electrically pumped silicon laser a remote plausibility which requires hybrid integration of laser sources made out of III-V compound semicouductor.

  17. Microwave GaAs Integrated Circuits On Quartz Substrates

    NASA Technical Reports Server (NTRS)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  18. High density electronic circuit and process for making

    DOEpatents

    Morgan, W.P.

    1999-06-29

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

  19. High density electronic circuit and process for making

    DOEpatents

    Morgan, William P.

    1999-01-01

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

  20. Research in Computer Simulation of Integrated Circuits.

    DTIC Science & Technology

    1983-07-31

    bwadeid a -’. ate dew’.d or "mom 1640e 4 4 4 4.5 he ham ala ker 27601 519 6145 2549 "and 3.2 1.5 2.2 34 4230 TAME 4 A,4er Stsmao m CLAS From the show...from SPICEV it is expected that the speedup is Larger for t.(As) 4 4 4 4 6 the adder circuits compared to the filters. A first observe- iter 352 27601

  1. Direct Desktop Printed-Circuits-on-Paper Flexible Electronics

    NASA Astrophysics Data System (ADS)

    Zheng, Yi; He, Zhizhu; Gao, Yunxia; Liu, Jing

    2013-05-01

    There currently lacks of a way to directly write out electronics, just like printing pictures on paper by an office printer. Here we show a desktop printing of flexible circuits on paper via developing liquid metal ink and related working mechanisms. Through modifying adhesion of the ink, overcoming its high surface tension by dispensing machine and designing a brush like porous pinhead for printing alloy and identifying matched substrate materials among different papers, the slightly oxidized alloy ink was demonstrated to be flexibly printed on coated paper, which could compose various functional electronics and the concept of Printed-Circuits-on-Paper was thus presented. Further, RTV silicone rubber was adopted as isolating inks and packaging material to guarantee the functional stability of the circuit, which suggests an approach for printing 3D hybrid electro-mechanical device. The present work paved the way for a low cost and easygoing method in directly printing paper electronics.

  2. Direct Desktop Printed-Circuits-on-Paper Flexible Electronics

    PubMed Central

    Zheng, Yi; He, Zhizhu; Gao, Yunxia; Liu, Jing

    2013-01-01

    There currently lacks of a way to directly write out electronics, just like printing pictures on paper by an office printer. Here we show a desktop printing of flexible circuits on paper via developing liquid metal ink and related working mechanisms. Through modifying adhesion of the ink, overcoming its high surface tension by dispensing machine and designing a brush like porous pinhead for printing alloy and identifying matched substrate materials among different papers, the slightly oxidized alloy ink was demonstrated to be flexibly printed on coated paper, which could compose various functional electronics and the concept of Printed-Circuits-on-Paper was thus presented. Further, RTV silicone rubber was adopted as isolating inks and packaging material to guarantee the functional stability of the circuit, which suggests an approach for printing 3D hybrid electro-mechanical device. The present work paved the way for a low cost and easygoing method in directly printing paper electronics.

  3. A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

    NASA Astrophysics Data System (ADS)

    Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

    2017-04-01

    Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

  4. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  5. Multi-channel detector readout method and integrated circuit

    SciTech Connect

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  6. Characteristics control of room-temperature operating single electron transistor with floating gate by charge pump circuit

    NASA Astrophysics Data System (ADS)

    Nozue, Motoki; Suzuki, Ryota; Nomura, Hirotoshi; Saraya, Takuya; Hiramoto, Toshiro

    2013-10-01

    A single electron transistor (SET) with floating gate, which has a non-volatile memory effect, is successfully integrated with a charge pump circuit that consists of conventional MOS circuits on the same chip. By applying high voltage generated by the charge pump circuit to SET with floating gate, characteristics control of the Coulomb blockade oscillation is demonstrated at room temperature for the first time. This attempt will open a new path of adding new functionality to conventional MOS circuits by integration with so-called "Beyond CMOS" devices.

  7. Monolithic microwave integrated circuits: Technology and design

    NASA Astrophysics Data System (ADS)

    Goyal, Ravender

    Theoretical and practical aspects of MMIC design are examined in a textbook intended for a senior or graduate engineering laboratory course. The individual chapters are contributed by specialists and cover fundamental MMIC characteristics and applications, the theory of microwave transmission, MMIC material and manufacturing technology, device modeling, amplifier design, nonlinear and control circuits, the TV-receive-only chip as a typical MMIC-based subsystem, design automation tools, on-wafer testing, MMIC packaging, and MMIC reliability. Extensive diagrams, drawings, graphs, photographs, and tables of numerical data are provided.

  8. Fuzzy classifier for fault diagnosis in analog electronic circuits.

    PubMed

    Kumar, Ashwani; Singh, A P

    2013-11-01

    Many studies have presented different approaches for the fault diagnosis with fault models having ± 50% variation in the component values in analog electronic circuits. There is still a need of the approaches which provide the fault diagnosis with the variation in the component value below ± 50%. A new single and multiple fault diagnosis technique for soft faults in analog electronic circuit using fuzzy classifier has been proposed in this paper. This technique uses the simulation before test (SBT) approach by analyzing the frequency response of the analog circuit under faulty and fault free conditions. Three signature parameters peak gain, frequency and phase associated with peak gain, of the frequency response of the analog circuit are observed and extracted such that they give unique values for faulty and fault free configuration of the circuit. The single and double fault models with the component variations from ± 10% to ± 50% are considered. The fuzzy classifier along the classification of faults gives the estimated component value under faulty and faultfree conditions. The proposed method is validated using simulated data and the real time data for a benchmark analog circuit. The comparative analysis is also presented for both the validations.

  9. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    PubMed

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

  10. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    PubMed Central

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  11. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication

    DTIC Science & Technology

    2008-08-25

    This approach combines a semiconductor transistor system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each...hybrid CMOS/nanodevice integrated circuits [10-12]. Such circuit combines a semiconductor transistors system with a nanowire crossbar, with simple two...both with and without embedded metallic clusters), self-assembled molecular monolayers, and thin chalcogenide and crystalline perovskite layers [20

  12. Development of integrated thermionic circuits for high-temperature applications

    NASA Technical Reports Server (NTRS)

    Mccormick, J. B.; Wilde, D.; Depp, S.; Hamilton, D. J.; Kerwin, W.; Derouin, C.; Roybal, L.; Wooley, R.

    1981-01-01

    Integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 C are studied. A set of practical design and performance equations is demonstrated. Experimental results are discussed in which both devices and simple circuits were successfully operated in 5000 C environments for extended periods. It is suggested that ITC's may become an important technology for high temperature instrumentation and control systems in geothermal and other high temperature environments.

  13. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  14. Pseudo-fermions in an Electronic Loss-Gain Circuit

    NASA Astrophysics Data System (ADS)

    Bagarello, F.; Pantano, G.

    2013-12-01

    In some recent papers a loss-gain electronic circuit has been introduced and analyzed within the context of PT-quantum mechanics. In this paper we show that this circuit can be analyzed using the formalism of the so-called pseudo-fermions. In particular we discuss the time behavior of the circuit, and we construct two biorthogonal bases associated to the Liouville matrix used in the treatment of the dynamics. We relate these bases to and , and we also show that a self-adjoint Liouville-like operator could be introduced in the game. Finally, we describe the time evolution of the circuit in an Heisenberg-like representation, driven by a non self-adjoint Hamiltonian.

  15. Integrated Circuit Electromagnetic Susceptibility Investigation - Phase 2. Bipolar NAND Gate Study

    DTIC Science & Technology

    1974-07-26

    INTEGRATED CIRCUIT SUSCEPTIBILITY MOC El 123 26 JULY 1974 II 100 POtER ABSORBED - mW 1000 FIGURE 51 CHARACTERISTICS OF R FOR THE OUTPUT PARASITIC...87117 Commanding Officer, Harry Diamond Laboratory Attn: J. Sweton W. L. Vault H. Dropkin Washington, D. C. 20438 Commander, Naval Electronics

  16. Chaos in Electronic Circuits: Nonlinear Time Series Analysis

    SciTech Connect

    Wheat, Jr., Robert M.

    2003-07-01

    Chaos in electronic circuits is a phenomenon that has been largely ignored by engineers, manufacturers, and researchers until the early 1990’s and the work of Chua, Matsumoto, and others. As the world becomes more dependent on electronic devices, the detrimental effects of non-normal operation of these devices becomes more significant. Developing a better understanding of the mechanisms involved in the chaotic behavior of electronic circuits is a logical step toward the prediction and prevention of any potentially catastrophic occurrence of this phenomenon. Also, a better understanding of chaotic behavior, in a general sense, could potentially lead to better accuracy in the prediction of natural events such as weather, volcanic activity, and earthquakes. As a first step in this improvement of understanding, and as part of the research being reported here, methods of computer modeling, identifying and analyzing, and producing chaotic behavior in simple electronic circuits have been developed. The computer models were developed using both the Alternative Transient Program (ATP) and Spice, the analysis techniques have been implemented using the C and C++ programming languages, and the chaotically behaving circuits developed using “off the shelf” electronic components.

  17. The Induction of Chaos in Electronic Circuits Final Report-October 1, 2001

    SciTech Connect

    R.M.Wheat, Jr.

    2003-04-01

    This project, now known by the name ''Chaos in Electronic Circuits,'' was originally tasked as a two-year project to examine various ''fault'' or ''non-normal'' operational states of common electronic circuits with some focus on determining the feasibility of exploiting these states. Efforts over the two-year duration of this project have been dominated by the study of the chaotic behavior of electronic circuits. These efforts have included setting up laboratory space and hardware for conducting laboratory tests and experiments, acquiring and developing computer simulation and analysis capabilities, conducting literature surveys, developing test circuitry and computer models to exercise and test our capabilities, and experimenting with and studying the use of RF injection as a means of inducing chaotic behavior in electronics. An extensive array of nonlinear time series analysis tools have been developed and integrated into a package named ''After Acquisition'' (AA), including capabilities such as Delayed Coordinate Embedding Mapping (DCEM), Time Resolved (3-D) Fourier Transform, and several other phase space re-creation methods. Many computer models have been developed for Spice and for the ATP (Alternative Transients Program), modeling the several working circuits that have been developed for use in the laboratory. And finally, methods of induction of chaos in electronic circuits have been explored.

  18. Control of electrostatic damage to electronic circuits

    SciTech Connect

    Kirk, W.J. Jr.

    1980-03-01

    Static is caused by the flow of materials and people within an environment. The static voltages generated by these movements can degrade or destroy many solid state devices currently being used in sophisticated electronic equipment. Discharge of static voltages through these sensitive devices during assembly operations can lead to a nonfunctional assembly fabricated from parts which previously were acceptable or to later failure of an assembly which was functional after fabrication. Sources of electrostatic charges, equipment and methods for minimizing the generation of electrostatic voltages during the production, assembly and packaging of solid state electronic equipment, and the sensitivity of solid state devices to electrostatic damage are discussed. It is concluded that static awareness is the key to an effective electrostatic damage (ESD) control program, and that production facilities must incorporate electrostatic protection facilities, materials, and processes so that workers can concentrate on producing a high-quality product without having to be overly concerned about ESD procedures. (LCL)

  19. Single Event Transients in Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  20. PETRIC - A positron emission tomography readout integrated circuit

    SciTech Connect

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  1. Intelligent switches of integrated lightwave circuits with core telecommunication functions

    NASA Astrophysics Data System (ADS)

    Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

    2001-05-01

    We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion loss<5dB, switching time<2ms...), the switch enables additional important build-in functionalities. It enables single-to- single channel switching and single-to-multiple channel multicasting/broadcasting. In addition, it has the capability of channel weighting and variable output power control (attenuation), for instance, to equalize signal levels and compensate for unbalanced different optical input powers, or to equalize unbalanced EDFA gain curve. We examine the market segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

  2. Automatic visual inspection of integrated circuits using an SEM

    SciTech Connect

    Kayaalp, A.E.

    1988-01-01

    The author investigates the complex problem of designing an integrated-circuit inspection system that will be used in controlling an automated semiconductor manufacturing facility. To satisfy the accuracy requirements, he proposes a system that integrates information supplied by multiple intelligent (virtual) sensors. Most of his work concentrated on the design of two scanning-electron-microscope (SEM)-based, intelligent sensors. One of them extracts 3D IC surface-topography information using computer stereo-vision techniques, and the other identifies shape defects in IC patterns using the IC design file as the reference. Both of these problems are viewed as constrained contour-matching problems. In stereo matching, feature contours extracted from the left and right stereo images are matched, where in pattern-shape inspection, pattern boundary contours extracted from the image and the IC design file are matched. An optimization technique is presented for solving the matching problem that results in both cases. This general approach simplifies the task of transforming the specifications of a physical problem into a computational form and results in a modular system.

  3. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    NASA Technical Reports Server (NTRS)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  4. Circulators for microwave and millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Schloemann, Ernst F.

    1988-02-01

    The requirements for circulators for use in combination with microwave and millimeter-wave integrated circuits are reviewed, with special emphasis on modules for phased-array antennas. Recent advances in broadbanding and in miniaturization are summarized. Novel types of circulators that are fabricated by attaching a ferrite disc and a suitable coupling structure to the surface of a dielectric or semiconductor substrate ('quasi-monolithic' integration) are described. Methods for achieving complete monolithic integration are also discussed.

  5. Photonic integrated circuits based on silica and polymer PLC

    NASA Astrophysics Data System (ADS)

    Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

    2013-03-01

    Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

  6. Circuit elements at optical frequencies from first principles: A synthesis of electronic structure and circuit theories

    NASA Astrophysics Data System (ADS)

    Ramprasad, R.; Tang, C.

    2006-08-01

    A first principles electronic structure based method is presented to determine the equivalent circuit representations of nanostructured physical systems at optical frequencies, via a mapping of the effective permittivity calculated for a lattice of physical nano-elements using density functional theory to that calculated for a lattice of impedances using circuit theory. Specifically, it is shown that silicon nanowires and carbon nanotubes can be represented as series combinations of inductance, capacitance and resistance. It is anticipated that the generality of this approach will allow for an alternate description of physical systems at optical frequencies, and in the realization of novel opto- and nanoelectronic devices, including negative refractive index materials.

  7. Thermally-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  8. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  9. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    NASA Astrophysics Data System (ADS)

    Heck, Martijn J. R.

    2016-06-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  10. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    NASA Astrophysics Data System (ADS)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  11. Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

    NASA Astrophysics Data System (ADS)

    Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

    2015-03-01

    This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

  12. Highly integrated electronics for the star TPC

    SciTech Connect

    Arthur, A.A.; Bieser, F.; Hearn, W.; Kleinfelder, S.; Merrick, T.; Millaud, J.; Noggle, T.; Rai, G.; Ritter, H.G.; Wieman, H.

    1991-12-31

    The concept for the STAR TPC front-end electronics is presented and the progress toward the development of a fully integrated solution is described. It is the goal of the R+D program to develop the complete electronics chain for the STAR central TPC detector at RHIC. It is obvious that solutions chosen e.g. for ALEPH are not adequate for the 150000 channels that need to be instrumented for readout. It will be necessary to perform all the signal processing, digitization and multiplexing directly on the detector in order to reduce per channel cost and the amount of cabling necessary to read out the information. We follow the approach chosen by the EOS TPC project, where the readout electronics on the detector consists of an integrated preamplifier, a hybrid shaping amplifier, an integrated switched capacitor array and a highly multiplexed ADC. The STAR electronics will be further integrated so that approximately 16 channels of the preamplifier, the shaper, the analog store and the ADC will be contained in two integrated circuits located directly on the pad plane.

  13. Integrated Circuit Chip Improves Network Efficiency

    NASA Technical Reports Server (NTRS)

    2008-01-01

    Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating

  14. Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

    DTIC Science & Technology

    2008-10-01

    phase switching technique," Electronics Letters, vol. 37, no. 14, pp. 875-877, Jul 2001. [10] W. Dally and B. Towles , Principles and Practices of...and A. Alvandpour, "A six-port 57gb/s double-pumped nonblocking router core," VLSI Circuits, 2005. Digest of Technical Papers . 2005 Symposium on, pp

  15. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  16. FASTHELP. Integrated Circuit Failure Analysis Hypertext Help System

    SciTech Connect

    Henderson, C; Barton, D; Campbell, A; Cole, E; Mikawa, R E; Peterson, K A; Rife, J L; Soden, J M

    1994-09-30

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  17. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1989-09-12

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  18. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, David R.

    1989-01-01

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  19. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    DOEpatents

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  20. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1988-04-20

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

  1. Evaluation performance of digital integrated circuits while exposed to radiation

    NASA Astrophysics Data System (ADS)

    Barbashov, V. M.; Trushkin, N. S.

    2016-10-01

    The methods of functional-logical simulation of digital integrated circuits (ICs) exposed to radiation are observed. It is shown that in a number of cases functional and electrical deterioration of ICs performances have both deterministic and non-deterministic nature. Methods for simulating IC failure exposed to radiation based on the model of fuzzy digital machine and Brauer probabilistic reliability machine are proposed.

  2. Applications of carbon nanotubes on integrated circuits

    NASA Astrophysics Data System (ADS)

    Zhang, Min

    The microelectronics technology falls within the boundaries of that definition. Carbon nanotube (CNT) is a promising alternative material for the future nanoelectronics. Owing to the unique properties of CNTs and the maturity of CMOS IC technology, the integration of the two technologies will take advantages of both. In this work, we demonstrate a new local silicon-gate carbon nanotube field-effect transistor (CNFET) by combining the in situ CNT growth technology and the SOI technology. The proposed CNFET structure has realized individual device operation, batch fabrication, low parasitics and better compatibility to the CMOS process at the same time. The configuration proposes a feasible approach to integrate the CNTs to CMOS platform for the first time, which makes CNT a step closer to application. The CNFETs show advanced DC characteristics. The ambipolar conductance and the scaling effect of the CNFETs have been analyzed based on the SB modulated conductance mechanism. Investigation of radio-frequency (RF) characteristics of CNTs is essential for their application. RF transmission characteristics of the semiconducting and metallic CNTs are investigated to the frequency of 12 GHz using the full two-port S-parameter methodology for the first time. Without the effect of the parasitics, the signal transmission capability of the CNTs maintains at a constant level and shows no degeneration even at a high frequency of 12 GHz. An empirical RLC element model has been proposed to fit the RF response of the CNT array. Capacitive contact is reported between the CNTs and the metal electrodes. We also explore the high-frequency properties of the local silicon-gate CNFET as an active device by measuring its S parameters using a common-source configuration. In addition, we demonstrate the application of CNT as via/contact filler to solve the problems of copper vias used in ICs nowadays. We have optimized the fabrication process for the CNT via integration. The CNT vias with

  3. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  4. Flexible circuits with integrated switches for robotic shape sensing

    NASA Astrophysics Data System (ADS)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  5. Hybrid integration platform based on silica-on-silicon planar lightwave circuit

    NASA Astrophysics Data System (ADS)

    Lin, Wenhua; Sun, C. Jacob; Schmidt, Kevin M.

    2007-02-01

    While silica waveguide PLC products have been deployed in various systems and applications, hybrid integration of semiconductor opto-electronic devices on silica-based planar lightwave circuit (PLC) has become the mainstream platform for small form factor, low-cost and high volume integrated transceiver modules. One of the main benefits of hybrid integration is the wafer-scale process, which greatly reduces chip/module size and assembly cost. This paper reviews the development of this technology, and as an example, presents a hybrid integrated transmitter with four wavelengths on silica PLC chip for LX4 and 10GbE applications.

  6. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    NASA Technical Reports Server (NTRS)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  7. Quantum dot rolled-up microtube optoelectronic integrated circuit.

    PubMed

    Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

    2013-05-15

    A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively.

  8. Modeling of single-event upset in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  9. Transmission line for millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Komar, G. I.; Shestopalov, V. P.

    The advantages of the miniature wideband slotted mirror line (SML) for millimeter-wave integrated circuits is described. It is shown that the SML has the same order of losses in the mm-range as the stripline in the cm-range. In addition, the SML makes possible the planar design of a wide range of functional components and units, and provides for the complex miniaturization of closed antenna-feed systems in the mm-range, which makes it possible to avoid the use of several types of sections in a single circuit. Forms of cross sections of the SML are presented.

  10. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    PubMed Central

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-01-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

  11. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    NASA Astrophysics Data System (ADS)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  12. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    SciTech Connect

    Arefin, Md Shamsul Redoute, Jean-Michel; Rasit Yuce, Mehmet; Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  13. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    NASA Astrophysics Data System (ADS)

    Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

    2014-06-01

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  14. Millimeter-wave and terahertz integrated circuit antennas

    NASA Technical Reports Server (NTRS)

    Rebeiz, Gabriel M.

    1992-01-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  15. Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

    DTIC Science & Technology

    2013-08-01

    package to help avoid errors and rework . II. PCB DATA PACKAGE REQUIREMENTS LIST The technical data package is comprised of documentation including an...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

  16. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  17. Curvilinear electronics formed using silicon membrane circuits and elastomeric transfer elements.

    PubMed

    Ko, Heung Cho; Shin, Gunchul; Wang, Shuodao; Stoykovich, Mark P; Lee, Jeong Won; Kim, Dong-Hun; Ha, Jeong Sook; Huang, Yonggang; Hwang, Keh-Chih; Rogers, John A

    2009-12-01

    Materials and methods to achieve electronics intimately integrated on the surfaces of substrates with complex, curvilinear shapes are described. The approach exploits silicon membranes in circuit mesh structures that can be deformed in controlled ways using thin, elastomeric films. Experimental and theoretical studies of the micromechanics of such curvilinear electronics demonstrate the underlying concepts. Electrical measurements illustrate the high yields that can be obtained. The results represent significant experimental and theoretical advances over recently reported concepts for creating hemispherical photodetectors in electronic eye cameras and for using printable silicon nanoribbons/membranes in flexible electronics. The results might provide practical routes to the integration of high performance electronics with biological tissues and other systems of interest for new applications.

  18. Laser-Controlled Rapid Prototyping of Photonic Integrated Circuits.

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.

    1994-01-01

    Photonic integrated circuits offer important cost and environmental advantages over circuits composed of discrete components. However, the design and fabrication of complex, large-area photonic integrated circuits (PICs) is severely limited by the lack of prototyping tools as well as the appropriate device structures. This thesis describes the use of a novel laser fabrication process for the rapid prototyping of integrated optical circuits in compound semiconductor substrates. The fabrication is based on a type of laser direct photoelectrochemical etching process that uses a focused laser beam which is scanned under computer control to form micrometer-scale grooves, thereby patterning rib-like optical waveguide structures. The computer-controlled apparatus can be programmed with any desired circuit pattern, and prototype waveguide circuits can be produced within a day. The technique does not require the use of a mask; thus, the etching can be done in a single step. In the first part of this thesis, the technique of micrometer-scale photoelectrochemical etching of GaAs is described. The use of this technique for the fabrication of several passive integrated optical devices in GaAs is then presented. These "building block" devices include linear waveguides, bends, Y-branches, and tapers. From these, we were able to form simple passive devices such as splitters and directional couplers. These devices have low optical loss, are single-mode, and can be accurately modeled using effective index calculations. The usefulness of this technique as a prototyping tool is then demonstrated by its use in the fabrication of the first sub-Angstrom integrated channel-dropping filter. After the presentation of the passive devices results, the use of this technique to fabricate several active devices is discussed. These electrooptic devices include a polarization modulator, an integrated amplitude modulator consisting of a polarization modulator and an on-chip polarizer, and an

  19. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, Anthony F.; Malba, Vincent

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  20. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  1. Trends in integrated circuit design for particle physics experiments

    NASA Astrophysics Data System (ADS)

    Atkin, E. V.

    2017-01-01

    Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation.

  2. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ... Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is... importation of certain semiconductor integrated circuit devices and products containing same. The complaint...] [FR Doc No: 2012-7567] INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor...

  3. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-06-10

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions, media players, and...

  4. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-12

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same...

  5. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-06

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... United States after importation of certain semiconductor integrated circuits using tungsten...

  6. Serpentine and corduroy circuits to enhance the stretchability of a stretchable electronic device

    SciTech Connect

    Maghribi, Mariam N.; Krulevitch, Peter A.; Wilson, Thomas S.; Hamilton, Julie K. , Park; Christina

    2007-09-04

    A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.

  7. Serpentine and corduroy circuits to enhance the stretchablity of a stretchable electronic device

    DOEpatents

    Maghribi, Mariam N [Livermore, CA; Krulevitch, Peter A [Pleasanton, CA; Wilson, Thomas S [Castro Valley, CA; Hamilton, Julie K [Tracy, CA; Park, Christina [Cambridge, MA

    2011-01-18

    A stretchable electronic apparatus and method of producing the apparatus. The apparatus has a central longitudinal axis and the apparatus is stretchable in a longitudinal direction generally aligned with the central longitudinal axis. The apparatus comprises a stretchable polymer body, and at least one circuit line operatively connected to the stretchable polymer body, the at least one circuit line extending in the longitudinal direction and having a longitudinal component that extends in the longitudinal direction and having an offset component that is at an angle to the longitudinal direction, the longitudinal component and the offset component allowing the apparatus to stretch in the longitudinal direction while maintaining the integrity of the at least one circuit line.

  8. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  9. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  10. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  11. Integrated circuit generating 3- and 5-scroll attractors

    NASA Astrophysics Data System (ADS)

    Trejo-Guerra, R.; Tlelo-Cuautle, E.; Jiménez-Fuentes, J. M.; Sánchez-López, C.; Muñoz-Pacheco, J. M.; Espinosa-Flores-Verdad, G.; Rocha-Pérez, J. M.

    2012-11-01

    This paper introduces the experimental realization of the first integrated circuit of a multi-scroll continuous chaotic oscillator showing 3- and 5-scroll attractors. It is based on a variant of the Chua's system. The most relevant issue is the implementation of a saw-tooth-like nonlinear function, which is designed by using floating gate MOS (FGMOS) transistors. Therefore, the realization of a voltage-to-current nonlinear cell by a piecewise-linear approach allows us to have only two external control inputs instead of numerous external voltage references, as usually done in current circuit realizations. Experimental results of the proposed integrated multi-scroll oscillator along with its corner analysis are provided.

  12. Broadband opto-mechanical phase shifter for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Guo, Xiang; Zou, Chang-Ling; Ren, Xi-Feng; Sun, Fang-Wen; Guo, Guang-Can

    2012-08-01

    A broadband opto-mechanical phase shifter for photonic integrated circuits is proposed and numerically investigated. The structure consists of a mode-carrying waveguide and a deformable non-mode-carrying nanostring, which are parallel with each other. Since the nanostring can be deflected by the optical gradient force between the waveguide and the nanostring, the effective refractive indices of the waveguide will be changed and a phase shift will be generated. The phase shift under different geometry sizes, launched powers and boundary conditions are calculated and the dynamical properties as well as the thermal noise's effect are also discussed. It is demonstrated that a π phase shift can be realized with only about 0.64 mW launched power and 50 μm long nanostring. The proposed phase shifter may find potential usage in future investigation of photonic integrated circuits.

  13. Transplanted embryonic neurons integrate into adult neocortical circuits.

    PubMed

    Falkner, Susanne; Grade, Sofia; Dimou, Leda; Conzelmann, Karl-Klaus; Bonhoeffer, Tobias; Götz, Magdalena; Hübener, Mark

    2016-11-10

    The ability of the adult mammalian brain to compensate for neuronal loss caused by injury or disease is very limited. Transplantation aims to replace lost neurons, but the extent to which new neurons can integrate into existing circuits is unknown. Here, using chronic in vivo two-photon imaging, we show that embryonic neurons transplanted into the visual cortex of adult mice mature into bona fide pyramidal cells with selective pruning of basal dendrites, achieving adult-like densities of dendritic spines and axonal boutons within 4-8 weeks. Monosynaptic tracing experiments reveal that grafted neurons receive area-specific, afferent inputs matching those of pyramidal neurons in the normal visual cortex, including topographically organized geniculo-cortical connections. Furthermore, stimulus-selective responses refine over the course of many weeks and finally become indistinguishable from those of host neurons. Thus, grafted neurons can integrate with great specificity into neocortical circuits that normally never incorporate new neurons in the adult brain.

  14. Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

    NASA Astrophysics Data System (ADS)

    Geier, Michael

    Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

  15. Aperture efficiency of integrated-circuit horn antennas

    NASA Technical Reports Server (NTRS)

    Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

    1991-01-01

    The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

  16. Monolithic microwave integrated circuit technology for advanced space communication

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Romanofsky, Robert R.

    1988-01-01

    Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

  17. Computer-Aided Engineering of Semiconductor Integrated Circuits

    DTIC Science & Technology

    1979-07-01

    growth and the resulting electrical properties are critical if reproducible device performance is to be achieved. Despite the fact that thermally grown... properties is the continuing decrease in active device This work represents a joint effort by the Stanford University Integrated Circuits Laboratory, Fairchild...goals will allow accurate prediction of oxide and surface properties and the influence of oxidation on other processes for an arbitrary device

  18. Extended life testing evaluation of complementary MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Brosnan, T. E.

    1972-01-01

    The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

  19. Laser Integration on Silicon Photonic Circuits Through Transfer Printing

    DTIC Science & Technology

    2017-03-10

    AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...Form ApprovedOMB No. 0704-0188 The public reporting burden for this collection of information is estimated to average 1 hour per response, including...collection of information . Send comments regarding this burden estimate or   any other aspect of this collection of information , including suggestions

  20. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit.

    PubMed

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-12-21

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10(-9) is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

  1. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    NASA Astrophysics Data System (ADS)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-12-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10-9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

  2. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    PubMed Central

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-01-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than −30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10−9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers. PMID:28000735

  3. Evolution of the Department of Defense Millimeter and Microwave Monolithic Integrated Circuit Program

    DTIC Science & Technology

    2007-02-01

    Dertouzos, Michael; Lester, Richard K.; Solow , Robert M.; Thorow, Lester C., “Toward a New Industrial America Scientific American, June 1989, pp...Vladimir Gelnovatch, Director of the U.S. Army Electronics Technology and Devices Laboratory; and Robert Heaston, Office of Under Secretary of Defense...Jack S. Kilby and Robert N. Noyce shared honors for the achievement. Hybrid microwave and millimeter wave integrated circuits achieved greater

  4. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-01

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of... the sale within the United States after importation of certain semiconductor integrated circuit... semiconductor integrated circuit devices and products containing same that infringe one or more of claims 1,...

  5. 75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-26

    ... COMMISSION In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same..., and sale within the United States after importation of certain encapsulated integrated circuit devices... encapsulated integrated circuit devices and products contains same in connection with claims 1- 4, 7, 17,...

  6. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-02-04

    ... COMMISSION In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice... importation, and sale within the United States after importation of certain semiconductor integrated circuits... infringement certain LSI integrated circuits, as well as certain Seagate hard disk drives that contain...

  7. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-23

    ... COMMISSION Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation... integrated circuit chips and products containing the same by reason of infringement of certain claims of U.S... importation of certain integrated circuit chips and products containing the same that infringe one or more...

  8. 77 FR 1505 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-01-10

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice... importation, and the sale within the United States after importation of certain integrated circuits, chipsets... importation, or the sale within the United States after importation of certain integrated circuits,...

  9. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-02-14

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of... received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938..., and the sale within the United States after importation of certain integrated circuit devices...

  10. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-05-05

    ... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... the sale within the United States after importation of certain large scale integrated circuit... certain large scale integrated circuit semiconductor chips or products containing the same that...

  11. Photonic-integrated circuit for continuous-wave THz generation.

    PubMed

    Theurer, Michael; Göbel, Thorsten; Stanze, Dennis; Troppenz, Ute; Soares, Francisco; Grote, Norbert; Schell, Martin

    2013-10-01

    We demonstrate a photonic-integrated circuit for continuous-wave (cw) terahertz (THz) generation. By comprising two lasers and an optical phase modulator on a single chip, the full control of the THz signal is enabled via a unique bidirectional operation technique. Integrated heaters allow for continuous tuning of the THz frequency over 570 GHz. Applied to a coherent cw THz photomixing system operated at 1.5 μm optical wavelength, we reach a signal-to-noise ratio of 44 dB at 1.25 THz, which is identical to the performance of a standard system based on discrete components.

  12. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    SciTech Connect

    Rath, P.; Ummethala, S.; Pernice, W. H. P.; Diewald, S.; Lewes-Malandrakis, G.; Brink, D.; Heidrich, N.; Nebel, C.

    2014-12-22

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions.

  13. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    PubMed

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-06-18

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  14. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    PubMed Central

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-01-01

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

  15. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    PubMed

    Hall, Trevor J; Hasan, Mehedi

    2016-04-04

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  16. Design and fabrication of an implantable cortical semiconductor integrated circuit electrode array

    NASA Astrophysics Data System (ADS)

    Lefevre, Pierre K.

    1990-12-01

    This research furthered the processing steps of the AFIT 16 by 16 implantable cortical semiconductor integrated circuit electrode array, or brain chip. The areas of interest include the brain chip electronics, metallization, ionic permeation, and implantation. The electronics and metallization are heavily covered. A high speed, single clock divide-by-two circuit was modified with a reset transistor and cascaded to form a ripple counter. This device had stable operation at specific source voltage and clock voltage and frequency. A 7-stage inverter with 10 unmodified divide-by-two circuits cascaded operated between 1.7 and 8 volts, and between 39 KHz and 1 MHz, respectively. The metallization process refers to coating Au/Ni or Pt onto exposed aluminum areas (pads) of a CMOS integrated circuit. Sputtering was used to coat the chip. And an Au/Ni etchant or Pt peel-off technique was used. The Au/Ni etchant used was iodine, potassium iodide, and deionized water solution.

  17. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

    2000-01-01

    We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

  18. Hybrid III-V/silicon SOA for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Kaspar, P.; Brenot, R.; Le Liepvre, A.; Accard, A.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Duan, G.-H.; Olivier, S.; Jany, Christophe; Kopp, C.; Menezo, S.

    2014-11-01

    Silicon photonics has reached a considerable level of maturity, and the complexity of photonic integrated circuits (PIC) is steadily increasing. As the number of components in a PIC grows, loss management becomes more and more important. Integrated semiconductor optical amplifiers (SOA) will be crucial components in future photonic systems for loss compensation. In addition, there are specific applications, where SOAs can play a key role beyond mere loss compensation, such as modulated reflective SOAs in carrier distributed passive optical networks or optical gates in packet switching. It is, therefore, highly desirable to find a generic integration platform that includes the possibility of integrating SOAs on silicon. Various methods are currently being developed to integrate light emitters on silicon-on-insulator (SOI) waveguide circuits. Many of them use III-V materials for the hybrid integration on SOI. Various types of lasers have been demonstrated by several groups around the globe. In some of the integration approaches, SOAs can be implemented using essentially the same technology as for lasers. In this paper we will focus on SOA devices based on a hybrid integration approach where III-V material is bonded on SOI and a vertical optical mode transfer is used to couple light between SOI waveguides and guides formed in bonded III-V semiconductor layers. In contrast to evanescent coupling schemes, this mode transfer allows for a higher confinement factor in the gain material and thus for efficient light amplification over short propagation distances. We will outline the fabrication process of our hybrid components and present some of the most interesting results from a fabricated and packaged hybrid SOA.

  19. Tomonaga-Luttinger physics in electronic quantum circuits.

    PubMed

    Jezouin, S; Albert, M; Parmentier, F D; Anthore, A; Gennser, U; Cavanna, A; Safi, I; Pierre, F

    2013-01-01

    In one-dimensional conductors, interactions result in correlated electronic systems. At low energy, a hallmark signature of the so-called Tomonaga-Luttinger liquids is the universal conductance curve predicted in presence of an impurity. A seemingly different topic is the quantum laws of electricity, when distinct quantum conductors are assembled in a circuit. In particular, the conductances are suppressed at low energy, a phenomenon called dynamical Coulomb blockade. Here we investigate the conductance of mesoscopic circuits constituted by a short single-channel quantum conductor in series with a resistance, and demonstrate a proposed link to Tomonaga-Luttinger physics. We reformulate and establish experimentally a recently derived phenomenological expression for the conductance using a wide range of circuits, including carbon nanotube data obtained elsewhere. By confronting both conductance data and phenomenological expression with the universal Tomonaga-Luttinger conductance curve, we demonstrate experimentally the predicted mapping between dynamical Coulomb blockade and the transport across a Tomonaga-Luttinger liquid with an impurity.

  20. Design and status of the RF-digitizer integrated circuit

    NASA Technical Reports Server (NTRS)

    Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

    1991-01-01

    An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

  1. Automatic layout of integrated-optics time-of-flight circuits

    NASA Astrophysics Data System (ADS)

    Kennett-Fogg, Ruth D.

    1995-04-01

    This work describes the architecture and algorithms used in the computer aided design tool developed for the automatic layout of integrated optic, time of flight circuit designs. This is similar to the layout of electronic VLSI circuits, where total wire length and chip area minimization are the major goals. Likewise, total wire length and chip area minimization are also the goals in the layout of time of flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time of flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. Secondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. The assumed development of integrated corner turning mirrors allows the use of a parallel, row based device placement architecture and a rectangular, fixed grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time of flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.

  2. InP-based three-dimensional photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  3. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications.

  4. Electron tunneling infrared sensor module with integrated control circuitry

    NASA Technical Reports Server (NTRS)

    Boyadzhyan-Sevak, Vardkes V. (Inventor)

    2001-01-01

    In an integrated electron tunneling sensor, an automatic tunneling control circuit varies a high voltage bias applied to the sensor deflection electrode in response to changes in sensor output to maintain the proper gap between the sensor tip and membrane. The control circuit ensures stable tunneling activity in the presence of large signals and other disturbances to the sensor. Output signals from the module may be derived from the amplified sensor output. The integrated sensor module is particularly well adapted for use in blood glucose measurement and monitoring system.

  5. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    PubMed Central

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

  6. Adaptive Voltage Management Enabling Energy Efficiency in Nanoscale Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Shapiro, Alexander E.

    Battery powered devices emphasize energy efficiency in modern sub-22 nm CMOS microprocessors rendering classic power reduction solutions not sufficient. Classical solutions that reduce power consumption in high performance integrated circuits are superseded with novel and enhanced power reduction techniques to enable the greater energy efficiency desired in modern microprocessors and emerging mobile platforms. Dynamic power consumption is reduced by operating over a wide range of supply voltages. This region of operation is enabled by a high speed and power efficient level shifter which translates low voltage digital signals to higher voltages (and vice versa), a key component that enables communication among circuits operating at different voltage levels. Additionally, optimizing the wide supply voltage range of signals propagating across long interconnect enables greater energy savings. A closed-form delay model supporting wide voltage range is developed to enable this capability. The model supports an ultra-wide voltage range from nominal voltages to subthreshold voltages, and a wide range of repeater sizes. To mitigate the drawback of lower operating speed at reduced supply voltages, the high performance exhibited by MOS current mode logic technology is exploited. High performance and energy efficient circuits are enabled by combining this logic style with power efficient near threshold circuits. Many-core systems that operate at high frequencies and process highly parallel workloads benefit from this combination of MCML with NTC. Due to aggressive scaling, static power consumption can in some cases overshadow dynamic power. Techniques to lower leakage power have therefore become an important objective in modern microprocessors. To address this issue, an adaptive power gating technique is proposed. This technique utilizes high levels of granularity to save additional leakage power when a circuit is active as opposed to standard power gating that saves static

  7. Scalability issues in evolutionary synthesis of electronic circuits: lessons learned and challenges ahead

    NASA Technical Reports Server (NTRS)

    Stoica, A.; Keymeulen, D.; Zebulum, R. S.; Ferguson, M. I.

    2003-01-01

    This paper describes scalability issues of evolutionary-driven automatic synthesis of electronic circuits. The article begins by reviewing the concepts of circuit evolution and discussing the limitations of this technique when trying to achieve more complex systems.

  8. Mechanical Designs for Inorganic Stretchable Circuits in Soft Electronics

    PubMed Central

    Wang, Shuodao; Huang, Yonggang; Rogers, John A.

    2016-01-01

    Mechanical concepts and designs in inorganic circuits for different levels of stretchability are reviewed in this paper, through discussions of the underlying mechanics and material theories, fabrication procedures for the constituent microscale/nanoscale devices, and experimental characterization. All of the designs reported here adopt heterogeneous structures of rigid and brittle inorganic materials on soft and elastic elastomeric substrates, with mechanical design layouts that isolate large deformations to the elastomer, thereby avoiding potentially destructive plastic strains in the brittle materials. The overall stiffnesses of the electronics, their stretchability, and curvilinear shapes can be designed to match the mechanical properties of biological tissues. The result is a class of soft stretchable electronic systems that are compatible with traditional high-performance inorganic semiconductor technologies. These systems afford promising options for applications in portable biomedical and health-monitoring devices. Mechanics theories and modeling play a key role in understanding the underlining physics and optimization of these systems. PMID:27668126

  9. Integrated Defensive Electronic Countermeasures (IDECM)

    DTIC Science & Technology

    2015-12-01

    Selected Acquisition Report (SAR) RCS: DD-A&T(Q&A)823-418 Integrated Defensive Electronic Countermeasures (IDECM) As of FY 2017 President’s Budget...Program Office Estimate RDT&E - Research, Development, Test, and Evaluation SAR - Selected Acquisition Report SCP - Service Cost Position TBD - To Be

  10. Polymer planar lightwave circuit based hybrid-integrated coherent receiver for advanced modulation signals

    NASA Astrophysics Data System (ADS)

    Wang, Jin; Han, Yang; Liang, Zhongcheng; Chen, Yongjin

    2012-11-01

    Applying coherent detection technique to advanced modulation formats makes it possible to electronically compensate the signal impairments. A key issue for a successful deployment of coherent detection technique is the availability of cost-efficient and compact integrated receivers, which are composed of an optical 90° hybrid mixer and four photodiodes (PDs). In this work, three different types of optical hybrids are fabricated with polymer planar lightwave circuit (PLC), and hybridly integrated with four vertical backside illuminated III-V PDs. Their performances, such as the insertion loss, the transmission imbalance, the polarization dependence and the phase deviation of 90° hybrid will be discussed.

  11. Compact electronic soma and synapse circuits fabricated using a low temperature approach

    NASA Astrophysics Data System (ADS)

    Subramaniam, Anand

    Digital circuits using the von Neumann architecture and complementary metal-oxide-semiconductor (CMOS) electronic devices dominate large-scale processing systems today and are extremely efficient at performing well-defined operations. However, these systems are less efficient at tasks which involve processing large amounts of imprecise information originating from the surrounding environment, such as pattern recognition and outcome prediction. The human brain is the best processor of such information sets, and consists of a large number of primitive elements (1010 neurons and 1014 synapses). Neuromorphic systems are a class of circuits that draw inspiration from the extremely parallel architecture of the brain. A major goal is thus to develop neuromorphic circuits using a large-area, low-power, and highly dense approach. The major focus of this work is the fabrication of a compact circuit which can implement a biologically realistic synaptic learning rule using low-temperature materials. Ambipolar nanocrystalline-silicon (nc-Si) thin-film transistors (TFTs) are selected as basic building blocks of spiking soma circuits. These TFTs are fabricated at the nanoscale using a CMOS-compatible fabrication process at a maximum temperature of 250 °C. High-κ gate dielectrics are incorporated to achieve lower subthreshold swings and threshold voltages. Soma circuits which consist of a few nc-Si TFTs and capacitors are fabricated and shown to display spiking behavior similar to biological neurons. Electronic synapses are fabricated using Au nanoparticle (NP) memory devices based on nc-Si TFTs and TiN/HfO2/TiN memristors. These are then integrated with the soma circuit to achieve an action potential pair-based learning rule, namely spike-timing-dependent plasticity (STDP). The STDP rule is experimentally demonstrated for the first time using simple rectangular voltage pulses alone. The soma circuits are shown to be capable of driving a significant number of synapses in a large

  12. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    PubMed

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  13. Integrated circuits: Resistless processing simplifies production and cuts costs

    NASA Astrophysics Data System (ADS)

    Weiner, K.

    1993-03-01

    Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today's industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, 'cluster' processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

  14. Implantable neurotechnologies: a review of integrated circuit neural amplifiers

    PubMed Central

    Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

  15. The integration of cryogenic cooling systems with superconducting electronic systems

    SciTech Connect

    Green, Michael A.

    2003-07-01

    The need for cryogenic cooling has been critical issue that has kept superconducting electronic devices from reaching the market place. Even though the performance of the superconducting circuit is superior to silicon electronics, the requirement for cryogenic cooling has put the superconducting devices at a disadvantage. This report will talk about the various methods for refrigerating superconducting devices. Cryocooler types will be compared for vibration, efficiency, and cost. Some solutions to specific problems of integrating cryocoolers to superconducting devices are presented.

  16. Heavy-ion induced single-event upset in integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1991-01-01

    The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

  17. Universal nondestructive mm-wave integrated circuit test fixture

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert R. (Inventor); Shalkhauser, Kurt A. (Inventor)

    1990-01-01

    Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

  18. Cycles of self-pulsations in a photonic integrated circuit.

    PubMed

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  19. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    1995-01-01

    An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

  20. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, E.I. Jr.; Soden, J.M.

    1995-07-04

    An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

  1. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

    1997-01-01

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

  2. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  3. State-transfer simulation in integrated waveguide circuits

    NASA Astrophysics Data System (ADS)

    Latmiral, L.; Di Franco, C.; Mennea, P. L.; Kim, M. S.

    2015-08-01

    Spin-chain models have been widely studied in terms of quantum information processes, for instance for the faithful transmission of quantum states. Here, we investigate the limitations of mapping this process to an equivalent one through a bosonic chain. In particular, we keep in mind experimental implementations, which the progress in integrated waveguide circuits could make possible in the very near future. We consider the feasibility of exploiting the higher dimensionality of the Hilbert space of the chain elements for the transmission of a larger amount of information, and the effects of unwanted excitations during the process. Finally, we exploit the information-flux method to provide bounds to the transfer fidelity.

  4. SiGe/Si Monolithically Integrated Amplifier Circuits

    NASA Technical Reports Server (NTRS)

    Katehi, Linda P. B.; Bhattacharya, Pallab

    1998-01-01

    With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

  5. Stainless Steel NaK Circuit Integration and Fill Submission

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

  6. DVD Based Integrated Electronic Pulser

    SciTech Connect

    Hughes, Michael A.; Kouzes, Richard T.; Morris, Scott J.; Pitts, W. K.; Pratt, Rick M.; Robinson, Eric E.

    2004-03-30

    The DVD based integrated pulser combines the storage capacity and simplicity of DVD technology with commonly available electronic components to build a relatively inexpensive yet highly capable testing instrument. DVD technology has matured to the mass consumer level and has found widespread acceptance in many scientific, industrial, and consumers sectors. Coupling the removable media and relatively large data capacity with a simple electronic readout allows this device to be easy to build, export and authenticate. Since there are few parts and the heart of the device is a mass consumer item the duplication cost is very low.

  7. Bipolar integrated circuits in SiC for extreme environment operation

    NASA Astrophysics Data System (ADS)

    Zetterling, Carl-Mikael; Hallén, Anders; Hedayati, Raheleh; Kargarrazi, Saleh; Lanni, Luigia; Malm, B. Gunnar; Mardani, Shabnam; Norström, Hans; Rusu, Ana; Saveda Suvanam, Sethu; Tian, Ye; Östling, Mikael

    2017-03-01

    Silicon carbide (SiC) integrated circuits have been suggested for extreme environment operation. The challenge of a new technology is to develop process flow, circuit models and circuit designs for a wide temperature range. A bipolar technology was chosen to avoid the gate dielectric weakness and low mobility drawback of SiC MOSFETs. Higher operation temperatures and better radiation hardness have been demonstrated for bipolar integrated circuits. Both digital and analog circuits have been demonstrated in the range from room temperature to 500 °C. Future steps are to demonstrate some mixed signal circuits of greater complexity. There are remaining challenges in contacting, metallization, packaging and reliability.

  8. Development of optical packet and circuit integrated ring network testbed.

    PubMed

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated.

  9. Integrated circuit amplifiers for multi-electrode intracortical recording.

    PubMed

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  10. Irradiation of electronic components and circuits at the Portuguese Research Reactor: Lessons learned

    SciTech Connect

    Marques, J.G.; Ramos, A.R.; Fernandes, A.C.; Santos, J.P.

    2015-07-01

    The behavior of electronic components and circuits under radiation is a concern shared by the nuclear industry, the space community and the high-energy physics community. Standard commercial components are used as much as possible instead of radiation hard components, since they are easier to obtain and allow a significant reduction of costs. However, these standard components need to be tested in order to determine their radiation tolerance. The Portuguese Research Reactor (RPI) is a 1 MW pool-type reactor, operating since 1961. The irradiation of electronic components and circuits is one area where a 1 MW reactor can be competitive, since the fast neutron fluences required for testing are in most cases well below 10{sup 16} n/cm{sup 2}. A program was started in 1999 to test electronics components and circuits for the LHC facility at CERN, initially using a dedicated in-pool irradiation device and later a beam line with tailored neutron and gamma filters. Neutron filters are essential to reduce the intensity of the thermal neutron flux, which does not produce significant defects in electronic components but produces unwanted radiation from activation of contacts and packages of integrated circuits and also of the printed circuit boards. In irradiations performed within the line-of-sight of the core of a fission reactor there is simultaneous gamma radiation which complicates testing in some cases. Filters can be used to reduce its importance and separate testing with a pure gamma radiation source can contribute to clarify some irradiation results. Practice has shown the need to introduce several improvements to the procedures and facilities over the years. We will review improvements done in the following areas: - Optimization of neutron and gamma filters; - Dosimetry procedures in mixed neutron / gamma fields; - Determination of hardness parameter and 1 MeV-equivalent neutron fluence; - Temperature measurement and control during irradiation; - Follow-up of reactor

  11. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  12. Graphene/Si CMOS hybrid hall integrated circuits.

    PubMed

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  13. Integrated circuit design considerations for spacecraft VLSI implemented in standard CMOS processes

    NASA Astrophysics Data System (ADS)

    Martin, Mark Noel

    2000-10-01

    In this dissertation I will examine issues concerning the use of custom Application Specific Integrated Circuits (ASIC)s, fabricated at commercial foundries, for use in spacecraft. I will examine this subject from the fabrication, device, circuit and system level. I begin with an overview of integrated circuit fabrication and post processing technology used to physically alter the circuit and enhance its electrical performance. I examine the MOS transistor and its variant the Floating-Gate MOS transistor from a device perspective. I discuss a model, derived from the electrostatics of the MOS structure, that is continuous over the entire region of operation while maintaining a small set of physical parameters. Secondly, the operation of the Floating-Gate MOSFET, a device finding increasing usage in adaptive systems, will be presented. The model is then expanded to include the effects of exposure to ionizing radiation on MOSFETs. From a circuit perspective, I will examine the issue of power and energy usage in a digital system. The current-mode design approach will be reviewed as an introduction to Current-Mode-Differential-Logic, a low energy logic family. I will discuss Floating-Gate-Logic, an application of floating-gate transistors to solve the low-power problem by adjusting device thresholds. The second half of the dissertation will be focused on radiation effects in MOS devices. I begin by describing the, rather unpleasant, environment that spacecraft operate in. I continue with a discussion on two main effects of radiation exposure that engineers need to contend with, radiation induced latchup and total-dose exposure. I will provide results from different experiments designed to evaluate a commercial CMOS process's usability for a space application. Finally I describe an application that utilizes the negative effects of radiation on floating-gate MOS devices, an integrated, electronic micro-dosimeter.

  14. Student use of model-based reasoning when troubleshooting an electronic circuit

    NASA Astrophysics Data System (ADS)

    Lewandowski, Heather; Stetzer, Mackenzie; van de Bogart, Kevin; Dounas-Frazer, Dimitri

    2016-03-01

    Troubleshooting systems is an integral part of experimental physics in both research and educational settings. Accordingly, ability to troubleshoot is an important learning goal for undergraduate physics lab courses. We investigate students' model-based reasoning on a troubleshooting task using data collected in think-aloud interviews during which pairs of students from two institutions attempted to diagnose and repair a malfunctioning circuit. Our analysis scheme was informed by the Experimental Modeling Framework, which describes physicists' use of mathematical and conceptual models when reasoning about experimental systems. We show that system and subsystem models were crucial for the evaluation of repairs to the circuit and played an important role in some troubleshooting strategies. Finally, drawing on data from interviews with electronics instructors from a broad range of institution types, we outline recommendations for model-based approaches to teaching and learning troubleshooting skills.

  15. Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits

    SciTech Connect

    Keast, Craig

    2007-02-28

    Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

  16. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    NASA Astrophysics Data System (ADS)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  17. E-Learning System for Experiments Involving Construction of Practical Electronic Circuits

    ERIC Educational Resources Information Center

    Takemura, Atsushi

    2013-01-01

    This paper proposes a novel e-learning system for technical experiments involving the construction of practical electronic circuits; this system would meet the various demands of individual experimenters. This mixed mode is beneficial for practical use in that an experimenter who does not have sufficient circuit components for circuit making can…

  18. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    PubMed

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  19. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q.; Enquist, P.M.

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  20. An Electronics Course: Part II--Some of the Circuits.

    ERIC Educational Resources Information Center

    James, Frank

    1981-01-01

    Describes and illustrates the following electric circuits suitable for student construction: basic circuit, dimmer, multivibrators, amplifiers, schmitt trigger, op-amplifier, radio reception, transmitter, sound effects generators, intercoms, and laboratory amplifier. (SK)

  1. Long-wavelength photonic integrated circuits and avalanche photodetectors

    NASA Astrophysics Data System (ADS)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  2. Wafer-scale boundary value integrated circuit architecture

    SciTech Connect

    Delgado-Frias, J.G.

    1986-01-01

    Wafer scale integration (WSI) technology offers the potential for improving speed and reliability of a large integrated circuit system. An architecture is presented for a boundary value integrated circuit engine which lends itself to implementation in WSI. The philosophy underpinning this architecture includes local communication, cell regularity, and fault tolerance. The research described here proposes, investigates, and simulates this computer architecture and its flaw avoidance schemes for a WSI implementation. Boundary value differential equation computations are utilized in a number of scientific and engineering applications. A boundary value machine is ideally suited for solutions of finite difference and finite element problems with specified boundary values. The architecture is a 2-D array of computational cells. Each basic cell has four bit serial processing elements (PEs) and a local memory. Most communications is limited to transfer between adjacent PEs to reduce complexity, avoid long delays, and localize the effects of silicon flaws. Memory access time is kept short by restricting memory service to PEs in the same cell. I/O operation is performed by means of a row multiple single line I/O bus, which allows fast, reliable and independent data transference. WSI yield losses are due to gross defects and random defects. Gross defects which affect large portions of the wafer are usually fatal for any WSI implementation. Overcoming random defects which cover either a small area or points is achieved by defect avoidance schemes that are developed for this architecture. Those schemes are provided at array, cell, and communication level. Capabilities and limitations of the proposed WSI architecture can be observed through the simulations. Speed degradation of the array and the PE due to silicon defects is observed by means of simulation. Also, module and bus utilization are computed and presented.

  3. 77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-09-18

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions... found that those Zoran products that were adjudicated in Integrated Circuits I are precluded under the... recommended a limited exclusion order barring entry of Zoran's and MediaTek's infringing integrated...

  4. Novel technique for reliability testing of silicon integrated circuits

    NASA Astrophysics Data System (ADS)

    LeMinh, Phuong; Wallinga, H.; Woerlee, P. H.; van den Berg, Albert; Holleman, J.

    2001-04-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.

  5. Investigation of failure mechanisms in integrated vacuum circuits

    NASA Technical Reports Server (NTRS)

    Rosengreen, A.

    1972-01-01

    The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

  6. Advanced polymer systems for optoelectronic integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Stengel, Kelly M. T.; Shacklette, Lawrence W.; Norwood, Robert A.; Xu, Chengzeng; Wu, Chengjiu; Yardley, James T.

    1997-01-01

    An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness, loss, and stability against yellowing and humidity. These monomers are intermiscible, providing for precise adjustment of the refractive index from 1.30 to 1.60. Waveguides are formed photolithographically, with the liquid monomer mixture polymerizing upon illumination in the UV via either mask exposure or laser direct-writing. A wide range of rigid and flexible substrates can be used, including glass, quartz, oxidized silicon, glass-filled epoxy printed circuit board substrate, and flexible polyimide film. We discuss the use of these materials on chips and on multi-chip modules (MCMs), specifically in transceivers where we adaptively produced waveguides on vertical-cavity surface-emitting lasers (VCSELs) embedded in transmitter MCMs and on high- speed photodetector chips in receiver MCMs. Light coupling from and to chips is achieved by cutting 45 degree mirrors using excimer laser ablation. The fabrication of our polymeric structures directly on the modules provides for stability, ruggedness, and hermeticity in packaging.

  7. Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

    PubMed

    Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

    2005-09-01

    This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB.

  8. Minimizing the area required for time constants in integrated circuits

    NASA Technical Reports Server (NTRS)

    Lyons, J. C.

    1972-01-01

    When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

  9. Integrated circuit for processing a low-frequency signal from a seismic detector

    SciTech Connect

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A. Fedorov, R. A.

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  10. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    PubMed

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-06

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

  11. IRIS (Integrity and Reliability in Integrated Circuits) Test Article Generation (ITAG)

    DTIC Science & Technology

    2015-03-31

    Projects Agency Microsystems Technology Office (MTO) Administrative Point of Contact Ms. Brigidann Cooper, brigidannc@usc.edu University of Southern...lifespan of these components. DARPA’s Microelectronics Technology Office established the Integrity and Reliability in Integrated Circuits (IRIS...in a cost-effective manner on State of the Art (SoA) process technologies 15. SUBJECT TERMS 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF 18

  12. Monolithic microwave integrated circuit devices for active array antennas

    NASA Technical Reports Server (NTRS)

    Mittra, R.

    1984-01-01

    Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

  13. Uncertain behaviours of integrated circuits improve computational performance

    PubMed Central

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  14. Apparatus and method for defect testing of integrated circuits

    SciTech Connect

    Cole, E.I. Jr.; Soden, J.M.

    2000-02-29

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  15. Wireless Neural Recording With Single Low-Power Integrated Circuit

    PubMed Central

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  16. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  17. Plasmonic nanopatch array for optical integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  18. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  19. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  20. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  1. Infrared transparent graphene heater for silicon photonic integrated circuits.

    PubMed

    Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

    2016-04-18

    Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

  2. Integrated Sagnac loop mirror circuit for fiber laser

    NASA Astrophysics Data System (ADS)

    Lee, Tae Ho; Kim, Chang-Seok; Jeong, Myung Yung

    2007-02-01

    Broadband reflection mirror is an important optical device to make a wide resonance bandwidth of the multi-wavelength fiber laser cavity including fiber Bragg grating mirrors. Though a chirped fiber Bragg grating has been used for broadband reflection mirror device, it still requires more improvements in the control of reflection wavelength bandwidth and reflection ratio, which are key design parameters of broadband reflection mirror. In this research, we propose an integrated mirror circuit based on polarization-maintaining fiber Sagnac loop interferometer to utilize for tunable resonance cavity of fiber laser with semiconductor optical amplifier. It is available to control both resonance bandwidth by varying the length of polarization-maintaining fiber and reflection ratio by tuning the polarization state of Sagnac loop. Broad resonance bandwidth of 40 nm could be obtained from Sagnac mirror with thes 0.15 m length of polarization-maintaining fiber.

  3. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

  4. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built.

  5. Organic–Inorganic Eu3+/Tb3+ codoped hybrid films for temperature mapping in integrated circuits

    PubMed Central

    Brites, Carlos D. S.; Lima, Patrícia P.; Silva, Nuno J. O.; Millán, Angel; Amaral, Vitor S.; Palacio, Fernando; Carlos, Luís D.

    2013-01-01

    The continuous decrease on the geometric size of electronic devices and integrated circuits generates higher local power densities and localized heating problems that cannot be characterized by conventional thermographic techniques. Here, a self-referencing intensity-based molecular thermometer involving a di-ureasil organic-inorganic hybrid thin film co-doped with Eu3+ and Tb3+ tris (β-diketonate) chelates is used to obtain the temperature map of a FR4 printed wiring board with spatio-temporal resolutions of 0.42 μm/4.8 ms. PMID:24790938

  6. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    SciTech Connect

    Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-17

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  7. Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics

    NASA Astrophysics Data System (ADS)

    Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.

    2015-02-01

    Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

  8. Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

    NASA Technical Reports Server (NTRS)

    Johnston, Allan H.; Rax, Bernard G.

    2006-01-01

    This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

  9. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    NASA Astrophysics Data System (ADS)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  10. Interactive Electronic Circuit Simulation on Small Computer Systems

    DTIC Science & Technology

    1979-11-01

    this is the most effective way of completing a computer-aided engineering design cycle. Compar- isons of the interactive versus batch simulation...run on almost any computer system with few if any modifications. Also included are the four benchmark test circuits which were used in many of the...the ensuing FORTRAN version. 2.2 Circuit Simulation Using BIAS-D (BASIC Version) Any circuit-simulation program can be di- vided into three

  11. Integrative approach to teaching electronics design

    NASA Astrophysics Data System (ADS)

    Bailey, Donald G.; Mercer, Ken; O'Driscoll, Bob; Plaw, Colin; Page, Wyatt H.; Nilson, Ross

    2000-10-01

    Students in the introductory electronics papers work together on a group project in parallel with their regularly scheduled lectures and laboratories. Each team of four students has to design and construct a complex electronic system. The staff involved with the project act as consultants to the design teams. The project is integrative in that it combines together a wide range of tools and techniques form across the spectrum of topics covered in lectures. The system to be designed is split into seven modules, with each module defined explicitly through a set of specifications. For each module, students are required to design a suitable circuit to meet the specifications, verify their design through simulation, prototype their design on breadboard, and realize their design on a PCB. By running the design project in parallel with the theory, the project improves the students understanding of the theory at the same time as developing design skills. An important factor to the success of the project is that the students find it fun.

  12. A multi-channel integrated readout circuit (MIROC) chip for solid state charged particle detectors

    NASA Astrophysics Data System (ADS)

    He, Xiang

    2011-12-01

    Various electronic amplifier systems have been developed during the past years for solid state detectors for energetic charged particle detection. Most of them were based on the design of discrete parts or high performance hybrid packaged chips. With rapid development of modern integrated circuit industry, there are more and more integrated systems built for such applications. This work describes a novel multi-channel integrated readout circuit (MIROC) mixed-signal ASIC for solid stage charged particle detectors. The chip contains nineteen analog amplifier channels including the test channel, three on-chip 8-bit ADCs, each equipped with a 8-bit parallel-to-serial shift register, three 19-input analog multiplexers, and other digital control logic modules. This was the first known integrated readout system with multiple channels and multiple ADCs, by the time the project started. The chip is designed with special interest in 1MeV electrons. It is a highly integrated system that only requires minimal external controls, which could significantly reduce cost, space, power and total mass of the readout system, and reduce the development cycle of new instruments. MIROC chip was fabricated with IBM 7WL 0.18microm SiGe BiCMOS technology through MOSIS MEP research license, and has been tested, with key components characterized. Measured only 4mmx4mm, this highly integrated readout system has a FWHM noise below 20keV. The four configurable conversion gain levels of the amplifier chains, measured to be 164mV/MeV, 378mV/MeV, 611mV/MeV and 950mV/MeV, make the chip capable of studying energetic charged particles over the range of 100keV up to 6MeV.

  13. SDN architecture for optical packet and circuit integrated networks

    NASA Astrophysics Data System (ADS)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  14. Paper-based silver-nanowire electronic circuits with outstanding electrical conductivity and extreme bending stability.

    PubMed

    Huang, Gui-Wen; Xiao, Hong-Mei; Fu, Shao-Yun

    2014-08-07

    Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated.

  15. Silicon hybrid Wafer Scale Integration (WSI) used to fabricate a Hilbert transform integrated circuit module

    NASA Astrophysics Data System (ADS)

    Gaughan, Daniel J.

    1990-12-01

    This research was performed in order to develop a superior processing schedule for fabricating wafer-scale integration (WSI) circuit modules. This technology allows the design of circuitry that spans the entire surface of a silicon substrate wafer. The circuit element employed in this research was the Hilbert transform, a digital phase-shifting circuit. The transform was incorporated into a three integrated circuit (IC) die package that consisted of a mechanically supportive silicon wafer, three IC die, and a planarizing silicon wafer. The die were epoxied into this wafer using a Teflon block as a flat, and the combination was epoxied onto the substrate wafer, forming the IC module. The original design goals of this research were to keep the IC die and wafer planar and to electrically characterize of the module's interconnections. The first goal was met; the resultant process uses a low temperature (50 C) cure to achieve die-to-wafer planarity of within 5 microns. The second was not met due to the inability to pattern the chosen photosensitive dielectric material. Recommendations for further research included the need to use a stable non-stick surface as a epoxy cure fixture and the need to investigate the photopatternable dielectric material.

  16. Closed circuit recovery of copper, lead and iron from electronic waste with citrate solutions.

    PubMed

    Torres, Robinson; Lapidus, Gretchen T

    2017-02-01

    An integral closed circuit hydrometallurgical process is presented for base metal recovery from electronic waste. The leaching medium consists of a sodium citrate solution, from which base metals are retrieved by direct electrowinning, and the barren solution is recycled back to the leaching stage. This leaching-electrowinning cycle was repeated four times. The redox properties of the fresh citrate solution, as well as the leach liquors, were characterized by cyclic voltammetry to determine adequate conditions for metal reduction, as well as to limit citrate degradation. The leaching efficiency of electronic waste, employing the same solution after four complete cycles was 71, 83 and 94% for copper, iron and lead, respectively, compared to the original leach with fresh citrate solution.

  17. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-03

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated...

  18. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-03-17

    ... From the Federal Register Online via the Government Publishing Office ] INTERNATIONAL TRADE COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... the sale within the United States after importation of certain large scale integrated...

  19. 77 FR 66481 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-11-05

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice..., and the sale within the United States after importation of certain integrated circuits, chipsets, and... collectively filed a motion to stay the procedural schedule pending the completion of Certain...

  20. 78 FR 16533 - Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-15

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation... importation, or the sale within the United States after importation of certain integrated circuit devices and... sale for importation, and/or the sale within the United States after importation of certain...

  1. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-04

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor integrated circuit devices and products containing same by reason of infringement of certain claims of U.S....

  2. 75 FR 65654 - In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-10-26

    ... COMMISSION In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including... sale for importation, and the sale within the United States after importation of certain integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  3. 75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-13

    ... COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... sale for importation, and the sale within the United States after importation of certain integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  4. Exploitation of parallelism and ultraspeed integrated circuits in the next generation of distributed super signal processors

    SciTech Connect

    Gilbert, B.K.; Naused, B.A.; Hartley, S.M.; Vannurden, W.K.; Deming, R.

    1983-10-01

    The emerging application of gallium arsenide digital integrated circuits to signal processing problems will require the development of architectures tuned to its special characteristics. Chip design methods may be similar to those used for silicon very high-speed integrated circuit (VHSIC) components, but system design constraints will be unique to GAAS. 8 references.

  5. Paper-based silver-nanowire electronic circuits with outstanding electrical conductivity and extreme bending stability

    NASA Astrophysics Data System (ADS)

    Huang, Gui-Wen; Xiao, Hong-Mei; Fu, Shao-Yun

    2014-07-01

    Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated.Here a facile, green and efficient printing-filtration-press (PFP) technique is reported for room-temperature (RT) mass-production of low-cost, environmentally friendly, high performance paper-based electronic circuits. The as-prepared silver nanowires (Ag-NWs) are uniformly deposited at RT on a pre-printed paper substrate to form high quality circuits via vacuum filtration and pressing. The PFP circuit exhibits more excellent electrical property and bending stability compared with other flexible circuits made by existing techniques. Furthermore, practical applications of the PFP circuits are demonstrated. Electronic supplementary information (ESI) available: Video of rolling tests; video of the PFP circuit used as flexible cable in a cell phone; video of the application of the circuit as a RFID tag; a detailed method for synthesizing silver nanowires; details of the PFP technique; folding tests for the circuits; air humidity test for the circuit. See DOI: 10.1039/c4nr00846d

  6. Ion-beam apparatus and method for analyzing and controlling integrated circuits

    DOEpatents

    Campbell, Ann N.; Soden, Jerry M.

    1998-01-01

    An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

  7. Ion-beam apparatus and method for analyzing and controlling integrated circuits

    DOEpatents

    Campbell, A.N.; Soden, J.M.

    1998-12-01

    An ion-beam apparatus and method for analyzing and controlling integrated circuits are disclosed. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal. 4 figs.

  8. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    NASA Technical Reports Server (NTRS)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  9. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Islam, Syed K; Blalock, Benjamin J

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  10. Design structure for in-system redundant array repair in integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  11. SOI-Based High-Voltage, High-Temperature Integrated Circuit Gate Driver for SiC-Based Power FETs

    SciTech Connect

    Huque, Mohammad A; Tolbert, Leon M; Blalock, Benjamin; Islam, Syed K

    2010-01-01

    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimizing system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8-m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  12. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    NASA Astrophysics Data System (ADS)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  13. Towards Evolving Electronic Circuits for Autonomous Space Applications

    NASA Technical Reports Server (NTRS)

    Lohn, Jason D.; Haith, Gary L.; Colombano, Silvano P.; Stassinopoulos, Dimitris

    2000-01-01

    The relatively new field of Evolvable Hardware studies how simulated evolution can reconfigure, adapt, and design hardware structures in an automated manner. Space applications, especially those requiring autonomy, are potential beneficiaries of evolvable hardware. For example, robotic drilling from a mobile platform requires high-bandwidth controller circuits that are difficult to design. In this paper, we present automated design techniques based on evolutionary search that could potentially be used in such applications. First, we present a method of automatically generating analog circuit designs using evolutionary search and a circuit construction language. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm, we present experimental results for five design tasks. Second, we investigate the use of coevolution in automated circuit design. We examine fitness evaluation by comparing the effectiveness of four fitness schedules. The results indicate that solution quality is highest with static and co-evolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.

  14. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

    PubMed Central

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

    2008-01-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  15. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

    PubMed Central

    Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

    2010-01-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

  16. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

    PubMed

    Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

    2009-12-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

  17. Tunable hollow optical waveguides for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Koyama, Fumio

    2004-10-01

    We propose a tunable hollow optical waveguide with a variable air core toward a new class of photonic integrated circuits. We present various unique features in hollow waveguides and the combination with microelectro-mechanical system (MEMS) will gives us widely tunable waveguide devices. We presente the design and fabrication of a tunable hollow waveguide with a variable air core. We describe the full-vectorial modeling of 3D and slab hollow waveguides with a variable air core, which is also supported by experiments. We demonstrated low loss and polarization insensitive waveguiding in an air core with optimized multilayer coating. The result shows a possibility of a large change of ~3% in propagation constant with a variable air core. We will present a wide variety of device applications based on hollow waveguides, which include tunable grating demultiplexers, variable attenuators, optical switches, tunable Bragg reflectors, tunable dispersion compensators and tunable lasers. The device structure can be formed by fully planar fabrication processes based on lithography and etching. The proposed concept may open up a new class of various tunable optical devices, which give us unique features of wide tunability, compact size and temperature insensitivity.

  18. An integrated modelling framework for neural circuits with multiple neuromodulators

    PubMed Central

    Vemana, Vinith

    2017-01-01

    Neuromodulators are endogenous neurochemicals that regulate biophysical and biochemical processes, which control brain function and behaviour, and are often the targets of neuropharmacological drugs. Neuromodulator effects are generally complex partly owing to the involvement of broad innervation, co-release of neuromodulators, complex intra- and extrasynaptic mechanism, existence of multiple receptor subtypes and high interconnectivity within the brain. In this work, we propose an efficient yet sufficiently realistic computational neural modelling framework to study some of these complex behaviours. Specifically, we propose a novel dynamical neural circuit model that integrates the effective neuromodulator-induced currents based on various experimental data (e.g. electrophysiology, neuropharmacology and voltammetry). The model can incorporate multiple interacting brain regions, including neuromodulator sources, simulate efficiently and easily extendable to large-scale brain models, e.g. for neuroimaging purposes. As an example, we model a network of mutually interacting neural populations in the lateral hypothalamus, dorsal raphe nucleus and locus coeruleus, which are major sources of neuromodulator orexin/hypocretin, serotonin and norepinephrine/noradrenaline, respectively, and which play significant roles in regulating many physiological functions. We demonstrate that such a model can provide predictions of systemic drug effects of the popular antidepressants (e.g. reuptake inhibitors), neuromodulator antagonists or their combinations. Finally, we developed user-friendly graphical user interface software for model simulation and visualization for both fundamental sciences and pharmacological studies. PMID:28100828

  19. Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

    PubMed Central

    Roham, Masoud; Halpern, Jeffrey M.; Martin, Heidi B.; Chiel, Hillel J.

    2015-01-01

    An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order ΔΣ modulator (ΔΣM) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 μm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of ~250 fA, ~1.5 pA, ~4.5 pA, and ~17 pA were achieved for input currents in the range of ±5, ±37, ±150, and ±600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 μM wirelessly over a transmission distance of ~0.5 m in flow injection analysis experiments. PMID:18990633

  20. Scheduling revisited workstations in integrated-circuit fabrication

    NASA Technical Reports Server (NTRS)

    Kline, Paul J.

    1992-01-01

    The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

  1. An automatic detection system for flatness of integrated circuit pins

    NASA Astrophysics Data System (ADS)

    Deng, Shichao; Liu, Tiegen; Xiao, Zexin; Li, Xiuyan

    2008-12-01

    The flatness of pins is an important quality indicator for integrated circuit packaging. Almost all of the detection methods which are currently used can't be successful on efficiency and precision. In this system, the image of IC pins was captured by an properly optical systems and corresponding CCD sensor. To detect the edge of each pin, traditional algorithmic, such as Sobel operator and Roberts operator, have some disadvantages: the edge is too thick for system to accurately measure and the edge show directional character. An image segmentation and border extracting algorithm focus on the extreme of neighborhood image intensity change was adopted. The advantage of this algorithm was each pixel's neighborhood image intensity information was considered, so the algorithm is more suitable for accurately measure. After edge was extracted, how to identify the useful spots is cast as a binary classification task. The support vector machine (SVM) would be used to identify pin's spots. After proper image characteristics are obtained and a certain amount of training, SVM provides higher discrimination ratio to distinguish spots of the IC pins. To measure the flatness of pin, a particular line which can be identified easily should be put in the image as a baseline. Through calculating the distance between the pins spot and baseline, the flatness of pins is obtained accurately. In this system, the flatness of IC pins can be accurately and quickly measured, which is worthy of broad application prospect in IC packaging.

  2. Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

    NASA Astrophysics Data System (ADS)

    Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

    2000-03-01

    Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this

  3. Variable Time Base Integrator Circuit for Buffet Signal Measurements

    NASA Technical Reports Server (NTRS)

    Batts, Colossie N.

    1973-01-01

    A measurement circuit to obtain buffet data from wind tunnel models wherein a signal proportional to the average RMS value of buffet data is produced for subsequent recording. Feedback means are employed to suppress the D.C. portion of signals developed by the strain gages during dynamic testing. Automatic recording of gain settings of amplifiers employed in the circuit is also provided.

  4. Circuit elements at optical frequencies: A synthesis of first principles electronic structure and circuit theories

    NASA Astrophysics Data System (ADS)

    Tang, C.; Ramprasad, R.

    2006-03-01

    We present a new first principles based method to determine the equivalent circuit representations of nanostructured physical systems at optical frequencies. This method involves the determination of the frequency dependent effective permittivity of two constructs: an ordered composite system consisting of physical nano-elements using density functional theory, and an ordered arrangement of impedances using transmission line theory. Matching the calculated effective permittivity functions of these two constructs has enabled a mapping of the physical nano-system to its equivalent circuit. Specifically, we will show that silicon nanowires and carbon nanotubes can be represented as a series combination of inductance, capacitance and resistance. Once this mapping has been reasonably accomplished for a variety of physical systems, the nano-elements can be combined suitably to result in equivalent circuit topologies appropriate for optical and nanoelectronic devices, including left-handed (or negative refractive index) materials.

  5. Hot-carrier reliability assessment in CMOS digital integrated circuits

    NASA Astrophysics Data System (ADS)

    Jiang, Wenjie

    As VLSI technologies scale to deep submicron region, the DC device-based hot-carrier criterion is no longer practical for predicting hot-carrier reliability. Understanding the AC hot-carrier degradation of MOSFETs in actual circuit environment and their corresponding impact on circuit performance becomes increasingly important. The purpose of this research is to contribute to the assessment of hot-carrier reliability in digital CMOS circuits. Several critical issues that face circuit- level hot-carrier reliability evaluation are investigated, including AC hot-carrier test circuit design and characterization, AC hot-carrier degradation model calibration, the major factors determining circuit- level hot-carrier reliability, and the trade-offs between circuit-level hot-carrier lifetime underestimation and the amount of information required. In the area of experimental assessment of AC hot-carrier reliability, this thesis provides a comprehensive understanding of the key issues in designing and characterizing hot-carrier reliability test circuits. Test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage are presented. New insights about previous test circuit designs are presented and additional test circuit designs are demonstrated. The design trade-offs between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed. In the area of circuit-level hot-carrier reliability simulation, this thesis examines key issues involved in the calibration and verification of the hot-carrier degradation models that are used for AC hot-carrier reliability simulation. The need to account for the stress oxide-field dependence of the degradation model coefficients is demonstrated. The statistical

  6. Virtual Instrument Systems in Reality (VISIR) for Remote Wiring and Measurement of Electronic Circuits on Breadboard

    ERIC Educational Resources Information Center

    Tawfik, M.; Sancristobal, E.; Martin, S.; Gil, R.; Diaz, G.; Colmenar, A.; Peire, J.; Castro, M.; Nilsson, K.; Zackrisson, J.; Hakansson, L.; Gustavsson, I.

    2013-01-01

    This paper reports on a state-of-the-art remote laboratory project called Virtual Instrument Systems in Reality (VISIR). VISIR allows wiring and measuring of electronic circuits remotely on a virtual workbench that replicates physical circuit breadboards. The wiring mechanism is developed by means of a relay switching matrix connected to a PCI…

  7. CIRCUS--A digital computer program for transient analysis of electronic circuits

    NASA Technical Reports Server (NTRS)

    Moore, W. T.; Steinbert, L. L.

    1968-01-01

    Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

  8. Low-noise low-power readout electronics circuit development in standard CMOS technology for 4 K applications

    NASA Astrophysics Data System (ADS)

    Merken, Patrick; Souverijns, Tim; Putzeys, Jan; Creten, Ybe; Van Hoof, Chris

    2006-06-01

    In the framework of the Photodetector Array Camera and Spectrometer (PACS) project IMEC designed the Cold Readout Electronics (CRE) for the Ge:Ga far-infrared detector array. Key specifications for this circuit were high linearity, low power consumption and low noise at an operating temperature of 4.2K. We have implemented this circuit in a standard CMOS technology which guarantees high yield and uniformity, and design portability. A drawback of this approach is the anomalous behavior of CMOS transistors at temperatures below 30-40K. These cryogenic phenomena disturb the normal functionality of commonly used circuits. We were able to overcome these problems and developed a library of digital and analog building blocks based on the modeling of cryogenic behavior, and on adapted design and layout techniques. We will present the design of the 18 channel CRE circuit, its interface with the Ge:Ga sensor, and its electrical performance. We will show how the library that was developed for PACS served as a baseline for the designs used in the Darwin-far-infrared detector array, where a cryogenic 180 channel, 30μm pitch, Readout Integrated Circuit (ROIC) for flip-chip integration was developed. Other designs and topologies for low noise and low power applications will be equally presented.

  9. Synthetic Plasma Liquid Based Electronic Circuits Realization-A Novel Concept

    PubMed Central

    Pandya, Killol V.; Kosta, ShivPrasad

    2016-01-01

    Biomedical research is contributing significant role in the field of biomedical engineering and applied science. It brings research and innovations to a different level. This study investigated artificial human blood –synthetic plasma liquid as conductive medium. Keeping in mind the conductivity of synthetic plasma, astable multivibrator as well as differential amplifier circuit were demonstrated. The circuits were given normal input voltages at regular temperature and ideal conditions. The result shows desired response which supports the novel concept. For both the circuits, phase shift of 180° achieved by analysing biological electronic circuits. PMID:27829822

  10. From The Lab to The Fab: Transistors to Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.

    2003-09-01

    Transistor action was experimentally observed by John Bardeen and Walter Brattain in n-type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold-plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point-contact semiconductor amplifier, often referred to as the point-contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point-contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. The a priori tuning of the point-contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to "burnout" were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p-n junction (bulk) transistors began replacing the point-contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore's Law in setting the parameters by which the IC industry's growth was monitored will be discussed.

  11. Method for producing a hybridization of detector array and integrated circuit for readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

    1993-01-01

    A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

  12. An Educational Laboratory for Digital Control and Rapid Prototyping of Power Electronic Circuits

    ERIC Educational Resources Information Center

    Choi, Sanghun; Saeedifard, M.

    2012-01-01

    This paper describes a new educational power electronics laboratory that was developed primarily to reinforce experimentally the fundamental concepts presented in a power electronics course. The developed laboratory combines theoretical design, simulation studies, digital control, fabrication, and verification of power-electronic circuits based on…

  13. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    NASA Technical Reports Server (NTRS)

    Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

    2000-01-01

    Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

  14. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    PubMed

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

  15. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    NASA Technical Reports Server (NTRS)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  16. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    ERIC Educational Resources Information Center

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  17. Low-power integrated-circuit driver for ferrite-memory word lines

    NASA Technical Reports Server (NTRS)

    Katz, S.

    1970-01-01

    Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

  18. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

    PubMed Central

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  19. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator.

    PubMed

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex.

  20. Equivalent circuit simulation of cylindrical monopole impedance measurements in ionospheric electron plasma

    NASA Astrophysics Data System (ADS)

    Kiraga, A.

    Several common problems occur in measurement techniques and interpretation of plasma natural emissions and impedance data. Antenna characteristics are of prime importance in equivalent circuit analysis. Spacecraft - plasma interaction contributes to variability of equivalent circuit impedances and e.m.f. components and imposes constrains on usefulness of experimental data. In order to have independent, built in estimate of local plasma frequency and to get deeper insight into properties of equivalent circuit for wave diagnostics, impedance measurement was integrated with radio receivers on the ACTIVE, APEX and CORONAS satellites. Impedance measurements of 7.5m long monopole were performed in frequency range .1-10MHz with the frequency step of 50kHz, in voltage divider configuration. Due to high inclination of 82.5deg and altitude range of 500-3000km, data from very different plasmas were collected. Data can be split into quasi normal, disturbed and very disturbed measurements. Equivalent circuit structure evolved in attempt to m tcha even very disturbed measurements. For quasi normal measurements, satisfactory matching is obtained with computed gyrofrequency fc and fitted plasma frequency fn, stray capacitance Cs and capacitance Cv of phenomenological vacuum sheath. With Balmain formula for monopole impedance in cold magnetoplasma, two basic spectral structures are explained. For sufficiently magnetized plasma (roughly fn/fc<2 if Cs=20pF), circuit parallel resonance frequency Fr falls into upper hybrid band (max(fn,fc),fu), resonance amplitude is reduced by high antenna resistance and horn like absolute maximum points fu. For values of fn/fc ratio, greater then critical, Fr is less than fn and broad absolute maximum at Fr follows from low antenna resistance. Further increase of fn/fc results in increasing lag of Fr behind fn. Critical rati o fn/fc increases with decreasing stray capacitance Cs. It follows from data analysis that stray capacitance may change in

  1. SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

    NASA Astrophysics Data System (ADS)

    Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

    2010-05-01

    A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

  2. 77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-11-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation in its Entirety AGENCY:...

  3. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-09

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation...

  4. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    ERIC Educational Resources Information Center

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  5. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    PubMed

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  6. INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

    PubMed

    Sholom, S; McKeever, S W S

    2016-09-01

    In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident.

  7. Real-time fast physical random number generator with a photonic integrated circuit.

    PubMed

    Ugajin, Kazusa; Terashima, Yuta; Iwakawa, Kento; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki; Inubushi, Masanobu

    2017-03-20

    Random number generators are essential for applications in information security and numerical simulations. Most optical-chaos-based random number generators produce random bit sequences by offline post-processing with large optical components. We demonstrate a real-time hardware implementation of a fast physical random number generator with a photonic integrated circuit and a field programmable gate array (FPGA) electronic board. We generate 1-Tbit random bit sequences and evaluate their statistical randomness using NIST Special Publication 800-22 and TestU01. All of the BigCrush tests in TestU01 are passed using 410-Gbit random bit sequences. A maximum real-time generation rate of 21.1 Gb/s is achieved for random bit sequences in binary format stored in a computer, which can be directly used for applications involving secret keys in cryptography and random seeds in large-scale numerical simulations.

  8. RNA signal amplifier circuit with integrated fluorescence output.

    PubMed

    Akter, Farhima; Yokobayashi, Yohei

    2015-05-15

    We designed an in vitro signal amplification circuit that takes a short RNA input that catalytically activates the Spinach RNA aptamer to produce a fluorescent output. The circuit consists of three RNA strands: an internally blocked Spinach aptamer, a fuel strand, and an input strand (catalyst), as well as the Spinach aptamer ligand 3,5-difluoro-4-hydroxylbenzylidene imidazolinone (DFHBI). The input strand initially displaces the internal inhibitory strand to activate the fluorescent aptamer while exposing a toehold to which the fuel strand can bind to further displace and recycle the input strand. Under a favorable condition, one input strand was able to activate up to five molecules of the internally blocked Spinach aptamer in 185 min at 30 °C. The simple RNA circuit reported here serves as a model for catalytic activation of arbitrary RNA effectors by chemical triggers.

  9. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    NASA Astrophysics Data System (ADS)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  10. Noise analysis for infrared focal plane arrays CMOS readout integrated circuit

    NASA Astrophysics Data System (ADS)

    Lin, Jiamu; Ding, Ruijun; Chen, Honglei; Shen, Xiao; Liu, Fei

    2008-12-01

    With the development of the infrared focal plane detectors, the internal noises in the infrared focal plane arrays (IRFPAs) CMOS readout integrated circuit gradually became an important factor of the development of the IRFPAs. The internal noises in IRFPAs CMOS readout integrated circuit are researched in this work. Part of the motivation for this work is to analyze the mechanism and influence of the internal noises in readout integrated circuit. And according to the signal transporting process, many kinds of internal noises are analyzed. According to the results of theory analysis, it is shown that 1/f noise, KTC noise and pulse switch noise have greater amplitude in frequency domain. These noises have seriously affected the performance of output signal. Also this work has frequency test on the signals of a readout integrated circuit chip which is using DI readout mode. After analyzing the frequency test results, it is shown that 1/f noises and pulse switch noises are the main components of the internal noises in IRFPAS CMOS readout integrated circuit and they are the noises which give a major impact to the output signal. In accordance with the type of noise, some design methods for noise suppression are put forward. And after the simulation of these methods with EDA software, the results show that noises have been reduced. The results of this work gave the referenced gist for improving the noise suppression design of IRFPAs CMOS readout integrated circuit.

  11. Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Burns, J. L.; Choma, J., Jr.

    1982-01-01

    A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.

  12. Integrated-Circuit Controller For Brushless dc Motor

    NASA Technical Reports Server (NTRS)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  13. Unipolar Complementary Circuits Using Double Electron Layer Tunneling Tansistors

    SciTech Connect

    Blount, M.A.; Hafich, M.J.; Moon, J.S.; Reno, J.L.; Simmons, J.A.

    1998-10-19

    We demonstrate unipolar complementary circuits consisting of a pair of resonant tunneling transistors based on the gate control of 2D-2D interlayer tunneling, where a single transistor - in addition to exhibiting a welldefined negative-differential-resistance can be operated with either positive or negative transconductance. Details of the device operation are analyzed in terms of the quantum capacitance effect and band-bending in a double quantum well structure, and show good agreement with experiment. Application of resonant tunneling complementary logic is discussed by demonstrating complementary static random access memory using two devices connected in series.

  14. Electronic circuit model for proton exchange membrane fuel cells

    NASA Astrophysics Data System (ADS)

    Yu, Dachuan; Yuvarajan, S.

    The proton exchange membrane (PEM) fuel cell is being investigated as an alternate power source for various applications like transportation and emergency power supplies. The paper presents a novel circuit model for a PEM fuel cell that can be used to design and analyze fuel cell power systems. The PSPICE-based model uses bipolar junction transistors (BJTs) and LC elements available in the PSPICE library with some modification. The model includes the phenomena like activation polarization, ohmic polarization, and mass transport effect present in a PEM fuel cell. The static and dynamic characteristics obtained through simulation are compared with experimental results obtained on a commercial fuel cell module.

  15. Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

    SciTech Connect

    Kim, D.S.; Seong, P.H. . Dept. of Nuclear Engineering)

    1994-02-01

    This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times.

  16. Process development of beam-lead silicon-gate COS/MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Baptiste, B.; Boesenberg, W.

    1974-01-01

    Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

  17. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  18. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    SciTech Connect

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  19. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  20. Development of plasmonic isolator for integration into photonic integrated circuits (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Zayets, Vadym; Saito, Hidekazu; Ando, Koji; Yuasa, Shinji

    2015-09-01

    An optical isolator is an important component of an optical network. At present, there is a significant commercial demand for an optical isolator, which can be integrated into the Photonic Integrated Circuits (PIC). A new design of an integrated optical isolator, which utilizes unique non-reciprocal properties of surface plasmons, has been proposed [1]. The main obstacle for a practical realization of the proposed design is a substantial propagation loss of the surface plasmons in structures containing a ferromagnetic metal. The reduction of the propagation loss of a surface plasmon is the key to make the plasmonic isolator competitive with other designs of the integrated isolator. We studied experimentally optical and magneto-optical properties of a Fe plasmonic waveguide integrated with an AlGaAs rib waveguides and a Co plasmonic waveguide integrated with Si nanowire waveguides. It was demonstrated experimentally that by utilizing a double-dielectric plasmonic waveguide it is possible to reduce significantly the optical loss in a plasmonic waveguide. For Fe/SiO2/AlGaAs double-dielectric plasmonic waveguide the low optical loss of 0.03 dB/um is obtained. As far as we know at present it is a lowest optical loss demonstrated for a plasmon propagating at a surface of a ferromagnetic metal. For Co/Ti2O3/SiO2 double-dielectric plasmonic waveguide integrated with a Si nanowire waveguide on a Si substrate the optical loss of 0.7 dB/um was demonstrated. The designs of the plasmonic isolator utilizing a ring resonator or a non-reciprocal coupler were studied. [1] V. Zayets, H. Saito, S. Yuasa, and K. Ando,, Materials 5, 857 (2012).

  1. The stabilized supralinear network: a unifying circuit motif underlying multi-input integration in sensory cortex.

    PubMed

    Rubin, Daniel B; Van Hooser, Stephen D; Miller, Kenneth D

    2015-01-21

    Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression--modulatory contextual stimuli suppress responses to driving stimuli; and (2) "normalization"--responses to multiple driving stimuli add sublinearly. These depend on input strength: for weak driving stimuli, contextual influences facilitate or more weakly suppress and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties, including the above, emerge robustly from four cortical circuit properties: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; and (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions.

  2. Conductance and activation energy for electron transport in series and parallel intramolecular circuits.

    PubMed

    Hsu, Liang-Yan; Wu, Ning; Rabitz, Herschel

    2016-11-30

    We investigate electron transport through series and parallel intramolecular circuits in the framework of the multi-level Redfield theory. Based on the assumption of weak monomer-bath couplings, the simulations depict the length and temperature dependence in six types of intramolecular circuits. In the tunneling regime, we find that the intramolecular circuit rule is only valid in the weak monomer coupling limit. In the thermally activated hopping regime, for circuits based on two different molecular units Ma and Mb with distinct activation energies Eact,a > Eact,b, the activation energies of Ma and Mb in series are nearly the same as Eact,a while those in parallel are nearly the same as Eact,b. This study gives a comprehensive description of electron transport through intramolecular circuits from tunneling to thermally activated hopping. We hope that this work can motivate additional studies to design intramolecular circuits based on different types of building blocks, and to explore the corresponding circuit laws and the length and temperature dependence of conductance.

  3. Buffer direct injection readout integrated circuit design for dual band infrared focal plane array detector

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Tang, Shiang-Feng; Lin, Wen-Jen

    2013-05-01

    This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 μm. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

  4. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

    NASA Astrophysics Data System (ADS)

    Neudeck, Philip G.; Meredith, Roger D.; Chen, Liangyu; Spry, David J.; Nakley, Leah M.; Hunter, Gary W.

    2016-12-01

    The prolonged operation of semiconductor integrated circuits (ICs) needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ˜ 460 °C, ˜ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks) electrical operation of two silicon carbide (4H-SiC) junction field effect transistor (JFET) ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus' surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

  5. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits

    DTIC Science & Technology

    1993-10-24

    circuit design software Touchstone and later adjusted using the electromagnetic analysis software emTm, from Sonnet . rhe analyzed performance is shown in...Design and Sonnet analysis of the tandem coupler performance. !5 previously reported in our interim report covering the period between July 1991 and...explained in our last quarterly report. A design procedure is being developed in which Sonnet is included in the design loop. Although the procedure is not

  6. High-resolution non-destructive three-dimensional imaging of integrated circuits.

    PubMed

    Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H R; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

    2017-03-15

    Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography-a high-resolution coherent diffractive imaging technique-can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

  7. High-resolution non-destructive three-dimensional imaging of integrated circuits

    NASA Astrophysics Data System (ADS)

    Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H. R.; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

    2017-03-01

    Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

  8. Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

    NASA Astrophysics Data System (ADS)

    Levy, James E.; Carroll, Malcolm S.; Ganti, Anand; Phillips, Cynthia A.; Landahl, Andrew J.; Gurrieri, Thomas M.; Carr, Robert D.; Stalford, Harold L.; Nielsen, Erik

    2011-08-01

    In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuit's error rate (by a factor of ~3-4 in our specific analysis). We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon-Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g. extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.

  9. Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

    PubMed

    Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

    2013-08-21

    For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge

  10. Evolutionary Technique for Automated Synthesis of Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

    2003-01-01

    A method for evolving a circuit comprising configuring a plurality of transistors using a plurality of reconfigurable switches so that each of the plurality of transistors has a terminal coupled to a terminal of another of the plurality of transistors that is controllable by a single reconfigurable switch. The plurality of reconfigurable switches being controlled in response to a chromosome pattern. The plurality of reconfigurable switches may be controlled using an annealing function. As such, the plurality of reconfigurable switches may be controlled by selecting qualitative values for the plurality of reconfigurable switches in response to the chromosomal pattern, selecting initial quantitative values for the selected qualitative values, and morphing the initial quantitative values. Typically, subsequent quantitative values will be selected more divergent than the initial quantitative values. The morphing process may continue to partially or to completely polarize the quantitative values.

  11. In vivo silicon-based flexible radio frequency integrated circuits monolithically encapsulated with biocompatible liquid crystal polymers.

    PubMed

    Hwang, Geon-Tae; Im, Donggu; Lee, Sung Eun; Lee, Jooseok; Koo, Min; Park, So Young; Kim, Seungjun; Yang, Kyounghoon; Kim, Sung June; Lee, Kwyro; Lee, Keon Jae

    2013-05-28

    Biointegrated electronics have been investigated for various healthcare applications which can introduce biomedical systems into the human body. Silicon-based semiconductors perform significant roles of nerve stimulation, signal analysis, and wireless communication in implantable electronics. However, the current large-scale integration (LSI) chips have limitations in in vivo devices due to their rigid and bulky properties. This paper describes in vivo ultrathin silicon-based liquid crystal polymer (LCP) monolithically encapsulated flexible radio frequency integrated circuits (RFICs) for medical wireless communication. The mechanical stability of the LCP encapsulation is supported by finite element analysis simulation. In vivo electrical reliability and bioaffinity of the LCP monoencapsulated RFIC devices are confirmed in rats. In vitro accelerated soak tests are performed with Arrhenius method to estimate the lifetime of LCP monoencapsulated RFICs in a live body. The work could provide an approach to flexible LSI in biointegrated electronics such as an artificial retina and wireless body sensor networks.

  12. Basic Study on the Radio Frequency Characteristics of the Transmission Lines Employing Periodically Perforated Ground Metal on GaAs Monolithic Microwave Integrated Circuit and Their Equivalent Ciruits

    NASA Astrophysics Data System (ADS)

    Yun, Young; Ju, Jeong-Gab; Kim, Hong Seung

    2011-01-01

    In this work, basic characteristics of transmission line employing periodically perforated ground metal (PPGM) were investigated using theoretical and experimental analysis. Concretely, bandwidth and impedance were investigated using theoretical analysis, and wavelength and effective permittivity were extracted from experimental results. In addition, insertion loss and isolation characteristics were investigated using equivalent circuit analysis. For simplification of design process, equivalent circuits for the PPGM cell were extracted, and all circuit parameters were expressed by closed-form equation. Above results indicate that the transmission line employing PPGM is a promising candidate for a development of matching and passive elements on monolithic microwave integrated circuit (MMIC) including wireless communication circuit and compound semiconducting devices such as high electron mobility transistor (HEMT), diamond field effect transistor (FET) and light emitting diode (LED).

  13. Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

    NASA Technical Reports Server (NTRS)

    Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

    1981-01-01

    Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

  14. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  15. Hidden hyperchaos and electronic circuit application in a 5D self-exciting homopolar disc dynamo

    NASA Astrophysics Data System (ADS)

    Wei, Zhouchao; Moroz, Irene; Sprott, J. C.; Akgul, Akif; Zhang, Wei

    2017-03-01

    We report on the finding of hidden hyperchaos in a 5D extension to a known 3D self-exciting homopolar disc dynamo. The hidden hyperchaos is identified through three positive Lyapunov exponents under the condition that the proposed model has just two stable equilibrium states in certain regions of parameter space. The new 5D hyperchaotic self-exciting homopolar disc dynamo has multiple attractors including point attractors, limit cycles, quasi-periodic dynamics, hidden chaos or hyperchaos, as well as coexisting attractors. We use numerical integrations to create the phase plane trajectories, produce bifurcation diagram, and compute Lyapunov exponents to verify the hidden attractors. Because no unstable equilibria exist in two parameter regions, the system has a multistability and six kinds of complex dynamic behaviors. To the best of our knowledge, this feature has not been previously reported in any other high-dimensional system. Moreover, the 5D hyperchaotic system has been simulated using a specially designed electronic circuit and viewed on an oscilloscope, thereby confirming the results of the numerical integrations. Both Matlab and the oscilloscope outputs produce similar phase portraits. Such implementations in real time represent a new type of hidden attractor with important consequences for engineering applications.

  16. Ultrafast electron transport across nano gaps in nanowire circuits

    SciTech Connect

    Potma, Eric O.

    2015-07-31

    In this Program we aim for a closer look at electron transfer through single molecules. To achieve this, we use ultrafast laser pulses to time stamp an electron tunneling event in a molecule that is connected between two metallic electrodes, while reading out the electron current. A key aspect of this project is the use of metallic substrates with plasmonic activity to efficiently manipulate the tunneling probability. The first Phase of this program is concerned with developing highly sensitive tools for the ultrafast optical manipulation of tethered molecules through the evanescent surface field of plasmonic substrates. The second Phase of the program aims to use these tools for exercising control over the electron tunneling probability.

  17. Integrated Defensive Electronic Countermeasures (IDECM)

    DTIC Science & Technology

    2013-12-01

    request support from the Fleet Support Team ( FST ) and/or Original Equipment Manufacturer (OEM). Depot Level activities will include: removal and...for the F/A-18 Interactive Electronic Technical Manual. The FST at Jacksonville presently manages the MaPls for the ALQ-214(V)2/3 and ALE-55(V...request support from the Fleet Support Team ( FST ) and/or Original Equipment Manfacturer (OEM). Depot Level activities will include: removal and

  18. Guided Wave Interactions in Millimeter-Wave Integrated Circuits.

    DTIC Science & Technology

    1988-01-15

    on a sustrate which is in turn inserted into a TEI{) waveguide along its E-plane. One end of the stub is connected to the top or bottom wall of the... waveguide whereas another end does not reach the opposite wall. This element can be used as a transition from a waveguide to a printed circuit and as a...touching E-plane fin is located in the waveguide below cutoff. With this configuration, an evanescent mode filter can be formed. The evanescent

  19. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    PubMed

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-02

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  20. External electro-optic probing of millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

    1989-01-01

    An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

  1. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1980-01-01

    The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

  2. A circuit method to integrate metamaterial and graphene in absorber design

    NASA Astrophysics Data System (ADS)

    Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

    2014-10-01

    We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

  3. The single-event effect evaluation technology for nano integrated circuits

    NASA Astrophysics Data System (ADS)

    Hongchao, Zheng; Yuanfu, Zhao; Suge, Yue; Long, Fan; Shougang, Du; Maoxin, Chen; Chunqing, Yu

    2015-11-01

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally.

  4. PECASE: All-Optical Photonic Integrated Circuits in Silicon

    DTIC Science & Technology

    2011-01-14

    elements for dense integrated photonics . Figure 33 The cross sections of the simulated electric energy distributions of (a) the 1st and (b) the 2nd...Soltani, and A. Adibi, “High Quality Planar Silicon Nitride Microdisk Resonators for Integrated Photonics in the Visible Wavelength Range,” Optics...Soltani, and A. Adibi, “High quality planar silicon nitride microdisk resonators for integrated photonics in the visible wavelength range,” Opt. Express

  5. Electronics box having internal circuit cards interconnected to external connectors sans motherboard

    NASA Technical Reports Server (NTRS)

    Hockett, John E. (Inventor)

    2005-01-01

    An electronics chassis box includes a pair of opposing sidewalls, a pair of opposing end walls, a bottom surface, a top cover, and ring connectors assemblies mounted in selective ones of the walls of the electronic box. Boss members extend from the bottom surface at different heights upon which circuit cards are mounted in spatial relationship to each other. A flex interconnect substantially reduces and generally eliminates the need of a motherboard by interconnecting the circuit cards to one another and to external connectors mounted within the ring connector assemblies.

  6. Closed Cycle Cryocooler for Low Temperature Electronics Circuits: Cold End Test.

    DTIC Science & Technology

    1983-08-01

    more isolated from the electrical load. -l A Stirling cryocooler is sensitive to the total amount of void volume associ- ated with the working gas...ID-Ai34 043 CLOSED CYCLE CRYOCOOLER FOR LOU TEMPERATURE ELECTRONICS i/i CIRCUITS: COLD END TEST(U) CT1-CRYOGENICS WALTHAM MA F N PIRTLE AUG 83...CRYOGENICS CLOSED CYCLE CRYOCOOLER FOR LOW TEMPERATURE ELECTRONICS CIRCUITS COLD END TEST CONTRACT N00014-82-C-0326 ’Ilk LAJ FELI d1XV10.601 nd cam u wt

  7. Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)

    NASA Astrophysics Data System (ADS)

    Ceylan, Omer; Shafique, Atia; Burak, Abdurrahman; Caliskan, Can; Yazici, Melik; Abbasi, Shahbaz; Galioglu, Arman; Kayahan, Huseyin; Gurbuz, Yasar

    2016-11-01

    This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8 Me- while achieving quantization noise of 198 e- and power consumption of 14.35 mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90 × 8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51 dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays.

  8. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    PubMed

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  9. Electron energy modulation with laser light using a small gap circuit a theoretical consideration

    NASA Astrophysics Data System (ADS)

    Bae, Jongsuck; Okuyama, Sumio; Akizuki, Taiji; Mizuno, Koji

    1993-07-01

    A free electron laser (FEL) using a klystron type interaction circuit is investigated. A metal slit has been considered as the circuit. From theoretical considerations on electron transition rates in a metal film gap and a dielectric (SiO 2) film, it is found that in the metal slit a transition rate above 10 -3/s could be obtained for an incident laser power density of 10 6 W/cm 2. The optimum slit dimensions have been determined for a laser wavelength of 780 nm and an initial electron energy of 80 keV. A rough estimation implies that a laser power of 30 mW will produce a signal output of 20 000 electrons/s for an electron beam density of 1 mA/cm 2 at the laser wavelength of 780 nm.

  10. Integrated low power digital gyro control electronics

    NASA Technical Reports Server (NTRS)

    M'Closkey, Robert (Inventor); Challoner, A. Dorian (Inventor); Grayver, Eugene (Inventor); Hayworth, Ken J. (Inventor)

    2005-01-01

    Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

  11. Differential transimpedance amplifier circuit for correlated differential amplification

    DOEpatents

    Gresham, Christopher A.; Denton, M. Bonner; Sperline, Roger P.

    2008-07-22

    A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

  12. DCal: A custom integrated circuit for calorimetry at the International Linear Collider

    SciTech Connect

    Hoff, James R.; Mekkaoui, Abderrazek; Yarema, Ray; Drake, Gary; Repond, Jose; /Argonne

    2005-10-01

    A research and development collaboration has been started with the goal of producing a prototype hadron calorimeter section for the purpose of proving the Particle Flow Algorithm concept for the International Linear Collider. Given the unique requirements of a Particle Flow Algorithm calorimeter, custom readout electronics must be developed to service these detectors. This paper introduces the DCal or Digital Calorimetry Chip, a custom integrated circuit developed in a 0.25um CMOS process specifically for this International Linear Collider project. The DCal is capable of handling 64 channels, producing a 1-bit Digital-to-Analog conversion of the input (i.e. hit/no hit). It maintains a 24-bit timestamp and is capable of operating either in an externally triggered mode or in a self-triggered mode. Moreover, it is capable of operating either with or without a pipeline delay. Finally, in order to permit the testing of different calorimeter technologies, its analog front end is capable of servicing Particle Flow Algorithm calorimeters made from either Resistive Plate Chambers or Gaseous Electron Multipliers.

  13. Integrated digital printing of flexible circuits for wireless sensing (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Ng, Tse Nga; Krusor, Brent S.; Ready, Steve E.; Daniel, George; Veres, Janos; Street, Bob

    2016-09-01

    Wireless sensing has broad applications in a wide variety of fields such as infrastructure monitoring, chemistry, environmental engineering and cold supply chain management. Further development of sensing systems will focus on achieving light weight, flexibility, low power consumption and low cost. Fully printed electronics provide excellent flexibility and customizability, as well as the potential for low cost and large area applications, but lack solutions for high-density, high-performance circuitry. Conventional electronics mounted on flexible printed circuit boards provide high performance but are not digitally fabricated or readily customizable. Incorporation of small silicon dies or packaged chips into a printed platform enables high performance without compromising flexibility or cost. At PARC, we combine high functionality c-Si CMOS and digitally printed components and interconnects to create an integrated platform that can read and process multiple discrete sensors. Our approach facilitates customization to a wide variety of sensors and user interfaces suitable for a broad range of applications including remote monitoring of health, structures and environment. This talk will describe several examples of printed wireless sensing systems. The technologies required for these sensor systems are a mix of novel sensors, printing processes, conventional microchips, flexible substrates and energy harvesting power solutions.

  14. Direct profiling of cancer biomarkers in tumor tissue using a multiplexed nanostructured microelectrode integrated circuit.

    PubMed

    Fang, Zhichao; Soleymani, Leyla; Pampalakis, Georgios; Yoshimoto, Maisa; Squire, Jeremy A; Sargent, Edward H; Kelley, Shana O

    2009-10-27

    The analysis of panels of nucleic acid biomarkers offers valuable diagnostic and prognostic information for cancer management. A cost-effective, highly sensitive electronic chip would offer an ideal platform for clinical biomarker readout and would have maximal utility if it was (i) multiplexed, enabling on-chip assays of multiple biomarkers, and (ii) able to perform direct (PCR-free) readout of disease-related genes. Here we report a chip onto which we integrate novel nanostructured microelectrodes and with which we directly detect cancer biomarkers in heterogeneous biological samples-both cell extracts and tumor tissues. Coarse photolithographic microfabrication defines a multiplexed sensing array; bottom-up fabrication of nanostructured microelectrodes then provides sensing elements. We analyzed a panel of mRNA samples for prostate cancer related gene fusions using the chip. We accurately identified gene fusions that correlate with aggressive prostate cancer and distinguished these from fusions associated with slower-progressing forms of the disease. The multiplexed nanostructured microelectrode integrated circuit reported herein provides direct, amplification-free, sample-to-answer in under 1 h using the 10 ng of mRNA readily available in biopsy samples.

  15. Three-dimensional integrated circuits for lab-on-chip dielectrophoresis of nanometer scale particles

    NASA Astrophysics Data System (ADS)

    Dickerson, Samuel J.; Noyola, Arnaldo J.; Levitan, Steven P.; Chiarulli, Donald M.

    2007-01-01

    In this paper, we present a mixed-technology micro-system for electronically manipulating and optically detecting virusscale particles in fluids that is designed using 3D integrated circuit technology. During the 3D fabrication process, the top-most chip tier is assembled upside down and the substrate material is removed. This places the polysilicon layer, which is used to create geometries with the process' minimum feature size, in close proximity to a fluid channel etched into the top of the stack. By taking advantage of these processing features inherent to "3D chip-stacking" technology, we create electrode arrays that have a gap spacing of 270 nm. Using 3D CMOS technology also provides the ability to densely integrate analog and digital control circuitry for the electrodes by using the additional levels of the chip stack. We show simulations of the system with a physical model of a Kaposi's sarcoma-associated herpes virus, which has a radius of approximately 125 nm, being dielectrophoretically arranged into striped patterns. We also discuss how these striped patterns of trapped nanometer scale particles create an effective diffraction grating which can then be sensed with macro-scale optical techniques.

  16. E-learning platform for automated testing of electronic circuits using signature analysis method

    NASA Astrophysics Data System (ADS)

    Gherghina, Cǎtǎlina; Bacivarov, Angelica; Bacivarov, Ioan C.; Petricǎ, Gabriel

    2016-12-01

    Dependability of electronic circuits can be ensured only through testing of circuit modules. This is done by generating test vectors and their application to the circuit. Testability should be viewed as a concerted effort to ensure maximum efficiency throughout the product life cycle, from conception and design stage, through production to repairs during products operating. In this paper, is presented the platform developed by authors for training for testability in electronics, in general and in using signature analysis method, in particular. The platform allows highlighting the two approaches in the field namely analog and digital signature of circuits. As a part of this e-learning platform, it has been developed a database for signatures of different electronic components meant to put into the spotlight different techniques implying fault detection, and from this there were also self-repairing techniques of the systems with this kind of components. An approach for realizing self-testing circuits based on MATLAB environment and using signature analysis method is proposed. This paper analyses the benefits of signature analysis method and simulates signature analyzer performance based on the use of pseudo-random sequences, too.

  17. Monolithical integration of polymer-based microfluidic structures on application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Chemnitz, Steffen; Schafer, Heiko; Schumacher, Stephanie; Koziy, Volodymyr; Fischer, Alexander; Meixner, Alfred J.; Ehrhardt, Dietmar; Bohm, Markus

    2003-04-01

    In this paper, a concept for a monolithically integrated chemical lab on microchip is presented. It contains an ASIC (Application Specific Integrated Circuit), an interface to the polymer based microfluidic layer and a Pyrex glass cap. The top metal layer of the ASIC is etched off and replaced by a double layer metallization, more suitable to microfluidic and electrophoresis systems. The metallization consists of an approximately 50 nm gold layer and a 10 nm chromium layer, acting as adhesion promoter. A necessary prerequisite is a planarized ASIC topography. SU-8 is used to serve as microfluidic structure because of its excellent aspect ratio. This polymer layer contains reservoirs, channels, mixers and electrokinetic micro pumps. The typical channel cross section is 10μm"10μm. First experimental results on a microfluidic pump, consisting of pairs of interdigitated electrodes on the bottom of the channel and without any moving parts show a flow of up to 50μm per second for low AC-voltages in the range of 5 V for aqueous fluids. The microfluidic system is irreversibly sealed with a 150μm thick Pyrex glass plate bonded to the SU-8-layer, supported by oxygen plasma. Due to capillary forces and surfaces properties of the walls the system is self-priming. The technologies for the fabrication of the microfluidic system and the preparation of the interface between the lab layer and the ASIC are presented.

  18. Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

    PubMed

    Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

    2015-06-01

    Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

  19. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  20. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  1. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-08

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  2. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-29

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  3. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2007-12-18

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  4. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    NASA Astrophysics Data System (ADS)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  5. Integrated silicon and silicon nitride photonic circuits on flexible substrates.

    PubMed

    Chen, Yu; Li, Mo

    2014-06-15

    Flexible integrated photonic devices based on crystalline materials on plastic substrates have a promising potential in many unconventional applications. In this Letter, we demonstrate a fully integrated photonic system including ring resonators and grating couplers, based on both crystalline silicon and silicon nitride, on flexible plastic substrate by using the stamping-transfer method. A high yield has been achieved by a simple, yet reliable transfer method without significant performance degradation.

  6. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

    1995-11-07

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

  7. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

    1995-01-01

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

  8. Compact beam splitters with deep gratings for miniature photonic integrated circuits: design and implementation aspects.

    PubMed

    Chen, Chin-Hui; Klamkin, Jonathan; Nicholes, Steven C; Johansson, Leif A; Bowers, John E; Coldren, Larry A

    2009-09-01

    We present an extensive study of an ultracompact grating-based beam splitter suitable for photonic integrated circuits (PICs) that have stringent density requirements. The 10 microm long beam splitter exhibits equal splitting, low insertion loss, and also provides a high extinction ratio in an integrated coherent balanced receiver. We further present the design strategies for avoiding mode distortion in the beam splitter and discuss optimization of the widths of the detectors to improve insertion loss and extinction ratio of the coherent receiver circuit. In our study, we show that the grating-based beam splitter is a competitive technology having low fabrication complexity for ultracompact PICs.

  9. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  10. Using Laboratory Experiments and Circuit Simulation IT Tools in an Undergraduate Course in Analog Electronics

    NASA Astrophysics Data System (ADS)

    Baltzis, Konstantinos B.; Koukias, Konstantinos D.

    2009-12-01

    Laboratory-based courses play a significant role in engineering education. Given the role of electronics in engineering and technology, laboratory experiments and circuit simulation IT tools are used in their teaching in several academic institutions. This paper discusses the characteristics and benefits of both methods. The content and structure of an introductory laboratory course in analog electronics is described. The aim of the course is the better understanding of the basic principles of analog electronic circuits without the need of specific technical and computer skills. The impact of the proposed method on the learning process is investigated. The evaluation of our proposal was based on both quantitative and qualitative data. Interesting conclusions about the teaching of electronics in undergraduate education are finally drawn.

  11. An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

    1991-01-01

    Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

  12. Automatic layout of integrated-optic time-of-flight circuits

    NASA Astrophysics Data System (ADS)

    Fogg, Ruth D.

    1996-11-01

    This work describes the architecture and algorithms used in the computer-aided design tool developed for the automatic layout of integrated-optic, time-of-flight circuit designs. As in VLSI circuit layout, total wire length and chip area minimization are the goals in the layout of time-of-flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time-of-flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. SEcondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. Assuming the continued development of corner turning mirrors allows the use of a parallel, row-based device placement architecture and a rectangular, fixed-grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time-of-flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.

  13. Using Laboratory Experiments and Circuit Simulation IT Tools in an Undergraduate Course in Analog Electronics

    ERIC Educational Resources Information Center

    Baltzis, Konstantinos B.; Koukias, Konstantinos D.

    2009-01-01

    Laboratory-based courses play a significant role in engineering education. Given the role of electronics in engineering and technology, laboratory experiments and circuit simulation IT tools are used in their teaching in several academic institutions. This paper discusses the characteristics and benefits of both methods. The content and structure…

  14. Method For Making Electronic Circuits Having Nial And Ni3al Substrates

    DOEpatents

    Deevi, Seetharama C.; Sikka, Vinod K.

    2001-01-30

    A method for making electronic circuit component having improved mechanical properties and thermal conductivity comprises steps of providing NiAl and/or Ni.sub.3 Al, and forming an alumina layer thereupon prior to applying the conductive elements. Additional layers of copper-aluminum alloy or copper further improve mechanical strength and thermal conductivity.

  15. Electronic circuits having NiAl and Ni.sub.3 Al substrates

    DOEpatents

    Deevi, Seetharama C.; Sikka, Vinod K.

    1999-01-01

    An electronic circuit component having improved mechanical properties and thermal conductivity comprises NiAl and/or Ni.sub.3 Al, upon which an alumina layer is formed prior to applying the conductive elements. Additional layers of copper-aluminum alloy or copper further improve mechanical strength and thermal conductivity.

  16. Closed Cycle Cryocooler for Low Temperature Electronic Circuits. Phase I. Concept Study

    DTIC Science & Technology

    1980-11-01

    4 III. METHOD OF" APPROACH, MODELING TECHNIQUE .. .. .... .......... ... 6 Modeling of Stirling Cycle...results of the Phase I study to develop concepts for closed cycle cryocoolers for low temperature electronic circuits. Technical contributions to the...conceptual study of small, low power, very low magnetic signature, lightweight, efficient closed cycle, cryocoolers suitable for use with superconductive and

  17. AIN-Coated Al(2)O(3) Substrates For Electronic Circuits

    NASA Technical Reports Server (NTRS)

    Kolawa, Elzbieta; Lowry, Lynn; Herman, Martin; Lee, Karen

    1996-01-01

    Type of improved ceramic substrate for high-frequency, high-power electronic circuits combines relatively high thermal conductivity of aluminum nitride with surface smoothness of alumina. Consists of 15-micrometer layer of AIN deposited on highly polished alumina. Used for packaging millimeter-wave gallium arsenide transmitter chips, power silicon chips, and like.

  18. Use of picosecond optical pulses and FET's integrated with printed circuit antennas to generate millimeter wave radiation

    NASA Astrophysics Data System (ADS)

    Ni, D. C.; Plant, D. V.; Fetterman, H. R.; Matloubian, M.

    1991-03-01

    Millimeter-wave radiation has been generated from FETs and high electron mobility transistors (HEMTs), integrated with printed circuit antennas and illuminated with picosecond optical pulses. Modulation of the millimeter waves was achieved by applying a swept RF signal to the transistor gate. Using this technique, tunable electrical sidebands were added to the optically generated carrier providing a method of transmitting information. The technique also provides increased resolution for use in spectroscopic applications. Heterodyne detection demonstrated that the system continuously generated tunable radiation, constrained by the high-gain antenna, from 45 to 75 GHz.

  19. Detection of orbital angular momentum using a photonic integrated circuit.

    PubMed

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-20

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  20. Detection of orbital angular momentum using a photonic integrated circuit

    PubMed Central

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916