Optical pulse generation in a transistor laser via intra-cavity photon-assisted tunneling and excess base carrier redistribution

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, M.; Iverson, E. W.; Wang, C. Y.

2015-11-02

For a direct-gap semiconductor (e.g., a p-n junction), photon-assisted tunneling is known to exhibit a high nonlinear absorption. In a transistor laser, as discussed here, the coherent photons generated at the quantum well interact with the collector junction field and “assist” electron tunneling from base to collector, thus resulting in the nonlinear modulation of the laser and the realization of optical pulse generation. 1 and 2 GHz optical pulses are demonstrated in the transistor laser using collector voltage control.

Modeling of charge transport in ion bipolar junction transistors.

PubMed

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Radiation-stimulated processes in transistor temperature sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pavlyk, B. V.; Grypa, A. S.

2016-05-15

The features of the radiation-stimulated changes in the I–V and C–V characteristics of the emitter–base junction in KT3117 transistors are considered. It is shown that an increase in the current through the emitter junction is observed at the initial stage of irradiation (at doses of D < 4000 Gy for the “passive” irradiation mode and D < 5200 Gy for the “active” mode), which is caused by the effect of radiation-stimulated ordering of the defect-containing structure of the p–n junction. It is also shown that the X-ray irradiation (D < 14000 Gy), the subsequent relaxation (96 h), and thermal annealingmore » (2 h at 400 K) of the transistor temperature sensors under investigation result in an increase in their radiation resistance.« less

Current-Induced Transistor Sensorics with Electrogenic Cells

PubMed Central

Fromherz, Peter

2016-01-01

The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned. PMID:27120627

Development of a measurement technique for qualitative analysis of MOS transistors using Kuhn's method for MOS varactors

NASA Astrophysics Data System (ADS)

Krautschneider, W.

The semiconductor junction region up to the oxidized surface layer is studied. The object of study is a MOS capacitor, but it is shown that the obtained values of the surface characteristics apply to more complicated MOS transistors. The metal oxide-silicon system is discussed in terms of an ideal varactor, the actual MOS structure, and the MOS system with p-n junction. The determination of the phase interface state density in MOS varactors and MOS transistors is addressed, as the quasistatic C(V) experiment of Kuhn (1970) is theoretically and experimentally extended from MOS varactors to MOS transistors. The surface recombination speed is treated, and the experimental results are compared with theoretical predictions.

Low-noise current amplifier based on mesoscopic Josephson junction.

PubMed

Delahaye, J; Hassel, J; Lindell, R; Sillanpää, M; Paalanen, M; Seppä, H; Hakonen, P

2003-02-14

We used the band structure of a mesoscopic Josephson junction to construct low-noise amplifiers. By taking advantage of the quantum dynamics of a Josephson junction, i.e., the interplay of interlevel transitions and the Coulomb blockade of Cooper pairs, we created transistor-like devices, Bloch oscillating transistors, with considerable current gain and high-input impedance. In these transistors, the correlated supercurrent of Cooper pairs is controlled by a small base current made up of single electrons. Our devices reached current and power gains on the order of 30 and 5, respectively. The noise temperature was estimated to be around 1 kelvin, but noise temperatures of less than 0.1 kelvin can be realistically achieved. These devices provide quantum-electronic building blocks that will be useful at low temperatures in low-noise circuit applications with an intermediate impedance level.

All-optical transistors and logic gates using a parity-time-symmetric Y-junction: Design and simulation

NASA Astrophysics Data System (ADS)

Ding, Shulin; Wang, Guo Ping

2015-09-01

Classical nonlinear or quantum all-optical transistors are dependent on the value of input signal intensity or need extra co-propagating beams. In this paper, we present a kind of all-optical transistors constructed with parity-time (PT)-symmetric Y-junctions, which perform independently on the value of signal intensity in an unsaturated gain case and can also work after introducing saturated gain. Further, we show that control signal can switch the device from amplification of peaks in time to transformation of peaks to amplified troughs. By using these PT-symmetric Y-junctions with currently available materials and technologies, we can implement interesting logic functions such as NOT and XOR (exclusive OR) gates, implying potential applications of such structures in designing optical logic gates, optical switches, and signal transformations or amplifications.

Superconducting current injection transistor with very high critical-current-density edge-junctions

NASA Astrophysics Data System (ADS)

van Zeghbroeck, B. J.

1985-03-01

A Superconducting Current Injection Transistor (Super-CIT) was fabricated with very high critical current-density edge-junctions. The junctions have a niobium base electrode and a lead-alloy counter electrode. The length of the junctions is 30 microns and the critical-current density is 190KA/sq cm. The Super-CIT has a current gain of 2, a large signal transresistance of 100 mV/A, and the turn-on delay, inferred from the junction resonance, is 7ps. The power dissipation is 3.5 microwatts and the power-delay product is 24.5aJ. Gap reduction due to heating was observed, limiting the maximum power dissipation per unit length to 1.1 microwatt/micron. Compared to lead-alloy Super-CITs, the device is five times smaller, three times faster, and has a three times larger output voltage. The damping resistor and the contact junction could also be eliminated.

Antenna-Coupled Superconducting Tunnel Junctions with Single-Electron Transistor Readout for Detection of Sub-mm Radiation

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Wollack, E. J.; Schoelkopf, R. J.; Teufel, J.; Krebs, Carolyn (Technical Monitor)

2002-01-01

Antenna-coupled superconducting tunnel junction detectors have the potential for photon-counting sensitivity at sub-mm wavelengths. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Performance comparison between p–i–n and p–n junction tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-06-01

In this study, we investigated the direct-current (DC) and radio-frequency (RF) performances of p–i–n and p–n junction tunneling field-effect transistors (TFETs). Compared to the p–i–n junction TFET, the p–n junction TFET exhibited higher on-state current (I on) because the channel formation mechanism of the p–n junction TFET resulted in a narrower tunneling barrier and an expanded tunneling area. Further, the reduction of I on of the p–n junction TFET by the interface trap was smaller. Moreover, the p–n junction TFET exhibited lower gate-to-drain capacitance (C gd) because a depletion capacitance (C gd,dep) was formed by the depletion region under gate dielectric. Consequently, the p–n junction TFET achieved an improvement of cut-off frequency (f T) and intrinsic delay time (τ), which are related to the current performance and total gate capacitance (C gg). We confirmed the enhancement of device performances in terms of I on, f T, and τ by the conduction mechanism of the p–n junction TFET.

Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion.

PubMed

Martí, A; Luque, A

2015-04-22

Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base-emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions.

Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion

PubMed Central

Martí, A.; Luque, A.

2015-01-01

Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base–emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions. PMID:25902374

The free electron gas primary thermometer using an ordinary bipolar junction transistor approaches ppm accuracy.

PubMed

Mimila-Arroyo, J

2017-06-01

In this paper, it is demonstrated that the free electron gas primary thermometer based on a bipolar junction transistor is able to provide the temperature with an accuracy of a few parts per million. Its simple functioning principle exploits the behavior of the collector current when properly biased to extract the temperature. Using general purpose silicon transistors at the water triple point (273.16 K) and gallium melting point (302.9146), an accuracy of a few parts per million has been reached, constituting the simplest and the easiest to operate primary thermometer, that might be considered even for the redefinition of Kelvin.

The free electron gas primary thermometer using an ordinary bipolar junction transistor approaches ppm accuracy

NASA Astrophysics Data System (ADS)

Mimila-Arroyo, J.

2017-06-01

In this paper, it is demonstrated that the free electron gas primary thermometer based on a bipolar junction transistor is able to provide the temperature with an accuracy of a few parts per million. Its simple functioning principle exploits the behavior of the collector current when properly biased to extract the temperature. Using general purpose silicon transistors at the water triple point (273.16 K) and gallium melting point (302.9146), an accuracy of a few parts per million has been reached, constituting the simplest and the easiest to operate primary thermometer, that might be considered even for the redefinition of Kelvin.

High temperature current mirror amplifier

DOEpatents

Patterson, III, Raymond B.

1984-05-22

A high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg.

All-optical transistors and logic gates using a parity-time-symmetric Y-junction: Design and simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ding, Shulin; Wang, Guo Ping, E-mail: gpwang@szu.edu.cn; College of Electronic Science and Technology, Shenzhen University, Shenzhen 518060

Classical nonlinear or quantum all-optical transistors are dependent on the value of input signal intensity or need extra co-propagating beams. In this paper, we present a kind of all-optical transistors constructed with parity-time (PT)-symmetric Y-junctions, which perform independently on the value of signal intensity in an unsaturated gain case and can also work after introducing saturated gain. Further, we show that control signal can switch the device from amplification of peaks in time to transformation of peaks to amplified troughs. By using these PT-symmetric Y-junctions with currently available materials and technologies, we can implement interesting logic functions such as NOTmore » and XOR (exclusive OR) gates, implying potential applications of such structures in designing optical logic gates, optical switches, and signal transformations or amplifications.« less

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation Using Superconducting Tunnel Junctions with Integrated Radio Frequency Single-Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Prober, D. E.; Rhee, K. W.; Schoelkopf, R. J.; Stahle, C. M.; Teufel, J.; Wollack, E. J.

2004-01-01

For high resolution imaging and spectroscopy in the FIR and submillimeter, space observatories will demand sensitive, fast, compact, low-power detector arrays with 104 pixels and sensitivity less than 10(exp -20) W/Hz(sup 0.5). Antenna-coupled superconducting tunnel junctions with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique. The device consists of an antenna to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure current through junctions contacting the absorber. We describe optimization of device parameters, and results on fabrication techniques for producing devices with high yield for detector arrays. We also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Transistor Laser Optical NOR Gate for High Speed Optical Logic Processors

DTIC Science & Technology

2017-03-20

proposes an optical bistable latch can be built with two universal photonic NOR gate circuits, which are implemented by the three-port tunneling ... Tunneling Junction Transistor Laser (TJ-TL); Optical NOR Gate. Introduction To fulfill the future national security and intelligence needs in this...two-terminal diode lasers. Three-Port Transistor Laser – an Integration of Quantum-Wells into Heterojunction Bipolar Transistor Different than

Electrolyte-gated transistors based on conducting polymer nanowire junction arrays.

PubMed

Alam, Maksudul M; Wang, Jun; Guo, Yaoyao; Lee, Stephanie P; Tseng, Hsian-Rong

2005-07-07

In this study, we describe the electrolyte gating and doping effects of transistors based on conducting polymer nanowire electrode junction arrays in buffered aqueous media. Conducting polymer nanowires including polyaniline, polypyrrole, and poly(ethylenedioxythiophene) were investigated. In the presence of a positive gate bias, the device exhibits a large on/off current ratio of 978 for polyaniline nanowire-based transistors; these values vary according to the acidity of the gate medium. We attribute these efficient electrolyte gating and doping effects to the electrochemically fabricated nanostructures of conducting polymer nanowires. This study demonstrates that two-terminal devices can be easily converted into three-terminal transistors by simply immersing the device into an electrolyte solution along with a gate electrode. Here, the field-induced modulation can be applied for signal amplification to enhance the device performance.

High temperature current mirror amplifier

DOEpatents

Patterson, R.B. III.

1984-05-22

Disclosed is a high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg. 2 figs.

Analysis of different tunneling mechanisms of In{sub x}Ga{sub 1−x}As/AlGaAs tunnel junction light-emitting transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Cheng-Han; Wu, Chao-Hsin, E-mail: chaohsinwu@ntu.edu.tw; Graduate Institute of Photonics and Optoelectronics, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 106, Taiwan

The electrical and optical characteristics of tunnel junction light-emitting transistors (TJLETs) with different indium mole fractions (x = 5% and 2.5%) of the In{sub x}Ga{sub 1−x}As base-collector tunnel junctions have been investigated. Two electron tunneling mechanisms (photon-assisted or direct tunneling) provide additional currents to electrical output and resupply holes back to the base region, resulting in the upward slope of I-V curves and enhanced optical output under forward-active operation. The larger direct tunneling probability and stronger Franz-Keldysh absorption for 5% TJLET lead to higher collector current slope and less optical intensity enhancement when base-collector junction is under reverse-biased.

Electrical characterisation of SiGe heterojunction bipolar transistors and Si pseudo-HBTS

NASA Astrophysics Data System (ADS)

De Barros, O.; Le Tron, B.; Woods, R. C.; Giroult-Matlakowski, G.; Vincent, G.; Brémond, G.

1996-08-01

This paper reports an electrical characterisation of the emitter-base junction of Si pseudo-HBTs and SiGe HBTs fabricated in a CMOS compatible single polysilicon self-aligned process. From the reverse characteristics it appears that the definition of the emitter-base junction by plasma etching induces peripheral defects that increase the base current of the transistors. Deep level transient spectroscopy measurements show a deep level in the case of SiGe base, whose spatial origin is not fully determinate up to now.

STABILIZED TRANSISTOR AMPLIFIER

DOEpatents

Noe, J.B.

1963-05-01

A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

Cryogenic measurements of aerojet GaAs n-JFETs

NASA Technical Reports Server (NTRS)

Goebel, John H.; Weber, Theodore T.

1993-01-01

The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.

Progress Towards High-Sensitivity Arrays of Detectors of Sub-mm Radiation using Superconducting Tunnel Junctions with Radio-Frequency Single-Electron Transistors

NASA Technical Reports Server (NTRS)

Stevenson, T. R.; Hsieh, W.-T.; Li, M. J.; Stahle, C. M.; Wollack, E. J.; Schoelkopf, R. J.; Krebs, Carolyn (Technical Monitor)

2002-01-01

The science drivers for the SPIRIT/SPECS missions demand sensitive, fast, compact, low-power, large-format detector arrays for high resolution imaging and spectroscopy in the far infrared and submillimeter. Detector arrays with 10,000 pixels and sensitivity less than 10(exp 20)-20 W/Hz(exp 20)0.5 are needed. Antenna-coupled superconducting tunnel junction detectors with integrated rf single-electron transistor readout amplifiers have the potential for achieving this high level of sensitivity, and can take advantage of an rf multiplexing technique when forming arrays. The device consists of an antenna structure to couple radiation into a small superconducting volume and cause quasiparticle excitations, and a single-electron transistor to measure currents through tunnel junction contacts to the absorber volume. We will describe optimization of device parameters, and recent results on fabrication techniques for producing devices with high yield for detector arrays. We will also present modeling of expected saturation power levels, antenna coupling, and rf multiplexing schemes.

Performance analysis of junction-less double Gate n-p-n impact ionization MOS transistor (JLDG n-IMOS)

NASA Astrophysics Data System (ADS)

Chauhan, Manvendra Singh; Chauhan, R. K.

2018-04-01

This paper demonstrates a Junction-less Double Gate n-p-n Impact ionization MOS transistor (JLDG n-IMOS) on a very light doped p-type silicon body. Device structure proposed in the paper is based on charge plasma concept. There is no metallurgical junctions in the proposed device and does not need any impurity doping to create the drain and source regions. Due to doping-less nature, the fabrication process is simple for JLDG n-IMOS. The double gate engineering in proposed device leads to reduction in avalanche breakdown via impact ionization, generating large number of carriers in drain-body junction, resulting high ION current, small IOFF current and great improvement in ION/IOFF ratio. The simulation and examination of the proposed device have been performed on ATLAS device simulatorsoftware.

Ion bipolar junction transistors

PubMed Central

Tybrandt, Klas; Larsson, Karin C.; Richter-Dahlfors, Agneta; Berggren, Magnus

2010-01-01

Dynamic control of chemical microenvironments is essential for continued development in numerous fields of life sciences. Such control could be achieved with active chemical circuits for delivery of ions and biomolecules. As the basis for such circuitry, we report a solid-state ion bipolar junction transistor (IBJT) based on conducting polymers and thin films of anion- and cation-selective membranes. The IBJT is the ionic analogue to the conventional semiconductor BJT and is manufactured using standard microfabrication techniques. Transistor characteristics along with a model describing the principle of operation, in which an anionic base current amplifies a cationic collector current, are presented. By employing the IBJT as a bioelectronic circuit element for delivery of the neurotransmitter acetylcholine, its efficacy in modulating neuronal cell signaling is demonstrated. PMID:20479274

The physical analysis on electrical junction of junctionless FET

NASA Astrophysics Data System (ADS)

Chen, Lun-Chun; Yeh, Mu-Shih; Lin, Yu-Ru; Lin, Ko-Wei; Wu, Min-Hsin; Thirunavukkarasu, Vasanthan; Wu, Yung-Chun

2017-02-01

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization.

Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

NASA Astrophysics Data System (ADS)

Mookerjea, Saurabh A.

Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SS<60 mV/dec) transistors are under intense research for its potential to replace the ubiquitous MOSFET. The focus of this dissertation is on the design, fabrication and characterization of band-to-band tunneling field effect transistor (TFET) which belongs to the family of steep slope transistors. TFET with a gate modulated zener tunnel junction at the source allows sub-kT/q (sub-60 mV/dec at room temperature) sub-threshold slope (SS) device operation over a certain gate bias range near the off-state. This allows TFET to achieve much higher I ON-IOFF ratio over a specified gate voltage swing compared to MOSFETs, thus enabling aggressive supply voltage scaling for low power logic operation without impacting its ON-OFF current ratio. This dissertation presents the operating principle of TFET, the material selection strategy and device design for TFET fabrication. This is followed by a novel 6T SRAM design which circumvents the issue of unidirectional conduction in TFET. The switching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

Development of ion implanted gallium arsenide transistors

NASA Technical Reports Server (NTRS)

Hunsperger, R.; Baron, R.

1972-01-01

Techniques were developed for creating bipolar microwave transistors in GaAs by ion implantation doping. The electrical properties of doped layers produced by the implantation of the light ions Be, Mg, and S were studied. Be, Mg, and S are suitable for forming the relatively deep base-collector junction at low ion energies. The electrical characteristics of ion-implanted diodes of both the mesa and planar types were determined. Some n-p-n planar transistor structures were fabricated by implantation of Mg to form the base regions and Si to form the emitters. These devices were found to have reasonably good base-collector and emitter-base junctions, but the current gain beta was small. The low was attributable to radiative recombination in the base region, which was extremely wide.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Characterization of vertical GaN p-n diodes and junction field-effect transistors on bulk GaN down to cryogenic temperatures

NASA Astrophysics Data System (ADS)

Kizilyalli, I. C.; Aktas, O.

2015-12-01

There is great interest in wide-bandgap semiconductor devices and most recently in vertical GaN structures for power electronic applications such as power supplies, solar inverters and motor drives. In this paper the temperature-dependent electrical behavior of vertical GaN p-n diodes and vertical junction field-effect transistors fabricated on bulk GaN substrates of low defect density (104 to 106 cm-2) is described. Homoepitaxial MOCVD growth of GaN on its native substrate and the ability to control the doping in the drift layers in GaN have allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40 μm and net carrier electron concentrations as low as 1 × 1015 cm-3. This parameter range is suitable for applications requiring breakdown voltages of 1.2 kV to 5 kV. Mg, which is used as a p-type dopant in GaN, is a relatively deep acceptor (E A ≈ 0.18 eV) and susceptible to freeze-out at temperatures below 200 K. The loss of holes in p-GaN has a deleterious effect on p-n junction behavior, p-GaN contacts and channel control in junction field-effect transistors at temperatures below 200 K. Impact ionization-based avalanche breakdown (BV > 1200 V) in GaN p-n junctions is characterized between 77 K and 423 K for the first time. At higher temperatures the p-n junction breakdown voltage improves due to increased phonon scattering. A positive temperature coefficient in the breakdown voltage is demonstrated down to 77 K; however, the device breakdown characteristics are not as abrupt at temperatures below 200 K. On the other hand, contact resistance to p-GaN is reduced dramatically above room temperature, improving the overall device performance in GaN p-n diodes in all cases except where the n-type drift region resistance dominates the total forward resistance. In this case, the electron mobility can be deconvolved and is found to decrease with T -3/2, consistent with a phonon scattering model. Also, normally-on vertical junction field-effect transistors with BV = 1000 V and drain currents of 4 A are fabricated and characterized over the same temperature range. It is demonstrated that vertical GaN devices (diodes and transistors) utilizing p-n junctions are suitable for most practical applications including automotive ones (210 K < T < 423 K). While devices are functional at cryogenic temperatures (77 K) there may be some limitations to their performance due the freeze-out of Mg acceptors.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

Thermal considerations in the use of solid state power amplifiers on the GOES spacecraft

NASA Technical Reports Server (NTRS)

Mallette, L.; Darby, S.; Baatz, M.; Ujihara, K.

1984-01-01

The use of solid state power amplifiers (SSPA) in satellites has been quite prevalent in several frequency bands. This trend is evidenced by the use of SSPAs at Hughes in the UHF band (Leasat/Syncom IV), S band (GOES), C band (Telstar), and SHF band. The junction temperature of the transistor is the driving requirement which determines the lifetime of the transistor, SSPA, and the payload. This temperature is determined by the transistor characteristics, use of the device, and mounting temperature of the SSPA. The temperature of the spacecraft in the area of the SSPA can be controlled by active or passive means. The various factors and interrelationships used to calculate and control the temperatures of SSPAs are described. The thermal design and calculation of junction temperatures are exemplified with the Geostationary Operational Environmental Satellite spacecraft.

Low noise charge sensitive preamplifier DC stabilized without a physical resistor

DOEpatents

Bertuccio, Giuseppe; Rehak, Pavel; Xi, Deming

1994-09-13

The invention is a novel charge sensitive preamplifier (CSP) which has no resistor in parallel with the feedback capacitor. No resetting circuit is required to discharge the feedback capacitor. The DC stabilization of the preamplifier is obtained by means of a second feedback loop between the preamplifier output and the common base transistor of the input cascode. The input transistor of the preamplifier is a Junction Field Transistor (JFET) with the gate-source junction forward biased. The detector leakage current flows into this junction. This invention is concerned with a new circuit configuration for a charge sensitive preamplifier and a novel use of the input Field Effect Transistor of the CSP itself. In particular this invention, in addition to eliminating the feedback resistor, eliminates the need for external devices between the detector and the preamplifier, and it eliminates the need for external circuitry to sense the output voltage and reset the CSP. Furthermore, the noise level of the novel CSP is very low, comparable with the performance achieved with other solutions. Experimental tests prove that this configuration for the charge sensitive preamplifier permits an excellent noise performance at temperatures including room temperature. An equivalent noise charge of less than 20 electrons r.m.s. has been measured at room temperature by using a commercial JFET as input device of the preamplifier.

Low noise charge sensitive preamplifier DC stabilized without a physical resistor

DOEpatents

Bertuccio, G.; Rehak, P.; Xi, D.

1994-09-13

The invention is a novel charge sensitive preamplifier (CSP) which has no resistor in parallel with the feedback capacitor. No resetting circuit is required to discharge the feedback capacitor. The DC stabilization of the preamplifier is obtained by means of a second feedback loop between the preamplifier output and the common base transistor of the input cascode. The input transistor of the preamplifier is a Junction Field Transistor (JFET) with the gate-source junction forward biased. The detector leakage current flows into this junction. This invention is concerned with a new circuit configuration for a charge sensitive preamplifier and a novel use of the input Field Effect Transistor of the CSP itself. In particular this invention, in addition to eliminating the feedback resistor, eliminates the need for external devices between the detector and the preamplifier, and it eliminates the need for external circuitry to sense the output voltage and reset the CSP. Furthermore, the noise level of the novel CSP is very low, comparable with the performance achieved with other solutions. Experimental tests prove that this configuration for the charge sensitive preamplifier permits an excellent noise performance at temperatures including room temperature. An equivalent noise charge of less than 20 electrons r.m.s. has been measured at room temperature by using a commercial JFET as input device of the preamplifier. 6 figs.

Developing Low-Noise GaAs JFETs For Cryogenic Operation

NASA Technical Reports Server (NTRS)

Cunningham, Thomas J.

1995-01-01

Report discusses aspects of effort to develop low-noise, low-gate-leakage gallium arsenide-based junction field-effect transistors (JFETs) for operation at temperature of about 4 K as readout amplifiers and multiplexing devices for infrared-imaging devices. Transistors needed to replace silicon transistors, relatively noisy at 4 K. Report briefly discusses basic physical principles of JFETs and describes continuing process of optimization of designs of GaAs JFETs for cryogenic operation.

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

NASA Technical Reports Server (NTRS)

Niedra, Janis M.

2006-01-01

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

A Comparison of High-Energy Electron and Cobalt-60 Gamma-Ray Radiation Testing

NASA Technical Reports Server (NTRS)

Boutte, Alvin J.; Campola, Michael J.; Carts, Martin A.; Wilcox, Edward P.; Marshall, Cheryl J.; Phan, Anthony M.; Pellish, Jonathan A.; Powell, Wesley A.; Xapsos, Michael A.

2012-01-01

In this paper, a comparison between the effects of irradiating microelectronics with high energy electrons and Cobalt-60 gamma-rays is examined. Additionally, the effect of electron energy is also discussed. A variety of part types are investigated, including discrete bipolar transistors, hybrids, and junction field effect transistors

Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ball, D. R.; Schrimpf, R. D.; Barnaby, H. J.

2006-01-01

The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

PubMed

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Origin of 1/f PM and AM noise in bipolar junction transistor amplifiers.

PubMed

Walls, F L; Ferre-Pikal, E S; Jefferts, S R

1997-01-01

In this paper we report the results of extensive research on phase modulation (PM) and amplitude modulation (AM) noise in linear bipolar junction transistor (BJT) amplifiers. BJT amplifiers exhibit 1/f PM and AM noise about a carrier signal that is much larger than the amplifiers thermal noise at those frequencies in the absence of the carrier signal. Our work shows that the 1/f PM noise of a BJT based amplifier is accompanied by 1/f AM noise which can be higher, lower, or nearly equal, depending on the circuit implementation. The 1/f AM and PM noise in BJTs is primarily the result of 1/f fluctuations in transistor current, transistor capacitance, circuit supply voltages, circuit impedances, and circuit configuration. We discuss the theory and present experimental data in reference to common emitter amplifiers, but the analysis can be applied to other configurations as well. This study provides the functional dependence of 1/f AM and PM noise on transistor parameters, circuit parameters, and signal frequency, thereby laying the groundwork for a comprehensive theory of 1/f AM and PM noise in BJT amplifiers. We show that in many cases the 1/f PM and AM noise can be reduced below the thermal noise of the amplifier.

Test simulation of neutron damage to electronic components using accelerator facilities

NASA Astrophysics Data System (ADS)

King, D. B.; Fleming, R. M.; Bielejec, E. S.; McDonald, J. K.; Vizkelethy, G.

2015-12-01

The purpose of this work is to demonstrate equivalent bipolar transistor damage response to neutrons and silicon ions. We report on irradiation tests performed at the White Sands Missile Range Fast Burst Reactor, the Sandia National Laboratories (SNL) Annular Core Research Reactor, the SNL SPHINX accelerator, and the SNL Ion Beam Laboratory using commercial silicon npn bipolar junction transistors (BJTs) and III-V Npn heterojunction bipolar transistors (HBTs). Late time and early time gain metrics as well as defect spectra measurements are reported.

Investigation of silicide-induced-dopant-activation for steep tunnel junction in tunnel field effect transistor (TFET)

NASA Astrophysics Data System (ADS)

Kim, Sihyun; Kwon, Dae Woong; Park, Euyhwan; Lee, Junil; Lee, Roongbin; Lee, Jong-Ho; Park, Byung-Gook

2018-02-01

Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Van der Waals epitaxial growth and optoelectronics of large-scale WSe2/SnS2 vertical bilayer p-n junctions.

PubMed

Yang, Tiefeng; Zheng, Biyuan; Wang, Zhen; Xu, Tao; Pan, Chen; Zou, Juan; Zhang, Xuehong; Qi, Zhaoyang; Liu, Hongjun; Feng, Yexin; Hu, Weida; Miao, Feng; Sun, Litao; Duan, Xiangfeng; Pan, Anlian

2017-12-04

High-quality two-dimensional atomic layered p-n heterostructures are essential for high-performance integrated optoelectronics. The studies to date have been largely limited to exfoliated and restacked flakes, and the controlled growth of such heterostructures remains a significant challenge. Here we report the direct van der Waals epitaxial growth of large-scale WSe 2 /SnS 2 vertical bilayer p-n junctions on SiO 2 /Si substrates, with the lateral sizes reaching up to millimeter scale. Multi-electrode field-effect transistors have been integrated on a single heterostructure bilayer. Electrical transport measurements indicate that the field-effect transistors of the junction show an ultra-low off-state leakage current of 10 -14 A and a highest on-off ratio of up to 10 7 . Optoelectronic characterizations show prominent photoresponse, with a fast response time of 500 μs, faster than all the directly grown vertical 2D heterostructures. The direct growth of high-quality van der Waals junctions marks an important step toward high-performance integrated optoelectronic devices and systems.

Theory of the Bloch oscillating transistor

NASA Astrophysics Data System (ADS)

Hassel, J.; Seppä, H.

2005-01-01

The Bloch oscillating transistor (BOT) is a device in which single electron current through a normal tunnel junction enhances Cooper pair current in a mesoscopic Josephson junction, leading to signal amplification. In this article we develop a theory in which the BOT dynamics is described as a two-level system. The theory is used to predict current-voltage characteristics and small-signal response. The transition from stable operation into the hysteretic regime is studied. By identifying the two-level switching noise as the main source of fluctuations, the expressions for equivalent noise sources and the noise temperature are derived. The validity of the model is tested by comparing the results with simulations and experiments.

ac Josephson effect and resonant Cooper pair tunneling emission of a single Cooper pair transistor.

PubMed

Billangeon, P-M; Pierre, F; Bouchiat, H; Deblock, R

2007-05-25

We measure the high-frequency emission of a single Cooper pair transistor (SCPT) in the regime where transport is only due to tunneling of Cooper pairs. This is achieved by coupling on chip the SCPT to a superconductor-insulator-superconductor junction and by measuring the photon assisted tunneling current of quasiparticles across the junction. This technique allows a direct detection of the ac Josephson effect of the SCPT and provides evidence of Landau-Zener transitions for proper gate voltage. The emission in the regime of resonant Cooper pair tunneling is also investigated. It is interpreted in terms of transitions between charge states coupled by the Josephson effect.

A comparative study on electrical characteristics of 1-kV pnp and npn SiC bipolar junction transistors

NASA Astrophysics Data System (ADS)

Okuda, Takafumi; Kimoto, Tsunenobu; Suda, Jun

2018-04-01

We investigate the electrical characteristics of 1-kV pnp SiC bipolar junction transistors (BJTs) and compare them with those of npn SiC BJTs. The base resistance, current gain, and blocking capability are characterized. It is found that the base resistance of pnp SiC BJTs is two orders of magnitude lower than that of npn SiC BJTs. However, the obtained current gains are low below unity in pnp SiC BJTs, whereas npn SiC BJTs exhibit a current gain of 14 without surface passivation. The reason for the poor current gain of pnp SiC BJTs is discussed.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Behavior of a chemically doped graphene junction

NASA Astrophysics Data System (ADS)

Farmer, Damon B.; Lin, Yu-Ming; Afzali-Ardakani, Ali; Avouris, Phaedon

2009-05-01

Polyethylene imine and diazonium salts are used as complementary molecular dopants to engineer a doping profile in a graphene transistor. Electronic transport in this device reveals the presence of two distinct resistance maxima, alluding to neutrality point separation and subsequent formation of a spatially abrupt junction. Carrier mobility in this device is not significantly affected by molecular doping or junction formation, and carrier transmission is found to scale inversely with the effective channel length of the device. Chemical dilutions are used to modify the dopant concentration and, in effect, alter the properties of the junction.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

NASA Astrophysics Data System (ADS)

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor.

Comparison between Field Effect Transistors and Bipolar Junction Transistors as Transducers in Electrochemical Sensors

PubMed Central

Zafar, Sufi; Lu, Minhua; Jagtiani, Ashish

2017-01-01

Field effect transistors (FET) have been widely used as transducers in electrochemical sensors for over 40 years. In this report, a FET transducer is compared with the recently proposed bipolar junction transistor (BJT) transducer. Measurements are performed on two chloride electrochemical sensors that are identical in all details except for the transducer device type. Comparative measurements show that the transducer choice significantly impacts the electrochemical sensor characteristics. Signal to noise ratio is 20 to 2 times greater for the BJT sensor. Sensitivity is also enhanced: BJT sensing signal changes by 10 times per pCl, whereas the FET signal changes by 8 or less times. Also, sensor calibration curves are impacted by the transducer choice. Unlike a FET sensor, the calibration curve of the BJT sensor is independent of applied voltages. Hence, a BJT sensor can make quantitative sensing measurements with minimal calibration requirements, an important characteristic for mobile sensing applications. As a demonstration for mobile applications, these BJT sensors are further investigated by measuring chloride levels in artificial human sweat for potential cystic fibrosis diagnostic use. In summary, the BJT device is demonstrated to be a superior transducer in comparison to a FET in an electrochemical sensor. PMID:28134275

Realization of Molecular-Based Transistors.

PubMed

Richter, Shachar; Mentovich, Elad; Elnathan, Roey

2018-06-06

Molecular-based devices are widely considered as significant candidates to play a role in the next generation of "post-complementary metal-oxide-semiconductor" devices. In this context, molecular-based transistors: molecular junctions that can be electrically gated-are of particular interest as they allow new modes of operation. The properties of molecular transistors composed of a single- or multimolecule assemblies, focusing on their practicality as real-world devices, concerning industry demands and its roadmap are compared. Also, the capability of the gate electrode to modulate the molecular transistor characteristics efficiently is addressed, showing that electrical gating can be easily facilitated in single molecular transistors and that gating of transistor composed of molecular assemblies is possible if the device is formed vertically. It is concluded that while the single-molecular transistor exhibits better performance on the lab-scale, its realization faces signifacant challenges when compared to those faced by transistors composed of a multimolecule assembly. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Quantum structures for recombination control in the light-emitting transistor

NASA Astrophysics Data System (ADS)

Chen, Kanuo; Hsiao, Fu-Chen; Joy, Brittany; Dallesasse, John M.

2017-02-01

Recombination of carriers in the direct-bandgap base of a transistor-injected quantum cascade laser (TI-QCL) is shown to be controllable through the field applied across the quantum cascade region located in the transistor's base-collector junction. The influence of the electric field on the quantum states in the cascade region's superlattice allows free flow of electrons out of the transistor base only for field values near the design field that provides optimal QCL gain. Quantum modulation of base recombination in the light-emitting transistor is therefore observed. In a GaAs-based light-emitting transistor, a periodic superlattice is grown between the p-type base and the n-type collector. Under different base-collector biasing conditions the distribution of quantum states, and as a consequence transition probabilities through the wells and barriers forming the cascade region, leads to strong field-dependent mobility for electrons in transit through the base-collector junction. The radiative base recombination, which is influenced by minority carrier transition lifetime, can be modulated through the quantum states alignment in the superlattice. A GaAs-based transistor-injected quantum cascade laser with AlGaAs/GaAs superlattice is designed and fabricated. Radiative base recombination is measured under both common-emitter and common-base configuration. In both configurations the optical output from the base is proportional to the emitter injection. When the quantum states in the superlattice are aligned the optical output in the base is reduced as electrons encounter less impedance entering the collector; when the quantum states are misaligned electrons have longer lifetime in the base and the radiative base recombination process is enhanced.

Proton Irradiation as a Screen for Displacement-Damage Sensitivity in Bipolar Junction Transistors

NASA Astrophysics Data System (ADS)

Arutt, Charles N.; Warren, Kevin M.; Schrimpf, Ronald D.; Weller, Robert A.; Kauppila, Jeffrey S.; Rowe, Jason D.; Sternberg, Andrew L.; Reed, Robert A.; Ball, Dennis R.; Fleetwood, Daniel M.

2015-12-01

NPN and PNP bipolar junction transistors of varying sizes are irradiated with 4-MeV protons and 10-keV X-rays to determine the amount of ionization-related degradation caused by protons and calculate an improved estimate of displacement-related degradation due to protons. While different ratios of degradation produced by displacement damage and ionization effects will occur for different device technologies, this general approach, with suitable margin, can be used as a screen for sensitivity to neutron-induced displacement damage. Further calculations are performed to estimate the amount of degradation produced by 1-MeV equivalent neutron displacement damage compared to that produced by the displacement damage due to protons. The results are compared to previous work.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

NASA Astrophysics Data System (ADS)

Shin, Sunhae; Rok Kim, Kyung

2015-06-01

In this paper, we propose a novel multiple negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) over 106 by combining tunnel diode with a conventional MOSFET, which suppresses the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and the second peak and valley are generated from the suppression of diffusion current in tunnel diode by the off-state MOSFET. The multiple NDR curves can be controlled by doping concentration of tunnel junction and the threshold voltage of MOSFET. By using complementary multiple NDR devices, five-state memory is demonstrated only with six transistors.

A dc model for power switching transistors suitable for computer-aided design and analysis

NASA Technical Reports Server (NTRS)

Wilson, P. M.; George, R. T., Jr.; Owen, H. A.; Wilson, T. G.

1979-01-01

A model for bipolar junction power switching transistors whose parameters can be readily obtained by the circuit design engineer, and which can be conveniently incorporated into standard computer-based circuit analysis programs is presented. This formulation results from measurements which may be made with standard laboratory equipment. Measurement procedures, as well as a comparison between actual and computed results, are presented.

Vortices in Long Josephson Junctions.

DTIC Science & Technology

1987-11-01

of the very low impedance vortex flow transistor and toward determination of its potential for high frequency applications. Capability for higher...version. New progress was made toward solution of the problems of high frequency testing of the very low impedance vortex flow transistor and towards... measurable transresistance ’". out to frequencies of about 10% of the theoretical transit time cutoff fre- quency. Capability for higher frequency testing

A random access memory immune to single event upset using a T-Resistor

DOEpatents

Ochoa, A. Jr.

1987-10-28

In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

Random access memory immune to single event upset using a T-resistor

DOEpatents

Ochoa, Jr., Agustin

1989-01-01

In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

Effect of quantum well position on the distortion characteristics of transistor laser

NASA Astrophysics Data System (ADS)

Piramasubramanian, S.; Ganesh Madhan, M.; Radha, V.; Shajithaparveen, S. M. S.; Nivetha, G.

2018-05-01

The effect of quantum well position on the modulation and distortion characteristics of a 1300 nm transistor laser is analyzed in this paper. Standard three level rate equations are numerically solved to study this characteristics. Modulation depth, second order harmonic and third order intermodulation distortion of the transistor laser are evaluated for different quantum well positions for a 900 MHz RF signal modulation. From the DC analysis, it is observed that optical power is maximum, when the quantum well is positioned near base-emitter interface. The threshold current of the device is found to increase with increasing the distance between the quantum well and the base-emitter junction. A maximum modulation depth of 0.81 is predicted, when the quantum well is placed at 10 nm from the base-emitter junction, under RF modulation. The magnitude of harmonic and intermodulation distortion are found to decrease with increasing current and with an increase in quantum well distance from the emitter base junction. A minimum second harmonic distortion magnitude of -25.96 dBc is predicted for quantum well position (230 nm) near to the base-collector interface for 900 MHz modulation frequency at a bias current of 20 Ibth. Similarly, a minimum third order intermodulation distortion of -38.2 dBc is obtained for the same position and similar biasing conditions.

Photojunction field-effect transistor based on a colloidal quantum dot absorber channel layer.

PubMed

Adinolfi, Valerio; Kramer, Illan J; Labelle, André J; Sutherland, Brandon R; Hoogland, S; Sargent, Edward H

2015-01-27

The performance of photodetectors is judged via high responsivity, fast speed of response, and low background current. Many previously reported photodetectors based on size-tuned colloidal quantum dots (CQDs) have relied either on photodiodes, which, since they are primary photocarrier devices, lack gain; or photoconductors, which provide gain but at the expense of slow response (due to delayed charge carrier escape from sensitizing centers) and an inherent dark current vs responsivity trade-off. Here we report a photojunction field-effect transistor (photoJFET), which provides gain while breaking prior photoconductors' response/speed/dark current trade-off. This is achieved by ensuring that, in the dark, the channel is fully depleted due to a rectifying junction between a deep-work-function transparent conductive top contact (MoO3) and a moderately n-type CQD film (iodine treated PbS CQDs). We characterize the rectifying behavior of the junction and the linearity of the channel characteristics under illumination, and we observe a 10 μs rise time, a record for a gain-providing, low-dark-current CQD photodetector. We prove, using an analytical model validated using experimental measurements, that for a given response time the device provides a two-orders-of-magnitude improvement in photocurrent-to-dark-current ratio compared to photoconductors. The photoJFET, which relies on a junction gate-effect, enriches the growing family of CQD photosensitive transistors.

A dc model for power switching transistors suitable for computer-aided design and analysis

NASA Technical Reports Server (NTRS)

Wilson, P. M.; George, R. T., Jr.; Owen, H. A., Jr.; Wilson, T. G.

1979-01-01

The proposed dc model for bipolar junction power switching transistors is based on measurements which may be made with standard laboratory equipment. Those nonlinearities which are of importance to power electronics design are emphasized. Measurements procedures are discussed in detail. A model formulation adapted for use with a computer program is presented, and a comparison between actual and computer-generated results is made.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

NASA Astrophysics Data System (ADS)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Static and dynamic behavior of a Si/Si0.8Ge0.2/Si heterojunction bipolar transistor using Monte Carlo simulation

NASA Astrophysics Data System (ADS)

Galdin, Sylvie; Dollfus, Philippe; Hesto, Patrice

1994-03-01

A theoretical study of a Si/Si1-xGex/Si heterojunction bipolar transistor using Monte Carlo simulations is reported. The geometry and composition of the emitter-base junction are optimized using one-dimensional simulations with a view to improving electron transport in the base. It is proposed to introduce a thin Si-P spacer layer, between the Si-N emitter and the SiGe-P base, which allows launching hot electrons into the base despite the lack of natural conduction-band discontinuity between Si and strain SiGe. The high-frequency behavior of the complete transistor is then studied using 2D modeling. A method of microwave analysis using small signal Monte Carlo simulations that consists of expanding the terminal currents in Fourier series is presented. A cutoff frequency fT of 68 GHz has been extracted. Finally, the occurrence of a parasitic electron barrier at the collector-base junction is responsible for the fT fall-off at high collector current density. This parasitic barrier is lowered through the influence of the collector potential.

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2006-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Graded junction termination extensions for electronic devices

NASA Technical Reports Server (NTRS)

Merrett, J. Neil (Inventor); Isaacs-Smith, Tamara (Inventor); Sheridan, David C. (Inventor); Williams, John R. (Inventor)

2007-01-01

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Single-event burnout of n-p-n bipolar-junction transistors in hybrid DC/DC converters

NASA Astrophysics Data System (ADS)

Warren, K.; Roth, D.; Kinnison, J.; Pappalardo, R.

2002-12-01

Single-event-induced failure of the Lambda Advanced Analog AMF2805S DC/DC Converter has been traced to burnout of an n-p-n transistor in the MOSFET drive stage. The failures were observed during testing while in inhibit mode only. Modifications to prevent burnout of the drive stage were successfully employed. A discussion of the failure mechanism and consequences for DC/DC converter testing are presented.

Steering of quantum waves: Demonstration of Y-junction transistors using InAs quantum wires

NASA Astrophysics Data System (ADS)

Jones, Gregory M.; Qin, Jie; Yang, Chia-Hung; Yang, Ming-Jey

2005-06-01

In this paper we demonstrate using an InAs quantum wire Y-branch switch that the electron wave can be switched to exit from the two drains by a lateral gate bias. The gating modifies the electron wave functions as well as their interference pattern, causing the anti-correlated, oscillatory transconductances. Our result suggests a new transistor function in a multiple-lead ballistic quantum wire system.

Studies of silicon p-n junction solar cells

NASA Technical Reports Server (NTRS)

Neugroschel, A.; Lindholm, F. A.

1979-01-01

To provide theoretical support for investigating different ways to obtain high open-circuit voltages in p-n junction silicon solar cells, an analytical treatment of heavily doped transparent-emitter devices is presented that includes the effects of bandgap narrowing, Fermi-Dirac statistics, a doping concentration gradient, and a finite surface recombination velocity at the emitter surface. Topics covered include: (1) experimental determination of bandgap narrowing in the emitter of silicon p-n junction devices; (2) heavily doped transparent regions in junction solar cells, diodes, and transistors; (3) high-low-emitter solar cell; (4) determination of lifetimes and recombination currents in p-n junction solar cells; (5) MOS and oxide-charged-induced BSF solar cells; and (6) design of high efficiency solar cells for space and terrestrial applications.

Experimental demonstration of single electron transistors featuring SiO{sub 2} plasma-enhanced atomic layer deposition in Ni-SiO{sub 2}-Ni tunnel junctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karbasian, Golnaz, E-mail: Golnaz.Karbasian.1@nd.edu; McConnell, Michael S.; Orlov, Alexei O.

The authors report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultrathin (≈1 nm) tunnel-transparent SiO{sub 2} in Ni-SiO{sub 2}-Ni tunnel junctions. They show that, as a result of the O{sub 2} plasma steps in PEALD of SiO{sub 2}, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO{sub 2}, most likely as a result of oxygen-containing species on the surface of the SiO{sub 2}. Due to the presence of these surface parasitic layersmore » of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni-SiO{sub 2}-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultrathin barriers. Using this technique, the authors successfully fabricated MIM SETs with minimal trace of parasitic NiO component. They demonstrate that the properties of the tunnel barrier in nanoscale tunnel junctions (with <10{sup −15} m{sup 2} in area) can be evaluated by electrical characterization of SETs.« less

Black Phosphorus-Zinc Oxide Nanomaterial Heterojunction for p-n Diode and Junction Field-Effect Transistor.

PubMed

Jeon, Pyo Jin; Lee, Young Tack; Lim, June Yeong; Kim, Jin Sung; Hwang, Do Kyung; Im, Seongil

2016-02-10

Black phosphorus (BP) nanosheet is two-dimensional (2D) semiconductor with distinct band gap and attracting recent attention from researches because it has some similarity to gapless 2D semiconductor graphene in the following two aspects: single element (P) for its composition and quite high mobilities depending on its fabrication conditions. Apart from several electronic applications reported with BP nanosheet, here we report for the first time BP nanosheet-ZnO nanowire 2D-1D heterojunction applications for p-n diodes and BP-gated junction field effect transistors (JFETs) with n-ZnO channel on glass. For these nanodevices, we take advantages of the mechanical flexibility of p-type conducting of BP and van der Waals junction interface between BP and ZnO. As a result, our BP-ZnO nanodimension p-n diode displays a high ON/OFF ratio of ∼10(4) in static rectification and shows kilohertz dynamic rectification as well while ZnO nanowire channel JFET operations are nicely demonstrated by BP gate switching in both electrostatics and kilohertz dynamics.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

NASA Astrophysics Data System (ADS)

Knoll, L.; Richter, S.; Nichau, A.; Trellenkamp, S.; Schäfer, A.; Wirths, S.; Blaeser, S.; Buca, D.; Bourdelle, K. K.; Zhao, Q.-T.; Mantl, S.

2014-08-01

Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78 μA/μm at VD = VG = 1.1 V is obtained.

Electronic decoherence of two-level systems in a Josephson junction

NASA Astrophysics Data System (ADS)

Bilmes, Alexander; Zanker, Sebastian; Heimes, Andreas; Marthaler, Michael; Schön, Gerd; Weiss, Georg; Ustinov, Alexey V.; Lisenfeld, Jürgen

2017-08-01

The sensitivity of superconducting qubits allows for spectroscopy and coherence measurements on individual two-level systems present in the disordered tunnel barrier of an Al /AlOx /Al Josephson junction. We report experimental evidence for the decoherence of two-level systems by Bogoliubov quasiparticles leaking into the insulating AlOx barrier. We control the density of quasiparticles in the junction electrodes either by the sample temperature or by injecting them using an on-chip dc superconducting quantum interference device driven to its resistive state. The decoherence rates were measured by observing the two-level system's quantum state evolving under application of resonant microwave pulses and were found to increase linearly with quasiparticle density, in agreement with theory. This interaction with electronic states provides a noise and decoherence mechanism that is relevant for various microfabricated devices such as qubits, single-electron transistors, and field-effect transistors. The presented experiments also offer a possibility to determine the location of the probed two-level systems across the tunnel barrier, providing clues about the fabrication step in which they emerge.

Transport properties and device-design of Z-shaped MoS2 nanoribbon planar junctions

NASA Astrophysics Data System (ADS)

Zhang, Hua; Zhou, Wenzhe; Liu, Qi; Yang, Zhixiong; Pan, Jiangling; Ouyang, Fangping; Xu, Hui

2017-09-01

Based on MoS2 nanoribbons, metal-semiconductor-metal planar junction devices were constructed. The electronic and transport properties of the devices were studied by using density function theory (DFT) and nonequilibrium Green's functions (NEGF). It is found that a band gap about 0.4 eV occurs in the planar junction. The electron and hole transmissions of the devices are mainly contributed by the Mo atomic orbitals. The electron transport channel is located at the edge of armchair MoS2 nanoribbon, while the hole transport channel is delocalized in the channel region. The I-V curve of the two-probe device shows typical transport behavior of Schottky barrier, and the threshold voltage is of about 0.2 V. The field effect transistors (FET) based on the planar junction turn out to be good bipolar transistors, the maximum current on/off ratio can reach up to 1 × 104, and the subthreshold swing is 243 mV/dec. It is found that the off-state current is dependent on the length and width of the channel, while the on-state current is almost unaffected. The switching performance of the FET is improved with increasing the length of the channel, and shows oscillation behavior with the change of the channel width.

Local bipolar-transistor gain measurement for VLSI devices

NASA Astrophysics Data System (ADS)

Bonnaud, O.; Chante, J. P.

1981-08-01

A method is proposed for measuring the gain of a bipolar transistor region as small as possible. The measurement then allows the evaluation particularly of the effect of the emitter-base junction edge and the technology-process influence of VLSI-technology devices. The technique consists in the generation of charge carriers in the transistor base layer by a focused laser beam in order to bias the device in as small a region as possible. To reduce the size of the conducting area, a transversal reverse base current is forced through the base layer resistance in order to pinch in the emitter current in the illuminated region. Transistor gain is deduced from small signal measurements. A model associated with this technique is developed, and this is in agreement with the first experimental results.

An Electronics "Unit Laboratory"

ERIC Educational Resources Information Center

Davies, E. R.; Penton, S. J.

1976-01-01

Describes a laboratory teaching technique in which a single topic (in this case, bipolar junction transistors) is studied over a period of weeks under the supervision of one staff member, who also designs the laboratory work. (MLH)

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

Long-Term Reliability of High Speed SiGe/Si Heterojunction Bipolar Transistors

NASA Technical Reports Server (NTRS)

Ponchak, George E. (Technical Monitor); Bhattacharya, Pallab

2003-01-01

Accelerated lifetime tests were performed on double-mesa structure Si/Si0.7Ge0.3/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175C-275C. Both single- and multiple finger transistors were tested. The single-finger transistors (with 5x20 micron sq m emitter area) have DC current gains approximately 40-50 and f(sub T) and f(sub MAX) of up to 22 GHz and 25 GHz, respectively. The multiple finger transistors (1.4 micron finger width, 9 emitter fingers with total emitter area of 403 micron sq m) have similar DC current gain but f(sub T) of 50 GHz. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REID has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of the devices at room temperature is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation. SiGe/Si based amplifier circuits were also subjected to lifetime testing and we extrapolate MTTF is approximately 1.1_10(exp 6) hours at 125iC junction temperature from the circuit lifetime data.

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

PubMed Central

Ohno, Takeo; Oyama, Yutaka

2012-01-01

In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm-2. They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor. PMID:27877466

Unimolecular rectifiers and proposed unimolecular amplifier.

PubMed

Metzger, Robert M

2003-12-01

The rectification by three molecules that form Langmuir-Blodgett monolayers between gold electrodes is reviewed, along with a proposal for the means to obtain gain in a unimolecular amplifier, the molecular analog of a bipolar junction transistor.

Control of radiative base recombination in the quantum cascade light-emitting transistor using quantum state overlap

NASA Astrophysics Data System (ADS)

Chen, Kanuo; Hsiao, Fu-Chen; Joy, Brittany; Dallesasse, John M.

2018-07-01

The concept of the quantum cascade light-emitting transistor (QCLET) is proposed by incorporating periodic stages of quantum wells and barriers in the completely depleted base-collector junction of a heterojunction bipolar transistor. The radiative band-to-band base recombination in the QCLET is shown to be controllable using the base-collector voltage bias for a given emitter-base biasing condition. A self-consistent Schrödinger-Poisson Equation model is built to validate the idea of the QCLET. A GaAs-based QCLET is designed and fabricated. Control of radiative band-to-band base recombination is observed and characterized. By changing the voltage across the quantum cascade region in the QCLET, the alignment of quantum states in the cascade region creates a tunable barrier for electrons that allows or suppresses emitter-injected electron flow from the p-type base through the quantum cascade region into the collector. The field-dependent electron barrier in the base-collector junction manipulates the effective minority carrier lifetime in the base and controls the radiative base recombination process. Under different quantum cascade region biasing conditions, the radiative base recombination is measured and analyzed.

MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

PubMed

Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

2011-10-15

In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

Engineering Design Handbook: Reliable Military Electronics

DTIC Science & Technology

1976-01-15

p. 30. CBS-Hytron: "I..ow-o::stPower Trall8istors," E1a::Drnic Design, 1 Nov. 1956, p. 24. Chang, C. M.: "An NPN High-Power Fast Germanium Col:e...34Monovibrator Has Fast Recovery Time," Electronics, Dec. 1957, p. 158. Carlson, A W. : "Junction Transistor Counters," EledronicDesign, 1 March 1957, p. 28...Method Makes Fast Pulses in Transistor Circuits," Electronic Design, 28 May 1958, p. 44. Stassior, R. A : "Pulse Applications cf a Diffused-Meltback

JFET/SOS (Junction Field-Effect Transistor/Silicon-on-Sapphire) Devices: Gamma-Radiation-Induced Effects.

DTIC Science & Technology

1988-03-01

Results, ATR-86A(8501)-1, The Aerospace Corporation: El Segundo, Calif. (20 May 1987). 3. D. Neaman , W. Shedd, and B. Buchanan, "Permanently Ionizing...Radiation Effects in Dielectrically Bounded Field-Effect Transistors," IEEE Trans.. Nucl. Sci. NS-20 [6], 158-165 (Decembe. 1973). 4. D. Neaman , W. Shedd...1974). 5. D. Neaman , W. Shedd, and B. Buchanan, "Silicon-Sapphire Interface Charge Trapping -- Effects of Sapphire Type and Epi Growth Conditions

The analysis of ion-selective field-effect transistor operation in chemical sensors

NASA Astrophysics Data System (ADS)

Hotra, Zenon; Holyaka, Roman; Hladun, Michael; Humenuk, Iryna

2003-09-01

In this paper we present the research results of influence of substrate potential in ion-selective field-effect transistors (ISFET) on output signal of chemical sensors, e.g. PH-meters. It is shown that the instability of substrate-source p-n junction bias in well-known chemical sensors, which use grounded reference electrode - ISFET gate, affect on sensor characteristics in negative way. The analytical description and research results of 'substrate effect' on ISFET characteristics are considered.

Bloch oscillating transistor as the readout element for hot electron bolometers

NASA Astrophysics Data System (ADS)

Hassel, Juha; Seppä, Heikki; Lindell, Rene; Hakonen, Pertti

2004-10-01

In this paper we analyse the properties of the Bloch oscillating transistor as a preamplifier in cryogenic devices. We consider here especially the readout of hot electron bolometers (HEBs) based on Normal-Superconductor-Insulator tunnel junctions, but the results also apply more generally. We show that one can get an equivalent noise voltage below 1 nV/√Hz with a single BOT. By using N BOTs in a parallel array configuration, a further reduction by factor √N may be achieved.

Noise characteristics of single-walled carbon nanotube network transistors.

PubMed

Kim, Un Jeong; Kim, Kang Hyun; Kim, Kyu Tae; Min, Yo-Sep; Park, Wanjun

2008-07-16

The noise characteristics of randomly networked single-walled carbon nanotubes grown directly by plasma enhanced chemical vapor deposition (PECVD) are studied with field effect transistors (FETs). Due to the geometrical complexity of nanotube networks in the channel area and the large number of tube-tube/tube-metal junctions, the inverse frequency, 1/f, dependence of the noise shows a similar level to that of a single single-walled carbon nanotube transistor. Detailed analysis is performed with the parameters of number of mobile carriers and mobility in the different environment. This shows that the change in the number of mobile carriers resulting in the mobility change due to adsorption and desorption of gas molecules (mostly oxygen molecules) to the tube surface is a key factor in the 1/f noise level for carbon nanotube network transistors.

Magnetic vortex based transistor operations.

PubMed

Kumar, D; Barman, S; Barman, A

2014-02-17

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan-out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT).

Magnetic Vortex Based Transistor Operations

NASA Astrophysics Data System (ADS)

Kumar, D.; Barman, S.; Barman, A.

2014-02-01

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan-out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT).

Energetic distributions of interface states Dit(phi sub s) of MOS transistors in extension of Kuhn's quasistatic C(V)-method

NASA Astrophysics Data System (ADS)

Krautschneider, W.; Wagemann, H. G.

1983-10-01

Kuhn's quasi-static C(V)-method has been extended to MOS transistors by considering the capacitances of the source and drain p-n junctions additionally to the MOS varactor circuit model. The width of the space charge layers w(phi sub s) is calculated as a function of the surface potential phi sub s and applied to the MOS capacitance as a function of the gate voltage. Capacitance behavior for different channel length is presented as a model and compared to measurement results and evaluations of energetic distributions of interface states Dit(phi sub s) for MOS transistor and MOS varactor on the same chip.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Very high frequency spectroscopy and tuning of a single-cooper-pair transistor with an on-chip generator.

PubMed

Billangeon, P-M; Pierre, F; Bouchiat, H; Deblock, R

2007-03-23

A single-Cooper-pair transistor (SCPT) is coupled capacitively to a voltage biased Josephson junction, used as a high-frequency generator. Thanks to the high energy of photons generated by the Josephson junction, transitions between energy levels, not limited to the first two levels, were induced and the effect of this irradiation on the dc Josephson current of the SCPT was measured. The phase and gate bias dependence of energy levels of the SCPT at high energy is probed. Because the energies of photons can be higher than the superconducting gap we can induce not only transfer of Cooper pairs but also transfer of quasiparticles through the island of the SCPT, thus controlling the poisoning of the SCPT. This can both decrease and increase the average Josephson energy of the SCPT: its supercurrent is then controlled by high-frequency irradiation.

Current conduction in junction gate field effect transistors. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Kim, C.

1970-01-01

The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.

Theoretical results on the tandem junction solar cell based on its Ebers-Moll transistor model

NASA Technical Reports Server (NTRS)

Goradia, C.; Vaughn, J.; Baraona, C. R.

1980-01-01

A one-dimensional theoretical model of the tandem junction solar cell (TJC) with base resistivity greater than about 1 ohm-cm and under low level injection has been derived. This model extends a previously published conceptual model which treats the TJC as an npn transistor. The model gives theoretical expressions for each of the Ebers-Moll type currents of the illuminated TJC and allows for the calculation of the spectral response, I(sc), V(oc), FF and eta under variation of one or more of the geometrical and material parameters and 1MeV electron fluence. Results of computer calculations based on this model are presented and discussed. These results indicate that for space applications, both a high beginning of life efficiency, greater than 15% AM0, and a high radiation tolerance can be achieved only with thin (less than 50 microns) TJC's with high base resistivity (greater than 10 ohm-cm).

High Accuracy Transistor Compact Model Calibrations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hembree, Charles E.; Mar, Alan; Robertson, Perry J.

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirementsmore » require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.« less

Development and fabrication of an augmented power transistor

NASA Technical Reports Server (NTRS)

Geisler, M. J.; Hill, F. E.; Ostop, J. A.

1983-01-01

The development of device design and processing techniques for the fabrication of an augmented power transistor capable of fast switching and high voltage power conversion is discussed. The major device goals sustaining voltages in the range of 800 to 1000 V at 80 A and 50 A, respectively, at a gain of 14. The transistor switching rise and fall times were both to have been less than 0.5 microseconds. The development of a passivating glass technique to shield the device high voltage junction from moisture and ionic contaminants is discussed as well as the development of an isolated package that separates the thermal and electrical interfaces. A new method was found to alloy the transistors to the molybdenum disc at a relatively low temperature. The measured electrical performance compares well with the predicted optimum design specified in the original proposed design. A 40 mm diameter transistor was fabricated with seven times the emitter area of the earlier 23 mm diameter device.

Theoretical and experimental characterization of the DUal-BAse transistor (DUBAT)

NASA Astrophysics Data System (ADS)

Wu, Chung-Yu; Wu, Ching-Yuan

1980-11-01

A new A-type integrated voltage controlled differential negative resistance device using an extra effective base region to form a lateral pnp (npn) bipolar transistor beside the original base region of a vertical npn (pnp) bipolar junction transistor, and so called the DUal BAse Transistor (DUBAT), is studied both experimentally and theoretically, The DUBAT has three terminals and is fully comparible with the existing bipolar integrated circuits technologies. Based upon the equivalent circuit of the DUBAT, a simple first-order analytical theory is developed, and important device parameters, such as: the I-V characteristic, the differential negative resistance, and the peak and valley points, are also characterized. One of the proposed integrated structures of the DUBAT, which is similar in structure to I 2L but with similar high density and a normally operated vertical npn transistor, has been successfully fabricated and studied. Comparisons between the experimental data and theoretical analyses are made, and show in satisfactory agreements.

Measuring, modeling, and minimizing capacitances in heterojunction bipolar transistors

NASA Astrophysics Data System (ADS)

Anholt, R.; Bozada, C.; Dettmer, R.; Via, D.; Jenkins, T.; Barrette, J.; Ebel, J.; Havasy, C.; Sewell, J.; Quach, T.

1996-07-01

We demonstrate methods to separate junction and pad capacitances from on-wafer S-parameter measurements of HBTs with different areas and layouts. The measured junction capacitances are in good agreement with models, indicating that large-area devices are suitable for monitoring vendor epi-wafer doping. Measuring open HBTs does not give the correct pad capacitances. Finally, a capacitance comparison for a variety of layouts shows that bar-devices consistently give smaller base-collector values than multiple dot HBTs.

Towards high frequency heterojunction transistors: Electrical characterization of N-doped amorphous silicon-graphene diodes

NASA Astrophysics Data System (ADS)

Strobel, C.; Chavarin, C. A.; Kitzmann, J.; Lupina, G.; Wenger, Ch.; Albert, M.; Bartha, J. W.

2017-06-01

N-type doped amorphous hydrogenated silicon (a-Si:H) is deposited on top of graphene (Gr) by means of very high frequency (VHF) and radio frequency plasma-enhanced chemical vapor deposition (PECVD). In order to preserve the structural integrity of the monolayer graphene, a plasma excitation frequency of 140 MHz was successfully applied during the a-Si:H VHF-deposition. Raman spectroscopy results indicate the absence of a defect peak in the graphene spectrum after the VHF-PECVD of (n)-a-Si:H. The diode junction between (n)-a-Si:H and graphene was characterized using temperature dependent current-voltage (IV) and capacitance-voltage measurements, respectively. We demonstrate that the current at the (n)-a-Si:H-graphene interface is dominated by thermionic emission and recombination in the space charge region. The Schottky barrier height (qΦB), derived by temperature dependent IV-characteristics, is about 0.49 eV. The junction properties strongly depend on the applied deposition method of (n)-a-Si:H with a clear advantage of the VHF(140 MHz)-technology. We have demonstrated that (n)-a-Si:H-graphene junctions are a promising technology approach for high frequency heterojunction transistors.

Planar edge Schottky barrier-tunneling transistors using epitaxial graphene/SiC junctions.

PubMed

Kunc, Jan; Hu, Yike; Palmer, James; Guo, Zelei; Hankinson, John; Gamal, Salah H; Berger, Claire; de Heer, Walt A

2014-09-10

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

Study of vertical type organic light emitting transistor using ZnO

NASA Astrophysics Data System (ADS)

Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro

2006-04-01

We propose a new type organic light emitting transistor (OLET) combining static induction transistor (SIT) with double hetero junction type organic light emitting diodes (OLED) using n-type zinc oxide (ZnO) films which works as a transparent and electron injection layer. The device characteristics of newly developed OLED and ZnO-SIT showed relatively high luminance of about 500 cd/m2 at 7.6 mA/cm2 and is able to control by gate voltage as low as a few volts, respectively. The crystal structures of the ZnO films as a function of Ar/O II flow ratio and the basic characteristics of the thin film transistor (TFT) and SIT depending on the ZnO sputtering conditions are investigated. The results obtained here show that the OLET using ZnO film is a suitable element for flexible sheet displays.

Magnetic Vortex Based Transistor Operations

PubMed Central

Kumar, D.; Barman, S.; Barman, A.

2014-01-01

Transistors constitute the backbone of modern day electronics. Since their advent, researchers have been seeking ways to make smaller and more efficient transistors. Here, we demonstrate a sustained amplification of magnetic vortex core gyration in coupled two and three vortices by controlling their relative core polarities. This amplification is mediated by a cascade of antivortex solitons travelling through the dynamic stray field. We further demonstrated that the amplification can be controlled by switching the polarity of the middle vortex in a three vortex sequence and the gain can be controlled by the input signal amplitude. An attempt to show fan–out operation yielded gain for one of the symmetrically placed branches which can be reversed by switching the core polarity of all the vortices in the network. The above observations promote the magnetic vortices as suitable candidates to work as stable bipolar junction transistors (BJT). PMID:24531235

Extreme Temperature Performance of Automotive-Grade Small Signal Bipolar Junction Transistors

NASA Technical Reports Server (NTRS)

Boomer, Kristen; Damron, Benny; Gray, Josh; Hammoud, Ahmad

2018-01-01

Electronics designed for space exploration missions must display efficient and reliable operation under extreme temperature conditions. For example, lunar outposts, Mars rovers and landers, James Webb Space Telescope, Europa orbiter, and deep space probes represent examples of missions where extreme temperatures and thermal cycling are encountered. Switching transistors, small signal as well as power level devices, are widely used in electronic controllers, data instrumentation, and power management and distribution systems. Little is known, however, about their performance in extreme temperature environments beyond their specified operating range; in particular under cryogenic conditions. This report summarizes preliminary results obtained on the evaluation of commercial-off-the-shelf (COTS) automotive-grade NPN small signal transistors over a wide temperature range and thermal cycling. The investigations were carried out to establish a baseline on functionality of these transistors and to determine suitability for use outside their recommended temperature limits.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Fabrication and characterization of the organic rectifying junctions by electrolysis

NASA Astrophysics Data System (ADS)

Karimov, Khasan; Ahmad, Zubair; Ali, Rashid; Noor, Adnan; Akmal, M.; Najeeb, M. A.; Shakoor, R. A.

2017-08-01

Unlike the conventional solution processable deposition techniques, in this study, we propose a novel and economical method for the fabrication of organic rectifying junctions. The solutions of the orange dye, copper phthalocyanine and NaCl were deposited on the surface-type interdigitated silver electrodes using electrolysis technique. Using the current-voltage (I-V) characteristics, the presence of rectifying behavior in the samples has been confirmed. This phenomenon, in principle, can be used for fabrication of the diodes, transistors and memory devices.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

A Single-Material Logical Junction Based on 2D Crystal PdS2.

PubMed

Ghorbani-Asl, Mahdi; Kuc, Agnieszka; Miró, Pere; Heine, Thomas

2016-02-03

A single-material logical junction with negligible contact resistance is designed by exploiting quantum-confinement effects in 1T PdS2 . The metallic bilayer serves as electrodes for the semiconducting channel monolayer, avoiding contact resistance. Heat dissipation is then governed by tunnel loss, which becomes negligible at channel lengths larger than 2.45 nm. This value marks the integration limit for a conventional 2D transistor. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A model for phase noise generation in amplifiers.

PubMed

Tomlin, T D; Fynn, K; Cantoni, A

2001-11-01

In this paper, a model is presented for predicting the phase modulation (PM) and amplitude modulation (AM) noise in bipolar junction transistor (BJT) amplifiers. The model correctly predicts the dependence of phase noise on the signal frequency (at a particular carrier offset frequency), explains the noise shaping of the phase noise about the signal frequency, and shows the functional dependence on the transistor parameters and the circuit parameters. Experimental studies on common emitter (CE) amplifiers have been used to validate the PM noise model at carrier frequencies between 10 and 100 MHz.

Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

NASA Technical Reports Server (NTRS)

Chen, Dakai; Ladbury Raymond; LaBel, Kenneth; Topper, Alyson; Ladbury, Raymond; Triggs, Brian; Kazmakites, Tony

2012-01-01

We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.;

Contact Metallization and Packaging Technology Development for SiC Bipolar Junction Transistors, PiN Diodes, and Schottky Diodes Designed for Long-Term Operations at 350degreeC

DTIC Science & Technology

2006-05-01

switches that are used in power conditioning systems. Silicon carbide diodes are now available commercially, and transistors (JEFETs, MOSFETs, IGBTs ...in UHP Ar for 60s in a rapid thermal annealing (RTA) furnace to achieve a low contact resistance. Following the RTA step, photolithography was...with 20μm Au is shown in Figure 3-4. The brazing process was performed with an SST 3150 high vacuum furnace . The 3150 utilizes an oil-free roughing

Superlattice structure modeling and simulation of High Electron Mobility Transistor for improved performance

NASA Astrophysics Data System (ADS)

Munusami, Ravindiran; Yakkala, Bhaskar Rao; Prabhakar, Shankar

2013-12-01

Magnetic tunnel junction were made by inserting the magnetic materials between the source, channel and the drain of the High Electron Mobility Transistor (HEMT) to enhance the performance. Material studio software package was used to design the superlattice layers. Different cases were analyzed to optimize the performance of the device by placing the magnetic material at different positions of the device. Simulation results based on conductivity reveals that the device has a very good electron transport due to the magnetic materials and will amplify very low frequency signals.

An investigation of the SNS Josephson junction as a three-terminal device. Ph.D. Thesis

NASA Technical Reports Server (NTRS)

Meissner, H.; Prans, G. P.

1973-01-01

A particular phenomenon of the SNS Josephson junction was investigated; i.e., control by a current entering the normal region and leaving through one of the superconducting regions. The effect of the control current on the junction was found to be dependent upon the ration of the resistances of the two halves of the N layer. A low frequency, lumped, nonlinear model was proposed to describe the electrical characteristics of the device, and a method was developed to plot the dynamic junction resistance as a function of junction current. The effective thermal noise temperature of the sample was determined. Small signal linearized analysis of the device suggests its use as an impedance transformer, although geometric limitations must be overcome. Linear approximation indicates that it is reciprocal and no power gain is possible. It is felt that, with suitable metallurgical and geometrical improvements, the device has promise to become a superconducting transistor.

Is there a relationship between curvature and inductance in the Josephson junction?

NASA Astrophysics Data System (ADS)

Dobrowolski, T.; Jarmoliński, A.

2018-03-01

A Josephson junction is a device made of two superconducting electrodes separated by a very thin layer of isolator or normal metal. This relatively simple device has found a variety of technical applications in the form of Superconducting Quantum Interference Devices (SQUIDs) and Single Electron Transistors (SETs). One can expect that in the near future the Josephson junction will find applications in digital electronics technology RSFQ (Rapid Single Flux Quantum) and in the more distant future in construction of quantum computers. Here we concentrate on the relation of the curvature of the Josephson junction with its inductance. We apply a simple Capacitively Shunted Junction (CSJ) model in order to find condition which guarantees consistency of this model with prediction based on the Maxwell and London equations with Landau-Ginzburg current of Cooper pairs. This condition can find direct experimental verification.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Synaptic plasticity and oscillation at zinc tin oxide/silver oxide interfaces

NASA Astrophysics Data System (ADS)

Murdoch, Billy J.; McCulloch, Dougal G.; Partridge, James G.

2017-02-01

Short-term plasticity, long-term potentiation, and pulse interval dependent plasticity learning/memory functions have been observed in junctions between amorphous zinc-tin-oxide and silver-oxide. The same junctions exhibited current-controlled negative differential resistance and when connected in an appropriate circuit, they behaved as relaxation oscillators. These oscillators produced voltage pulses suitable for device programming. Transmission electron microscopy, energy dispersive X-ray spectroscopy, and electrical measurements suggest that the characteristics of these junctions arise from Ag+/O- electromigration across a highly resistive interface layer. With memory/learning functions and programming spikes provided in a single device structure, arrays of similar devices could be used to form transistor-free neuromorphic circuits.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Dual origin of room temperature sub-terahertz photoresponse in graphene field effect transistors

NASA Astrophysics Data System (ADS)

Bandurin, D. A.; Gayduchenko, I.; Cao, Y.; Moskotin, M.; Principi, A.; Grigorieva, I. V.; Goltsman, G.; Fedorov, G.; Svintsov, D.

2018-04-01

Graphene is considered as a promising platform for detectors of high-frequency radiation up to the terahertz (THz) range due to its superior electron mobility. Previously, it has been shown that graphene field effect transistors (FETs) exhibit room temperature broadband photoresponse to incoming THz radiation, thanks to the thermoelectric and/or plasma wave rectification. Both effects exhibit similar functional dependences on the gate voltage, and therefore, it was difficult to disentangle these contributions in previous studies. In this letter, we report on combined experimental and theoretical studies of sub-THz response in graphene field-effect transistors analyzed at different temperatures. This temperature-dependent study allowed us to reveal the role of the photo-thermoelectric effect, p-n junction rectification, and plasmonic rectification in the sub-THz photoresponse of graphene FETs.

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

An Evaluation of Bipolar Junction Transistors as Dosimeter for Megavoltage Electron Beams

DOE Office of Scientific and Technical Information (OSTI.GOV)

Passos, Renan Garcia de; Vidal da Silva, Rogerio Matias; Silva, Malana Marcelina Almeida

Dosimetry is an extremely important field in medical applications of radiation and nowadays, electron beam is a good option for superficial tumor radiotherapy. Normally, the applied dose to the patient both in diagnostic and therapy must be monitored to prevent injuries and ensure the success of the treatment, therefore, we should always look for improving of the dosimetric methods. Accordingly, the aim of this work is about the use of a bipolar junction transistor (BJT) for electron beam dosimetry. After previous studies, such an electronic device can work as a dosimeter when submitted to ionizing radiation of photon beam. Actually,more » a typical BJT consists of two PN semiconductor junctions resulting in the NPN structure device, for while, and each semiconductor is named as collector (C), base (B) and emitter (E), respectively. Although the transistor effect, which corresponds to the current amplification, be accurately described by the quantum physics, one can utilize a simple concept from the circuit theory: the base current IB (input signal) is amplified by a factor of β resulting in the collector current IC (output signal) at least one hundred times greater the IB. In fact, the BJT is commonly used as a current amplifier with gain β=I{sub C}/I{sub B}, therefore, it was noticed that this parameter is altered when the device is exposed to ionizing radiation. The current gain alteration can be explained by the trap creation and the positive charges build up, beside the degradation of the lattice structure. Then, variations of the gain of irradiated transistors may justify their use as a dosimeter. Actually, the methodology is based on the measurements of the I{sub C} variations whereas I{sub B} is maintained constant. BC846 BJT type was used for dose monitoring from passive-mode measurements: evaluation of its electrical characteristic before and after irradiation procedure. Thus, IC readings were plotted as a function of the applied dose in 6 MeV electron beam from a linear accelerator, Clinac iX. The results show that this new methodology could be an alternative to study the dose in superficial tumors in radiation oncology. (authors)« less

Superconducting flux flow digital circuits

DOEpatents

Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.

1995-01-01

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

AlGaN Channel Transistors for Power Management and Distribution

NASA Technical Reports Server (NTRS)

VanHove, James M.

1996-01-01

Contained within is the Final report of a Phase 1 SBIR program to develop AlGaN channel junction field effect transistors (JFET). The report summarizes our work to design, deposit, and fabricate JFETS using molecular beam epitaxy growth AlGaN. Nitride growth is described using a RF atomic nitrogen plasma source. Processing steps needed to fabricate the device such as ohmic source-drain contacts, reactive ion etching, gate formation, and air bride fabrication are documented. SEM photographs of fabricated power FETS are shown. Recommendations are made to continue the effort in a Phase 2 Program.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

PubMed

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

Digital Storage Oscilloscopes in the Undergraduate Laboratory

ERIC Educational Resources Information Center

Kraftmakher, Yaakov

2012-01-01

Digital storage oscilloscopes (DSOs) are now easily available to undergraduate laboratories. In many cases, a DSO can replace a data-acquisition system. Seven such experiments/demonstrations are considered: (i) families of "I-V" characteristics of electronic devices (bipolar junction transistor), (ii) the "V-I" curve of a high-temperature…

Superconducting flux flow digital circuits

DOEpatents

Hietala, V.M.; Martens, J.S.; Zipperian, T.E.

1995-02-14

A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.

Greatly improved 3C-SiC p-n junction diodes grown by chemical vapor deposition

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Larkin, David J.; Starr, Jonathan E.; Powell, J. A.; Salupo, Carl S.; Matus, Lawrence G.

1993-01-01

This paper reports the fabrication and initial electrical characterization of greatly improved 3C-SiC (beta-SiC) p-n junction diodes. These diodes, which were grown on commercially available 6H-SiC substrates by chemical vapor deposition, demonstrate rectification to -200 V at room temperature, representing a fourfold improvement in reported 3C-SiC diode blocking voltage. The reverse leakage currents and saturation current densities measured on these diodes also show significant improvement compared to previously reported 3C-SiC p-n junction diodes. When placed under sufficient forward bias, the diodes emit significantly bright green-yellow light. These results should lead to substantial advancements in 3C-SiC transistor performance.

Polarization-induced Zener tunnel diodes in GaN/InGaN/GaN heterojunctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, Xiaodong; Li, Wenjun; Islam, S. M.

By the insertion of thin In{sub x}Ga{sub 1−x}N layers into Nitrogen-polar GaN p-n junctions, polarization-induced Zener tunnel junctions are studied. The reverse-bias interband Zener tunneling current is found to be weakly temperature dependent, as opposed to the strongly temperature-dependent forward bias current. This indicates tunneling as the primary reverse-bias current transport mechanism. The Indium composition in the InGaN layer is systematically varied to demonstrate the increase in the interband tunneling current. Comparing the experimentally measured tunneling currents to a model helps identify the specific challenges in potentially taking such junctions towards nitride-based polarization-induced tunneling field-effect transistors.

Europium Silicide – a Prospective Material for Contacts with Silicon

PubMed Central

Averyanov, Dmitry V.; Tokmachev, Andrey M.; Karateeva, Christina G.; Karateev, Igor A.; Lobanovich, Eduard F.; Prutskov, Grigory V.; Parfenov, Oleg E.; Taldenkov, Alexander N.; Vasiliev, Alexander L.; Storchak, Vyacheslav G.

2016-01-01

Metal-silicon junctions are crucial to the operation of semiconductor devices: aggressive scaling demands low-resistive metallic terminals to replace high-doped silicon in transistors. It suggests an efficient charge injection through a low Schottky barrier between a metal and Si. Tremendous efforts invested into engineering metal-silicon junctions reveal the major role of chemical bonding at the interface: premier contacts entail epitaxial integration of metal silicides with Si. Here we present epitaxially grown EuSi2/Si junction characterized by RHEED, XRD, transmission electron microscopy, magnetization and transport measurements. Structural perfection leads to superb conductivity and a record-low Schottky barrier with n-Si while an antiferromagnetic phase invites spin-related applications. This development opens brand-new opportunities in electronics. PMID:27211700

Europium Silicide - a Prospective Material for Contacts with Silicon.

PubMed

Averyanov, Dmitry V; Tokmachev, Andrey M; Karateeva, Christina G; Karateev, Igor A; Lobanovich, Eduard F; Prutskov, Grigory V; Parfenov, Oleg E; Taldenkov, Alexander N; Vasiliev, Alexander L; Storchak, Vyacheslav G

2016-05-23

Metal-silicon junctions are crucial to the operation of semiconductor devices: aggressive scaling demands low-resistive metallic terminals to replace high-doped silicon in transistors. It suggests an efficient charge injection through a low Schottky barrier between a metal and Si. Tremendous efforts invested into engineering metal-silicon junctions reveal the major role of chemical bonding at the interface: premier contacts entail epitaxial integration of metal silicides with Si. Here we present epitaxially grown EuSi2/Si junction characterized by RHEED, XRD, transmission electron microscopy, magnetization and transport measurements. Structural perfection leads to superb conductivity and a record-low Schottky barrier with n-Si while an antiferromagnetic phase invites spin-related applications. This development opens brand-new opportunities in electronics.

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

PubMed

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Magnetometry with Low-Resistance Proximity Josephson Junction

NASA Astrophysics Data System (ADS)

Jabdaraghi, R. N.; Peltonen, J. T.; Golubev, D. S.; Pekola, J. P.

2018-06-01

We characterize a niobium-based superconducting quantum interference proximity transistor (Nb-SQUIPT) and its key constituent formed by a Nb-Cu-Nb SNS weak link. The Nb-SQUIPT and SNS devices are fabricated simultaneously in two separate lithography and deposition steps, relying on Ar ion cleaning of the Nb contact surfaces. The quality of the Nb-Cu interface is characterized by measuring the temperature-dependent equilibrium critical supercurrent of the SNS junction. In the Nb-SQUIPT device, we observe a maximum flux-to-current transfer function value of about 55 nA/Φ_0 in the sub-gap regime of bias voltages. This results in suppression of power dissipation down to a few fW. Low-bias operation of the device with a relatively low probe junction resistance decreases the dissipation by up to two orders of magnitude compared to a conventional device based on an Al-Cu-Al SNS junction and an Al tunnel probe (Al-SQUIPT).

Theoretical evaluation of two dimensional electron gas characteristics of quaternary AlxInyGa1-x-yN/GaN hetero-junctions

NASA Astrophysics Data System (ADS)

Rahbardar Mojaver, Hassan; Manouchehri, Farzin; Valizadeh, Pouya

2016-04-01

The two dimensional electron gas (2DEG) characteristics of gated metal-face wurtzite AlInGaN/GaN hetero-junctions including positions of subband energy levels, fermi energy level, and the 2DEG concentration as functions of physical and compositional properties of the hetero-junction (i.e., barrier thickness and metal mole-fractions) are theoretically evaluated using the variational method. The calculated values of the 2DEG concentration are in good agreement with the sparsely available experimental data reported in the literature. According to our simulation results, a considerable shift in the positive direction of threshold voltage of AlInGaN/GaN hetero-junction field-effect transistors can be achieved by engineering both the spontaneous and the piezoelectric polarizations using a quaternary AlInGaN barrier-layer of appropriate mole-fractions.

A pattern recognition approach to transistor array parameter variance

NASA Astrophysics Data System (ADS)

da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

2018-06-01

The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yeluri, Ramya, E-mail: ramyay@ece.ucsb.edu; Lu, Jing; Keller, Stacia

2015-05-04

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm{sup 2}) and low ON-resistance (0.4 mΩ cm{sup 2}) are demonstrated. Non-planar selective area regrowth is identified as the limiting factormore » to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities.« less

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

NASA Astrophysics Data System (ADS)

Jin, Liu; Yongguang, Chen; Zhiliang, Tan; Jie, Yang; Xijun, Zhang; Zhenxing, Wang

2011-10-01

Electrostatic discharge (ESD) phenomena involve both electrical and thermal effects, and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability. Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors (BJTs) under ESD conditions has been investigated theoretically and experimentally. 100 samples have been tested for multiple pulses until a failure occurred. Meanwhile, the distributions of electric field, current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici. There is a good agreement between the simulated results and failure analysis. In the case of a thermal couple, the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects. The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure. When the ESD level increased to 1.3 kV, the collector-base junction has been burnt out first. The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic. In addition, fatigue phenomena are observed during ESD testing, with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.

Prognostics of Power MOSFET

NASA Technical Reports Server (NTRS)

Celaya, Jose Ramon; Saxena, Abhinav; Vashchenko, Vladislay; Saha, Sankalita; Goebel, Kai Frank

2011-01-01

This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and Gaussian process regression to perform prognostics. The approach is validated with experiments on 100V power MOSFETs. The failure mechanism for the stress conditions is determined to be die-attachment degradation. Change in ON-state resistance is used as a precursor of failure due to its dependence on junction temperature. The experimental data is augmented with a finite element analysis simulation that is based on a two-transistor model. The simulation assists in the interpretation of the degradation phenomena and SOA (safe operation area) change.

Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

NASA Technical Reports Server (NTRS)

Zoutendyk, John A. (Inventor)

1991-01-01

Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

Rylene and related diimides for organic electronics.

PubMed

Zhan, Xiaowei; Facchetti, Antonio; Barlow, Stephen; Marks, Tobin J; Ratner, Mark A; Wasielewski, Michael R; Marder, Seth R

2011-01-11

Organic electron-transporting materials are essential for the fabrication of organic p-n junctions, photovoltaic cells, n-channel field-effect transistors, and complementary logic circuits. Rylene diimides are a robust, versatile class of polycyclic aromatic electron-transport materials with excellent thermal and oxidative stability, high electron affinities, and, in many cases, high electron mobilities; they are, therefore, promising candidates for a variety of organic electronics applications. In this review, recent developments in the area of high-electron-mobility diimides based on rylenes and related aromatic cores, particularly perylene- and naphthalene-diimide-based small molecules and polymers, for application in high-performance organic field-effect transistors and photovoltaic cells are summarized and analyzed.

Raman Channel Temperature Measurement of SiC MESFET as a Function of Ambient Temperature and DC Power

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Eldridge, Jeffrey J.; Krainsky, Isay L.

2009-01-01

Raman spectroscopy is used to measure the junction temperature of a Cree SiC MESFET as a function of the ambient temperature and DC power. The carrier temperature, which is approximately equal to the ambient temperature, is varied from 25 C to 450 C, and the transistor is biased with VDS=10V and IDS of 50 mA and 100 mA. It is shown that the junction temperature is approximately 52 and 100 C higher than the ambient temperature for the DC power of 500 and 1000 mW, respectively.

Animation Based Learning of Electronic Devices

ERIC Educational Resources Information Center

Gero, Aharon; Zoabi, Wishah; Sabag, Nissim

2014-01-01

Two-year college teachers face great difficulty when they teach the principle of operation of the bipolar junction transistor--a subject which forms the basis for electronics studies. The difficulty arises from both the complexity of the device and by the lack of adequate scientific background among the students. We, therefore, developed a unique…

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

PubMed

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-01-01

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Theoretical calculation of performance enhancement in lattice-matched SiGeSn/GeSn p-channel tunneling field-effect transistor with type-II staggered tunneling junction

NASA Astrophysics Data System (ADS)

Wang, Hongjuan; Han, Genquan; Wang, Yibo; Peng, Yue; Liu, Yan; Zhang, Chunfu; Zhang, Jincheng; Hu, Shengdong; Hao, Yue

2016-04-01

In this work, a lattice-matched SiGeSn/GeSn heterostructure p-channel tunneling field-effect transistor (hetero-PTFET) with a type-II staggered tunneling junction (TJ) is investigated theoretically. Lattice matching and type-II band alignment at the Γ-point is obtained at the SiGeSn/GeSn interface by tuning Sn and Si compositions. A steeper subthreshold swing (SS) and a higher on state current (I ON) are demonstrated in SiGeSn/GeSn hetero-PTFET than in GeSn homo-PTFET. Si0.31Ge0.49Sn0.20/Ge0.88Sn0.12 hetero-PTFET achieves a 2.3-fold higher I ON than Ge0.88Sn0.12 homo-PTFET at V DD of 0.3 V. Hetero-PTFET achieves a more abrupt hole profile and a higher carrier density near TJ than the homo-PTFET, which contributes to the significantly enhanced band-to-band tunneling (BTBT) rate and tunneling current in hetero-PTFET.

Dynamics of Bloch oscillating transistor near bifurcation threshold and its applicability for common mode rejection capability of a differential pair BOT

NASA Astrophysics Data System (ADS)

Sarkar, Jayanta; Puska, Antti; Hassel, Juha; Hakonen, Pertti

2014-03-01

Bloch oscillating transistor (BOT) is mesoscopic current amplier based on a combination of a Josephson junction or a squid connected with a large resistor and a NIS junction. We have studied the dynamics of BOT near the bifurcation threshold. This is an important feature for an amplifier as this can be utilized to improve its performance characteristics. We have measured the I - V characteristics of the BOT with different base currents (IB) over a wide range of Josephson coupling energies (EJ) . The current gain (β) is found to be increasing with increasing IB and eventually diverging. We have found a record large β = 50 in our experiment. In order to determine the common mode rejection ratio (CMRR) of a differential pair BOT we have used two BOTs fabricated on the same chip. The common mode port is connected to the bases of the two BOTs and fed with varying voltages; simultaneously emitter currents of the two BOTs are recorded. In our experiment we found a 20dB of CMRR.

Ultra-low switching energy and scaling in electric-field-controlled nanoscale magnetic tunnel junctions with high resistance-area product

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grezes, C.; Alzate, J. G.; Cai, X.

2016-01-04

We report electric-field-induced switching with write energies down to 6 fJ/bit for switching times of 0.5 ns, in nanoscale perpendicular magnetic tunnel junctions (MTJs) with high resistance-area product and diameters down to 50 nm. The ultra-low switching energy is made possible by a thick MgO barrier that ensures negligible spin-transfer torque contributions, along with a reduction of the Ohmic dissipation. We find that the switching voltage and time are insensitive to the junction diameter for high-resistance MTJs, a result accounted for by a macrospin model of purely voltage-induced switching. The measured performance enables integration with same-size CMOS transistors in compact memorymore » and logic integrated circuits.« less

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-11-01

Tunnel field-effect transistor (TFET) is very attractive in replacing a MOSFET, particularly for low-power nanoelectronic circuits. The U-shaped channel TFET (U-TFET) was proposed to improve the drain-source current with a reduced footprint. In this work, the impact of the source height (HS) on the characteristic of the U-shaped channel tunnel field-effect transistor (U-TFET) is investigated by using TCAD simulation. It is found that with a fixed gate height (HG) the drain-source current has a negative correlation with HS. This is because when the gate region is deeper than the source region, the electric field near the corner of the tunneling junction can be enhanced and the tunneling rate is increased. When HS becomes very thin, the drain-source current is limited by the source region volume. The U-TFET with an n+ pocket is also studied and the same trend is observed.

High concentration effects of neutral-potential-well interface traps on recombination dc current-voltage lineshape in metal-oxide-silicon transistors

NASA Astrophysics Data System (ADS)

Chen, Zuhui; Jie, Bin B.; Sah, Chih-Tang

2008-11-01

Steady-state Shockley-Read-Hall kinetics is employed to explore the high concentration effect of neutral-potential-well interface traps on the electron-hole recombination direct-current current-voltage (R-DCIV) properties in metal-oxide-silicon field-effect transistors. Extensive calculations include device parameter variations in neutral-trapping-potential-well electron interface-trap density NET (charge states 0 and -1), dopant impurity concentration PIM, oxide thickness Xox, forward source/drain junction bias VPN, and transistor temperature T. It shows significant distortion of the R-DCIV lineshape by the high concentrations of the interface traps. The result suggests that the lineshape distortion observed in past experiments, previously attributed to spatial variation in surface impurity concentration and energy distribution of interface traps in the silicon energy gap, can also arise from interface-trap concentration along surface channel region.

6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.;

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-low-power applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.

Check that JFET! Easy-to-Build Tester Makes It Simple

ERIC Educational Resources Information Center

Harman, Charles

2008-01-01

This article describes an activity that will allow students to learn how to make a junction field effect transistor (JFET) checker. Most electronics students do not have the experience or knowledge that it takes to recognize whether a JFET is operating normally, and both instructors and students will find having the means to check the operation of…

Flexible Graphene Transistor Architecture for Optical Sensor Technology

NASA Astrophysics Data System (ADS)

Ordonez, Richard Christopher

The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional investigation demonstrated PN junction operation and the successful integration of the proposed architecture into an optoelectronic application with the use of semiconductor quantum dots in contact with the graphene material that acted as optical absorbers to increase detector gain. Applications that can benefit from such technology advancement include Nano-satellites (Nanosat), Underwater autonomous vehicles (UAV), and airborne platforms in which flexibility and sensitivity are critical parameters that must be optimized to increase mission duration and range.

Multimode Silicon Nanowire Transistors

PubMed Central

2014-01-01

The combined capabilities of both a nonplanar design and nonconventional carrier injection mechanisms are subject to recent scientific investigations to overcome the limitations of silicon metal oxide semiconductor field effect transistors. In this Letter, we present a multimode field effect transistors device using silicon nanowires that feature an axial n-type/intrinsic doping junction. A heterostructural device design is achieved by employing a self-aligned nickel-silicide source contact. The polymorph operation of the dual-gate device enabling the configuration of one p- and two n-type transistor modes is demonstrated. Not only the type but also the carrier injection mode can be altered by appropriate biasing of the two gate terminals or by inverting the drain bias. With a combined band-to-band and Schottky tunneling mechanism, in p-type mode a subthreshold swing as low as 143 mV/dec and an ON/OFF ratio of up to 104 is found. As the device operates in forward bias, a nonconventional tunneling transistor is realized, enabling an effective suppression of ambipolarity. Depending on the drain bias, two different n-type modes are distinguishable. The carrier injection is dominated by thermionic emission in forward bias with a maximum ON/OFF ratio of up to 107 whereas in reverse bias a Schottky tunneling mechanism dominates the carrier transport. PMID:25303290

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Beheim, Glenn M.; Okojie, Robert S.; Chang, Carl W.; Meredith, Roger D.; Ferrier, Terry L.; Evans, Laura J.; Krasowski, Michael J.;

Contact resistance reduction of ZnO thin film transistors (TFTs) with saw-shaped electrode.

PubMed

Park, Woojin; Shaikh, Sohail F; Min, Jung-Wook; Lee, Sang Kyung; Lee, Byoung Hun; Hussain, Muhammad M

2018-08-10

We report on a saw-shaped electrode architecture ZnO thin film transistor (TFT), which effectively increases the channel width. The contact line of the saw-shaped electrode is almost twice as long at the contact metal/ZnO channel junction. We experimentally observed an enhancement in the output drive current by 50% and a reduction in the contact resistance by over 50%, when compared to a typically shaped electrode ZnO TFT consuming the same chip area. This performance enhancement is attributed to the extension of the channel width. This technique can contribute to device performance enhancement, and in particular reduce the contact resistance, which is a serious challenge.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Technical Reports Server (NTRS)

Pavlidis, Dimitris

1991-01-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

NASA Astrophysics Data System (ADS)

Pavlidis, Dimitris

1991-02-01

The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

Lateral carrier diffusion and current gain in terahertz InGaAs/InP double-heterojunction bipolar transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chiang, Han-Wei; Rode, Johann C.; Choudhary, Prateek

2014-01-21

The DC current gain in In{sub 0.53}Ga{sub 0.47}As/InP double-heterojunction bipolar transistors is computed based on a drift-diffusion model, and is compared with experimental data. Even in the absence of other scaling effects, lateral diffusion of electrons to the base Ohmic contacts causes a rapid reduction in DC current gain as the emitter junction width and emitter-base contact spacing are reduced. The simulation and experimental data are compared in order to examine the effect of carrier lateral diffusion on current gain. The impact on current gain due to device scaling and approaches to increase current gain are discussed.

Transparent indium-tin oxide/indium-gallium-zinc oxide Schottky diodes formed by gradient oxygen doping

NASA Astrophysics Data System (ADS)

Ho, Szuheng; Yu, Hyeonggeun; So, Franky

2017-11-01

Amorphous InGaZnO (a-IGZO) is promising for transparent electronics due to its high carrier mobility and optical transparency. However, most metal/a-IGZO junctions are ohmic due to the Fermi-level pinning at the interface, restricting their device applications. Here, we report that indium-tin oxide/a-IGZO Schottky diodes can be formed by gradient oxygen doping in the a-IGZO layer that would otherwise form an ohmic contact. Making use of back-to-back a-IGZO Schottky junctions, a transparent IGZO permeable metal-base transistor is also demonstrated with a high common-base gain.

Binding configurations and intramolecular strain in single-molecule devices.

PubMed

Rascón-Ramos, Habid; Artés, Juan Manuel; Li, Yuanhui; Hihath, Joshua

2015-05-01

The development of molecular-scale electronic devices has made considerable progress over the past decade, and single-molecule transistors, diodes and wires have all been demonstrated. Despite this remarkable progress, the agreement between theoretically predicted conductance values and those measured experimentally remains limited. One of the primary reasons for these discrepancies lies in the difficulty to experimentally determine the contact geometry and binding configuration of a single-molecule junction. In this Article, we apply a small-amplitude, high-frequency, sinusoidal mechanical signal to a series of single-molecule devices during junction formation and breakdown. By measuring the current response at this frequency, it is possible to determine the most probable binding and contact configurations for the molecular junction at room temperature in solution, and to obtain information about how an applied strain is distributed within the molecular junction. These results provide insight into the complex configuration of single-molecule devices, and are in excellent agreement with previous predictions from theoretical models.

Strong electroluminescence from direct band and defects in Ge n+/p shallow junctions at room temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lin, Guangyang; Li, Cheng, E-mail: lich@xmu.edu.cn; Chen, Chaowen

2016-05-09

Strong room temperature electroluminescence with two emission peaks at around 0.786 eV and 0.747 eV from Ge n+/p shallow junctions was reported. The peak at around 0.786 eV comes from direct band luminescence (DBL) in n + Ge regions, while the peak fixing at 0.747 eV is resulted from defects induced by ion implantation. Heavy n-type doping in Ge renders realization of strong defect-related luminescence (DRL) feasible. The peak intensity ratio of DRL/DBL decreases with increase of injection current since more electrons are filled in Γ valley. Above all, the Ge n+/p shallow junction is fully compatible with the source and drain in Gemore » metal-oxide-semiconductor field effect transistors.« less

Noise of a superconducting magnetic flux sensor based on a proximity Josephson junction.

PubMed

Jabdaraghi, R N; Golubev, D S; Pekola, J P; Peltonen, J T

2017-08-14

We demonstrate simultaneous measurements of DC transport properties and flux noise of a hybrid superconducting magnetometer based on the proximity effect (superconducting quantum interference proximity transistor, SQUIPT). The noise is probed by a cryogenic amplifier operating in the frequency range of a few MHz. In our non-optimized device, we achieve minimum flux noise ~4 μΦ 0 /Hz 1/2 , set by the shot noise of the probe tunnel junction. The flux noise performance can be improved by further optimization of the SQUIPT parameters, primarily minimization of the proximity junction length and cross section. Furthermore, the experiment demonstrates that the setup can be used to investigate shot noise in other nonlinear devices with high impedance. This technique opens the opportunity to measure sensitive magnetometers including SQUIPT devices with very low dissipation.

Development of a low-noise amplifier for neutron detection in harsh environment

NASA Astrophysics Data System (ADS)

Angelone, M.; Cardarelli, R.; Paolozzi, L.; Pillon, M.

2014-10-01

A fast matching charge amplifier for neutron spectroscopy in harsh environment has been developed and tested at the JET Tokamak. This front-end circuit is capable to operate at a distance up to 100 meters from a sensor without increasing its equivalent noise charge. Further improvements are possible by exploiting the intrinsic performance of silicon-germanium bipolar junction transistors.

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

NASA Astrophysics Data System (ADS)

Kim, Jungsik; Oh, Hyeongwan; Kim, Jiwon; Meyyappan, M.; Lee, Jeong-Soo

2017-02-01

Effects of using asymmetric channel thickness in tunneling field-effect transistors (TFET) are investigated in sub-50 nm channel regime using two-dimensional (2D) simulations. As the thickness of the source side becomes narrower in narrow-source wide-drain (NSWD) TFETs, the threshold voltage (V th) and the subthreshold swing (SS) decrease due to enhanced gate controllability of the source side. The narrow source thickness can make the band-to-band tunneling (BTBT) distance shorter and induce much higher electric field near the source junction at the on-state condition. In contrast, in a TFET with wide-source narrow-drain (WSND), the SS shows almost constant values and the V th slightly increases with narrowing thickness of the drain side. In addition, the ambipolar current can rapidly become larger with smaller thickness on the drain side because of the shorter BTBT distance and the higher electric-field at the drain junction. The on-current of the asymmetric channel TFET is lower than that of conventional TFETs due to the volume limitation of the NSWD TFET and high series resistance of the WSND TFET. The on-current is almost determined by the channel thickness of the source side.

Highly flexible electronics from scalable vertical thin film transistors.

PubMed

Liu, Yuan; Zhou, Hailong; Cheng, Rui; Yu, Woojong; Huang, Yu; Duan, Xiangfeng

2014-03-12

Flexible thin-film transistors (TFTs) are of central importance for diverse electronic and particularly macroelectronic applications. The current TFTs using organic or inorganic thin film semiconductors are usually limited by either poor electrical performance or insufficient mechanical flexibility. Here, we report a new design of highly flexible vertical TFTs (VTFTs) with superior electrical performance and mechanical robustness. By using the graphene as a work-function tunable contact for amorphous indium gallium zinc oxide (IGZO) thin film, the vertical current flow across the graphene-IGZO junction can be effectively modulated by an external gate potential to enable VTFTs with a highest on-off ratio exceeding 10(5). The unique vertical transistor architecture can readily enable ultrashort channel devices with very high delivering current and exceptional mechanical flexibility. With large area graphene and IGZO thin film available, our strategy is intrinsically scalable for large scale integration of VTFT arrays and logic circuits, opening up a new pathway to highly flexible macroelectronics.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

PubMed

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Correlated full-field and pointwise temporally resolved measurements of thermomechanical stress inside an operating power transistor

NASA Astrophysics Data System (ADS)

Borza, Dan N.; Gautrelet, Christophe

2015-01-01

The paper describes a measurement system based on time-resolved speckle interferometry, able to record long series of thermally induced full-field deformation maps of die and wire bonds inside an operating power transistor. The origin of the deformation is the transistor heating during its normal operation. The full-field results consist in completely unwrapped deformation maps for out-of-plane displacements greater than 14 μm, with nanometer resolution, in presence of discontinuities due to structural and material inhomogeneity. These measurements are synchronized with the measurement of heatsink temperature and of base-emitter junction temperature, so as to provide data related to several interacting physical parameters. The temporal histories of the displacement are also accessible for any point. They are correlated with the thermal and electrical time series. Mechanical full-field curvatures may also be estimated, making these measurements useful for inspecting physical origins of thermomechanical stresses and for interacting with numerical models used in reliability-related studies.

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.

PubMed

Dell' Anna, Francesco; Dong, Tao; Li, Ping; Wen, Yumei; Azadmehr, Mehdi; Casu, Mario; Berg, Yngvar

2018-04-17

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

Improved performance of graphene transistors by strain engineering.

PubMed

Nguyen, V Hung; Nguyen, Huy-Viet; Dollfus, P

2014-04-25

By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.

Multicontrol Over Graphene–Molecule Hetereojunctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yun-Peng; Fry, James N.; Cheng, Hai-Ping

The vertical configuration is a powerful tool recently developed experimentally to investigate field effects in quasi two-dimensional systems. Prototype graphene-based vertical tunneling transistors can achieve an extraordinary control over current density utilizing gate voltages. In this work, we study theoretically vertical tunneling junctions that consist of a monolayer of photoswitchable aryl azobenzene molecules sandwiched between two sheets of graphene. Azobenzene molecules transform between trans and cis conformations upon photoexcitation, thus adding a second knob that enhances the control over physical properties of the junction. Using first-principles methods within the density functional framework, we perform simulations with the inclusion of fieldmore » effects for both trans and cis configurations. Lastly, we find that the interference of interface states resulting from molecule–graphene interactions at the Fermi energy introduces a dual-peak pattern in the transmission functions and dominates the transport properties of gate junctions, shedding new light on interfacial processes.« less

Vertical versus Lateral Two-Dimensional Heterostructures: On the Topic of Atomically Abrupt p/n-Junctions.

PubMed

Zhou, Ruiping; Ostwal, Vaibhav; Appenzeller, Joerg

2017-08-09

The key appeal of two-dimensional (2D) materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene for electronic applications certainly lies in their atomically thin nature that offers opportunities for devices beyond conventional transistors. It is also this property that makes them naturally suited for a type of integration that is not possible with any three-dimensional (3D) material, that is, forming heterostructures by stacking dissimilar 2D materials together. Recently, a number of research groups have reported on the formation of atomically sharp p/n-junctions in various 2D heterostructures that show strong diode-type rectification. In this article, we will show that truly vertical heterostructures do exhibit much smaller rectification ratios and that the reported results on atomically sharp p/n-junctions can be readily understood within the framework of the gate and drain voltage response of Schottky barriers that are involved in the lateral transport.

Multicontrol Over Graphene–Molecule Hetereojunctions

DOE PAGES

Wang, Yun-Peng; Fry, James N.; Cheng, Hai-Ping

2017-09-15

The vertical configuration is a powerful tool recently developed experimentally to investigate field effects in quasi two-dimensional systems. Prototype graphene-based vertical tunneling transistors can achieve an extraordinary control over current density utilizing gate voltages. In this work, we study theoretically vertical tunneling junctions that consist of a monolayer of photoswitchable aryl azobenzene molecules sandwiched between two sheets of graphene. Azobenzene molecules transform between trans and cis conformations upon photoexcitation, thus adding a second knob that enhances the control over physical properties of the junction. Using first-principles methods within the density functional framework, we perform simulations with the inclusion of fieldmore » effects for both trans and cis configurations. Lastly, we find that the interference of interface states resulting from molecule–graphene interactions at the Fermi energy introduces a dual-peak pattern in the transmission functions and dominates the transport properties of gate junctions, shedding new light on interfacial processes.« less

Performance enhancement of Ge-on-Insulator tunneling FETs with source junctions formed by low-energy BF2 ion implantation

NASA Astrophysics Data System (ADS)

Katoh, Takumi; Matsumura, Ryo; Takaguchi, Ryotaro; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

To clarify the process of formation of source regions of high-performance Ge n-channel tunneling field-effect transistors (TFETs), p+-n junctions formed by low-energy ion implantation (I/I) of BF2 atoms are characterized. Here, the formation of p+-n junctions with steep B profiles and low junction leakage is a key issue. The steepness of 5.7 nm/dec in profiles of B implanted into Ge is obtained for BF2 I/I at 3 keV with a dose of 4 × 1014 cm-2. Ge-on-insulator (GOI) n-TFETs with the source tunnel junctions formed by low-energy B and BF2 I/I are fabricated on GOI substrates and the device operation is confirmed. Although the performance at room temperature is significantly degraded by the source junction leakage current, an I on/I off ratio of 105 and the minimum sub-threshold swing (S.S.) of 130 mV/dec are obtained at 10 K. It is found that GOI n-TFETs with steeper B profiles formed by BF2 I/I have led to higher on current and a lower sub-threshold slope, demonstrating the effectiveness of steep B profiles in enhancing the GOI TFET performance.

Ge-on-insulator tunneling FET with abrupt source junction formed by utilizing snowplow effect of NiGe

NASA Astrophysics Data System (ADS)

Matsumura, Ryo; Katoh, Takumi; Takaguchi, Ryotaro; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Tunneling field-effect transistors (TFETs) attract much attention for use in realizing next-generation low-power processors. In particular, Ge-on-insulator (GOI) TFETs are expected to realize low power operation with a high on-current/off-current (I on/I off) ratio, owing to their narrow bandgap. Here, to improve the performance of GOI-TFETs, a source junction with a high doping concentration and an abrupt impurity profile is essential. In this study, a snowplow effect of NiGe combined with low-energy BF2 + implantation has been investigated to realize an abrupt p+/n Ge junction for GOI n-channel TFETs. By optimizing the Ni thickness to form NiGe (thickness: 4 nm), an abrupt junction with a B profile abruptness of ˜5 nm/dec has been realized with a high doping concentration of around 1021 cm-3. The operation of GOI n-TFETs with this source junction having the abrupt B profile has been demonstrated, and the improvement of TFET properties such as the I on/I off ratio from 311 to 743 and the subthreshold slope from 368 to 239 mV/dec has been observed. This junction formation technology is attractive for enhancing the TFET performance.

Carbon reactivation kinetics in the base of heterojunction GaInP-GaAs bipolar transistors

NASA Astrophysics Data System (ADS)

Mimila-Arroyo, J.; Bland, S. W.; Chevallier, J.

2002-05-01

The reactivation kinetics of carbon acceptors in the base region of GaInP/GaAs heterojunction bipolar transistors was studied. The reactivation was achieved by ex situ thermal annealing, through a multistage annealing experiment where the carrier concentration was monitored at each stage. Results indicate that carbon reactivation follows a first-order kinetics process in which the activation energy appears to be the sum of the energy needed to debond the hydrogen from the carbon-hydrogen complex, and the energy necessary to overcome the electrostatic junction barrier. The reactivation constant is thermally activated with an activation energy of 2.83 eV and an attempt frequency of 1.2×1013 s-1.

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

PubMed Central

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-01-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits. PMID:27491391

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

NASA Astrophysics Data System (ADS)

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal.

PubMed

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-05

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature 'prototype' PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

Understanding channel and contact effects on transport in 1-dimensional nanotransistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swartzentruber, Brian S.; Delker, Collin James; Yoo, Jinkyoung

Nanowire transistors are generally formed by metal contacts to a uniformly doped nanowire. The transistor can be modeled as a series combination of resistances from both the channel and the contacts. In this study, a simple model is proposed consisting of a resistive channel in series with two Schottky metal-semiconductor contacts modeled using the WKB approximation. This model captures several phenomena commonly observed in nanowire transistor measurements, including the mobility as a function of gate potential, mobility reduction with respect to bulk mobility, and non-linearities in output characteristics. For example, the maximum measured mobility as a function of gate voltagemore » in a nanowire transistor can be predicted based on the semiconductor bulk mobility in addition to barrier height and other properties of the contact. The model is then extended to nanowires with axial p-n junctions having an inde- pendent gate over each wire segment by splitting the channel resistance into a series component for each doping segment. Finally, the contact-channel model is applied to low-frequency noise analysis in nanowire devices, where the noise can be generated in both the channel and the contacts. Because contacts play a major, yet often neglected, role in nanowire transistor operation, they must be accounted for in order to extract meaningful parameters from I-V and noise measurements.« less

A Single-Level Tunnel Model to Account for Electrical Transport through Single Molecule- and Self-Assembled Monolayer-based Junctions

PubMed Central

Garrigues, Alvar R.; Yuan, Li; Wang, Lejia; Mucciolo, Eduardo R.; Thompon, Damien; del Barco, Enrique; Nijhuis, Christian A.

2016-01-01

We present a theoretical analysis aimed at understanding electrical conduction in molecular tunnel junctions. We focus on discussing the validity of coherent versus incoherent theoretical formulations for single-level tunneling to explain experimental results obtained under a wide range of experimental conditions, including measurements in individual molecules connecting the leads of electromigrated single-electron transistors and junctions of self-assembled monolayers (SAM) of molecules sandwiched between two macroscopic contacts. We show that the restriction of transport through a single level in solid state junctions (no solvent) makes coherent and incoherent tunneling formalisms indistinguishable when only one level participates in transport. Similar to Marcus relaxation processes in wet electrochemistry, the thermal broadening of the Fermi distribution describing the electronic occupation energies in the electrodes accounts for the exponential dependence of the tunneling current on temperature. We demonstrate that a single-level tunnel model satisfactorily explains experimental results obtained in three different molecular junctions (both single-molecule and SAM-based) formed by ferrocene-based molecules. Among other things, we use the model to map the electrostatic potential profile in EGaIn-based SAM junctions in which the ferrocene unit is placed at different positions within the molecule, and we find that electrical screening gives rise to a strongly non-linear profile across the junction. PMID:27216489

Electrical properties of graphene tunnel junctions with high-κ metal-oxide barriers

NASA Astrophysics Data System (ADS)

Feng, Ying; Trainer, Daniel J.; Chen, Ke

2017-04-01

An insulating barrier is one of the key components in electronic devices that makes use of quantum tunneling principles. Many metal-oxides have been used as a good barrier material in a tunnel junction for their large band gap, stable chemical properties and superb properties for forming a thin and pin-hole-free insulating layer. The reduced dimensions of transistors have led to the need for alternative, high dielectric constant (high-κ) oxides to replace conventional silicon-based dielectrics to reduce the leaking current induced by electron tunneling. On the other hand, a tunnel junction with one or both electrodes made of graphene may lead to novel applications due to the massless Dirac fermions from the graphene. Here we have fabricated sandwich-type graphene tunnel junctions with high-κ metal-oxides as barriers, including Al2O3, HfO2, ZrO2, and TiO2. Tunneling properties are investigated by observing the temperature and time dependences of the tunneling spectra. Our results show the potential for applications of high-κ oxides in graphene tunnel junctions and bringing new opportunities for memory and logic electronic devices.

Dual-gate operation and carrier transport in SiGe p–n junction nanowires

DOE PAGES

Delker, Collin James; Yoo, Jink Young; Bussmann, Ezra; ...

2017-10-23

Here, we investigate carrier transport in silicon–germanium nanowires with an axial p–n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source–drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source–drain configuration, current is limited by the nickel/n-side Schottky contact.

Ultralow-voltage design of graphene PN junction quantum reflective switch transistor

NASA Astrophysics Data System (ADS)

Sohier, Thibault; Yu, Bin

2011-05-01

We propose the concept of a graphene-based quantum reflective switch (QRS) for low-power logic application. With the unique electronic properties of graphene, a tilted PN junction is used to implement logic switch function with 103 ON/OFF ratio. Carriers are reflected on an electrostatically induced potential step with strong incidence-angle-dependency due to the widening of classically forbidden energies. Optimized design of the device for ultralow-voltage operating has been conducted. The device is constantly ON with a turning-off gate voltage around 180 mV using thin HfO2 as the gate dielectric. The results suggest a class of logic switch devices operating with micropower dissipation.

Enhanced distributed energy resource system

DOEpatents

Atcitty, Stanley [Albuquerque, NM; Clark, Nancy H [Corrales, NM; Boyes, John D [Albuquerque, NM; Ranade, Satishkumar J [Las Cruces, NM

2007-07-03

A power transmission system including a direct current power source electrically connected to a conversion device for converting direct current into alternating current, a conversion device connected to a power distribution system through a junction, an energy storage device capable of producing direct current connected to a converter, where the converter, such as an insulated gate bipolar transistor, converts direct current from an energy storage device into alternating current and supplies the current to the junction and subsequently to the power distribution system. A microprocessor controller, connected to a sampling and feedback module and the converter, determines when the current load is higher than a set threshold value, requiring triggering of the converter to supply supplemental current to the power transmission system.

Dual-gate operation and carrier transport in SiGe p-n junction nanowires

NASA Astrophysics Data System (ADS)

Delker, C. J.; Yoo, J. Y.; Bussmann, E.; Swartzentruber, B. S.; Harris, C. T.

2017-11-01

We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.

Dual-gate operation and carrier transport in SiGe p–n junction nanowires

DOE Office of Scientific and Technical Information (OSTI.GOV)

Delker, Collin James; Yoo, Jink Young; Bussmann, Ezra

Here, we investigate carrier transport in silicon–germanium nanowires with an axial p–n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source–drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source–drain configuration, current is limited by the nickel/n-side Schottky contact.

Analysis of multiple time scales in a transistor amplifier.

PubMed

Armstead, Douglas N; Carroll, Thomas L

2005-03-01

It was shown previously in an experiment that when high frequency signals (on the order of 1 MHz) were injected into this low frequency amplifier, the nonlinearities of the pn junctions caused period doubling, chaos, and very low frequency oscillations (on the order of 1 Hz). In this paper we present theory and simulations to explain the existence of the low frequency oscillations.

Press to Test: Shop-Built BJT Checker Is Easy to Use

ERIC Educational Resources Information Center

Harman, Charles

2008-01-01

Whether a student or an instructor in an electronics lab, having the means to check the operation of a bipolar junction transistor (BJT) at the proto-board stage is a blessing. Most students do not have the experience or knowledge that it takes to recognize whether or not a BJT is operating. With this handy BJT checker, a student or the instructor…

Low Power Band to Band Tunnel Transistors

DTIC Science & Technology

2010-12-15

burden, to Washington Headquarters Services , Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA...issues like poor dielectric interface quality and low density of states[1.10]. Further homo junction TFETs in these ultra low bandgap materials exhibit...drain leakage current on MOSFET scaling”, International Electron Devices Meeting, Vol.33, pp: 718-721, 1987 [1.3] W. M. Reddick, G. A. Amaratunga

Direct observation of lifetime killing defects in 4H SiC epitaxial layers through spin dependent recombination in bipolar junction transistors

NASA Astrophysics Data System (ADS)

Cochrane, C. J.; Lenahan, P. M.; Lelis, A. J.

2009-03-01

We have identified a magnetic resonance spectrum associated with minority carrier lifetime killing defects in device quality 4H SiC through magnetic resonance measurements in bipolar junction transistors using spin dependent recombination (SDR). The SDR spectrum has nine distinguishable lines; it is, within experimental error, essentially isotropic with four distinguishable pairs of side peaks symmetric about the strong center line. The line shape is, within experimental error, independent of bias voltage and recombination current. The large amplitude and spacing of the inner pair of side peaks and three more widely separated pairs of side peaks are not consistent with either a simple silicon or carbon vacancy or a carbon or silicon antisite. This indicates that the lifetime killing defect is not a simple defect but a defect aggregate. The spectrum is consistent with a multidefect cluster with an electron spin S =1/2. (The observed spectrum has not been reported previously in the magnetic resonance literature on SiC.) A fairly strong argument can be made in terms of a first order model linking the SDR spectrum to a divacancy or possibly a vacancy/antisite pair. The SDR amplitude versus gate voltage is semiquantitatively consistent with a very simple model in which the defect is uniformly distributed within the depletion region of the base/collector junction and is also the dominating recombination center. The large relative amplitude of the SDR response is more nearly consistent with a Kaplan-Solomon-Mott-like model for spin dependent recombination than the Lepine model.

Schottky Barrier Height Tuning via the Dopant Segregation Technique through Low-Temperature Microwave Annealing.

PubMed

Fu, Chaochao; Zhou, Xiangbiao; Wang, Yan; Xu, Peng; Xu, Ming; Wu, Dongping; Luo, Jun; Zhao, Chao; Zhang, Shi-Li

2016-04-27

The Schottky junction source/drain structure has great potential to replace the traditional p/n junction source/drain structure of the future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs), as it can form ultimately shallow junctions. However, the effective Schottky barrier height (SBH) of the Schottky junction needs to be tuned to be lower than 100 meV in order to obtain a high driving current. In this paper, microwave annealing is employed to modify the effective SBH of NiSi on Si via boron or arsenic dopant segregation. The barrier height decreased from 0.4-0.7 eV to 0.2-0.1 eV for both conduction polarities by annealing below 400 °C. Compared with the required temperature in traditional rapid thermal annealing, the temperature demanded in microwave annealing is ~60 °C lower, and the mechanisms of this observation are briefly discussed. Microwave annealing is hence of high interest to future semiconductor processing owing to its unique capability of forming the metal/semiconductor contact at a remarkably lower temperature.

Schottky Barrier Height Tuning via the Dopant Segregation Technique through Low-Temperature Microwave Annealing

PubMed Central

Fu, Chaochao; Zhou, Xiangbiao; Wang, Yan; Xu, Peng; Xu, Ming; Wu, Dongping; Luo, Jun; Zhao, Chao; Zhang, Shi-Li

2016-01-01

The Schottky junction source/drain structure has great potential to replace the traditional p/n junction source/drain structure of the future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs), as it can form ultimately shallow junctions. However, the effective Schottky barrier height (SBH) of the Schottky junction needs to be tuned to be lower than 100 meV in order to obtain a high driving current. In this paper, microwave annealing is employed to modify the effective SBH of NiSi on Si via boron or arsenic dopant segregation. The barrier height decreased from 0.4–0.7 eV to 0.2–0.1 eV for both conduction polarities by annealing below 400 °C. Compared with the required temperature in traditional rapid thermal annealing, the temperature demanded in microwave annealing is ~60 °C lower, and the mechanisms of this observation are briefly discussed. Microwave annealing is hence of high interest to future semiconductor processing owing to its unique capability of forming the metal/semiconductor contact at a remarkably lower temperature. PMID:28773440

Modulation-doped growth of mosaic graphene with single-crystalline p–n junctions for efficient photocurrent generation

PubMed Central

Yan, Kai; Wu, Di; Peng, Hailin; Jin, Li; Fu, Qiang; Bao, Xinhe; Liu, Zhongfan

2012-01-01

Device applications of graphene such as ultrafast transistors and photodetectors benefit from the combination of both high-quality p- and n-doped components prepared in a large-scale manner with spatial control and seamless connection. Here we develop a well-controlled chemical vapour deposition process for direct growth of mosaic graphene. Mosaic graphene is produced in large-area monolayers with spatially modulated, stable and uniform doping, and shows considerably high room temperature carrier mobility of ~5,000 cm2 V−1 s−1 in intrinsic portion and ~2,500 cm2 V−1 s−1 in nitrogen-doped portion. The unchanged crystalline registry during modulation doping indicates the single-crystalline nature of p–n junctions. Efficient hot carrier-assisted photocurrent was generated by laser excitation at the junction under ambient conditions. This study provides a facile avenue for large-scale synthesis of single-crystalline graphene p–n junctions, allowing for batch fabrication and integration of high-efficiency optoelectronic and electronic devices within the atomically thin film. PMID:23232410

Oscillatory threshold logic.

PubMed

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

Forward-bias tunneling - A limitation to bipolar device scaling

NASA Technical Reports Server (NTRS)

Del Alamo, Jesus A.; Swanson, Richard M.

1986-01-01

Forward-bias tunneling is observed in heavily doped p-n junctions of bipolar transistors. A simple phenomenological model suitable to incorporation in device codes is developed. The model identifies as key parameters the space-charge-region (SCR) thickness at zero bias and the reduced doping level at its edges which can both be obtained from CV characteristics. This tunneling mechanism may limit the maximum gain achievable from scaled bipolar devices.

Theoretical investigation of GaAsBi/GaAsN tunneling field-effect transistors with type-II staggered tunneling junction

NASA Astrophysics Data System (ADS)

Wang, Yibo; Liu, Yan; Han, Genquan; Wang, Hongjuan; Zhang, Chunfu; Zhang, Jincheng; Hao, Yue

2017-06-01

We investigate GaAsBi/GaAsN system for the design of type-II staggered hetero tunneling field-effect transistor (hetero-TFET). Strain-symmetrized GaAsBi/GaAsN with effective lattice match to GaAs exhibits a type-II band lineup, and the effective bandgap EG,eff at interface is significantly reduced with the incorporation of Bi and N elements. The band-to-band tunneling (BTBT) rate and drive current of GaAsBi/GaAsN hetero-TFETs are boosted due to the utilizing of the type-II staggered tunneling junction with the reduced EG,eff. Numerical simulation shows that the drive current and subthreshold swing (SS) characteristics of GaAsBi/GaAsN hetero-TFETs are remarkably improved by increasing Bi and N compositions. The dilute content GaAs0.85Bi0.15/GaAs0.92N0.08 staggered hetero-nTFET achieves 7.8 and 550 times higher ION compared to InAs and In0.53Ga0.47As homo-TFETs, respectively, at the supply voltage of 0.3 V. GaAsBi/GaAsN heterostructure is a potential candidate for high performance TFET.

Electrical detection of the biological interaction of a charged peptide via gallium arsenide junction-field-effect transistors

PubMed Central

Lee, Kangho; Nair, Pradeep R.; Alam, Muhammad A.; Janes, David B.; Wampler, Heeyeon P.; Zemlyanov, Dmitry Y.; Ivanisevic, Albena

2008-01-01

GaAs junction-field-effect transistors (JFETs) are utilized to achieve label-free detection of biological interaction between a probe transactivating transcriptional activator (TAT) peptide and the target trans-activation-responsive (TAR) RNA. The TAT peptide is a short sequence derived from the human immunodeficiency virus-type 1 TAT protein. The GaAs JFETs are modified with a mixed adlayer of 1-octadecanethiol (ODT) and TAT peptide, with the ODT passivating the GaAs surface from polar ions in physiological solutions and the TAT peptide providing selective binding sites for TAR RNA. The devices modified with the mixed adlayer exhibit a negative pinch-off voltage (VP) shift, which is attributed to the fixed positive charges from the arginine-rich regions in the TAT peptide. Immersing the modified devices into a TAR RNA solution results in a large positive VP shift (>1 V) and a steeper subthreshold slope (∼80 mV∕decade), whereas “dummy” RNA induced a small positive VP shift (∼0.3 V) without a significant change in subthreshold slopes (∼330 mV∕decade). The observed modulation of device characteristics is analyzed with analytical modeling and two-dimensional numerical device simulations to investigate the electronic interactions between the GaAs JFETs and biological molecules. PMID:19484151

Atypical transistor-based chaotic oscillators: Design, realization, and diversity

NASA Astrophysics Data System (ADS)

Minati, Ludovico; Frasca, Mattia; OświÈ©cimka, Paweł; Faes, Luca; DroŻdŻ, Stanisław

2017-07-01

In this paper, we show that novel autonomous chaotic oscillators based on one or two bipolar junction transistors and a limited number of passive components can be obtained via random search with suitable heuristics. Chaos is a pervasive occurrence in these circuits, particularly after manual adjustment of a variable resistor placed in series with the supply voltage source. Following this approach, 49 unique circuits generating chaotic signals when physically realized were designed, representing the largest collection of circuits of this kind to date. These circuits are atypical as they do not trivially map onto known topologies or variations thereof. They feature diverse spectra and predominantly anti-persistent monofractal dynamics. Notably, we recurrently found a circuit comprising one resistor, one transistor, two inductors, and one capacitor, which generates a range of attractors depending on the parameter values. We also found a circuit yielding an irregular quantized spike-train resembling some aspects of neural discharge and another one generating a double-scroll attractor, which represent the smallest known transistor-based embodiments of these behaviors. Through three representative examples, we additionally show that diffusive coupling of heterogeneous oscillators of this kind may give rise to complex entrainment, such as lag synchronization with directed information transfer and generalized synchronization. The replicability and reproducibility of the experimental findings are good.

Atypical transistor-based chaotic oscillators: Design, realization, and diversity.

PubMed

Minati, Ludovico; Frasca, Mattia; Oświȩcimka, Paweł; Faes, Luca; Drożdż, Stanisław

2017-07-01

In this paper, we show that novel autonomous chaotic oscillators based on one or two bipolar junction transistors and a limited number of passive components can be obtained via random search with suitable heuristics. Chaos is a pervasive occurrence in these circuits, particularly after manual adjustment of a variable resistor placed in series with the supply voltage source. Following this approach, 49 unique circuits generating chaotic signals when physically realized were designed, representing the largest collection of circuits of this kind to date. These circuits are atypical as they do not trivially map onto known topologies or variations thereof. They feature diverse spectra and predominantly anti-persistent monofractal dynamics. Notably, we recurrently found a circuit comprising one resistor, one transistor, two inductors, and one capacitor, which generates a range of attractors depending on the parameter values. We also found a circuit yielding an irregular quantized spike-train resembling some aspects of neural discharge and another one generating a double-scroll attractor, which represent the smallest known transistor-based embodiments of these behaviors. Through three representative examples, we additionally show that diffusive coupling of heterogeneous oscillators of this kind may give rise to complex entrainment, such as lag synchronization with directed information transfer and generalized synchronization. The replicability and reproducibility of the experimental findings are good.

Four-gate transistor analog multiplier circuit

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)

2011-01-01

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Room-temperature current blockade in atomically defined single-cluster junctions

NASA Astrophysics Data System (ADS)

Lovat, Giacomo; Choi, Bonnie; Paley, Daniel W.; Steigerwald, Michael L.; Venkataraman, Latha; Roy, Xavier

2017-11-01

Fabricating nanoscopic devices capable of manipulating and processing single units of charge is an essential step towards creating functional devices where quantum effects dominate transport characteristics. The archetypal single-electron transistor comprises a small conducting or semiconducting island separated from two metallic reservoirs by insulating barriers. By enabling the transfer of a well-defined number of charge carriers between the island and the reservoirs, such a device may enable discrete single-electron operations. Here, we describe a single-molecule junction comprising a redox-active, atomically precise cobalt chalcogenide cluster wired between two nanoscopic electrodes. We observe current blockade at room temperature in thousands of single-cluster junctions. Below a threshold voltage, charge transfer across the junction is suppressed. The device is turned on when the temporary occupation of the core states by a transiting carrier is energetically enabled, resulting in a sequential tunnelling process and an increase in current by a factor of ∼600. We perform in situ and ex situ cyclic voltammetry as well as density functional theory calculations to unveil a two-step process mediated by an orbital localized on the core of the cluster in which charge carriers reside before tunnelling to the collector reservoir. As the bias window of the junction is opened wide enough to include one of the cluster frontier orbitals, the current blockade is lifted and charge carriers can tunnel sequentially across the junction.

Experimental synchronization of chaos in a large ring of mutually coupled single-transistor oscillators: phase, amplitude, and clustering effects.

PubMed

Minati, Ludovico

2014-12-01

In this paper, experimental evidence of multiple synchronization phenomena in a large (n = 30) ring of chaotic oscillators is presented. Each node consists of an elementary circuit, generating spikes of irregular amplitude and comprising one bipolar junction transistor, one capacitor, two inductors, and one biasing resistor. The nodes are mutually coupled to their neighbours via additional variable resistors. As coupling resistance is decreased, phase synchronization followed by complete synchronization is observed, and onset of synchronization is associated with partial synchronization, i.e., emergence of communities (clusters). While component tolerances affect community structure, the general synchronization properties are maintained across three prototypes and in numerical simulations. The clusters are destroyed by adding long distance connections with distant notes, but are otherwise relatively stable with respect to structural connectivity changes. The study provides evidence that several fundamental synchronization phenomena can be reliably observed in a network of elementary single-transistor oscillators, demonstrating their generative potential and opening way to potential applications of this undemanding setup in experimental modelling of the relationship between network structure, synchronization, and dynamical properties.

Research Update: Molecular electronics: The single-molecule switch and transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sotthewes, Kai; Heimbuch, René, E-mail: r.heimbuch@utwente.nl; Kumar, Avijit

2014-01-01

In order to design and realize single-molecule devices it is essential to have a good understanding of the properties of an individual molecule. For electronic applications, the most important property of a molecule is its conductance. Here we show how a single octanethiol molecule can be connected to macroscopic leads and how the transport properties of the molecule can be measured. Based on this knowledge we have realized two single-molecule devices: a molecular switch and a molecular transistor. The switch can be opened and closed at will by carefully adjusting the separation between the electrical contacts and the voltage dropmore » across the contacts. This single-molecular switch operates in a broad temperature range from cryogenic temperatures all the way up to room temperature. Via mechanical gating, i.e., compressing or stretching of the octanethiol molecule, by varying the contact's interspace, we are able to systematically adjust the conductance of the electrode-octanethiol-electrode junction. This two-terminal single-molecule transistor is very robust, but the amplification factor is rather limited.« less

Electron and hole photoemission detection for band offset determination of tunnel field-effect transistor heterojunctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Wei; Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871; Zhang, Qin

2014-11-24

We report experimental methods to ascertain a complete energy band alignment of a broken-gap tunnel field-effect transistor based on an InAs/GaSb hetero-junction. By using graphene as an optically transparent electrode, both the electron and hole barrier heights at the InAs/GaSb interface can be quantified. For a Al{sub 2}O{sub 3}/InAs/GaSb layer structure, the barrier height from the top of the InAs and GaSb valence bands to the bottom of the Al{sub 2}O{sub 3} conduction band is inferred from electron emission whereas hole emissions reveal the barrier height from the top of the Al{sub 2}O{sub 3} valence band to the bottom ofmore » the InAs and GaSb conduction bands. Subsequently, the offset parameter at the broken gap InAs/GaSb interface is extracted and thus can be used to facilitate the development of predicted models of electron quantum tunneling efficiency and transistor performance.« less

Coulomb Blockade and Multiple Andreev Reflection in a Superconducting Single-Electron Transistor

NASA Astrophysics Data System (ADS)

Lorenz, Thomas; Sprenger, Susanne; Scheer, Elke

2018-06-01

In superconducting quantum point contacts, multiple Andreev reflection (MAR), which describes the coherent transport of m quasiparticles each carrying an electron charge with m≥3, sets in at voltage thresholds eV = 2Δ /m. In single-electron transistors, Coulomb blockade, however, suppresses the current at low voltage. The required voltage for charge transport increases with the square of the effective charge eV∝ ( me) ^2. Thus, studying the charge transport in all-superconducting single-electron transistors (SSETs) sets these two phenomena into competition. In this article, we present the fabrication as well as a measurement scheme and transport data for a SSET with one junction in which the transmission and thereby the MAR contributions can be continuously tuned. All regimes from weak to strong coupling are addressed. We extend the Orthodox theory by incorporating MAR processes to describe the observed data qualitatively. We detect a new transport process the nature of which is unclear at present. Furthermore, we observe a renormalization of the charging energy when approaching the strong coupling regime.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

PubMed Central

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

The effects of neutron and gamma rays on the electrical and switching characteristics of power semiconductor switches must be known and understood by the designer of the power conditioning, control, and transmission subsystem of space nuclear power systems. The SP-100 radiation requirements at 25 m from the nuclear source are a neutron fluence of 10(exp 13) n/sq cm and a gamma dose of 0.5 Mrads. Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN Bipolar Junction Transistors (BJTs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Static Induction Transistors (SITs) are presented. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Post-irradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions.

PubMed

Trommer, Jens; Heinzig, André; Mühle, Uwe; Löffler, Markus; Winzer, Annett; Jordan, Paul M; Beister, Jürgen; Baldauf, Tim; Geidel, Marion; Adolphi, Barbara; Zschech, Ehrenfried; Mikolajick, Thomas; Weber, Walter M

2017-02-28

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element drift-diffusion simulations reveal that both leakage current suppression and polarity control can also be achieved at highly scaled geometries, providing solutions for future energy-efficient systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Custer, Jonathan S.; Fleming, James G.; Roherty-Osmun, Elizabeth

Refractory ternary nitride films for diffusion barriers in microelectronics have been grown using chemical vapor deposition. Thin films of titanium-silicon-nitride, tungsten-boron-nitride, and tungsten-silicon-nitride of various compositions have been deposited on 150 mm Si wafers. The microstructure of the films are either fully amorphous for the tungsten based films, or nauocrystalline TiN in an amorphous matrix for titanium-silicon-nitride. All films exhibit step coverages suitable for use in future microelectronics generations. Selected films have been tested as diffusion barriers between copper and silicon, and generally perform extremely weH. These fiIms are promising candidates for advanced diffusion barriers for microelectronics applications. The manufacturingmore » of silicon wafers into integrated circuits uses many different process and materials. The manufacturing process is usually divided into two parts: the front end of line (FEOL) and the back end of line (BEOL). In the FEOL the individual transistors that are the heart of an integrated circuit are made on the silicon wafer. The responsibility of the BEOL is to wire all the transistors together to make a complete circuit. The transistors are fabricated in the silicon itself. The wiring is made out of metal, currently aluminum and tungsten, insulated by silicon dioxide, see Figure 1. Unfortunately, silicon will diffuse into aluminum, causing aluminum spiking of junctions, killing transistors. Similarly, during chemical vapor deposition (CVD) of tungsten from ~fj, the reactivity of the fluorine can cause "worn-holes" in the silicon, also destroying transistors. The solution to these problems is a so-called diffusion barrier, which will allow current to pass from the transistors to the wiring, but will prevent reactions between silicon and the metal.« less

Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

NASA Astrophysics Data System (ADS)

Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

2016-02-01

Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal radiation sensing and cryogenic terahertz radiation sensing.

Nonadiabatic Josephson current pumping by chiral microwave irradiation

NASA Astrophysics Data System (ADS)

Venitucci, B.; Feinberg, D.; Mélin, R.; Douçot, B.

2018-05-01

Irradiating a Josephson junction with microwaves can operate not only on the amplitude but also on the phase of the Josephson current. This requires breaking time-inversion symmetry, which is achieved by introducing a phase lapse between the microwave components acting on the two sides of the junction. General symmetry arguments and the solution of a specific single-level quantum dot model show that this induces chirality in the Cooper pair dynamics due to the topology of the Andreev bound-state wave function. Another essential condition is to break electron-hole symmetry within the junction. A shift of the current-phase relation is obtained, which is controllable in sign and amplitude with the microwave phase and an electrostatic gate, thus producing a "chiral" Josephson transistor. The dot model is solved in the infinite-gap limit by Floquet theory and in the general case with Keldysh nonequilibrium Green's functions. The chiral current is nonadiabatic: it is extremal and changes sign close to resonant chiral transitions between the Andreev bound states.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

International Technical Exchange on 2D Atomic Sheets: Optoelectronics, Strain, and Energy Applications

DTIC Science & Technology

2015-01-15

Shi, University of Texas - Austin Thermal and Thermoelectric Properties and Applications of Two-Dimensional Materials beyond Graphene 11:45 – 1:15 pm...M., et al., Large and tunable photo- thermoelectric effect in single-layer MoS2, Nano Letters (2013) [4] Castellanos-Gomez, A., et al., Isolation...phosphorus field- effect transistors. Nano Letters (2014) [6] Buscema M., et al., Photovoltaic effect in few-layer black phosphorus PN junctions

Solid state image sensing arrays

NASA Technical Reports Server (NTRS)

Sadasiv, G.

1972-01-01

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Minority carrier device comprising a passivating layer including a Group 13 element and a chalcogenide component

NASA Technical Reports Server (NTRS)

Barron, Andrew R. (Inventor); Hepp, Aloysius F. (Inventor); Jenkins, Phillip P. (Inventor); MacInnes, Andrew N. (Inventor)

1999-01-01

A minority carrier device includes at least one junction of at least two dissimilar materials, at least one of which is a semiconductor, and a passivating layer on at least one surface of the device. The passivating layer includes a Group 13 element and a chalcogenide component. Embodiments of the minority carrier device include, for example, laser diodes, light emitting diodes, heterojunction bipolar transistors, and solar cells.

Hardening measures for bipolar transistors against microwave-induced damage

NASA Astrophysics Data System (ADS)

Chai, Chang-Chun; Ma, Zhen-Yang; Ren, Xing-Rong; Yang, Yin-Tang; Zhao, Ying-Bo; Yu, Xin-Hai

2013-06-01

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.

Oscillatory Threshold Logic

PubMed Central

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

Atomtronics: Realizing the behavior of electronic components in ultracold atomic systems

NASA Astrophysics Data System (ADS)

Pepino, Ron

2007-06-01

Atomtronics focuses on creating an analogy of electronic devices and circuits with ultracold atoms. Such an analogy can come from the highly tunable band structure of ultracold neutral atoms trapped in optical lattices. Solely by tuning the parameters of the optical lattice, we demonstrate that conditions can be created that cause atoms in lattices to exhibit the same behavior as electrons moving through solid state media. We present our model and show how the atomtronic diode, field effect transistor, and bipolar junction transistor can all be realized. Our analogs of these fundamental components exhibit precisely-controlled atomic signal amplification, trimming, and switching (on/off) characteristics. In addition, the evolution of dynamics of the superfluid atomic currents within these systems is completely reversible. This implies a possible use of atomtronic systems in the development of quantum computational devices.

Effects of oxygen-inserted layers on diffusion of boron, phosphorus, and arsenic in silicon for ultra-shallow junction formation

NASA Astrophysics Data System (ADS)

Zhang, X.; Connelly, D.; Takeuchi, H.; Hytha, M.; Mears, R. J.; Rubin, L. M.; Liu, T.-J. K.

2018-03-01

The effects of oxygen-inserted (OI) layers on the diffusion of boron (B), phosphorus (P), and arsenic (As) in silicon (Si) are investigated, for ultra-shallow junction formation by high-dose ion implantation followed by rapid thermal annealing. The projected range (Rp) of the implanted dopants is shallower than the depth of the OI layers. Secondary ion mass spectrometry is used to compare the dopant profiles in silicon samples that have OI layers against the dopant profiles in control samples that do not have OI layers. Diffusion is found to be substantially retarded by the OI layers for B and P, and less for As, providing shallower junction depth. The experimental results suggest that the OI layers serve to block the diffusion of Si self-interstitials and thereby effectively reduce interstitial-aided diffusion beyond the depth of the OI layers. The OI layers also help to retain more dopants within the Si, which technology computer-aided design simulations indicate to be beneficial for achieving shallower junctions with lower sheet resistance to enable further miniaturization of planar metal-oxide-semiconductor field-effect transistors for improved integrated-circuit performance and cost per function.

Effect of low and staggered gap quantum wells inserted in GaAs tunnel junctions

NASA Astrophysics Data System (ADS)

Louarn, K.; Claveau, Y.; Marigo-Lombart, L.; Fontaine, C.; Arnoult, A.; Piquemal, F.; Bounouh, A.; Cavassilas, N.; Almuneau, G.

2018-04-01

In this article, we investigate the impact of the insertion of either a type I InGaAs or a type II InGaAs/GaAsSb quantum well on the performances of MBE-grown GaAs tunnel junctions (TJs). The devices are designed and simulated using a quantum transport model based on the non-equilibrium Green’s function formalism and a 6-band k.p Hamiltonian. We experimentally observe significant improvements of the peak tunneling current density on both heterostructures with a 460-fold increase for a moderately doped GaAs TJ when the InGaAs QW is inserted at the junction interface, and a 3-fold improvement on a highly doped GaAs TJ integrating a type II InGaAs/GaAsSb QW. Thus, the simple insertion of staggered band lineup heterostructures enables us to reach a tunneling current well above the kA cm‑2 range, equivalent to the best achieved results for Si-doped GaAs TJs, implying very interesting potential for TJ-based components, such as multi-junction solar cells, vertical cavity surface emitting lasers and tunnel-field effect transistors.

Strategies for improving neural signal detection using a neural-electronic interface.

PubMed

Szlavik, Robert B

2003-03-01

There have been various theoretical and experimental studies presented in the literature that focus on interfacing neurons with discrete electronic devices, such as transistors. From both a theoretical and experimental perspective, these studies have emphasized the variability in the characteristics of the detected action potential from the nerve cell. The demonstrated lack of reproducible fidelity of the nerve cell action potential at the device junction would make it impractical to implement these devices in any neural prosthetic application where reliable detection of the action potential was a prerequisite. In this study, the effects of several different physical parameters on the fidelity of the detected action potential at the device junction are investigated and discussed. The impact of variations in the extracellular resistivity, which directly affects the junction seal resistance, is studied along with the impact of variable nerve cell membrane capacitance and variations in the injected charge. These parameters are discussed in the context of their suitability to design manipulation for the purpose of improving the fidelity of the detected neural action potential. In addition to investigating the effects of variations in these parameters, the applicability of the linear equivalent circuit approach to calculating the junction potential is investigated.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

An accurate two-dimensional LBIC solution for bipolar transistors

NASA Astrophysics Data System (ADS)

Benarab, A.; Baudrand, H.; Lescure, M.; Boucher, J.

1988-05-01

A complete solution of the diffusion problem of carriers generated by a located light beam in the emitter and base region of a bipolar structure is presented. Green's function method and moment method are used to solve the 2-D diffusion equation in these regions. From the Green's functions solution of these equations, the light beam induced currents (LBIC) in the different junctions of the structure due to an extended generation represented by a rectangular light spot; are thus decided. The equations of these currents depend both on the parameters which characterise the structure, surface states, dimensions of the emitter and the base region, and the characteristics of the light spot, that is to say, the width and the wavelength. Curves illustrating the variation of the various LBIC in the base region junctions as a function of the impact point of the light beam ( x0) for different values of these parameters are discussed. In particular, the study of the base-emitter currents when the light beam is swept right across the sample illustrates clearly a good geometrical definition of the emitter region up to base end of the emitter-base space-charge areas and a "whirl" lateral diffusion beneath this region, (i.e. the diffusion of the generated carriers near the surface towards the horizontal base-emitter junction and those created beneath this junction towards the lateral (B-E) junctions).

Radio-frequency measurement of an asymmetric single electron transistor

NASA Astrophysics Data System (ADS)

Ji, Zhongqing; Xue, Weiwei; Rimberg, A. J.

2007-03-01

Since the invention of the radio-frequency single-electron transistor (RF-SET) by Schoelkopf et al.,[1] most measurements have focused on the symmetric single electron transistor. It has been shown, however, that the symmetric SET has a rather low measurement efficiency in its normal working regime.[2][3] Recently, it has been pointed out that an asymmetric SET can be considerably more efficient than a symmetric SET as a quantum amplifier. In this case the measurement efficiency of the asymmetric SET becomes similar to that of the quantum point contact (QPC) detector which can approach the quantum limit. We investigate the asymmetric SET by fabricating Al/AlOx SETs with junction areas 40x40 nm^2 and 40x80nm^2 and total resistance of about 25kφ. The results of RF and DC characterization of such asymmetric SETs will be discussed. [1] R. J. Schoelkopf, P. Wahlgren, A. A. Kozhevnikov, P. Delsing, D. E. Prober, Science, 280, 1242 (1998). [2] A. N. Korotkov, Phys. Rev. B, 63, 085312 (2001); 63, 115403 (2001). [3] D. Mozyrsky, I. Martin, and M. B. Hastings, Phys. Rev. Lett., 92, 018303 (2004). [4] S. A. Gurvitz and G. P. Berman, Phys. Rev. B, 72 , 073303(2005).

Experimental synchronization of chaos in a large ring of mutually coupled single-transistor oscillators: Phase, amplitude, and clustering effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minati, Ludovico, E-mail: lminati@ieee.org, E-mail: ludovico.minati@unitn.it

In this paper, experimental evidence of multiple synchronization phenomena in a large (n = 30) ring of chaotic oscillators is presented. Each node consists of an elementary circuit, generating spikes of irregular amplitude and comprising one bipolar junction transistor, one capacitor, two inductors, and one biasing resistor. The nodes are mutually coupled to their neighbours via additional variable resistors. As coupling resistance is decreased, phase synchronization followed by complete synchronization is observed, and onset of synchronization is associated with partial synchronization, i.e., emergence of communities (clusters). While component tolerances affect community structure, the general synchronization properties are maintained across three prototypes andmore » in numerical simulations. The clusters are destroyed by adding long distance connections with distant notes, but are otherwise relatively stable with respect to structural connectivity changes. The study provides evidence that several fundamental synchronization phenomena can be reliably observed in a network of elementary single-transistor oscillators, demonstrating their generative potential and opening way to potential applications of this undemanding setup in experimental modelling of the relationship between network structure, synchronization, and dynamical properties.« less

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

High-Performance Organic Vertical Thin Film Transistor Using Graphene as a Tunable Contact.

PubMed

Liu, Yuan; Zhou, Hailong; Weiss, Nathan O; Huang, Yu; Duan, Xiangfeng

2015-11-24

Here we present a general strategy for the fabrication of high-performance organic vertical thin film transistors (OVTFTs) based on the heterostructure of graphene and different organic semiconductor thin films. Utilizing the unique tunable work function of graphene, we show that the vertical carrier transport across the graphene-organic semiconductor junction can be effectively modulated to achieve an ON/OFF ratio greater than 10(3). Importantly, with the OVTFT design, the channel length is determined by the organic thin film thickness rather than by lithographic resolution. It can thus readily enable transistors with ultrashort channel lengths (<200 nm) to afford a delivering current greatly exceeding that of conventional planar TFTs, thus enabling a respectable operation frequency (up to 0.4 MHz) while using low-mobility organic semiconductors and low-resolution lithography. With this vertical device architecture, the entire organic channel is sandwiched and naturally protected between the source and drain electrodes, which function as the self-passivation layer to ensure stable operation of both p- and n-type OVTFTs in ambient conditions and enable complementary circuits with voltage gain. The creation of high-performance and highly robust OVTFTs can open up exciting opportunities in large-area organic macroelectronics.

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2018-04-01

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

Metal oxides for optoelectronic applications.

PubMed

Yu, Xinge; Marks, Tobin J; Facchetti, Antonio

2016-04-01

Metal oxides (MOs) are the most abundant materials in the Earth's crust and are ingredients in traditional ceramics. MO semiconductors are strikingly different from conventional inorganic semiconductors such as silicon and III-V compounds with respect to materials design concepts, electronic structure, charge transport mechanisms, defect states, thin-film processing and optoelectronic properties, thereby enabling both conventional and completely new functions. Recently, remarkable advances in MO semiconductors for electronics have been achieved, including the discovery and characterization of new transparent conducting oxides, realization of p-type along with traditional n-type MO semiconductors for transistors, p-n junctions and complementary circuits, formulations for printing MO electronics and, most importantly, commercialization of amorphous oxide semiconductors for flat panel displays. This Review surveys the uniqueness and universality of MOs versus other unconventional electronic materials in terms of materials chemistry and physics, electronic characteristics, thin-film fabrication strategies and selected applications in thin-film transistors, solar cells, diodes and memories.

Metal oxides for optoelectronic applications

NASA Astrophysics Data System (ADS)

Yu, Xinge; Marks, Tobin J.; Facchetti, Antonio

2016-04-01

Metal oxides (MOs) are the most abundant materials in the Earth's crust and are ingredients in traditional ceramics. MO semiconductors are strikingly different from conventional inorganic semiconductors such as silicon and III-V compounds with respect to materials design concepts, electronic structure, charge transport mechanisms, defect states, thin-film processing and optoelectronic properties, thereby enabling both conventional and completely new functions. Recently, remarkable advances in MO semiconductors for electronics have been achieved, including the discovery and characterization of new transparent conducting oxides, realization of p-type along with traditional n-type MO semiconductors for transistors, p-n junctions and complementary circuits, formulations for printing MO electronics and, most importantly, commercialization of amorphous oxide semiconductors for flat panel displays. This Review surveys the uniqueness and universality of MOs versus other unconventional electronic materials in terms of materials chemistry and physics, electronic characteristics, thin-film fabrication strategies and selected applications in thin-film transistors, solar cells, diodes and memories.

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE PAGES

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

2017-11-13

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

Ambipolar insulator-to-metal transition in black phosphorus by ionic-liquid gating.

PubMed

Saito, Yu; Iwasa, Yoshihiro

2015-03-24

We report ambipolar transport properties in black phosphorus using an electric-double-layer transistor configuration. The transfer curve clearly exhibits ambipolar transistor behavior with an ON-OFF ratio of ∼5 × 10(3). The band gap was determined as ≅0.35 eV from the transfer curve, and Hall-effect measurements revealed that the hole mobility was ∼190 cm(2)/(V s) at 170 K, which is 1 order of magnitude larger than the electron mobility. By inducing an ultrahigh carrier density of ∼10(14) cm(-2), an electric-field-induced transition from the insulating state to the metallic state was realized, due to both electron and hole doping. Our results suggest that black phosphorus will be a good candidate for the fabrication of functional devices, such as lateral p-n junctions and tunnel diodes, due to the intrinsic narrow band gap.

Stochastic Gain Degradation in III-V Heterojunction Bipolar Transistors due to Single Particle Displacement Damage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vizkelethy, Gyorgy; Bielejec, Edward S.; Aguirre, Brandon A.

As device dimensions decrease single displacement effects are becoming more important. We measured the gain degradation in III-V Heterojunction Bipolar Transistors due to single particles using a heavy ion microbeam. Two devices with different sizes were irradiated with various ion species ranging from oxygen to gold to study the effect of the irradiation ion mass on the gain change. From the single steps in the inverse gain (which is proportional to the number of defects) we calculated Cumulative Distribution Functions to help determine design margins. The displacement process was modeled using the Marlowe Binary Collision Approximation (BCA) code. The entiremore » structure of the device was modeled and the defects in the base-emitter junction were counted to be compared to the experimental results. While we found good agreement for the large device, we had to modify our model to reach reasonable agreement for the small device.« less

Neutron and gamma irradiation effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1990-01-01

The performance characteristics of high-power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Neutron and gamma irradiation effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1990-01-01

The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Bipolar Transistor and Diode Failure to Electrical Transients-Predictive Failure Modeling versus Experimental Damage Testing. 1 Junction Capacitance Damage Model

DTIC Science & Technology

1981-06-01

into the Wunsch-Bell equation) are P = A R , 1t-0 5 1.2 PD) = A26B2t-.5 (3) JAJ where A,*, A, B1, and B2 are experimentally determined constants and TJ...ATTN CODE 7240, S. N. LICHT’NAN PATRICK AID, FL 32J25 DIV COIMAND SAN DIEGO, CA 92152 ATTN D]PN-ATC AF WEAPONS LABORATORY, AFSC ATTN DRCFN- TDS -DSI

Prolonged 500 C Operation of 6H-SiC JFET Integrated Circuitry

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger D.; Ferrier, Terry L.; Krasowski, Michael J.;

Neutron Transmutation Doped (NTD) germanium thermistors for sub-mm bolometer applications

NASA Technical Reports Server (NTRS)

Haller, E. E.; Itoh, K. M.; Beeman, J. W.

1996-01-01

Recent advances in the development of neutron transmutation doped (NTD) semiconductor thermistors fabricated from natural and controlled isotopic composition germanium are reported. The near ideal doping uniformity that can be achieved with the NTD process, the device simplicity of NTD Ge thermistors and the high performance of cooled junction field effect transistor preamplifiers led to the widespread acceptance of these thermal sensors in ground-based, airborne and spaceborne radio telescopes. These features made possible the development of efficient bolometer arrays.

Germanium-Source Tunnel Field Effect Transistors for Ultra-Low Power Digital Logic

DTIC Science & Technology

2012-05-10

carrier injection via band-to-band tunneling (BTBT) and the absence of thermal (kT) dependence allows for the subthreshold swing to be steeper than... tunneling probability was derived by Kane using time- dependent perturbation theory and Fermi’s Golden Rule [8-9]. This section will instead employ a...be based on tunneling across a reverse- biased p-n junction as shown in Fig. 2.2. In order to obtain a closed form solution of the BTBT

How Small is too Small True Microrobots and Nanorobots for Military Applications in 2035

DTIC Science & Technology

2010-04-01

field effect transistor or diode junction based.41 Additionally, NEMS sensors based on resonating thin films and nanowires42 and optical based...acoustic sensor is fabricated from piezoelectric thin films and measures 600 µm by 600 µm by 2.2 µm thick with a total volume of 0.0008 mm3.50 Since...microrobot systems by 2035. Reduction in thin film width dimensions (under 600 µm), in order to be able to physically incorporate this into a

Oxide nanoelectronics on demand.

PubMed

Cen, Cheng; Thiel, Stefan; Mannhart, Jochen; Levy, Jeremy

2009-02-20

Electronic confinement at nanoscale dimensions remains a central means of science and technology. We demonstrate nanoscale lateral confinement of a quasi-two-dimensional electron gas at a lanthanum aluminate-strontium titanate interface. Control of this confinement using an atomic force microscope lithography technique enabled us to create tunnel junctions and field-effect transistors with characteristic dimensions as small as 2 nanometers. These electronic devices can be modified or erased without the need for complex lithographic procedures. Our on-demand nanoelectronics fabrication platform has the potential for widespread technological application.

Extraction of physical Schottky parameters using the Lambert function in Ni/AlGaN/GaN HEMT devices with defined conduction phenomena

NASA Astrophysics Data System (ADS)

Latry, O.; Divay, A.; Fadil, D.; Dherbécourt, P.

2017-01-01

Electrical characterization analyses are proposed in this work using the Lambert function on Schottky junctions in GaN wide band gap semiconductor devices for extraction of physical parameters. The Lambert function is used to give an explicit expression of the current in the Schottky junction. This function is applied with defined conduction phenomena, whereas other work presented arbitrary (or undefined) conduction mechanisms in such parameters’ extractions. Based upon AlGaN/GaN HEMT structures, extractions of parameters are undergone in order to provide physical characteristics. This work highlights a new expression of current with defined conduction phenomena in order to quantify the physical properties of Schottky contacts in AlGaN/GaN HEMT transistors. Project supported by the French Department of Defense (DGA).

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Current-voltage characteristics of n-AlMgZnO/p-GaN junction diodes

NASA Astrophysics Data System (ADS)

Hsueh, Kuang-Po; Cheng, Po-Wei; Cheng, Yi-Chang; Sheu, Jinn-Kong; Yeh, Yu-Hsiang; Chiu, Hsien-Chin; Wang, Hsiang-Chun

2013-03-01

This study investigates the temperature dependence of the current-voltage (I-V) characteristics of Al-doped MgxZn1-xO/p-GaN junction diodes. Specifically, this study reports the deposition of n-type Al-doped MgxZn1-xO (AMZO) films on p-GaN using a radio-frequency (RF) magnetron sputtering system followed by annealing at 700, 800, 900, and 1000 °C in a nitrogen ambient for 60 seconds, respectively. The AMZO/GaN films were thereafter analyzed using Hall measurement and the x-ray diffraction (XRD) patterns. The XRD results show that the diffraction angles of the annealed AMZO films remain the same as that of GaN without shifting. The n-AMZO/p-GaN diode with 900 °C annealing had the lowest leakage current in forward and reverse bias. However, the leakage current of the diodes did not change significantly with an increase in annealing temperatures. These findings show that the n-AMZO/p-GaN junction diode is feasible for GaN-based heterojunction bipolar transistors (HBTs) and UV light-emitting diodes (LEDs).

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

NASA Astrophysics Data System (ADS)

Shiota, Koki; Kai, Kazuho; Nagaoka, Shiro; Tsuji, Takuto; Wakahara, Akihiro; Rusop, Mohamad

2016-07-01

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As the result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.

Determination of lifetimes and recombination currents in p-n junction solar cells, diodes, and transistors

NASA Technical Reports Server (NTRS)

Neugroschel, A.

1981-01-01

New methods are presented and illustrated that enable the accurate determination of the diffusion length of minority carriers in the narrow regions of a solar cell or a diode. Other methods now available are inaccurate for the desired case in which the width of the region is less than the diffusion length. Once the diffusion length is determined by the new methods, this result can be combined with measured dark I-V characteristics and with small-signal admittance characteristics to enable determination of the recombination currents in each quasi-neutral region of the cell - for example, in the emitter, low-doped base, and high-doped base regions of the BSF (back-surface-field) cell. This approach leads to values for the effective surface recombination velocity of the high-low junction forming the back-surface field of BSF cells or the high-low emitter junction of HLE cells. These methods are also applicable for measuring the minority-carrier lifetime in thin epitaxial layers grown on substrates with opposite conductivity type.

Four-Quadrant Analog Multipliers Using G4-FETs

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Blalock, Benjamin; Christoloveanu, Sorin; Chen, Suheng; Akarvardar, Kerem

2006-01-01

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Analytical modeling of trilayer graphene nanoribbon Schottky-barrier FET for high-speed switching applications.

PubMed

Rahmani, Meisam; Ahmadi, Mohammad Taghi; Abadi, Hediyeh Karimi Feiz; Saeidmanesh, Mehdi; Akbari, Elnaz; Ismail, Razali

2013-01-30

Recent development of trilayer graphene nanoribbon Schottky-barrier field-effect transistors (FETs) will be governed by transistor electrostatics and quantum effects that impose scaling limits like those of Si metal-oxide-semiconductor field-effect transistors. The current-voltage characteristic of a Schottky-barrier FET has been studied as a function of physical parameters such as effective mass, graphene nanoribbon length, gate insulator thickness, and electrical parameters such as Schottky barrier height and applied bias voltage. In this paper, the scaling behaviors of a Schottky-barrier FET using trilayer graphene nanoribbon are studied and analytically modeled. A novel analytical method is also presented for describing a switch in a Schottky-contact double-gate trilayer graphene nanoribbon FET. In the proposed model, different stacking arrangements of trilayer graphene nanoribbon are assumed as metal and semiconductor contacts to form a Schottky transistor. Based on this assumption, an analytical model and numerical solution of the junction current-voltage are presented in which the applied bias voltage and channel length dependence characteristics are highlighted. The model is then compared with other types of transistors. The developed model can assist in comprehending experiments involving graphene nanoribbon Schottky-barrier FETs. It is demonstrated that the proposed structure exhibits negligible short-channel effects, an improved on-current, realistic threshold voltage, and opposite subthreshold slope and meets the International Technology Roadmap for Semiconductors near-term guidelines. Finally, the results showed that there is a fast transient between on-off states. In other words, the suggested model can be used as a high-speed switch where the value of subthreshold slope is small and thus leads to less power consumption.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

3D modeling of dual-gate FinFET.

PubMed

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-13

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

3D modeling of dual-gate FinFET

NASA Astrophysics Data System (ADS)

Mil'shtein, Samson; Devarakonda, Lalitha; Zanchi, Brian; Palma, John

2012-11-01

The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at V g1 > V g2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth.

PubMed

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-12-12

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm 2 /Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now.

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth

PubMed Central

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-01-01

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm2/Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now. PMID:27941825

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth

NASA Astrophysics Data System (ADS)

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-12-01

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm2/Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now.

Ferroelectricity in Covalently functionalized Two-dimensional Materials: Integration of High-mobility Semiconductors and Nonvolatile Memory.

PubMed

Wu, Menghao; Dong, Shuai; Yao, Kailun; Liu, Junming; Zeng, Xiao Cheng

2016-11-09

Realization of ferroelectric semiconductors by conjoining ferroelectricity with semiconductors remains a challenging task because most present-day ferroelectric materials are unsuitable for such a combination due to their wide bandgaps. Herein, we show first-principles evidence toward the realization of a new class of two-dimensional (2D) ferroelectric semiconductors through covalent functionalization of many prevailing 2D materials. Members in this new class of 2D ferroelectric semiconductors include covalently functionalized germanene, and stanene (Nat. Commun. 2014, 5, 3389), as well as MoS 2 monolayer (Nat. Chem. 2015, 7, 45), covalent functionalization of the surface of bulk semiconductors such as silicon (111) (J. Phys. Chem. B 2006, 110 , 23898), and the substrates of oxides such as silica with self-assembly monolayers (Nano Lett. 2014, 14, 1354). The newly predicted 2D ferroelectric semiconductors possess high mobility, modest bandgaps, and distinct ferroelectricity that can be exploited for developing various heterostructural devices with desired functionalities. For example, we propose applications of the 2D materials as 2D ferroelectric field-effect transistors with ultrahigh on/off ratio, topological transistors with Dirac Fermions switchable between holes and electrons, ferroelectric junctions with ultrahigh electro-resistance, and multiferroic junctions for controlling spin by electric fields. All these heterostructural devices take advantage of the combination of high-mobility semiconductors with fast writing and nondestructive reading capability of nonvolatile memory, thereby holding great potential for the development of future multifunctional devices.

Electrical characteristics of multilayer MoS2 FET's with MoS2/graphene heterojunction contacts.

PubMed

Kwak, Joon Young; Hwang, Jeonghyun; Calderon, Brian; Alsalman, Hussain; Munoz, Nini; Schutter, Brian; Spencer, Michael G

2014-08-13

The electrical properties of multilayer MoS2/graphene heterojunction transistors are investigated. Temperature-dependent I-V measurements indicate the concentration of unintentional donors in exfoliated MoS2 to be 3.57 × 10(11) cm(-2), while the ionized donor concentration is determined as 3.61 × 10(10) cm(-2). The temperature-dependent measurements also reveal two dominant donor levels, one at 0.27 eV below the conduction band and another located at 0.05 eV below the conduction band. The I-V characteristics are asymmetric with drain bias voltage and dependent on the junction used for the source or drain contact. I-V characteristics of the device are consistent with a long channel one-dimensional field-effect transistor model with Schottky contact. Utilizing devices, which have both graphene/MoS2 and Ti/MoS2 contacts, the Schottky barrier heights of both interfaces are measured. The charge transport mechanism in both junctions was determined to be either thermionic-field emission or field emission depending on bias voltage and temperature. On the basis of a thermionic field emission model, the barrier height at the graphene/MoS2 interface was determined to be 0.23 eV, while the barrier height at the Ti/MoS2 interface was 0.40 eV. The value of Ti/MoS2 barrier is higher than previously reported values, which did not include the effects of thermionic field emission.

Ferroelectric-Domain-Patterning-Controlled Schottky Junction State in Monolayer MoS 2

DOE PAGES

Xiao, Zhiyong; Song, Jingfeng; Ferry, David K.; ...

2017-06-08

Here, we exploit scanning probe controlled domain patterning in a ferroelectric top-layer to induce nonvolatile modulation of the conduction characteristic of monolayer MoS 2 between a transistor and a junction state. In the presence of a domain wall, MoS 2 exhibits rectified I-V that is well described by the thermionic emission model. The induced Schottky barrier height Φ eff Β varies from 0.38 eV to 0.57 eV and is tunabe by a SiO 2 global back-gate, while the tuning range of Φ eff Β the barrier height depends sensitively on the conduction band tail trapping states. Our work points tomore » a new route to achieve programmable functionalities in van der Waals materials and sheds light on the critical performance limiting factors in these hybrid systems.« less

Single Molecule Electronics and Devices

PubMed Central

Tsutsui, Makusu; Taniguchi, Masateru

2012-01-01

The manufacture of integrated circuits with single-molecule building blocks is a goal of molecular electronics. While research in the past has been limited to bulk experiments on self-assembled monolayers, advances in technology have now enabled us to fabricate single-molecule junctions. This has led to significant progress in understanding electron transport in molecular systems at the single-molecule level and the concomitant emergence of new device concepts. Here, we review recent developments in this field. We summarize the methods currently used to form metal-molecule-metal structures and some single-molecule techniques essential for characterizing molecular junctions such as inelastic electron tunnelling spectroscopy. We then highlight several important achievements, including demonstration of single-molecule diodes, transistors, and switches that make use of electrical, photo, and mechanical stimulation to control the electron transport. We also discuss intriguing issues to be addressed further in the future such as heat and thermoelectric transport in an individual molecule. PMID:22969345

Reinventing solid state electronics: Harnessing quantum confinement in bismuth thin films

NASA Astrophysics Data System (ADS)

Gity, Farzan; Ansari, Lida; Lanius, Martin; Schüffelgen, Peter; Mussler, Gregor; Grützmacher, Detlev; Greer, J. C.

2017-02-01

Solid state electronics relies on the intentional introduction of impurity atoms or dopants into a semiconductor crystal and/or the formation of junctions between different materials (heterojunctions) to create rectifiers, potential barriers, and conducting pathways. With these building blocks, switching and amplification of electrical currents and voltages are achieved. As miniaturisation continues to ultra-scaled transistors with critical dimensions on the order of ten atomic lengths, the concept of doping to form junctions fails and forming heterojunctions becomes extremely difficult. Here, it is shown that it is not needed to introduce dopant atoms nor is a heterojunction required to achieve the fundamental electronic function of current rectification. Ideal diode behavior or rectification is achieved solely by manipulation of quantum confinement using approximately 2 nm thick films consisting of a single atomic element, the semimetal bismuth. Crucially for nanoelectronics, this approach enables room temperature operation.

Strain-enhanced tunneling magnetoresistance in MgO magnetic tunnel junctions

PubMed Central

Loong, Li Ming; Qiu, Xuepeng; Neo, Zhi Peng; Deorani, Praveen; Wu, Yang; Bhatia, Charanjit S.; Saeys, Mark; Yang, Hyunsoo

2014-01-01

While the effects of lattice mismatch-induced strain, mechanical strain, as well as the intrinsic strain of thin films are sometimes detrimental, resulting in mechanical deformation and failure, strain can also be usefully harnessed for applications such as data storage, transistors, solar cells, and strain gauges, among other things. Here, we demonstrate that quantum transport across magnetic tunnel junctions (MTJs) can be significantly affected by the introduction of controllable mechanical strain, achieving an enhancement factor of ~2 in the experimental tunneling magnetoresistance (TMR) ratio. We further correlate this strain-enhanced TMR with coherent spin tunneling through the MgO barrier. Moreover, the strain-enhanced TMR is analyzed using non-equilibrium Green's function (NEGF) quantum transport calculations. Our results help elucidate the TMR mechanism at the atomic level and can provide a new way to enhance, as well as tune, the quantum properties in nanoscale materials and devices. PMID:25266219

Ferroelectric-Domain-Patterning-Controlled Schottky Junction State in Monolayer MoS 2

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiao, Zhiyong; Song, Jingfeng; Ferry, David K.

Here, we exploit scanning probe controlled domain patterning in a ferroelectric top-layer to induce nonvolatile modulation of the conduction characteristic of monolayer MoS 2 between a transistor and a junction state. In the presence of a domain wall, MoS 2 exhibits rectified I-V that is well described by the thermionic emission model. The induced Schottky barrier height Φ eff Β varies from 0.38 eV to 0.57 eV and is tunabe by a SiO 2 global back-gate, while the tuning range of Φ eff Β the barrier height depends sensitively on the conduction band tail trapping states. Our work points tomore » a new route to achieve programmable functionalities in van der Waals materials and sheds light on the critical performance limiting factors in these hybrid systems.« less

High-performance passive microwave survey on Josephson Junctions

NASA Technical Reports Server (NTRS)

Denisov, A. G.; Radzikhovsky, V. N.; Kudeliya, A. M.

1995-01-01

The quasi-optical generations of images of objects with their internal structure in millimeter (MM) and submillimeter (SMM) bands is one of prime problems of modern radioelectronics. The main advantage of passive MM imaging systems in comparison with visible and infrared (IR) systems is small attenuation of signals in fog, cloud, smoke, dust and other obscurants. However, at a panoramic scanning of space the observation time lengthens and thereby the information processing rate becomes restricted so that single-channel system cannot image in real time. Therefore we must use many radiometers in parallel to reduce the observation time. Such system must contain receiving sensors as pixels in multibeam antenna. The use of Josephson Junctions (JJ) for this purpose together with the cryoelectronic devices like GaAs FET (field effect transistors) or SQUIDS for signal amplifications after JJ is of particular interest in this case.

NANOELECTRONICS. Epitaxial growth of a monolayer WSe2-MoS2 lateral p-n junction with an atomically sharp interface.

PubMed

Li, Ming-Yang; Shi, Yumeng; Cheng, Chia-Chin; Lu, Li-Syuan; Lin, Yung-Chang; Tang, Hao-Lin; Tsai, Meng-Lin; Chu, Chih-Wei; Wei, Kung-Hwa; He, Jr-Hau; Chang, Wen-Hao; Suenaga, Kazu; Li, Lain-Jong

2015-07-31

Two-dimensional transition metal dichalcogenides (TMDCs) such as molybdenum sulfide MoS2 and tungsten sulfide WSe2 have potential applications in electronics because they exhibit high on-off current ratios and distinctive electro-optical properties. Spatially connected TMDC lateral heterojunctions are key components for constructing monolayer p-n rectifying diodes, light-emitting diodes, photovoltaic devices, and bipolar junction transistors. However, such structures are not readily prepared via the layer-stacking techniques, and direct growth favors the thermodynamically preferred TMDC alloys. We report the two-step epitaxial growth of lateral WSe2-MoS2 heterojunction, where the edge of WSe2 induces the epitaxial MoS2 growth despite a large lattice mismatch. The epitaxial growth process offers a controllable method to obtain lateral heterojunction with an atomically sharp interface. Copyright © 2015, American Association for the Advancement of Science.

Electronic Model of a Ferroelectric Field Effect Transistor

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen; Russell, Larry (Technical Monitor)

2001-01-01

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

Novel H+-Ion Sensor Based on a Gated Lateral BJT Pair

PubMed Central

Yuan, Heng; Zhang, Jixing; Cao, Chuangui; Zhang, Gangyuan; Zhang, Shaoda

2015-01-01

An H+-ion sensor based on a gated lateral bipolar junction transistor (BJT) pair that can operate without the classical reference electrode is proposed. The device is a special type of ion-sensitive field-effect transistor (ISFET). Classical ISFETs have the advantage of miniaturization, but  they are difficult to fabricate by a single fabrication process because of the bulky and brittle reference electrode materials. Moreover, the reference electrodes need to be separated from the sensor device in some cases. The proposed device is composed of two gated lateral BJT components, one of which had a silicide layer while the other was without the layer. The two components were operated under the metal-oxide semiconductor field-effect transistor (MOSFET)-BJT hybrid mode, which can be controlled by emitter voltage and base current. Buffer solutions with different pH values were used as the sensing targets to verify the characteristics of the proposed device. Owing to their different sensitivities, both components could simultaneously detect the H+-ion concentration and function as a reference to each other. Per the experimental results, the sensitivity of the proposed device was found to be approximately 0.175 μA/pH. This experiment demonstrates enormous potential to lower the cost of the ISFET-based sensor technology. PMID:26703625

Spintronic logic: from switching devices to computing systems

NASA Astrophysics Data System (ADS)

Friedman, Joseph S.

2017-09-01

Though numerous spintronic switching devices have been proposed or demonstrated, there has been significant difficulty in translating these advances into practical computing systems. The challenge of cascading has impeded the integration of multiple devices into a logic family, and several proposed solutions potentially overcome these challenges. Here, the cascading techniques by which the output of each spintronic device can drive the input of another device are described for several logic families, including spin-diode logic (in particular, all-carbon spin logic), complementary magnetic tunnel junction logic (CMAT), and emitter-coupled spin-transistor logic (ECSTL).

Total Ionizing Dose Effects on Ge Channel $p$FETs with Raised $${\\rm Si}_{0.55}{\\rm Ge}_{0.45}$$ Source/Drain

DOE PAGES

Wang, Liang; Zhang, En Xia; Schrimpf, Ronald D.; ...

2015-12-17

Here, the total ionizing dose response of Ge channel pFETs with raised Si 0.55Ge 0.45 source/drain is investigated under different radiation bias conditions. Threshold-voltage shifts and transconductance degradation are noticeable only for negative-bias (on state) irradiation, and are mainly due to negative bias-temperature instability (NBTI). Nonmonotonic leakage changes during irradiation are observed, which are attributed to the competition of radiation-induced field transistor leakage and S/D junction leakage.

A Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance

DTIC Science & Technology

2012-10-01

right by a pitch (P) and subsequently summed to provide a multi-gate superimposed temperature distribution ( TMG (x)). An example is shown in figure...temperature rise over the coolant, or the difference between the centerline multi gate junction temperature on the upper surface ( TMG ,GaN(0)) of the GaN...TC coolant temperature (°C) TCP(x) cold plate temperature distribution (°C) TGaN(x,y) temperature distribution within GaN (°C) TMG (x) multiple gate

Cryogenic photodetectors

NASA Astrophysics Data System (ADS)

Chardin, G.

2000-03-01

Some of the most significant developments in cryogenic photodetectors are presented. In particular, the main characteristics of microbolometers involving Transition Edge- and NTD-sensors and offering resolutions of a few eV in the keV range, superconducting tunnel junction detectors with resolutions of the order of 10 eV or offering position sensitivity, and infrared bolometers with recent developments towards matrix detectors are discussed. Some of the recent achievements using large mass bolometers for gamma and neutron discriminating detectors, and future prospects of single photon detection in the far infrared using Single Electron Transistor devices are also presented.

W-band six-port network analyzer for two-port characterization of millimeter wave transistors

NASA Technical Reports Server (NTRS)

Moeller, Karl J.; Schaffner, James H.; Fetterman, Harold R.

1989-01-01

A W-band (75-100 GHz) six-port junction network analyzer was constructed from commercially available descrete waveguide components and was used for the direct two-port S-parameter measurement of active three-terminal devices. A comparison between the six-port and a down-converter-type frequency extender for a conventional network analyzer revealed the superior performance of the six-port. The application of the six-port to characterize a 0.1-micron gate-length HEMT at W-band is described, and representative results are presented.

Tuning electronic transport in epitaxial graphene-based van der Waals heterostructures

NASA Astrophysics Data System (ADS)

Lin, Yu-Chuan; Li, Jun; de La Barrera, Sergio C.; Eichfeld, Sarah M.; Nie, Yifan; Addou, Rafik; Mende, Patrick C.; Wallace, Robert M.; Cho, Kyeongjae; Feenstra, Randall M.; Robinson, Joshua A.

2016-04-01

Two-dimensional tungsten diselenide (WSe2) has been used as a component in atomically thin photovoltaic devices, field effect transistors, and tunneling diodes in tandem with graphene. In some applications it is necessary to achieve efficient charge transport across the interface of layered WSe2-graphene, a semiconductor to semimetal junction with a van der Waals (vdW) gap. In such cases, band alignment engineering is required to ensure a low-resistance, ohmic contact. In this work, we investigate the impact of graphene electronic properties on the transport at the WSe2-graphene interface. Electrical transport measurements reveal a lower resistance between WSe2 and fully hydrogenated epitaxial graphene (EGFH) compared to WSe2 grown on partially hydrogenated epitaxial graphene (EGPH). Using low-energy electron microscopy and reflectivity on these samples, we extract the work function difference between the WSe2 and graphene and employ a charge transfer model to determine the WSe2 carrier density in both cases. The results indicate that WSe2-EGFH displays ohmic behavior at small biases due to a large hole density in the WSe2, whereas WSe2-EGPH forms a Schottky barrier junction.Two-dimensional tungsten diselenide (WSe2) has been used as a component in atomically thin photovoltaic devices, field effect transistors, and tunneling diodes in tandem with graphene. In some applications it is necessary to achieve efficient charge transport across the interface of layered WSe2-graphene, a semiconductor to semimetal junction with a van der Waals (vdW) gap. In such cases, band alignment engineering is required to ensure a low-resistance, ohmic contact. In this work, we investigate the impact of graphene electronic properties on the transport at the WSe2-graphene interface. Electrical transport measurements reveal a lower resistance between WSe2 and fully hydrogenated epitaxial graphene (EGFH) compared to WSe2 grown on partially hydrogenated epitaxial graphene (EGPH). Using low-energy electron microscopy and reflectivity on these samples, we extract the work function difference between the WSe2 and graphene and employ a charge transfer model to determine the WSe2 carrier density in both cases. The results indicate that WSe2-EGFH displays ohmic behavior at small biases due to a large hole density in the WSe2, whereas WSe2-EGPH forms a Schottky barrier junction. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr01902a

Charge transport with single molecules--an electrochemical approach.

PubMed

Li, Chen; Mishchenko, Artem; Pobelov, Ilya; Wandlowski, Thomas

2010-01-01

After an introduction and brief review of charge transport in nanoscale molecular systems we report on experimental studies in gold / (single) molecule / gold junctions at solid / liquid interfaces employing a scanning tunneling microscopy (STM)-based 'break junction' technique. We demonstrate attempts in developing basic relationships between molecular structure, conductance properties and nanoscale electrochemical concepts based on four case studies from our own work. In experiments with alpha, omega-alkanedithiol and biphenyldithiol molecular junctions we address the role of sulfur-gold couplings and molecular conformation, such as gauche defects in the alkyl chains and the torsion angle between two phenyl rings. Combination with quantum chemistry calculations enabled a detailed molecular-level understanding of the electronic structure and transport characteristics of both systems. Employing the concept of 'electrolyte gating' with redox-active molecules, such as thiol-terminated derivatives of viologens (HS-6V6-SH or (HS-6V6)) we demonstrate the construction of symmetric and asymmetric active molecular junctions with transistor- or diode-like behavior upon polarization in an electrochemical environment. The experimental data could be represented quantitatively by the Kutznetsov/Ulstrup model assuming a two-step electron transfer with partial vibration relaxation. Finally, we show that surface-immobilized gold nanoparticles with a diameter of (2.4 +/- 0.5) nm exhibit features of locally addressable multi-state electronic switching upon electrolyte gating, which appears to be reminiscent of a sequential charging through several 'oxidation/reduction states'.

A Simple Method for Decreasing the Liquid Junction Potential in a Flow-through-Type Differential pH Sensor Probe Consisting of pH-FETs by Exerting Spatiotemporal Control of the Liquid Junction

PubMed Central

Yamada, Akira; Mohri, Satoshi; Nakamura, Michihiro; Naruse, Keiji

2015-01-01

The liquid junction potential (LJP), the phenomenon that occurs when two electrolyte solutions of different composition come into contact, prevents accurate measurements in potentiometry. The effect of the LJP is usually remarkable in measurements of diluted solutions with low buffering capacities or low ion concentrations. Our group has constructed a simple method to eliminate the LJP by exerting spatiotemporal control of a liquid junction (LJ) formed between two solutions, a sample solution and a baseline solution (BLS), in a flow-through-type differential pH sensor probe. The method was contrived based on microfluidics. The sensor probe is a differential measurement system composed of two ion-sensitive field-effect transistors (ISFETs) and one Ag/AgCl electrode. With our new method, the border region of the sample solution and BLS is vibrated in order to mix solutions and suppress the overshoot after the sample solution is suctioned into the sensor probe. Compared to the conventional method without vibration, our method shortened the settling time from over two min to 15 s and reduced the measurement error by 86% to within 0.060 pH. This new method will be useful for improving the response characteristics and decreasing the measurement error of many apparatuses that use LJs. PMID:25835300

Schottky barrier contrasts in single and bi-layer graphene contacts for MoS{sub 2} field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Du, Hyewon; Kim, Taekwang; Shin, Somyeong

We have investigated single- and bi-layer graphene as source-drain electrodes for n-type MoS{sub 2} transistors. Ti-MoS{sub 2}-graphene heterojunction transistors using both single-layer MoS{sub 2} (1M) and 4-layer MoS{sub 2} (4M) were fabricated in order to compare graphene electrodes with commonly used Ti electrodes. MoS{sub 2}-graphene Schottky barrier provided electron injection efficiency up to 130 times higher in the subthreshold regime when compared with MoS{sub 2}-Ti, which resulted in V{sub DS} polarity dependence of device parameters such as threshold voltage (V{sub TH}) and subthreshold swing (SS). Comparing single-layer graphene (SG) with bi-layer graphene (BG) in 4M devices, SG electrodes exhibited enhancedmore » device performance with higher on/off ratio and increased field-effect mobility (μ{sub FE}) due to more sensitive Fermi level shift by gate voltage. Meanwhile, in the strongly accumulated regime, we observed opposing behavior depending on MoS{sub 2} thickness for both SG and BG contacts. Differential conductance (σ{sub d}) of 1M increases with V{sub DS} irrespective of V{sub DS} polarity, while σ{sub d} of 4M ceases monotonic growth at positive V{sub DS} values transitioning to ohmic-like contact formation. Nevertheless, the low absolute value of σ{sub d} saturation of the 4M-graphene junction demonstrates that graphene electrode could be unfavorable for high current carrying transistors.« less

Flexible Organic Electronics in Biology: Materials and Devices.

PubMed

Liao, Caizhi; Zhang, Meng; Yao, Mei Yu; Hua, Tao; Li, Li; Yan, Feng

2015-12-09

At the convergence of organic electronics and biology, organic bioelectronics attracts great scientific interest. The potential applications of organic semiconductors to reversibly transmit biological signals or stimulate biological tissues inspires many research groups to explore the use of organic electronics in biological systems. Considering the surfaces of movable living tissues being arbitrarily curved at physiological environments, the flexibility of organic bioelectronic devices is of paramount importance in enabling stable and reliable performances by improving the contact and interaction of the devices with biological systems. Significant advances in flexible organic bio-electronics have been achieved in the areas of flexible organic thin film transistors (OTFTs), polymer electrodes, smart textiles, organic electrochemical ion pumps (OEIPs), ion bipolar junction transistors (IBJTs) and chemiresistors. This review will firstly discuss the materials used in flexible organic bioelectronics, which is followed by an overview on various types of flexible organic bioelectronic devices. The versatility of flexible organic bioelectronics promises a bright future for this emerging area. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Scaling and Graphical Transport-Map Analysis of Ambipolar Schottky-Barrier Thin-Film Transistors Based on a Parallel Array of Si Nanowires.

PubMed

Jeon, Dae-Young; Pregl, Sebastian; Park, So Jeong; Baraban, Larysa; Cuniberti, Gianaurelio; Mikolajick, Thomas; Weber, Walter M

2015-07-08

Si nanowire (Si-NW) based thin-film transistors (TFTs) have been considered as a promising candidate for next-generation flexible and wearable electronics as well as sensor applications with high performance. Here, we have fabricated ambipolar Schottky-barrier (SB) TFTs consisting of a parallel array of Si-NWs and performed an in-depth study related to their electrical performance and operation mechanism through several electrical parameters extracted from the channel length scaling based method. Especially, the newly suggested current-voltage (I-V) contour map clearly elucidates the unique operation mechanism of the ambipolar SB-TFTs, governed by Schottky-junction between NiSi2 and Si-NW. Further, it reveals for the first-time in SB based FETs the important internal electrostatic coupling between the channel and externally applied voltages. This work provides helpful information for the realization of practical circuits with ambipolar SB-TFTs that can be transferred to different substrate technologies and applications.

An ion-gated bipolar amplifier for ion sensing with enhanced signal and improved noise performance

NASA Astrophysics Data System (ADS)

Zhang, Da; Gao, Xindong; Chen, Si; Norström, Hans; Smith, Ulf; Solomon, Paul; Zhang, Shi-Li; Zhang, Zhen

2014-08-01

This work presents a proof-of-concept ion-sensitive device operating in electrolytes. The device, i.e., an ion-gated bipolar amplifier (IGBA), consists of a modified ion-sensitive field-effect transistor (ISFET) intimately integrated with a vertical bipolar junction transistor for immediate current amplification without introducing additional noise. With the current non-optimized design, the IGBA is already characterized by a 70-fold internal amplification of the ISFET output signal. This signal amplification is retained when the IGBA is used for monitoring pH variations. The tight integration significantly suppresses the interference of the IGBA signal by external noise, which leads to an improvement in signal-to-noise performance compared to its ISFET reference. The IGBA concept is especially suitable for biochips with millions of electric sensors that are connected to peripheral readout circuitry via extensive metallization which may in turn invite external interferences leading to contamination of the signal before it reaches the first external amplification stage.

Characterization of high-dose and high-energy implanted gate and source diode and analysis of lateral spreading of p gate profile in high voltage SiC static induction transistors

NASA Astrophysics Data System (ADS)

Onose, Hidekatsu; Kobayashi, Yutaka; Onuki, Jin

2017-03-01

The effect of the p gate dose on the characteristics of the gate-source diode in SiC static induction transistors (SIT) was investigated. It was found that a dose of 1.5 × 1014 cm-2 yields a pn junction breakdown voltage higher than 60 V and good forward characteristics. A normally on SiC SIT was fabricated and demonstrated. A blocking voltage higher than 2.0 kV at a gate-source voltage of -50 V and on-resistance of 70 mΩ cm2 were obtained. Device simulations were performed to investigate the effect of the lateral spreading. By comparing the measured I-V curves with simulation results, the lateral spreading factor was estimated to be about 0.5. The lateral spreading detrimentally affected the electrical properties of the SIT made using implantations at energies higher than 1 MeV.

Component technology for space power systems

NASA Technical Reports Server (NTRS)

Finke, R. C.

1982-01-01

Progress made by NASA toward implementation of equipment for the conversion, management, and distribution of voltage power in space applications are reviewed. Work has been carried forward on components such as bipolar transistors, deep impurity semiconductors, conductors, dielectrics, magnetic devices, and rotary power transfer. Specific programs for the high voltage systems have included research on lightweight, low-cost conductors featuring graphite fibers containing electron donor materials for wires and cables with reduced mass and the conductivity of copper. Attention has also been given p-n junction technology for high-speed, high-current, high-voltage materials and diamond-like dielectric films which are hard, have high dielectric strength, and can operate up to 300 C. A transistor has been fabricated with a voltage of 1200 V at 100 A, with a gain of 10 and a 0.5 microsec rise/fall time. A 25 kW transformer has also been built which performs at 20 kHz with an efficiency of 99.2%.

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

NASA Astrophysics Data System (ADS)

Dhakras, Prathamesh; Agnihotri, Pratik; Lee, Ji Ung

2017-06-01

The three pillars of semiconductor device technologies are (1) the p-n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

Improved transfer of graphene for gated Schottky-junction, vertical, organic, field-effect transistors.

PubMed

Lemaitre, Maxime G; Donoghue, Evan P; McCarthy, Mitchell A; Liu, Bo; Tongay, Sefaattin; Gila, Brent; Kumar, Purushottam; Singh, Rajiv K; Appleton, Bill R; Rinzler, Andrew G

2012-10-23

An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.

Carbon doping in molecular beam epitaxy of GaAs from a heated graphite filament

NASA Technical Reports Server (NTRS)

Malik, R. J.; Nottenberg, R. N.; Schubert, E. F.; Walker, J. F.; Ryan, R. W.

1988-01-01

Carbon doping of GaAs grown by molecular beam epitaxy has been obtained for the first time by use of a heated graphite filament. Controlled carbon acceptor concentrations over the range of 10 to the 17th-10 to the 20th/cu cm were achieved by resistively heating a graphite filament with a direct current power supply. Capacitance-voltage, p/n junction and secondary-ion mass spectrometry measurements indicate that there is negligible diffusion of carbon during growth and with postgrowth rapid thermal annealing. Carbon was used for p-type doping in the base of Npn AlGaAs/GaAs heterojunction bipolar transistors. Current gains greater than 100 and near-ideal emitter heterojunctions were obtained in transistors with a carbon base doping of 1 x 10 to the 19th/cu cm. These preliminary results indicate that carbon doping from a solid graphite source may be an attractive substitute for beryllium, which is known to have a relatively high diffusion coefficient in GaAs.

A simplified boron diffusion for preparing the silicon single crystal p-n junction as an educational device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shiota, Koki, E-mail: a14510@sr.kagawa-nct.ac.jp; Kai, Kazuho; Nagaoka, Shiro, E-mail: nagaoka@es.kagawa-nct.ac.jp

The educational method which is including designing, making, and evaluating actual semiconductor devices with learning the theory is one of the best way to obtain the fundamental understanding of the device physics and to cultivate the ability to make unique ideas using the knowledge in the semiconductor device. In this paper, the simplified Boron thermal diffusion process using Sol-Gel material under normal air environment was proposed based on simple hypothesis and the feasibility of the reproducibility and reliability were investigated to simplify the diffusion process for making the educational devices, such as p-n junction, bipolar and pMOS devices. As themore » result, this method was successfully achieved making p+ region on the surface of the n-type silicon substrates with good reproducibility. And good rectification property of the p-n junctions was obtained successfully. This result indicates that there is a possibility to apply on the process making pMOS or bipolar transistors. It suggests that there is a variety of the possibility of the applications in the educational field to foster an imagination of new devices.« less

Electronic components embedded in a single graphene nanoribbon.

PubMed

Jacobse, P H; Kimouche, A; Gebraad, T; Ervasti, M M; Thijssen, J M; Liljeroth, P; Swart, I

2017-07-25

The use of graphene in electronic devices requires a band gap, which can be achieved by creating nanostructures such as graphene nanoribbons. A wide variety of atomically precise graphene nanoribbons can be prepared through on-surface synthesis, bringing the concept of graphene nanoribbon electronics closer to reality. For future applications it is beneficial to integrate contacts and more functionality directly into single ribbons by using heterostructures. Here, we use the on-surface synthesis approach to fabricate a metal-semiconductor junction and a tunnel barrier in a single graphene nanoribbon consisting of 5- and 7-atom wide segments. We characterize the atomic scale geometry and electronic structure by combined atomic force microscopy, scanning tunneling microscopy, and conductance measurements complemented by density functional theory and transport calculations. These junctions are relevant for developing contacts in all-graphene nanoribbon devices and creating diodes and transistors, and act as a first step toward complete electronic devices built into a single graphene nanoribbon.Adding functional electronic components to graphene nanoribbons requires precise control over their atomic structure. Here, the authors use a bottom-up approach to build a metal-semiconductor junction and a tunnel barrier directly into a single graphene nanoribbon, an exciting development for graphene-based electronic devices.

Investigation of dielectric pocket induced variations in tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Upasana; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

2016-04-01

The performance of conventional Tunnel FETs struggling from ambipolar issues, insufficient on-current, lower transconductance value, higher delay and lower cut off frequency has been improved by introducing several material and device engineering concepts in past few years. Keeping this in view, another interesting and reliable option i.e. Dielectric Pocket TFET (featuring a dielectric pocket placement near tunneling junction) has been comprehensively and qualitatively demonstrated using ATLAS device simulator. The architecture has been explored in terms of various device electrostatic parameters such as potential, energy band profile, electron and hole concentration, electric field variation and band to band generation rate (GBTB) near the tunneling junction where the Dielectric Pocket (DP) has been introduced. Subsequently, a detailed investigation by changing the position and dielectric constant of pocket at respective junctions has been made where DP induced variations in drain current, transconductance and parasitic capacitance have been examined. The work highlights major improvements over conventional TFET in terms of lower subthreshold swing and threshold voltage, higher drain current and transconductance, improved on-to-off current ratio, suppressed ambipolar conduction and improved dynamic power dissipation issues for low voltage analog and digital applications.

Metallic Electrode: Semiconducting Nanotube Junction Model

NASA Technical Reports Server (NTRS)

Yamada, Toshishige; Biegel, Bryon (Technical Monitor)

2001-01-01

A model is proposed for two observed current-voltage (I-V) patterns in an experiment with a scanning tunneling microscope tip and a carbon nanotube [Collins et al., Science 278, 100 ('97)]. We claim that there are two contact modes for a tip (metal) -nanotube semi conductor) junction depending whether the alignment of the metal and semiconductor band structure is (1) variable (vacuum-gap) or (2) fixed (touching) with V. With the tip grounded, the tunneling case in (1) would produce large dI/dV with V > 0, small dI/dV with V < 0, and I = 0 near V = 0 for an either n- or p-nanotube. However, the Schottky mechanism in (2) would result in forward current with V < 0 for an n-nanotube, while with V > 0 for an p-nanotube. The two observed I-V patterns are thus entirely explained by a tip-nanotube contact of the two types, where the nanotube must be n-type. We apply this picture to the source-drain I-V characteristics in a long nanotube-channel field-effect-transistor (Zhou et al., Appl. Phys. Lett. 76, 1597 ('00)], and show that two independent metal-semiconductor junctions connected in series are responsible for the observed behavior.

Long-Term Reliability of SiGe/Si HBTs From Accelerated Lifetime Testing

NASA Technical Reports Server (NTRS)

Bhattacharya, Pallab

2001-01-01

Accelerated lifetime tests were performed on double-mesa structure Si(0.7)Ge(0.3)/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175 C-275 C. The transistors (with 5x20 sq micron emitter area) have DC current gains approx. 40-50 and f(sub T) and f(sub max) of up to 22 GHz and 25 GHz, respectively. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REED has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of these devices at room temperature under 1.35 x 10(exp 4) A/sq cm current density operation is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Developing the OEIC solutions using two section light-emitting transistor

NASA Astrophysics Data System (ADS)

Liang, Shan-Fong; Hsu, Yuan-Fu; Cheng, Gong-Sheng; Wu, Chao-Hsin

2016-02-01

An integrated on-chip optical device composed of a multiple quantum-well light-emitter and photodetector in the lightemitting transistor (LET) platform is fabricated. The two devices are 400 μm in length and electrically isolated by dry etching with 4.9 μm gap. The two facets are formed by cleaving for optical output. In this report, we discuss the characteristics of the two-section device and demonstrate the optical detection by the heterojunction phototransistor (HPT) under different operation points (IB and VCE) and injected optical powers. The collector current of the HPT is 74.88 mA without illumination and 83.87 mA under illumination of 7.46μW at VCE = 3 V and IB = 12 mA, which exhibits 12% increment. The responsivity of the InGaP/GaAs HPT can reach to 711.74 A/W. At the electrical modulation bandwidth of phototransistor fT is enhanced from 1.4 GHz to 1.51 GHz under illumination. This is attributed to the Franz-Keldysh photon-assisted absorption at base-collector junction of light-emitting transistor, which produces additional holes and electrons to enhance the current gain. Through the analysis of small-signal equivalent circuit models, we can show the transit time by de-embedding the circuit parasitic effect. Extracting those parameters can clearly know the thermionic emission lifetime in the quantum well.

Catching the electron in action in real space inside a Ge-Si core-shell nanowire transistor.

PubMed

Jaishi, Meghnath; Pati, Ranjit

2017-09-21

Catching the electron in action in real space inside a semiconductor Ge-Si core-shell nanowire field effect transistor (FET), which has been demonstrated (J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature, 2006, 441, 489) to outperform the state-of-the-art metal oxide semiconductor FET, is central to gaining unfathomable access into the origin of its functionality. Here, using a quantum transport approach that does not make any assumptions on electronic structure, charge, and potential profile of the device, we unravel the most probable tunneling pathway for electrons in a Ge-Si core-shell nanowire FET with orbital level spatial resolution, which demonstrates gate bias induced decoupling of electron transport between the core and the shell region. Our calculation yields excellent transistor characteristics as noticed in the experiment. Upon increasing the gate bias beyond a threshold value, we observe a rapid drop in drain current resulting in a gate bias driven negative differential resistance behavior and switching in the sign of trans-conductance. We attribute this anomalous behavior in drain current to the gate bias induced modification of the carrier transport pathway from the Ge core to the Si shell region of the nanowire channel. A new experiment involving a four probe junction is proposed to confirm our prediction on gate bias induced decoupling.

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2016-01-01

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T = 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

Digitally gain controlled linear high voltage amplifier for laboratory applications.

PubMed

Koçum, C

2011-08-01

The design of a digitally gain controlled high-voltage non-inverting bipolar linear amplifier is presented. This cost efficient and relatively simple circuit has stable operation range from dc to 90 kHz under the load of 10 kΩ and 39 pF. The amplifier can swing up to 360 V(pp) under these conditions and it has 2.5 μs rise time. The gain can be changed by the aid of JFETs. The amplifiers have been realized using a combination of operational amplifiers and high-voltage discrete bipolar junction transistors. The circuit details and performance characteristics are discussed.

High performance thyratron driver with low jitter.

PubMed

Verma, Rishi; Lee, P; Springham, S V; Tan, T L; Rawat, R S

2007-08-01

We report the design and development of insulated gate bipolar junction transistor based high performance driver for operating thyratrons in grounded grid mode. With careful design, the driver meets the specification of trigger output pulse rise time less than 30 ns, jitter less than +/-1 ns, and time delay less than 160 ns. It produces a -600 V pulse of 500 ns duration (full width at half maximum) at repetition rate ranging from 1 Hz to 1.14 kHz. The developed module also facilitates heating and biasing units along with protection circuitry in one complete package.

Stacking fault induced tunnel barrier in platelet graphite nanofiber

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lan, Yann-Wen, E-mail: chiidong@phys.sinica.edu.tw, E-mail: ywlan@phys.sinica.edu.tw; Chang, Yuan-Chih; Chang, Chia-Seng

A correlation study using image inspection and electrical characterization of platelet graphite nanofiber devices is conducted. Close transmission electron microscopy and diffraction pattern inspection reveal layers with inflection angles appearing in otherwise perfectly stacked graphene platelets, separating nanofibers into two domains. Electrical measurement gives a stability diagram consisting of alternating small-large Coulomb blockade diamonds, suggesting that there are two charging islands coupled together through a tunnel junction. Based on these two findings, we propose that a stacking fault can behave as a tunnel barrier for conducting electrons and is responsible for the observed double-island single electron transistor characteristics.

Laser induced forward transfer of graphene

NASA Astrophysics Data System (ADS)

Smits, Edsger C. P.; Walter, Arnaud; de Leeuw, Dago M.; Asadi, Kamal

2017-10-01

Transfer of graphene and other two-dimensional materials is still a technical challenge. The 2D-materials are typically patterned after transfer, which leads to a major loss of material. Here, we present laser induced forward transfer of chemical vapor deposition grown graphene layers with well-defined shapes and geometries. The transfer is based on photo-decomposition of a triazene-based transfer layer that produces N2 gas, which propels a graphene layer from the donor to the acceptor substrate. The functionality of the graphene-metal junction was verified by realizing functional bottom contact bottom gate field-effect transistors.

Heavy doping effects in high efficiency silicon solar cells

NASA Technical Reports Server (NTRS)

Lindholm, F. A.; Neugroschel, A.

1985-01-01

The use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells was examined. The results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contact are presented. A reciprocity theorem is presented that relates the short circuit current of a device, induced by a carrier generation source, to the minority carrier Fermi level in the dark. A method for accurate measurement of minority-carrier diffusion coefficients in silicon is described.

Long-term reliable physically unclonable function based on oxide tunnel barrier breakdown on two-transistors two-magnetic-tunnel-junctions cell-based embedded spin transfer torque magnetoresistive random access memory

NASA Astrophysics Data System (ADS)

Takaya, Satoshi; Tanamoto, Tetsufumi; Noguchi, Hiroki; Ikegami, Kazutaka; Abe, Keiko; Fujita, Shinobu

2017-04-01

Among the diverse applications of spintronics, security for internet-of-things (IoT) devices is one of the most important. A physically unclonable function (PUF) with a spin device (spin transfer torque magnetoresistive random access memory, STT-MRAM) is presented. Oxide tunnel barrier breakdown is used to realize long-term stability for PUFs. A secure PUF has been confirmed by evaluating the Hamming distance of a 32-bit STT-MRAM-PUF fabricated using 65 nm CMOS technology.

Superconducting active impedance converter

DOEpatents

Ginley, David S.; Hietala, Vincent M.; Martens, Jon S.

1993-01-01

A transimpedance amplifier for use with high temperature superconducting, other superconducting, and conventional semiconductor allows for appropriate signal amplification and impedance matching to processing electronics. The amplifier incorporates the superconducting flux flow transistor into a differential amplifier configuration which allows for operation over a wide temperature range, and is characterized by high gain, relatively low noise, and response times less than 200 picoseconds over at least a 10-80 K. temperature range. The invention is particularly useful when a signal derived from either far-IR focal plane detectors or from Josephson junctions is to be processed by higher signal/higher impedance electronics, such as conventional semiconductor technology.

A low noise single-transistor transimpedance preamplifier for Fourier-transform mass spectrometry using a T feedback network

PubMed Central

Lin, Tzu-Yung; Green, Roger J.; O’Connor, Peter B.

2012-01-01

A novel single-transistor transimpedance preamplifier has been introduced for improving performance in Fourier-transform ion cyclotron resonance (FT-ICR) mass spectrometry. A low noise junction field-effect transistor (JFET), BF862, is used as the main amplification stage of this trans-impedance preamplifier, and a T-shaped feedback network is introduced as both the feedback and the gate biasing solutions. The T feedback network has been studied using an operational amplifier (Op Amp), AD8099. Such a feedback system allows ∼100-fold less feedback resistance at a given transimpedance, hence preserving bandwidth, which is beneficial to applications demanding high gain. The single-transistor preamplifier yields a tested transimpedance of ∼104 Ω (80 dBΩ) in the frequency range between 1 kHz and 1 MHz (mass-to-charge ratio, m/z, of around 180-180k for a 12-T FT-ICR system), with a low power consumption of ∼6 mW, which implies that this preamplifier is well suited to a 12-T FT-ICR mass spectrometer. In trading noise performance for higher trans-impedance, an alternative preamplifier design, an AD8099 preamplifier with the T feedback network, has also been studied with a capability of ∼106 Ω (120 dBΩ) transimpedance in the same frequency range. The resistive components in the T feedback network reported here can be replaced by complex impedances, which allows adaptation of this feedback system to other frequency, transimpedance, and noise characteristics for applications not only in other mass spectrometers, such as Orbitrap, time-of-flight (TOF), and ion trap systems, but also in other charge/current detecting systems such as spectroscopy systems, microscopy systems, optical communication systems, or charge-coupled devices (CCDs). PMID:23020394

A low noise single-transistor transimpedance preamplifier for Fourier-transform mass spectrometry using a T feedback network.

PubMed

Lin, Tzu-Yung; Green, Roger J; O'Connor, Peter B

2012-09-01

A novel single-transistor transimpedance preamplifier has been introduced for improving performance in Fourier-transform ion cyclotron resonance (FT-ICR) mass spectrometry. A low noise junction field-effect transistor (JFET), BF862, is used as the main amplification stage of this trans-impedance preamplifier, and a T-shaped feedback network is introduced as both the feedback and the gate biasing solutions. The T feedback network has been studied using an operational amplifier (Op Amp), AD8099. Such a feedback system allows ~100-fold less feedback resistance at a given transimpedance, hence preserving bandwidth, which is beneficial to applications demanding high gain. The single-transistor preamplifier yields a tested transimpedance of ~10(4) Ω (80 dBΩ) in the frequency range between 1 kHz and 1 MHz (mass-to-charge ratio, m/z, of around 180-180k for a 12-T FT-ICR system), with a low power consumption of ~6 mW, which implies that this preamplifier is well suited to a 12-T FT-ICR mass spectrometer. In trading noise performance for higher trans-impedance, an alternative preamplifier design, an AD8099 preamplifier with the T feedback network, has also been studied with a capability of ~10(6) Ω (120 dBΩ) transimpedance in the same frequency range. The resistive components in the T feedback network reported here can be replaced by complex impedances, which allows adaptation of this feedback system to other frequency, transimpedance, and noise characteristics for applications not only in other mass spectrometers, such as Orbitrap, time-of-flight (TOF), and ion trap systems, but also in other charge/current detecting systems such as spectroscopy systems, microscopy systems, optical communication systems, or charge-coupled devices (CCDs).

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

NASA Astrophysics Data System (ADS)

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-09-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage.

Simple phenomenological modeling of transition-region capacitance of forward-biased p-n junction diodes and transistor diodes

NASA Technical Reports Server (NTRS)

Lindholm, F. A.

1982-01-01

The derivation of a simple expression for the capacitance C(V) associated with the transition region of a p-n junction under a forward bias is derived by phenomenological reasoning. The treatment of C(V) is based on the conventional Shockley equations, and simpler expressions for C(V) result that are in general accord with the previous analytical and numerical results. C(V) consists of two components resulting from changes in majority carrier concentration and from free hole and electron accumulation in the space-charge region. The space-charge region is conceived as the intrinsic region of an n-i-p structure for a space-charge region markedly wider than the extrinsic Debye lengths at its edges. This region is excited in the sense that the forward bias creates hole and electron densities orders of magnitude larger than those in equilibrium. The recent Shirts-Gordon (1979) modeling of the space-charge region using a dielectric response function is contrasted with the more conventional Schottky-Shockley modeling.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Ultrahigh Responsivity-Bandwidth Product in a Compact InP Nanopillar Phototransistor Directly Grown on Silicon

PubMed Central

Ko, Wai Son; Bhattacharya, Indrasen; Tran, Thai-Truong D.; Ng, Kar Wei; Adair Gerke, Stephen; Chang-Hasnain, Connie

2016-01-01

Highly sensitive and fast photodetectors can enable low power, high bandwidth on-chip optical interconnects for silicon integrated electronics. III-V compound semiconductor direct-bandgap materials with high absorption coefficients are particularly promising for photodetection in energy-efficient optical links because of the potential to scale down the absorber size, and the resulting capacitance and dark current, while maintaining high quantum efficiency. We demonstrate a compact bipolar junction phototransistor with a high current gain (53.6), bandwidth (7 GHz) and responsivity (9.5 A/W) using a single crystalline indium phosphide nanopillar directly grown on a silicon substrate. Transistor gain is obtained at sub-picowatt optical power and collector bias close to the CMOS line voltage. The quantum efficiency-bandwidth product of 105 GHz is the highest for photodetectors on silicon. The bipolar junction phototransistor combines the receiver front end circuit and absorber into a monolithic integrated device, eliminating the wire capacitance between the detector and first amplifier stage. PMID:27659796

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Simulation of carbon nanotube welding through Ar bombardment.

PubMed

Kucukkal, Mustafa U; Stuart, Steven J

2017-04-01

Single-walled carbon nanotubes show promise as nanoscale transistors for nanocomputing applications. This use will require appropriate methods for creating electrical connections between distinct nanotubes, analogous to welding of metallic wires at larger length scales, but methods for performing nanoscale chemical welding are not yet sufficiently understood. This study examines the effect of Ar bombardment on the junction of two crossed single-walled carbon nanotubes, to understand the value and limitations of this method for generating connections between nanotubes. A geometric criterion was used to assess the quality of the junctions formed, with the goal of identifying the most productive conditions for experimental ion bombardment. In particular, the effects of nanotube chirality, Ar impact kinetic energy, impact particle flux and fluence, and annealing temperature were considered. The most productive bombardment conditions, leading to the most crosslinking of the tubes with the smallest loss of graphitic (i.e., conductive) character, were found to be at relatively mild impact energies (100 eV), with low flux and high-temperature (3000 K) annealing. Particularly noteworthy for experimental application, a high junction quality is maintained for a relatively broad range of fluences, from 3 × 10 19  m -2 to at least 1 × 10 20  m -2 .

Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

DOE PAGES

Choi, Sukwon; Peake, Gregory M.; Keeler, Gordon A.; ...

2016-04-21

Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less

Experimental study of the minority-carrier transport at the polysilicon-monosilicon interface

NASA Astrophysics Data System (ADS)

Neugroschel, A.; Arienzo, M.; Isaac, R. D.; Komem, Y.

1985-04-01

This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n(+) polysilicon-n(+) monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 10,000 cm/s.

Design consideration of δ-doping channels for high-performance n + - GaAs / p + -InGaP/n-GaAs camel-gate field effect transistors

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui; Chen, Jeng-Shyan; Chu, Yu-Jui

2005-01-01

The influence of δ-doping channels on the performance of n +-GaAs/p +-InGaP/n-GaAs camel-gate field effect transistors is investigated by theoretical analysis and experimental results. The depleted pn junction of the camel gate and the existence of considerable conduction band discontinuity at the InGaP/GaAs heterojunction enhance the potential barrier height and the forward gate voltage. As the concentration-thickness products of the n-GaAs layer and δ-doping layer are fixed, the higher δ-doping device exhibits a higher potential barrier height, a larger drain current, and a broader gate voltage swing, whereas the transconductance is somewhat lower. For a n +=5.5×10 12 cm -2δ-doping device, the experimental result exhibits a maximum transconductance of 240 mS/mm and a gate voltage swing of 3.5 V. Consequently, the studied devices provide a good potential for large signal and linear circuit applications.

A neuron-astrocyte transistor-like model for neuromorphic dressed neurons.

PubMed

Valenza, G; Pioggia, G; Armato, A; Ferro, M; Scilingo, E P; De Rossi, D

2011-09-01

Experimental evidences on the role of the synaptic glia as an active partner together with the bold synapse in neuronal signaling and dynamics of neural tissue strongly suggest to investigate on a more realistic neuron-glia model for better understanding human brain processing. Among the glial cells, the astrocytes play a crucial role in the tripartite synapsis, i.e. the dressed neuron. A well-known two-way astrocyte-neuron interaction can be found in the literature, completely revising the purely supportive role for the glia. The aim of this study is to provide a computationally efficient model for neuron-glia interaction. The neuron-glia interactions were simulated by implementing the Li-Rinzel model for an astrocyte and the Izhikevich model for a neuron. Assuming the dressed neuron dynamics similar to the nonlinear input-output characteristics of a bipolar junction transistor, we derived our computationally efficient model. This model may represent the fundamental computational unit for the development of real-time artificial neuron-glia networks opening new perspectives in pattern recognition systems and in brain neurophysiology. Copyright © 2011 Elsevier Ltd. All rights reserved.

Development of a multi-space constrained density functional theory approach and its application to graphene-based vertical transistors

NASA Astrophysics Data System (ADS)

Kim, Han Seul; Kim, Yong-Hoon

We have been developing a multi-space-constrained density functional theory approach for the first-principles calculations of nano-scale junctions subjected to non-equilibrium conditions and charge transport through them. In this presentation, we apply the method to vertically-stacked graphene/hexagonal boron nitride (hBN)/graphene Van der Waals heterostructures in the context of tunneling transistor applications. Bias-dependent changes in energy level alignment, wavefunction hybridization, and current are extracted. In particular, we compare quantum transport properties of single-layer (graphene) and infinite (graphite) electrode limits on the same ground, which is not possible within the traditional non-equilibrium Green function formalism. The effects of point defects within hBN on the current-voltage characteristics will be also discussed. Global Frontier Program (2013M3A6B1078881), Nano-Material Technology Development Programs (2016M3A7B4024133, 2016M3A7B4909944, and 2012M3A7B4049888), and Pioneer Program (2016M3C1A3906149) of the National Research Foundation.

Investigation of performance enhancement in InAs/InGaAs heterojunction-enhanced N-channel tunneling field-effect transistor

NASA Astrophysics Data System (ADS)

Han, Genquan; Zhao, Bin; Liu, Yan; Wang, Hongjuan; Liu, Mingshan; Zhang, Chunfu; Hu, Shengdong; Hao, Yue

2015-12-01

We design a heterojunction-enhanced n-channel tunneling field effect transistor (HE-TFET) with an InAs/In1-xGaxAs heterojunction located in channel region with a distance of LT-H from source/channel tunneling junction. The influence of LT-H on the performance of HE-TFETs is investigated by simulation. Compared with InAs homo-NTFET, the positive shift of onset voltage, the steeper subthreshold swing (SS), and the enhanced on-state current ION are achieved in HE-NTFETs, which is attributed to the modulation of the heterojunction on band-to-band tunneling. At a supply voltage of 0.3 V, ION of InAs/In0.9Ga0.1As HE-NTFET with a LT-H of 6 nm demonstrates an enhancement of 119.3% in comparison with the homo device. Furthermore, the impact of Ga composition on the performance of HE-NTFETs is studied. As the Ga composition increases, the average SS characteristics of HE-NTFETs are improved, while the drive current of devices is reduced due to the increasing of tunneling barrier.

Nonlinear system analysis in bipolar integrated circuits

NASA Astrophysics Data System (ADS)

Fang, T. F.; Whalen, J. J.

1980-01-01

Since analog bipolar integrated circuits (IC's) have become important components in modern communication systems, the study of the Radio Frequency Interference (RFI) effects in bipolar IC amplifiers is an important subject for electromagnetic compatibility (EMC) engineering. The investigation has focused on using the nonlinear circuit analysis program (NCAP) to predict RF demodulation effects in broadband bipolar IC amplifiers. The audio frequency (AF) voltage at the IC amplifier output terminal caused by an amplitude modulated (AM) RF signal at the IC amplifier input terminal was calculated and compared to measured values. Two broadband IC amplifiers were investigated: (1) a cascode circuit using a CA3026 dual differential pair; (2) a unity gain voltage follower circuit using a micro A741 operational amplifier (op amp). Before using NCAP for RFI analysis, the model parameters for each bipolar junction transistor (BJT) in the integrated circuit were determined. Probe measurement techniques, manufacturer's data, and other researcher's data were used to obtain the required NCAP BJT model parameter values. An important contribution included in this effort is a complete set of NCAP BJT model parameters for most of the transistor types used in linear IC's.

All-Metallic Vertical Transistors Based on Stacked Dirac Materials

NASA Astrophysics Data System (ADS)

Wang, Yangyang; Ni, Zeyuan; Liu, Qihang; Quhe, Ruge; Zheng, Jiaxin; Ye, Meng; Yu, Dapeng; Shi, Junjie; Yang, Jinbo; Li, Ju; Lu, Jing; Collaborative Innovation Center of Quantum Matter, Beijing Collaboration

2015-03-01

All metallic transistor can be fabricated from pristine semimetallic Dirac materials (such as graphene, silicene, and germanene), but the on/off current ratio is very low. In a vertical heterostructure composed by two Dirac materials, the Dirac cones of the two materials survive the weak interlayer van der Waals interaction based on density functional theory method, and electron transport from the Dirac cone of one material to the one of the other material is therefore forbidden without assistance of phonon because of momentum mismatch. First-principles quantum transport simulations of the all-metallic vertical Dirac material heterostructure devices confirm the existence of a transport gap of over 0.4 eV, accompanied by a switching ratio of over 104. Such a striking behavior is robust against the relative rotation between the two Dirac materials and can be extended to twisted bilayer graphene. Therefore, all-metallic junction can be a semiconductor and novel avenue is opened up for Dirac material vertical structures in high-performance devices without opening their band gaps. A visiting student in MIT now.

Analysis of Radiation Effects in Silicon using Kinetic Monte Carlo Methods

DOE PAGES

Hehr, Brian Douglas

2014-11-25

The transient degradation of semiconductor device performance under irradiation has long been an issue of concern. Neutron irradiation can instigate the formation of quasi-stable defect structures, thereby introducing new energy levels into the bandgap that alter carrier lifetimes and give rise to such phenomena as gain degradation in bipolar junction transistors. Normally, the initial defect formation phase is followed by a recovery phase in which defect-defect or defect-dopant interactions modify the characteristics of the damaged structure. A kinetic Monte Carlo (KMC) code has been developed to model both thermal and carrier injection annealing of initial defect structures in semiconductor materials.more » The code is employed to investigate annealing in electron-irradiated, p-type silicon as well as the recovery of base current in silicon transistors bombarded with neutrons at the Los Alamos Neutron Science Center (LANSCE) “Blue Room” facility. Our results reveal that KMC calculations agree well with these experiments once adjustments are made, within the appropriate uncertainty bounds, to some of the sensitive defect parameters.« less

Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane heterostructures

NASA Astrophysics Data System (ADS)

Das, Tanmoy; Jang, Houk; Bok Lee, Jae; Chu, Hyunwoo; Kim, Seong Dae; Ahn, Jong-Hyun

2015-12-01

Graphene-based heterostructured vertical transistors have attracted a great deal of research interest. Herein we propose a Si-based technology platform for creating graphene/ultrathin semiconductor/metal (GSM) junctions, which can be applied to large-scale and low-power electronics compatible with a variety of substrates. We fabricated graphene/Si nanomembrane (NM)/metal vertical heterostructures by using a dry transfer technique to transfer Si NMs onto chemical vapor deposition-grown graphene layers. The resulting van der Waals interfaces between graphene and p-Si NMs exhibited nearly ideal Schottky barrier behavior. Due to the low density of states of graphene, the graphene/Si NM Schottky barrier height can be modulated by modulating the band profile in the channel region, yielding well-defined current modulation. We obtained a maximum current on/off ratio (Ion/Ioff) of up to ˜103, with a current density of 102 A cm-2. We also observed significant dependence of Schottky barrier height Δφb on the thickness of the Si NMs. We confirmed that the transport in these devices is dominated by the effects of the graphene/Si NM Schottky barrier.

RF Single Electron Transistor Readout Amplifiers for Superconducting Astronomical Detectors for X-Ray to Sub-mm Wavelengths

NASA Technical Reports Server (NTRS)

Stevenson, Thomas; Aassime, Abdelhanin; Delsing, Per; Frunzio, Luigi; Li, Li-Qun; Prober, Daniel; Schoelkopf, Robert; Segall, Ken; Wilson, Chris; Stahle, Carl

2000-01-01

We report progress on using a new type of amplifier, the Radio-Frequency Single-Electron Transistor (RF-SET), to develop multi-channel sensor readout systems for fast and sensitive readout of high impedance cryogenic photodetectors such as Superconducting Tunnel Junctions and Single Quasiparticle Photon Counters. Although cryogenic, these detectors are desirable because of capabilities not other-wise attainable. However, high impedances and low output levels make low-noise, high-speed readouts challenging, and large format arrays would be facilitated by compact, low-power, on-chip integrated amplifiers. Well-suited for this application are RF-SETs, very high performance electrometers which use an rf readout technique to provide 100 MHz bandwidth. Small size, low power, and cryogenic operation allow direct integration with detectors, and using multiple rf carrier frequencies permits simultaneous readout of 20-50 amplifiers with a common electrical connection. We describe both the first 2-channel demonstration of this wavelength division multiplexing technique for RF-SETs, and Charge-Locked-Loop operation with 100 kHz of closed-loop bandwidth.

Josephson junction devices: Model quantum mechanical systems and medical applications

NASA Astrophysics Data System (ADS)

Chen, Josephine

In this dissertation, three experiments using Josephson junction devices are described. In Part I, the effect of dissipation on tunneling between charge states in a superconducting single-electron transistor (sSET) was studied. The sSET was fabricated on top of a semi-conductor heterostructure with a two-dimensional electron gas (2DEG) imbedded beneath the surface. The 2DEG acted as a dissipative ground plane. The sheet resistance of the 2DEG could be varied in situ by applying a large voltage to a gate on the back of the substrate. The zero-bias conductance of the sSET was observed to increase with increasing temperature and 2DEG resistance. Some qualitative but not quantitative agreement was found with theoretical calculations of the functional dependence of the conductance on temperature and 2DEG resistance. Part II describes a series of experiments performed on magnesium diboride point-contact junctions. The pressure between the MgB2 tip and base pieces could be adjusted to form junctions with different characteristics. With light pressure applied between the two pieces, quasiparticle tunneling in superconductor-insulator-superconductor junctions was measured. From these data, a superconducting gap of approximately 2 meV and a critical temperature of 29 K were estimated. Increasing the pressure between the MgB2 pieces formed junctions with superconductor-normal metal-superconductor characteristics. We used these junctions to form MgB2 superconducting quantum interference devices (SQUIDS). Noise levels as low as 35 fT/Hz1/2 and 4 muphi 0/Hz1/2 at 1 kHz were measured. In Part III, we used a SQUID-based instrument to acquire magnetocardiograms (MCG), the magnetic field signal measured from the human heart. We measured 51 healthy volunteers and 11 cardiac patients both at rest and after treadmill exercise. We found age and sex related differences in the MCG of the healthy volunteers that suggest that these factors should be considered when evaluating the MCG for disease. We also defined a spatio-temporal MCG parameter, the repolarization stabilization interval, which successfully discriminated our patients from our healthy controls.

A high voltage dielectrically isolated smart power technology based on silicon direct bonding

NASA Astrophysics Data System (ADS)

Macary, Veronique

1992-09-01

The feasibility of a dielectrically isolated technology based on the silicon direct bonding technique, for high voltage smart power applications in the 1000 to 1550 V/1 to 20 A range, where a vertical power switch is necessary, is investigated and demonstrated. Static and dynamic isolation of the low voltage circuitry integrated beside the vertical power transistor is the main concern of this family of circuits. The dielectric isolation offers better protection to the low voltage part than does the junction isolation, because of the elimination of the parasitic bipolar transistor inherent to the latter isolation technique. Silicon direct bonding provides a cost effective way to obtain a buried oxide isolation layer. In addition, the application requires a Si/Si bonded area in the active region of the vertical power switch. Strong influence of the prebonding cleaning in the electrical characteristics of the Si/Si interface is pointed out, and presence of crystalline defects is assumed to be at the origin of electrical failures. The main problems of silicon direct bonding process compatibility with standard processes were overcome, and a complete process flow, including the simultaneous integration of a vertical power bipolar transistor together with a bipolar control circuitry, was validated. Using a peripheral biased ring is shown to provide an easy way to optimize high voltage termination for the smart power circuit, while adding a non-additional technological step. This technique was studied by dimensional electrical simulations (BIDIM2 software), as well as analytically computed.

Research and development of a high-performance differential-hybrid charge sensitive preamplifier.

PubMed

Zeng, Guoqiang; Hu, Chuanhao; Wei, Shilong; Yang, Jian; Li, Qiang; Ge, Liangquan; Tan, Chengjun

2017-02-01

A differential-hybrid charge sensitive preamplifier (CSP) was designed by taking a monolithic dual N-Channel Junction Field-effect Transistor (JFET) and a high-speed, low-noise, operational amplifier as the core parts. Input-stage of the circuit employs low-noise differential dual JFET, which ensures high input impedance and low noise. The differential dual transistor makes the quiescent point of the first-stage differential output stable, which is convenient for connecting with the post stage high-speed operational amplifier. Broadband could be amplified by connecting to the double differential dual transistors through the folded cascode-bootstrap. The amplifying circuit which replaces the interstage and post stage discrete components of a traditional CSP with integrated operational amplifier is simpler and more reliable. It simplifies the design of the quiescent point, gives full play to advantages of releasing large open-loop gain, and improves charge-voltage conversion gain stability. Particularly, the charge-voltage conversion gain is larger under a smaller feedback capacitor, thus enabling to gain better signal-noise ratio. The designed CSP was tested, reporting 3.3×10 13 V/C charge sensitivity, about 90ns rise time of signals, 35:1 signal-noise ratio to gamma-rays of 137 Cs (662keV) and a 0.023 fC/pF noise slope. Gamma-rays of 241 Am (59.5keV) were measured by the BPX66 detector and the designed CSP under room temperature, providing 1.97% energy resolution. Copyright © 2016 Elsevier Ltd. All rights reserved.

High-mobility hydrogen-terminated Si(111) transistors for measurement of six-fold valley degenerate two-dimensional electron systems in fractional quantum Hall regime

NASA Astrophysics Data System (ADS)

Hu, Binhui; Yazdanpanah, Mohamad Meqdad; Kane, Bruce E.

2015-03-01

The quality of hydrogen-terminated Si(111) (H-Si(111)) transistors has improved significantly. Peak electron mobility of 325,000 cm2/Vs was achieved at 90 mK, and the fractional quantum Hall effect (FQHE) at 1 < ν < 2 was studied extensively. We have further improved the device by solving gate leakage and contact problems with an updated design, in which a Si piece with thermal oxide acts as a gate through a vacuum cavity, and PN junctions are used to define a hexagonal two-dimensional (2D) region on a H-Si(111) piece. The device operates as an ambipolar transistor, in which a 2D electron system (2DES) and a 2D hole system can be induced at the same H-Si(111) surface. Peak electron mobility of more than 200,000 cm2/Vs is routinely achieved at 300 mK. The Si(111) surface has a six-fold valley degeneracy. The hexagonal device is designed to investigate the symmetry of the 2DES. Preliminary data show that the transport anisotropy at ν < 6 can be explained by the valley occupancy. The details of the valley occupancy can be caused by several mechanisms, such as miscut, magnetic field, pseudospin quantum Hall ferromagnetism (QHFM), and nematic valley polarization phases. The FQHE is investigated in magnetic fields up to 35T, and the properties of composite fermions will be discussed.

Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

PubMed Central

Kazior, Thomas E.

2014-01-01

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

PubMed

Kazior, Thomas E

2014-03-28

Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

3D assembly of carbon nanotubes for fabrication of field-effect transistors through nanomanipulation and electron-beam-induced deposition

NASA Astrophysics Data System (ADS)

Yu, Ning; Shi, Qing; Nakajima, Masahiro; Wang, Huaping; Yang, Zhan; Sun, Lining; Huang, Qiang; Fukuda, Toshio

2017-10-01

Three-dimensional carbon nanotube field-effect transistors (3D CNTFETs) possess predictable characteristics that rival those of planar CNTFETs and Si-based MOSFETs. However, due to the lack of a reliable assembly technology, they are rarely reported on, despite the amount of attention they receive. To address this problem, we propose the novel concept of a 3D CNTFET and develop its assembly strategy based on nanomanipulation and the electron-beam-induced deposition (EBID) technique inside a scanning electron microscope (SEM). In particular, the electrodes in our transistor design are three metallic cuboids of the same size, and their front, top and back surfaces are all wrapped up in CNTs. The assembly strategy is employed to build the structure through a repeated basic process of pick-up, placement, fixing and cutting of CNTs. The pick-up and placement is performed through one nanomanipulator with four degrees of freedom. Fixing is carried out through the EBID technique so as to improve the mechanical and electrical characteristics of the CNT/electrodes connection. CNT cutting is undertaken using the typical method of electrical breakdown. Experimental results showed that two CNTs were successfully assembled on the front sides of the cubic electrodes. This validates our assembly method for the 3D CNTFET. Also, when contact resistance was measured, tens of kilohms of resistance was observed at the CNT-EBID deposition-FET electrodes junction.. This manifests the electrical reliability of our assembly strategy.

Superconducting active impedance converter

DOEpatents

Ginley, D.S.; Hietala, V.M.; Martens, J.S.

1993-11-16

A transimpedance amplifier for use with high temperature superconducting, other superconducting, and conventional semiconductors allows for appropriate signal amplification and impedance matching to processing electronics. The amplifier incorporates the superconducting flux flow transistor into a differential amplifier configuration which allows for operation over a wide temperature range, and is characterized by high gain, relatively low noise, and response times less than 200 picoseconds over at least a 10-80 K. temperature range. The invention is particularly useful when a signal derived from either far-IR focal plane detectors or from Josephson junctions is to be processed by higher signal/higher impedance electronics, such as conventional semiconductor technology. 12 figures.

n-Type diamond and method for producing same

DOEpatents

Anderson, Richard J.

2002-01-01

A new n-type semiconducting diamond is disclosed, which is doped with n-type dopant atoms. Such diamond is advantageously formed by chemical vapor deposition from a source gas mixture comprising a carbon source compound for the diamond, and a volatile hot wire filament for the n-type impurity species, so that the n-type impurity atoms are doped in the diamond during its formation. A corresponding chemical vapor deposition method of forming the n-type semiconducting diamond is disclosed. The n-type semiconducting diamond of the invention may be usefully employed in the formation of diamond-based transistor devices comprising pn diamond junctions, and in other microelectronic device applications.

Manipulation of electron transport in graphene by nanopatterned electrostatic potential on an electret

NASA Astrophysics Data System (ADS)

Wang, Xiaowei; Wang, Rui; Wang, Shengnan; Zhang, Dongdong; Jiang, Xingbin; Cheng, Zhihai; Qiu, Xiaohui

2018-01-01

The electron transport characteristics of graphene can be finely tuned using local electrostatic fields. Here, we use a scanning probe technique to construct a statically charged electret gate that enables in-situ fabrication of graphene devices with precisely designed potential landscapes, including p-type and n-type unipolar graphene transistors and p-n junctions. Electron dynamic simulation suggests that electron beam collimation and focusing in graphene can be achieved via periodic charge lines and concentric charge circles. This approach to spatially manipulating carrier density distribution may offer an efficient way to investigate the novel electronic properties of graphene and other low-dimensional materials.

Note: A high dynamic range, linear response transimpedance amplifier.

PubMed

Eckel, S; Sushkov, A O; Lamoreaux, S K

2012-02-01

We have built a high dynamic range (nine decade) transimpedance amplifier with a linear response. The amplifier uses junction-gate field effect transistors (JFETs) to switch between three different resistors in the feedback of a low input bias current operational amplifier. This allows for the creation of multiple outputs, each with a linear response and a different transimpedance gain. The overall bandwidth of the transimpedance amplifier is set by the bandwidth of the most sensitive range. For our application, we demonstrate a three-stage amplifier with transimpedance gains of approximately 10(9)Ω, 3 × 10(7)Ω, and 10(4)Ω with a bandwidth of 100 Hz.

A parallel input composite transimpedance amplifier.

PubMed

Kim, D J; Kim, C

2018-01-01

A new approach to high performance current to voltage preamplifier design is presented. The design using multiple operational amplifiers (op-amps) has a parasitic capacitance compensation network and a composite amplifier topology for fast, precision, and low noise performance. The input stage consisting of a parallel linked JFET op-amps and a high-speed bipolar junction transistor (BJT) gain stage driving the output in the composite amplifier topology, cooperating with the capacitance compensation feedback network, ensures wide bandwidth stability in the presence of input capacitance above 40 nF. The design is ideal for any two-probe measurement, including high impedance transport and scanning tunneling microscopy measurements.

A parallel input composite transimpedance amplifier

NASA Astrophysics Data System (ADS)

Kim, D. J.; Kim, C.

2018-01-01

A new approach to high performance current to voltage preamplifier design is presented. The design using multiple operational amplifiers (op-amps) has a parasitic capacitance compensation network and a composite amplifier topology for fast, precision, and low noise performance. The input stage consisting of a parallel linked JFET op-amps and a high-speed bipolar junction transistor (BJT) gain stage driving the output in the composite amplifier topology, cooperating with the capacitance compensation feedback network, ensures wide bandwidth stability in the presence of input capacitance above 40 nF. The design is ideal for any two-probe measurement, including high impedance transport and scanning tunneling microscopy measurements.

Lithography-Free Fabrication of Core-Shell GaAs Nanowire Tunnel Diodes.

PubMed

Darbandi, A; Kavanagh, K L; Watkins, S P

2015-08-12

GaAs core-shell p-n junction tunnel diodes were demonstrated by combining vapor-liquid-solid growth with gallium oxide deposition by atomic layer deposition for electrical isolation. The characterization of an ensemble of core-shell structures was enabled by the use of a tungsten probe in a scanning electron microscope without the need for lithographic processing. Radial tunneling transport was observed, exhibiting negative differential resistance behavior with peak-to-valley current ratios of up to 3.1. Peak current densities of up to 2.1 kA/cm(2) point the way to applications in core-shell photovoltaics and tunnel field effect transistors.

Modulation linearization of a frequency-modulated voltage controlled oscillator, part 3

NASA Technical Reports Server (NTRS)

Honnell, M. A.

1975-01-01

An analysis is presented for the voltage versus frequency characteristics of a varactor modulated VHF voltage controlled oscillator in which the frequency deviation is linearized by using the nonlinear characteristics of a field effect transistor as a signal amplifier. The equations developed are used to calculate the oscillator output frequency in terms of pertinent circuit parameters. It is shown that the nonlinearity exponent of the FET has a pronounced influence on frequency deviation linearity, whereas the junction exponent of the varactor controls total frequency deviation for a given input signal. A design example for a 250 MHz frequency modulated oscillator is presented.

Nonlinear analysis of a family of LC tuned inverters. [dc to square wave circuits for power conditioning

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1974-01-01

A family of four dc-to-square-wave LC tuned inverters are analyzed using singular point. Limit cycles and waveshape characteristics are given for three modes of oscillation: quasi-harmonic, relaxation, and discontinuous. An inverter in which the avalanche breakdown of the transistor emitter-to-base junction occurs is discussed and the starting characteristics of this family of inverters are presented. The LC tuned inverters are shown to belong to a family of inverters with a common equivalent circuit consisting of only three 'series' elements: a five-segment piecewise-linear current-controlled resistor, linear inductor, and linear capacitor.

0-π phase-controllable thermal Josephson junction

NASA Astrophysics Data System (ADS)

Fornieri, Antonio; Timossi, Giuliano; Virtanen, Pauli; Solinas, Paolo; Giazotto, Francesco

2017-05-01

Two superconductors coupled by a weak link support an equilibrium Josephson electrical current that depends on the phase difference ϕ between the superconducting condensates. Yet, when a temperature gradient is imposed across the junction, the Josephson effect manifests itself through a coherent component of the heat current that flows opposite to the thermal gradient for |ϕ| < π/2 (refs 2-4). The direction of both the Josephson charge and heat currents can be inverted by adding a π shift to ϕ. In the static electrical case, this effect has been obtained in a few systems, for example via a ferromagnetic coupling or a non-equilibrium distribution in the weak link. These structures opened new possibilities for superconducting quantum logic and ultralow-power superconducting computers. Here, we report the first experimental realization of a thermal Josephson junction whose phase bias can be controlled from 0 to π. This is obtained thanks to a superconducting quantum interferometer that allows full control of the direction of the coherent energy transfer through the junction. This possibility, in conjunction with the completely superconducting nature of our system, provides temperature modulations with an unprecedented amplitude of ∼100 mK and transfer coefficients exceeding 1 K per flux quantum at 25 mK. Then, this quantum structure represents a fundamental step towards the realization of caloritronic logic components such as thermal transistors, switches and memory devices. These elements, combined with heat interferometers and diodes, would complete the thermal conversion of the most important phase-coherent electronic devices and benefit cryogenic microcircuits requiring energy management, such as quantum computing architectures and radiation sensors.

Zinc Alloys for the Fabrication of Semiconductor Devices

NASA Technical Reports Server (NTRS)

Ryu, Yungryel; Lee, Tae S.

2009-01-01

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Gold Nanoparticles on Functionalized Silicon Substrate under Coulomb Blockade Regime: An Experimental and Theoretical Investigation.

PubMed

Pluchery, Olivier; Caillard, Louis; Dollfus, Philippe; Chabal, Yves J

2018-01-18

Single charge electronics offer a way for disruptive technology in nanoelectronics. Coulomb blockade is a realistic way for controlling the electric current through a device with the accuracy of one electron. In such devices the current exhibits a step-like increase upon bias which reflects the discrete nature of the fundamental charge. We have assembled a double tunnel junction on an oxide-free silicon substrate that exhibits Coulomb staircase characteristics using gold nanoparticles (AuNPs) as Coulomb islands. The first tunnel junction is an insulating layer made of a grafted organic monolayer (GOM) developed for this purpose. The GOM also serves for attaching AuNPs covalently. The second tunnel junction is made by the tip of an STM. We show that this device exhibits reproducible Coulomb blockade I-V curves at 40 K in vacuum. We also show that depending on the doping of the silicon substrate, the whole Coulomb staircase can be adjusted. We have developed a simulation approach based on the orthodox theory that was completed by calculating the bias dependent tunnel barriers and by including an accurate calculation of the band bending. This model accounts for the experimental data and the doping dependence of Coulomb oscillations. This study opens new perspectives toward designing new kind of single electron transistors (SET) based on this dependence of the Coulomb staircase with the charge carrier concentration.

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

SiC JFET Transistor Circuit Model for Extreme Temperature Range

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

2008-01-01

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Multiscale examination and modeling of electron transport in nanoscale materials and devices

NASA Astrophysics Data System (ADS)

Banyai, Douglas R.

For half a century the integrated circuits (ICs) that make up the heart of electronic devices have been steadily improving by shrinking at an exponential rate. However, as the current crop of ICs get smaller and the insulating layers involved become thinner, electrons leak through due to quantum mechanical tunneling. This is one of several issues which will bring an end to this incredible streak of exponential improvement of this type of transistor device, after which future improvements will have to come from employing fundamentally different transistor architecture rather than fine tuning and miniaturizing the metal-oxide-semiconductor field effect transistors (MOSFETs) in use today. Several new transistor designs, some designed and built here at Michigan Tech, involve electrons tunneling their way through arrays of nanoparticles. We use a multi-scale approach to model these devices and study their behavior. For investigating the tunneling characteristics of the individual junctions, we use a first-principles approach to model conduction between sub-nanometer gold particles. To estimate the change in energy due to the movement of individual electrons, we use the finite element method to calculate electrostatic capacitances. The kinetic Monte Carlo method allows us to use our knowledge of these details to simulate the dynamics of an entire device---sometimes consisting of hundreds of individual particles---and watch as a device 'turns on' and starts conducting an electric current. Scanning tunneling microscopy (STM) and the closely related scanning tunneling spectroscopy (STS) are a family of powerful experimental techniques that allow for the probing and imaging of surfaces and molecules at atomic resolution. However, interpretation of the results often requires comparison with theoretical and computational models. We have developed a new method for calculating STM topographs and STS spectra. This method combines an established method for approximating the geometric variation of the electronic density of states, with a modern method for calculating spin-dependent tunneling currents, offering a unique balance between accuracy and accessibility.

Characterization of Polar, Semi-Polar, and Non-Polar p-n Homo and Hetero-junctions grown by Ammonia Molecular Beam Epitaxy

NASA Astrophysics Data System (ADS)

Hurni, Christophe Antoine

Widespread interest in the group III-Nitrides began with the achievement of p-type conductivity in the early 1990s in Mg-doped GaN films grown by metal organic chemical vapor deposition (MOCVD) by Nakamura et al. Indeed, MOCVD-grown Mg-doped GaN is insulating as-grown, because of the formation of neutral Mg-H complexes. Nakamura et al. showed that a rapid thermal anneal removes the hydrogen and enables p-conductivity. Shortly after this discovery, the first LEDs and lasers were demonstrated by Nakamura et al. The necessary annealing step is problematic for devices which need a buried p-layer, such as hetero-junction bipolar transistors. Ammonia molecular beam epitaxy (NH3-MBE) has a great potential for growing vertical III-Nitrides-based devices, thank to its N-rich growth conditions and all the usual advantages of MBE, which include a low-impurity growth environment, in situ monitoring techniques as well as the ability to grow sharp interfaces. We first investigated the growth of p-GaN by NH3-MBE. We found that the hole concentration strongly depends on the growth temperature. Thanks to comprehensive Hall and transfer length measurements, we found evidences for a compensating donor defects in NH3-MBE-grown Mg-doped GaN films. High-quality p-n junctions with very low reverse current and close to unity ideality factor were also grown and investigated. For the design of heterojunction devices such as laser diodes, light emitting diodes or heterojunction bipolar transistors, hetero-interface's characteristics such as the band offset or interface charges are fundamental. A technique developed by Kroemer et al. uses capacitance-voltage (C-V) profiling to extract band-offsets and charges at a hetero-interface. We applied this technique to the III-Nitrides. We discovered that for the polar III-Nitrides, the technique is not applicable because of the very large polarization charge. We nevertheless successfully measured the polarization charge at the AlGaN/GaN hetero-interface though C-V profiling. In the non-polar and semi-polar cases, the hetero-interface charge was low enough to extract the conduction band-offset through C-V profiling, provided that the doping profile had a foreseeable behavior.

One-pot growth of two-dimensional lateral heterostructures via sequential edge-epitaxy

NASA Astrophysics Data System (ADS)

Sahoo, Prasana K.; Memaran, Shahriar; Xin, Yan; Balicas, Luis; Gutiérrez, Humberto R.

2018-01-01

Two-dimensional heterojunctions of transition-metal dichalcogenides have great potential for application in low-power, high-performance and flexible electro-optical devices, such as tunnelling transistors, light-emitting diodes, photodetectors and photovoltaic cells. Although complex heterostructures have been fabricated via the van der Waals stacking of different two-dimensional materials, the in situ fabrication of high-quality lateral heterostructures with multiple junctions remains a challenge. Transition-metal-dichalcogenide lateral heterostructures have been synthesized via single-step, two-step or multi-step growth processes. However, these methods lack the flexibility to control, in situ, the growth of individual domains. In situ synthesis of multi-junction lateral heterostructures does not require multiple exchanges of sources or reactors, a limitation in previous approaches as it exposes the edges to ambient contamination, compromises the homogeneity of domain size in periodic structures, and results in long processing times. Here we report a one-pot synthetic approach, using a single heterogeneous solid source, for the continuous fabrication of lateral multi-junction heterostructures consisting of monolayers of transition-metal dichalcogenides. The sequential formation of heterojunctions is achieved solely by changing the composition of the reactive gas environment in the presence of water vapour. This enables selective control of the water-induced oxidation and volatilization of each transition-metal precursor, as well as its nucleation on the substrate, leading to sequential edge-epitaxy of distinct transition-metal dichalcogenides. Photoluminescence maps confirm the sequential spatial modulation of the bandgap, and atomic-resolution images reveal defect-free lateral connectivity between the different transition-metal-dichalcogenide domains within a single crystal structure. Electrical transport measurements revealed diode-like responses across the junctions. Our new approach offers greater flexibility and control than previous methods for continuous growth of transition-metal-dichalcogenide-based multi-junction lateral heterostructures. These findings could be extended to other families of two-dimensional materials, and establish a foundation for the development of complex and atomically thin in-plane superlattices, devices and integrated circuits.

A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Saremi, Mehdi

2018-02-01

In this paper, the influence of ultra-scaled physical symmetrical contraction on electrical characteristics of ultra-thin silicon-on-insulator nanowires with circular gate-all-around structure is investigated by using a 3D Atlas numerical quantum simulator based on non-equilibrium green's function formalism. It is demonstrated that local cross-section variation in a nanowire transistor results in the establishment of tunnel energy barriers at the source-channel and drain-channel junctions which change device physics and cause a transmission from a quantum wire (1-D) to a floating quantum dot nanowire (0-D) introducing a resonant tunneling nanowire FET (RT-NWFET) as an interesting concept of nanoscale MOSFETs. The barriers construct resonance energy levels in the channel region of nanowires because of the longitudinal confinement in three directions causing some fluctuation in I D- V GS characteristic. In addition, these barriers remarkably improve the subthreshold swing and minimize the ON/OFF-current ratio degradation at a low operation voltage of 0.5 V. As a result, RT-NWFETs are intrinsically preserved from drain-source tunneling and are an interesting candidate for developing the roadmap below 10 nm.

Charge Transport in Semiconductor Nanocrystal Solids

NASA Astrophysics Data System (ADS)

Talapin, Dmitri; Shevchenko, Elena; Lee, Jong Soo; Urban, Jeffrey; Mitzi, David; Murray, Christopher

2007-03-01

Self-assembly of chemically-synthesized nanocrystals can yield complex long-range ordered structures which can be used as model systems for studying transport phenomena in low-dimensional materials [1]. Treatment of close-packed PbSe nanocrystal arrays with hydrazine enhanced exchange coupling between the nanocrystals and improved conductance by more than ten orders of magnitude compared to native nanocrystal films [2]. The conductivity of PbSe nanocrystal solids can be switched between n- and p-type transports by controlling the saturation of electronic states at nanocrystal surfaces. Nanocrystal arrays form the n- and p-channels of field-effect transistors with electron and hole mobilities of 2.5 cm^2V-1s-1 and 0.3 cm^2V-1s-1, respectively, and current modulation Ion/Ioff˜10^3-10^4. The field-effect mobility in PbSe nanocrystal arrays is higher than the mobility of organic transistors while the easy switch between n- and p-transport allows realization of complimentary circuits and p-n junctions for nanocrystal-based solar cells and thermoelectric devices. [1] E. V. Shevchenko, D. V. Talapin, N. A. Kotov, S. O'Brien, C. B. Murray. Nature 439, 55 (2006). [2] D. V. Talapin, C. B. Murray. Science 310, 86 (2005).

Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor

NASA Astrophysics Data System (ADS)

Ahish, S.; Sharma, Dheeraj; Vasantha, M. H.; Kumar, Y. B. N.

2017-03-01

In this paper, analog/RF performance of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor (HJTFET) has been explored. A highly doped n+ layer is placed at the Source-Channel junction in order to improve the horizontal electric field component and thus, improve the realiability of the device. The analog performance of the device is analysed by extracting current-voltage characteristics, transcondutance (gm), gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). Further, RF performance of the device is evaluated by obtaining cut-off frequency (fT) and Gain Bandwidth (GBW) product. ION /IOFF ratio equal to ≈ 109, subthreshold slope of 27 mV/dec, maximum fT of 2.1 THz and maximum GBW of 484 GHz were achieved. Also, the impact of temperature variation on the linearity performance of the device has been investigated. Furthermore, the circuit level performance of the device is performed by implementing a Common Source (CS) amplifier; maximum gain of 31.11 dB and 3-dB cut-off frequency equal to 91.2 GHz were achieved for load resistance (RL) = 17.5 KΩ.

Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials

NASA Astrophysics Data System (ADS)

Ilatikhameneh, Hesameddin; Tan, Yaohua; Novakovic, Bozidar; Klimeck, Gerhard; Rahman, Rajib; Appenzeller, Joerg

2015-12-01

In this work, the performance of Tunnel Field-Effect Transistors (TFETs) based on two-dimensional Transition Metal Dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2D material based TFETs can have tight gate control and high electric fields at the tunnel junction, and can in principle generate high ON-currents along with a sub-threshold swing smaller than 60 mV/dec. Our simulations reveal that high performance TMD TFETs, not only require good gate control, but also rely on the choice of the right channel material with optimum band gap, effective mass and source/drain doping level. Unlike previous works, a full band atomistic tight binding method is used self-consistently with 3D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the subthreshold swing and energy-delay of these TFETs are compared with conventional CMOS devices.

Control of the Intrinsic Sensor Response to Volatile Organic Compounds with Fringing Electric Fields.

PubMed

Henning, Alex; Swaminathan, Nandhini; Vaknin, Yonathan; Jurca, Titel; Shimanovich, Klimentiy; Shalev, Gil; Rosenwaks, Yossi

2018-01-26

The ability to control surface-analyte interaction allows tailoring chemical sensor sensitivity to specific target molecules. By adjusting the bias of the shallow p-n junctions in the electrostatically formed nanowire (EFN) chemical sensor, a multiple gate transistor with an exposed top dielectric layer allows tuning of the fringing electric field strength (from 0.5 × 10 7 to 2.5 × 10 7 V/m) above the EFN surface. Herein, we report that the magnitude and distribution of this fringing electric field correlate with the intrinsic sensor response to volatile organic compounds. The local variations of the surface electric field influence the analyte-surface interaction affecting the work function of the sensor surface, assessed by Kelvin probe force microscopy on the nanometer scale. We show that the sensitivity to fixed vapor analyte concentrations can be nullified and even reversed by varying the fringing field strength, and demonstrate selectivity between ethanol and n-butylamine at room temperature using a single transistor without any extrinsic chemical modification of the exposed SiO 2 surface. The results imply an electric-field-controlled analyte reaction with a dielectric surface extremely compelling for sensitivity and selectivity enhancement in chemical sensors.

Fabrication of assembled ZnO/TiO2 heterojunction thin film transistors using solution processing technique

NASA Astrophysics Data System (ADS)

Liau, Leo Chau-Kuang; Lin, Yun-Guo

2015-01-01

Ceramic-based metal-oxide-semiconductor (MOS) field-effect thin film transistors (TFTs), which were assembled by ZnO and TiO2 heterojunction films coated using solution processing technique, were fabricated and characterized. The fabrication of the device began with the preparation of ZnO and TiO2 films by spin coating. The ZnO and TiO2 films that were stacked together and annealed at 450 °C were characterized as a p-n junction diode. Two types of the devices, p-channel and n-channel TFTs, were produced using different assemblies of ZnO and TiO2 films. Results show that the p-channel TFTs (p-TFTs) and n-channel TFTs (n-TFTs) using the assemblies of ZnO and TiO2 films were demonstrated by source-drain current vs. drain voltage (IDS-VDS) measurements. Several electronic properties of the p- and n- TFTs, such as threshold voltage (Vth), on-off ratio, channel mobility, and subthreshold swing (SS), were determined by current-voltage (I-V) data analysis. The ZnO/TiO2-based TFTs can be produced using solution processing technique and an assembly approach.

Phase-tunable temperature amplifier

NASA Astrophysics Data System (ADS)

Paolucci, F.; Marchegiani, G.; Strambini, E.; Giazotto, F.

2017-06-01

Coherent caloritronics, the thermal counterpart of coherent electronics, has drawn growing attention since the discovery of heat interference in 2012. Thermal interferometers, diodes, transistors and nano-valves have been theoretically proposed and experimentally demonstrated by exploiting the quantum phase difference between two superconductors coupled through a Josephson junction. So far, the quantum-phase modulator has been realized in the form of a superconducting quantum interference device (SQUID) or a superconducting quantum interference proximity transistor (SQUIPT). Thence, an external magnetic field is necessary in order to manipulate the heat transport. Here, we theoretically propose the first on-chip fully thermal caloritronic device: the phase-tunable temperature amplifier (PTA). Taking advantage of a recently discovered thermoelectric effect in spin-split superconductors coupled to a spin-polarized system, we generate the magnetic flux controlling the transport through a temperature-biased SQUIPT by applying a temperature gradient. We simulate the behavior of the device and define a number of figures of merit in full analogy with voltage amplifiers. Notably, our architecture ensures almost infinite input thermal impedance, maximum gain of about 11 and efficiency reaching the 95%. This concept paves the way for applications in radiation sensing, thermal logics and quantum information.

High performance tunnel field-effect transistor by gate and source engineering.

PubMed

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Performance improvement in novel germanium-tin/germanium heterojunction-enhanced p-channel tunneling field-effect transistor

NASA Astrophysics Data System (ADS)

Wang, Hongjuan; Liu, Yan; Liu, Mingshan; Zhang, Qingfang; Zhang, Chunfu; Ma, Xiaohua; Zhang, Jincheng; Hao, Yue; Han, Genquan

2015-07-01

We design a novel GeSn-based heterojunction-enhanced p-channel tunneling field-effect transistor (HE-PTFET) with a Ge0.92Sn0.08/Ge heterojunction located in channel region, at a distance of LT-H from the Ge0.92Sn0.08 source-channel tunneling junction (TJ). HE-PTFETs demonstrate the negative shift of onset voltage VONSET, the steeper subthreshold swing S, and the improved on-state current ION compared to Ge0.92Sn0.08 homo-PTFET. At low VGS, the suppression of BTBT due to the widening of the tunneling barrier caused by the heterojunction leads to a negative shift of VONSET in HE-PTFETs. At high VGS, ION enhancement in HE-PTFETs is achieved over the homo device, which is attributed to the confinement of BTBT in Ge0.92Sn0.08 source-channel TJ region by the heterojunction, where the short tunneling paths lead to a high tunneling probability. Due to the steeper average S, HE-PTFET with a 6 nm LT-H achieves a 4 times higher ION compared to homo device at a VDD of -0.3 V.

High Reliability of 0.1 μm InGaAs/InAlAs/InP High Electron Mobility Transistors Microwave Monolithic Integrated Circuit on 3-inch InP Substrates

NASA Astrophysics Data System (ADS)

Chou, Yeong-Chang; Leung, Denise; Lai, Richard; Grundbacher, Ron; Scarpulla, John; Barsky, Mike; Nishimoto, Matt; Eng, David; Liu, Po-Hsin; Oki, Aaron; Streit, Dwight

2002-02-01

The high-reliability performance of K-band microwave monolithic integrated circuit (MMIC) amplifiers fabricated with 0.1 μm gate length InGaAs/InAlAs/InP high electron mobility transistors (HEMTs) on 3-inch wafers using a high volume production process technology is reported. Operating at an accelerated life test condition of Vds=1.5 V and Ids=150 mA/mm, two-stage balanced amplifiers were lifetested at two-temperatures (T1=230°C, and T2=250°C) in nitrogen ambient. The activation energy (Ea) is as high as 1.5 eV, achieving a projected median-time-to-failure (MTTF) >1× 106 h at a 125°C of junction temperature. MTTF was determined by 2-temperature constant current stress using |Δ S21|>1.0 dB as the failure criteria. This is the first report of high reliability 0.1 μm InGaAs/InAlAs/InP HEMT MMICs based on small-signal microwave characteristics. This result demonstrates a reliable InGaAs/InAlAs/InP HEMT production technology.

Damage effect and mechanism of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

NASA Astrophysics Data System (ADS)

Xiao-Wen, Xi; Chang-Chun, Chai; Gang, Zhao; Yin-Tang, Yang; Xin-Hai, Yu; Yang, Liu

2016-04-01

The damage effect and mechanism of the electromagnetic pulse (EMP) on the GaAs pseudomorphic high electron mobility transistor (PHEMT) are investigated in this paper. By using the device simulation software, the distributions and variations of the electric field, the current density and the temperature are analyzed. The simulation results show that there are three physical effects, i.e., the forward-biased effect of the gate Schottky junction, the avalanche breakdown, and the thermal breakdown of the barrier layer, which influence the device current in the damage process. It is found that the damage position of the device changes with the amplitude of the step voltage pulse. The damage appears under the gate near the drain when the amplitude of the pulse is low, and it also occurs under the gate near the source when the amplitude is sufficiently high, which is consistent with the experimental results. Project supported by the National Basic Research Program of China (Grant No. 2014CB339900), and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (CAEP) (Grant No. 2015-0214.XY.K).

Light-Triggered Ternary Device and Inverter Based on Heterojunction of van der Waals Materials.

PubMed

Shim, Jaewoo; Jo, Seo-Hyeon; Kim, Minwoo; Song, Young Jae; Kim, Jeehwan; Park, Jin-Hong

2017-06-27

Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (V TH s). Here, we report a finding: the photoinduced drain current in graphene/WSe 2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe 2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe 2 -based MVL logic circuits by using the I D -V G characteristics with two distinctive V TH s. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔV out of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

NASA Technical Reports Server (NTRS)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Development of silicon carbide semiconductor devices for high temperature applications

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

1991-01-01

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Electrical characterization of the temperature dependence in CdTe/CdS heterojunctions deposited in-situ by pulsed laser deposition

NASA Astrophysics Data System (ADS)

Avila-Avendano, Jesus; Quevedo-Lopez, Manuel; Young, Chadwin

2018-02-01

The I-V and C-V characteristics of CdTe/CdS heterojunctions deposited in-situ by Pulsed Laser Deposition (PLD) were evaluated. In-situ deposition enables the study of the CdTe/CdS interface by avoiding potential impurities at the surface and interface as a consequence of exposure to air. The I-V and C-V characteristics of the resulting junctions were obtained at different temperatures, ranging from room temperature to 150 °C, where the saturation current (from 10-8 to 10-4 A/cm2), ideality factor (between 1 and 2), series resistance (from 102 to 105 Ω), built-in potential (0.66-0.7 V), rectification factor (˜106), and carrier concentration (˜1016 cm-3) were obtained. The current-voltage temperature dependence study indicates that thermionic emission is the main transport mechanism at the CdTe/CdS interface. This study also demonstrated that the built-in potential (Vbi) calculated using a thermionic emission model is more accurate than that calculated using C-V extrapolation since C-V plots showed a Vbi shift as a function of frequency. Although CdTe/CdS is widely used for photovoltaic applications, the parameters evaluated in this work indicate that CdTe/CdS heterojunctions could be used as rectifying diodes and junction field effect transistors (JFETs). JFETs require a low PN diode saturation current, as demonstrated for the CdTe/CdS junction studied here.

Fabrication of metallic single electron transistors featuring plasma enhanced atomic layer deposition of tunnel barriers

NASA Astrophysics Data System (ADS)

Karbasian, Golnaz

The continuing increase of the device density in integrated circuits (ICs) gives rise to the high level of power that is dissipated per unit area and consequently a high temperature in the circuits. Since temperature affects the performance and reliability of the circuits, minimization of the energy consumption in logic devices is now the center of attention. According to the International Technology Roadmaps for Semiconductors (ITRS), single electron transistors (SETs) hold the promise of achieving the lowest power of any known logic device, as low as 1x10-18 J per switching event. Moreover, SETs are the most sensitive electrometers to date, and are capable of detecting a fraction of an electron charge. Despite their low power consumption and high sensitivity for charge detection, room temperature operation of these devices is quite challenging mainly due to lithographical constraints in fabricating structures with the required dimensions of less than 10 nm. Silicon based SETs have been reported to operate at room temperature. However, they all suffer from significant variation in batch-to-batch performance, low fabrication yield, and temperature-dependent tunnel barrier height. In this project, we explored the fabrication of SETs featuring metal-insulator-metal (MIM) tunnel junctions. While Si-based SETs suffer from undesirable effect of dopants that result in irregularities in the device behavior, in metal-based SETs the device components (tunnel barrier, island, and the leads) are well-defined. Therefore, metal SETs are potentially more predictable in behavior, making them easier to incorporate into circuits, and easier to check against theoretical models. Here, the proposed fabrication method takes advantage of unique properties of chemical mechanical polishing (CMP) and plasma enhanced atomic layer deposition (PEALD). Chemical mechanical polishing provides a path for tuning the dimensions of the tunnel junctions, surpassing the limits imposed by electron beam lithography and lift-off, while atomic layer deposition provides precise control over the thickness of the tunnel barrier and significantly increases the choices for barrier materials. As described below in detail, the fabrication of ultra-thin (~1nm) tunnel transparent barriers with PEALD is in fact challenging; we demonstrate that in fabrication of SETs with PEALD to form the barrier in the Ni-insulator-Ni tunnel junctions, additional NiO layers are parasitically formed in the Ni layers that form the top and bottom electrodes of the tunnel junctions. The NiO on the bottom electrode is formed due to oxidizing effect of the O 2 plasma used in the PEALD process, while the NiO on the bottom of the top electrode is believed to form during the metal deposition due to oxygen-containing contaminants on the surface of the deposited tunnel barrier. We also show that due to the presence of these surface parasitic layers of NiO, the resistance of Ni-insulator-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with the tunnel barrier in series with compound layers of NiO and possibly, NiSixOy. The parasitic component in the tunnel junctions results in conduction freeze-out at low temperatures, deviation of junction parameters from ideal model, and excessive noise in the device. The reduction of NiO to Ni is therefore necessary to restore the metal-insulator-metal structure of the junctions. We have studied forming gas anneal as well as H2 plasma treatment as techniques to reduce the NiO layers that are parasitically formed in the junctions. Using either of these two techniques, we reduced the NiO formed on the island after being covered with the PEALD dielectric and before defining the top source and drain. Later, the NiO formed on the bottom of the source/drain is reduced during a second reducing step after the source/drain are formed on the tunnel barrier. Electrical characterization of SETs that are made with the proposed reducing treatments enable us to study the effect of each reducing process on the properties of the constituent tunnel junctions. In comparison to the junctions annealed twice in forming gas at 400°C, we consistently observed a ~10x higher conductance in devices treated twice with H2 plasma at 300°C. The possible damage to the barrier during the plasma treatment and thermally induced film deformation during the anneal which respectively, is believed to increase and lower the conductance are among the possible cause of this difference. Although both types of treatments were effective in alleviating the effect of the activated components in the junctions, all the devices that were treated by two anneal steps or by two H2 plasma steps (for reducing the top and bottom NiO) show deviations from ideal simulated MIM SET model and suffer from significant random telegraph signal (RTS) noise. However, our results show that by using forming gas anneal for bottom NiO reduction and H2 plasma for the top NiO reduction, one can achieve devices close to ideal MIM SETs with significantly less noise.

Characterization, Modeling and Design Parameters Identification of Silicon Carbide Junction Field Effect Transistor for Temperature Sensor Applications

PubMed Central

Salah, Tarek Ben; Khachroumi, Sofiane; Morel, Hervé

2010-01-01

Sensor technology is moving towards wide-band-gap semiconductors providing high temperature capable devices. Indeed, the higher thermal conductivity of silicon carbide, (three times more than silicon), permits better heat dissipation and allows better cooling and temperature management. Though many temperature sensors have already been published, little endeavours have been invested in the study of silicon carbide junction field effect devices (SiC-JFET) as a temperature sensor. SiC-JFETs devices are now mature enough and it is close to be commercialized. The use of its specific properties versus temperatures is the major focus of this paper. The SiC-JFETs output current-voltage characteristics are characterized at different temperatures. The saturation current and its on-resistance versus temperature are successfully extracted. It is demonstrated that these parameters are proportional to the absolute temperature. A physics-based model is also presented. Relationships between on-resistance and saturation current versus temperature are introduced. A comparative study between experimental data and simulation results is conducted. Important to note, the proposed model and the experimental results reflect a successful agreement as far as a temperature sensor is concerned. PMID:22315547

Synthesis of p-type GaN nanowires.

PubMed

Kim, Sung Wook; Park, Youn Ho; Kim, Ilsoo; Park, Tae-Eon; Kwon, Byoung Wook; Choi, Won Kook; Choi, Heon-Jin

2013-09-21

GaN has been utilized in optoelectronics for two decades. However, p-type doping still remains crucial for realization of high performance GaN optoelectronics. Though Mg has been used as a p-dopant, its efficiency is low due to the formation of Mg-H complexes and/or structural defects in the course of doping. As a potential alternative p-type dopant, Cu has been recognized as an acceptor impurity for GaN. Herein, we report the fabrication of Cu-doped GaN nanowires (Cu:GaN NWs) and their p-type characteristics. The NWs were grown vertically via a vapor-liquid-solid (VLS) mechanism using a Au/Ni catalyst. Electrical characterization using a nanowire-field effect transistor (NW-FET) showed that the NWs exhibited n-type characteristics. However, with further annealing, the NWs showed p-type characteristics. A homo-junction structure (consisting of annealed Cu:GaN NW/n-type GaN thin film) exhibited p-n junction characteristics. A hybrid organic light emitting diode (OLED) employing the annealed Cu:GaN NWs as a hole injection layer (HIL) also demonstrated current injected luminescence. These results suggest that Cu can be used as a p-type dopant for GaN NWs.

Josephson Photodetectors via Temperature-to-Phase Conversion

NASA Astrophysics Data System (ADS)

Virtanen, P.; Ronzani, A.; Giazotto, F.

2018-05-01

We theoretically investigate the temperature-to-phase conversion (TPC) process occurring in dc superconducting quantum interferometers based on superconductor-normal-metal-superconductor (S -N -S ) mesoscopic Josephson junctions. In particular, we predict the temperature-driven rearrangement of the phase gradients in the interferometer under the fixed constraints of fluxoid quantization and supercurrent conservation. This mechanism allows sizeable phase variations across the junctions for suitable structure parameters and temperatures. We show that the TPC can be a basis for sensitive single-photon sensors or bolometers. We propose a radiation detector realizable with conventional materials and state-of-the-art nanofabrication techniques. Integrated with a superconducting quantum-interference proximity transistor as a readout setup, an aluminum-based TPC calorimeter can provide a large signal-to-noise ratio >100 in the 10-GHz-10-THz frequency range and a resolving power larger than 1 02 below 50 mK for terahertz photons. In the bolometric operation, electrical noise equivalent power of approximately 10-22 W /√{Hz } is predicted at 50 mK. This device can be attractive as a cryogenic single-photon sensor operating in the giga- and terahertz regime with applications in dark-matter searches.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmid, H., E-mail: sih@zurich.ibm.com; Borg, M.; Moselund, K.

2015-06-08

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm{sup 2}/V s, while the alongsidemore » fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at V{sub DS} = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.« less

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Giant mesoscopic fluctuations of the elastic cotunneling thermopower of a single-electron transistor

NASA Astrophysics Data System (ADS)

Vasenko, A. S.; Basko, D. M.; Hekking, F. W. J.

2015-02-01

We study the thermoelectric transport of a small metallic island weakly coupled to two electrodes by tunnel junctions. In the Coulomb blockade regime, in the case when the ground state of the system corresponds to an even number of electrons on the island, the main mechanism of electron transport at the lowest temperatures is elastic cotunneling. In this regime, the transport coefficients strongly depend on the realization of the random impurity potential or the shape of the island. Using random-matrix theory, we calculate the thermopower and the thermoelectric kinetic coefficient and study the statistics of their mesoscopic fluctuations in the elastic cotunneling regime. The fluctuations of the thermopower turn out to be much larger than the average value.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Optically switched graphene/4H-SiC junction bipolar transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

PubMed Central

Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

2016-01-01

Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End

PubMed Central

Felini, Corrado; Della Corte, Francesco G.

2018-01-01

In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern. PMID:29301297

Graphene Exfoliation at a Ferroelectric Domain Wall Induced by the Piezoelectric Effect: Impact on the Conductance of the Graphene Channel

NASA Astrophysics Data System (ADS)

Morozovska, Anna N.; Kurchak, Anatolii I.; Strikha, Maksym V.

2017-11-01

p -n junctions in graphene on ferroelectric substrates have been actively studied, but the impact of the piezoelectric effect in ferroelectric substrate with ferroelectric domain walls (FDWs) on graphene characteristics was not considered. Because of the piezoeffect, ferroelectric domain stripes with opposite spontaneous polarizations elongate or contract depending on the polarity of voltage applied to the substrate. We show that the alternating piezoelectric displacement of the ferroelectric domain surfaces can lead to the alternate stretching and separation of graphene areas at the steps between elongated and contracted domains. Graphene separation at FDWs induced by the piezoeffect can cause unusual effects. In particular, the conductance of the graphene channel in a field-effect transistor increases significantly because electrons in the stretched section scatter on acoustic phonons. At the same time, the graphene conductance is determined by ferroelectric spontaneous polarization and varies greatly in the presence of FDWs. The revealed piezomechanism of graphene conductance control is promising for next generations of graphene-based field-effect transistors, modulators, electrical transducers, and piezoresistive elements. Also, our results propose the method of suspended graphene fabrication based on the piezoeffect in a ferroelectric substrate that does not require any additional technological procedures.

Thermal Analysis of AlGaN/GaN High-Electron-Mobility Transistor and Its RF Power Efficiency Optimization with Source-Bridged Field-Plate Structure.

PubMed

Kwak, Hyeon-Tak; Chang, Seung-Bo; Jung, Hyun-Gu; Kim, Hyun-Seok

2018-09-01

In this study, we consider the relationship between the temperature in a two-dimensional electron gas (2-DEG) channel layer and the RF characteristics of an AlGaN/GaN high-electron-mobility transistor by changing the geometrical structure of the field-plate. The final goal is to achieve a high power efficiency by decreasing the channel layer temperature. First, simulations were performed to compare and contrast the experimental data of a conventional T-gate head structure. Then, a source-bridged field-plate (SBFP) structure was used to obtain the lower junction temperature in the 2-DEG channel layer. The peak electric field intensity was reduced, and a decrease in channel temperature resulted in an increase in electron mobility. Furthermore, the gate-to-source capacitance was increased by the SBFP structure. However, under the large current flow condition, the SBFP structure had a lower maximum temperature than the basic T-gate head structure, which improved the device electron mobility. Eventually, an optimum position of the SBFP was used, which led to higher frequency responses and improved the breakdown voltages. Hence, the optimized SBFP structure can be a promising candidate for high-power RF devices.

Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism

NASA Astrophysics Data System (ADS)

Martino, Marcio Dalla Valle; Neves, Felipe; Ghedini Der Agopian, Paula; Martino, João Antonio; Vandooren, Anne; Rooyackers, Rita; Simoen, Eddy; Thean, Aaron; Claeys, Cor

2015-10-01

The goal of this work is to study the analog performance of tunnel field effect transistors (TFETs) and its susceptibility to temperature variation and to different dominant transport mechanisms. The experimental input characteristic of nanowire TFETs with different source compositions (100% Si and Si1-xGex) has been presented, leading to the extraction of the Activation Energy for each bias condition. These first results have been connected to the prevailing transport mechanism for each configuration, namely band-to-band tunneling (BTBT) or trap assisted tunneling (TAT). Afterward, this work analyzes the analog behavior, with the intrinsic voltage gain calculated in terms of Early voltage, transistor efficiency, transconductance and output conductance. Comparing the results for devices with different source compositions, it is interesting to note how the analog trends vary depending on the source characteristics and the prevailing transport mechanisms. This behavior results in a different suitability analysis depending on the working temperature. In other words, devices with full-Silicon source and non-abrupt junction profile present the worst intrinsic voltage gain at room temperature, but the best results for high temperatures. This was possible since, among the 4 studied devices, this configuration was the only one with a positive intrinsic voltage gain dependence on the temperature variation.

Performance evaluation of electro-optic effect based graphene transistors

NASA Astrophysics Data System (ADS)

Gupta, Gaurav; Abdul Jalil, Mansoor Bin; Yu, Bin; Liang, Gengchiau

2012-09-01

Despite the advantages afforded by the unique electronic properties of graphene, the absence of a bandgap has limited its applicability in logic devices. This has led to a study on electro-optic behavior in graphene for novel device operations, beyond the conventional field effect, to meet the requirements of ultra-low power and high-speed logic transistors. Recently, two potential designs have been proposed to leverage on this effect and open a virtual bandgap for ballistic transport in the graphene channel. The first one implements a barrier in the centre of the channel, whereas the second incorporates a tilted gate junction. In this paper, we computationally evaluate the relative device performance of these two designs, in terms of subthreshold slope (SS) and ION/IOFF ratio under different temperature and voltage bias, for a defect-free graphene channel. Our calculations employ pure optical modeling for low field electron transport under the constraints of device anatomy. The calculated results show that the two designs are functionally similar and are able to provide SS smaller than 60 mV per decade. Both designs show similar device performance but marginally top one another under different operating constraints. Our results could serve as a guide to circuit designers in selecting an appropriate design as per their system specifications and requirements.

Performance evaluation of electro-optic effect based graphene transistors.

PubMed

Gupta, Gaurav; Jalil, Mansoor Bin Abdul; Yu, Bin; Liang, Gengchiau

2012-10-21

Despite the advantages afforded by the unique electronic properties of graphene, the absence of a bandgap has limited its applicability in logic devices. This has led to a study on electro-optic behavior in graphene for novel device operations, beyond the conventional field effect, to meet the requirements of ultra-low power and high-speed logic transistors. Recently, two potential designs have been proposed to leverage on this effect and open a virtual bandgap for ballistic transport in the graphene channel. The first one implements a barrier in the centre of the channel, whereas the second incorporates a tilted gate junction. In this paper, we computationally evaluate the relative device performance of these two designs, in terms of subthreshold slope (SS) and I(ON)/I(OFF) ratio under different temperature and voltage bias, for a defect-free graphene channel. Our calculations employ pure optical modeling for low field electron transport under the constraints of device anatomy. The calculated results show that the two designs are functionally similar and are able to provide SS smaller than 60 mV per decade. Both designs show similar device performance but marginally top one another under different operating constraints. Our results could serve as a guide to circuit designers in selecting an appropriate design as per their system specifications and requirements.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Nanostructured p-type semiconducting transparent oxides: promising materials for nano-active devices and the emerging field of "transparent nanoelectronics".

PubMed

Banerjee, Arghya; Chattopadhyay, Kalyan K

2008-01-01

Transparent conducting oxides (TCO) with p-type semiconductivity have recently gained renewed interest for the fabrication of all-oxide transparent junctions, having potential applications in the emerging field of 'Transparent' or 'Invisible Electronics'. This kind of transparent junctions can be used as a "functional" window, which will transmit visible portion of solar radiation, but generates electricity by the absorption of the UV part. Therefore, these devices can be used as UV shield as well as UV cells. In this report, a brief review on the research activities on various p-TCO materials is furnished along-with the fabrication of different transparent p-n homojunction, heterojunction and field-effect transistors. Also the reason behind the difficulties in obtaining p-TCO materials and possible solutions are discussed in details. Considerable attention is given in describing the various patent generations on the field of p-TCO materials as well as transparent p-n junction diodes and light emitting devices. Also, most importantly, a detailed review and patenting activities on the nanocrystalline p-TCO materials and transparent nano-active device fabrication are furnished with considerable attention. And finally, a systematic description on the fabrication and characterization of nanocrystalline, p-type transparent conducting CuAlO(2) thin film, deposited by cost-effective low-temperature DC sputtering technique, by our group, is furnished in details. These p-TCO micro/nano-materials have wide range of applications in the field of optoelectronics, nanoelectronics, space sciences, field-emission displays, thermoelectric converters and sensing devices.

APCVD hexagonal boron nitride thin films for passive near-junction thermal management of electronics

NASA Astrophysics Data System (ADS)

KC, Pratik; Rai, Amit; Ashton, Taylor S.; Moore, Arden L.

2017-12-01

The ability of graphene to serve as an ultrathin heat spreader has been previously demonstrated with impressive results. However, graphene is electrically conductive, making its use in contact with electronic devices problematic from a reliability and integration perspective. As an alternative, hexagonal boron nitride (h-BN) is a similarly structured material with large in-plane thermal conductivity but which possesses a wide band gap, thereby giving it potential to be utilized for directing contact, near-junction thermal management of electronics without shorting or the need for an insulating intermediate layer. In this work, the viability of using large area, continuous h-BN thin films as direct contact, near-junction heat spreaders for electronic devices is experimentally evaluated. Thin films of h-BN several square millimeters in size were synthesized via an atmospheric pressure chemical vapor deposition (APCVD) method that is both simple and scalable. These were subsequently transferred onto a microfabricated test device that simulated a multigate transistor while also allowing for measurements of the device temperature at various locations via precision resistance thermometry. Results showed that these large-area h-BN films with thicknesses of 77-125 nm are indeed capable of significantly lowering microdevice temperatures, with the best sample showing the presence of the h-BN thin film reduced the effective thermal resistance by 15.9% ± 4.6% compared to a bare microdevice at the same power density. Finally, finite element simulations of these experiments were utilized to estimate the thermal conductivity of the h-BN thin films and identify means by which further heat spreading performance gains could be attained.

Multiband corrections for the semi-classical simulation of interband tunneling in GaAs tunnel junctions

NASA Astrophysics Data System (ADS)

Louarn, K.; Claveau, Y.; Hapiuk, D.; Fontaine, C.; Arnoult, A.; Taliercio, T.; Licitra, C.; Piquemal, F.; Bounouh, A.; Cavassilas, N.; Almuneau, G.

2017-09-01

The aim of this study is to investigate the impact of multiband corrections on the current density in GaAs tunnel junctions (TJs) calculated with a refined yet simple semi-classical interband tunneling model (SCITM). The non-parabolicity of the considered bands and the spin-orbit effects are considered by using a recently revisited SCITM available in the literature. The model is confronted to experimental results from a series of molecular beam epitaxy grown GaAs TJs and to numerical results obtained with a full quantum model based on the non-equilibrium Green’s function formalism and a 6-band k.p Hamiltonian. We emphasize the importance of considering the non-parabolicity of the conduction band by two different measurements of the energy-dependent electron effective mass in N-doped GaAs. We also propose an innovative method to compute the non-uniform electric field in the TJ for the SCITM simulations, which is of prime importance for a successful operation of the model. We demonstrate that, when considering the multiband corrections and this new computation of the non-uniform electric field, the SCITM succeeds in predicting the electrical characteristics of GaAs TJs, and are also in agreement with the quantum model. Besides the fundamental study of the tunneling phenomenon in TJs, the main benefit of this SCITM is that it can be easily embedded into drift-diffusion software, which are the most widely-used simulation tools for electronic and opto-electronic devices such as multi-junction solar cells, tunnel field-effect transistors, or vertical-cavity surface-emitting lasers.

Study on electrical properties of metal/GaSb junctions using metal-GaSb alloys

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nishi, Koichi, E-mail: nishi@mosfet.t.u-tokyo.ac.jp; Yokoyama, Masafumi; Kim, Sanghyeon

2014-01-21

We study the metal-GaSb alloy formation, the structural properties and the electrical characteristics of the metal-alloy/GaSb diodes by employing metal materials such as Ni, Pd, Co, Ti, Al, and Ta, in order to clarify metals suitable for GaSb p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) as metal-GaSb alloy source/drain (S/D). It is found that Ni, Pd, Co, and Ti can form alloy with GaSb by rapid thermal annealing at 250, 250, 350, and 450 °C, respectively. The Ni-GaSb and Pd-GaSb alloy formation temperature of 250 °C is lower than the conventional dopant activation annealing for ion implantation, which enable us to lower the processmore » temperature. The alloy layers show lower sheet resistance (R{sub Sheet}) than that of p{sup +}-GaSb layer formed by ion implantation and activation annealing. We also study the electrical characteristics of the metal-alloy/GaSb junctions. The alloy/n-GaSb contact has large Schottky barrier height (ϕ{sub B}) for electrons, ∼0.6 eV, and low ϕ{sub B} for holes, ∼0.2 eV, which enable us to realize high on/off ratio in pMOSFETs. We have found that the Ni-GaSb/GaSb Schottky junction shows the best electrical characteristics with ideal factor (n) of 1.1 and on-current/off-current ratio (I{sub on}/I{sub off}) of ∼10{sup 4} among the metal-GaSb alloy/GaSb junctions evaluated in the present study. These electrical properties are also superior to those of a p{sup +}-n diode fabricated by Be ion implantation with activation annealing at 350 °C. As a result, the Ni-GaSb alloy can be regarded as one of the best materials to realize metal S/D in GaSb pMOSFETs.« less

Tunneling contact IGZO TFTs with reduced saturation voltages

NASA Astrophysics Data System (ADS)

Wang, Longyan; Sun, Yin; Zhang, Xintong; Zhang, Lining; Zhang, Shengdong; Chan, Mansun

2017-04-01

We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

Hot-Electron-Induced Device Degradation during Gate-Induced Drain Leakage Stress

NASA Astrophysics Data System (ADS)

Kim, Kwang-Soo; Han, Chang-Hoon; Lee, Jun-Ki; Kim, Dong-Soo; Kim, Hyong-Joon; Shin, Joong-Shik; Lee, Hea-Beoum; Choi, Byoung-Deog

2012-11-01

We studied the interface state generation and electron trapping by hot electrons under gate-induced drain leakage (GIDL) stress in p-type metal oxide semiconductor field-effect transistors (P-MOSFETs), which are used as the high-voltage core circuit of flash memory devices. When negative voltage was applied to a drain in the off-state, a GIDL current was generated, but when high voltage was applied to the drain, electrons had a high energy. The hot electrons produced the interface state and electron trapping. As a result, the threshold voltage shifted and the off-state leakage current (trap-assisted drain junction leakage current) increased. On the other hand, electron trapping mitigated the energy band bending near the drain and thus suppressed the GIDL current generation.

Development of multi-layer crystal detector and related front end electronics

NASA Astrophysics Data System (ADS)

Cardarelli, R.; Di Ciaccio, A.; Paolozzi, L.

2014-05-01

A crystal (diamond) particle detector has been developed and tested, whose constitute elements are a multi-layer polycrystalline diamond and a pick-up system capable of collecting in parallel the charge produced in the layers. The charge is read with a charge-to-voltage amplifier (5-6 mV/fC) realized with bipolar junction transistors in order to minimize the effect of the detector capacitance. The tests performed with cosmic rays and at the beam test facility of Frascati with 500 MeV electrons in single electron mode operation have shown that a detector with 4-5 layers of 250 μm thickness each and 9 mm2 active area exhibits an upper limit of 150 ps time resolution for minimum ionizing particles at an operating voltage of about 350 V.

Cryogenic ultra-low power dissipation operational amplifiers with GaAs JFETs

NASA Astrophysics Data System (ADS)

Hibi, Yasunori; Matsuo, Hiroshi; Ikeda, Hirokazu; Fujiwara, Mikio; Kang, Lin; Chen, Jian; Wu, Peiheng

2016-01-01

To realize a multipixel camera for astronomical observation, we developed cryogenic multi-channel readout systems using gallium arsenide junction field-effect transistor (GaAs JFET) integrated circuits (ICs). Based on our experience with these cryogenic ICs, we designed, manufactured, and demonstrated operational amplifiers requiring four power supplies and two voltage sources. The amplifiers operate at 4.2 K with an open-loop gain of 2000. The gain-bandwidth product can expect 400 kHz at a power dissipation of 6 μW. In performance evaluations, the input-referred voltage noise was 4 μVrms/Hz0.5 at 1 Hz and 30 nVrms/Hz0.5 at 10 kHz, respectively. The noise power spectrum density was of type 1/f and extended to 10 kHz.

A back-illuminated megapixel CMOS image sensor

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

2005-01-01

In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spathis, C., E-mail: cspathis@ece.upatras.gr; Birbas, A.; Georgakopoulou, K.

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel andmore » quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.« less

Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour

NASA Astrophysics Data System (ADS)

Jain, Prateek; Yadav, Chandan; Agarwal, Amit; Chauhan, Yogesh Singh

2017-08-01

We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Japanese project aims at supercomputer that executes 10 gflops

DOE Office of Scientific and Technical Information (OSTI.GOV)

Burskey, D.

1984-05-03

Dubbed supercom by its multicompany design team, the decade-long project's goal is an engineering supercomputer that can execute 10 billion floating-point operations/s-about 20 times faster than today's supercomputers. The project, guided by Japan's Ministry of International Trade and Industry (MITI) and the Agency of Industrial Science and Technology encompasses three parallel research programs, all aimed at some angle of the superconductor. One program should lead to superfast logic and memory circuits, another to a system architecture that will afford the best performance, and the last to the software that will ultimately control the computer. The work on logic and memorymore » chips is based on: GAAS circuit; Josephson junction devices; and high electron mobility transistor structures. The architecture will involve parallel processing.« less

Nonlinear analysis of a family of LC tuned inverters

NASA Technical Reports Server (NTRS)

Lee, F. C. Y.; Wilson, T. G.

1975-01-01

Four widely used self-oscillating dc-to-square-wave parallel inverters which employ an inductor-capacitor tuned network to determine the oscillation frequency are reduced to a common equivalent RLC network, The techniques of singular-point analysis and state-plane interpretations are employed to describe the steady-state and transient behavior of these circuits and to elucidate the three possible modes of operation: quasi-harmonic, relaxation, and discontinuous. Design guidelines are provided through a study of the influence of circuit parameter variations on the characteristics of oscillation and on frequency stability. Several examples are provided to illustrate the usefulness of this analysis when studying such problems as transistor emitter-to-base junction breakdown during oscillations and the design of starting circuits to insure self-excited oscillations in these inverters.

Reversible Conversion of Dominant Polarity in Ambipolar Polymer/Graphene Oxide Hybrids

PubMed Central

Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Ma, Xinlei; Chen, Jihua; Zheng, Zijian; Roy, V. A. L.

2015-01-01

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. This hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits. PMID:25801827

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Significant accomplishments include development of a procedure to correct for the substantial differences of transistor delay time as measured with different instruments or with the same instrument at different frequencies; association of infrared response spectra of poor quality germanium gamma ray detectors with spectra of detectors fabricated from portions of a good crystal that had been degraded in known ways; and confirmation of the excellent quality and cosmetic appearance of ultrasonic bonds made with aluminum ribbon wire. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon, development of the infrared response technique; evaluation of wire bonds and die attachment; and measurement of thermal properties of semiconductor devices, delay time and related carrier transport properties in junction devices, and noise properties of microwave diodes.

Tunneling in BP-MoS2 heterostructure

NASA Astrophysics Data System (ADS)

Liu, Xiaochi; Qu, Deshun; Kim, Changsik; Ahmed, Faisal; Yoo, Won Jong

Tunnel field effect transistor (TFET) is considered to be a leading option for achieving SS <60 mV/dec. In this work, black phosphorus (BP) and molybdenum disulfide (MoS2) heterojunction devices are fabricated. We find that thin BP flake and MoS2 form normal p-n junctions, tunneling phenomena can be observed when BP thickness increases to certain level. PEO:CsClO4 is applied on the surface of the device together with a side gate electrode patterned together with source and drain electrodes. The Fermi level of MoS2 on top of BP layer can be modulated by the side gating, and this enables to vary the MoS2-BP tunnel diode property from off-state to on-state. Since tunneling is the working mechanism of MoS2-BP junction, and PEO:CsClO4\\ possesses ultra high dielectric constant and small equivalent oxide thickness (EOT), a low SS of 55 mV/dec is obtained from MoS2-BP TFET. This work was supported by the Global Research Laboratory and Global Frontier R&D Programs at the Center for Hybrid Interface Materials, both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea (NRF).

Modeling of Current-Voltage Characteristics in Large Metal-Semiconducting Carbon Nanotube Systems

NASA Technical Reports Server (NTRS)

Yamada, Toshishige; Biegel, Bryon A. (Technical Monitor)

2000-01-01

A model is proposed for two observed current-voltage (I-V) patterns in recent experiment with a scanning tunneling microscope tip and a carbon nanotube [Collins et al., Science 278, 100 (1997)]. We claim that there are two contact modes for a tip (metal)-nanotube (semiconductor) junction depending whether the alignment of the metal and the semiconductor band structures is (1) variable (vacuum-gap) or (2) fixed (touching) with V. With the tip grounded, the tunneling case in (1) would produce large dI/dV with V > 0, small dI/dV with V < 0, and I = 0 near V = 0 for an either n- or p-nanotube. However, the Schottky mechanism in (2) would result in forward current with V < 0 for an n-nanotube, while with V > 0 for an p-nanotube. The two observed I-V patterns are thus entirely explained by a tip-nanotube contact of the two types, where the nanotube must be n-type. We apply this model to the source-drain I-V characteristics in a long nanotube-channel field-effect-transistor with metallic electrodes at low temperature [Zhou et al., Appl. Phys. Lett. 76, 1597 (2000)], and show that two independent metal-semiconductor junctions in series are responsible for the observed behavior.

Thermal Performance Benchmarking: Annual Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Feng, Xuhui

In FY16, the thermal performance of the 2014 Honda Accord Hybrid power electronics thermal management systems were benchmarked. Both experiments and numerical simulation were utilized to thoroughly study the thermal resistances and temperature distribution in the power module. Experimental results obtained from the water-ethylene glycol tests provided the junction-to-liquid thermal resistance. The finite element analysis (FEA) and computational fluid dynamics (CFD) models were found to yield a good match with experimental results. Both experimental and modeling results demonstrate that the passive stack is the dominant thermal resistance for both the motor and power electronics systems. The 2014 Accord power electronicsmore » systems yield steady-state thermal resistance values around 42- 50 mm to the 2nd power K/W, depending on the flow rates. At a typical flow rate of 10 liters per minute, the thermal resistance of the Accord system was found to be about 44 percent lower than that of the 2012 Nissan LEAF system that was benchmarked in FY15. The main reason for the difference is that the Accord power module used a metalized-ceramic substrate and eliminated the thermal interface material layers. FEA models were developed to study the transient performance of 2012 Nissan LEAF, 2014 Accord, and two other systems that feature conventional power module designs. The simulation results indicate that the 2012 LEAF power module has lowest thermal impedance at a time scale less than one second. This is probably due to moving low thermally conductive materials further away from the heat source and enhancing the heat spreading effect from the copper-molybdenum plate close to the insulated gate bipolar transistors. When approaching steady state, the Honda system shows lower thermal impedance. Measurement results of the thermal resistance of the 2015 BMW i3 power electronic system indicate that the i3 insulated gate bipolar transistor module has significantly lower junction-to-liquid thermal resistance as compared to the other systems. At a flow rate of 12 liters per minute, the thermal resistance of the i3 systems is only 30 percent of the Accord system and 15 percent of the LEAF system.« less

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

NASA Astrophysics Data System (ADS)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

Bottom-up and top-down fabrication of nanowire-based electronic devices: In situ doping of vapor liquid solid grown silicon nanowires and etch-dependent leakage current in InGaAs tunnel junctions

NASA Astrophysics Data System (ADS)

Kuo, Meng-Wei

Semiconductor nanowires are important components in future nanoelectronic and optoelectronic device applications. These nanowires can be fabricated using either bottom-up or top-down methods. While bottom-up techniques can achieve higher aspect ratio at reduced dimension without having surface and sub-surface damage, uniform doping distributions with abrupt junction profiles are less challenging for top-down methods. In this dissertation, nanowires fabricated by both methods were systematically investigated to understand: (1) the in situ incorporation of boron (B) dopants in Si nanowires grown by the bottom-up vapor-liquid-solid (VLS) technique, and (2) the impact of plasma-induced etch damage on InGaAs p +-i-n+ nanowire junctions for tunnel field-effect transistors (TFETs) applications. In Chapter 2 and 3, the in situ incorporation of B in Si nanowires grown using silane (SiH4) or silicon tetrachloride (SiCl4) as the Si precursor and trimethylboron (TMB) as the p-type dopant source is investigated by I-V measurements of individual nanowires. The results from measurements using a global-back-gated test structure reveal nonuniform B doping profiles on nanowires grown from SiH4, which is due to simultaneous incorporation of B from nanowire surface and the catalyst during VLS growth. In contrast, a uniform B doping profile in both the axial and radial directions is achieved for TMBdoped Si nanowires grown using SiCl4 at high substrate temperatures. In Chapter 4, the I-V characteristics of wet- and dry-etched InGaAs p+-i-n+ junctions with different mesa geometries, orientations, and perimeter-to-area ratios are compared to evaluate the impact of the dry etch process on the junction leakage current properties. Different post-dry etch treatments, including wet etching and thermal annealing, are performed and the effectiveness of each is assessed by temperaturedependent I-V measurements. As compared to wet-etched control devices, dry-etched junctions have a significantly higher leakage current and a current kink in the reverse bias regime, which is likely due to additional trap states created by plasma-induced damage during the Cl2/Ar/H2 mesa isolation step. These states extend more than 60 nm from the mesa surface and can only be partially passivated after a thermal anneal at 350°C for 20 minutes. The evolution of the electrical properties with post-dry etch treatments indicates that the shallow and deep-level trap states resulting from ion-induced point defects, arsenic vacancies and hydrogen-dopant complexes are the primary cause of degradation in the electrical properties of the dry-etched junctions.

Real-time photoelectron spectroscopy study of the oxidation reaction kinetics on p-type and n-type Si (001) surfaces

NASA Astrophysics Data System (ADS)

Yu, Zhou

Silicon oxides thermally grown on Si surface are the core gate materials of metal-oxide-semiconductor field effect transistor (MOSFET). This thin oxide layer insulates the gate terminals and the transistors substrate which make MOSFET has certain advantages over those conventional junctions, such as field-effect transistor (FET) and junction field effect transistor (JFET). With an oxide insulating layer, MOSFET is able to sustain higher input impedance and the corresponding gate leakage current can be minimized. Today, though the oxidation process on Si substrate is popular in industry, there are still some uncertainties about its oxidation kinetics. On a path to clarify and modeling the oxidation kinetics, a study of initial oxidation kinetics on Si (001) surface has attracted attentions due to having a relatively low surface electron density and few adsorption channels compared with other Si surface direction. Based on previous studies, there are two oxidation models of Si (001) that extensively accepted, which are dual oxide species mode and autocatalytic reaction model. These models suggest the oxidation kinetics on Si (001) mainly relies on the metastable oxygen atom on the surface and the kinetic is temperature dependent. Professor Yuji Takakuwa's group, Surface Physics laboratory, Institute of Multidisciplinary Research for Advanced Materials, Tohoku University, observed surface strain existed during the oxidation kinetics on Si (001) and this is the first time that strain was discovered during Si oxidation. Therefore, it is necessary to explain where the strain comes from since none of previous model research included the surface strain (defects generation) into considerations. Moreover, recent developing of complementary metal-oxide-semiconductor (CMOS) requires a simultaneous oxidation process on p- and n-type Si substrate. However, none of those previous models included the dopant factor into the oxidation kinetic modeling. All of these points that further work is necessary to update and modify the traditional Si (001) oxidation models that had been accepted for several decades. To update and complement the Si (001) oxidation kinetics, an understanding of the temperature and dopant factor during initial oxidation kinetics on Si (001) is our first step. In this study, real-time photoelectron spectroscopy is applied to characterize the oxidized (001) surface and surface information was collected by ultraviolet photoelectron spectroscopy technique. By analyzing parameters such as O 2p spectra uptake, change of work function and the surface state in respect of p- and n- type Si (001) substrate under different temperature, the oxygen adsorption structure and the dopant factor can be determined. In this study, experiments with temperature gradients on p-type Si (001) were conducted and this aims to clarify the temperature dependent characteristic of Si (001) surface oxidation. A comparison of the O 2p uptake, change of work function and surface state between p-and n-type Si (001) is made under a normal temperature and these provides with the data to explain how the dopant factor impacts the oxygen adsorption structure on the surface. In the future, the study of the oxygen adsorption structure will lead to an explanation of the surface strain that discovered; therefore, fundamental of the initial oxidation on Si (001) would be updated and complemented, which would contribute to the future gate technology in MOSFET and CMOS.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

H+-type and OH--type biological protonic semiconductors and complementary devices

NASA Astrophysics Data System (ADS)

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Rousdari, Anita Fadavi; Helms, Brett A.; Zhong, Chao; Anantram, M. P.; Rolandi, Marco

2013-10-01

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H+ hop along chains of hydrogen bonds between water molecules and hydrophilic residues - proton wires. These wires also support the transport of OH- as proton holes. Discriminating between H+ and OH- transport has been elusive. Here, H+ and OH- transport is achieved in polysaccharide- based proton wires and devices. A H+- OH- junction with rectifying behaviour and H+-type and OH--type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H+ and OH- to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems.

Comparison of gain degradation and deep level transient spectroscopy in pnp Si bipolar junction transistors irradiated with different ion species

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aguirre, B. A.; Bielejec, E.; Fleming, R. M.

Here, we studied the effect of light ion and heavy ion irradiations on pnp Si BJTs. A mismatch in DLTS deep peak amplitude for devices with same final gain but irradiated with different ion species was observed. Also, different ions cause different gain degradation when the DLTS spectra are matched. Pre-dosed ion-irradiated samples show that ion induced ionization does not account for the differences in DLTS peak height but isochronal annealing studies suggest that light ions produce more VP defects than heavy ions to compensate for the lack of clusters that heavy ions produce. The creation of defect clusters bymore » heavy ions is evident by the higher content of E4 and V* 2 defects compared to light ions.« less

H+-type and OH−-type biological protonic semiconductors and complementary devices

PubMed Central

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Rousdari, Anita Fadavi; Helms, Brett A.; Zhong, Chao; Anantram, M. P.; Rolandi, Marco

2013-01-01

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H+ hop along chains of hydrogen bonds between water molecules and hydrophilic residues – proton wires. These wires also support the transport of OH− as proton holes. Discriminating between H+ and OH− transport has been elusive. Here, H+ and OH− transport is achieved in polysaccharide- based proton wires and devices. A H+- OH− junction with rectifying behaviour and H+-type and OH−-type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H+ and OH− to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems. PMID:24089083

Research on design feasibility of high-power light-weight dc-to-dc converters for space power applications

NASA Technical Reports Server (NTRS)

Wilson, T. G.

1981-01-01

Utilizing knowledge gained from past experience with experimental current-or-voltage step-up dc-to-dc converter power stages operating at output powers up to and in excess of 2 kW, a new experimental current-or-voltage step-up power stage using paralleled bipolar junction transistors (BJTs) as the controlled power switch, was constructed during the current reporting period. The major motivation behind the construction of this new experimental power stage was to improve the circuit layout so as to reduce the effects of stray circuit parasitic inductances resulting from excess circuit lead lengths and circuit loops, and to take advantage of the layout improvements which could be made when some recently-available power components, particularly power diodes and polypropylene filter capacitors, were incorporated into the design.

High mobility and high concentration Type-III heterojunction FET

NASA Astrophysics Data System (ADS)

Tsu, R.; Fiddy, M. A.; Her, T.

2018-02-01

The PN junction was introduced in transistors by doping, resulting in high losses due to Coulomb scattering from the dopants. The MOSFET introduced carriers in the form of electrons and holes with an applied bias to the oxide barrier, resulting in carrier transfer without doping. This avoids high scattering losses and dominates the IC industries. With heterojunctions having valence-band maxima near and even above the conduction-band minimum in the formation of Type-III superlattices, very useful devices, introduced by Tsu, Sai-Halacz, and Esaki, soon followed. If the layer thicknesses are more than the carrier mean-free-path, incoherent scattering results in the formation of carrier transfer via diffusion instead of opening up new energy gaps. The exploitation of carriers without scattering represents a new and significant opportunity in what we call a Broken Gap Heterojunction FET.

Advanced components for spaceborne infrared astronomy

NASA Technical Reports Server (NTRS)

Davidson, A. W.

1984-01-01

The need for improved cryogenic components to be used in future spaceborne infrared astronomy missions was identified. Improved low noise cryogenic amplifiers operated with infrared detectors, and better cryogenic actuators and motors with extremely low power dissipation are needed. The feasibility of achieving technological breakthroughs in both of these areas was studied. An improved silicon junction field effect transistor (JFET) could be developed if: (1) high purity silicon; (2) optimum dopants; and (3) very high doping levels are used. The feasibility of a simple stepper motor equipped with superconducting coils is demonstrated by construction of such a device based on a standard commercial motor. It is found that useful levels of torque at immeasurably low power levels were achieved. It is concluded that with modest development and optimization efforts, significant performance gains is possible for both cryogenic preamplifiers and superconducting motors and actuators.

High current density Esaki tunnel diodes based on GaSb-InAsSb heterostructure nanowires.

PubMed

Ganjipour, Bahram; Dey, Anil W; Borg, B Mattias; Ek, Martin; Pistol, Mats-Erik; Dick, Kimberly A; Wernersson, Lars-Erik; Thelander, Claes

2011-10-12

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.

Methods of measurement for semiconductor materials, process control, and devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1972-01-01

Activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices are described. Accomplishments include the determination of the reasons for differences in measurements of transistor delay time, identification of an energy level model for gold-doped silicon, and the finding of evidence that it does not appear to be necessary for an ultrasonic bonding tool to grip the wire and move it across the substrate metallization to make the bond. Work is continuing on measurement of resistivity of semiconductor crystals; study of gold-doped silicon; development of the infrared response technique; evaluation of wire bonds and die attachment; measurement of thermal properties of semiconductor devices, delay time, and related carrier transport properties in junction devices, and noise properties of microwave diodes; and characterization of silicon nuclear radiation detectors.

Reversible conversion of dominant polarity in ambipolar polymer/graphene oxide hybrids

DOE PAGES

Zhou, Ye; Han, Su -Ting; Sonar, Prashant; ...

2015-03-24

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. Wemore » conclude that this hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits.« less

Performance of a 100V Half-Bridge MOSFET Driver, Type MIC4103, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard L.; Hammoud, Ahmad

2011-01-01

The operation of a high frequency, high voltage MOSFET (metal-oxide semiconductor field-effect transistors) driver was investigated over a wide temperature regime that extended beyond its specified range. The Micrel MIC4103 is a 100V, non-inverting, dual driver that is designed to independently drive both high-side and low-side N-channel MOSFETs. It features fast propagation delay times and can drive 1000 pF load with 10ns rise times and 6 ns fall times [1]. The device consumes very little power, has supply under-voltage protection, and is rated for a -40 C to +125 C junction temperature range. The floating high-side driver of the chip can sustain boost voltages up to 100 V. Table I shows some of the device manufacturer s specification.

Comparison of gain degradation and deep level transient spectroscopy in pnp Si bipolar junction transistors irradiated with different ion species

DOE PAGES

Aguirre, B. A.; Bielejec, E.; Fleming, R. M.; ...

2016-12-09

Here, we studied the effect of light ion and heavy ion irradiations on pnp Si BJTs. A mismatch in DLTS deep peak amplitude for devices with same final gain but irradiated with different ion species was observed. Also, different ions cause different gain degradation when the DLTS spectra are matched. Pre-dosed ion-irradiated samples show that ion induced ionization does not account for the differences in DLTS peak height but isochronal annealing studies suggest that light ions produce more VP defects than heavy ions to compensate for the lack of clusters that heavy ions produce. The creation of defect clusters bymore » heavy ions is evident by the higher content of E4 and V* 2 defects compared to light ions.« less

Flexible hybrid circuit fully inkjet-printed: Surface mount devices assembled by silver nanoparticles-based inkjet ink

NASA Astrophysics Data System (ADS)

Arrese, J.; Vescio, G.; Xuriguera, E.; Medina-Rodriguez, B.; Cornet, A.; Cirera, A.

2017-03-01

Nowadays, inkjet-printed devices such as transistors are still unstable in air and have poor performances. Moreover, the present electronics applications require a high degree of reliability and quality of their properties. In order to accomplish these application requirements, hybrid electronics is fulfilled by combining the advantages of the printing technologies with the surface-mount technology. In this work, silver nanoparticle-based inkjet ink (AgNP ink) is used as a novel approach to connect surface-mount devices (SMDs) onto inkjet-printed pads, conducted by inkjet printing technology. Excellent quality AgNP ink-junctions are ensured with high resolution picoliter drop jetting at low temperature (˜150 °C). Electrical, mechanical, and morphological characterizations are carried out to assess the performance of the AgNP ink junction. Moreover, AgNP ink is compared with common benchmark materials (i.e., silver epoxy and solder). Electrical contact resistance characterization shows a similar performance between the AgNP ink and the usual ones. Mechanical characterization shows comparable shear strength for AgNP ink and silver epoxy, and both present higher adhesion than solder. Morphological inspections by field-emission scanning electron microscopy confirm a high quality interface of the silver nanoparticle interconnection. Finally, a flexible hybrid circuit on paper controlled by an Arduino board is manufactured, demonstrating the viability and scalability of the AgNP ink assembling technique.

Carbon-Nanotube-Confined Vertical Heterostructures with Asymmetric Contacts.

PubMed

Zhang, Jin; Zhang, Kenan; Xia, Bingyu; Wei, Yang; Li, Dongqi; Zhang, Ke; Zhang, Zhixing; Wu, Yang; Liu, Peng; Duan, Xidong; Xu, Yong; Duan, Wenhui; Fan, Shoushan; Jiang, Kaili

2017-10-01

Van der Waals (vdW) heterostructures have received intense attention for their efficient stacking methodology with 2D nanomaterials in vertical dimension. However, it is still a challenge to scale down the lateral size of vdW heterostructures to the nanometer and make proper contacts to achieve optimized performances. Here, a carbon-nanotube-confined vertical heterostructure (CCVH) is employed to address this challenge, in which 2D semiconductors are asymmetrically sandwiched by an individual metallic single-walled carbon nanotube (SWCNT) and a metal electrode. By using WSe 2 and MoS 2 , the CCVH can be made into p-type and n-type field effect transistors with high on/off ratios even when the channel length is 3.3 nm. A complementary inverter was further built with them, indicating their potential in logic circuits with a high integration level. Furthermore, the Fermi level of SWCNTs can be efficiently modulated by the gate voltage, making it competent for both electron and hole injection in the CCVHs. This unique property is shown by the transition of WSe 2 CCVH from unipolar to bipolar, and the transition of WSe 2 /MoS 2 from p-n junction to n-n junction under proper source-drain biases and gate voltages. Therefore, the CCVH, as a member of 1D/2D mixed heterostructures, shows great potentials in future nanoelectronics and nano-optoelectronics. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

InN/InGaN complementary heterojunction-enhanced tunneling field-effect transistor with enhanced subthreshold swing and tunneling current

NASA Astrophysics Data System (ADS)

Peng, Yue; Han, Genquan; Wang, Hongjuan; Zhang, Chunfu; Liu, Yan; Wang, Yibo; Zhao, Shenglei; Zhang, Jincheng; Hao, Yue

2016-05-01

InN/In0.75Ga0.25N complementary heterojunction-enhanced tunneling field-effect transistors (HE-TFETs) were characterized using the numerical simulation. InN/In0.75Ga0.25N HE-TFET has an InN/In0.75Ga0.25N heterojunction located in the channel region with a distance of LT-H from the source/channel tunneling junction. We demonstrate that, for both n- and p-channel devices, HE-TFETs have a delay of onset voltage VONSET, a steeper subthreshold swing (SS), and an enhanced on-state current ION in comparison with the homo-TFETs. InN/In0.75Ga0.25N n- and p-channel HE-TFETs with a gate length LG of 25 nm and a LT-H of 5 nm achieve a 7 and 9 times ION improvement in comparison with the homo devices, respectively, at a supply voltage of 0.3 V. The performance enhancement in HE-TFETs is attributed to the modulating effect of heterojunction on band-to-band tunneling (BTBT). Because InN/In0.75Ga0.25N heterointerface shows the similar band offsets at conduction and valence bands, the InN/In0.75Ga0.25N heterojunction exhibits the improved effect on BTBT for both n- and p-channel devices. This makes InN/In0.75Ga0.25N heterojunction a promising structure for high performance complementary TFETs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

NONE

Work under DOE Grant No. DE-FG47-93R701314, to investigate a Novel Process for Fabricating MOSFET Devices, has progressed to a point where feasibility of producing MOSFETS using Chromium Disilicide Schottky barrier junctions at Source and Drain has been shown. Devices fabricated, however, show inconsistent operating characteristics from device to device, and further work is required to overcome the defects. Some fabrication procedures have produced a relatively high, (e.g., ninety-five (95%) percent), yield of devices on a substrate which show at least some transistor action, while others have resulted in very low yield, (e.g., five (5%) percent). Consistency of results from devicemore » to device is less than desired. However, considering that the University of Nebraska at Lincoln (UNL) Electrical Engineering Fabrication Lab is not what industry can provide, it is reasonable to project that essentially one-hundred (99.99+%) percent yield should be achievable in an industrial setting because of the simplicity in the fabrication procedure.« less

Gate-Controlled BP-WSe2 Heterojunction Diode for Logic Rectifiers and Logic Optoelectronics.

PubMed

Li, Dong; Wang, Biao; Chen, Mingyuan; Zhou, Jun; Zhang, Zengxing

2017-06-01

p-n junctions play an important role in modern semiconductor electronics and optoelectronics, and field-effect transistors are often used for logic circuits. Here, gate-controlled logic rectifiers and logic optoelectronic devices based on stacked black phosphorus (BP) and tungsten diselenide (WSe 2 ) heterojunctions are reported. The gate-tunable ambipolar charge carriers in BP and WSe 2 enable a flexible, dynamic, and wide modulation on the heterojunctions as isotype (p-p and n-n) and anisotype (p-n) diodes, which exhibit disparate rectifying and photovoltaic properties. Based on such characteristics, it is demonstrated that BP-WSe 2 heterojunction diodes can be developed for high-performance logic rectifiers and logic optoelectronic devices. Logic optoelectronic devices can convert a light signal to an electric one by applied gate voltages. This work should be helpful to expand the applications of 2D crystals. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Implementing Bayesian networks with embedded stochastic MRAM

NASA Astrophysics Data System (ADS)

Faria, Rafatul; Camsari, Kerem Y.; Datta, Supriyo

2018-04-01

Magnetic tunnel junctions (MTJ's) with low barrier magnets have been used to implement random number generators (RNG's) and it has recently been shown that such an MTJ connected to the drain of a conventional transistor provides a three-terminal tunable RNG or a p-bit. In this letter we show how this p-bit can be used to build a p-circuit that emulates a Bayesian network (BN), such that the correlations in real world variables can be obtained from electrical measurements on the corresponding circuit nodes. The p-circuit design proceeds in two steps: the BN is first translated into a behavioral model, called Probabilistic Spin Logic (PSL), defined by dimensionless biasing (h) and interconnection (J) coefficients, which are then translated into electronic circuit elements. As a benchmark example, we mimic a family tree of three generations and show that the genetic relatedness calculated from a SPICE-compatible circuit simulator matches well-known results.

Microwave SQUID Multiplexer for the Readout of Metallic Magnetic Calorimeters

NASA Astrophysics Data System (ADS)

Kempf, S.; Gastaldo, L.; Fleischmann, A.; Enss, C.

2014-06-01

We have realized a frequency-domain multiplexing technique for the readout of large metallic magnetic calorimeter detector arrays. It is based on non-hysteretic single-junction SQUIDs and allows for a simultaneous readout of hundreds or thousands of detectors by using a single cryogenic high electron mobility transistor amplifier and two coaxial cables that are routed from room-temperature to the detector array. We discuss the working principle of the multiplexer and present details about our prototype multiplexer design. We show that fabricated devices are fully operational and that characteristic SQUID parameters such as the input sensitivity of the SQUID or the resonance frequency of the readout circuit can be predicted with confidence. Our best device so far has shown a magnetic flux white noise level of 1.4 m which can in future be reduced by an optimization of the fabrication processes as well as an improved microwave readout system.

SQUID amplifiers for axion search experiments

NASA Astrophysics Data System (ADS)

Matlashov, Andrei; Schmelz, Matthias; Zakosarenko, Vyacheslav; Stolz, Ronny; Semertzidis, Yannis K.

2018-04-01

In the experiments for dark-matter QCD-axion searches, very weak microwave signals from a low-temperature High-Q resonant cavity should be detected using the highest sensitivity. The best commercial low-noise cryogenic semiconductor amplifiers based on high electron mobility transistors have a lowest noise temperature above 1.0 K, even if they are cooled well below 1 K. Superconducting quantum interference devices can work as microwave amplifiers with temperature noise close to the standard quantum limit. Previous SQUID-based RF amplifiers designed for axion search experiments have a microstrip resonant input coil and are thus called micro-strip SQUID amplifiers or MSAs. Due to the resonant input coupling they usually have narrow bandwidth. In this paper we report on a SQUID-based wideband microwave amplifier fabricated using sub-micron size Josephson junctions with very low capacitance. A single amplifier can be used in a frequency range of approximately 1-5 GHz.

Space solar cell technology development - A perspective

NASA Technical Reports Server (NTRS)

Scott-Monck, J.

1982-01-01

The developmental history of photovoltaics is examined as a basis for predicting further advances to the year 2000. Transistor technology was the precursor of solar cell development. Terrestrial cells were modified for space through changes in geometry and size, as well as the use of Ag-Ti contacts and manufacture of a p-type base. The violet cell was produced for Comsat, and involved shallow junctions, new contacts, and an enhanced antireflection coating for better radiation tolerance. The driving force was the desire by private companies to reduce cost and weight for commercial satellite power supplies. Liquid phase epitaxial (LPE) GaAs cells are the latest advancement, having a 4 sq cm area and increased efficiency. GaAs cells are expected to be flight ready in the 1980s. Testing is still necessary to verify production techniques and the resistance to electron and photon damage. Research will continue in CVD cell technology, new panel technology, and ultrathin Si cells.

Uniaxial angular accelerometers

NASA Astrophysics Data System (ADS)

Seleznev, A. V.; Shvab, I. A.

1985-05-01

The basic mechanical components of an angular accelerometer are the sensor, the damper, and the transducer. Penumatic dampers are simplest in construction, but the viscosity of air is very low and, therefore, dampers with special purpose oils having a high temperature stability (synthetic silicon or organosilicon oils) are most widely used. The most common types of viscous dampers are lamellar with meshed opposed arrays of fixed and movable vanes in the dashpot, piston dampers regulated by an adjustable-length capillary tube, and dampers with paddle wheel in closed tank. Another type of damper is an impact-inertial one with large masses absorbing the rotational energy upon collision with the sensor. Conventional measuring elements are resistive, capacitive, electromagnetic, photoelectric, and penumatic or hydraulic. Novel types of angular accelerometers are based on inertia of gas jets, electron beams, and ion beams, the piezoelectric effect in p-n junctions of diode and transistors, the electrokinetic effect in fluids, and cryogenic suspension of the sensor.

Improving off-state leakage characteristics for high voltage AlGaN/GaN-HFETs on Si substrates

NASA Astrophysics Data System (ADS)

Moon, Sung-Woon; Twynam, John; Lee, Jongsub; Seo, Deokwon; Jung, Sungdal; Choi, Hong Goo; Shim, Heejae; Yim, Jeong Soon; Roh, Sungwon D.

2014-06-01

We present a reliable process and design technique for realizing high voltage AlGaN/GaN hetero-junction field effect transistors (HFETs) on Si substrates with very low and stable off-state leakage current characteristics. In this work, we have investigated the effects of the surface passivation layer, prepared by low pressure chemical vapor deposition (LPCVD) of silicon nitride (SiNx), and gate bus isolation design on the off-state leakage characteristics of metal-oxide-semiconductor (MOS) gate structure-based GaN HFETs. The surface passivated devices with gate bus isolation fully surrounding the source and drain regions showed extremely low off-state leakage currents of less than 20 nA/mm at 600 V, with very small variation. These techniques were successfully applied to high-current devices with 80-mm gate width, yielding excellent off-state leakage characteristics within a drain voltage range 0-700 V.

High-Tc Superconducting Bolometer Noise Measurement Using Low Noise Transformers - Theory and Optimization

NASA Technical Reports Server (NTRS)

Aslam, Shahid; Jones, Hollis H.

2011-01-01

Care must always be taken when performing noise measurements on high-Tc superconducting materials to ensure that the results are not from the measurement system itself. One situation likely to occur is with low noise transformers. One of the least understood devices, it provides voltage gain for low impedance inputs (< 100 ), e.g., YBaCuO and GdBaCuO thin films, with comparatively lower noise levels than other devices for instance field effect and bipolar junction transistors. An essential point made in this paper is that because of the complex relationships between the transformer ports, input impedance variance alters the transformer s transfer function in particular, the low frequency cutoff shift. The transfer of external and intrinsic transformer noise to the output along with optimization and precautions are treated; all the while, we will cohesively connect the transfer function shift, the load impedance, and the actual noise at the transformer output.

Controlled Trapping of Onion-Like Carbon (OLC) via Dielectrophoresis

NASA Astrophysics Data System (ADS)

Olariu, Marius; Arcire, Alexandru; Plonska-Brzezinska, Marta E.

2017-01-01

Manipulation of onion-like carbon (OLC), also known as carbon nano-onions (CNOs), at the level of various arrays of microelectrodes is vital in practical applications such as biological and chemical sensing, ultracapacitors (supercapacitors), electromagnetic shielding, catalysis, tribology, optical limiting and molecular junctions in scanning tunneling microscopy, and field-effect transistors. In spite of technological developments in this area, rigorous handling of carbon nano-onions towards desired locations within a device remains a challenge, and the quantity of OLC required significantly influences the price of the final electrical or electronic device. We present herein an experimental study on electromanipulation and trapping of onion-like carbon (OLC) at the level of gold-patterned interdigitated microelectrodes through dielectrophoresis. The influence of the magnitude as well as frequency of the alternating-current (AC) voltage employed for OLC trapping is discussed in detail. The effects of tuning the AC field strength and frequency on the OLC trapping behavior are also considered.

Analog tree-organized multiplexer

NASA Technical Reports Server (NTRS)

Crabbe, J. S.; Smith, D. M.; Turner, W. R.

1971-01-01

An analog tree-organized multiplexer (ATOM) which is intended for use in the telemetry system of an interplanetary spacecraft is designed. The ATOM will be fabricated by a monolithic, dielectric isolation process, and will contain silicon junction field effect transistors (JFET) as the active elements. The effect of the radiation environment on the performance of the ATOM is analyzed. The result indicates that the expected radiation environment will cause only minor changes in the preradiation characteristics of ATOM. The JFET in the ATOM is designed to meet the electrical requirements when fabricated by either the double poly-dielectric isolation process or the raised dielectric isolation process. The effect of the heat treatment required for the dielectric isolation process on the diffusion profile of the JFET is described. The layout of the ATOM circuit for fabrication by either the double poly or raised dielectric isolation process is also given.

Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

NASA Astrophysics Data System (ADS)

Lahgere, Avinash; Panchore, Meena; Singh, Jawar

2016-08-01

In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10× improvement in on-current, 100× reduced leakage current, 3× more transconductance (gm), and on-off current ratio of ∼1011 as compared to DL-TFET.

Performance analysis of gate all around GaAsP/AlGaSb CP-TFET

NASA Astrophysics Data System (ADS)

Lemtur, Alemienla; Sharma, Dheeraj; Suman, Priyanka; Patel, Jyoti; Yadav, Dharmendra Singh; Sharma, Neeraj

2018-05-01

Illustration of importance of gate all around (GAA) structure and hetero-junction formed by III-V semiconductor compounds has been analysed through GaAsP/AlGaSb CP-TFET (charge plasma tunnel field effect transistor). Charge plasma concept has been incorporated here to make this device more immune towards random dopant fluctuations (RDF). A high driving current of 1.28 ×10-5 A/μm and transconductance (gm) of 96.4 μS at supply voltages VGS = 1V and VDS = 0.5V is achieved. Further, implications of employing this device in analog/RF circuits have been supported with simulated results showing a high cut-off frequency of 34.5 THz and device efficiency of 3.45 MV-1. Apart from this, an insight of the linearity performances has also been included. Simultaneously, all the results are compared with a conventional gate all around charge plasma TFET.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, J.B.; Kaschmitter, J.L.; Thompson, J.B.; Sigmon, T.W.

1995-06-20

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate is disclosed, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27--730 C is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including HETEROJUNCTION-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

Pulsed energy synthesis and doping of silicon carbide

DOEpatents

Truher, Joel B.; Kaschmitter, James L.; Thompson, Jesse B.; Sigmon, Thomas W.

1995-01-01

A method for producing beta silicon carbide thin films by co-depositing thin films of amorphous silicon and carbon onto a substrate, whereafter the films are irradiated by exposure to a pulsed energy source (e.g. excimer laser) to cause formation of the beta-SiC compound. Doped beta-SiC may be produced by introducing dopant gases during irradiation. Single layers up to a thickness of 0.5-1 micron have been produced, with thicker layers being produced by multiple processing steps. Since the electron transport properties of beta silicon carbide over a wide temperature range of 27.degree.-730.degree. C. is better than these properties of alpha silicon carbide, they have wide application, such as in high temperature semiconductors, including hetero-junction bipolar transistors and power devices, as well as in high bandgap solar arrays, ultra-hard coatings, light emitting diodes, sensors, etc.

A 700 V narrow channel nJFET with low pinch-off voltage and suppressed drain-induced barrier lowering effect

NASA Astrophysics Data System (ADS)

Mao, Kun; Qiao, Ming; Zhang, WenTong; Zhang, Bo; Li, Zhaoji

2014-11-01

This paper proposes a 700 V narrow channel region triple-RESURF (reduced surface field) n-type junction field-effect transistor (NCT-nJFET). Compared to traditional structures, low pinch-off voltage (VP) with unobvious drain-induced barrier lowering (DIBL) effect and large saturated current (IDsat) are achieved. This is because p-type buried layer (Pbury) and PWELL are introduced to shape narrow n-type channel in JFET channel region. DIBL sensitivity (SDIBL) is firstly introduced in this paper to analyze the DIBL effect of high-voltage long-channel JFET. Ultra-high breakdown voltage is obtained by triple RESURF technology. Experimental results show that proposed NCT-nJFET achieves 24-V VP, 3.5% SDIBL, 2.3-mA IDsat, 800-V OFF-state breakdown voltage (OFF-BV) and 650-V ON-state breakdown voltage when VGS equals 0 V (ON-BV).

Extraction method of interfacial injected charges for SiC power MOSFETs

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

2018-01-01

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

High performance InP JFETs grown by MOCVD using tertiarybutylphosphine

NASA Astrophysics Data System (ADS)

Hashemi, M. M.; Shealy, J. B.; Corvini, P. J.; Denbaars, S. P.; Mishra, U. K.

1994-02-01

Indium phosphide channel junction field effect transistors were fabricated by metalorganic chemical vapor deposition using tertiarybulylphosphine (TBP) as the alternative source for phosphine. At growth temperatures of 600°C, InP with specular surface morphology and mobilities as high as 61000 cm2/V s at 77Khas been achieved using trimethylindium and TBP. To improve device isolation, pinch-off characteristics, and output transconductance, we employ a high resistivity (1 × 108 Ω-cm) semi-insulating InP buffer layer using ferrocene as the Fe-dopant. Devices with gate lengths of 1 urn exhibit very high extrinsic transconductance of 130 mS/mm, gate-drain breakdown voltage exceeding 20 V, maximum current density of >450 mA/mm with record high fT and fmax of 15 GHz and 35 GHz, respectively. These results indicate: that InP JFETs are promising electronic devices for microwave power amplification, and that TBP is capable of device quality materials.

Graphene Dirac point tuned by ferroelectric polarization field

NASA Astrophysics Data System (ADS)

Wang, Xudong; Chen, Yan; Wu, Guangjian; Wang, Jianlu; Tian, Bobo; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Kang, Tingting; Tang, Minghua; Xiao, Yongguang; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao

2018-04-01

Graphene has received numerous attention for future nanoelectronics and optoelectronics. The Dirac point is a key parameter of graphene that provides information about its carrier properties. There are lots of methods to tune the Dirac point of graphene, such as chemical doping, impurities, defects, and disorder. In this study, we report a different approach to tune the Dirac point of graphene using a ferroelectric polarization field. The Dirac point can be adjusted to near the ferroelectric coercive voltage regardless its original position. We have ensured this phenomenon by temperature-dependent experiments, and analyzed its mechanism with the theory of impurity correlation in graphene. Additionally, with the modulation of ferroelectric polymer, the current on/off ratio and mobility of graphene transistor both have been improved. This work provides an effective method to tune the Dirac point of graphene, which can be readily used to configure functional devices such as p-n junctions and inverters.

Transistor Effect in Improperly Connected Transistors.

ERIC Educational Resources Information Center

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

AITRAC: Augmented Interactive Transient Radiation Analysis by Computer. User's information manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

1977-10-01

AITRAC is a program designed for on-line, interactive, DC, and transient analysis of electronic circuits. The program solves linear and nonlinear simultaneous equations which characterize the mathematical models used to predict circuit response. The program features 100 external node--200 branch capability; conversional, free-format input language; built-in junction, FET, MOS, and switch models; sparse matrix algorithm with extended-precision H matrix and T vector calculations, for fast and accurate execution; linear transconductances: beta, GM, MU, ZM; accurate and fast radiation effects analysis; special interface for user-defined equations; selective control of multiple outputs; graphical outputs in wide and narrow formats; and on-line parametermore » modification capability. The user describes the problem by entering the circuit topology and part parameters. The program then automatically generates and solves the circuit equations, providing the user with printed or plotted output. The circuit topology and/or part values may then be changed by the user, and a new analysis, requested. Circuit descriptions may be saved on disk files for storage and later use. The program contains built-in standard models for resistors, voltage and current sources, capacitors, inductors including mutual couplings, switches, junction diodes and transistors, FETS, and MOS devices. Nonstandard models may be constructed from standard models or by using the special equations interface. Time functions may be described by straight-line segments or by sine, damped sine, and exponential functions. 42 figures, 1 table. (RWR)« less

Perimeter Governed Minority Carrier Lifetimes in 4H-SiC p(+)-n Diodes Measured by Reverse Recovery Switching Transient Analysis

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

1998-01-01

Minority carrier lifetimes in epitaxial 4H-SiC p(+)-n junction diodes were measured via an analysis of reverse recovery switching characteristics. Behavior of reverse recovery storage time (t(s)) as a function of initial ON-state forward current (I(F)) and OFF-state reverse current (I(R)) followed well-documented trends which have been observed for decades in silicon p-n rectifiers. Average minority carrier (hole) lifetimes (tau(p)) calculated from plots of t(s) vs I(R)/I(F) strongly decreased with decreasing device area. Bulk and perimeter components of average hole lifetimes were separated by plotting 1/tau(p) as a function of device perimeter-to- area ratio (P/A). This plot reveals that perimeter recombination is dominant in these devices, whose areas are all less than 1 sq mm. The bulk minority carrier (hole) lifetime extracted from the 1/tau(p) vs P/A plot is approximately 0.7 micro-s, well above the 60 ns to 300 ns average iit'eptimes obtained when perimeter recombination effects are ignored in the analysis. Given the fact that there has been little previous investigation of bipolar diode and transistor performance as a function of perimeter-to-area ratio, this work raises the possibility that perimeter recombination may be partly responsible for poor effective minority carrier lifetimes and limited performance obtained in many previous SiC bipolar junction devices.

Perimeter Governed Minority Carrier Lifetimes in 4H-SiC p+n Diodes Measured by Reverse Recovery Switching Transient Analysis

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.

1998-01-01

Minority carrier lifetimes in epitaxial 4H-SiC p-n junction diodes were measured via an analysis of reverse recovery switching characteristics. Behavior of reverse recovery storage time (t(sub s)) as a function of initial ON-state forward current (I(sub f)) and OFF-state reverse current (I(sub R)) followed well-documented trends which have been observed for decades in silicon p-n rectifiers. Average minority carrier (hole) lifetimes (tau(sub p)) calculated from plots of t(sub s) vs I(sub R)/I(sub F) strongly decreased with decreasing device area. Bulk and perimeter components of average hole lifetimes were separated by plotting tau(sub p) as a function of device perimeter-to-area ratio (P/A). This plot reveals that perimeter recombination is dominant in these devices, whose areas are all less than 1 square mm. The bulk minority carrier (hole) lifetime extracted from the 1/Tau(sub p) vs P/A plot is approximately 0.7 microns, well above the 60 ns to 300 ns average lifetimes obtained when perimeter recombination effects are ignored in the analysis. Given the fact that there has been little previous investigation of bipolar diode and transistor performance as a function of perimeter-to-area ratio, this work raises the possibility that perimeter recombination may be partly responsible for poor effective minority carrier lifetimes and limited performance obtained in many previous SiC bipolar junction devices.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

SiC Optically Modulated Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Tabib-Azar, Massood

2009-01-01

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.

Analyses of Transistor Punchthrough Failures

NASA Technical Reports Server (NTRS)

Nicolas, David P.

1999-01-01

The failure of two transistors in the Altitude Switch Assembly for the Solid Rocket Booster followed by two additional failures a year later presented a challenge to failure analysts. These devices had successfully worked for many years on numerous missions. There was no history of failures with this type of device. Extensive checks of the test procedures gave no indication for a source of the cause. The devices were manufactured more than twenty years ago and failure information on this lot date code was not readily available. External visual exam, radiography, PEID, and leak testing were performed with nominal results Electrical testing indicated nearly identical base-emitter and base-collector characteristics (both forward and reverse) with a low resistance short emitter to collector. These characteristics are indicative of a classic failure mechanism called punchthrough. In failure analysis punchthrough refers to an condition where a relatively low voltage pulse causes the device to conduct very hard producing localized areas of thermal runaway or "hot spots". At one or more of these hot spots, the excessive currents melt the silicon. Heavily doped emitter material diffuses through the base region to the collector forming a diffusion pipe shorting the emitter to base to collector. Upon cooling, an alloy junction forms between the pipe and the base region. Generally, the hot spot (punch-through site) is under the bond and no surface artifact is visible. The devices were delidded and the internal structures were examined microscopically. The gold emitter lead was melted on one device, but others had anomalies in the metallization around the in-tact emitter bonds. The SEM examination confirmed some anomalies to be cosmetic defects while other anomalies were artifacts of the punchthrough site. Subsequent to these analyses, the contractor determined that some irregular testing procedures occurred at the time of the failures heretofore unreported. These testing irregularities involved the use of a breakout box and were the likely cause of the failures. There was no evidence to suggest a generic failure mechanism was responsible for the failure of these transistors.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

NASA Technical Reports Server (NTRS)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

PubMed

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

2015-10-01

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Rhombic Coulomb diamonds in a single-electron transistor based on an Au nanoparticle chemically anchored at both ends.

PubMed

Azuma, Yasuo; Onuma, Yuto; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-02-28

Rhombic Coulomb diamonds are clearly observed in a chemically anchored Au nanoparticle single-electron transistor. The stability diagrams show stable Coulomb blockade phenomena and agree with the theoretical curve calculated using the orthodox model. The resistances and capacitances of the double-barrier tunneling junctions between the source electrode and the Au core (R1 and C1, respectively), and those between the Au core and the drain electrode (R2 and C2, respectively), are evaluated as 4.5 MΩ, 1.4 aF, 4.8 MΩ, and 1.3 aF, respectively. This is determined by fitting the theoretical curve against the experimental Coulomb staircases. Two-methylene-group short octanedithiols (C8S2) in a C8S2/hexanethiol (C6S) mixed self-assembled monolayer is concluded to chemically anchor the core of the Au nanoparticle at both ends between the electroless-Au-plated nanogap electrodes even when the Au nanoparticle is protected by decanethiol (C10S). This is because the R1 value is identical to that of R2 and corresponds to the tunneling resistances of the octanedithiol chemically bonded with the Au core and the Au electrodes. The dependence of the Coulomb diamond shapes on the tunneling resistance ratio (R1/R2) is also discussed, especially in the case of the rhombic Coulomb diamonds. Rhombic Coulomb diamonds result from chemical anchoring of the core of the Au nanoparticle at both ends between the electroless-Au-plated nanogap electrodes.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

Evolvable circuit with transistor-level reconfigurability

NASA Technical Reports Server (NTRS)

Stoica, Adrian (Inventor); Salazar-Lazaro, Carlos Harold (Inventor)

2004-01-01

An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.

Transistor-based interface circuitry

DOEpatents

Taubman, Matthew S [Richland, WA

2007-02-13

Among the embodiments of the present invention is an apparatus that includes a transistor, a servo device, and a current source. The servo device is operable to provide a common base mode of operation of the transistor by maintaining an approximately constant voltage level at the transistor base. The current source is operable to provide a bias current to the transistor. A first device provides an input signal to an electrical node positioned between the emitter of the transistor and the current source. A second device receives an output signal from the collector of the transistor.

Transistor-based particle detection systems and methods

DOEpatents

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Multiple-channel detection of cellular activities by ion-sensitive transistors

NASA Astrophysics Data System (ADS)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

Josephson parametric phase-locked oscillator and its application to dispersive readout of superconducting qubits

NASA Astrophysics Data System (ADS)

Lin, Z. R.; Inomata, K.; Koshino, K.; Oliver, W. D.; Nakamura, Y.; Tsai, J. S.; Yamamoto, T.

2014-07-01

The parametric phase-locked oscillator (PPLO) is a class of frequency-conversion device, originally based on a nonlinear element such as a ferrite ring, that served as a fundamental logic element for digital computers more than 50 years ago. Although it has long since been overtaken by the transistor, there have been numerous efforts more recently to realize PPLOs in different physical systems such as optical photons, trapped atoms, and electromechanical resonators. This renewed interest is based not only on the fundamental physics of nonlinear systems, but also on the realization of new, high-performance computing devices with unprecedented capabilities. Here we realize a PPLO with Josephson-junction circuitry and operate it as a sensitive phase detector. Using a PPLO, we demonstrate the demodulation of a weak binary phase-shift keying microwave signal of the order of a femtowatt. We apply PPLO to dispersive readout of a superconducting qubit, and achieved high-fidelity, single-shot and non-destructive readout with Rabi-oscillation contrast exceeding 90%.

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

2016-01-01

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

Automated Array Assembly, Phase 2

NASA Technical Reports Server (NTRS)

Carbajal, B. G.

1979-01-01

The solar cell module process development activities in the areas of surface preparation are presented. The process step development was carried out on texture etching including the evolution of a conceptual process model for the texturing process; plasma etching; and diffusion studies that focused on doped polymer diffusion sources. Cell processing was carried out to test process steps and a simplified diode solar cell process was developed. Cell processing was also run to fabricate square cells to populate sample minimodules. Module fabrication featured the demonstration of a porcelainized steel glass structure that should exceed the 20 year life goal of the low cost silicon array program. High efficiency cell development was carried out in the development of the tandem junction cell and a modification of the TJC called the front surface field cell. Cell efficiencies in excess of 16 percent at AM1 have been attained with only modest fill factors. The transistor-like model was proposed that fits the cell performance and provides a guideline for future improvements in cell performance.

Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET

NASA Astrophysics Data System (ADS)

Nigam, Kaushal; Gupta, Sarthak; Pandey, Sunil; Kondekar, P. N.; Sharma, Dheeraj

2018-05-01

Ambipolar conduction in tunnel field-effect transistors (TFETs) has been occurred as an inherent issue due to drain-channel tunneling. It makes TFET less efficient and restricts its application in complementary digital circuits. Therefore, this manuscript reports the application of Gaussian doping profile on nanometer regime silicon channel TFETs to completely eliminate the ambipolarity. For this, Gaussian doping is used in the drain region of conventional gate-drain overlap TFET to control the tunneling of electrons from the valence band of channel to the conduction band of drain. As a result, barrier width at the drain/channel junction increases significantly leading to the suppression of an ambipolar current even when higher doping concentration (1 ? 10 ? cm ?) is considered in the drain region. However, significant improvement in terms of RF figure-of-merits such as cut-off frequency (f ?), gain bandwidth product (GBW), and gate-to-drain capacitance (C ?) is achieved with Gaussian doped gate on drain overlap TFET as compared to its counterpart TFET.

Understanding the Implications of a LINAC’s Microstructure on Devices and Photocurrent Models

DOE PAGES

McLain, Michael Lee; McDonald, Joseph Kyle; Hembree, Charles E.; ...

2017-10-20

Here, the effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO 2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effectsmore » are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.« less

Understanding the Implications of a LINAC’s Microstructure on Devices and Photocurrent Models

DOE Office of Scientific and Technical Information (OSTI.GOV)

McLain, Michael Lee; McDonald, Joseph Kyle; Hembree, Charles E.

Here, the effect of a linear accelerator’s (LINAC’s) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO 2, and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effectsmore » are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.« less

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

PubMed

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

Theoretical evaluation of maximum electric field approximation of direct band-to-band tunneling Kane model for low bandgap semiconductors

NASA Astrophysics Data System (ADS)

Dang Chien, Nguyen; Shih, Chun-Hsing; Hoa, Phu Chi; Minh, Nguyen Hong; Thi Thanh Hien, Duong; Nhung, Le Hong

2016-06-01

The two-band Kane model has been popularly used to calculate the band-to-band tunneling (BTBT) current in tunnel field-effect transistor (TFET) which is currently considered as a promising candidate for low power applications. This study theoretically clarifies the maximum electric field approximation (MEFA) of direct BTBT Kane model and evaluates its appropriateness for low bandgap semiconductors. By analysing the physical origin of each electric field term in the Kane model, it has been elucidated in the MEFA that the local electric field term must be remained while the nonlocal electric field terms are assigned by the maximum value of electric field at the tunnel junction. Mathematical investigations have showed that the MEFA is more appropriate for low bandgap semiconductors compared to high bandgap materials because of enhanced tunneling probability in low field regions. The appropriateness of the MEFA is very useful for practical uses in quickly estimating the direct BTBT current in low bandgap TFET devices.

Large Work Function Modulation of Monolayer MoS2 by Ambient Gases.

PubMed

Lee, Si Young; Kim, Un Jeong; Chung, JaeGwan; Nam, Honggi; Jeong, Hye Yun; Han, Gang Hee; Kim, Hyun; Oh, Hye Min; Lee, Hyangsook; Kim, Hyochul; Roh, Young-Geun; Kim, Jineun; Hwang, Sung Woo; Park, Yeonsang; Lee, Young Hee

2016-06-28

Although two-dimensional monolayer transition-metal dichalcogenides reveal numerous unique features that are inaccessible in bulk materials, their intrinsic properties are often obscured by environmental effects. Among them, work function, which is the energy required to extract an electron from a material to vacuum, is one critical parameter in electronic/optoelectronic devices. Here, we report a large work function modulation in MoS2 via ambient gases. The work function was measured by an in situ Kelvin probe technique and further confirmed by ultraviolet photoemission spectroscopy and theoretical calculations. A measured work function of 4.04 eV in vacuum was converted to 4.47 eV with O2 exposure, which is comparable with a large variation in graphene. The homojunction diode by partially passivating a transistor reveals an ideal junction with an ideality factor of almost one and perfect electrical reversibility. The estimated depletion width obtained from photocurrent mapping was ∼200 nm, which is much narrower than bulk semiconductors.

Effect of interfaces on electron transport properties of MoS2-Au Contacts

NASA Astrophysics Data System (ADS)

Aminpour, Maral; Hapala, Prokop; Le, Duy; Jelinek, Pavel; Rahman, Talat S.; Rahman's Group Collaboration; Nanosurf Lab Collaboration

2014-03-01

Single layer MoS2 is a promising material for future electronic devices such as transistors since it has good transport characteristics with mobility greater than 200 cm-1V-1s-1 and on-off current ratios up to 108. However, before MoS2 can become a mainstream electronic material for the semiconductor industry, the design of low resistive metal-semiconductor junctions as contacts of the electronic devices needs to be addressed and studied systematically. We have examined the effect of Au contacts on the electronic transport properties of single layer MoS2 using density functional theory in combination with the non-equilibrium Green's function method. The Schottky barrier between Au contact and MoS2, transmission spectra, and I-V curves will be reported and discussed as a function of MoS2 and Au interfaces of varying geometry. This work is supported in part by the US Department of Energy under grant DE-FG02-07ER15842.

All-carbon sp-sp2 hybrid structures: Geometrical properties, current rectification, and current amplification

PubMed Central

Zhang, Zhenhua; Zhang, Junjun; Kwong, Gordon; Li, Ji; Fan, Zhiqiang; Deng, Xiaoqing; Tang, Guiping

2013-01-01

All-carbon sp-sp2 hybrid structures comprised of a zigzag-edged trigonal graphene (ZTG)and carbon chains are proposed and constructed as nanojunctions. It has been found that such simple hybrid structures possess very intriguing propertiesapp:addword:intriguing. The high-performance rectifying behaviors similar to macroscopic p-n junction diodes, such as a nearly linear positive-bias I-V curve (metallic behavior), a very small leakage current under negative bias (insulating behavior), a rather low threshold voltage, and a large bias region contributed to a rectification, can be predicted. And also, a transistor can be built by such a hybrid structure, which can show an extremely high current amplification. This is because a sp-hybrid carbon chain has a special electronic structure which can limit the electronic resonant tunneling of the ZTG to a unique and favorable situation. These results suggest that these hybrid structures might promise importantly potential applications for developing nano-scale integrated circuits. PMID:23999318

Trends and techniques for space base electronics. [mathematical models, ion implantation, and semiconductors

NASA Technical Reports Server (NTRS)

Gassaway, J. D.; Mahmood, Q.; Trotter, J. D.

1978-01-01

A system was developed for depositing aluminum and aluminum alloys by the D.C. sputtering technique. This system which was designed for a high level of cleanliness and ion monitoring the deposition parameters during film preparation is ready for studying the deposition and annealing parameters upon double level metal preparation. The finite element method was studied for use in the computer modeling of two dimensional MOS transistor structures. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions typical of those used at MSFC. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients. Data are given showing both two dimensional effects and the evolution of the junction depth, sheet resistance and integrated dose with redistribution time.